]> git.sur5r.net Git - u-boot/commitdiff
mxc_i2c: clear i2sr before waiting for bit
authorTroy Kisky <troy.kisky@boundarydevices.com>
Thu, 19 Jul 2012 08:18:05 +0000 (08:18 +0000)
committerHeiko Schocher <hs@denx.de>
Tue, 31 Jul 2012 05:42:20 +0000 (07:42 +0200)
Let's clear the sr register before waiting for
bit to be set, instead of clearing it after
hardware sets it. No real operational difference here,
but allows combining of i2c_imx_trx_complete and
i2c_imx_bus_busy in later patches.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
drivers/i2c/mxc_i2c.c

index d147dd5f34516653eca086b008af1c22b367055f..57027ad4db5822349d8ea5e8741dde899c7050b9 100644 (file)
@@ -200,10 +200,8 @@ int i2c_imx_trx_complete(void)
        int timeout = I2C_MAX_TIMEOUT;
 
        while (timeout--) {
-               if (readb(&i2c_regs->i2sr) & I2SR_IIF) {
-                       writeb(0, &i2c_regs->i2sr);
+               if (readb(&i2c_regs->i2sr) & I2SR_IIF)
                        return 0;
-               }
 
                udelay(1);
        }
@@ -215,6 +213,7 @@ static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte)
 {
        int ret;
 
+       writeb(0, &i2c_regs->i2sr);
        writeb(byte, &i2c_regs->i2dr);
        ret = i2c_imx_trx_complete();
        if (ret < 0)
@@ -346,7 +345,8 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
        if (len == 1)
                temp |= I2CR_TX_NO_AK;
        writeb(temp, &i2c_regs->i2cr);
-       readb(&i2c_regs->i2dr);
+       writeb(0, &i2c_regs->i2sr);
+       readb(&i2c_regs->i2dr);         /* dummy read to clear ICF */
 
        /* read data */
        for (i = 0; i < len; i++) {
@@ -369,6 +369,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
                        writeb(temp, &i2c_regs->i2cr);
                }
 
+               writeb(0, &i2c_regs->i2sr);
                buf[i] = readb(&i2c_regs->i2dr);
        }