Changes since for U-Boot 0.1.0:
======================================================================
+* Added support for both PCMCIA slots (at the same time!) on MPC8xx
+
+* Patch by Rod Boyce, 21 Nov 2002:
+ fix PCMCIA on MBX8xx board
+
+* Patch by Pierre Aubert , 21 Nov 2002
+ Add CFG_CPM_POST_WORD_ADDR to make the offset of the
+ bootmode word in DPRAM configurable
+
* Patch by Daniel Engström, 18 Nov 2002:
Fixes for x86 port (mostly strings issues)
wrong setting might damage your board. Read
doc/README.MBX before setting this variable!
+- CFG_CPM_POST_WORD_ADDR: (MPC8xx, MPC8260 only)
+ Offset of the bootmode word in DPRAM used by post
+ (Power On Self Tests). This definition overrides
+ #define'd default value in commproc.h resp.
+ cpm_8260.h.
+
Building the Software:
======================
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
ulong result;
- int iflag, cflag, prot, sect;
+ int iflag, prot, sect;
int rc = ERR_OK;
int chip1, chip2;
minor |= ali512x_cio_in(20)?1:0;
printf("AMD SC520 CDP revision %d.%d\n", major, minor);
+
+ return 0;
}
static void print_funcid (int func);
static void print_fixed (volatile uchar *p);
static int identify (volatile uchar *p);
-static int check_ide_device (void);
+static int check_ide_device (int slot);
#endif /* CONFIG_IDE_8xx_PCCARD */
static u_int m8xx_get_graycode(u_int size);
int i;
u_long reg, base;
pcmcia_win_t *win;
+ u_int slotbit;
+ u_int rc, slot;
debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
return (1);
}
+ slotbit = PCMCIA_SLOT_x;
for (i=0; i<PCMCIA_MEM_WIN_NO; ++i) {
win->br = base;
+#if (PCMCIA_SOCKETS_NO == 2)
+ if (i == 4) /* Another slot starting from win 4 */
+ slotbit = (slotbit ? PCMCIA_PSLOT_A : PCMCIA_PSLOT_B);
+#endif
switch (i) {
#ifdef CONFIG_IDE_8xx_PCCARD
+ case 4:
case 0: { /* map attribute memory */
win->or = ( PCMCIA_BSIZE_64M
| PCMCIA_PPS_8
| PCMCIA_PRS_ATTR
- | PCMCIA_SLOT_x
+ | slotbit
| PCMCIA_PV
| CFG_PCMCIA_TIMING );
break;
}
-
+ case 5:
case 1: { /* map I/O window for data reg */
win->or = ( PCMCIA_BSIZE_1K
| PCMCIA_PPS_16
| PCMCIA_PRS_IO
- | PCMCIA_SLOT_x
+ | slotbit
| PCMCIA_PV
| CFG_PCMCIA_TIMING );
break;
}
-
+ case 6:
case 2: { /* map I/O window for command/ctrl reg block */
win->or = ( PCMCIA_BSIZE_1K
| PCMCIA_PPS_8
| PCMCIA_PRS_IO
- | PCMCIA_SLOT_x
+ | slotbit
| PCMCIA_PV
| CFG_PCMCIA_TIMING );
break;
++win;
}
- /* turn off voltage */
- if (voltage_set(_slot_, 0, 0))
- return (1);
-
- /* Enable external hardware */
- if (hardware_enable(_slot_))
- return (1);
-
+ for (i = 0, rc = 0, slot = _slot_; i < PCMCIA_SOCKETS_NO; i++, slot = !slot) {
+ /* turn off voltage */
+ if ((rc = voltage_set(slot, 0, 0)))
+ continue;
+
+ /* Enable external hardware */
+ if ((rc = hardware_enable(slot)))
+ continue;
+
#ifdef CONFIG_IDE_8xx_PCCARD
- if (check_ide_device())
- return (1);
+ if ((rc = check_ide_device(i)))
+ continue;
#endif
- return (0);
+ }
+ return (rc);
}
/* ------------------------------------------------------------------------- */
#define MAX_TUPEL_SZ 512
#define MAX_FEATURES 4
-static int check_ide_device (void)
+static int check_ide_device (int slot)
{
volatile uchar *ident = NULL;
volatile uchar *feature_p[MAX_FEATURES];
- volatile uchar *p, *start;
+ volatile uchar *p, *start, *addr;
int n_features = 0;
uchar func_id = ~0;
uchar code, len;
int found = 0;
int i;
- debug ("PCMCIA MEM: %08X\n", CFG_PCMCIA_MEM_ADDR);
+ addr = (volatile uchar *)(CFG_PCMCIA_MEM_ADDR +
+ CFG_PCMCIA_MEM_SIZE * (slot * 4));
+ debug ("PCMCIA MEM: %08X\n", addr);
- start = p = (volatile uchar *) CFG_PCMCIA_MEM_ADDR;
+ start = p = (volatile uchar *) addr;
while ((p - start) < MAX_TUPEL_SZ) {
}
/* set I/O area in config reg -> only valid for ARGOSY D5!!! */
- *((uchar *)(CFG_PCMCIA_MEM_ADDR + config_base)) = 1;
+ *((uchar *)(addr + config_base)) = 1;
return (0);
}
debug ("[%d] %s: PIPR(%p)=0x%x\n",
__LINE__,__FUNCTION__,
&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
- if (pcmp->pcmc_pipr & 0x00001800) {
+ if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
printf (" No Card found\n");
return (1);
}
debug ("[%d] %s: PIPR(%p)=0x%x\n",
__LINE__,__FUNCTION__,
&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
- if (pcmp->pcmc_pipr & 0x00001800) {
+ if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
printf (" No Card found\n");
return (1);
}
debug ("[%d] %s: PIPR(%p)=0x%x\n",
__LINE__,__FUNCTION__,
&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
- if (pcmp->pcmc_pipr & 0x00001800) {
+ if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
printf (" No Card found\n");
return (1);
}
debug ("[%d] %s: PIPR(%p)=0x%x\n",
__LINE__,__FUNCTION__,
&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
- if (pcmp->pcmc_pipr & 0x00001800) {
+ if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
printf (" No Card found\n");
return (1);
}
/*
* Make sure there is a card in the slot, then configure the interface.
*/
- udelay (10000);
- debug ("[%d] %s: PIPR(%p)=0x%x\n", __LINE__, __FUNCTION__,
- &(pcmp->pcmc_pipr), pcmp->pcmc_pipr);
-
- if (pcmp->pcmc_pipr & 0x00001800) {
+ udelay(10000);
+ debug ("[%d] %s: PIPR(%p)=0x%x\n",
+ __LINE__,__FUNCTION__,
+ &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
+ if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
printf (" No Card found\n");
return (1);
}
debug ("[%d] %s: PIPR(%p)=0x%x\n",
__LINE__,__FUNCTION__,
&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
- if (pcmp->pcmc_pipr & 0x00001800) {
+ if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
printf (" No Card found\n");
return (1);
}
sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
/* clear interrupt state, and disable interrupts */
- pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
- pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
+ pcmp->pcmc_pscr = PCMCIA_MASK(slot);
+ pcmp->pcmc_per &= ~PCMCIA_MASK(slot);
/* disable interrupts & DMA */
- PCMCIA_PGCRX(_slot_) = 0;
+ PCMCIA_PGCRX(slot) = 0;
/*
* Disable PCMCIA buffers (isolate the interface)
* and assert RESET signal
*/
debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
+ reg = PCMCIA_PGCRX(slot);
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
+ PCMCIA_PGCRX(slot) = reg;
+ udelay(2500);
/*
* Configure Port B pins for
* 3 Volts enable
*/
- cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3;
- cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3;
- /* remove all power */
- cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; /* active low */
-
+ if (slot) { /* Slot A is built-in */
+ cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3;
+ cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3;
+ /* remove all power */
+ cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; /* active low */
+ }
/*
* Make sure there is a card in the slot, then configure the interface.
*/
debug ("[%d] %s: PIPR(%p)=0x%x\n",
__LINE__,__FUNCTION__,
&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
- if (pcmp->pcmc_pipr & 0x00001800) {
+ if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
printf (" No Card found\n");
return (1);
}
/*
* Power On.
*/
+ printf("\n Slot %c:", 'A' + slot);
mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
reg = pcmp->pcmc_pipr;
debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
if ((reg & mask) == mask) {
puts (" 5.0V card found: NOT SUPPORTED !!!\n");
} else {
- cp->cp_pbdat &= ~KUP4K_PCMCIA_B_3V3;
+ if(slot)
+ cp->cp_pbdat &= ~KUP4K_PCMCIA_B_3V3;
puts (" 3.3V card found: ");
}
#if 0
udelay(500000);
#endif
debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
+ reg = PCMCIA_PGCRX(slot);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
+ PCMCIA_PGCRX(slot) = reg;
udelay(250000); /* some cards need >150 ms to come up :-( */
cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
/* remove all power */
- cp->cp_pbdat |= DDC4000_PCMCIA_B_3V3;
+ if (slot)
+ cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3;
/* Configure PCMCIA General Control Register */
- PCMCIA_PGCRX(_slot_) = 0;
+ PCMCIA_PGCRX(slot) = 0;
debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
+ reg = PCMCIA_PGCRX(slot);
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
+ PCMCIA_PGCRX(slot) = reg;
udelay(10000);
" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
+ if (!slot) /* Slot A is not configurable */
+ return 0;
+
immap = (immap_t *)CFG_IMMR;
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
* and assert RESET signal
*/
debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
+ reg = PCMCIA_PGCRX(slot);
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
+ PCMCIA_PGCRX(slot) = reg;
udelay(500);
debug ("PCMCIA power OFF\n");
puts("PCMCIA: vcc not supported");
break;
}
-
+ udelay(10000);
/* Checking supported voltages */
debug ("PIPR: 0x%x --> %s\n",
pcmp->pcmc_pipr,
- (pcmp->pcmc_pipr & 0x00008000)
+ (pcmp->pcmc_pipr & (0x80000000 >> (slot << 4)))
? "only 5 V --> NOT SUPPORTED"
: "can do 3.3V");
debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
+ reg = PCMCIA_PGCRX(slot);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
+ PCMCIA_PGCRX(slot) = reg;
udelay(500);
debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc)
BFD_ROOT_DIR = /usr/local/tools
else
+ifeq ($(HOSTARCH),$(ARCH))
+# native
+BFD_ROOT_DIR = /usr
+else
#BFD_ROOT_DIR = /LinuxPPC/CDK # Linux/i386
#BFD_ROOT_DIR = /usr/pkg/cross # NetBSD/i386
-#BFD_ROOT_DIR = /usr # native
BFD_ROOT_DIR = /opt/powerpc
endif
+endif
#########################################################################
#include <common.h>
#ifdef CONFIG_PCI
+#ifndef __I386__
#include <asm/processor.h>
#include <asm/io.h>
}
#endif
+#endif
/* Parameter RAM offsets from the base.
*/
+#ifndef CFG_CPM_POST_WORD_ADDR
#define CPM_POST_WORD_ADDR 0x80FC /* steal a long at the end of SCC1 */
+#else
+#define CPM_POST_WORD_ADDR CFG_CPM_POST_WORD_ADDR
+#endif
#define PROFF_SCC1 ((uint)0x8000)
#define PROFF_SCC2 ((uint)0x8100)
#define PROFF_SCC3 ((uint)0x8200)
#endif
+#ifndef CFG_CPM_POST_WORD_ADDR
#define CPM_POST_WORD_ADDR 0x07FC
+#else
+#define CPM_POST_WORD_ADDR CFG_CPM_POST_WORD_ADDR
+#endif
#define BD_IIC_START ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */
*
*/
-#define CONFIG_PCMCIA_SLOT_B 1 /* KUP4K use SLOT_B */
+/* KUP4K use both slots, SLOT_A as "primary". */
+#define CONFIG_PCMCIA_SLOT_A 1
#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
#define CFG_PCMCIA_IO_ADDR (0xEC000000)
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
+#define PCMCIA_SOCKETS_NO 2
+#define PCMCIA_MEM_WIN_NO 8
/*-----------------------------------------------------------------------
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
*-----------------------------------------------------------------------
#undef CONFIG_IDE_LED /* LED for ide not supported */
#undef CONFIG_IDE_RESET /* reset for ide not supported */
-#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
+#define CFG_IDE_MAXBUS 2
+#define CFG_IDE_MAXDEVICE 4
#define CFG_ATA_IDE0_OFFSET 0x0000
+#define CFG_ATA_IDE1_OFFSET (4 * CFG_PCMCIA_MEM_SIZE)
+
#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
/* Offset for data I/O */
#undef CONFIG_BOOTARGS
/* POST support */
-#define CONFIG_POST (CFG_POST_CACHE | \
+#define CONFIG_POST (CFG_POST_CACHE | \
CFG_POST_WATCHDOG | \
- CFG_POST_RTC | \
- CFG_POST_MEMORY | \
- CFG_POST_CPU | \
- CFG_POST_UART | \
- CFG_POST_ETHER | \
- CFG_POST_SPI | \
- CFG_POST_USB | \
+ CFG_POST_RTC | \
+ CFG_POST_MEMORY | \
+ CFG_POST_CPU | \
+ CFG_POST_UART | \
+ CFG_POST_ETHER | \
+ CFG_POST_I2C | \
+ CFG_POST_SPI | \
+ CFG_POST_USB | \
CFG_POST_SPR)
#define CONFIG_BOOTCOMMAND "run flash_self"
#undef CONFIG_STATUS_LED /* Status LED disabled */
/* enable I2C and select the hardware/software driver */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#undef CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
-#ifdef CONFIG_HARD_I2C
-/*
- * Hardware (CPM) I2C driver configuration
- */
-# define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
-# define CFG_I2C_SLAVE 0xFE
-#endif /* CONFIG_HARD_I2C */
+#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
+#define CFG_I2C_SLAVE 0xFE
#ifdef CONFIG_SOFT_I2C
/*
+++ /dev/null
-/*
- * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Andreas Heppel <aheppel@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * mpc75x.h
- *
- * MPC75x/MPC74xx specific definitions
- */
-
-#ifndef __MPC75X_H__
-#define __MPC75X_H__
-
-/*----------------------------------------------------------------
- * Exception offsets (PowerPC standard)
- */
-#define EXC_OFF_SYS_RESET 0x0100 /* default system reset offset */
-
-/*----------------------------------------------------------------
- * l2cr values
- */
-#define l2cr 1017
-
-#define L2CR_L2E 0x80000000 /* bit 0 - enable */
-#define L2CR_L2PE 0x40000000 /* bit 1 - data parity */
-#define L2CR_L2SIZ_2M 0x00000000 /* bits 2-3 - 2MB, MPC7400 only! */
-#define L2CR_L2SIZ_1M 0x30000000 /* ... 1MB */
-#define L2CR_L2SIZ_HM 0x20000000 /* ... 512K */
-#define L2CR_L2SIZ_QM 0x10000000 /* ... 256k */
-#define L2CR_L2CLK_1 0x02000000 /* bits 4-6 clock ratio div 1 */
-#define L2CR_L2CLK_1_5 0x04000000 /* bits 4-6 clock ratio div 1.5 */
-#define L2CR_L2CLK_2 0x08000000 /* bits 4-6 clock ratio div 2 */
-#define L2CR_L2CLK_2_5 0x0a000000 /* bits 4-6 clock ratio div 2.5 */
-#define L2CR_L2CLK_3 0x0c000000 /* bits 4-6 clock ratio div 3 */
-#define L2CR_L2CLK_3_5 0x06000000 /* bits 4-6 clock ratio div 3.5 */
-#define L2CR_L2CLK_4 0x0e000000 /* bits 4-6 clock ratio div 4 */
-#define L2CR_L2RAM_BURST 0x01000000 /* bits 7-8 - burst SRAM */
-#define L2CR_DO 0x00400000 /* bit 9 - enable caching of instr. in L2 */
-#define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */
-#define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */
-#define L2CR_L2WT 0x00080000 /* bit 12 - l2 write-through */
-#define L2CR_TS 0x00040000 /* bit 13 - test support on */
-#define L2CR_TS_OFF -L2CR_TS /* bit 13 - test support off */
-#define L2CR_L2OH_5 0x00000000 /* bits 14-15 - output hold time = short */
-#define L2CR_L2OH_1 0x00010000 /* bits 14-15 - output hold time = medium */
-#define L2CR_L2OH_INV 0x00020000 /* bits 14-15 - output hold time = long */
-#define L2CR_L2IP 0x00000001 /* global invalidate in progress */
-
-/*----------------------------------------------------------------
- * BAT settings. Look in config_<BOARD>.h for the actual setup
- */
-
-#define BATU_BL_128K 0x00000000
-#define BATU_BL_256K 0x00000004
-#define BATU_BL_512K 0x0000000c
-#define BATU_BL_1M 0x0000001c
-#define BATU_BL_2M 0x0000003c
-#define BATU_BL_4M 0x0000007c
-#define BATU_BL_8M 0x000000fc
-#define BATU_BL_16M 0x000001fc
-#define BATU_BL_32M 0x000003fc
-#define BATU_BL_64M 0x000007fc
-#define BATU_BL_128M 0x00000ffc
-#define BATU_BL_256M 0x00001ffc
-
-#define BATU_VS 0x00000002
-#define BATU_VP 0x00000001
-#define BATU_INVALID 0x00000000
-
-#define BATL_WRITETHROUGH 0x00000080
-#define BATL_CACHEINHIBIT 0x00000040
-#define BATL_COHERENT 0x00000020
-#define BATL_GUARDED 0x00000010
-
-#define BATL_NO_ACCESS 0x00000000
-#define BATL_RO 0x00000001
-#define BATL_RW 0x00000002
-
-#endif /* __MPC75X_H__ */
#error Both CONFIG_PCMCIA_SLOT_A and CONFIG_PCMCIA_SLOT_B configured
#endif
+#ifndef PCMCIA_SOCKETS_NO
#define PCMCIA_SOCKETS_NO 1
+#endif
+#ifndef PCMCIA_MEM_WIN_NO
#define PCMCIA_MEM_WIN_NO 4
+#endif
#define PCMCIA_IO_WIN_NO 2
/* define _slot_ to be able to optimize macros */
void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
ulong addr, ulong *len_ptr, int verify)
{
- ulong base_ptr;
+ void *base_ptr;
ulong len = 0, checksum;
ulong initrd_start, initrd_end;
initrd_end = 0;
}
- base_ptr = load_zimage(addr + sizeof(image_header_t), ntohl(hdr->ih_size),
+ base_ptr = load_zimage((void*)addr + sizeof(image_header_t), ntohl(hdr->ih_size),
initrd_start, initrd_end-initrd_start, 0);
if (NULL == base_ptr) {
#include <asm/io.h>
#include <pci.h>
-#define cfg_read(val, addr, type, op) *val = op((type)(addr))
-#define cfg_write(val, addr, type, op) op((val), (type *)(addr))
+#define cfg_read(val, addr, op) *val = op((int)(addr))
+#define cfg_write(val, addr, op) op((val), (int)(addr))
#define TYPE1_PCI_OP(rw, size, type, op, mask) \
static int \
type1_##rw##_config_##size(struct pci_controller *hose, \
pci_dev_t dev, int offset, type val) \
{ \
- outl(dev | (offset & 0xfc) | 0x80000000, hose->cfg_addr); \
- cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
+ outl(dev | (offset & 0xfc) | 0x80000000, (int)hose->cfg_addr); \
+ cfg_##rw(val, hose->cfg_data + (offset & mask), op); \
return 0; \
}
#include <common.h>
#include <asm/io.h>
#include <asm/ptrace.h>
+#include <asm/realmode.h>
#define REALMODE_BASE ((char*)0x7c0)
/* copy the realmode switch code */
if (i386boot_realmode_size > (REALMODE_MAILBOX-REALMODE_BASE)) {
printf("realmode switch too large (%ld bytes, max is %d)\n",
- i386boot_realmode_size, (REALMODE_MAILBOX-REALMODE_BASE));
+ i386boot_realmode_size, (int)(REALMODE_MAILBOX-REALMODE_BASE));
return -1;
}
- memcpy(REALMODE_BASE, i386boot_realmode, i386boot_realmode_size);
+ memcpy(REALMODE_BASE, (void*)i386boot_realmode, i386boot_realmode_size);
in->eip = off;
in->xcs = seg;
- if (3>in->esp & 0xffff) {
+ if (3>(in->esp & 0xffff)) {
printf("Warning: entering realmode with sp < 4 will fail\n");
}
int ic = icache_status ();
int ret = 0;
+ WATCHDOG_RESET();
if (ic)
icache_disable ();
ret = cpu_post_test_two ();
if (ret == 0)
ret = cpu_post_test_twox ();
+ WATCHDOG_RESET();
if (ret == 0)
ret = cpu_post_test_three ();
if (ret == 0)
ret = cpu_post_test_threex ();
if (ret == 0)
ret = cpu_post_test_threei ();
- WATCHDOG_RESET();
if (ret == 0)
ret = cpu_post_test_andi ();
+ WATCHDOG_RESET();
if (ret == 0)
ret = cpu_post_test_srawi ();
if (ret == 0)
ret = cpu_post_test_rlwinm ();
if (ret == 0)
ret = cpu_post_test_rlwimi ();
+ WATCHDOG_RESET();
if (ret == 0)
ret = cpu_post_test_store ();
if (ret == 0)
ret = cpu_post_test_load ();
- WATCHDOG_RESET();
if (ret == 0)
ret = cpu_post_test_cr ();
if (ret == 0)
ret = cpu_post_test_b ();
+ WATCHDOG_RESET();
if (ret == 0)
ret = cpu_post_test_multi ();
if (ret == 0)
ret = cpu_post_test_string ();
if (ret == 0)
ret = cpu_post_test_complex ();
+ WATCHDOG_RESET();
if (ic)
icache_enable ();
+ WATCHDOG_RESET();
+
return ret;
}
(flags & test_flags[last] & POST_ALWAYS) &&
(flags & test_flags[last] & POST_MEM)) {
- post_run_single (post_list + last, test_flags[last],
- flags | POST_REBOOT, last);
+ post_run_single (post_list + last,
+ test_flags[last],
+ flags | POST_REBOOT, last);
for (i = last + 1; i < post_list_size; i++) {
- post_run_single (post_list + i, test_flags[i],
- flags, i);
+ post_run_single (post_list + i,
+ test_flags[i],
+ flags, i);
}
}
} else {
for (i = 0; i < post_list_size; i++) {
- post_run_single (post_list + i, test_flags[i], flags,
- i);
+ post_run_single (post_list + i,
+ test_flags[i],
+ flags, i);
}
}
projects / u-boot / commitdiff