arm: am57xx: Fix alignment where necessary

This just fixes alignment for better readability.

Signed-off-by: Keerthy <j-keerthy@ti.com>

diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index f533b1a4d001f1ac079bf4b39952303368b8a831..ccf97b2b13bb4ab11002a6490d9210c125b0011d 100644 (file)
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -63,28 +63,28 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 }
 
 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
-       .sdram_config_init      = 0x61851b32,
-       .sdram_config           = 0x61851b32,
-       .sdram_config2          = 0x08000000,
-       .ref_ctrl               = 0x000040F1,
-       .ref_ctrl_final         = 0x00001035,
-       .sdram_tim1             = 0xcccf36ab,
-       .sdram_tim2             = 0x308f7fda,
-       .sdram_tim3             = 0x409f88a8,
-       .read_idle_ctrl         = 0x00050000,
-       .zq_config              = 0x5007190b,
-       .temp_alert_config      = 0x00000000,
-       .emif_ddr_phy_ctlr_1_init = 0x0024400b,
-       .emif_ddr_phy_ctlr_1    = 0x0e24400b,
-       .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
-       .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
-       .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
-       .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
-       .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
-       .emif_rd_wr_lvl_rmp_win = 0x00000000,
-       .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
-       .emif_rd_wr_lvl_ctl     = 0x00000000,
-       .emif_rd_wr_exec_thresh = 0x00000305
+       .sdram_config_init              = 0x61851b32,
+       .sdram_config                   = 0x61851b32,
+       .sdram_config2                  = 0x08000000,
+       .ref_ctrl                       = 0x000040F1,
+       .ref_ctrl_final                 = 0x00001035,
+       .sdram_tim1                     = 0xcccf36ab,
+       .sdram_tim2                     = 0x308f7fda,
+       .sdram_tim3                     = 0x409f88a8,
+       .read_idle_ctrl                 = 0x00050000,
+       .zq_config                      = 0x5007190b,
+       .temp_alert_config              = 0x00000000,
+       .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
+       .emif_ddr_phy_ctlr_1            = 0x0e24400b,
+       .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
+       .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
+       .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
+       .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
+       .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
+       .emif_rd_wr_lvl_rmp_win         = 0x00000000,
+       .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
+       .emif_rd_wr_lvl_ctl             = 0x00000000,
+       .emif_rd_wr_exec_thresh         = 0x00000305
 };
 
 /* Ext phy ctrl regs 1-35 */
@@ -127,28 +127,28 @@ static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
 };
 
 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
-       .sdram_config_init      = 0x61851b32,
-       .sdram_config           = 0x61851b32,
-       .sdram_config2          = 0x08000000,
-       .ref_ctrl               = 0x000040F1,
-       .ref_ctrl_final         = 0x00001035,
-       .sdram_tim1             = 0xcccf36b3,
-       .sdram_tim2             = 0x308f7fda,
-       .sdram_tim3             = 0x407f88a8,
-       .read_idle_ctrl         = 0x00050000,
-       .zq_config              = 0x5007190b,
-       .temp_alert_config      = 0x00000000,
-       .emif_ddr_phy_ctlr_1_init = 0x0024400b,
-       .emif_ddr_phy_ctlr_1    = 0x0e24400b,
-       .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
-       .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
-       .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
-       .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
-       .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
-       .emif_rd_wr_lvl_rmp_win = 0x00000000,
-       .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
-       .emif_rd_wr_lvl_ctl     = 0x00000000,
-       .emif_rd_wr_exec_thresh = 0x00000305
+       .sdram_config_init              = 0x61851b32,
+       .sdram_config                   = 0x61851b32,
+       .sdram_config2                  = 0x08000000,
+       .ref_ctrl                       = 0x000040F1,
+       .ref_ctrl_final                 = 0x00001035,
+       .sdram_tim1                     = 0xcccf36b3,
+       .sdram_tim2                     = 0x308f7fda,
+       .sdram_tim3                     = 0x407f88a8,
+       .read_idle_ctrl                 = 0x00050000,
+       .zq_config                      = 0x5007190b,
+       .temp_alert_config              = 0x00000000,
+       .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
+       .emif_ddr_phy_ctlr_1            = 0x0e24400b,
+       .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
+       .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
+       .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
+       .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
+       .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
+       .emif_rd_wr_lvl_rmp_win         = 0x00000000,
+       .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
+       .emif_rd_wr_lvl_ctl             = 0x00000000,
+       .emif_rd_wr_exec_thresh         = 0x00000305
 };
 
 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
@@ -221,7 +221,7 @@ struct vcores_data beagle_x15_volts = {
        .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
        .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
        .mpu.pmic               = &tps659038,
-       .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
+       .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 
        .eve.value              = VDD_EVE_DRA7,
        .eve.efuse.reg          = STD_FUSE_OPP_VMIN_DSPEVE,