sunxi: add LPDDR3 timing from stock boot0

As we added LPDDR3 support in the former patch, we need a set of timing
info to really enable it.

Add the timing info used by stock boot0.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 2761915638439773c04b1875cf4a9cc80daa93b0..bd3e7d3b3f20a315be98f91a6bf2f41ede989aa6 100644 (file)
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -242,6 +242,13 @@ config SUNXI_DRAM_DDR3_1333
        This option is the original only supported memory type, which suits
        many H3/H5/A64 boards available now.
 
+config SUNXI_DRAM_LPDDR3_STOCK
+       bool "LPDDR3 with Allwinner stock configuration"
+       select SUNXI_DRAM_LPDDR3
+       ---help---
+       This option is the LPDDR3 timing used by the stock boot0 by
+       Allwinner.
+
 config SUNXI_DRAM_DDR2_V3S
        bool "DDR2 found in V3s chip"
        select SUNXI_DRAM_DDR2

diff --git a/arch/arm/mach-sunxi/dram_timings/Makefile b/arch/arm/mach-sunxi/dram_timings/Makefile
index a4c9dc556c7b9259beb54a42efc8c2cee2b613a0..278a8a14cc2ff1d0d1d4131564ebcea96d79ef36 100644 (file)
--- a/arch/arm/mach-sunxi/dram_timings/Makefile
+++ b/arch/arm/mach-sunxi/dram_timings/Makefile
@@ -1,2 +1,3 @@
 obj-$(CONFIG_SUNXI_DRAM_DDR3_1333)     += ddr3_1333.o
+obj-$(CONFIG_SUNXI_DRAM_LPDDR3_STOCK)  += lpddr3_stock.o
 obj-$(CONFIG_SUNXI_DRAM_DDR2_V3S)      += ddr2_v3s.o

diff --git a/arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c b/arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c
new file mode 100644 (file)
index 0000000..bd57e2f
--- /dev/null
+++ b/arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c
@@ -0,0 +1,83 @@
+#include <common.h>
+#include <asm/arch/dram.h>
+#include <asm/arch/cpu.h>
+
+void mctl_set_timing_params(uint16_t socid, struct dram_para *para)
+{
+       struct sunxi_mctl_ctl_reg * const mctl_ctl =
+                       (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+       u8 tccd         = 2;
+       u8 tfaw         = max(ns_to_t(50), 4);
+       u8 trrd         = max(ns_to_t(10), 2);
+       u8 trcd         = max(ns_to_t(24), 2);
+       u8 trc          = ns_to_t(70);
+       u8 txp          = max(ns_to_t(8), 2);
+       u8 twtr         = max(ns_to_t(8), 2);
+       u8 trtp         = max(ns_to_t(8), 2);
+       u8 twr          = max(ns_to_t(15), 3);
+       u8 trp          = max(ns_to_t(27), 2);
+       u8 tras         = ns_to_t(42);
+       u16 trefi       = ns_to_t(3900) / 32;
+       u16 trfc        = ns_to_t(210);
+
+       u8 tmrw         = 5;
+       u8 tmrd         = 5;
+       u8 tmod         = 12;
+       u8 tcke         = 3;
+       u8 tcksrx       = 5;
+       u8 tcksre       = 5;
+       u8 tckesr       = 5;
+       u8 trasmax      = 24;
+
+       u8 tcl          = 6; /* CL 12 */
+       u8 tcwl         = 3; /* CWL 6 */
+       u8 t_rdata_en   = 5;
+       u8 wr_latency   = 2;
+
+       u32 tdinit0     = (200 * CONFIG_DRAM_CLK) + 1;          /* 200us */
+       u32 tdinit1     = (100 * CONFIG_DRAM_CLK) / 1000 + 1;   /* 100ns */
+       u32 tdinit2     = (11 * CONFIG_DRAM_CLK) + 1;           /* 11us */
+       u32 tdinit3     = (1 * CONFIG_DRAM_CLK) + 1;            /* 1us */
+
+       u8 twtp         = tcwl + 4 + twr + 1;
+       u8 twr2rd       = tcwl + 4 + 1 + twtr;
+       u8 trd2wr       = tcl + 4 + 5 - tcwl + 1;
+
+       /* set mode register */
+       writel(0xc3, &mctl_ctl->mr[1]);         /* nWR=8, BL8 */
+       writel(0xa, &mctl_ctl->mr[2]);          /* RL=12, WL=6 */
+       writel(0x2, &mctl_ctl->mr[3]);          /* 40 0hms PD/PU */
+
+       /* set DRAM timing */
+       writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) |
+              DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras),
+              &mctl_ctl->dramtmg[0]);
+       writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc),
+              &mctl_ctl->dramtmg[1]);
+       writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) |
+              DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd),
+              &mctl_ctl->dramtmg[2]);
+       writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod),
+              &mctl_ctl->dramtmg[3]);
+       writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) |
+              DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]);
+       writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) |
+              DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke),
+              &mctl_ctl->dramtmg[5]);
+
+       /* set two rank timing */
+       clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
+                       (0x66 << 8) | (0x10 << 0));
+
+       /* set PHY interface timing, write latency and read latency configure */
+       writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
+              (wr_latency << 0), &mctl_ctl->pitmg[0]);
+
+       /* set PHY timing, PTR0-2 use default */
+       writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]);
+       writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]);
+
+       /* set refresh timing */
+       writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg);
+}