]> git.sur5r.net Git - u-boot/commitdiff
armv8: ls1043a: add PCIe dts node
authorMinghuan Lian <Minghuan.Lian@nxp.com>
Tue, 13 Dec 2016 06:54:13 +0000 (14:54 +0800)
committerYork Sun <york.sun@nxp.com>
Wed, 18 Jan 2017 17:25:43 +0000 (09:25 -0800)
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
arch/arm/dts/fsl-ls1043a.dtsi

index f038f96171e15ecc42685474ea71eb84324fafc9..fe6698f1612cc215c6fab72bb350b878ce2268fb 100644 (file)
                        interrupts = <0 63 0x4>;
                        dr_mode = "host";
                };
+
+               pcie@3400000 {
+                       compatible = "fsl,ls-pcie", "snps,dw-pcie";
+                       reg = <0x00 0x03400000 0x0 0x10000   /* dbi registers */
+                              0x00 0x03410000 0x0 0x10000   /* lut registers */
+                              0x40 0x00000000 0x0 0x20000>; /* configuration space */
+                       reg-names = "dbi", "lut", "config";
+                       big-endian;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       device_type = "pci";
+                       bus-range = <0x0 0xff>;
+                       ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000   /* downstream I/O */
+                                 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+               };
+
+               pcie@3500000 {
+                       compatible = "fsl,ls-pcie", "snps,dw-pcie";
+                       reg = <0x00 0x03500000 0x0 0x10000   /* dbi registers */
+                              0x00 0x03510000 0x0 0x10000   /* lut registers */
+                              0x48 0x00000000 0x0 0x20000>; /* configuration space */
+                       reg-names = "dbi", "lut", "config";
+                       big-endian;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       device_type = "pci";
+                       num-lanes = <2>;
+                       bus-range = <0x0 0xff>;
+                       ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000   /* downstream I/O */
+                                 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+               };
+
+               pcie@3600000 {
+                       compatible = "fsl,ls-pcie", "snps,dw-pcie";
+                       reg = <0x00 0x03600000 0x0 0x10000   /* dbi registers */
+                              0x00 0x03610000 0x0 0x10000   /* lut registers */
+                              0x50 0x00000000 0x0 0x20000>; /* configuration space */
+                       reg-names = "dbi", "lut", "config";
+                       big-endian;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       device_type = "pci";
+                       bus-range = <0x0 0xff>;
+                       ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000   /* downstream I/O */
+                                 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+               };
        };
 };