]> git.sur5r.net Git - u-boot/commitdiff
usb: ehci: rmobile: Add support ehci host driver of rmobile SoCs
authorNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Thu, 3 Apr 2014 04:55:54 +0000 (13:55 +0900)
committerMarek Vasut <marex@denx.de>
Wed, 30 Apr 2014 08:30:56 +0000 (10:30 +0200)
The rmobile SoC has usb host controller.
This supports USB controllers listed in the R8A7790, R8A7791 and R8A7740.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Reviewed-by: Marek Vasut <marex@denx.de>
arch/arm/include/asm/arch-rmobile/ehci-rmobile.h [new file with mode: 0644]
drivers/usb/host/Makefile
drivers/usb/host/ehci-rmobile.c [new file with mode: 0644]

diff --git a/arch/arm/include/asm/arch-rmobile/ehci-rmobile.h b/arch/arm/include/asm/arch-rmobile/ehci-rmobile.h
new file mode 100644 (file)
index 0000000..463654e
--- /dev/null
@@ -0,0 +1,147 @@
+/*
+ *  Copyright (C) 2013,2014 Renesas Electronics Corporation
+ *  Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ *
+ *  SPDX-License-Identifier:     GPL-2.0
+ */
+
+#ifndef __EHCI_RMOBILE_H__
+#define __EHCI_RMOBILE_H__
+
+/* Register offset */
+#define OHCI_OFFSET    0x00
+#define OHCI_SIZE      0x1000
+#define EHCI_OFFSET    0x1000
+#define EHCI_SIZE      0x1000
+
+#define EHCI_USBCMD    (EHCI_OFFSET + 0x0020)
+
+/* USBCTR */
+#define DIRPD          (1 << 8)
+#define PLL_RST                (1 << 2)
+#define PCICLK_MASK    (1 << 1)
+#define USBH_RST       (1 << 0)
+
+/* CMND_STS */
+#define SERREN         (1 << 8)
+#define PERREN         (1 << 6)
+#define MASTEREN       (1 << 2)
+#define MEMEN          (1 << 1)
+
+/* PCIAHB_WIN1_CTR and PCIAHB_WIN2_CTR */
+#define PCIAHB_WIN_PREFETCH    ((1 << 1)|(1 << 0))
+
+/* AHBPCI_WIN1_CTR */
+#define PCIWIN1_PCICMD         ((1 << 3)|(1 << 1))
+#define AHB_CFG_AHBPCI         0x40000000
+#define AHB_CFG_HOST           0x80000000
+
+/* AHBPCI_WIN2_CTR */
+#define PCIWIN2_PCICMD         ((1 << 2)|(1 << 1))
+
+/* PCI_INT_ENABLE */
+#define USBH_PMEEN             (1 << 19)
+#define USBH_INTBEN            (1 << 17)
+#define USBH_INTAEN            (1 << 16)
+
+/* AHB_BUS_CTR */
+#define SMODE_READY_CTR                (1 << 17)
+#define SMODE_READ_BURST       (1 << 16)
+#define MMODE_HBUSREQ          (1 << 7)
+#define MMODE_BOUNDARY         ((1 << 6)|(1 << 5))
+#define MMODE_BURST_WIDTH      ((1 << 4)|(1 << 3))
+#define MMODE_SINGLE_MODE      ((1 << 4)|(1 << 3))
+#define MMODE_WR_INCR          (1 << 2)
+#define MMODE_BYTE_BURST       (1 << 1)
+#define MMODE_HTRANS           (1 << 0)
+
+/* PCI_ARBITER_CTR */
+#define PCIBUS_PARK_TIMER       0x00FF0000
+#define PCIBUS_PARK_TIMER_SET   0x00070000
+#define PCIBP_MODE             (1 << 12)
+#define PCIREQ7                 (1 << 7)
+#define PCIREQ6                 (1 << 6)
+#define PCIREQ5                 (1 << 5)
+#define PCIREQ4                 (1 << 4)
+#define PCIREQ3                 (1 << 3)
+#define PCIREQ2                 (1 << 2)
+#define PCIREQ1                 (1 << 1)
+#define PCIREQ0                 (1 << 0)
+
+#define SMSTPCR7        0xE615014C
+#define SMSTPCR703      (1 << 3)
+
+/* Init AHB master and slave functions of the host logic */
+#define AHB_BUS_CTR_INIT \
+       (SMODE_READY_CTR | MMODE_HBUSREQ | MMODE_WR_INCR | \
+        MMODE_BYTE_BURST | MMODE_HTRANS)
+
+#define USBCTR_WIN_SIZE_1GB    0x800
+
+/* PCI Configuration Registers */
+#define PCI_CONF_OHCI_OFFSET   0x10000
+#define PCI_CONF_EHCI_OFFSET   0x10100
+struct ahb_pciconf {
+       u32 vid_did;
+       u32 cmnd_sts;
+       u32 rev;
+       u32 cache_line;
+       u32 basead;
+};
+
+/* PCI Configuration Registers for AHB-PCI Bridge Registers */
+#define PCI_CONF_AHBPCI_OFFSET 0x10000
+struct ahbconf_pci_bridge {
+       u32 vid_did;            /* 0x00 */
+       u32 cmnd_sts;
+       u32 revid_cc;
+       u32 cls_lt_ht_bist;
+       u32 basead;             /* 0x10 */
+       u32 win1_basead;
+       u32 win2_basead;
+       u32 dummy0[5];
+       u32 ssvdi_ssid;         /* 0x2C */
+       u32 dummy1[4];
+       u32 intr_line_pin;
+};
+
+/* AHB-PCI Bridge PCI Communication Registers */
+#define AHBPCI_OFFSET  0x10800
+struct ahbcom_pci_bridge {
+       u32 pciahb_win1_ctr;    /* 0x00 */
+       u32 pciahb_win2_ctr;
+       u32 pciahb_dct_ctr;
+       u32 dummy0;
+       u32 ahbpci_win1_ctr;    /* 0x10 */
+       u32 ahbpci_win2_ctr;
+       u32 dummy1;
+       u32 ahbpci_dct_ctr;
+       u32 pci_int_enable;     /* 0x20 */
+       u32 pci_int_status;
+       u32 dummy2[2];
+       u32 ahb_bus_ctr;        /* 0x30 */
+       u32 usbctr;
+       u32 dummy3[2];
+       u32 pci_arbiter_ctr;    /* 0x40 */
+       u32 dummy4;
+       u32 pci_unit_rev;       /* 0x48 */
+};
+
+struct rmobile_ehci_reg {
+       u32 hciversion;         /* hciversion/caplength */
+       u32 hcsparams;          /* hcsparams */
+       u32 hccparams;          /* hccparams */
+       u32 hcsp_portroute;     /* hcsp_portroute */
+       u32 usbcmd;             /* usbcmd */
+       u32 usbsts;             /* usbsts */
+       u32 usbintr;            /* usbintr */
+       u32 frindex;            /* frindex */
+       u32 ctrldssegment;      /* ctrldssegment */
+       u32 periodiclistbase;   /* periodiclistbase */
+       u32 asynclistaddr;      /* asynclistaddr */
+       u32 dummy[9];
+       u32 configflag;         /* configflag */
+       u32 portsc;             /* portsc */
+};
+
+#endif /* __EHCI_RMOBILE_H__ */
index 578b097fc9591cfc9f813422dcb9ae223604b608..b301e28252bc31c34e6f7fcd0df95a6127fcd427 100644 (file)
@@ -36,6 +36,7 @@ obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
 obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o
 obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
 obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
+obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
 
 # xhci
 obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
diff --git a/drivers/usb/host/ehci-rmobile.c b/drivers/usb/host/ehci-rmobile.c
new file mode 100644 (file)
index 0000000..049e4c4
--- /dev/null
@@ -0,0 +1,130 @@
+/*
+ *  EHCI HCD (Host Controller Driver) for USB.
+ *
+ *  Copyright (C) 2013,2014 Renesas Electronics Corporation
+ *  Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ *
+ *  SPDX-License-Identifier:     GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ehci-rmobile.h>
+#include "ehci.h"
+
+#if defined(CONFIG_R8A7740)
+static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = {
+       0xC6700000
+};
+#elif defined(CONFIG_R8A7790)
+static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = {
+       0xEE080000,     /* USB0 (EHCI) */
+       0xEE0A0000,     /* USB1 */
+       0xEE0C0000,     /* USB2 */
+       0xEE000000      /* USB3 (USB3.0 Host)*/
+};
+#elif defined(CONFIG_R8A7791)
+static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = {
+       0xEE080000,     /* USB0 (EHCI) */
+       0xEE0C0000,     /* USB1 */
+       0xEE000000      /* USB3 (USB3.0 Host)*/
+};
+#else
+#error rmobile EHCI USB driver not supported on this platform
+#endif
+
+int ehci_hcd_stop(int index)
+{
+       int i;
+       u32 base;
+       struct ahbcom_pci_bridge *ahbcom_pci;
+
+       base = usb_base_address[index];
+       ahbcom_pci = (struct ahbcom_pci_bridge *)(base + AHBPCI_OFFSET);
+       writel(0, &ahbcom_pci->ahb_bus_ctr);
+
+       /* reset ehci */
+       setbits_le32(base + EHCI_USBCMD, CMD_RESET);
+       for (i = 100; i > 0; i--) {
+               if (!(readl(base + EHCI_USBCMD) & CMD_RESET))
+                       break;
+               udelay(100);
+       }
+
+       if (!i)
+               printf("error : ehci(%d) reset failed.\n", index);
+
+       if (index == (CONFIG_USB_MAX_CONTROLLER_COUNT - 1))
+               setbits_le32(SMSTPCR7, SMSTPCR703);
+
+       return 0;
+}
+
+int ehci_hcd_init(int index, enum usb_init_type init,
+       struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+       u32 base;
+       u32 phys_base;
+       struct rmobile_ehci_reg *rehci;
+       struct ahbcom_pci_bridge *ahbcom_pci;
+       struct ahbconf_pci_bridge *ahbconf_pci;
+       struct ahb_pciconf *ahb_pciconf_ohci;
+       struct ahb_pciconf *ahb_pciconf_ehci;
+       uint32_t cap_base;
+
+       base = usb_base_address[index];
+       phys_base = base;
+       if (index == 0)
+               clrbits_le32(SMSTPCR7, SMSTPCR703);
+
+       rehci = (struct rmobile_ehci_reg *)(base + EHCI_OFFSET);
+       ahbcom_pci = (struct ahbcom_pci_bridge *)(base + AHBPCI_OFFSET);
+       ahbconf_pci =
+               (struct ahbconf_pci_bridge *)(base + PCI_CONF_AHBPCI_OFFSET);
+       ahb_pciconf_ohci = (struct ahb_pciconf *)(base + PCI_CONF_OHCI_OFFSET);
+       ahb_pciconf_ehci = (struct ahb_pciconf *)(base + PCI_CONF_EHCI_OFFSET);
+
+       /* Clock & Reset & Direct Power Down */
+       clrsetbits_le32(&ahbcom_pci->usbctr,
+                       (DIRPD | PCICLK_MASK | USBH_RST), USBCTR_WIN_SIZE_1GB);
+       clrbits_le32(&ahbcom_pci->usbctr, PLL_RST);
+
+       /* AHB-PCI Bridge Communication Registers */
+       writel(AHB_BUS_CTR_INIT, &ahbcom_pci->ahb_bus_ctr);
+       writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | PCIAHB_WIN_PREFETCH,
+              &ahbcom_pci->pciahb_win1_ctr);
+       writel(0xf0000000 | PCIAHB_WIN_PREFETCH,
+              &ahbcom_pci->pciahb_win2_ctr);
+       writel(phys_base | PCIWIN2_PCICMD, &ahbcom_pci->ahbpci_win2_ctr);
+
+       setbits_le32(&ahbcom_pci->pci_arbiter_ctr,
+                    PCIBP_MODE | PCIREQ1 | PCIREQ0);
+
+       /* PCI Configuration Registers for AHBPCI */
+       writel(PCIWIN1_PCICMD | AHB_CFG_AHBPCI,
+              &ahbcom_pci->ahbpci_win1_ctr);
+       writel(phys_base + AHBPCI_OFFSET, &ahbconf_pci->basead);
+       writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, &ahbconf_pci->win1_basead);
+       writel(0xf0000000, &ahbconf_pci->win2_basead);
+       writel(SERREN | PERREN | MASTEREN | MEMEN,
+              &ahbconf_pci->cmnd_sts);
+
+       /* PCI Configuration Registers for EHCI */
+       writel(PCIWIN1_PCICMD | AHB_CFG_HOST, &ahbcom_pci->ahbpci_win1_ctr);
+       writel(phys_base + OHCI_OFFSET, &ahb_pciconf_ohci->basead);
+       writel(phys_base + EHCI_OFFSET, &ahb_pciconf_ehci->basead);
+       writel(SERREN | PERREN | MASTEREN | MEMEN,
+              &ahb_pciconf_ohci->cmnd_sts);
+       writel(SERREN | PERREN | MASTEREN | MEMEN,
+              &ahb_pciconf_ehci->cmnd_sts);
+
+       /* Enable PCI interrupt */
+       setbits_le32(&ahbcom_pci->pci_int_enable,
+                    USBH_PMEEN | USBH_INTBEN | USBH_INTAEN);
+
+       *hccr = (struct ehci_hccr *)((uint32_t)&rehci->hciversion);
+       cap_base = ehci_readl(&(*hccr)->cr_capbase);
+       *hcor = (struct ehci_hcor *)((uint32_t)*hccr + HC_LENGTH(cap_base));
+
+       return 0;
+}