]> git.sur5r.net Git - u-boot/commitdiff
mips: bmips: add support for bcm6318 usb
authorÁlvaro Fernández Rojas <noltari@gmail.com>
Sun, 4 Feb 2018 20:11:16 +0000 (21:11 +0100)
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
Wed, 21 Mar 2018 22:23:13 +0000 (23:23 +0100)
Signed-off-by: Ã\81lvaro Fernández Rojas <noltari@gmail.com>
arch/mips/dts/brcm,bcm6318.dtsi
include/configs/bmips_bcm6318.h

index 54964a700989327285e4b7c85c64bf7c5b7c8ad9..015acc91735c6f39a2052973f2c0a3f97fc467dc 100644 (file)
                        reg = <0x10004000 0x38>;
                        u-boot,dm-pre-reloc;
                };
+
+               ehci: usb-controller@10005000 {
+                       compatible = "brcm,bcm6318-ehci", "generic-ehci";
+                       reg = <0x10005000 0x100>;
+                       phys = <&usbh>;
+                       big-endian;
+
+                       status = "disabled";
+               };
+
+               ohci: usb-controller@10005100 {
+                       compatible = "brcm,bcm6318-ohci", "generic-ohci";
+                       reg = <0x10005100 0x100>;
+                       phys = <&usbh>;
+                       big-endian;
+
+                       status = "disabled";
+               };
+
+               usbh: usb-phy@10005200 {
+                       compatible = "brcm,bcm6318-usbh";
+                       reg = <0x10005200 0x30>;
+                       #phy-cells = <0>;
+                       clocks = <&periph_clk BCM6318_CLK_USB>;
+                       clock-names = "usbh";
+                       power-domains = <&periph_pwr BCM6318_PWR_USB>;
+                       resets = <&periph_rst BCM6318_RST_USBH>;
+
+                       status = "disabled";
+               };
        };
 };
index 454a7b7f7bafdaefdd3657af91e4a359f28b1fe5..5541cc5cf6a543450f0ce3780c16392908e41592 100644 (file)
 #define CONFIG_NR_DRAM_BANKS           1
 #define CONFIG_SYS_SDRAM_BASE          0x80000000
 
+/* USB */
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_OHCI_NEW
+
 /* U-Boot */
 #define CONFIG_SYS_LOAD_ADDR           CONFIG_SYS_SDRAM_BASE + 0x100000