]> git.sur5r.net Git - u-boot/commitdiff
OMAP5: Enable access to auxclk registers
authorLubomir Popov <lpopov@mm-sol.com>
Wed, 15 May 2013 04:41:01 +0000 (04:41 +0000)
committerTom Rini <trini@ti.com>
Mon, 10 Jun 2013 12:54:46 +0000 (08:54 -0400)
auxclk0 and auxclk1 are utilized on some OMAP5 boards.
Define the infrastructure needed for accessing them
without using magic numbers.

Also remove unrelated TPS62361 defines from clocks.h

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
arch/arm/cpu/armv7/omap5/prcm-regs.c
arch/arm/include/asm/arch-omap5/clock.h
arch/arm/include/asm/omap_common.h

index 5a7370c773240c4e07fccb64ad97383ad01f2eee..e839ff5fe53828b0f38c27dea002f02c7fcd863b 100644 (file)
@@ -308,6 +308,10 @@ struct prcm_regs const omap5_es1_prcm = {
        .prm_sldo_mpu_ctrl = 0x4ae07bd0,
        .prm_sldo_mm_setup = 0x4ae07bd4,
        .prm_sldo_mm_ctrl = 0x4ae07bd8,
+
+       /* SCRM stuff, used by some boards */
+       .scrm_auxclk0 = 0x4ae0a310,
+       .scrm_auxclk1 = 0x4ae0a314,
 };
 
 struct omap_sys_ctrl_regs const omap5_ctrl = {
@@ -751,6 +755,10 @@ struct prcm_regs const omap5_es2_prcm = {
        .prm_sldo_mm_ctrl = 0x4ae07cd8,
        .prm_abbldo_mpu_setup = 0x4ae07cdc,
        .prm_abbldo_mpu_ctrl = 0x4ae07ce0,
+
+       /* SCRM stuff, used by some boards */
+       .scrm_auxclk0 = 0x4ae0a310,
+       .scrm_auxclk1 = 0x4ae0a314,
 };
 
 struct prcm_regs const dra7xx_prcm = {
index 1affa4f6668bf5b82decd574e6552295d2d771e5..4d2765d878f0be40215f0d4449bf66d42b819e46 100644 (file)
 #define TPS62361_BASE_VOLT_MV  500
 #define TPS62361_VSEL0_GPIO    7
 
+/* Defines for DPLL setup */
+#define DPLL_LOCKED_FREQ_TOLERANCE_0           0
+#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ     500
+#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ       1000
+
 #define DPLL_NO_LOCK   0
 #define DPLL_LOCK      1
 
 #endif
 
 #define V_SCLK V_OSCK
+
+/* AUXCLKx reg fields */
+#define AUXCLK_ENABLE_MASK             (1 << 8)
+#define AUXCLK_SRCSELECT_SHIFT         1
+#define AUXCLK_SRCSELECT_MASK          (3 << 1)
+#define AUXCLK_CLKDIV_SHIFT            16
+#define AUXCLK_CLKDIV_MASK             (0xF << 16)
+
+#define AUXCLK_SRCSELECT_SYS_CLK       0
+#define AUXCLK_SRCSELECT_CORE_DPLL     1
+#define AUXCLK_SRCSELECT_PER_DPLL      2
+#define AUXCLK_SRCSELECT_ALTERNATE     3
+
 #endif /* _CLOCKS_OMAP5_H_ */
index fa2963e5697df4425b408d72e47bf1ef2ea9c07f..787e614ecb0da881f18028971c7f258453f25a74 100644 (file)
@@ -351,6 +351,10 @@ struct prcm_regs {
        u32 cm_l3init_usbphy_clkctrl;
        u32 cm_l4per_mcbsp4_clkctrl;
        u32 prm_vc_cfg_channel;
+
+       /* SCRM stuff, used by some boards */
+       u32 scrm_auxclk0;
+       u32 scrm_auxclk1;
 };
 
 struct omap_sys_ctrl_regs {