sbc8548: enable ability to boot from alternate flash

This board has an 8MB soldered on flash, and a 64MB SODIMM
flash module.  Normally the board boots from the 8MB flash,
but the hardware can be configured for booting from the 64MB
flash as well by swapping CS0 and CS6.  This can be handy
for recovery purposes, or for supporting u-boot and VxBoot
at the same time.

To support this in u-boot, we need to have different BR0/OR0
and BR6/OR6 settings in place for when the board is configured
in this way, and a different TEXT_BASE needs to be used due
to the larger sector size of the 64MB flash module.

We introduce the suffix _8M and _64M for the BR0/BR6 and the
OR0/OR6 values so it is clear which is being used to map what
specific device.

The larger sector size (512k) of the alternate flash needs
a larger malloc pool, otherwise you'll get failures when
running saveenv, so bump it up accordingly.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c
index febb6829c35f04ef6604fa43636bf4bf70dd9008..c263191c3ddf37c79bc88867e3961be5c9fc6427 100644 (file)
--- a/board/sbc8548/law.c
+++ b/board/sbc8548/law.c
@@ -41,13 +41,21 @@
  * 0xf8b0_0000 0xf80f_ffff     EEPROM                  1M
  * 0xff80_0000 0xffff_ffff     FLASH (boot bank)       8M
  *
+ * If swapped CS0/CS6 via JP12+SW2.8:
+ * 0xef80_0000 0xefff_ffff     FLASH (2nd bank)        8M
+ * 0xfc00_0000 0xffff_ffff     FLASH (boot bank)       64M
+ *
  * Notes:
  *     CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
  *     If flash is 8M at default position (last 8M), no LAW needed.
  */
 
 struct law_entry law_table[] = {
+#ifdef CONFIG_SYS_ALT_BOOT
+       SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
+#else
        SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+#endif
 #ifndef CONFIG_SPD_EEPROM
        SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
 #endif

diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index 26095a545596f96a48f775b18ebed7bad0084a31..63d504d61da5b7290727f0e1e5bdaaf1f1a53c8d 100644 (file)
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -113,7 +113,7 @@ void lbc_sdram_init(void)
 
        puts("    SDRAM: ");
 
-       print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+       print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 
        /*
         * Setup SDRAM Base and Option Registers

diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c
index e9cedc7c0dc3a755f35af5543d1578d8d14be32b..4bf72147bad51580e32bb32e960906ef840eecbb 100644 (file)
--- a/board/sbc8548/tlb.c
+++ b/board/sbc8548/tlb.c
@@ -104,6 +104,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 5, BOOKE_PAGESZ_16M, 1),
 
+#ifndef CONFIG_SYS_ALT_BOOT
        /*
         * TLB 6:       64M     Non-cacheable, guarded
         * 0xec000000   64M     64MB user FLASH
@@ -111,6 +112,24 @@ struct fsl_e_tlb_entry tlb_table[] = {
        SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 6, BOOKE_PAGESZ_64M, 1),
+#else
+       /*
+        * TLB 6:       4M      Non-cacheable, guarded
+        * 0xef800000   4M      1st 1/2 8MB soldered FLASH
+        */
+       SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 6, BOOKE_PAGESZ_4M, 1),
+
+       /*
+        * TLB 7:       4M      Non-cacheable, guarded
+        * 0xefc00000   4M      2nd half 8MB soldered FLASH
+        */
+       SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000,
+                     CONFIG_SYS_ALT_FLASH + 0x400000,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 7, BOOKE_PAGESZ_4M, 1),
+#endif
 
 };
 

diff --git a/doc/README.sbc8548 b/doc/README.sbc8548
index 5fa9c936851f03dd6b1d6e2952777750e11110fc..e6b8abe2b362334c181288318398a2ede92bd58b 100644 (file)
--- a/doc/README.sbc8548
+++ b/doc/README.sbc8548
@@ -86,6 +86,33 @@ The "md" steps in the above are just a precautionary step that allow
 you to confirm the u-boot version that was downloaded, and then confirm
 that it was copied to flash.
 
+The above assumes that you are using the default board settings which
+have u-boot in the 8MB flash, tied to /CS0.
+
+If you are running the default 8MB /CS0 settings but want to store an
+image in the SODIMM that is built with CONFIG_SYS_ALT_BOOT enabled,
+(as a backup, etc) then the steps will become:
+
+       tftp u-boot.bin
+       md 200000 10
+       protect off all
+       era eff00000 efffffff
+       cp.b 200000 eff00000 100000
+       md eff00000 10
+       protect on all
+
+Finally, if you are running the alternate 64MB /CS0 settings and want
+to update the in-use u-boot image, then (again with CONFIG_SYS_ALT_BOOT
+enabled) the steps will become:
+
+       tftp u-boot.bin
+       md 200000 10
+       protect off all
+       era fff00000 ffffffff
+       cp.b 200000 fff00000 100000
+       md fff00000 10
+       protect on all
+
 
 Hardware Reference:
 ===================
@@ -127,10 +154,9 @@ JP19               PCI mode        PCI             PCI-X
 onto /CS0 and the SODIMM flash on /CS6 (default).  When JP12
 is jumpered parallel to the LBC-SDRAM, then /CS0 is for the
 SODIMM flash and /CS6 is for the boot flash.  Note that in this
-alternate setting, you also need to switch SW2.8 to ON.  Currently
-u-boot doesn't support booting off the SODIMM in this alternate
-setting without manually altering BR0/OR0 and BR6/OR6 in the
-board config file appropriately.
+alternate setting, you also need to switch SW2.8 to ON.
+See the setting CONFIG_SYS_ALT_BOOT if you want to use this setting
+and boot u-boot from the 64MB SODIMM
 
 
        Switches:

diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index cea017900ff9cb96e0daf27b3eef3404fe526708..fb07d09f3f40f26d015d7d2b66b97cd7b347ac9c 100644 (file)
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -57,9 +57,19 @@
 #define CONFIG_MPC8548         1       /* MPC8548 specific */
 #define CONFIG_SBC8548         1       /* SBC8548 board specific */
 
+/*
+ * If you want to boot from the SODIMM flash, instead of the soldered
+ * on flash, set this, and change JP12, SW2:8 accordingly.
+ */
+#undef CONFIG_SYS_ALT_BOOT
+
 #ifndef CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_SYS_ALT_BOOT
+#define CONFIG_SYS_TEXT_BASE   0xfff00000
+#else
 #define CONFIG_SYS_TEXT_BASE   0xfffa0000
 #endif
+#endif
 
 #undef CONFIG_RIO
 
@@ -139,28 +149,54 @@
 /*
  * FLASH on the Local Bus
  * Two banks, one 8MB the other 64MB, using the CFI driver.
- * Boot from BR0/OR0 bank at 0xff80_0000
- * Alternate BR6/OR6 bank at 0xec00_0000
+ * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have
+ * CS0 the 8MB boot flash, and CS6 the 64MB flash.
  *
- * BR0:
+ *     Default:
+ *     ec00_0000       efff_ffff       64MB SODIMM
+ *     ff80_0000       ffff_ffff       8MB soldered flash
+ *
+ *     Alternate:
+ *     ef80_0000       efff_ffff       8MB soldered flash
+ *     fc00_0000       ffff_ffff       64MB SODIMM
+ *
+ * BR0_8M:
  *    Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0
  *    Port Size = 8 bits = BRx[19:20] = 01
  *    Use GPCM = BRx[24:26] = 000
  *    Valid = BRx[31] = 1
  *
- * 0    4    8    12   16   20   24   28
- * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801    BR0
- *
- * BR6:
- *    Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0
+ * BR0_64M:
+ *    Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0
  *    Port Size = 32 bits = BRx[19:20] = 11
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801    BR0_8M
+ * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801    BR0_64M
+ */
+#define CONFIG_SYS_BR0_8M      0xff800801
+#define CONFIG_SYS_BR0_64M     0xfc001801
+
+/*
+ * BR6_8M:
+ *    Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0
+ *    Port Size = 8 bits = BRx[19:20] = 01
  *    Use GPCM = BRx[24:26] = 000
  *    Valid = BRx[31] = 1
+
+ * BR6_64M:
+ *    Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0
+ *    Port Size = 32 bits = BRx[19:20] = 11
  *
  * 0    4    8    12   16   20   24   28
- * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801    BR6
- *
- * OR0:
+ * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801    BR6_8M
+ * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801    BR6_64M
+ */
+#define CONFIG_SYS_BR6_8M      0xef800801
+#define CONFIG_SYS_BR6_64M     0xec001801
+
+/*
+ * OR0_8M:
  *    Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0
  *    XAM = OR0[17:18] = 11
  *    CSNT = OR0[20] = 1
@@ -169,11 +205,20 @@
  *    TRLX = use relaxed timing = OR0[29] = 1
  *    EAD = use external address latch delay = OR0[31] = 1
  *
- * 0    4    8    12   16   20   24   28
- * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    OR0
+ * OR0_64M:
+ *    Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0
  *
- * OR6:
- *    Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    OR0_8M
+ * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65    OR0_64M
+ */
+#define CONFIG_SYS_OR0_8M      0xff806e65
+#define CONFIG_SYS_OR0_64M     0xfc006e65
+
+/*
+ * OR6_8M:
+ *    Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0
  *    XAM = OR6[17:18] = 11
  *    CSNT = OR6[20] = 1
  *    ACS = half cycle delay = OR6[21:22] = 11
@@ -181,20 +226,37 @@
  *    TRLX = use relaxed timing = OR6[29] = 1
  *    EAD = use external address latch delay = OR6[31] = 1
  *
+ * OR6_64M:
+ *    Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0
+ *
  * 0    4    8    12   16   20   24   28
- * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65    OR6
+ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    OR6_8M
+ * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65    OR6_64M
  */
+#define CONFIG_SYS_OR6_8M      0xff806e65
+#define CONFIG_SYS_OR6_64M     0xfc006e65
 
+#ifndef CONFIG_SYS_ALT_BOOT            /* JP12 in default position */
 #define CONFIG_SYS_BOOT_BLOCK          0xff800000      /* start of 8MB Flash */
 #define CONFIG_SYS_ALT_FLASH           0xec000000      /* 64MB "user" flash */
-#define CONFIG_SYS_FLASH_BASE          CONFIG_SYS_BOOT_BLOCK   /* start of FLASH 16M */
 
-#define CONFIG_SYS_BR0_PRELIM          0xff800801
-#define CONFIG_SYS_BR6_PRELIM          0xec001801
+#define CONFIG_SYS_BR0_PRELIM          CONFIG_SYS_BR0_8M
+#define CONFIG_SYS_OR0_PRELIM          CONFIG_SYS_OR0_8M
+
+#define CONFIG_SYS_BR6_PRELIM          CONFIG_SYS_BR6_64M
+#define CONFIG_SYS_OR6_PRELIM          CONFIG_SYS_OR6_64M
+#else                                  /* JP12 in alternate position */
+#define CONFIG_SYS_BOOT_BLOCK          0xfc000000      /* start 64MB Flash */
+#define CONFIG_SYS_ALT_FLASH           0xef800000      /* 8MB soldered flash */
 
-#define        CONFIG_SYS_OR0_PRELIM           0xff806e65
-#define        CONFIG_SYS_OR6_PRELIM           0xfc006e65
+#define CONFIG_SYS_BR0_PRELIM          CONFIG_SYS_BR0_64M
+#define CONFIG_SYS_OR0_PRELIM          CONFIG_SYS_OR0_64M
+
+#define CONFIG_SYS_BR6_PRELIM          CONFIG_SYS_BR6_8M
+#define CONFIG_SYS_OR6_PRELIM          CONFIG_SYS_OR6_8M
+#endif
 
+#define CONFIG_SYS_FLASH_BASE          CONFIG_SYS_BOOT_BLOCK
 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE, \
                                         CONFIG_SYS_ALT_FLASH}
 #define CONFIG_SYS_MAX_FLASH_BANKS     2               /* number of banks */
@@ -330,7 +392,7 @@
  * thing for MONITOR_LEN in both cases.
  */
 #define CONFIG_SYS_MONITOR_LEN         (~CONFIG_SYS_TEXT_BASE + 1)
-#define CONFIG_SYS_MALLOC_LEN          (128 * 1024)    /* Reserved for malloc */
+#define CONFIG_SYS_MALLOC_LEN          (1024 * 1024) /* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX      1