Exynos542x: cache: Disable clean/evict push to external

L2 Auxiliary Control Register provides configuration
and control options for the L2 memory system. Bit 3
of L2ACTLR stands for clean/evict push to external.
Setting bit 3 disables clean/evict which is what
this patch intends to do.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/arch/arm/cpu/armv7/exynos/soc.c b/arch/arm/cpu/armv7/exynos/soc.c
index 8c7d7d893f1b1e7433279f6b16a420803b687733..427f54c7e629373068a1c80e6a671833431bc796 100644 (file)
--- a/arch/arm/cpu/armv7/exynos/soc.c
+++ b/arch/arm/cpu/armv7/exynos/soc.c
@@ -13,7 +13,9 @@ enum l2_cache_params {
        CACHE_TAG_RAM_SETUP = (1 << 9),
        CACHE_DATA_RAM_SETUP = (1 << 5),
        CACHE_TAG_RAM_LATENCY = (2 << 6),
-       CACHE_DATA_RAM_LATENCY = (2 << 0)
+       CACHE_DATA_RAM_LATENCY = (2 << 0),
+       CACHE_ENABLE_CLEAN_EVICT = (0 << 3),
+       CACHE_DISABLE_CLEAN_EVICT = (1 << 3)
 };
 
 void reset_cpu(ulong addr)
@@ -37,14 +39,28 @@ static void exynos5_set_l2cache_params(void)
 {
        unsigned int val = 0;
 
+       /* Read L2CTLR value */
        asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(val));
 
+       /* Set cache setup and latency cycles */
        val |= CACHE_TAG_RAM_SETUP |
                CACHE_DATA_RAM_SETUP |
                CACHE_TAG_RAM_LATENCY |
                CACHE_DATA_RAM_LATENCY;
 
+       /* Write new vlaue to L2CTLR */
        asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
+
+       if (proid_is_exynos5420() || proid_is_exynos5800()) {
+               /* Read L2ACTLR value */
+               asm volatile("mrc       p15, 1, %0, c15, c0, 0" : "=r" (val));
+
+               /* Disable clean/evict push to external */
+               val |= CACHE_DISABLE_CLEAN_EVICT;
+
+               /* Write new vlaue to L2ACTLR */
+               asm volatile("mcr       p15, 1, %0, c15, c0, 0" : : "r" (val));
+       }
 }
 
 /*