gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
return 0;
}
+
+/* This is a dummy function on arc */
+int dram_init(void)
+{
+ return 0;
+}
DECLARE_GLOBAL_DATA_PTR;
-int initdram(void)
+int dram_init(void)
{
ddr_tap_tuning();
gd->ram_size = get_ram_size((void *)KSEG1, SZ_256M);
}
/* initialize the DDR2 Controller and DDR2 PHY */
-int initdram(void)
+int dram_init(void)
{
ddr2_pmd_ungate();
ddr2_phy_init();
#ifndef __MICROCHIP_PIC32_DDR_H
#define __MICROCHIP_PIC32_DDR_H
-/* called by initdram() function */
+/* called by dram_init() function */
void ddr2_phy_init(void);
void ddr2_ctrl_init(void);
phys_size_t ddr2_calculate_size(void);
.ops = &altera_nios2_ops,
.flags = DM_FLAG_PRE_RELOC,
};
+
+/* This is a dummy function on nios2 */
+int dram_init(void)
+{
+ return 0;
+}
/*
* On MPC5200, the initial RAM (and gd) is located in the internal
* SRAM. So we can actually call the preloader console init code
- * before calling initdram(). This makes serial output (printf)
+ * before calling dram_init(). This makes serial output (printf)
* available very early, even before SDRAM init, which has been
* an U-Boot priciple from day 1.
*/
* First we need to initialize the SDRAM, so that the real
* U-Boot or the OS (Linux) can be loaded
*/
- initdram();
+ dram_init();
/* Clear bss */
memset(__bss_start, '\0', __bss_end - __bss_start);
#ifndef CONFIG_FSL_CORENET
#if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
!defined(CONFIG_SYS_INIT_L2_ADDR)
-int initdram(void)
+int dram_init(void)
{
#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
defined(CONFIG_ARCH_QEMU_E500)
return 0;
}
#else /* CONFIG_SYS_RAMBOOT */
-int initdram(void)
+int dram_init(void)
{
phys_size_t dram_size = 0;
}
/*-----------------------------------------------------------------------------+
- * initdram. Initializes the 440SP Memory Queue and DDR SDRAM controller.
+ * dram_init. Initializes the 440SP Memory Queue and DDR SDRAM controller.
* Note: This routine runs from flash with a stack set up in the chip's
* sram space. It is important that the routine does not require .sbss, .bss or
* .data sections. It also cannot call routines that require these sections.
*-----------------------------------------------------------------------------*/
/*-----------------------------------------------------------------------------
- * Function: initdram
+ * Function: dram_init
* Description: Configures SDRAM memory banks for DDR operation.
* Auto Memory Configuration option reads the DDR SDRAM EEPROMs
* via the IIC bus and then configures the DDR SDRAM memory
* banks appropriately. If Auto Memory Configuration is
* not used, it is assumed that no DIMM is plugged
*-----------------------------------------------------------------------------*/
-int initdram(void)
+int dram_init(void)
{
unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE};
#else /* CONFIG_SPD_EEPROM */
/*-----------------------------------------------------------------------------
- * Function: initdram
+ * Function: dram_init
* Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller.
* The configuration is performed using static, compile-
* time parameters.
* Configures the PPC405EX(r) and PPC460EX/GT
*---------------------------------------------------------------------------*/
-int initdram(void)
+int dram_init(void)
{
unsigned long val;
}
/*-----------------------------------------------------------------------------+
- * initdram. Initializes the 440EPx/GPx DDR SDRAM controller.
+ * dram_init. Initializes the 440EPx/GPx DDR SDRAM controller.
* Note: This routine runs from flash with a stack set up in the chip's
* sram space. It is important that the routine does not require .sbss, .bss or
* .data sections. It also cannot call routines that require these sections.
*-----------------------------------------------------------------------------*/
/*-----------------------------------------------------------------------------
- * Function: initdram
+ * Function: dram_init
* Description: Configures SDRAM memory banks for DDR operation.
* Auto Memory Configuration option reads the DDR SDRAM EEPROMs
* via the IIC bus and then configures the DDR SDRAM memory
* banks appropriately. If Auto Memory Configuration is
* not used, it is assumed that no DIMM is plugged
*-----------------------------------------------------------------------------*/
-int initdram(void)
+int dram_init(void)
{
unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
unsigned long dimm_ranks[MAXDIMMS];
unsigned long cas_latency = 0; /* to quiet initialization warning */
unsigned long dram_size;
- debug("\nEntering initdram()\n");
+ debug("\nEntering dram_init()\n");
/*------------------------------------------------------------------
* Stop the DDR-SDRAM controller.
/*
* Autodetect onboard SDRAM on 405 platforms
*/
-int initdram(void)
+int dram_init(void)
{
ulong speed;
ulong sdtr1;
* so this should be extended for other future boards
* using this routine!
*/
-int initdram(void)
+int dram_init(void)
{
int i;
int tr1_bank1;
* First we need to initialize the SDRAM, so that the real
* U-Boot or the OS (Linux) can be loaded
*/
- initdram();
+ dram_init();
/* Clear bss */
memset(__bss_start, '\0', __bss_end - __bss_start);
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
}
+
+int dram_init(void)
+{
+ return 0;
+}
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
- initdram();
+ dram_init();
#ifdef CONFIG_SPL_NAND_BOOT
puts("Tertiary program loader running in sram...");
#else
return 0;
}
-int initdram(void)
+int dram_init(void)
{
int size, i;
#endif
/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
* use of CONFIG_SYS_SDRAM_BASE. The code does not work if
* CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
*/
-int initdram(void)
+int dram_init(void)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
#endif
/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
* is something else than 0x00000000.
*/
-int initdram(void)
+int dram_init(void)
{
ulong dramsize = 0;
uint svr, pvr;
return;
}
-int initdram(void)
+int dram_init(void)
{
int i;
u32 val;
}
-int initdram(void)
+int dram_init(void)
{
gd->ram_size = spd_sdram();
}
/* -------------------------------------------------------------------------
- initdram() reads EEPROM via I2c. EEPROM contains all of
+ dram_init() reads EEPROM via I2c. EEPROM contains all of
the necessary info for SDRAM controller configuration
------------------------------------------------------------------------- */
-int initdram(void)
+int dram_init(void)
{
gd->ram_size = spd_sdram();
/*************************************************************************
*
- * initdram -- 440EPx's DDR controller is a DENALI Core
+ * dram_init -- 440EPx's DDR controller is a DENALI Core
*
************************************************************************/
-int initdram(void)
+int dram_init(void)
{
#if !defined(CONFIG_SYS_RAMBOOT)
ulong speed = get_bus_freq(0);
}
/*
- * initdram() reads EEPROM via I2c. EEPROM contains all of
+ * dram_init() reads EEPROM via I2c. EEPROM contains all of
* the necessary info for SDRAM controller configuration
*/
-int initdram(void)
+int dram_init(void)
{
gd->ram_size = spd_sdram();
}
/*************************************************************************
- * initdram -- doesn't use serial presence detect.
+ * dram_init -- doesn't use serial presence detect.
*
* Assumes: 256 MB, ECC, non-registered
* PLB @ 133 MHz
*tr1_value = (first_good + last_bad) / 2;
}
-int initdram(void)
+int dram_init(void)
{
register uint reg;
int tr1_bank1, tr1_bank2;
return 0;
}
-int initdram(void)
+int dram_init(void)
{
#if !defined(CONFIG_MONITOR_IS_IN_RAM)
sdram_t *sdp = (sdram_t *)(MMAP_SDRAM);
#endif
/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
* is something else than 0x00000000.
*/
-int initdram(void)
+int dram_init(void)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
/*
* Initalize SDRAM - configure SDRAM controller, detect memory size.
*/
-int initdram(void)
+int dram_init(void)
{
ulong dramsize = 0;
#ifndef CONFIG_SYS_RAMBOOT
return 0;
};
-int initdram(void)
+int dram_init(void)
{
volatile sdramctrl_t *sdp = (sdramctrl_t *) (MMAP_SDRAM);
DECLARE_GLOBAL_DATA_PTR;
-int initdram(void)
+int dram_init(void)
{
gd->ram_size = fixed_sdram(NULL, NULL, 0);
DECLARE_GLOBAL_DATA_PTR;
-int initdram(void)
+int dram_init(void)
{
/* Sdram is setup by assembler code */
/* If memory could be changed, we should return the true value here */
return 0;
}
-int initdram(void)
+int dram_init(void)
{
gd->ram_size = get_ram_size(0, fixed_sdram(NULL, NULL, 0));
};
/*
- * initdram -- 440EPx's DDR controller is a DENALI Core
+ * dram_init -- 440EPx's DDR controller is a DENALI Core
*/
int initdram_by_rb(int rows, int banks)
{
return 0;
}
-int initdram(void)
+int dram_init(void)
{
phys_size_t size;
int n;
void ddr_enable_ecc(unsigned int dram_size);
-int initdram(void)
+int dram_init(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize = 0;
popts->cpo_sample = 0x3e;
}
-int initdram(void)
+int dram_init(void)
{
phys_size_t dram_size;
puts("\n\n");
- initdram();
+ dram_init();
#ifdef CONFIG_SPL_NAND_BOOT
nand_boot();
i2c_init_all();
- initdram();
+ dram_init();
#ifdef CONFIG_SPL_NAND_BOOT
puts("TPL\n");
popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
}
-int initdram(void)
+int dram_init(void)
{
phys_size_t dram_size;
return 0;
};
-int initdram(void)
+int dram_init(void)
{
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
return 0;
};
-int initdram(void)
+int dram_init(void)
{
u32 dramsize;
return 0;
};
-int initdram(void)
+int dram_init(void)
{
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
};
-int initdram(void)
+int dram_init(void)
{
unsigned long junk = 0xa5a59696;
return 0;
};
-int initdram(void)
+int dram_init(void)
{
u32 dramsize = 0;
return 0;
};
-int initdram(void)
+int dram_init(void)
{
/*
* Check to see if the SDRAM has already been initialized
return 0;
};
-int initdram(void)
+int dram_init(void)
{
sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM);
return 0;
};
-int initdram(void)
+int dram_init(void)
{
sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
return 0;
}
-int initdram(void)
+int dram_init(void)
{
u32 dramsize, i, dramclk;
return 0;
};
-int initdram(void)
+int dram_init(void)
{
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
return 0;
};
-int initdram(void)
+int dram_init(void)
{
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
return 0;
};
-int initdram(void)
+int dram_init(void)
{
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
return 0;
};
-int initdram(void)
+int dram_init(void)
{
u32 dramsize;
return 0;
};
-int initdram(void)
+int dram_init(void)
{
u32 dramsize;
#ifdef CONFIG_CF_SBF
return 0;
};
-int initdram(void)
+int dram_init(void)
{
u32 dramsize;
#ifdef CONFIG_CF_SBF
return 0;
};
-int initdram(void)
+int dram_init(void)
{
siu_t *siu = (siu_t *) (MMAP_SIU);
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
return 0;
};
-int initdram(void)
+int dram_init(void)
{
siu_t *siu = (siu_t *) (MMAP_SIU);
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
return(ismicron);
}
-int initdram(void)
+int dram_init(void)
{
u32 msize = 0;
/*
return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
}
-int initdram(void)
+int dram_init(void)
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize;
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
puts("NAND boot... ");
timer_init();
- initdram();
+ dram_init();
relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
CONFIG_SYS_NAND_U_BOOT_RELOC);
}
return msize;
}
-int initdram(void)
+int dram_init(void)
{
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile fsl_lbc_t *lbc = &im->im_lbc;
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
puts("NAND boot... ");
timer_init();
- initdram();
+ dram_init();
relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
CONFIG_SYS_NAND_U_BOOT_RELOC);
}
}
#endif /* CONFIG_SYS_RAMBOOT */
-int initdram(void)
+int dram_init(void)
{
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
u32 msize;
int fixed_sdram(void);
-int initdram(void)
+int dram_init(void)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msize = 0;
int fixed_sdram(void);
-int initdram(void)
+int dram_init(void)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msize = 0;
#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
-int initdram(void)
+int dram_init(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
phys_size_t msize = 0;
};
#endif /* CONFIG_PCI */
-int initdram(void)
+int dram_init(void)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msize = 0;
#endif
int fixed_sdram(void);
-int initdram(void)
+int dram_init(void)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msize = 0;
#endif
int fixed_sdram(void);
-int initdram(void)
+int dram_init(void)
{
immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msize = 0;
}
-int initdram(void)
+int dram_init(void)
{
phys_size_t dram_size = 0;
return 0;
}
-int initdram(void)
+int dram_init(void)
{
phys_size_t dram_size = 0;
i2c_init_all();
- initdram();
+ dram_init();
#ifdef CONFIG_SPL_NAND_BOOT
puts("\nTertiary program loader running in sram...");
#else
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
- initdram();
+ dram_init();
#ifdef CONFIG_SPL_NAND_BOOT
puts("Tertiary program loader running in sram...");
#else
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
- initdram();
+ dram_init();
#ifdef CONFIG_SPL_NAND_BOOT
puts("Tertiary program loader running in sram...");
#else
popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
}
-int initdram(void)
+int dram_init(void)
{
phys_size_t dram_size = 0;
}
#endif
-int initdram(void)
+int dram_init(void)
{
phys_size_t dram_size;
i2c_init_all();
- initdram();
+ dram_init();
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
}
#endif
-int initdram(void)
+int dram_init(void)
{
phys_size_t dram_size;
i2c_init_all();
- initdram();
+ dram_init();
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
}
#endif
-int initdram(void)
+int dram_init(void)
{
phys_size_t dram_size;
}
#endif
-int initdram(void)
+int dram_init(void)
{
phys_size_t dram_size;
puts("\n\n");
- initdram();
+ dram_init();
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
popts->cpo_sample = 0x64;
}
-int initdram(void)
+int dram_init(void)
{
phys_size_t dram_size;
i2c_init_all();
- initdram();
+ dram_init();
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
popts->cpo_sample = 0x54;
}
-int initdram(void)
+int dram_init(void)
{
phys_size_t dram_size;
i2c_init_all();
- initdram();
+ dram_init();
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
popts->cpo_sample = 0x63;
}
-int initdram(void)
+int dram_init(void)
{
phys_size_t dram_size;
i2c_init_all();
- initdram();
+ dram_init();
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
popts->cpo_sample = 0x64;
}
-int initdram(void)
+int dram_init(void)
{
phys_size_t dram_size;
i2c_init_all();
- initdram();
+ dram_init();
mmc_boot();
}
#include <config.h>
#include <asm/leon.h>
-int initdram(void)
+int dram_init(void)
{
/* Does not set gd->ram_size here */
#include <config.h>
#include <asm/leon.h>
-int initdram(void)
+int dram_init(void)
{
/* Does not set gd->ram_size here */
#include <config.h>
#include <asm/leon.h>
-int initdram(void)
+int dram_init(void)
{
/* Does not set gd->ram_size here */
#include <common.h>
#include <asm/leon.h>
-int initdram(void)
+int dram_init(void)
{
/* Does not set gd->ram_size here */
#include <common.h>
#include <asm/leon.h>
-int initdram(void)
+int dram_init(void)
{
/* Does not set gd->ram_size here */
return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
}
-int initdram(void)
+int dram_init(void)
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize;
return msize;
}
-int initdram(void)
+int dram_init(void)
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
fsl_lbc_t *lbc = &im->im_lbc;
/* EMPTY, optional, we don't do it */
};
-int initdram(void)
+int dram_init(void)
{
gd->ram_size = fixed_sdram(NULL, sdram_init_seq,
ARRAY_SIZE(sdram_init_seq));
#endif
/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
* use of CONFIG_SYS_SDRAM_BASE. The code does not work if
* CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
*/
-int initdram(void)
+int dram_init(void)
{
struct mpc5xxx_mmap_ctl *mmap_ctl =
(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
DECLARE_GLOBAL_DATA_PTR;
-int initdram(void)
+int dram_init(void)
{
u32 ddrconf0 = __raw_readl((uint32_t *)BOSTON_PLAT_DDRCONF0);
}
}
-int initdram(void)
+int dram_init(void)
{
gd->ram_size = CONFIG_SYS_MEM_SIZE;
DECLARE_GLOBAL_DATA_PTR;
/* initialize the DDR Controller and PHY */
-int initdram(void)
+int dram_init(void)
{
/* MIG IP block is smart and doesn't need SW
* to do any init */
#endif
/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
* is something else than 0x00000000.
*/
-int initdram(void)
+int dram_init(void)
{
volatile struct mpc5xxx_mmap_ctl *mm =
(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
#endif
/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
* use of CONFIG_SYS_SDRAM_BASE. The code does not work if
* CONFIG_SYS_SDRAM_BASE is something other than 0x00000000.
*/
-int initdram(void)
+int dram_init(void)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
}
/*
- * ATTENTION: Although partially referenced initdram does NOT make real
+ * ATTENTION: Although partially referenced dram_init does NOT make real
* use of CONFIG_SYS_SDRAM_BASE. The code does not work if
* CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
*/
-int initdram(void)
+int dram_init(void)
{
struct mpc5xxx_mmap_ctl *mmap_ctl =
(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
#endif
/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
* is something else than 0x00000000.
*/
-int initdram(void)
+int dram_init(void)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
#endif /* CONFIG_SYS_SDRAM_LIST */
-int initdram(void)
+int dram_init(void)
{
immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
memctl8260_t *memctl = &immap->im_memctl;
return msize;
}
-int initdram(void)
+int dram_init(void)
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize = 0;
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR_ODT_75ohm;
}
-int initdram(void)
+int dram_init(void)
{
phys_size_t dram_size = 0;
/*************************************************************************
*
- * initdram -- 440EPx's DDR controller is a DENALI Core
+ * dram_init -- 440EPx's DDR controller is a DENALI Core
*
************************************************************************/
-int initdram(void)
+int dram_init(void)
{
/* CL=4 */
mtsdram(DDR0_02, 0x00000000);
* SDRAM is already configured by the bootstrap code, only return the
* auto-detected size here
*/
-int initdram(void)
+int dram_init(void)
{
gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_MBYTES_SDRAM << 20);
/*
* Initalize SDRAM - configure SDRAM controller, detect memory size.
*/
-int initdram(void)
+int dram_init(void)
{
ulong dramsize = 0;
#ifndef CONFIG_SYS_RAMBOOT
return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
}
-int initdram(void)
+int dram_init(void)
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize;
/* ------------------------------------------------------------------------- */
/* ------------------------------------------------------------------------- */
/*
- initdram() reads EEPROM via I2c. EEPROM contains all of
+ dram_init() reads EEPROM via I2c. EEPROM contains all of
the necessary info for SDRAM controller configuration
*/
/* ------------------------------------------------------------------------- */
/* ------------------------------------------------------------------------- */
static int test_dram (unsigned long ramsize);
-int initdram(void)
+int dram_init(void)
{
unsigned long bank_reg[4], tmp, bank_size;
/*
* Get RAM size.
*/
-int initdram(void)
+int dram_init(void)
{
unsigned char board_rev;
unsigned long reg;
/* ------------------------------------------------------------------------- */
/* ------------------------------------------------------------------------- */
/*
- initdram() reads EEPROM via I2c. EEPROM contains all of
+ dram_init() reads EEPROM via I2c. EEPROM contains all of
the necessary info for SDRAM controller configuration
*/
/* ------------------------------------------------------------------------- */
/* ------------------------------------------------------------------------- */
static int test_dram (unsigned long ramsize);
-int initdram(void)
+int dram_init(void)
{
unsigned long bank_reg[4], tmp, bank_size;
int i, ds;
#endif
/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
* is something else than 0x00000000.
*/
-int initdram(void)
+int dram_init(void)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
DECLARE_GLOBAL_DATA_PTR;
-int initdram(void)
+int dram_init(void)
{
/* Sdram is setup by assembler code */
/* If memory could be changed, we should return the true value here */
},
};
-int initdram(void)
+int dram_init(void)
{
int i;
u32 msize = 0;
#endif
/*
- * ATTENTION: Although partially referenced initdram does NOT make
+ * ATTENTION: Although partially referenced dram_init does NOT make
* real use of CONFIG_SYS_SDRAM_BASE. The code does not
* work if CONFIG_SYS_SDRAM_BASE
* is something else than 0x00000000.
*/
-int initdram(void)
+int dram_init(void)
{
volatile struct mpc5xxx_mmap_ctl *mm =
(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
DECLARE_GLOBAL_DATA_PTR;
-int initdram(void)
+int dram_init(void)
{
/* Sdram is setup by assembler code */
/* If memory could be changed, we should return the true value here */
#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
-int initdram(void)
+int dram_init(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize = 0;
return 0;
}
-int initdram(void)
+int dram_init(void)
{
long dram_size = 0;
}
/*
- * in initdram we are here executing from flash
+ * in dram_init we are here executing from flash
* case 1:
* is with no ACR/flash cache enabled
* nop = 40ns (scope measured)
asm volatile ("nop");
}
-int initdram(void)
+int dram_init(void)
{
u32 dramsize, RC;
#endif
/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
* is something else than 0x00000000.
*/
-int initdram(void)
+int dram_init(void)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
/**************************************************************************
* DRAM initalization and size detection
*/
-int initdram(void)
+int dram_init(void)
{
long bank_size;
long size;
/* ------------------------------------------------------------------------- */
-int initdram(void)
+int dram_init(void)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
#endif /* !CONFIG_SYS_RAMBOOT */
-int initdram(void)
+int dram_init(void)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
}
-int initdram(void)
+int dram_init(void)
{
phys_size_t dram_size;
return msize;
}
-int initdram(void)
+int dram_init(void)
{
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile fsl_lbc_t *lbc = &im->im_lbc;
return 0;
}
-int initdram(void)
+int dram_init(void)
{
gd->ram_size = spd_sdram();
return 0;
}
-int initdram(void)
+int dram_init(void)
{
phys_size_t dram_size = fsl_ddr_sdram();
return 0;
}
-int initdram(void)
+int dram_init(void)
{
gd->ram_size = get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
return 0;
}
-int initdram(void)
+int dram_init(void)
{
gd->ram_size = get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
return 0;
}
-#if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K)
-static int init_func_ram(void)
-{
- return initdram();
-}
-#endif
-
static int show_dram_config(void)
{
unsigned long long size;
init_func_spi,
#endif
announce_dram_init,
- /* TODO: unify all these dram functions? */
-#if defined(CONFIG_ARM) || defined(CONFIG_X86) || defined(CONFIG_NDS32) || \
- defined(CONFIG_MICROBLAZE) || defined(CONFIG_AVR32) || \
- defined(CONFIG_SH)
dram_init, /* configure available RAM banks */
-#endif
-#if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K)
- init_func_ram,
-#endif
#ifdef CONFIG_POST
post_init_f,
#endif
Disable : 15, 14
11) Create DDR's TLB entriy
- Location : Board_init_f -> init_func_ram -> initdram
+ Location : Board_init_f -> dram_init
TLB entry : Search free TLB entry
12) Update Flash's TLB entry
print_size(total_memory, " of memory\n");
printf(" This U-Boot only supports < 4G of DDR\n");
printf(" You could rebuild it with CONFIG_PHYS_64BIT\n");
- printf(" "); /* re-align to match init_func_ram print */
+ printf(" "); /* re-align to match init_dram print */
total_memory = CONFIG_MAX_MEM_MAPPED;
}
#endif
/*
* fsl_ddr_sdram(void) -- this is the main function to be
- * called by initdram() in the board file.
+ * called by dram_init() in the board file.
*
* It returns amount of memory configured in bytes.
*/
int timer_init(void);
int cpu_init(void);
-/* */
-int initdram(void);
-
#include <display_options.h>
/* common/main.c */
projects / u-boot / commitdiff