net: zynq: Change MDC setup for arm64

MDC setting depends on pclk input clocks which varies across SoC. This
driver is used by xilinx zynq and zynqmp SOC.
Input clock frequence on silicon is 125MHz where divider 64 put
frequency below 2.5MHz requires by spec (125/64=1.95).

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 97e30f3be044e0a76db6428245648d5b3251a874..b3821c31a91dc36f0cf6e7169c9ecc7bbad10c02 100644 (file)
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -57,7 +57,11 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ZYNQ_GEM_NWCFG_SPEED1000       0x000000400 /* 1Gbps operation */
 #define ZYNQ_GEM_NWCFG_FDEN            0x000000002 /* Full Duplex mode */
 #define ZYNQ_GEM_NWCFG_FSREM           0x000020000 /* FCS removal */
+#ifdef CONFIG_ARM64
+#define ZYNQ_GEM_NWCFG_MDCCLKDIV       0x000100000 /* Div pclk by 64, max 160MHz */
+#else
 #define ZYNQ_GEM_NWCFG_MDCCLKDIV       0x0000c0000 /* Div pclk by 48, max 120MHz */
+#endif
 
 #ifdef CONFIG_ARM64
 # define ZYNQ_GEM_DBUS_WIDTH   (1 << 21) /* 64 bit bus */