powerpc/p2040: Add various p2040 specific information

Add P2040 SoC specific information:
* SERDES Table
* Added p2040 to cpu_type_list and SVR list
* Added number of LAWs for p2040
* Set CONFIG_MAX_CPUS to 4 for p2040

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/arch/powerpc/cpu/mpc85xx/p2040_serdes.c b/arch/powerpc/cpu/mpc85xx/p2040_serdes.c
new file mode 100644 (file)
index 0000000..a96eff4
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/p2040_serdes.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include "fsl_corenet_serdes.h"
+
+static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
+       [0x2] = {NONE, NONE, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
+               NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
+       [0x5] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
+               NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
+       [0x8] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
+               PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, SATA1,
+               SATA2, NONE, NONE, NONE, NONE, },
+       [0xa] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
+               PCIE2, PCIE2, PCIE2, NONE, NONE, PCIE3, PCIE3, PCIE3,
+               PCIE3, NONE, NONE, NONE, NONE, },
+       [0xf] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2,
+               SRIO2, SRIO1, SRIO1, NONE, NONE, PCIE3, SGMII_FM1_DTSEC5,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
+       [0x14] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
+               PCIE2, SRIO1, SRIO1, NONE, NONE, AURORA,
+               SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE,
+               NONE, NONE, NONE, },
+       [0x16] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
+               SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE,
+               NONE, NONE, NONE, },
+       [0x1a] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2,
+               SRIO2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE,
+               NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, },
+       [0x1c] = {NONE, NONE, PCIE1, SGMII_FM1_DTSEC2, PCIE2, PCIE2,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, AURORA,
+               SGMII_FM1_DTSEC5, NONE, NONE, NONE, NONE, NONE, NONE, },
+};
+
+enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
+{
+       if (!serdes_lane_enabled(lane))
+               return NONE;
+
+       return serdes_cfg_tbl[cfg][lane];
+}

diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 94051de70d5d5c99043f636c1a43a42bb67d181f..4335fb4f31ff1c879f1f380a5e90377bb6bf6592 100644 (file)
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -84,6 +84,8 @@ struct cpu_type cpu_type_list [] = {
        CPU_TYPE_ENTRY(P2010, P2010_E, 1),
        CPU_TYPE_ENTRY(P2020, P2020, 2),
        CPU_TYPE_ENTRY(P2020, P2020_E, 2),
+       CPU_TYPE_ENTRY(P2040, P2040, 4),
+       CPU_TYPE_ENTRY(P2040, P2040_E, 4),
        CPU_TYPE_ENTRY(P3041, P3041, 4),
        CPU_TYPE_ENTRY(P3041, P3041_E, 4),
        CPU_TYPE_ENTRY(P4040, P4040, 4),

diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index 1328b9d117436824a4d9915b97b7bf25f20e3eb5..1b9c47bac10547020437b9cd7352d1a6b53da7a0 100644 (file)
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -47,6 +47,8 @@
        defined(CONFIG_P1021) || defined(CONFIG_P1022) || \
        defined(CONFIG_P2020) || defined(CONFIG_MPC8641)
 #define CONFIG_MAX_CPUS                2
+#elif defined(CONFIG_PPC_P2040)
+#define CONFIG_MAX_CPUS                4
 #elif defined(CONFIG_PPC_P3041)
 #define CONFIG_MAX_CPUS                4
 #elif defined(CONFIG_PPC_P4080)

diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 646e0db945369c2b20f6ea6222b16fb7331e794b..fcee1a2428510045e7933a410da4717ea06b309a 100644 (file)
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1058,6 +1058,8 @@
 #define SVR_P2010_E    0x80EB00
 #define SVR_P2020      0x80E200
 #define SVR_P2020_E    0x80EA00
+#define SVR_P2040      0x821000
+#define SVR_P2040_E    0x821800
 #define SVR_P3041      0x821103
 #define SVR_P3041_E    0x821903
 #define SVR_P4040      0x820100

diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c
index a30d851f3a5e2db44b0e24b9c6b2d6af7e870607..76f46880c0d4d0f88e77c956d8417dab0f53b49a 100644 (file)
--- a/drivers/misc/fsl_law.c
+++ b/drivers/misc/fsl_law.c
@@ -44,8 +44,8 @@ DECLARE_GLOBAL_DATA_PTR;
       defined(CONFIG_P1013) || defined(CONFIG_P1022) || \
       defined(CONFIG_P2010) || defined(CONFIG_P2020)
 #define FSL_HW_NUM_LAWS 12
-#elif defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P4080) || \
-      defined(CONFIG_PPC_P5020)
+#elif defined(CONFIG_PPC_P2040) || defined(CONFIG_PPC_P3041) || \
+      defined(CONFIG_PPC_P4080) || defined(CONFIG_PPC_P5020)
 #define FSL_HW_NUM_LAWS 32
 #else
 #error FSL_HW_NUM_LAWS not defined for this platform