]> git.sur5r.net Git - u-boot/commitdiff
mmc: fsl_esdhc: drop CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
authorPeng Fan <peng.fan@nxp.com>
Mon, 12 Jun 2017 09:50:55 +0000 (17:50 +0800)
committerStefano Babic <sbabic@denx.de>
Wed, 12 Jul 2017 07:44:22 +0000 (09:44 +0200)
CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT is not the correct method
to set I/O to 1.8. To boards that does not support vqmmc-supply,
use vs18_enable in fsl_esdhc_cfg. If regulator is supported,
use fixed 1.8V regulator for vqmmc-supply.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
board/warp/warp.c
doc/README.fsl-esdhc
drivers/mmc/fsl_esdhc.c
include/configs/warp.h
scripts/config_whitelist.txt

index 0bc0a6a92e66d16e639f13c54803830f2fa2c8e2..b1b528a47056d6ad00ffde4c20e0a94249681030 100644 (file)
@@ -62,7 +62,7 @@ static void setup_iomux_uart(void)
 }
 
 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
-       {USDHC2_BASE_ADDR},
+       {USDHC2_BASE_ADDR, 0, 0, 0, 1},
 };
 
 int board_mmc_getcd(struct mmc *mmc)
index 7e713875763e4a5a86e4934c7c33bb7c4b406efd..29cc6619eaba7a5caaee80709f04897a6030ceca 100644 (file)
@@ -20,5 +20,3 @@ Freescale esdhc-specific options
        - CONFIG_SYS_FSL_ESDHC_BE
                ESDHC IP is in big-endian mode. Accessing ESDHC registers can be determined
                by ESDHC IP's endian mode or processor's endian mode.
-
-       - CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT forces to run at 1.8V.
index 50ed80a4d8cbc9b80f4a4cca8c1ccd5f9c4fc3a8..3abd2d30aff89cb821645e5d79884f2cb0f85202 100644 (file)
@@ -673,10 +673,6 @@ static int esdhc_init(struct mmc *mmc)
        /* Set timout to the maximum value */
        esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
 
-#ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
-       esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
-#endif
-
        if (priv->vs18_enable)
                esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
 
index afe3eaed46d1c5f74b2ca36a159222162a76251f..e3f79b199a3a82bfb0a4b3821abba19bdb90edf0 100644 (file)
@@ -23,7 +23,6 @@
 
 /* MMC Configs */
 #define CONFIG_SYS_FSL_ESDHC_ADDR      USDHC2_BASE_ADDR
-#define CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
 #define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
 #define CONFIG_SUPPORT_EMMC_BOOT
 
index e261d02455706ee2c1c50d450aa3f4d78e23fff3..baf87996a807289a5cdf2218afc151ea61300320 100644 (file)
@@ -3208,7 +3208,6 @@ CONFIG_SYS_FSL_ERRATUM_A_004934
 CONFIG_SYS_FSL_ESDHC_ADDR
 CONFIG_SYS_FSL_ESDHC_BE
 CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
 CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
 CONFIG_SYS_FSL_ESDHC_LE
 CONFIG_SYS_FSL_ESDHC_NUM