arm, davinci: da850/dm365 lowlevel cleanup

- Cleanup a lot of fix values, and use defines instead.
- Also make some values configurable through the board config
  file.
- delete the NAND_SPL code for da850, as it is not used actually
- remove the asm code

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Wolfgang Denk <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Tom Rini <tom.rini@gmail.com>
Cc: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
index 327ff97a8714667364cf8ffa571ace3008745005..c7ec70f8ca852bc9cd490206733eb55314601e02 100644 (file)
--- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
+++ b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
@@ -29,6 +29,7 @@
 #include <asm/arch/hardware.h>
 #include <asm/arch/ddr2_defs.h>
 #include <asm/arch/emif_defs.h>
+#include <asm/arch/pll_defs.h>
 
 void da850_waitloop(unsigned long loopcnt)
 {
@@ -42,18 +43,18 @@ int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
 {
        if (reg == davinci_pllc0_regs)
                /* Unlock PLL registers. */
-               clrbits_le32(&davinci_syscfg_regs->cfgchip0, 0x00000010);
+               clrbits_le32(&davinci_syscfg_regs->cfgchip0, PLL_MASTER_LOCK);
 
        /*
         * Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled
         * through MMR
         */
-       clrbits_le32(&reg->pllctl, 0x00000020);
+       clrbits_le32(&reg->pllctl, PLLCTL_PLLENSRC);
        /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
-       clrbits_le32(&reg->pllctl, 0x00000200);
+       clrbits_le32(&reg->pllctl, PLLCTL_EXTCLKSRC);
 
        /* Set PLLEN=0 => PLL BYPASS MODE */
-       clrbits_le32(&reg->pllctl, 0x00000001);
+       clrbits_le32(&reg->pllctl, PLLCTL_PLLEN);
 
        da850_waitloop(150);
 
@@ -62,42 +63,43 @@ int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
                 * Select the Clock Mode bit 8 as External Clock or On Chip
                 * Oscilator
                 */
-               dv_maskbits(&reg->pllctl, 0xFFFFFEFF);
-               setbits_le32(&reg->pllctl, (CONFIG_SYS_DV_CLKMODE << 8));
+               dv_maskbits(&reg->pllctl, ~PLLCTL_RES_9);
+               setbits_le32(&reg->pllctl,
+                       (CONFIG_SYS_DV_CLKMODE << PLLCTL_CLOCK_MODE_SHIFT));
        }
 
        /* Clear PLLRST bit to reset the PLL */
-       clrbits_le32(&reg->pllctl, 0x00000008);
+       clrbits_le32(&reg->pllctl, PLLCTL_PLLRST);
 
        /* Disable the PLL output */
-       setbits_le32(&reg->pllctl, 0x00000010);
+       setbits_le32(&reg->pllctl, PLLCTL_PLLDIS);
 
        /* PLL initialization sequence */
        /*
         * Power up the PLL- PWRDN bit set to 0 to bring the PLL out of
         * power down bit
         */
-       clrbits_le32(&reg->pllctl, 0x00000002);
+       clrbits_le32(&reg->pllctl, PLLCTL_PLLPWRDN);
 
        /* Enable the PLL from Disable Mode PLLDIS bit to 0 */
-       clrbits_le32(&reg->pllctl, 0x00000010);
+       clrbits_le32(&reg->pllctl, PLLCTL_PLLDIS);
 
        /* Program the required multiplier value in PLLM */
        writel(pllmult, &reg->pllm);
 
        /* program the postdiv */
        if (reg == davinci_pllc0_regs)
-               writel((0x8000 | CONFIG_SYS_DA850_PLL0_POSTDIV),
+               writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL0_POSTDIV),
                        &reg->postdiv);
        else
-               writel((0x8000 | CONFIG_SYS_DA850_PLL1_POSTDIV),
+               writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL1_POSTDIV),
                        &reg->postdiv);
 
        /*
         * Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that
         * no GO operation is currently in progress
         */
-       while ((readl(&reg->pllstat) & 0x1) == 1)
+       while ((readl(&reg->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
                ;
 
        if (reg == davinci_pllc0_regs) {
@@ -118,20 +120,20 @@ int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
         * Set the GOSET bit in PLLCMD to 1 to initiate a new divider
         * transition.
         */
-       setbits_le32(&reg->pllcmd, 0x01);
+       setbits_le32(&reg->pllcmd, PLLCMD_GOSTAT);
 
        /*
         * Wait for the GOSTAT bit in PLLSTAT to clear to 0
         * (completion of phase alignment).
         */
-       while ((readl(&reg->pllstat) & 0x1) == 1)
+       while ((readl(&reg->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
                ;
 
        /* Wait for PLL to reset properly. See PLL spec for PLL reset time */
        da850_waitloop(200);
 
        /* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */
-       setbits_le32(&reg->pllctl, 0x00000008);
+       setbits_le32(&reg->pllctl, PLLCTL_PLLRST);
 
        /* Wait for PLL to lock. See PLL spec for PLL lock time */
        da850_waitloop(2400);
@@ -140,7 +142,7 @@ int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
         * Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass
         * mode
         */
-       setbits_le32(&reg->pllctl, 0x00000001);
+       setbits_le32(&reg->pllctl, PLLCTL_PLLEN);
 
 
        /*
@@ -148,12 +150,13 @@ int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
         * run off SYSCLK
         */
        if (reg == davinci_pllc0_regs)
-               dv_maskbits(&davinci_syscfg_regs->cfgchip3, 0xFFFFFFF8);
+               dv_maskbits(&davinci_syscfg_regs->cfgchip3,
+                       ~(PLL_SCSCFG3_DIV45PENA | PLL_SCSCFG3_EMA_CLKSRC));
 
        return 0;
 }
 
-int da850_ddr_setup(unsigned int freq)
+int da850_ddr_setup(void)
 {
        unsigned long   tmp;
 
@@ -197,8 +200,8 @@ int da850_ddr_setup(unsigned int freq)
         * the timing registers
         */
        tmp = CONFIG_SYS_DA850_DDR2_SDBCR;
-       tmp &= ~(0x1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT);
-       tmp |= (0x1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT);
+       tmp &= ~DV_DDR_BOOTUNLOCK;
+       tmp |= DV_DDR_TIMUNLOCK;
        writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
 
        /* write memory configuration and timing */
@@ -207,7 +210,7 @@ int da850_ddr_setup(unsigned int freq)
        writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
 
        /* clear the TIMUNLOCK bit and write the value of the CL field */
-       tmp &= ~(0x1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT);
+       tmp &= ~DV_DDR_TIMUNLOCK;
        writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
 
        /*
@@ -225,8 +228,9 @@ int da850_ddr_setup(unsigned int freq)
        lpsc_on(DAVINCI_LPSC_DDR_EMIF);
 
        /* disable self refresh */
-       clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr, 0xc0000000);
-       writel(0x30, &dv_ddr2_regs_ctrl->pbbpr);
+       clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
+               DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_LPMODEN);
+       writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
 
        return 0;
 }
@@ -244,57 +248,14 @@ void board_gpio_init(void)
        return;
 }
 
-#if defined(CONFIG_NAND_SPL)
-void nand_boot(void)
-{
-       __attribute__((noreturn)) void (*uboot)(void);
-
-       /* copy image from NOR to RAM */
-       memcpy((void *)CONFIG_SYS_NAND_U_BOOT_DST,
-               (void *)CONFIG_SYS_NAND_U_BOOT_OFFS,
-               CONFIG_SYS_NAND_U_BOOT_SIZE);
-
-       /* and jump to it ... */
-       uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
-       (*uboot)();
-}
-#endif
-
-#if defined(CONFIG_NAND_SPL)
-void board_init_f(ulong bootflag)
-#else
 int arch_cpu_init(void)
-#endif
 {
-       /*
-        * copied from arch/arm/cpu/arm926ejs/start.S
-        *
-        * flush v4 I/D caches
-        */
-       asm("mov        r0, #0");
-       asm("mcr        p15, 0, r0, c7, c7, 0");        /* flush v3/v4 cache */
-       asm("mcr        p15, 0, r0, c8, c7, 0");        /* flush v4 TLB */
-
-       /*
-        * disable MMU stuff and caches
-        */
-       asm("mrc        p15, 0, r0, c1, c0, 0");
-       /* clear bits 13, 9:8 (--V- --RS) */
-       asm("bic        r0, r0, #0x00002300");
-       /* clear bits 7, 2:0 (B--- -CAM) */
-       asm("bic        r0, r0, #0x00000087");
-       /* set bit 2 (A) Align */
-       asm("orr        r0, r0, #0x00000002");
-       /* set bit 12 (I) I-Cache */
-       asm("orr        r0, r0, #0x00001000");
-       asm("mcr        p15, 0, r0, c1, c0, 0");
-
        /* Unlock kick registers */
-       writel(0x83e70b13, &davinci_syscfg_regs->kick0);
-       writel(0x95a4f1e0, &davinci_syscfg_regs->kick1);
+       writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
+       writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
 
        dv_maskbits(&davinci_syscfg_regs->suspsrc,
-               ((1 << 27) | (1 << 22) | (1 << 20) | (1 << 5) | (1 << 16)));
+               CONFIG_SYS_DA850_SYSCFG_SUSPSRC);
 
        /* Setup Pinmux */
        da850_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX0);
@@ -326,10 +287,14 @@ int arch_cpu_init(void)
        board_gpio_init();
 
        /* setup CSn config */
+#if defined(CONFIG_SYS_DA850_CS2CFG)
        writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr);
+#endif
+#if defined(CONFIG_SYS_DA850_CS3CFG)
        writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr);
+#endif
 
-       lpsc_on(DAVINCI_LPSC_UART2);
+       lpsc_on(CONFIG_SYS_DA850_LPSC_UART);
        NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
                        CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
 
@@ -337,17 +302,10 @@ int arch_cpu_init(void)
         * Fix Power and Emulation Management Register
         * see sprufw3a.pdf page 37 Table 24
         */
-       writel(readl((CONFIG_SYS_NS16550_COM1 + 0x30)) | 0x00006001,
-               (CONFIG_SYS_NS16550_COM1 + 0x30));
-#if defined(CONFIG_NAND_SPL)
-       puts("ddr init\n");
-       da850_ddr_setup(132);
+       writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
+               DAVINCI_UART_PWREMU_MGMT_UTRST),
+              &davinci_uart2_ctrl_regs->pwremu_mgmt);
 
-       puts("boot u-boot ...\n");
-
-       nand_boot();
-#else
-       da850_ddr_setup(132);
+       da850_ddr_setup();
        return 0;
-#endif
 }

diff --git a/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c
index 3772e64cc4f23fa44ec993960f947c6bff15584f..6e998ded99e7cf7609d2a841f178b81d4cf723a4 100644 (file)
--- a/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c
+++ b/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c
@@ -45,7 +45,8 @@ int dm365_pll1_init(unsigned long pllmult, unsigned long prediv)
        clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLPWRDN);
 
        clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9);
-       setbits_le32(&dv_pll0_regs->pllctl, clksrc << 8);
+       setbits_le32(&dv_pll0_regs->pllctl,
+               clksrc << PLLCTL_CLOCK_MODE_SHIFT);
 
        /*
         * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
@@ -82,7 +83,7 @@ int dm365_pll1_init(unsigned long pllmult, unsigned long prediv)
        writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
 
        /* Program the PostDiv for PLL1 */
-       writel(0x8000, &dv_pll0_regs->postdiv);
+       writel(PLL_POSTDEN, &dv_pll0_regs->postdiv);
 
        /* Post divider setting for PLL1 */
        writel(CONFIG_SYS_DM36x_PLL1_PLLDIV1, &dv_pll0_regs->plldiv1);
@@ -126,7 +127,8 @@ int dm365_pll2_init(unsigned long pllm, unsigned long prediv)
         * VDB has input on MXI pin
         */
        clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_RES_9);
-       setbits_le32(&dv_pll1_regs->pllctl, clksrc << 8);
+       setbits_le32(&dv_pll1_regs->pllctl,
+               clksrc << PLLCTL_CLOCK_MODE_SHIFT);
 
        /*
         * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
@@ -151,7 +153,7 @@ int dm365_pll2_init(unsigned long pllm, unsigned long prediv)
        writel(pllm, &dv_pll1_regs->pllm);
        writel(prediv, &dv_pll1_regs->prediv);
 
-       writel(0x8000, &dv_pll1_regs->postdiv);
+       writel(PLL_POSTDEN, &dv_pll1_regs->postdiv);
 
        /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
        writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
@@ -261,21 +263,23 @@ void dm365_vpss_sync_reset(void)
                VPSS_CLK_CTL_VPSS_CLKMD);
 
        /* LPSC SyncReset DDR Clock Enable */
-       writel(((readl(&dv_psc_regs->mdctl[47]) & ~PSC_MD_STATE_MSK) |
-               PSC_SYNCRESET), &dv_psc_regs->mdctl[47]);
+       writel(((readl(&dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]) &
+               ~PSC_MD_STATE_MSK) | PSC_SYNCRESET),
+               &dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]);
 
        writel((1 << PdNum), &dv_psc_regs->ptcmd);
 
        while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT) == 0))
                ;
-       while (!((readl(&dv_psc_regs->mdstat[47]) &  PSC_MD_STATE_MSK) ==
-               PSC_SYNCRESET))
+       while (!((readl(&dv_psc_regs->mdstat[DAVINCI_LPSC_VPSSMASTER]) &
+               PSC_MD_STATE_MSK) == PSC_SYNCRESET))
                ;
 }
 
 void dm365_por_reset(void)
 {
-       if (readl(&dv_pll0_regs->rstype) & 3)
+       if (readl(&dv_pll0_regs->rstype) &
+               (PLL_RSTYPE_POR | PLL_RSTYPE_XWRST))
                dm365_vpss_sync_reset();
 }
 
@@ -291,19 +295,20 @@ void dm365_psc_init(void)
 
        for (lpscgroup = lpscmin; lpscgroup <= lpscmax; lpscgroup++) {
                if (lpscgroup == 0) {
-                       lpsc_start = 0; /* Enabling LPSC 3 to 28 SCR first */
-                       lpsc_end   = 28;
+                       /* Enabling LPSC 3 to 28 SCR first */
+                       lpsc_start = DAVINCI_LPSC_VPSSMSTR;
+                       lpsc_end   = DAVINCI_LPSC_TIMER1;
                } else if (lpscgroup == 1) { /* Skip locked LPSCs [29-37] */
-                       lpsc_start = 38;
-                       lpsc_end   = 47;
+                       lpsc_start = DAVINCI_LPSC_CFG5;
+                       lpsc_end   = DAVINCI_LPSC_VPSSMASTER;
                } else {
-                       lpsc_start = 50;
-                       lpsc_end   = 51;
+                       lpsc_start = DAVINCI_LPSC_MJCP;
+                       lpsc_end   = DAVINCI_LPSC_HDVICP;
                }
 
                /* NEXT=0x3, Enable LPSC's */
                for (i = lpsc_start; i <= lpsc_end; i++)
-                       setbits_le32(&dv_psc_regs->mdctl[i], 0x3);
+                       setbits_le32(&dv_psc_regs->mdctl[i], PSC_ENABLE);
 
                /*
                 * Program goctl to start transition sequence for LPSCs
@@ -322,7 +327,7 @@ void dm365_psc_init(void)
                /* Wait for MODSTAT = ENABLE from LPSC's */
                for (i = lpsc_start; i <= lpsc_end; i++)
                        while (!((readl(&dv_psc_regs->mdstat[i]) &
-                               PSC_MD_STATE_MSK) == 0x3))
+                               PSC_MD_STATE_MSK) == PSC_ENABLE))
                                ;
        }
 }
@@ -332,7 +337,7 @@ static void dm365_emif_init(void)
        writel(CONFIG_SYS_DM36x_AWCCR, &davinci_emif_regs->awccr);
        writel(CONFIG_SYS_DM36x_AB1CR, &davinci_emif_regs->ab1cr);
 
-       setbits_le32(&davinci_emif_regs->nandfcr, 1);
+       setbits_le32(&davinci_emif_regs->nandfcr, DAVINCI_NANDFCR_CS2NAND);
 
        writel(CONFIG_SYS_DM36x_AB2CR, &davinci_emif_regs->ab2cr);
 
@@ -361,31 +366,12 @@ int post_log(char *format, ...)
 
 void dm36x_lowlevel_init(ulong bootflag)
 {
-       /*
-        * copied from arch/arm/cpu/arm926ejs/start.S
-        *
-        * flush v4 I/D caches
-        */
-       asm("mov        r0, #0");
-       asm("mcr        p15, 0, r0, c7, c7, 0");        /* flush v3/v4 cache */
-       asm("mcr        p15, 0, r0, c8, c7, 0");        /* flush v4 TLB */
-
-       /*
-        * disable MMU stuff and caches
-        */
-       asm("mrc        p15, 0, r0, c1, c0, 0");
-       /* clear bits 13, 9:8 (--V- --RS) */
-       asm("bic        r0, r0, #0x00002300");
-       /* clear bits 7, 2:0 (B--- -CAM) */
-       asm("bic        r0, r0, #0x00000087");
-       /* set bit 2 (A) Align */
-       asm("orr        r0, r0, #0x00000002");
-       /* set bit 12 (I) I-Cache */
-       asm("orr        r0, r0, #0x00001000");
-       asm("mcr        p15, 0, r0, c1, c0, 0");
+       struct davinci_uart_ctrl_regs *davinci_uart_ctrl_regs =
+               (struct davinci_uart_ctrl_regs *)(CONFIG_SYS_NS16550_COM1 +
+               DAVINCI_UART_CTRL_BASE);
 
        /* Mask all interrupts */
-       writel(0x04, &dv_aintc_regs->intctl);
+       writel(DV_AINTC_INTCTL_IDMODE, &dv_aintc_regs->intctl);
        writel(0x0, &dv_aintc_regs->eabase);
        writel(0x0, &dv_aintc_regs->eint0);
        writel(0x0, &dv_aintc_regs->eint1);
@@ -422,7 +408,10 @@ void dm36x_lowlevel_init(ulong bootflag)
         * Fix Power and Emulation Management Register
         * see sprufh2.pdf page 38 Table 22
         */
-       writel(0x0000e003, (CONFIG_SYS_NS16550_COM1 + 0x30));
+       writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
+               DAVINCI_UART_PWREMU_MGMT_UTRST),
+              &davinci_uart_ctrl_regs->pwremu_mgmt);
+
        puts("ddr init\n");
        dm365_ddr_setup();
 

diff --git a/arch/arm/include/asm/arch-davinci/aintc_defs.h b/arch/arm/include/asm/arch-davinci/aintc_defs.h
index 8f3705320916ef8d8921a57e25629b5321a081cd..38f814c0185bc9f1a6c1d408a874bd17bfc732cb 100644 (file)
--- a/arch/arm/include/asm/arch-davinci/aintc_defs.h
+++ b/arch/arm/include/asm/arch-davinci/aintc_defs.h
@@ -47,4 +47,6 @@ struct dv_aintc_regs {
 
 #define dv_aintc_regs ((struct dv_aintc_regs *)DAVINCI_ARM_INTC_BASE)
 
+#define DV_AINTC_INTCTL_IDMODE (1 << 2)
+
 #endif /* _DV_AINTC_DEFS_H_ */

diff --git a/arch/arm/include/asm/arch-davinci/da850_lowlevel.h b/arch/arm/include/asm/arch-davinci/da850_lowlevel.h
index 22a92a3fa67a5e1f31c12a49b21883fbbbbd1607..e489c474754cd581c65921b4f1aaa26f7669fc8c 100644 (file)
--- a/arch/arm/include/asm/arch-davinci/da850_lowlevel.h
+++ b/arch/arm/include/asm/arch-davinci/da850_lowlevel.h
@@ -36,7 +36,7 @@ void da850_waitloop(unsigned long loopcnt);
 int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult);
 void da850_lpc_transition(unsigned char pscnum, unsigned char module,
                unsigned char domain, unsigned char state);
-int da850_ddr_setup(unsigned int freq);
+int da850_ddr_setup(void);
 void da850_psc_init(void);
 void da850_pinmux_ctl(unsigned long offset, unsigned long mask,
        unsigned long value);

diff --git a/arch/arm/include/asm/arch-davinci/ddr2_defs.h b/arch/arm/include/asm/arch-davinci/ddr2_defs.h
index 1b9430ce6b3038fc627d91a819eaf86b47be57b8..4f943b81b36d4a7b1f46c3bfaf60a67d36600151 100644 (file)
--- a/arch/arm/include/asm/arch-davinci/ddr2_defs.h
+++ b/arch/arm/include/asm/arch-davinci/ddr2_defs.h
@@ -63,6 +63,7 @@ struct dv_ddr2_regs_ctrl {
 
 #define DV_DDR_SDTMR2_RASMAX_SHIFT     27
 #define DV_DDR_SDTMR2_XP_SHIFT 25
+#define DV_DDR_SDTMR2_ODT_SHIFT        23
 #define DV_DDR_SDTMR2_XSNR_SHIFT       16
 #define DV_DDR_SDTMR2_XSRD_SHIFT       8
 #define DV_DDR_SDTMR2_RTP_SHIFT        5
@@ -84,6 +85,9 @@ struct dv_ddr2_regs_ctrl {
 #define DV_DDR_SDCR_IBANK_SHIFT        4
 #define DV_DDR_SDCR_PAGESIZE_SHIFT     0
 
+#define DV_DDR_SDRCR_LPMODEN   (1 << 31)
+#define DV_DDR_SDRCR_MCLKSTOPEN        (1 << 30)
+
 #define DV_DDR_SRCR_LPMODEN_SHIFT      31
 #define DV_DDR_SRCR_MCLKSTOPEN_SHIFT   30
 

diff --git a/arch/arm/include/asm/arch-davinci/emif_defs.h b/arch/arm/include/asm/arch-davinci/emif_defs.h
index b48ec17e9755e7583d1b9384cda57efcdedf552d..b9e78a5dbdc5f15b4cc7709be8cdf068a704e02e 100644 (file)
--- a/arch/arm/include/asm/arch-davinci/emif_defs.h
+++ b/arch/arm/include/asm/arch-davinci/emif_defs.h
@@ -70,6 +70,7 @@ struct davinci_emif_regs {
 #define DAVINCI_NANDFCR_1BIT_ECC_START(n)              (1 << (8 + (n-2)))
 #define DAVINCI_NANDFCR_4BIT_ECC_START                 (1 << 12)
 #define DAVINCI_NANDFCR_4BIT_CALC_START                        (1 << 13)
+#define DAVINCI_NANDFCR_CS2NAND                                (1 << 0)
 
 /* Chip Select setup */
 #define DAVINCI_ABCR_STROBE_SELECT                     (1 << 31)

diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index ee8fd43c1dca7fa429657bb6d95c3f04883085c1..f80f31244794f5d7919137dd47819a4ca72b8a29 100644 (file)
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -230,6 +230,9 @@ typedef volatile unsigned int *     dv_reg_p;
 #define DAVINCI_LPSC_CFG5              38
 #define DAVINCI_LPSC_GEM               39
 #define DAVINCI_LPSC_IMCOP             40
+#define DAVINCI_LPSC_VPSSMASTER                47
+#define DAVINCI_LPSC_MJCP              50
+#define DAVINCI_LPSC_HDVICP            51
 
 #define DAVINCI_DM646X_LPSC_EMAC       14
 #define DAVINCI_DM646X_LPSC_UART0      26
@@ -385,6 +388,20 @@ struct davinci_psc_regs {
 #define PINMUX3                                0x01c4000c
 #define PINMUX4                                0x01c40010
 
+struct davinci_uart_ctrl_regs {
+       dv_reg  revid1;
+       dv_reg  res;
+       dv_reg  pwremu_mgmt;
+       dv_reg  mdr;
+};
+
+#define DAVINCI_UART_CTRL_BASE 0x28
+
+/* UART PWREMU_MGMT definitions */
+#define DAVINCI_UART_PWREMU_MGMT_FREE  (1 << 0)
+#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13)
+#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14)
+
 #else /* CONFIG_SOC_DA8XX */
 
 struct davinci_pllc_regs {
@@ -492,6 +509,9 @@ struct davinci_syscfg1_regs {
 #define VTP_READY              (1 << 15)
 #define VTP_IOPWRDWN           (1 << 14)
 
+#define DV_SYSCFG_KICK0_UNLOCK 0x83e70b13
+#define DV_SYSCFG_KICK1_UNLOCK 0x95a4f1e0
+
 /* Interrupt controller */
 struct davinci_aintc_regs {
        dv_reg  revid;

diff --git a/arch/arm/include/asm/arch-davinci/pll_defs.h b/arch/arm/include/asm/arch-davinci/pll_defs.h
index 5c309533a2797e24492e4916a6930f3e0d88070b..f1396e31942430e8cf9348620993d8d69b5a1bdb 100644 (file)
--- a/arch/arm/include/asm/arch-davinci/pll_defs.h
+++ b/arch/arm/include/asm/arch-davinci/pll_defs.h
@@ -57,11 +57,24 @@ struct dv_pll_regs {
        unsigned int    plldiv9;        /* 0x174 */
 };
 
+#define PLL_MASTER_LOCK        (1 << 4)
+
+#define PLLCTL_CLOCK_MODE_SHIFT        8
 #define PLLCTL_PLLEN   (1 << 0)
 #define PLLCTL_PLLPWRDN        (1 << 1)
 #define PLLCTL_PLLRST  (1 << 3)
+#define PLLCTL_PLLDIS  (1 << 4)
 #define PLLCTL_PLLENSRC        (1 << 5)
 #define PLLCTL_RES_9   (1 << 8)
+#define PLLCTL_EXTCLKSRC       (1 << 9)
+
+#define PLL_POSTDEN    (1 << 15)
+
+#define PLL_SCSCFG3_DIV45PENA  (1 << 2)
+#define PLL_SCSCFG3_EMA_CLKSRC (1 << 1)
+
+#define PLL_RSTYPE_POR         (1 << 0)
+#define PLL_RSTYPE_XWRST       (1 << 1)
 
 #define PLLSECCTL_TINITZ       (1 << 16)
 #define PLLSECCTL_TENABLE      (1 << 17)
@@ -69,6 +82,7 @@ struct dv_pll_regs {
 #define PLLSECCTL_STOPMODE     (1 << 22)
 
 #define PLLCMD_GOSET           (1 << 0)
+#define PLLCMD_GOSTAT          (1 << 0)
 
 #define PLL0_LOCK              0x07000000
 #define PLL1_LOCK              0x07000000