]> git.sur5r.net Git - u-boot/commitdiff
dm: Init device tree as well as driver model in SPL
authorSimon Glass <sjg@chromium.org>
Sat, 28 Feb 2015 05:06:42 +0000 (22:06 -0700)
committerSimon Glass <sjg@chromium.org>
Thu, 23 Apr 2015 15:05:55 +0000 (09:05 -0600)
If enabled, make sure that the device tree is available in SPL before
setting up driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
common/spl/spl.c

index af1336ce100014b2da4a153a5413c491dad68b96..6a02c9ed96a3f167646e4175c31a2c24b180ce90 100644 (file)
@@ -151,6 +151,8 @@ static void spl_ram_load_image(void)
 void board_init_r(gd_t *dummy1, ulong dummy2)
 {
        u32 boot_device;
+       int ret;
+
        debug(">>spl:board_init_r()\n");
 
 #if defined(CONFIG_SYS_SPL_MALLOC_START)
@@ -161,9 +163,21 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
        gd->malloc_limit = CONFIG_SYS_MALLOC_F_LEN;
        gd->malloc_ptr = 0;
 #endif
-#ifdef CONFIG_SPL_DM
-       dm_init_and_scan(true);
-#endif
+       if (IS_ENABLED(CONFIG_OF_CONTROL) &&
+                       !IS_ENABLED(CONFIG_SPL_DISABLE_OF_CONTROL)) {
+               ret = fdtdec_setup();
+               if (ret) {
+                       debug("fdtdec_setup() returned error %d\n", ret);
+                       hang();
+               }
+       }
+       if (IS_ENABLED(CONFIG_SPL_DM)) {
+               ret = dm_init_and_scan(true);
+               if (ret) {
+                       debug("dm_init_and_scan() returned error %d\n", ret);
+                       hang();
+               }
+       }
 
 #ifndef CONFIG_PPC
        /*