CONFIG_BOOTP_HOSTNAME=y
CONFIG_BOOTP_SUBNETMASK=y
CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_SPARTAN3=y
CONFIG_MXC_GPIO=y
CONFIG_MMC_MXC=y
CONFIG_NAND=y
CONFIG_FPGA_ALTERA=y
CONFIG_FPGA_CYCLON2=y
CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_SPARTAN3=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTP_DNS=y
CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_SPARTAN3=y
CONFIG_SYS_OMAP24_I2C_SPEED=400000
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_BOOTCOUNT_ADDR=0xD2801FF8
CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_SPARTAN3=y
CONFIG_SYS_I2C_DW=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
Enable FPGA driver for loading bitstream in BIT and BIN format
on Xilinx Zynq UltraScale+ (ZynqMP) device.
+config FPGA_SPARTAN3
+ bool "Enable Spartan3 FPGA driver"
+ help
+ Enable Spartan3 FPGA driver for loading in BIT format.
+
endmenu
* FPGA
*/
#define CONFIG_FPGA_COUNT 1
-#define CONFIG_FPGA_SPARTAN3
#define CONFIG_SYS_FPGA_WAIT 250 /* 250 ms */
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_SYS_FPGA_CHECK_CTRLC
#define CONFIG_SYS_LOAD_ADDR 0x20000
#define CONFIG_FPGA_COUNT 1
-#define CONFIG_FPGA_SPARTAN3
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_SYS_FPGA_WAIT 1000
/*
* FPGA
*/
-#define CONFIG_FPGA_SPARTAN3
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_SYS_FPGA_WAIT 10000
#define CONFIG_MAX_FPGA_DEVICES 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
/* FPGA config options */
-#define CONFIG_FPGA_SPARTAN3
#define CONFIG_FPGA_COUNT 1
/* USB EHCI options */