/* Register access macros */
#define sm_readl(reg) \
- readl((void *)SM_BASE + SM_##reg)
+ readl((void *)ATMEL_BASE_SM + SM_##reg)
#define sm_writel(reg,value) \
- writel((value), (void *)SM_BASE + SM_##reg)
+ writel((value), (void *)ATMEL_BASE_SM + SM_##reg)
#endif /* __CPU_AT32AP_SM_H__ */
/* Register access macros */
#define hsdramc1_readl(reg) \
- readl((void *)HSDRAMC_BASE + HSDRAMC1_##reg)
+ readl((void *)ATMEL_BASE_HSDRAMC + HSDRAMC1_##reg)
#define hsdramc1_writel(reg,value) \
- writel((value), (void *)HSDRAMC_BASE + HSDRAMC1_##reg)
+ writel((value), (void *)ATMEL_BASE_HSDRAMC + HSDRAMC1_##reg)
#endif /* __ASM_AVR32_HSDRAMC1_H__ */
/* Register access macros */
#define hsmc3_readl(reg) \
- readl((void *)HSMC_BASE + HSMC3_##reg)
+ readl((void *)ATMEL_BASE_HSMC + HSMC3_##reg)
#define hsmc3_writel(reg,value) \
- writel((value), (void *)HSMC_BASE + HSMC3_##reg)
+ writel((value), (void *)ATMEL_BASE_HSMC + HSMC3_##reg)
#endif /* __CPU_AT32AP_HSMC3_H__ */
intpr = (handler_addr & HANDLER_MASK);
intpr |= (priority & INTLEV_MASK) << INTLEV_SHIFT;
- writel(intpr, (void *)INTC_BASE + 4 * nr);
+ writel(intpr, (void *)ATMEL_BASE_INTC + 4 * nr);
return 0;
}
{
switch (pin >> 5) {
case 0:
- return (void *)PIOA_BASE;
+ return (void *)ATMEL_BASE_PIOA;
case 1:
- return (void *)PIOB_BASE;
+ return (void *)ATMEL_BASE_PIOB;
case 2:
- return (void *)PIOC_BASE;
+ return (void *)ATMEL_BASE_PIOC;
case 3:
- return (void *)PIOD_BASE;
+ return (void *)ATMEL_BASE_PIOD;
case 4:
- return (void *)PIOE_BASE;
+ return (void *)ATMEL_BASE_PIOE;
default:
return NULL;
}
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-#ifndef __AT32AP7000_MEMORY_MAP_H__
-#define __AT32AP7000_MEMORY_MAP_H__
+#ifndef __AT32AP7000_HARDWARE_H__
+#define __AT32AP7000_HARDWARE_H__
/* Internal and external memories */
#define EBI_SRAM_CS0_BASE 0x00000000
#define INTERNAL_SRAM_SIZE 0x00008000
/* Devices on the High Speed Bus (HSB) */
-#define LCDC_BASE 0xFF000000
-#define DMAC_BASE 0xFF200000
-#define USB_FIFO 0xFF300000
+#define LCDC_BASE 0xFF000000
+#define DMAC_BASE 0xFF200000
+#define USB_FIFO 0xFF300000
/* Devices on Peripheral Bus A (PBA) */
-#define SPI0_BASE 0xFFE00000
-#define SPI1_BASE 0xFFE00400
-#define TWI_BASE 0xFFE00800
-#define USART0_BASE 0xFFE00C00
-#define USART1_BASE 0xFFE01000
-#define USART2_BASE 0xFFE01400
-#define USART3_BASE 0xFFE01800
-#define SSC0_BASE 0xFFE01C00
-#define SSC1_BASE 0xFFE02000
-#define SSC2_BASE 0xFFE02400
-#define PIOA_BASE 0xFFE02800
-#define PIOB_BASE 0xFFE02C00
-#define PIOC_BASE 0xFFE03000
-#define PIOD_BASE 0xFFE03400
-#define PIOE_BASE 0xFFE03800
-#define PSIF_BASE 0xFFE03C00
+#define ATMEL_BASE_SPI0 0xFFE00000
+#define ATMEL_BASE_SPI1 0xFFE00400
+#define ATMEL_BASE_TWI0 0xFFE00800
+#define ATMEL_BASE_USART0 0xFFE00C00
+#define ATMEL_BASE_USART1 0xFFE01000
+#define ATMEL_BASE_USART2 0xFFE01400
+#define ATMEL_BASE_USART3 0xFFE01800
+#define ATMEL_BASE_SSC0 0xFFE01C00
+#define ATMEL_BASE_SSC1 0xFFE02000
+#define ATMEL_BASE_SSC2 0xFFE02400
+#define ATMEL_BASE_PIOA 0xFFE02800
+#define ATMEL_BASE_PIOB 0xFFE02C00
+#define ATMEL_BASE_PIOC 0xFFE03000
+#define ATMEL_BASE_PIOD 0xFFE03400
+#define ATMEL_BASE_PIOE 0xFFE03800
+#define ATMEL_BASE_PSIF 0xFFE03C00
/* Devices on Peripheral Bus B (PBB) */
-#define SM_BASE 0xFFF00000
-#define INTC_BASE 0xFFF00400
-#define HMATRIX_BASE 0xFFF00800
-#define TIMER0_BASE 0xFFF00C00
-#define TIMER1_BASE 0xFFF01000
-#define PWM_BASE 0xFFF01400
-#define MACB0_BASE 0xFFF01800
-#define MACB1_BASE 0xFFF01C00
-#define DAC_BASE 0xFFF02000
-#define MMCI_BASE 0xFFF02400
-#define AUDIOC_BASE 0xFFF02800
-#define HISI_BASE 0xFFF02C00
-#define USB_BASE 0xFFF03000
-#define HSMC_BASE 0xFFF03400
-#define HSDRAMC_BASE 0xFFF03800
-#define ECC_BASE 0xFFF03C00
+#define ATMEL_BASE_SM 0xFFF00000
+#define ATMEL_BASE_INTC 0xFFF00400
+#define ATMEL_BASE_HMATRIX 0xFFF00800
+#define ATMEL_BASE_TIMER0 0xFFF00C00
+#define ATMEL_BASE_TIMER1 0xFFF01000
+#define ATMEL_BASE_PWM 0xFFF01400
+#define ATMEL_BASE_MACB0 0xFFF01800
+#define ATMEL_BASE_MACB1 0xFFF01C00
+#define ATMEL_BASE_DAC 0xFFF02000
+#define ATMEL_BASE_MMCI 0xFFF02400
+#define ATMEL_BASE_AUDIOC 0xFFF02800
+#define ATMEL_BASE_HISI 0xFFF02C00
+#define ATMEL_BASE_USB 0xFFF03000
+#define ATMEL_BASE_HSMC 0xFFF03400
+#define ATMEL_BASE_HSDRAMC 0xFFF03800
+#define ATMEL_BASE_ECC 0xFFF03C00
-#endif /* __AT32AP7000_MEMORY_MAP_H__ */
+#endif /* __AT32AP7000_HARDWARE_H__ */
#include <asm/arch/gpio.h>
-#define PORTMUX_PORT_A ((void *)PIOA_BASE)
-#define PORTMUX_PORT_B ((void *)PIOB_BASE)
-#define PORTMUX_PORT_C ((void *)PIOC_BASE)
-#define PORTMUX_PORT_D ((void *)PIOD_BASE)
-#define PORTMUX_PORT_E ((void *)PIOE_BASE)
+#define PORTMUX_PORT_A ((void *)ATMEL_BASE_PIOA)
+#define PORTMUX_PORT_B ((void *)ATMEL_BASE_PIOB)
+#define PORTMUX_PORT_C ((void *)ATMEL_BASE_PIOC)
+#define PORTMUX_PORT_D ((void *)ATMEL_BASE_PIOD)
+#define PORTMUX_PORT_E ((void *)ATMEL_BASE_PIOE)
void portmux_enable_ebi(unsigned int bus_width, unsigned int addr_width,
unsigned long flags, unsigned long drive_strength);
/* Register access macros */
#define __hmatrix_reg(reg) \
- (((volatile struct hmatrix_regs *)HMATRIX_BASE)->reg)
+ (((volatile struct hmatrix_regs *)ATMEL_BASE_HMATRIX)->reg)
#define hmatrix_read(reg) \
(__hmatrix_reg(reg))
#define hmatrix_write(reg, value) \
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bi)
{
- macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]);
- macb_eth_initialize(1, (void *)MACB1_BASE, bi->bi_phy_id[1]);
+ macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
+ macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
return 0;
}
#endif
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bi)
{
- macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]);
- macb_eth_initialize(1, (void *)MACB1_BASE, bi->bi_phy_id[1]);
+ macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
+ macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
return 0;
}
#endif
#if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET)
int board_eth_init(bd_t *bi)
{
- return macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]);
+ return macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0,
+ bi->bi_phy_id[0]);
}
#endif
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bi)
{
- macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]);
- macb_eth_initialize(1, (void *)MACB1_BASE, bi->bi_phy_id[1]);
+ macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
+ macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
return 0;
}
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
- return macb_eth_initialize(0, (void *)MACB0_BASE, bis->bi_phy_id[0]);
+ return macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0,
+ bis->bi_phy_id[0]);
}
#endif
* Register access macros
*/
#define mmci_readl(reg) \
- readl((void *)MMCI_BASE + MMCI_##reg)
+ readl((void *)ATMEL_BASE_MMCI + MMCI_##reg)
#define mmci_writel(reg,value) \
- writel((value), (void *)MMCI_BASE + MMCI_##reg)
+ writel((value), (void *)ATMEL_BASE_MMCI + MMCI_##reg)
#endif /* __CPU_AT32AP_ATMEL_MCI_H__ */
*/
#define CONFIG_SYS_PLL0_OPT 0x04
-#define CONFIG_USART1 1
-
+#define CONFIG_USART_BASE ATMEL_BASE_USART1
+#define CONFIG_USART_ID 1
/* User serviceable stuff */
#define CONFIG_DOS_PARTITION 1
*/
#define CONFIG_SYS_PLL0_OPT 0x04
-#undef CONFIG_USART0
-#define CONFIG_USART1 1
-#undef CONFIG_USART2
-#undef CONFIG_USART3
+#define CONFIG_USART_BASE ATMEL_BASE_USART1
+#define CONFIG_USART_ID 1
/* User serviceable stuff */
#define CONFIG_DOS_PARTITION 1
*/
#define CONFIG_SYS_PLL0_OPT 0x04
-#undef CONFIG_USART0
-#define CONFIG_USART1 1
-#undef CONFIG_USART2
-#undef CONFIG_USART3
+#define CONFIG_USART_BASE ATMEL_BASE_USART1
+#define CONFIG_USART_ID 1
/* User serviceable stuff */
#define CONFIG_DOS_PARTITION 1
*/
#define CONFIG_SYS_PLL0_OPT 0x04
-#undef CONFIG_USART0
-#define CONFIG_USART1 1
-#undef CONFIG_USART2
-#undef CONFIG_USART3
+#define CONFIG_USART_BASE ATMEL_BASE_USART1
+#define CONFIG_USART_ID 1
/* User serviceable stuff */
#define CONFIG_DOS_PARTITION 1
*/
#define CONFIG_SYS_PLL0_OPT 0x04
-#undef CONFIG_USART0
-#define CONFIG_USART1 1
-#undef CONFIG_USART2
-#undef CONFIG_USART3
+#define CONFIG_USART_BASE ATMEL_BASE_USART1
+#define CONFIG_USART_ID 1
/* User serviceable stuff */
#define CONFIG_DOS_PARTITION 1
*/
#define CONFIG_SYS_PLL0_OPT 0x04
-#undef CONFIG_USART0
-#undef CONFIG_USART1
-#undef CONFIG_USART2
-#define CONFIG_USART3 1
+#define CONFIG_USART_BASE ATMEL_BASE_USART3
+#define CONFIG_USART_ID 3
/* User serviceable stuff */
#define CONFIG_DOS_PARTITION 1
*/
#define CONFIG_SYS_PLL0_OPT 0x04
-#define CONFIG_USART1 1
+#define CONFIG_USART_BASE ATMEL_BASE_USART1
+#define CONFIG_USART_ID 1
#define CONFIG_HOSTNAME hammerhead
*/
#define CONFIG_SYS_PLL0_OPT 0x04
-#define CONFIG_USART1 1
+#define CONFIG_USART_BASE ATMEL_BASE_USART1
+#define CONFIG_USART_ID 1
+
#define CONFIG_MIMC200_DBGLINK 1
/* User serviceable stuff */