]> git.sur5r.net Git - u-boot/commitdiff
omap3:clock: configure GFX clock to 200MHz for AM/DM37x
authorVaibhav Hiremath <hvaibhav@ti.com>
Sun, 4 Sep 2011 01:29:59 +0000 (21:29 -0400)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Sun, 4 Sep 2011 09:36:17 +0000 (11:36 +0200)
AM/DM37x is another OMAP3 variant, where the GFX clock has been
boosted to 192MHz/200MHz. So fix the GFX_DIV value for this change.

HW Errata: Due to dependency of TV out clock of 54MHz, it is not
possible to configure GFX to 192MHz. So as per HW errats, the
recommended GFX clock is 200MHz (=CORE_CLK/2).

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
arch/arm/cpu/armv7/omap3/clock.c
arch/arm/include/asm/arch-omap3/clocks_omap3.h

index 3d38d08ccbfee81062c442a65deb1dd3af0c1f5d..29ff7131de1972144901663500755700daf36788 100644 (file)
@@ -399,7 +399,7 @@ static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
                /* L3 */
                sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
                /* GFX */
-               sr32(&prcm_base->clksel_gfx,  0, 3, GFX_DIV);
+               sr32(&prcm_base->clksel_gfx,  0, 3, GFX_DIV_36X);
                /* RESET MGR */
                sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
                /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
index ef600dd9db868aa651001067a3e39a25e75c4131..db29b7c6df55e9cb9b901cae185f0be87a166cad 100644 (file)
@@ -39,6 +39,7 @@
 #define CORE_L4_DIV    2       /* 83MHz  : L4 */
 #define CORE_L3_DIV    2       /* 166MHz : L3 {DDR} */
 #define GFX_DIV                2       /* 83MHz  : CM_CLKSEL_GFX */
+#define GFX_DIV_36X    5       /* 200MHz : CM_CLKSEL_GFX */
 #define WKUP_RSM       2       /* 41.5MHz: CM_CLKSEL_WKUP */
 
 /* PER DPLL */