]> git.sur5r.net Git - u-boot/commitdiff
arm: Move SYS_FSL_SRDS_* and SYS_HAS_SERDES to Kconfig
authorYork Sun <york.sun@nxp.com>
Wed, 5 Oct 2016 01:01:34 +0000 (18:01 -0700)
committerYork Sun <york.sun@nxp.com>
Thu, 6 Oct 2016 16:59:11 +0000 (09:59 -0700)
Move these options to Kconfig and clean up existing uses.

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
12 files changed:
arch/arm/cpu/armv7/ls102xa/Kconfig
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
arch/arm/include/asm/arch-fsl-layerscape/config.h
arch/arm/include/asm/arch-ls102xa/config.h
include/configs/ls1012a_common.h
include/configs/ls1021aqds.h
include/configs/ls1021atwr.h
include/configs/ls1043a_common.h
include/configs/ls1043aqds.h
include/configs/ls1046a_common.h
include/configs/ls1046aqds.h
include/configs/ls2080a_common.h

index 88983f4c181d1e6a6347e3e78fbe388eb4da3914..17f19758a6948d01045f66c4d899ade6362460f5 100644 (file)
@@ -1,6 +1,8 @@
 config ARCH_LS1021A
        bool
        select SYS_FSL_ERRATUM_A010315
+       select SYS_FSL_SRDS_1
+       select SYS_HAS_SERDES
 
 menu "LS102xA architecture"
        depends on ARCH_LS1021A
@@ -23,6 +25,15 @@ config MAX_CPUS
 config SYS_FSL_ERRATUM_A010315
        bool "Workaround for PCIe erratum A010315"
 
+config SYS_FSL_SRDS_1
+       bool
+
+config SYS_FSL_SRDS_2
+       bool
+
+config SYS_HAS_SERDES
+       bool
+
 config SYS_FSL_IFC_BANK_COUNT
        int "Maximum banks of Integrated flash controller"
        depends on ARCH_LS1021A
index 7aae39727ef1eee4f5914a3bab154e1bf14d9821..28589aea8f1cb5b3f274ac5f8cb0b387a4c8e8c1 100644 (file)
@@ -14,16 +14,23 @@ config ARCH_LS1046A
        bool
        select FSL_LSCH2
        select SYS_FSL_ERRATUM_A010539
+       select SYS_FSL_SRDS_2
 
 config ARCH_LS2080A
        bool
        select FSL_LSCH3
+       select SYS_FSL_HAS_DP_DDR
+       select SYS_FSL_SRDS_2
 
 config FSL_LSCH2
        bool
+       select SYS_FSL_SRDS_1
+       select SYS_HAS_SERDES
 
 config FSL_LSCH3
        bool
+       select SYS_FSL_SRDS_1
+       select SYS_HAS_SERDES
 
 menu "Layerscape architecture"
        depends on FSL_LSCH2 || FSL_LSCH3
@@ -65,4 +72,13 @@ config SYS_FSL_IFC_BANK_COUNT
 config SYS_FSL_HAS_DP_DDR
        bool
 
+config SYS_FSL_SRDS_1
+       bool
+
+config SYS_FSL_SRDS_2
+       bool
+
+config SYS_HAS_SERDES
+       bool
+
 endmenu
index 6ee75cb4e83f5f2f552575ae535ccec370509f40..3039e72b04e93d1345caad52304f62d136a0a547 100644 (file)
@@ -32,8 +32,6 @@
 #ifdef CONFIG_LS2080A
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS          { 1, 1, 4, 4 }
 #define        SRDS_MAX_LANES  8
-#define CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_FSL_SRDS_2
 #define CONFIG_SYS_PAGE_SIZE           0x10000
 #ifndef L1_CACHE_BYTES
 #define L1_CACHE_SHIFT         6
 #define CONFIG_SYS_FSL_PEX_LUT_BE
 #define CONFIG_SYS_FSL_SEC_BE
 
-#define CONFIG_SYS_FSL_SRDS_1
-
 /* SoC related */
 #ifdef CONFIG_LS1043A
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_DDR_BLOCK1_SIZE  ((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED           CONFIG_SYS_DDR_BLOCK1_SIZE
 
-#define CONFIG_SYS_FSL_SRDS_2
 #define CONFIG_SYS_FSL_IFC_BE
 #define CONFIG_SYS_FSL_SFP_VER_3_2
 #define CONFIG_SYS_FSL_SNVS_LE
index 70cc7039f2a9f9cf6c22f211630d9f3afef2d443..dfcb54600d713071ff94a90f8467a7d8535a9903 100644 (file)
 
 #define DCU_LAYER_MAX_NUM                      16
 
-#define CONFIG_SYS_FSL_SRDS_1
-
 #ifdef CONFIG_LS102XA
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT          8
 #define CONFIG_NUM_DDR_CONTROLLERS             1
index 1056755b4176541573846e1301266c924b6ba42d..ced8eadebee21e2cf6520c383ca83f36a9396c06 100644 (file)
@@ -10,8 +10,6 @@
 #define CONFIG_FSL_LAYERSCAPE
 #define CONFIG_GICV2
 
-#define        CONFIG_SYS_HAS_SERDES
-
 #include <asm/arch/config.h>
 #define CONFIG_SYS_NO_FLASH
 
index 7cf8253e06ffff8e6c95dbb91b515b895524e456..d6945be1f37255591afcf6df1b0072c066fee40c 100644 (file)
@@ -142,8 +142,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 #endif
 
-#define CONFIG_SYS_HAS_SERDES
-
 #define CONFIG_FSL_CAAM                        /* Enable CAAM */
 
 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
index 023143c92122526cfeb6b1c0e9aa4ab409c4ba3f..511f573e8f15f309c310c195dd9b0ed13fea5776 100644 (file)
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 
-#define CONFIG_SYS_HAS_SERDES
-
 #define CONFIG_FSL_CAAM                        /* Enable CAAM */
 
 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
index ac86c08ee419e6520a5665b559ac6bcf28f09e0d..3a85b6a8efd0e0e18f2cc2152764d52605a38046 100644 (file)
@@ -15,9 +15,6 @@
 #define CONFIG_GICV2
 
 #include <asm/arch/config.h>
-#ifdef CONFIG_SYS_FSL_SRDS_1
-#define        CONFIG_SYS_HAS_SERDES
-#endif
 
 /* Link Definitions */
 #define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
index a80e33db542a5d34c158c267ff6c3cbfcc1cdef8..b18fcc0c2f5b0695a590e2d3a7cfd4a4ceccb435 100644 (file)
@@ -52,8 +52,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 #endif
 
-#define CONFIG_SYS_HAS_SERDES
-
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define CONFIG_FMAN_ENET
 #define CONFIG_PHYLIB
index ec6c908d4b97164dcf54336a4ab9df924d4d9122..c4bbd5600d3b308e2ff157736ac50703cc3f2bb3 100644 (file)
@@ -14,9 +14,6 @@
 #define CONFIG_GICV2
 
 #include <asm/arch/config.h>
-#ifdef CONFIG_SYS_FSL_SRDS_1
-#define        CONFIG_SYS_HAS_SERDES
-#endif
 
 /* Link Definitions */
 #define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
index 2e5c2f181fff92de4db9040998d5640ff7dfd6a8..d1adf3f3e2cd903ea1e29dbd452505ba50fa3c15 100644 (file)
@@ -49,8 +49,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 #endif
 
-#define CONFIG_SYS_HAS_SERDES
-
 /* DSPI */
 #ifdef CONFIG_FSL_DSPI
 #define CONFIG_SPI_FLASH_STMICRO       /* cs0 */
index d9eea0928f5f0be5100ab6d306d546c9bd689d5e..187aee146916184bca408c48faf3c492a35f8398 100644 (file)
@@ -15,9 +15,6 @@
 
 #include <asm/arch/ls2080a_stream_id.h>
 #include <asm/arch/config.h>
-#if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
-#define        CONFIG_SYS_HAS_SERDES
-#endif
 
 /* Link Definitions */
 #define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)