Move these options to Kconfig and clean up existing uses.
Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
config ARCH_LS1021A
bool
select SYS_FSL_ERRATUM_A010315
+ select SYS_FSL_SRDS_1
+ select SYS_HAS_SERDES
menu "LS102xA architecture"
depends on ARCH_LS1021A
config SYS_FSL_ERRATUM_A010315
bool "Workaround for PCIe erratum A010315"
+config SYS_FSL_SRDS_1
+ bool
+
+config SYS_FSL_SRDS_2
+ bool
+
+config SYS_HAS_SERDES
+ bool
+
config SYS_FSL_IFC_BANK_COUNT
int "Maximum banks of Integrated flash controller"
depends on ARCH_LS1021A
bool
select FSL_LSCH2
select SYS_FSL_ERRATUM_A010539
+ select SYS_FSL_SRDS_2
config ARCH_LS2080A
bool
select FSL_LSCH3
+ select SYS_FSL_HAS_DP_DDR
+ select SYS_FSL_SRDS_2
config FSL_LSCH2
bool
+ select SYS_FSL_SRDS_1
+ select SYS_HAS_SERDES
config FSL_LSCH3
bool
+ select SYS_FSL_SRDS_1
+ select SYS_HAS_SERDES
menu "Layerscape architecture"
depends on FSL_LSCH2 || FSL_LSCH3
config SYS_FSL_HAS_DP_DDR
bool
+config SYS_FSL_SRDS_1
+ bool
+
+config SYS_FSL_SRDS_2
+ bool
+
+config SYS_HAS_SERDES
+ bool
+
endmenu
#ifdef CONFIG_LS2080A
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
#define SRDS_MAX_LANES 8
-#define CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_FSL_SRDS_2
#define CONFIG_SYS_PAGE_SIZE 0x10000
#ifndef L1_CACHE_BYTES
#define L1_CACHE_SHIFT 6
#define CONFIG_SYS_FSL_PEX_LUT_BE
#define CONFIG_SYS_FSL_SEC_BE
-#define CONFIG_SYS_FSL_SRDS_1
-
/* SoC related */
#ifdef CONFIG_LS1043A
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
-#define CONFIG_SYS_FSL_SRDS_2
#define CONFIG_SYS_FSL_IFC_BE
#define CONFIG_SYS_FSL_SFP_VER_3_2
#define CONFIG_SYS_FSL_SNVS_LE
#define DCU_LAYER_MAX_NUM 16
-#define CONFIG_SYS_FSL_SRDS_1
-
#ifdef CONFIG_LS102XA
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_FSL_LAYERSCAPE
#define CONFIG_GICV2
-#define CONFIG_SYS_HAS_SERDES
-
#include <asm/arch/config.h>
#define CONFIG_SYS_NO_FLASH
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
-#define CONFIG_SYS_HAS_SERDES
-
#define CONFIG_FSL_CAAM /* Enable CAAM */
#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_HAS_SERDES
-
#define CONFIG_FSL_CAAM /* Enable CAAM */
#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
#define CONFIG_GICV2
#include <asm/arch/config.h>
-#ifdef CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_HAS_SERDES
-#endif
/* Link Definitions */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
-#define CONFIG_SYS_HAS_SERDES
-
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_FMAN_ENET
#define CONFIG_PHYLIB
#define CONFIG_GICV2
#include <asm/arch/config.h>
-#ifdef CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_HAS_SERDES
-#endif
/* Link Definitions */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
-#define CONFIG_SYS_HAS_SERDES
-
/* DSPI */
#ifdef CONFIG_FSL_DSPI
#define CONFIG_SPI_FLASH_STMICRO /* cs0 */
#include <asm/arch/ls2080a_stream_id.h>
#include <asm/arch/config.h>
-#if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
-#define CONFIG_SYS_HAS_SERDES
-#endif
/* Link Definitions */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)