]> git.sur5r.net Git - u-boot/commitdiff
powerpc/mpc85xx: Add T1024/T1023 SoC support
authorShengzhou Liu <Shengzhou.Liu@freescale.com>
Mon, 24 Nov 2014 09:11:54 +0000 (17:11 +0800)
committerYork Sun <yorksun@freescale.com>
Fri, 5 Dec 2014 16:06:14 +0000 (08:06 -0800)
Add support for Freescale T1024/T1023 SoC.

The T1024 SoC includes the following function and features:
- Two 64-bit Power architecture e5500 cores, up to 1.4GHz
- private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC)
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI)
- High-speed peripheral interfaces
  - Three PCI Express 2.0 controllers
- Additional peripheral interfaces
  - One SATA 2.0 controller
  - Two USB 2.0 controllers with integrated PHY
  - Enhanced secure digital host controller (SD/eSDHC/eMMC)
  - Enhanced serial peripheral interface (eSPI)
  - Four I2C controllers
  - Four 2-pin UARTs or two 4-pin UARTs
  - Integrated Flash Controller supporting NAND and NOR flash
- Two 8-channel DMA engines
- Multicore programmable interrupt controller (PIC)
- LCD interface (DIU) with 12 bit dual data rate
- QUICC Engine block supporting TDM, HDLC, and UART
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0

Differences between T1024 and T1023:
  Feature         T1024  T1023
  QUICC Engine:   yes    no
  DIU:            yes    no
  Deep Sleep:     yes    no
  I2C controller: 4      3
  DDR:            64-bit 32-bit
  IFC:            32-bit 28-bit

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
arch/powerpc/cpu/mpc85xx/Makefile
arch/powerpc/cpu/mpc85xx/speed.c
arch/powerpc/cpu/mpc85xx/t1024_ids.c [new file with mode: 0644]
arch/powerpc/cpu/mpc85xx/t1024_serdes.c [new file with mode: 0644]
arch/powerpc/cpu/mpc8xxx/cpu.c
arch/powerpc/include/asm/config_mpc85xx.h
arch/powerpc/include/asm/fsl_secure_boot.h
arch/powerpc/include/asm/immap_85xx.h
arch/powerpc/include/asm/processor.h
drivers/net/fm/Makefile
drivers/net/fm/t1024.c [new file with mode: 0644]

index ad26b432f1832ea356907c7bf0923dd23dec0abb..b93158b9ed25490505483566f35215f3d785dfc2 100644 (file)
@@ -51,6 +51,8 @@ obj-$(CONFIG_PPC_T1040) += t1040_ids.o
 obj-$(CONFIG_PPC_T1042)        += t1040_ids.o
 obj-$(CONFIG_PPC_T1020)        += t1040_ids.o
 obj-$(CONFIG_PPC_T1022)        += t1040_ids.o
+obj-$(CONFIG_PPC_T1023) += t1024_ids.o
+obj-$(CONFIG_PPC_T1024) += t1024_ids.o
 obj-$(CONFIG_PPC_T2080) += t2080_ids.o
 obj-$(CONFIG_PPC_T2081) += t2080_ids.o
 
@@ -97,6 +99,8 @@ obj-$(CONFIG_PPC_T1040) += t1040_serdes.o
 obj-$(CONFIG_PPC_T1042)        += t1040_serdes.o
 obj-$(CONFIG_PPC_T1020)        += t1040_serdes.o
 obj-$(CONFIG_PPC_T1022)        += t1040_serdes.o
+obj-$(CONFIG_PPC_T1023) += t1024_serdes.o
+obj-$(CONFIG_PPC_T1024) += t1024_serdes.o
 obj-$(CONFIG_PPC_T2080) += t2080_serdes.o
 obj-$(CONFIG_PPC_T2081) += t2080_serdes.o
 
index 56f41bcf7bbe209dd0872e552f590a9c7ee538a0..7e698730f3d1bfd0b48631b01fa35421e020a575 100644 (file)
@@ -185,6 +185,9 @@ void get_sys_info(sys_info_t *sys_info)
        defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
 #define FM1_CLK_SEL    0xe0000000
 #define FM1_CLK_SHIFT  29
+#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
+#define FM1_CLK_SEL    0x00000007
+#define FM1_CLK_SHIFT  0
 #else
 #define PME_CLK_SEL    0xe0000000
 #define PME_CLK_SHIFT  29
@@ -192,8 +195,12 @@ void get_sys_info(sys_info_t *sys_info)
 #define FM1_CLK_SHIFT  26
 #endif
 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
+#if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
+       rcw_tmp = in_be32(&gur->rcwsr[15]) - 4;
+#else
        rcw_tmp = in_be32(&gur->rcwsr[7]);
 #endif
+#endif
 
 #ifdef CONFIG_SYS_DPAA_PME
 #ifndef CONFIG_PME_PLAT_CLK_DIV
@@ -230,7 +237,10 @@ void get_sys_info(sys_info_t *sys_info)
 #endif
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
-       sys_info->freq_qman = sys_info->freq_systembus / 2;
+#ifndef CONFIG_QBMAN_CLK_DIV
+#define CONFIG_QBMAN_CLK_DIV   2
+#endif
+       sys_info->freq_qman = sys_info->freq_systembus / CONFIG_QBMAN_CLK_DIV;
 #endif
 
 #ifdef CONFIG_SYS_DPAA_FMAN
diff --git a/arch/powerpc/cpu/mpc85xx/t1024_ids.c b/arch/powerpc/cpu/mpc85xx/t1024_ids.c
new file mode 100644 (file)
index 0000000..5f24c15
--- /dev/null
@@ -0,0 +1,82 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+       /* dqrr liodn, frame data liodn, liodn off, sdest */
+       SET_QP_INFO(1, 27, 1, 0),
+       SET_QP_INFO(2, 28, 1, 0),
+       SET_QP_INFO(3, 29, 1, 1),
+       SET_QP_INFO(4, 30, 1, 1),
+       SET_QP_INFO(5, 31, 1, 2),
+       SET_QP_INFO(6, 32, 1, 2),
+       SET_QP_INFO(7, 33, 1, 3),
+       SET_QP_INFO(8, 34, 1, 3),
+       SET_QP_INFO(9, 35, 1, 0),
+       SET_QP_INFO(10, 36, 1, 0),
+};
+#endif
+
+struct liodn_id_table liodn_tbl[] = {
+#ifdef CONFIG_SYS_DPAA_QBMAN
+       SET_QMAN_LIODN(62),
+       SET_BMAN_LIODN(63),
+#endif
+
+       SET_SDHC_LIODN(1, 552),
+
+       SET_USB_LIODN(1, "fsl-usb2-mph", 553),
+       SET_USB_LIODN(2, "fsl-usb2-dr", 554),
+
+       SET_SATA_LIODN(1, 555),
+
+       SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
+       SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228),
+       SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308),
+
+       SET_DMA_LIODN(1, 147),
+       SET_DMA_LIODN(2, 227),
+       /* SET_NEXUS_LIODN(557), -- not yet implemented */
+       SET_QE_LIODN(559),
+       SET_TDM_LIODN(560),
+};
+int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct liodn_id_table fman1_liodn_tbl[] = {
+       SET_FMAN_RX_1G_LIODN(1, 0, 88),
+       SET_FMAN_RX_1G_LIODN(1, 1, 89),
+       SET_FMAN_RX_1G_LIODN(1, 2, 90),
+       SET_FMAN_RX_1G_LIODN(1, 3, 91),
+       SET_FMAN_RX_10G_LIODN(1, 0, 94),
+};
+int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
+#endif
+
+struct liodn_id_table sec_liodn_tbl[] = {
+       SET_SEC_JR_LIODN_ENTRY(0, 454, 458),
+       SET_SEC_JR_LIODN_ENTRY(1, 455, 459),
+       SET_SEC_JR_LIODN_ENTRY(2, 456, 460),
+       SET_SEC_JR_LIODN_ENTRY(3, 457, 461),
+       SET_SEC_RTIC_LIODN_ENTRY(a, 453),
+       SET_SEC_RTIC_LIODN_ENTRY(b, 549),
+       SET_SEC_RTIC_LIODN_ENTRY(c, 550),
+       SET_SEC_RTIC_LIODN_ENTRY(d, 551),
+       SET_SEC_DECO_LIODN_ENTRY(0, 541, 610),
+       SET_SEC_DECO_LIODN_ENTRY(1, 542, 611),
+};
+int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
+
+struct liodn_id_table liodn_bases[] = {
+       [FSL_HW_PORTAL_SEC]  = SET_LIODN_BASE_2(462, 558),
+#ifdef CONFIG_SYS_DPAA_FMAN
+       [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973),
+#endif
+};
diff --git a/arch/powerpc/cpu/mpc85xx/t1024_serdes.c b/arch/powerpc/cpu/mpc85xx/t1024_serdes.c
new file mode 100644 (file)
index 0000000..7dc8385
--- /dev/null
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+
+static u8 serdes_cfg_tbl[][4] = {
+       [0xD5] = {QSGMII_FM1_A, PCIE3, PCIE2, PCIE1},
+       [0xD6] = {QSGMII_FM1_A, PCIE3, PCIE2, SATA1},
+       [0x95] = {XFI_FM1_MAC1, PCIE3, PCIE2, PCIE1},
+       [0x99] = {XFI_FM1_MAC1, PCIE3, SGMII_FM1_DTSEC2, PCIE1},
+       [0x46] = {PCIE1, PCIE1, PCIE2, SATA1},
+       [0x47] = {PCIE1, PCIE1, PCIE2, SGMII_FM1_DTSEC1},
+       [0x56] = {PCIE1, PCIE3, PCIE2, SATA1},
+       [0x5A] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SATA1},
+       [0x5B] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1},
+       [0x6A] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SATA1},
+       [0x6B] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1},
+       [0x6F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2,
+                 SGMII_2500_FM1_DTSEC1},
+       [0x77] = {PCIE1, SGMII_2500_FM1_DTSEC3, PCIE2, SGMII_FM1_DTSEC1},
+       [0x7F] = {PCIE1, SGMII_2500_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2,
+                 SGMII_2500_FM1_DTSEC1},
+       [0x119] = {AURORA, PCIE3, SGMII_FM1_DTSEC2, PCIE1},
+       [0x135] = {AURORA, SGMII_2500_FM1_DTSEC3, PCIE2, PCIE1},
+};
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+       return serdes_cfg_tbl[cfg][lane];
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+       int i;
+
+       if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
+               return 0;
+
+       for (i = 0; i < 4; i++) {
+               if (serdes_cfg_tbl[prtcl][i] != NONE)
+                       return 1;
+       }
+
+       return 0;
+}
index 84fec5ed289b03f5574d2fb71f2e147398d3025f..2d28eb26552af73833018bd17660910dd9df1245 100644 (file)
@@ -76,6 +76,10 @@ static struct cpu_type cpu_type_list[] = {
        CPU_TYPE_ENTRY(T1020, T1020, 0),
        CPU_TYPE_ENTRY(T1021, T1021, 0),
        CPU_TYPE_ENTRY(T1022, T1022, 0),
+       CPU_TYPE_ENTRY(T1024, T1024, 0),
+       CPU_TYPE_ENTRY(T1023, T1023, 0),
+       CPU_TYPE_ENTRY(T1014, T1014, 0),
+       CPU_TYPE_ENTRY(T1013, T1013, 0),
        CPU_TYPE_ENTRY(T2080, T2080, 0),
        CPU_TYPE_ENTRY(T2081, T2081, 0),
        CPU_TYPE_ENTRY(BSC9130, 9130, 1),
index bcce5a3ab70c4dae45089c8d47365af1eeac2547..33f3d039a372656b0b793d75e909f6b1390b07bd 100644 (file)
@@ -787,6 +787,51 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define MAX_QE_RISC                    1
 #define QE_NUM_OF_SNUM                 28
 
+#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\
+defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
+#define CONFIG_E5500
+#define CONFIG_FSL_CORENET          /* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS2  /* Freescale Chassis generation 2 */
+#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
+#define CONFIG_SYS_FSL_QMAN_V3  /* QMAN version 3 */
+#define CONFIG_SYS_FMAN_V3
+#ifdef CONFIG_SYS_FSL_DDR4
+#define CONFIG_SYS_FSL_DDRC_GEN4
+#endif
+#if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
+#define CONFIG_MAX_CPUS                        2
+#elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
+#define CONFIG_MAX_CPUS                        1
+#endif
+#define CONFIG_SYS_FSL_NUM_CC_PLL      2
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS  { 1, 1, 1, 1 }
+#define CONFIG_SYS_SDHC_CLOCK          0
+#define CONFIG_SYS_FSL_NUM_LAWS                16
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_SEC_COMPAT      5
+#define CONFIG_SYS_NUM_FMAN            1
+#define CONFIG_SYS_NUM_FM1_DTSEC       4
+#define CONFIG_SYS_NUM_FM1_10GEC       1
+#define CONFIG_NUM_DDR_CONTROLLERS     1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT        2
+#define CONFIG_SYS_FSL_DDR_VER  FSL_DDR_VER_5_0
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT  8
+#define CONFIG_SYS_FM1_CLK             0
+#define CONFIG_QBMAN_CLK_DIV           1
+#define CONFIG_SYS_FM_MURAM_SIZE       0x30000
+#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+#define CONFIG_SYS_FSL_TBCLK_DIV       16
+#define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v2.4"
+#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_CCSRBAR_DEFAULT     0xfe000000
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
+#define QE_MURAM_SIZE                  0x6000UL
+#define MAX_QE_RISC                    1
+#define QE_NUM_OF_SNUM                 28
+#define CONFIG_SYS_FSL_SFP_VER_3_0
+
 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
 #define CONFIG_E6500
 #define CONFIG_SYS_PPC64               /* 64-bit core */
index 74c5d8f2d9233e4534ff05e60b44d4bc5e8cf7dd..14c6fc3cfec2eba879a9c0ed3d3b0faa84f92a5e 100644 (file)
@@ -22,7 +22,9 @@
        defined(CONFIG_T2080QDS) || \
        defined(CONFIG_T2080RDB) || \
        defined(CONFIG_T1040QDS) || \
-       defined(CONFIG_T104xRDB)
+       defined(CONFIG_T104xRDB) || \
+       defined(CONFIG_PPC_T1023) || \
+       defined(CONFIG_PPC_T1024)
 #define CONFIG_SYS_CPC_REINIT_F
 #undef CONFIG_SYS_INIT_L3_ADDR
 #define CONFIG_SYS_INIT_L3_ADDR                        0xbff00000
index 0264523d6402779e094ed5fee993f9fddcc95be0..f58456f541c2024095f9d39a796b74696ee73ad3 100644 (file)
@@ -1787,6 +1787,20 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define PXCKEN_MASK    0x80000000
 #define PXCK_MASK      0x00FF0000
 #define PXCK_BITS_START        16
+#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) || \
+       defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL                0xff800000
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT  23
+#define FSL_CORENET_RCWSR6_BOOT_LOC            0x0f800000
+#define FSL_CORENET_RCWSR13_EC1                        0x30000000 /* bits 418..419 */
+#define FSL_CORENET_RCWSR13_EC1_RGMII          0x00000000
+#define FSL_CORENET_RCWSR13_EC1_GPIO           0x10000000
+#define FSL_CORENET_RCWSR13_EC2                        0x0c000000
+#define FSL_CORENET_RCWSR13_EC2_RGMII          0x08000000
+#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET    0x28
+#define PXCKEN_MASK                            0x80000000
+#define PXCK_MASK                              0x00FF0000
+#define PXCK_BITS_START                                16
 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL                0xff000000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT  24
index 1b98e0f8a991f0b329592b0aa7b259988a09115d..2ed51b12486b62f3cbe535eb386a3396328d5ee1 100644 (file)
 #define SVR_T1020      0x852100
 #define SVR_T1021      0x852101
 #define SVR_T1022      0x852102
+#define SVR_T1024      0x854000
+#define SVR_T1023      0x854100
+#define SVR_T1014      0x854400
+#define SVR_T1013      0x854500
 #define SVR_T2080      0x853000
 #define SVR_T2081      0x853100
 
index 5ae3b167a93d681fed0b929972966da805174328..d052fcb372cbf590fa7c45bc1c23ee117300f459 100644 (file)
@@ -28,6 +28,8 @@ obj-$(CONFIG_PPC_T1040) += t1040.o
 obj-$(CONFIG_PPC_T1042)        += t1040.o
 obj-$(CONFIG_PPC_T1020)        += t1040.o
 obj-$(CONFIG_PPC_T1022)        += t1040.o
+obj-$(CONFIG_PPC_T1023) += t1024.o
+obj-$(CONFIG_PPC_T1024) += t1024.o
 obj-$(CONFIG_PPC_T2080) += t2080.o
 obj-$(CONFIG_PPC_T2081) += t2080.o
 obj-$(CONFIG_PPC_T4240) += t4240.o
diff --git a/drivers/net/fm/t1024.c b/drivers/net/fm/t1024.c
new file mode 100644 (file)
index 0000000..9b31173
--- /dev/null
@@ -0,0 +1,88 @@
+/* Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+
+u32 port_to_devdisr[] = {
+       [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
+       [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
+       [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
+       [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
+       [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1, /* MAC1 */
+};
+
+static int is_device_disabled(enum fm_port port)
+{
+       ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       u32 devdisr2 = in_be32(&gur->devdisr2);
+
+       return port_to_devdisr[port] & devdisr2;
+}
+
+void fman_disable_port(enum fm_port port)
+{
+       ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+       setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
+}
+
+phy_interface_t fman_port_enet_if(enum fm_port port)
+{
+       ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
+
+       if (is_device_disabled(port))
+               return PHY_INTERFACE_MODE_NONE;
+
+       if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC1)))
+               return PHY_INTERFACE_MODE_XGMII;
+
+       if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
+               FSL_CORENET_RCWSR13_EC2_RGMII) &&
+                                       (!is_serdes_configured(QSGMII_FM1_A)))
+               return PHY_INTERFACE_MODE_RGMII;
+
+       if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
+               FSL_CORENET_RCWSR13_EC1_RGMII) &&
+                                       (!is_serdes_configured(QSGMII_FM1_A)))
+               return PHY_INTERFACE_MODE_RGMII;
+
+       /* handle SGMII */
+       switch (port) {
+       case FM1_DTSEC1:
+       case FM1_DTSEC2:
+       case FM1_DTSEC3:
+               if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
+                       return PHY_INTERFACE_MODE_SGMII;
+               else if (is_serdes_configured(SGMII_2500_FM1_DTSEC1
+                        + port - FM1_DTSEC1))
+                       return PHY_INTERFACE_MODE_SGMII_2500;
+               break;
+       default:
+               break;
+       }
+
+       /* handle QSGMII */
+       switch (port) {
+       case FM1_DTSEC1:
+       case FM1_DTSEC2:
+       case FM1_DTSEC3:
+       case FM1_DTSEC4:
+               /* check lane A on SerDes1 */
+               if (is_serdes_configured(QSGMII_FM1_A))
+                       return PHY_INTERFACE_MODE_QSGMII;
+               break;
+       default:
+               break;
+       }
+
+       return PHY_INTERFACE_MODE_NONE;
+}