]> git.sur5r.net Git - u-boot/commitdiff
tegra: Add flow, gp_padctl, fuse, sdram headers
authorYen Lin <yelin@nvidia.com>
Mon, 2 Apr 2012 13:18:49 +0000 (13:18 +0000)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Tue, 15 May 2012 06:31:37 +0000 (08:31 +0200)
These headers provide access to additional Tegra features.

flow - start/stop CPUs
sdram - parameters for SDRAM
fuse - access to on-chip fuses / security settings
gp_padctl - pad control and general purpose registers

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Yen Lin <yelin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
arch/arm/include/asm/arch-tegra2/flow.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra2/fuse.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra2/gp_padctrl.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra2/sdram_param.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra2/tegra2.h

diff --git a/arch/arm/include/asm/arch-tegra2/flow.h b/arch/arm/include/asm/arch-tegra2/flow.h
new file mode 100644 (file)
index 0000000..cce6cbf
--- /dev/null
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2010, 2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _FLOW_H_
+#define _FLOW_H_
+
+struct flow_ctlr {
+       u32     halt_cpu_events;
+       u32     halt_cop_events;
+       u32     cpu_csr;
+       u32     cop_csr;
+       u32     halt_cpu1_events;
+       u32     cpu1_csr;
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-tegra2/fuse.h b/arch/arm/include/asm/arch-tegra2/fuse.h
new file mode 100644 (file)
index 0000000..b7e3808
--- /dev/null
@@ -0,0 +1,39 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _FUSE_H_
+#define _FUSE_H_
+
+/* FUSE registers */
+struct fuse_regs {
+       u32 reserved0[64];              /* 0x00 - 0xFC: */
+       u32 production_mode;            /* 0x100: FUSE_PRODUCTION_MODE */
+       u32 reserved1[3];               /* 0x104 - 0x10c: */
+       u32 sku_info;                   /* 0x110 */
+       u32 reserved2[13];              /* 0x114 - 0x144: */
+       u32 fa;                         /* 0x148: FUSE_FA */
+       u32 reserved3[21];              /* 0x14C - 0x19C: */
+       u32 security_mode;              /* 0x1A0: FUSE_SECURITY_MODE */
+};
+
+#endif /* ifndef _FUSE_H_ */
diff --git a/arch/arm/include/asm/arch-tegra2/gp_padctrl.h b/arch/arm/include/asm/arch-tegra2/gp_padctrl.h
new file mode 100644 (file)
index 0000000..25bb46d
--- /dev/null
@@ -0,0 +1,64 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _GP_PADCTRL_H_
+#define _GP_PADCTRL_H_
+
+/* APB_MISC_GP and padctrl registers */
+struct apb_misc_gp_ctlr {
+       u32     modereg;        /* 0x00: APB_MISC_GP_MODEREG */
+       u32     hidrev;         /* 0x04: APB_MISC_GP_HIDREV */
+       u32     reserved0[22];  /* 0x08 - 0x5C: */
+       u32     emu_revid;      /* 0x60: APB_MISC_GP_EMU_REVID */
+       u32     xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
+       u32     aocfg1;         /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
+       u32     aocfg2;         /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */
+       u32     atcfg1;         /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
+       u32     atcfg2;         /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
+       u32     cdevcfg1;       /* 0x78: APB_MISC_GP_CDEV1CFGPADCTRL */
+       u32     cdevcfg2;       /* 0x7C: APB_MISC_GP_CDEV2CFGPADCTRL */
+       u32     csuscfg;        /* 0x80: APB_MISC_GP_CSUSCFGPADCTRL */
+       u32     dap1cfg;        /* 0x84: APB_MISC_GP_DAP1CFGPADCTRL */
+       u32     dap2cfg;        /* 0x88: APB_MISC_GP_DAP2CFGPADCTRL */
+       u32     dap3cfg;        /* 0x8C: APB_MISC_GP_DAP3CFGPADCTRL */
+       u32     dap4cfg;        /* 0x90: APB_MISC_GP_DAP4CFGPADCTRL */
+       u32     dbgcfg;         /* 0x94: APB_MISC_GP_DBGCFGPADCTRL */
+       u32     lcdcfg1;        /* 0x98: APB_MISC_GP_LCDCFG1PADCTRL */
+       u32     lcdcfg2;        /* 0x9C: APB_MISC_GP_LCDCFG2PADCTRL */
+       u32     sdmmc2_cfg;     /* 0xA0: APB_MISC_GP_SDMMC2CFGPADCTRL */
+       u32     sdmmc3_cfg;     /* 0xA4: APB_MISC_GP_SDMMC3CFGPADCTRL */
+       u32     spicfg;         /* 0xA8: APB_MISC_GP_SPICFGPADCTRL */
+       u32     uaacfg;         /* 0xAC: APB_MISC_GP_UAACFGPADCTRL */
+       u32     uabcfg;         /* 0xB0: APB_MISC_GP_UABCFGPADCTRL */
+       u32     uart2cfg;       /* 0xB4: APB_MISC_GP_UART2CFGPADCTRL */
+       u32     uart3cfg;       /* 0xB8: APB_MISC_GP_UART3CFGPADCTRL */
+       u32     vicfg1;         /* 0xBC: APB_MISC_GP_VICFG1PADCTRL */
+       u32     vicfg2;         /* 0xC0: APB_MISC_GP_VICFG2PADCTRL */
+       u32     xm2cfga;        /* 0xC4: APB_MISC_GP_XM2CFGAPADCTRL */
+       u32     xm2cfgc;        /* 0xC8: APB_MISC_GP_XM2CFGCPADCTRL */
+       u32     xm2cfgd;        /* 0xCC: APB_MISC_GP_XM2CFGDPADCTRL */
+       u32     xm2clkcfg;      /* 0xD0: APB_MISC_GP_XM2CLKCFGPADCTRL */
+       u32     memcomp;        /* 0xD4: APB_MISC_GP_MEMCOMPPADCTRL */
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-tegra2/sdram_param.h b/arch/arm/include/asm/arch-tegra2/sdram_param.h
new file mode 100644 (file)
index 0000000..6c427d0
--- /dev/null
@@ -0,0 +1,148 @@
+/*
+ *  (C) Copyright 2010, 2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SDRAM_PARAM_H_
+#define _SDRAM_PARAM_H_
+
+/*
+ * Defines the number of 32-bit words provided in each set of SDRAM parameters
+ * for arbitration configuration data.
+ */
+#define BCT_SDRAM_ARB_CONFIG_WORDS 27
+
+enum memory_type {
+       MEMORY_TYPE_NONE = 0,
+       MEMORY_TYPE_DDR,
+       MEMORY_TYPE_LPDDR,
+       MEMORY_TYPE_DDR2,
+       MEMORY_TYPE_LPDDR2,
+       MEMORY_TYPE_NUM,
+       MEMORY_TYPE_FORCE32 = 0x7FFFFFFF
+};
+
+/* Defines the SDRAM parameter structure */
+struct sdram_params {
+       enum memory_type memory_type;
+       u32 pllm_charge_pump_setup_control;
+       u32 pllm_loop_filter_setup_control;
+       u32 pllm_input_divider;
+       u32 pllm_feedback_divider;
+       u32 pllm_post_divider;
+       u32 pllm_stable_time;
+       u32 emc_clock_divider;
+       u32 emc_auto_cal_interval;
+       u32 emc_auto_cal_config;
+       u32 emc_auto_cal_wait;
+       u32 emc_pin_program_wait;
+       u32 emc_rc;
+       u32 emc_rfc;
+       u32 emc_ras;
+       u32 emc_rp;
+       u32 emc_r2w;
+       u32 emc_w2r;
+       u32 emc_r2p;
+       u32 emc_w2p;
+       u32 emc_rd_rcd;
+       u32 emc_wr_rcd;
+       u32 emc_rrd;
+       u32 emc_rext;
+       u32 emc_wdv;
+       u32 emc_quse;
+       u32 emc_qrst;
+       u32 emc_qsafe;
+       u32 emc_rdv;
+       u32 emc_refresh;
+       u32 emc_burst_refresh_num;
+       u32 emc_pdex2wr;
+       u32 emc_pdex2rd;
+       u32 emc_pchg2pden;
+       u32 emc_act2pden;
+       u32 emc_ar2pden;
+       u32 emc_rw2pden;
+       u32 emc_txsr;
+       u32 emc_tcke;
+       u32 emc_tfaw;
+       u32 emc_trpab;
+       u32 emc_tclkstable;
+       u32 emc_tclkstop;
+       u32 emc_trefbw;
+       u32 emc_quseextra;
+       u32 emc_fbioc_fg1;
+       u32 emc_fbio_dqsib_dly;
+       u32 emc_fbio_dqsib_dly_msb;
+       u32 emc_fbio_quse_dly;
+       u32 emc_fbio_quse_dly_msb;
+       u32 emc_fbio_cfg5;
+       u32 emc_fbio_cfg6;
+       u32 emc_fbio_spare;
+       u32 emc_mrs;
+       u32 emc_emrs;
+       u32 emc_mrw1;
+       u32 emc_mrw2;
+       u32 emc_mrw3;
+       u32 emc_mrw_reset_command;
+       u32 emc_mrw_reset_init_wait;
+       u32 emc_adr_cfg;
+       u32 emc_adr_cfg1;
+       u32 emc_emem_cfg;
+       u32 emc_low_latency_config;
+       u32 emc_cfg;
+       u32 emc_cfg2;
+       u32 emc_dbg;
+       u32 ahb_arbitration_xbar_ctrl;
+       u32 emc_cfg_dig_dll;
+       u32 emc_dll_xform_dqs;
+       u32 emc_dll_xform_quse;
+       u32 warm_boot_wait;
+       u32 emc_ctt_term_ctrl;
+       u32 emc_odt_write;
+       u32 emc_odt_read;
+       u32 emc_zcal_ref_cnt;
+       u32 emc_zcal_wait_cnt;
+       u32 emc_zcal_mrw_cmd;
+       u32 emc_mrs_reset_dll;
+       u32 emc_mrw_zq_init_dev0;
+       u32 emc_mrw_zq_init_dev1;
+       u32 emc_mrw_zq_init_wait;
+       u32 emc_mrs_reset_dll_wait;
+       u32 emc_emrs_emr2;
+       u32 emc_emrs_emr3;
+       u32 emc_emrs_ddr2_dll_enable;
+       u32 emc_mrs_ddr2_dll_reset;
+       u32 emc_emrs_ddr2_ocd_calib;
+       u32 emc_edr2_wait;
+       u32 emc_cfg_clktrim0;
+       u32 emc_cfg_clktrim1;
+       u32 emc_cfg_clktrim2;
+       u32 pmc_ddr_pwr;
+       u32 apb_misc_gp_xm2cfga_padctrl;
+       u32 apb_misc_gp_xm2cfgc_padctrl;
+       u32 apb_misc_gp_xm2cfgc_padctrl2;
+       u32 apb_misc_gp_xm2cfgd_padctrl;
+       u32 apb_misc_gp_xm2cfgd_padctrl2;
+       u32 apb_misc_gp_xm2clkcfg_padctrl;
+       u32 apb_misc_gp_xm2comp_padctrl;
+       u32 apb_misc_gp_xm2vttgen_padctrl;
+       u32 arbitration_config[BCT_SDRAM_ARB_CONFIG_WORDS];
+};
+#endif
index ca1881e3a2fd140a15f8c35d4f5d387b1b4fd0ae..2e152fd077e17478ecc8d427ea967b31be277227 100644 (file)
@@ -40,6 +40,7 @@
 #define NV_PA_APB_UARTE_BASE   (NV_PA_APB_MISC_BASE + 0x6400)
 #define TEGRA2_SPI_BASE                (NV_PA_APB_MISC_BASE + 0xC380)
 #define TEGRA2_PMC_BASE                (NV_PA_APB_MISC_BASE + 0xE400)
+#define TEGRA2_FUSE_BASE       (NV_PA_APB_MISC_BASE + 0xF800)
 #define NV_PA_CSITE_BASE       0x70040000
 #define TEGRA_USB1_BASE                0xC5000000
 #define TEGRA_USB3_BASE                0xC5008000