ARM: Add workaround for Cortex-A9 errata 794072

A short loop including a DMB instruction might cause a denial of
service on another processor which executes a CP15 broadcast operation.
Exists on r1, r2, r3, r4 revisions.

Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>

diff --git a/README b/README
index 216f0c70aa9403534127dcd256627fa55e12f08e..00127a75ef76854d01062c90800c1c7cb7be7026 100644 (file)
--- a/README
+++ b/README
@@ -566,6 +566,7 @@ The following options need to be configured:
                CONFIG_ARM_ERRATA_742230
                CONFIG_ARM_ERRATA_743622
                CONFIG_ARM_ERRATA_751472
+               CONFIG_ARM_ERRATA_794072
 
                If set, the workarounds for these ARM errata are applied early
                during U-Boot startup. Note that these options force the

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index ac1e55a708d7edb8a9e3d65202867b472aaf5096..f3830c847161a0dc891cd3ef1fc0a6226347be18 100644 (file)
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -205,7 +205,7 @@ ENTRY(cpu_init_cp15)
        mcr     p15, 0, r0, c1, c0, 0   @ write system control register
 #endif
 
-#ifdef CONFIG_ARM_ERRATA_742230
+#if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072))
        mrc     p15, 0, r0, c15, c0, 1  @ read diagnostic register
        orr     r0, r0, #1 << 4         @ set bit #4
        mcr     p15, 0, r0, c15, c0, 1  @ write diagnostic register