-obj-$(CONFIG_CLK_RCAR_GEN3) += clk-rcar-gen3.o
+obj-$(CONFIG_CLK_RCAR_GEN3) += clk-rcar-gen3.o \
+ r8a7795-cpg-mssr.o \
+ r8a7796-cpg-mssr.o \
+ r8a77970-cpg-mssr.o \
+ r8a77995-cpg-mssr.o
#include <wait_bit.h>
#include <asm/io.h>
-#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
-#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
-#include <dt-bindings/clock/r8a77970-cpg-mssr.h>
-#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
#define CPG_RST_MODEMR 0x0060
/* Software Reset Clearing Register offsets */
#define SRSTCLR(i) (0x940 + (i) * 4)
-struct gen3_clk_priv {
- void __iomem *base;
- struct clk clk_extal;
- struct clk clk_extalr;
- const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
- const struct cpg_core_clk *core_clk;
- u32 core_clk_size;
- const struct mssr_mod_clk *mod_clk;
- u32 mod_clk_size;
-};
-
-/*
- * Definitions of CPG Core Clocks
- *
- * These include:
- * - Clock outputs exported to DT
- * - External input clocks
- * - Internal CPG clocks
- */
-struct cpg_core_clk {
- /* Common */
- const char *name;
- unsigned int id;
- unsigned int type;
- /* Depending on type */
- unsigned int parent; /* Core Clocks only */
- unsigned int div;
- unsigned int mult;
- unsigned int offset;
-};
-
-enum clk_types {
- /* Generic */
- CLK_TYPE_IN, /* External Clock Input */
- CLK_TYPE_FF, /* Fixed Factor Clock */
-
- /* Custom definitions start here */
- CLK_TYPE_CUSTOM,
-};
-
-#define DEF_TYPE(_name, _id, _type...) \
- { .name = _name, .id = _id, .type = _type }
-#define DEF_BASE(_name, _id, _type, _parent...) \
- DEF_TYPE(_name, _id, _type, .parent = _parent)
-
-#define DEF_INPUT(_name, _id) \
- DEF_TYPE(_name, _id, CLK_TYPE_IN)
-#define DEF_FIXED(_name, _id, _parent, _div, _mult) \
- DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
-#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
- DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
-#define DEF_GEN3_RPC(_name, _id, _parent, _offset) \
- DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset)
-#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
- _div_clean) \
- DEF_BASE(_name, _id, CLK_TYPE_FF, \
- (_parent_clean), .div = (_div_clean), 1)
-
-/*
- * Definitions of Module Clocks
- */
-struct mssr_mod_clk {
- const char *name;
- unsigned int id;
- unsigned int parent; /* Add MOD_CLK_BASE for Module Clocks */
-};
-
-/* Convert from sparse base-100 to packed index space */
-#define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
-
-#define MOD_CLK_ID(x) (MOD_CLK_BASE + MOD_CLK_PACK(x))
-
-#define DEF_MOD(_name, _mod, _parent...) \
- { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
-
-enum rcar_gen3_clk_types {
- CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
- CLK_TYPE_GEN3_PLL0,
- CLK_TYPE_GEN3_PLL1,
- CLK_TYPE_GEN3_PLL2,
- CLK_TYPE_GEN3_PLL3,
- CLK_TYPE_GEN3_PLL4,
- CLK_TYPE_GEN3_SD,
- CLK_TYPE_GEN3_RPC,
- CLK_TYPE_GEN3_R,
- CLK_TYPE_GEN3_PE,
- CLK_TYPE_GEN3_Z2,
-};
-
-struct rcar_gen3_cpg_pll_config {
- unsigned int extal_div;
- unsigned int pll1_mult;
- unsigned int pll3_mult;
-};
-
-enum clk_ids {
- /* Core Clock Outputs exported to DT */
- LAST_DT_CORE_CLK = R8A7796_CLK_OSC,
-
- /* External Input Clocks */
- CLK_EXTAL,
- CLK_EXTALR,
-
- /* Internal Core Clocks */
- CLK_MAIN,
- CLK_PLL0,
- CLK_PLL1,
- CLK_PLL2,
- CLK_PLL3,
- CLK_PLL4,
- CLK_PLL1_DIV2,
- CLK_PLL1_DIV4,
- CLK_PLL0D2,
- CLK_PLL0D3,
- CLK_PLL0D5,
- CLK_PLL1D2,
- CLK_PE,
- CLK_S0,
- CLK_S1,
- CLK_S2,
- CLK_S3,
- CLK_SDSRC,
- CLK_RPCSRC,
- CLK_SSPSRC,
- CLK_RINT,
-
- /* Module Clocks */
- MOD_CLK_BASE
-};
-
-static const struct cpg_core_clk r8a7795_core_clks[] = {
- /* External Clock Inputs */
- DEF_INPUT("extal", CLK_EXTAL),
- DEF_INPUT("extalr", CLK_EXTALR),
-
- /* Internal Core Clocks */
- DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
- DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
- DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
- DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
- DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
- DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
-
- DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
- DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
- DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
- DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
- DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
- DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
- DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
- DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
-
- /* Core Clock Outputs */
- DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
- DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
- DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
- DEF_FIXED("zx", R8A7795_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
- DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1),
- DEF_FIXED("s0d2", R8A7795_CLK_S0D2, CLK_S0, 2, 1),
- DEF_FIXED("s0d3", R8A7795_CLK_S0D3, CLK_S0, 3, 1),
- DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1),
- DEF_FIXED("s0d6", R8A7795_CLK_S0D6, CLK_S0, 6, 1),
- DEF_FIXED("s0d8", R8A7795_CLK_S0D8, CLK_S0, 8, 1),
- DEF_FIXED("s0d12", R8A7795_CLK_S0D12, CLK_S0, 12, 1),
- DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1),
- DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1),
- DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1),
- DEF_FIXED("s2d1", R8A7795_CLK_S2D1, CLK_S2, 1, 1),
- DEF_FIXED("s2d2", R8A7795_CLK_S2D2, CLK_S2, 2, 1),
- DEF_FIXED("s2d4", R8A7795_CLK_S2D4, CLK_S2, 4, 1),
- DEF_FIXED("s3d1", R8A7795_CLK_S3D1, CLK_S3, 1, 1),
- DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1),
- DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1),
-
- DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074),
- DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078),
- DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268),
- DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c),
-
- DEF_GEN3_RPC("rpc", R8A7795_CLK_RPC, CLK_RPCSRC, 0x238),
-
- DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
- DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
-
- /* NOTE: HDMI, CSI, CAN etc. clock are missing */
-
- DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
-};
-
-static const struct mssr_mod_clk r8a7795_mod_clks[] = {
- DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */
- DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),
- DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
- DEF_MOD("scif5", 202, R8A7795_CLK_S3D4),
- DEF_MOD("scif4", 203, R8A7795_CLK_S3D4),
- DEF_MOD("scif3", 204, R8A7795_CLK_S3D4),
- DEF_MOD("scif1", 206, R8A7795_CLK_S3D4),
- DEF_MOD("scif0", 207, R8A7795_CLK_S3D4),
- DEF_MOD("msiof3", 208, R8A7795_CLK_MSO),
- DEF_MOD("msiof2", 209, R8A7795_CLK_MSO),
- DEF_MOD("msiof1", 210, R8A7795_CLK_MSO),
- DEF_MOD("msiof0", 211, R8A7795_CLK_MSO),
- DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S0D3),
- DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S0D3),
- DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3),
- DEF_MOD("cmt3", 300, R8A7795_CLK_R),
- DEF_MOD("cmt2", 301, R8A7795_CLK_R),
- DEF_MOD("cmt1", 302, R8A7795_CLK_R),
- DEF_MOD("cmt0", 303, R8A7795_CLK_R),
- DEF_MOD("scif2", 310, R8A7795_CLK_S3D4),
- DEF_MOD("sdif3", 311, R8A7795_CLK_SD3),
- DEF_MOD("sdif2", 312, R8A7795_CLK_SD2),
- DEF_MOD("sdif1", 313, R8A7795_CLK_SD1),
- DEF_MOD("sdif0", 314, R8A7795_CLK_SD0),
- DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1),
- DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1),
- DEF_MOD("usb-dmac30", 326, R8A7795_CLK_S3D1),
- DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), /* ES1.x */
- DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1),
- DEF_MOD("usb-dmac31", 329, R8A7795_CLK_S3D1),
- DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1),
- DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1),
- DEF_MOD("rwdt", 402, R8A7795_CLK_R),
- DEF_MOD("intc-ex", 407, R8A7795_CLK_CP),
- DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1),
- DEF_MOD("audmac1", 501, R8A7795_CLK_S0D3),
- DEF_MOD("audmac0", 502, R8A7795_CLK_S0D3),
- DEF_MOD("drif7", 508, R8A7795_CLK_S3D2),
- DEF_MOD("drif6", 509, R8A7795_CLK_S3D2),
- DEF_MOD("drif5", 510, R8A7795_CLK_S3D2),
- DEF_MOD("drif4", 511, R8A7795_CLK_S3D2),
- DEF_MOD("drif3", 512, R8A7795_CLK_S3D2),
- DEF_MOD("drif2", 513, R8A7795_CLK_S3D2),
- DEF_MOD("drif1", 514, R8A7795_CLK_S3D2),
- DEF_MOD("drif0", 515, R8A7795_CLK_S3D2),
- DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1),
- DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1),
- DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
- DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1),
- DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
- DEF_MOD("thermal", 522, R8A7795_CLK_CP),
- DEF_MOD("pwm", 523, R8A7795_CLK_S0D12),
- DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), /* ES1.x */
- DEF_MOD("fcpvd2", 601, R8A7795_CLK_S0D2),
- DEF_MOD("fcpvd1", 602, R8A7795_CLK_S0D2),
- DEF_MOD("fcpvd0", 603, R8A7795_CLK_S0D2),
- DEF_MOD("fcpvb1", 606, R8A7795_CLK_S0D1),
- DEF_MOD("fcpvb0", 607, R8A7795_CLK_S0D1),
- DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1), /* ES1.x */
- DEF_MOD("fcpvi1", 610, R8A7795_CLK_S0D1),
- DEF_MOD("fcpvi0", 611, R8A7795_CLK_S0D1),
- DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), /* ES1.x */
- DEF_MOD("fcpf1", 614, R8A7795_CLK_S0D1),
- DEF_MOD("fcpf0", 615, R8A7795_CLK_S0D1),
- DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1), /* ES1.x */
- DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1), /* ES1.x */
- DEF_MOD("fcpcs", 619, R8A7795_CLK_S0D1),
- DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), /* ES1.x */
- DEF_MOD("vspd2", 621, R8A7795_CLK_S0D2),
- DEF_MOD("vspd1", 622, R8A7795_CLK_S0D2),
- DEF_MOD("vspd0", 623, R8A7795_CLK_S0D2),
- DEF_MOD("vspbc", 624, R8A7795_CLK_S0D1),
- DEF_MOD("vspbd", 626, R8A7795_CLK_S0D1),
- DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */
- DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1),
- DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1),
- DEF_MOD("ehci3", 700, R8A7795_CLK_S3D4),
- DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4),
- DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4),
- DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4),
- DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4),
- DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D4),
- DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */
- DEF_MOD("csi20", 714, R8A7795_CLK_CSI0),
- DEF_MOD("csi41", 715, R8A7795_CLK_CSI0),
- DEF_MOD("csi40", 716, R8A7795_CLK_CSI0),
- DEF_MOD("du3", 721, R8A7795_CLK_S2D1),
- DEF_MOD("du2", 722, R8A7795_CLK_S2D1),
- DEF_MOD("du1", 723, R8A7795_CLK_S2D1),
- DEF_MOD("du0", 724, R8A7795_CLK_S2D1),
- DEF_MOD("lvds", 727, R8A7795_CLK_S0D4),
- DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI),
- DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI),
- DEF_MOD("vin7", 804, R8A7795_CLK_S0D2),
- DEF_MOD("vin6", 805, R8A7795_CLK_S0D2),
- DEF_MOD("vin5", 806, R8A7795_CLK_S0D2),
- DEF_MOD("vin4", 807, R8A7795_CLK_S0D2),
- DEF_MOD("vin3", 808, R8A7795_CLK_S0D2),
- DEF_MOD("vin2", 809, R8A7795_CLK_S0D2),
- DEF_MOD("vin1", 810, R8A7795_CLK_S0D2),
- DEF_MOD("vin0", 811, R8A7795_CLK_S0D2),
- DEF_MOD("etheravb", 812, R8A7795_CLK_S0D6),
- DEF_MOD("sata0", 815, R8A7795_CLK_S3D2),
- DEF_MOD("imr3", 820, R8A7795_CLK_S0D2),
- DEF_MOD("imr2", 821, R8A7795_CLK_S0D2),
- DEF_MOD("imr1", 822, R8A7795_CLK_S0D2),
- DEF_MOD("imr0", 823, R8A7795_CLK_S0D2),
- DEF_MOD("gpio7", 905, R8A7795_CLK_S3D4),
- DEF_MOD("gpio6", 906, R8A7795_CLK_S3D4),
- DEF_MOD("gpio5", 907, R8A7795_CLK_S3D4),
- DEF_MOD("gpio4", 908, R8A7795_CLK_S3D4),
- DEF_MOD("gpio3", 909, R8A7795_CLK_S3D4),
- DEF_MOD("gpio2", 910, R8A7795_CLK_S3D4),
- DEF_MOD("gpio1", 911, R8A7795_CLK_S3D4),
- DEF_MOD("gpio0", 912, R8A7795_CLK_S3D4),
- DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2),
- DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4),
- DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4),
- DEF_MOD("rpc", 917, R8A7795_CLK_RPC),
- DEF_MOD("i2c6", 918, R8A7795_CLK_S0D6),
- DEF_MOD("i2c5", 919, R8A7795_CLK_S0D6),
- DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP),
- DEF_MOD("i2c4", 927, R8A7795_CLK_S0D6),
- DEF_MOD("i2c3", 928, R8A7795_CLK_S0D6),
- DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2),
- DEF_MOD("i2c1", 930, R8A7795_CLK_S3D2),
- DEF_MOD("i2c0", 931, R8A7795_CLK_S3D2),
- DEF_MOD("ssi-all", 1005, R8A7795_CLK_S3D4),
- DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
- DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
- DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
- DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
- DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
- DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
- DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
- DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
- DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
- DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
- DEF_MOD("scu-all", 1017, R8A7795_CLK_S3D4),
- DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
- DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
- DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
- DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
-};
-
-static const struct cpg_core_clk r8a7796_core_clks[] = {
- /* External Clock Inputs */
- DEF_INPUT("extal", CLK_EXTAL),
- DEF_INPUT("extalr", CLK_EXTALR),
-
- /* Internal Core Clocks */
- DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
- DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
- DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
- DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
- DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
- DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
-
- DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
- DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
- DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
- DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
- DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
- DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
- DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
- DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
-
- /* Core Clock Outputs */
- DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
- DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
- DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
- DEF_FIXED("zx", R8A7796_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
- DEF_FIXED("s0d1", R8A7796_CLK_S0D1, CLK_S0, 1, 1),
- DEF_FIXED("s0d2", R8A7796_CLK_S0D2, CLK_S0, 2, 1),
- DEF_FIXED("s0d3", R8A7796_CLK_S0D3, CLK_S0, 3, 1),
- DEF_FIXED("s0d4", R8A7796_CLK_S0D4, CLK_S0, 4, 1),
- DEF_FIXED("s0d6", R8A7796_CLK_S0D6, CLK_S0, 6, 1),
- DEF_FIXED("s0d8", R8A7796_CLK_S0D8, CLK_S0, 8, 1),
- DEF_FIXED("s0d12", R8A7796_CLK_S0D12, CLK_S0, 12, 1),
- DEF_FIXED("s1d1", R8A7796_CLK_S1D1, CLK_S1, 1, 1),
- DEF_FIXED("s1d2", R8A7796_CLK_S1D2, CLK_S1, 2, 1),
- DEF_FIXED("s1d4", R8A7796_CLK_S1D4, CLK_S1, 4, 1),
- DEF_FIXED("s2d1", R8A7796_CLK_S2D1, CLK_S2, 1, 1),
- DEF_FIXED("s2d2", R8A7796_CLK_S2D2, CLK_S2, 2, 1),
- DEF_FIXED("s2d4", R8A7796_CLK_S2D4, CLK_S2, 4, 1),
- DEF_FIXED("s3d1", R8A7796_CLK_S3D1, CLK_S3, 1, 1),
- DEF_FIXED("s3d2", R8A7796_CLK_S3D2, CLK_S3, 2, 1),
- DEF_FIXED("s3d4", R8A7796_CLK_S3D4, CLK_S3, 4, 1),
-
- DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074),
- DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078),
- DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268),
- DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c),
-
- DEF_GEN3_RPC("rpc", R8A7796_CLK_RPC, CLK_RPCSRC, 0x238),
-
- DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
- DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1),
-
- /* NOTE: HDMI, CSI, CAN etc. clock are missing */
-
- DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
-};
-
-static const struct mssr_mod_clk r8a7796_mod_clks[] = {
- DEF_MOD("scif5", 202, R8A7796_CLK_S3D4),
- DEF_MOD("scif4", 203, R8A7796_CLK_S3D4),
- DEF_MOD("scif3", 204, R8A7796_CLK_S3D4),
- DEF_MOD("scif1", 206, R8A7796_CLK_S3D4),
- DEF_MOD("scif0", 207, R8A7796_CLK_S3D4),
- DEF_MOD("msiof3", 208, R8A7796_CLK_MSO),
- DEF_MOD("msiof2", 209, R8A7796_CLK_MSO),
- DEF_MOD("msiof1", 210, R8A7796_CLK_MSO),
- DEF_MOD("msiof0", 211, R8A7796_CLK_MSO),
- DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S0D3),
- DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S0D3),
- DEF_MOD("sys-dmac0", 219, R8A7796_CLK_S0D3),
- DEF_MOD("cmt3", 300, R8A7796_CLK_R),
- DEF_MOD("cmt2", 301, R8A7796_CLK_R),
- DEF_MOD("cmt1", 302, R8A7796_CLK_R),
- DEF_MOD("cmt0", 303, R8A7796_CLK_R),
- DEF_MOD("scif2", 310, R8A7796_CLK_S3D4),
- DEF_MOD("sdif3", 311, R8A7796_CLK_SD3),
- DEF_MOD("sdif2", 312, R8A7796_CLK_SD2),
- DEF_MOD("sdif1", 313, R8A7796_CLK_SD1),
- DEF_MOD("sdif0", 314, R8A7796_CLK_SD0),
- DEF_MOD("pcie1", 318, R8A7796_CLK_S3D1),
- DEF_MOD("pcie0", 319, R8A7796_CLK_S3D1),
- DEF_MOD("usb3-if0", 328, R8A7796_CLK_S3D1),
- DEF_MOD("usb-dmac0", 330, R8A7796_CLK_S3D1),
- DEF_MOD("usb-dmac1", 331, R8A7796_CLK_S3D1),
- DEF_MOD("rwdt", 402, R8A7796_CLK_R),
- DEF_MOD("intc-ex", 407, R8A7796_CLK_CP),
- DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1),
- DEF_MOD("audmac1", 501, R8A7796_CLK_S0D3),
- DEF_MOD("audmac0", 502, R8A7796_CLK_S0D3),
- DEF_MOD("drif7", 508, R8A7796_CLK_S3D2),
- DEF_MOD("drif6", 509, R8A7796_CLK_S3D2),
- DEF_MOD("drif5", 510, R8A7796_CLK_S3D2),
- DEF_MOD("drif4", 511, R8A7796_CLK_S3D2),
- DEF_MOD("drif3", 512, R8A7796_CLK_S3D2),
- DEF_MOD("drif2", 513, R8A7796_CLK_S3D2),
- DEF_MOD("drif1", 514, R8A7796_CLK_S3D2),
- DEF_MOD("drif0", 515, R8A7796_CLK_S3D2),
- DEF_MOD("hscif4", 516, R8A7796_CLK_S3D1),
- DEF_MOD("hscif3", 517, R8A7796_CLK_S3D1),
- DEF_MOD("hscif2", 518, R8A7796_CLK_S3D1),
- DEF_MOD("hscif1", 519, R8A7796_CLK_S3D1),
- DEF_MOD("hscif0", 520, R8A7796_CLK_S3D1),
- DEF_MOD("thermal", 522, R8A7796_CLK_CP),
- DEF_MOD("pwm", 523, R8A7796_CLK_S0D12),
- DEF_MOD("fcpvd2", 601, R8A7796_CLK_S0D2),
- DEF_MOD("fcpvd1", 602, R8A7796_CLK_S0D2),
- DEF_MOD("fcpvd0", 603, R8A7796_CLK_S0D2),
- DEF_MOD("fcpvb0", 607, R8A7796_CLK_S0D1),
- DEF_MOD("fcpvi0", 611, R8A7796_CLK_S0D1),
- DEF_MOD("fcpf0", 615, R8A7796_CLK_S0D1),
- DEF_MOD("fcpci0", 617, R8A7796_CLK_S0D2),
- DEF_MOD("fcpcs", 619, R8A7796_CLK_S0D2),
- DEF_MOD("vspd2", 621, R8A7796_CLK_S0D2),
- DEF_MOD("vspd1", 622, R8A7796_CLK_S0D2),
- DEF_MOD("vspd0", 623, R8A7796_CLK_S0D2),
- DEF_MOD("vspb", 626, R8A7796_CLK_S0D1),
- DEF_MOD("vspi0", 631, R8A7796_CLK_S0D1),
- DEF_MOD("ehci1", 702, R8A7796_CLK_S3D4),
- DEF_MOD("ehci0", 703, R8A7796_CLK_S3D4),
- DEF_MOD("hsusb", 704, R8A7796_CLK_S3D4),
- DEF_MOD("csi20", 714, R8A7796_CLK_CSI0),
- DEF_MOD("csi40", 716, R8A7796_CLK_CSI0),
- DEF_MOD("du2", 722, R8A7796_CLK_S2D1),
- DEF_MOD("du1", 723, R8A7796_CLK_S2D1),
- DEF_MOD("du0", 724, R8A7796_CLK_S2D1),
- DEF_MOD("lvds", 727, R8A7796_CLK_S2D1),
- DEF_MOD("hdmi0", 729, R8A7796_CLK_HDMI),
- DEF_MOD("vin7", 804, R8A7796_CLK_S0D2),
- DEF_MOD("vin6", 805, R8A7796_CLK_S0D2),
- DEF_MOD("vin5", 806, R8A7796_CLK_S0D2),
- DEF_MOD("vin4", 807, R8A7796_CLK_S0D2),
- DEF_MOD("vin3", 808, R8A7796_CLK_S0D2),
- DEF_MOD("vin2", 809, R8A7796_CLK_S0D2),
- DEF_MOD("vin1", 810, R8A7796_CLK_S0D2),
- DEF_MOD("vin0", 811, R8A7796_CLK_S0D2),
- DEF_MOD("etheravb", 812, R8A7796_CLK_S0D6),
- DEF_MOD("imr1", 822, R8A7796_CLK_S0D2),
- DEF_MOD("imr0", 823, R8A7796_CLK_S0D2),
- DEF_MOD("gpio7", 905, R8A7796_CLK_S3D4),
- DEF_MOD("gpio6", 906, R8A7796_CLK_S3D4),
- DEF_MOD("gpio5", 907, R8A7796_CLK_S3D4),
- DEF_MOD("gpio4", 908, R8A7796_CLK_S3D4),
- DEF_MOD("gpio3", 909, R8A7796_CLK_S3D4),
- DEF_MOD("gpio2", 910, R8A7796_CLK_S3D4),
- DEF_MOD("gpio1", 911, R8A7796_CLK_S3D4),
- DEF_MOD("gpio0", 912, R8A7796_CLK_S3D4),
- DEF_MOD("can-fd", 914, R8A7796_CLK_S3D2),
- DEF_MOD("can-if1", 915, R8A7796_CLK_S3D4),
- DEF_MOD("can-if0", 916, R8A7796_CLK_S3D4),
- DEF_MOD("rpc", 917, R8A7796_CLK_RPC),
- DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6),
- DEF_MOD("i2c5", 919, R8A7796_CLK_S0D6),
- DEF_MOD("i2c-dvfs", 926, R8A7796_CLK_CP),
- DEF_MOD("i2c4", 927, R8A7796_CLK_S0D6),
- DEF_MOD("i2c3", 928, R8A7796_CLK_S0D6),
- DEF_MOD("i2c2", 929, R8A7796_CLK_S3D2),
- DEF_MOD("i2c1", 930, R8A7796_CLK_S3D2),
- DEF_MOD("i2c0", 931, R8A7796_CLK_S3D2),
- DEF_MOD("ssi-all", 1005, R8A7796_CLK_S3D4),
- DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
- DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
- DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
- DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
- DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
- DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
- DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
- DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
- DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
- DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
- DEF_MOD("scu-all", 1017, R8A7796_CLK_S3D4),
- DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
- DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
- DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
- DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
-};
-
-static const struct cpg_core_clk r8a77970_core_clks[] = {
- /* External Clock Inputs */
- DEF_INPUT("extal", CLK_EXTAL),
- DEF_INPUT("extalr", CLK_EXTALR),
-
- /* Internal Core Clocks */
- DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
- DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
- DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
- DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
-
- DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
- DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
- DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 4, 1),
- DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 6, 1),
- DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
-
- /* Core Clock Outputs */
- DEF_BASE("z2", R8A77970_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL1_DIV4),
- DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
- DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
- DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
- DEF_FIXED("zx", R8A77970_CLK_ZX, CLK_PLL1_DIV2, 3, 1),
- DEF_FIXED("s1d1", R8A77970_CLK_S1D1, CLK_S1, 1, 1),
- DEF_FIXED("s1d2", R8A77970_CLK_S1D2, CLK_S1, 2, 1),
- DEF_FIXED("s1d4", R8A77970_CLK_S1D4, CLK_S1, 4, 1),
- DEF_FIXED("s2d1", R8A77970_CLK_S2D1, CLK_S2, 1, 1),
- DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_S2, 2, 1),
- DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_S2, 4, 1),
-
- DEF_GEN3_SD("sd0", R8A77970_CLK_SD0, CLK_PLL1_DIV4, 0x0074),
-
- DEF_GEN3_RPC("rpc", R8A77970_CLK_RPC, CLK_RPCSRC, 0x238),
-
- DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1),
- DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1),
-
- /* NOTE: HDMI, CSI, CAN etc. clock are missing */
-
- DEF_BASE("r", R8A77970_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
-};
-
-static const struct mssr_mod_clk r8a77970_mod_clks[] = {
- DEF_MOD("ivcp1e", 127, R8A77970_CLK_S2D1),
- DEF_MOD("scif4", 203, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
- DEF_MOD("scif3", 204, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
- DEF_MOD("scif1", 206, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
- DEF_MOD("scif0", 207, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
- DEF_MOD("msiof3", 208, R8A77970_CLK_MSO),
- DEF_MOD("msiof2", 209, R8A77970_CLK_MSO),
- DEF_MOD("msiof1", 210, R8A77970_CLK_MSO),
- DEF_MOD("msiof0", 211, R8A77970_CLK_MSO),
- DEF_MOD("mfis", 213, R8A77970_CLK_S2D2), /* @@ H3=S3D2 */
- DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
- DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
- DEF_MOD("sdif", 314, R8A77970_CLK_SD0),
- DEF_MOD("rwdt0", 402, R8A77970_CLK_R),
- DEF_MOD("intc-ex", 407, R8A77970_CLK_CP),
- DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
- DEF_MOD("hscif3", 517, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
- DEF_MOD("hscif2", 518, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
- DEF_MOD("hscif1", 519, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
- DEF_MOD("hscif0", 520, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
- DEF_MOD("thermal", 522, R8A77970_CLK_CP),
- DEF_MOD("pwm", 523, R8A77970_CLK_S2D4),
- DEF_MOD("fcpvd0", 603, R8A77970_CLK_S2D1),
- DEF_MOD("vspd0", 623, R8A77970_CLK_S2D1),
- DEF_MOD("csi40", 716, R8A77970_CLK_CSI0),
- DEF_MOD("du0", 724, R8A77970_CLK_S2D1),
- DEF_MOD("lvds", 727, R8A77970_CLK_S2D1),
- DEF_MOD("vin3", 808, R8A77970_CLK_S2D1),
- DEF_MOD("vin2", 809, R8A77970_CLK_S2D1),
- DEF_MOD("vin1", 810, R8A77970_CLK_S2D1),
- DEF_MOD("vin0", 811, R8A77970_CLK_S2D1),
- DEF_MOD("etheravb", 812, R8A77970_CLK_S2D2),
- DEF_MOD("isp", 817, R8A77970_CLK_S2D1),
- DEF_MOD("gpio5", 907, R8A77970_CLK_CP),
- DEF_MOD("gpio4", 908, R8A77970_CLK_CP),
- DEF_MOD("gpio3", 909, R8A77970_CLK_CP),
- DEF_MOD("gpio2", 910, R8A77970_CLK_CP),
- DEF_MOD("gpio1", 911, R8A77970_CLK_CP),
- DEF_MOD("gpio0", 912, R8A77970_CLK_CP),
- DEF_MOD("can-fd", 914, R8A77970_CLK_S2D2),
- DEF_MOD("rpc", 917, R8A77970_CLK_RPC),
- DEF_MOD("i2c4", 927, R8A77970_CLK_S2D2),
- DEF_MOD("i2c3", 928, R8A77970_CLK_S2D2),
- DEF_MOD("i2c2", 929, R8A77970_CLK_S2D2),
- DEF_MOD("i2c1", 930, R8A77970_CLK_S2D2),
- DEF_MOD("i2c0", 931, R8A77970_CLK_S2D2),
-};
-
-static const struct cpg_core_clk r8a77995_core_clks[] = {
- /* External Clock Inputs */
- DEF_INPUT("extal", CLK_EXTAL),
-
- /* Internal Core Clocks */
- DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
- DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
- DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
-
- DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 4, 250),
- DEF_FIXED(".pll0d2", CLK_PLL0D2, CLK_PLL0, 2, 1),
- DEF_FIXED(".pll0d3", CLK_PLL0D3, CLK_PLL0, 3, 1),
- DEF_FIXED(".pll0d5", CLK_PLL0D5, CLK_PLL0, 5, 1),
- DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
- DEF_FIXED(".pe", CLK_PE, CLK_PLL0D3, 4, 1),
- DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
- DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
- DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
- DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
- DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
-
- /* Core Clock Outputs */
- DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1),
- DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
- DEF_FIXED("zt", R8A77995_CLK_ZT, CLK_PLL1, 4, 1),
- DEF_FIXED("zx", R8A77995_CLK_ZX, CLK_PLL1, 3, 1),
- DEF_FIXED("s0d1", R8A77995_CLK_S0D1, CLK_S0, 1, 1),
- DEF_FIXED("s1d1", R8A77995_CLK_S1D1, CLK_S1, 1, 1),
- DEF_FIXED("s1d2", R8A77995_CLK_S1D2, CLK_S1, 2, 1),
- DEF_FIXED("s1d4", R8A77995_CLK_S1D4, CLK_S1, 4, 1),
- DEF_FIXED("s2d1", R8A77995_CLK_S2D1, CLK_S2, 1, 1),
- DEF_FIXED("s2d2", R8A77995_CLK_S2D2, CLK_S2, 2, 1),
- DEF_FIXED("s2d4", R8A77995_CLK_S2D4, CLK_S2, 4, 1),
- DEF_FIXED("s3d1", R8A77995_CLK_S3D1, CLK_S3, 1, 1),
- DEF_FIXED("s3d2", R8A77995_CLK_S3D2, CLK_S3, 2, 1),
- DEF_FIXED("s3d4", R8A77995_CLK_S3D4, CLK_S3, 4, 1),
-
- DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1),
- DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1),
- DEF_FIXED("osc", R8A77995_CLK_OSC, CLK_EXTAL, 384, 1),
- DEF_FIXED("r", R8A77995_CLK_R, CLK_EXTAL, 1536, 1),
-
- DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2),
- DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
- DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
- DEF_GEN3_PE("s3d4c", R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
-
- DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, CLK_SDSRC, 0x268),
-};
-
-static const struct mssr_mod_clk r8a77995_mod_clks[] = {
- DEF_MOD("scif5", 202, R8A77995_CLK_S3D4C),
- DEF_MOD("scif4", 203, R8A77995_CLK_S3D4C),
- DEF_MOD("scif3", 204, R8A77995_CLK_S3D4C),
- DEF_MOD("scif1", 206, R8A77995_CLK_S3D4C),
- DEF_MOD("scif0", 207, R8A77995_CLK_S3D4C),
- DEF_MOD("msiof3", 208, R8A77995_CLK_MSO),
- DEF_MOD("msiof2", 209, R8A77995_CLK_MSO),
- DEF_MOD("msiof1", 210, R8A77995_CLK_MSO),
- DEF_MOD("msiof0", 211, R8A77995_CLK_MSO),
- DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1),
- DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1),
- DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1),
- DEF_MOD("cmt3", 300, R8A77995_CLK_R),
- DEF_MOD("cmt2", 301, R8A77995_CLK_R),
- DEF_MOD("cmt1", 302, R8A77995_CLK_R),
- DEF_MOD("cmt0", 303, R8A77995_CLK_R),
- DEF_MOD("scif2", 310, R8A77995_CLK_S3D4C),
- DEF_MOD("emmc0", 312, R8A77995_CLK_SD0),
- DEF_MOD("usb-dmac0", 330, R8A77995_CLK_S3D1),
- DEF_MOD("usb-dmac1", 331, R8A77995_CLK_S3D1),
- DEF_MOD("rwdt", 402, R8A77995_CLK_R),
- DEF_MOD("intc-ex", 407, R8A77995_CLK_CP),
- DEF_MOD("intc-ap", 408, R8A77995_CLK_S3D1),
- DEF_MOD("audmac0", 502, R8A77995_CLK_S3D1),
- DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C),
- DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C),
- DEF_MOD("thermal", 522, R8A77995_CLK_CP),
- DEF_MOD("pwm", 523, R8A77995_CLK_S3D4C),
- DEF_MOD("fcpvd1", 602, R8A77995_CLK_S1D2),
- DEF_MOD("fcpvd0", 603, R8A77995_CLK_S1D2),
- DEF_MOD("fcpvbs", 607, R8A77995_CLK_S0D1),
- DEF_MOD("vspd1", 622, R8A77995_CLK_S1D2),
- DEF_MOD("vspd0", 623, R8A77995_CLK_S1D2),
- DEF_MOD("vspbs", 627, R8A77995_CLK_S0D1),
- DEF_MOD("ehci0", 703, R8A77995_CLK_S3D2),
- DEF_MOD("hsusb", 704, R8A77995_CLK_S3D2),
- DEF_MOD("du1", 723, R8A77995_CLK_S2D1),
- DEF_MOD("du0", 724, R8A77995_CLK_S2D1),
- DEF_MOD("lvds", 727, R8A77995_CLK_S2D1),
- DEF_MOD("vin7", 804, R8A77995_CLK_S1D2),
- DEF_MOD("vin6", 805, R8A77995_CLK_S1D2),
- DEF_MOD("vin5", 806, R8A77995_CLK_S1D2),
- DEF_MOD("vin4", 807, R8A77995_CLK_S1D2),
- DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2),
- DEF_MOD("imr0", 823, R8A77995_CLK_S1D2),
- DEF_MOD("gpio6", 906, R8A77995_CLK_S3D4),
- DEF_MOD("gpio5", 907, R8A77995_CLK_S3D4),
- DEF_MOD("gpio4", 908, R8A77995_CLK_S3D4),
- DEF_MOD("gpio3", 909, R8A77995_CLK_S3D4),
- DEF_MOD("gpio2", 910, R8A77995_CLK_S3D4),
- DEF_MOD("gpio1", 911, R8A77995_CLK_S3D4),
- DEF_MOD("gpio0", 912, R8A77995_CLK_S3D4),
- DEF_MOD("can-fd", 914, R8A77995_CLK_S3D2),
- DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4),
- DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4),
- DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2),
- DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2),
- DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2),
- DEF_MOD("i2c0", 931, R8A77995_CLK_S3D2),
- DEF_MOD("ssi-all", 1005, R8A77995_CLK_S3D4),
- DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
- DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
- DEF_MOD("scu-all", 1017, R8A77995_CLK_S3D4),
- DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
- DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
- DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
- DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
-};
-
/*
* CPG Clock Data
*/
static int gen3_clk_get_mod(struct clk *clk, const struct mssr_mod_clk **mssr)
{
struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
+ struct cpg_mssr_info *info = priv->info;
const unsigned long clkid = clk->id & 0xffff;
int i;
if (!gen3_clk_is_mod(clk))
return -EINVAL;
- for (i = 0; i < priv->mod_clk_size; i++) {
- if (priv->mod_clk[i].id != MOD_CLK_ID(clkid))
+ for (i = 0; i < info->mod_clk_size; i++) {
+ if (info->mod_clk[i].id != MOD_CLK_ID(clkid))
continue;
- *mssr = &priv->mod_clk[i];
+ *mssr = &info->mod_clk[i];
return 0;
}
static int gen3_clk_get_core(struct clk *clk, const struct cpg_core_clk **core)
{
struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
+ struct cpg_mssr_info *info = priv->info;
const unsigned long clkid = clk->id & 0xffff;
int i;
if (gen3_clk_is_mod(clk))
return -EINVAL;
- for (i = 0; i < priv->core_clk_size; i++) {
- if (priv->core_clk[i].id != clkid)
+ for (i = 0; i < info->core_clk_size; i++) {
+ if (info->core_clk[i].id != clkid)
continue;
- *core = &priv->core_clk[i];
+ *core = &info->core_clk[i];
return 0;
}
return 0;
}
-static const struct clk_ops gen3_clk_ops = {
+const struct clk_ops gen3_clk_ops = {
.enable = gen3_clk_enable,
.disable = gen3_clk_disable,
.get_rate = gen3_clk_get_rate,
.of_xlate = gen3_clk_of_xlate,
};
-enum gen3_clk_model {
- CLK_R8A7795,
- CLK_R8A7796,
- CLK_R8A77970,
- CLK_R8A77995,
-};
-
-static int gen3_clk_probe(struct udevice *dev)
+int gen3_clk_probe(struct udevice *dev)
{
struct gen3_clk_priv *priv = dev_get_priv(dev);
- enum gen3_clk_model model = dev_get_driver_data(dev);
+ struct cpg_mssr_info *info =
+ (struct cpg_mssr_info *)dev_get_driver_data(dev);
fdt_addr_t rst_base;
u32 cpg_mode;
int ret;
if (!priv->base)
return -EINVAL;
- switch (model) {
- case CLK_R8A7795:
- priv->core_clk = r8a7795_core_clks;
- priv->core_clk_size = ARRAY_SIZE(r8a7795_core_clks);
- priv->mod_clk = r8a7795_mod_clks;
- priv->mod_clk_size = ARRAY_SIZE(r8a7795_mod_clks);
- ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
- "renesas,r8a7795-rst");
- if (ret < 0)
- return ret;
- break;
- case CLK_R8A7796:
- priv->core_clk = r8a7796_core_clks;
- priv->core_clk_size = ARRAY_SIZE(r8a7796_core_clks);
- priv->mod_clk = r8a7796_mod_clks;
- priv->mod_clk_size = ARRAY_SIZE(r8a7796_mod_clks);
- ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
- "renesas,r8a7796-rst");
- if (ret < 0)
- return ret;
- break;
- case CLK_R8A77970:
- priv->core_clk = r8a77970_core_clks;
- priv->core_clk_size = ARRAY_SIZE(r8a77970_core_clks);
- priv->mod_clk = r8a77970_mod_clks;
- priv->mod_clk_size = ARRAY_SIZE(r8a77970_mod_clks);
- ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
- "renesas,r8a77970-rst");
- if (ret < 0)
- return ret;
- break;
- case CLK_R8A77995:
- priv->core_clk = r8a77995_core_clks;
- priv->core_clk_size = ARRAY_SIZE(r8a77995_core_clks);
- priv->mod_clk = r8a77995_mod_clks;
- priv->mod_clk_size = ARRAY_SIZE(r8a77995_mod_clks);
- ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
- "renesas,r8a77995-rst");
- if (ret < 0)
- return ret;
- break;
- default:
- return -EINVAL;
- }
+ priv->info = info;
+ ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, info->reset_node);
+ if (ret < 0)
+ return ret;
rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg");
if (rst_base == FDT_ADDR_T_NONE)
if (ret < 0)
return ret;
- if (model != CLK_R8A77995) {
- ret = clk_get_by_name(dev, "extalr", &priv->clk_extalr);
+ if (info->extalr_node) {
+ ret = clk_get_by_name(dev, info->extalr_node, &priv->clk_extalr);
if (ret < 0)
return ret;
}
return 0;
}
-struct mstp_stop_table {
- u32 dis;
- u32 en;
-};
-
-static struct mstp_stop_table r8a7795_mstp_table[] = {
- { 0x00640800, 0x0 }, { 0xF3EE9390, 0x0 },
- { 0x340FAFDC, 0x2040 }, { 0xD80C7CDF, 0x400 },
- { 0x80000184, 0x180 }, { 0x40BFFF46, 0x0 },
- { 0xE5FBEECF, 0x0 }, { 0x39FFFF0E, 0x0 },
- { 0x01F19FF4, 0x0 }, { 0xFFDFFFFF, 0x0 },
- { 0xFFFEFFE0, 0x0 }, { 0x00000000, 0x0 },
-};
-
-static struct mstp_stop_table r8a7796_mstp_table[] = {
- { 0x00200000, 0x0 }, { 0xFFFFFFFF, 0x0 },
- { 0x340E2FDC, 0x2040 }, { 0xFFFFFFDF, 0x400 },
- { 0x80000184, 0x180 }, { 0xC3FFFFFF, 0x0 },
- { 0xFFFFFFFF, 0x0 }, { 0xFFFFFFFF, 0x0 },
- { 0x01F1FFF7, 0x0 }, { 0xFFFFFFFE, 0x0 },
- { 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 },
-};
-
-static struct mstp_stop_table r8a77970_mstp_table[] = {
- { 0x00230000, 0x0 }, { 0xFFFFFFFF, 0x0 },
- { 0x14062FD8, 0x2040 }, { 0xFFFFFFDF, 0x400 },
- { 0x80000184, 0x180 }, { 0x83FFFFFF, 0x0 },
- { 0xFFFFFFFF, 0x0 }, { 0xFFFFFFFF, 0x0 },
- { 0x7FF3FFF4, 0x0 }, { 0xFBF7FF97, 0x0 },
- { 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 },
-};
-
-static struct mstp_stop_table r8a77995_mstp_table[] = {
- { 0x00200000, 0x0 }, { 0xFFFFFFFF, 0x0 },
- { 0x340E2FDC, 0x2040 }, { 0xFFFFFFDF, 0x400 },
- { 0x80000184, 0x180 }, { 0xC3FFFFFF, 0x0 },
- { 0xFFFFFFFF, 0x0 }, { 0xFFFFFFFF, 0x0 },
- { 0x01F1FFF7, 0x0 }, { 0xFFFFFFFE, 0x0 },
- { 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 },
-};
-
-#define TSTR0 0x04
-#define TSTR0_STR0 BIT(0)
-
-static int gen3_clk_remove(struct udevice *dev)
+int gen3_clk_remove(struct udevice *dev)
{
struct gen3_clk_priv *priv = dev_get_priv(dev);
- enum gen3_clk_model model = dev_get_driver_data(dev);
- struct mstp_stop_table *tbl;
- unsigned int i, tbl_size;
-
- switch (model) {
- case CLK_R8A7795:
- tbl = r8a7795_mstp_table;
- tbl_size = ARRAY_SIZE(r8a7795_mstp_table);
- break;
- case CLK_R8A7796:
- tbl = r8a7796_mstp_table;
- tbl_size = ARRAY_SIZE(r8a7796_mstp_table);
- break;
- case CLK_R8A77970:
- tbl = r8a77970_mstp_table;
- tbl_size = ARRAY_SIZE(r8a77970_mstp_table);
- break;
- case CLK_R8A77995:
- tbl = r8a77995_mstp_table;
- tbl_size = ARRAY_SIZE(r8a77995_mstp_table);
- break;
- default:
- return -EINVAL;
- }
+ struct cpg_mssr_info *info = priv->info;
+ unsigned int i;
/* Stop TMU0 */
clrbits_le32(TMU_BASE + TSTR0, TSTR0_STR0);
/* Stop module clock */
- for (i = 0; i < tbl_size; i++) {
- clrsetbits_le32(priv->base + SMSTPCR(i), tbl[i].dis, tbl[i].en);
- clrsetbits_le32(priv->base + RMSTPCR(i), tbl[i].dis, 0x0);
+ for (i = 0; i < info->mstp_table_size; i++) {
+ clrsetbits_le32(priv->base + SMSTPCR(i),
+ info->mstp_table[i].dis,
+ info->mstp_table[i].en);
+ clrsetbits_le32(priv->base + RMSTPCR(i),
+ info->mstp_table[i].dis, 0x0);
}
return 0;
}
-
-static const struct udevice_id gen3_clk_ids[] = {
- { .compatible = "renesas,r8a7795-cpg-mssr", .data = CLK_R8A7795 },
- { .compatible = "renesas,r8a7796-cpg-mssr", .data = CLK_R8A7796 },
- { .compatible = "renesas,r8a77970-cpg-mssr", .data = CLK_R8A77970 },
- { .compatible = "renesas,r8a77995-cpg-mssr", .data = CLK_R8A77995 },
- { }
-};
-
-U_BOOT_DRIVER(clk_gen3) = {
- .name = "clk_gen3",
- .id = UCLASS_CLK,
- .of_match = gen3_clk_ids,
- .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
- .ops = &gen3_clk_ops,
- .probe = gen3_clk_probe,
- .remove = gen3_clk_remove,
-};
--- /dev/null
+/*
+ * Renesas R8A7795 CPG MSSR driver
+ *
+ * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Based on the following driver from Linux kernel:
+ * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2016 Glider bvba
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+
+#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+
+static const struct cpg_core_clk r8a7795_core_clks[] = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+ DEF_INPUT("extalr", CLK_EXTALR),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
+ DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
+ DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
+
+ DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+ DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
+ DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
+ DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
+ DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
+
+ /* Core Clock Outputs */
+ DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
+ DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
+ DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
+ DEF_FIXED("zx", R8A7795_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1),
+ DEF_FIXED("s0d2", R8A7795_CLK_S0D2, CLK_S0, 2, 1),
+ DEF_FIXED("s0d3", R8A7795_CLK_S0D3, CLK_S0, 3, 1),
+ DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1),
+ DEF_FIXED("s0d6", R8A7795_CLK_S0D6, CLK_S0, 6, 1),
+ DEF_FIXED("s0d8", R8A7795_CLK_S0D8, CLK_S0, 8, 1),
+ DEF_FIXED("s0d12", R8A7795_CLK_S0D12, CLK_S0, 12, 1),
+ DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1),
+ DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1),
+ DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1),
+ DEF_FIXED("s2d1", R8A7795_CLK_S2D1, CLK_S2, 1, 1),
+ DEF_FIXED("s2d2", R8A7795_CLK_S2D2, CLK_S2, 2, 1),
+ DEF_FIXED("s2d4", R8A7795_CLK_S2D4, CLK_S2, 4, 1),
+ DEF_FIXED("s3d1", R8A7795_CLK_S3D1, CLK_S3, 1, 1),
+ DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1),
+ DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1),
+
+ DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074),
+ DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078),
+ DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268),
+ DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c),
+
+ DEF_GEN3_RPC("rpc", R8A7795_CLK_RPC, CLK_RPCSRC, 0x238),
+
+ DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
+ DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
+
+ /* NOTE: HDMI, CSI, CAN etc. clock are missing */
+
+ DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
+};
+
+static const struct mssr_mod_clk r8a7795_mod_clks[] = {
+ DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */
+ DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),
+ DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
+ DEF_MOD("scif5", 202, R8A7795_CLK_S3D4),
+ DEF_MOD("scif4", 203, R8A7795_CLK_S3D4),
+ DEF_MOD("scif3", 204, R8A7795_CLK_S3D4),
+ DEF_MOD("scif1", 206, R8A7795_CLK_S3D4),
+ DEF_MOD("scif0", 207, R8A7795_CLK_S3D4),
+ DEF_MOD("msiof3", 208, R8A7795_CLK_MSO),
+ DEF_MOD("msiof2", 209, R8A7795_CLK_MSO),
+ DEF_MOD("msiof1", 210, R8A7795_CLK_MSO),
+ DEF_MOD("msiof0", 211, R8A7795_CLK_MSO),
+ DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S0D3),
+ DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S0D3),
+ DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3),
+ DEF_MOD("cmt3", 300, R8A7795_CLK_R),
+ DEF_MOD("cmt2", 301, R8A7795_CLK_R),
+ DEF_MOD("cmt1", 302, R8A7795_CLK_R),
+ DEF_MOD("cmt0", 303, R8A7795_CLK_R),
+ DEF_MOD("scif2", 310, R8A7795_CLK_S3D4),
+ DEF_MOD("sdif3", 311, R8A7795_CLK_SD3),
+ DEF_MOD("sdif2", 312, R8A7795_CLK_SD2),
+ DEF_MOD("sdif1", 313, R8A7795_CLK_SD1),
+ DEF_MOD("sdif0", 314, R8A7795_CLK_SD0),
+ DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1),
+ DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1),
+ DEF_MOD("usb-dmac30", 326, R8A7795_CLK_S3D1),
+ DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), /* ES1.x */
+ DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1),
+ DEF_MOD("usb-dmac31", 329, R8A7795_CLK_S3D1),
+ DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1),
+ DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1),
+ DEF_MOD("rwdt", 402, R8A7795_CLK_R),
+ DEF_MOD("intc-ex", 407, R8A7795_CLK_CP),
+ DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1),
+ DEF_MOD("audmac1", 501, R8A7795_CLK_S0D3),
+ DEF_MOD("audmac0", 502, R8A7795_CLK_S0D3),
+ DEF_MOD("drif7", 508, R8A7795_CLK_S3D2),
+ DEF_MOD("drif6", 509, R8A7795_CLK_S3D2),
+ DEF_MOD("drif5", 510, R8A7795_CLK_S3D2),
+ DEF_MOD("drif4", 511, R8A7795_CLK_S3D2),
+ DEF_MOD("drif3", 512, R8A7795_CLK_S3D2),
+ DEF_MOD("drif2", 513, R8A7795_CLK_S3D2),
+ DEF_MOD("drif1", 514, R8A7795_CLK_S3D2),
+ DEF_MOD("drif0", 515, R8A7795_CLK_S3D2),
+ DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1),
+ DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1),
+ DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
+ DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1),
+ DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
+ DEF_MOD("thermal", 522, R8A7795_CLK_CP),
+ DEF_MOD("pwm", 523, R8A7795_CLK_S0D12),
+ DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), /* ES1.x */
+ DEF_MOD("fcpvd2", 601, R8A7795_CLK_S0D2),
+ DEF_MOD("fcpvd1", 602, R8A7795_CLK_S0D2),
+ DEF_MOD("fcpvd0", 603, R8A7795_CLK_S0D2),
+ DEF_MOD("fcpvb1", 606, R8A7795_CLK_S0D1),
+ DEF_MOD("fcpvb0", 607, R8A7795_CLK_S0D1),
+ DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1), /* ES1.x */
+ DEF_MOD("fcpvi1", 610, R8A7795_CLK_S0D1),
+ DEF_MOD("fcpvi0", 611, R8A7795_CLK_S0D1),
+ DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), /* ES1.x */
+ DEF_MOD("fcpf1", 614, R8A7795_CLK_S0D1),
+ DEF_MOD("fcpf0", 615, R8A7795_CLK_S0D1),
+ DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1), /* ES1.x */
+ DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1), /* ES1.x */
+ DEF_MOD("fcpcs", 619, R8A7795_CLK_S0D1),
+ DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), /* ES1.x */
+ DEF_MOD("vspd2", 621, R8A7795_CLK_S0D2),
+ DEF_MOD("vspd1", 622, R8A7795_CLK_S0D2),
+ DEF_MOD("vspd0", 623, R8A7795_CLK_S0D2),
+ DEF_MOD("vspbc", 624, R8A7795_CLK_S0D1),
+ DEF_MOD("vspbd", 626, R8A7795_CLK_S0D1),
+ DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */
+ DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1),
+ DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1),
+ DEF_MOD("ehci3", 700, R8A7795_CLK_S3D4),
+ DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4),
+ DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4),
+ DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4),
+ DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4),
+ DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D4),
+ DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */
+ DEF_MOD("csi20", 714, R8A7795_CLK_CSI0),
+ DEF_MOD("csi41", 715, R8A7795_CLK_CSI0),
+ DEF_MOD("csi40", 716, R8A7795_CLK_CSI0),
+ DEF_MOD("du3", 721, R8A7795_CLK_S2D1),
+ DEF_MOD("du2", 722, R8A7795_CLK_S2D1),
+ DEF_MOD("du1", 723, R8A7795_CLK_S2D1),
+ DEF_MOD("du0", 724, R8A7795_CLK_S2D1),
+ DEF_MOD("lvds", 727, R8A7795_CLK_S0D4),
+ DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI),
+ DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI),
+ DEF_MOD("vin7", 804, R8A7795_CLK_S0D2),
+ DEF_MOD("vin6", 805, R8A7795_CLK_S0D2),
+ DEF_MOD("vin5", 806, R8A7795_CLK_S0D2),
+ DEF_MOD("vin4", 807, R8A7795_CLK_S0D2),
+ DEF_MOD("vin3", 808, R8A7795_CLK_S0D2),
+ DEF_MOD("vin2", 809, R8A7795_CLK_S0D2),
+ DEF_MOD("vin1", 810, R8A7795_CLK_S0D2),
+ DEF_MOD("vin0", 811, R8A7795_CLK_S0D2),
+ DEF_MOD("etheravb", 812, R8A7795_CLK_S0D6),
+ DEF_MOD("sata0", 815, R8A7795_CLK_S3D2),
+ DEF_MOD("imr3", 820, R8A7795_CLK_S0D2),
+ DEF_MOD("imr2", 821, R8A7795_CLK_S0D2),
+ DEF_MOD("imr1", 822, R8A7795_CLK_S0D2),
+ DEF_MOD("imr0", 823, R8A7795_CLK_S0D2),
+ DEF_MOD("gpio7", 905, R8A7795_CLK_S3D4),
+ DEF_MOD("gpio6", 906, R8A7795_CLK_S3D4),
+ DEF_MOD("gpio5", 907, R8A7795_CLK_S3D4),
+ DEF_MOD("gpio4", 908, R8A7795_CLK_S3D4),
+ DEF_MOD("gpio3", 909, R8A7795_CLK_S3D4),
+ DEF_MOD("gpio2", 910, R8A7795_CLK_S3D4),
+ DEF_MOD("gpio1", 911, R8A7795_CLK_S3D4),
+ DEF_MOD("gpio0", 912, R8A7795_CLK_S3D4),
+ DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2),
+ DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4),
+ DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4),
+ DEF_MOD("rpc", 917, R8A7795_CLK_RPC),
+ DEF_MOD("i2c6", 918, R8A7795_CLK_S0D6),
+ DEF_MOD("i2c5", 919, R8A7795_CLK_S0D6),
+ DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP),
+ DEF_MOD("i2c4", 927, R8A7795_CLK_S0D6),
+ DEF_MOD("i2c3", 928, R8A7795_CLK_S0D6),
+ DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2),
+ DEF_MOD("i2c1", 930, R8A7795_CLK_S3D2),
+ DEF_MOD("i2c0", 931, R8A7795_CLK_S3D2),
+ DEF_MOD("ssi-all", 1005, R8A7795_CLK_S3D4),
+ DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
+ DEF_MOD("scu-all", 1017, R8A7795_CLK_S3D4),
+ DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
+};
+
+static const struct mstp_stop_table r8a7795_mstp_table[] = {
+ { 0x00640800, 0x0 }, { 0xF3EE9390, 0x0 },
+ { 0x340FAFDC, 0x2040 }, { 0xD80C7CDF, 0x400 },
+ { 0x80000184, 0x180 }, { 0x40BFFF46, 0x0 },
+ { 0xE5FBEECF, 0x0 }, { 0x39FFFF0E, 0x0 },
+ { 0x01F19FF4, 0x0 }, { 0xFFDFFFFF, 0x0 },
+ { 0xFFFEFFE0, 0x0 }, { 0x00000000, 0x0 },
+};
+
+static const struct cpg_mssr_info r8a7795_cpg_mssr_info = {
+ .core_clk = r8a7795_core_clks,
+ .core_clk_size = ARRAY_SIZE(r8a7795_core_clks),
+ .mod_clk = r8a7795_mod_clks,
+ .mod_clk_size = ARRAY_SIZE(r8a7795_mod_clks),
+ .mstp_table = r8a7795_mstp_table,
+ .mstp_table_size = ARRAY_SIZE(r8a7795_mstp_table),
+ .reset_node = "renesas,r8a7795-rst",
+ .extalr_node = "extalr",
+};
+
+static const struct udevice_id r8a7795_clk_ids[] = {
+ {
+ .compatible = "renesas,r8a7795-cpg-mssr",
+ .data = (ulong)&r8a7795_cpg_mssr_info
+ },
+ { }
+};
+
+U_BOOT_DRIVER(clk_r8a7795) = {
+ .name = "clk_r8a7795",
+ .id = UCLASS_CLK,
+ .of_match = r8a7795_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
+ .ops = &gen3_clk_ops,
+ .probe = gen3_clk_probe,
+ .remove = gen3_clk_remove,
+};
--- /dev/null
+/*
+ * Renesas R8A7796 CPG MSSR driver
+ *
+ * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Based on the following driver from Linux kernel:
+ * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2016 Glider bvba
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+
+#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+
+static const struct cpg_core_clk r8a7796_core_clks[] = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+ DEF_INPUT("extalr", CLK_EXTALR),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
+ DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
+ DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
+
+ DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+ DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
+ DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
+ DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
+ DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
+
+ /* Core Clock Outputs */
+ DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
+ DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
+ DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
+ DEF_FIXED("zx", R8A7796_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED("s0d1", R8A7796_CLK_S0D1, CLK_S0, 1, 1),
+ DEF_FIXED("s0d2", R8A7796_CLK_S0D2, CLK_S0, 2, 1),
+ DEF_FIXED("s0d3", R8A7796_CLK_S0D3, CLK_S0, 3, 1),
+ DEF_FIXED("s0d4", R8A7796_CLK_S0D4, CLK_S0, 4, 1),
+ DEF_FIXED("s0d6", R8A7796_CLK_S0D6, CLK_S0, 6, 1),
+ DEF_FIXED("s0d8", R8A7796_CLK_S0D8, CLK_S0, 8, 1),
+ DEF_FIXED("s0d12", R8A7796_CLK_S0D12, CLK_S0, 12, 1),
+ DEF_FIXED("s1d1", R8A7796_CLK_S1D1, CLK_S1, 1, 1),
+ DEF_FIXED("s1d2", R8A7796_CLK_S1D2, CLK_S1, 2, 1),
+ DEF_FIXED("s1d4", R8A7796_CLK_S1D4, CLK_S1, 4, 1),
+ DEF_FIXED("s2d1", R8A7796_CLK_S2D1, CLK_S2, 1, 1),
+ DEF_FIXED("s2d2", R8A7796_CLK_S2D2, CLK_S2, 2, 1),
+ DEF_FIXED("s2d4", R8A7796_CLK_S2D4, CLK_S2, 4, 1),
+ DEF_FIXED("s3d1", R8A7796_CLK_S3D1, CLK_S3, 1, 1),
+ DEF_FIXED("s3d2", R8A7796_CLK_S3D2, CLK_S3, 2, 1),
+ DEF_FIXED("s3d4", R8A7796_CLK_S3D4, CLK_S3, 4, 1),
+
+ DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074),
+ DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078),
+ DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268),
+ DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c),
+
+ DEF_GEN3_RPC("rpc", R8A7796_CLK_RPC, CLK_RPCSRC, 0x238),
+
+ DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
+ DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1),
+
+ /* NOTE: HDMI, CSI, CAN etc. clock are missing */
+
+ DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
+};
+
+static const struct mssr_mod_clk r8a7796_mod_clks[] = {
+ DEF_MOD("scif5", 202, R8A7796_CLK_S3D4),
+ DEF_MOD("scif4", 203, R8A7796_CLK_S3D4),
+ DEF_MOD("scif3", 204, R8A7796_CLK_S3D4),
+ DEF_MOD("scif1", 206, R8A7796_CLK_S3D4),
+ DEF_MOD("scif0", 207, R8A7796_CLK_S3D4),
+ DEF_MOD("msiof3", 208, R8A7796_CLK_MSO),
+ DEF_MOD("msiof2", 209, R8A7796_CLK_MSO),
+ DEF_MOD("msiof1", 210, R8A7796_CLK_MSO),
+ DEF_MOD("msiof0", 211, R8A7796_CLK_MSO),
+ DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S0D3),
+ DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S0D3),
+ DEF_MOD("sys-dmac0", 219, R8A7796_CLK_S0D3),
+ DEF_MOD("cmt3", 300, R8A7796_CLK_R),
+ DEF_MOD("cmt2", 301, R8A7796_CLK_R),
+ DEF_MOD("cmt1", 302, R8A7796_CLK_R),
+ DEF_MOD("cmt0", 303, R8A7796_CLK_R),
+ DEF_MOD("scif2", 310, R8A7796_CLK_S3D4),
+ DEF_MOD("sdif3", 311, R8A7796_CLK_SD3),
+ DEF_MOD("sdif2", 312, R8A7796_CLK_SD2),
+ DEF_MOD("sdif1", 313, R8A7796_CLK_SD1),
+ DEF_MOD("sdif0", 314, R8A7796_CLK_SD0),
+ DEF_MOD("pcie1", 318, R8A7796_CLK_S3D1),
+ DEF_MOD("pcie0", 319, R8A7796_CLK_S3D1),
+ DEF_MOD("usb3-if0", 328, R8A7796_CLK_S3D1),
+ DEF_MOD("usb-dmac0", 330, R8A7796_CLK_S3D1),
+ DEF_MOD("usb-dmac1", 331, R8A7796_CLK_S3D1),
+ DEF_MOD("rwdt", 402, R8A7796_CLK_R),
+ DEF_MOD("intc-ex", 407, R8A7796_CLK_CP),
+ DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1),
+ DEF_MOD("audmac1", 501, R8A7796_CLK_S0D3),
+ DEF_MOD("audmac0", 502, R8A7796_CLK_S0D3),
+ DEF_MOD("drif7", 508, R8A7796_CLK_S3D2),
+ DEF_MOD("drif6", 509, R8A7796_CLK_S3D2),
+ DEF_MOD("drif5", 510, R8A7796_CLK_S3D2),
+ DEF_MOD("drif4", 511, R8A7796_CLK_S3D2),
+ DEF_MOD("drif3", 512, R8A7796_CLK_S3D2),
+ DEF_MOD("drif2", 513, R8A7796_CLK_S3D2),
+ DEF_MOD("drif1", 514, R8A7796_CLK_S3D2),
+ DEF_MOD("drif0", 515, R8A7796_CLK_S3D2),
+ DEF_MOD("hscif4", 516, R8A7796_CLK_S3D1),
+ DEF_MOD("hscif3", 517, R8A7796_CLK_S3D1),
+ DEF_MOD("hscif2", 518, R8A7796_CLK_S3D1),
+ DEF_MOD("hscif1", 519, R8A7796_CLK_S3D1),
+ DEF_MOD("hscif0", 520, R8A7796_CLK_S3D1),
+ DEF_MOD("thermal", 522, R8A7796_CLK_CP),
+ DEF_MOD("pwm", 523, R8A7796_CLK_S0D12),
+ DEF_MOD("fcpvd2", 601, R8A7796_CLK_S0D2),
+ DEF_MOD("fcpvd1", 602, R8A7796_CLK_S0D2),
+ DEF_MOD("fcpvd0", 603, R8A7796_CLK_S0D2),
+ DEF_MOD("fcpvb0", 607, R8A7796_CLK_S0D1),
+ DEF_MOD("fcpvi0", 611, R8A7796_CLK_S0D1),
+ DEF_MOD("fcpf0", 615, R8A7796_CLK_S0D1),
+ DEF_MOD("fcpci0", 617, R8A7796_CLK_S0D2),
+ DEF_MOD("fcpcs", 619, R8A7796_CLK_S0D2),
+ DEF_MOD("vspd2", 621, R8A7796_CLK_S0D2),
+ DEF_MOD("vspd1", 622, R8A7796_CLK_S0D2),
+ DEF_MOD("vspd0", 623, R8A7796_CLK_S0D2),
+ DEF_MOD("vspb", 626, R8A7796_CLK_S0D1),
+ DEF_MOD("vspi0", 631, R8A7796_CLK_S0D1),
+ DEF_MOD("ehci1", 702, R8A7796_CLK_S3D4),
+ DEF_MOD("ehci0", 703, R8A7796_CLK_S3D4),
+ DEF_MOD("hsusb", 704, R8A7796_CLK_S3D4),
+ DEF_MOD("csi20", 714, R8A7796_CLK_CSI0),
+ DEF_MOD("csi40", 716, R8A7796_CLK_CSI0),
+ DEF_MOD("du2", 722, R8A7796_CLK_S2D1),
+ DEF_MOD("du1", 723, R8A7796_CLK_S2D1),
+ DEF_MOD("du0", 724, R8A7796_CLK_S2D1),
+ DEF_MOD("lvds", 727, R8A7796_CLK_S2D1),
+ DEF_MOD("hdmi0", 729, R8A7796_CLK_HDMI),
+ DEF_MOD("vin7", 804, R8A7796_CLK_S0D2),
+ DEF_MOD("vin6", 805, R8A7796_CLK_S0D2),
+ DEF_MOD("vin5", 806, R8A7796_CLK_S0D2),
+ DEF_MOD("vin4", 807, R8A7796_CLK_S0D2),
+ DEF_MOD("vin3", 808, R8A7796_CLK_S0D2),
+ DEF_MOD("vin2", 809, R8A7796_CLK_S0D2),
+ DEF_MOD("vin1", 810, R8A7796_CLK_S0D2),
+ DEF_MOD("vin0", 811, R8A7796_CLK_S0D2),
+ DEF_MOD("etheravb", 812, R8A7796_CLK_S0D6),
+ DEF_MOD("imr1", 822, R8A7796_CLK_S0D2),
+ DEF_MOD("imr0", 823, R8A7796_CLK_S0D2),
+ DEF_MOD("gpio7", 905, R8A7796_CLK_S3D4),
+ DEF_MOD("gpio6", 906, R8A7796_CLK_S3D4),
+ DEF_MOD("gpio5", 907, R8A7796_CLK_S3D4),
+ DEF_MOD("gpio4", 908, R8A7796_CLK_S3D4),
+ DEF_MOD("gpio3", 909, R8A7796_CLK_S3D4),
+ DEF_MOD("gpio2", 910, R8A7796_CLK_S3D4),
+ DEF_MOD("gpio1", 911, R8A7796_CLK_S3D4),
+ DEF_MOD("gpio0", 912, R8A7796_CLK_S3D4),
+ DEF_MOD("can-fd", 914, R8A7796_CLK_S3D2),
+ DEF_MOD("can-if1", 915, R8A7796_CLK_S3D4),
+ DEF_MOD("can-if0", 916, R8A7796_CLK_S3D4),
+ DEF_MOD("rpc", 917, R8A7796_CLK_RPC),
+ DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6),
+ DEF_MOD("i2c5", 919, R8A7796_CLK_S0D6),
+ DEF_MOD("i2c-dvfs", 926, R8A7796_CLK_CP),
+ DEF_MOD("i2c4", 927, R8A7796_CLK_S0D6),
+ DEF_MOD("i2c3", 928, R8A7796_CLK_S0D6),
+ DEF_MOD("i2c2", 929, R8A7796_CLK_S3D2),
+ DEF_MOD("i2c1", 930, R8A7796_CLK_S3D2),
+ DEF_MOD("i2c0", 931, R8A7796_CLK_S3D2),
+ DEF_MOD("ssi-all", 1005, R8A7796_CLK_S3D4),
+ DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
+ DEF_MOD("scu-all", 1017, R8A7796_CLK_S3D4),
+ DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
+};
+
+static const struct mstp_stop_table r8a7796_mstp_table[] = {
+ { 0x00200000, 0x0 }, { 0xFFFFFFFF, 0x0 },
+ { 0x340E2FDC, 0x2040 }, { 0xFFFFFFDF, 0x400 },
+ { 0x80000184, 0x180 }, { 0xC3FFFFFF, 0x0 },
+ { 0xFFFFFFFF, 0x0 }, { 0xFFFFFFFF, 0x0 },
+ { 0x01F1FFF7, 0x0 }, { 0xFFFFFFFE, 0x0 },
+ { 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 },
+};
+
+static const struct cpg_mssr_info r8a7796_cpg_mssr_info = {
+ .core_clk = r8a7796_core_clks,
+ .core_clk_size = ARRAY_SIZE(r8a7796_core_clks),
+ .mod_clk = r8a7796_mod_clks,
+ .mod_clk_size = ARRAY_SIZE(r8a7796_mod_clks),
+ .mstp_table = r8a7796_mstp_table,
+ .mstp_table_size = ARRAY_SIZE(r8a7796_mstp_table),
+ .reset_node = "renesas,r8a7796-rst",
+ .extalr_node = "extalr",
+};
+
+static const struct udevice_id r8a7796_clk_ids[] = {
+ {
+ .compatible = "renesas,r8a7796-cpg-mssr",
+ .data = (ulong)&r8a7796_cpg_mssr_info,
+ },
+ { }
+};
+
+U_BOOT_DRIVER(clk_r8a7796) = {
+ .name = "clk_r8a7796",
+ .id = UCLASS_CLK,
+ .of_match = r8a7796_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
+ .ops = &gen3_clk_ops,
+ .probe = gen3_clk_probe,
+ .remove = gen3_clk_remove,
+};
--- /dev/null
+/*
+ * Renesas R8A77970 CPG MSSR driver
+ *
+ * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Based on the following driver from Linux kernel:
+ * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2016 Glider bvba
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+
+#include <dt-bindings/clock/r8a77970-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+
+static const struct cpg_core_clk r8a77970_core_clks[] = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+ DEF_INPUT("extalr", CLK_EXTALR),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
+
+ DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+ DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 4, 1),
+ DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 6, 1),
+ DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
+
+ /* Core Clock Outputs */
+ DEF_BASE("z2", R8A77970_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL1_DIV4),
+ DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
+ DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
+ DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
+ DEF_FIXED("zx", R8A77970_CLK_ZX, CLK_PLL1_DIV2, 3, 1),
+ DEF_FIXED("s1d1", R8A77970_CLK_S1D1, CLK_S1, 1, 1),
+ DEF_FIXED("s1d2", R8A77970_CLK_S1D2, CLK_S1, 2, 1),
+ DEF_FIXED("s1d4", R8A77970_CLK_S1D4, CLK_S1, 4, 1),
+ DEF_FIXED("s2d1", R8A77970_CLK_S2D1, CLK_S2, 1, 1),
+ DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_S2, 2, 1),
+ DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_S2, 4, 1),
+
+ DEF_GEN3_SD("sd0", R8A77970_CLK_SD0, CLK_PLL1_DIV4, 0x0074),
+
+ DEF_GEN3_RPC("rpc", R8A77970_CLK_RPC, CLK_RPCSRC, 0x238),
+
+ DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1),
+ DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1),
+
+ /* NOTE: HDMI, CSI, CAN etc. clock are missing */
+
+ DEF_BASE("r", R8A77970_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
+};
+
+static const struct mssr_mod_clk r8a77970_mod_clks[] = {
+ DEF_MOD("ivcp1e", 127, R8A77970_CLK_S2D1),
+ DEF_MOD("scif4", 203, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
+ DEF_MOD("scif3", 204, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
+ DEF_MOD("scif1", 206, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
+ DEF_MOD("scif0", 207, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
+ DEF_MOD("msiof3", 208, R8A77970_CLK_MSO),
+ DEF_MOD("msiof2", 209, R8A77970_CLK_MSO),
+ DEF_MOD("msiof1", 210, R8A77970_CLK_MSO),
+ DEF_MOD("msiof0", 211, R8A77970_CLK_MSO),
+ DEF_MOD("mfis", 213, R8A77970_CLK_S2D2), /* @@ H3=S3D2 */
+ DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
+ DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
+ DEF_MOD("sdif", 314, R8A77970_CLK_SD0),
+ DEF_MOD("rwdt0", 402, R8A77970_CLK_R),
+ DEF_MOD("intc-ex", 407, R8A77970_CLK_CP),
+ DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
+ DEF_MOD("hscif3", 517, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
+ DEF_MOD("hscif2", 518, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
+ DEF_MOD("hscif1", 519, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
+ DEF_MOD("hscif0", 520, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
+ DEF_MOD("thermal", 522, R8A77970_CLK_CP),
+ DEF_MOD("pwm", 523, R8A77970_CLK_S2D4),
+ DEF_MOD("fcpvd0", 603, R8A77970_CLK_S2D1),
+ DEF_MOD("vspd0", 623, R8A77970_CLK_S2D1),
+ DEF_MOD("csi40", 716, R8A77970_CLK_CSI0),
+ DEF_MOD("du0", 724, R8A77970_CLK_S2D1),
+ DEF_MOD("lvds", 727, R8A77970_CLK_S2D1),
+ DEF_MOD("vin3", 808, R8A77970_CLK_S2D1),
+ DEF_MOD("vin2", 809, R8A77970_CLK_S2D1),
+ DEF_MOD("vin1", 810, R8A77970_CLK_S2D1),
+ DEF_MOD("vin0", 811, R8A77970_CLK_S2D1),
+ DEF_MOD("etheravb", 812, R8A77970_CLK_S2D2),
+ DEF_MOD("isp", 817, R8A77970_CLK_S2D1),
+ DEF_MOD("gpio5", 907, R8A77970_CLK_CP),
+ DEF_MOD("gpio4", 908, R8A77970_CLK_CP),
+ DEF_MOD("gpio3", 909, R8A77970_CLK_CP),
+ DEF_MOD("gpio2", 910, R8A77970_CLK_CP),
+ DEF_MOD("gpio1", 911, R8A77970_CLK_CP),
+ DEF_MOD("gpio0", 912, R8A77970_CLK_CP),
+ DEF_MOD("can-fd", 914, R8A77970_CLK_S2D2),
+ DEF_MOD("rpc", 917, R8A77970_CLK_RPC),
+ DEF_MOD("i2c4", 927, R8A77970_CLK_S2D2),
+ DEF_MOD("i2c3", 928, R8A77970_CLK_S2D2),
+ DEF_MOD("i2c2", 929, R8A77970_CLK_S2D2),
+ DEF_MOD("i2c1", 930, R8A77970_CLK_S2D2),
+ DEF_MOD("i2c0", 931, R8A77970_CLK_S2D2),
+};
+
+static const struct mstp_stop_table r8a77970_mstp_table[] = {
+ { 0x00230000, 0x0 }, { 0xFFFFFFFF, 0x0 },
+ { 0x14062FD8, 0x2040 }, { 0xFFFFFFDF, 0x400 },
+ { 0x80000184, 0x180 }, { 0x83FFFFFF, 0x0 },
+ { 0xFFFFFFFF, 0x0 }, { 0xFFFFFFFF, 0x0 },
+ { 0x7FF3FFF4, 0x0 }, { 0xFBF7FF97, 0x0 },
+ { 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 },
+};
+
+static const struct cpg_mssr_info r8a77970_cpg_mssr_info = {
+ .core_clk = r8a77970_core_clks,
+ .core_clk_size = ARRAY_SIZE(r8a77970_core_clks),
+ .mod_clk = r8a77970_mod_clks,
+ .mod_clk_size = ARRAY_SIZE(r8a77970_mod_clks),
+ .mstp_table = r8a77970_mstp_table,
+ .mstp_table_size = ARRAY_SIZE(r8a77970_mstp_table),
+ .reset_node = "renesas,r8a77970-rst",
+ .extalr_node = "extalr",
+};
+
+static const struct udevice_id r8a77970_clk_ids[] = {
+ {
+ .compatible = "renesas,r8a77970-cpg-mssr",
+ .data = (ulong)&r8a77970_cpg_mssr_info
+ },
+ { }
+};
+
+U_BOOT_DRIVER(clk_r8a77970) = {
+ .name = "clk_r8a77970",
+ .id = UCLASS_CLK,
+ .of_match = r8a77970_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
+ .ops = &gen3_clk_ops,
+ .probe = gen3_clk_probe,
+ .remove = gen3_clk_remove,
+};
--- /dev/null
+/*
+ * Renesas R8A77995 CPG MSSR driver
+ *
+ * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Based on the following driver from Linux kernel:
+ * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2016 Glider bvba
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+
+#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+
+static const struct cpg_core_clk r8a77995_core_clks[] = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
+
+ DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 4, 250),
+ DEF_FIXED(".pll0d2", CLK_PLL0D2, CLK_PLL0, 2, 1),
+ DEF_FIXED(".pll0d3", CLK_PLL0D3, CLK_PLL0, 3, 1),
+ DEF_FIXED(".pll0d5", CLK_PLL0D5, CLK_PLL0, 5, 1),
+ DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
+ DEF_FIXED(".pe", CLK_PE, CLK_PLL0D3, 4, 1),
+ DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
+ DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
+ DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
+ DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
+ DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
+
+ /* Core Clock Outputs */
+ DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1),
+ DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
+ DEF_FIXED("zt", R8A77995_CLK_ZT, CLK_PLL1, 4, 1),
+ DEF_FIXED("zx", R8A77995_CLK_ZX, CLK_PLL1, 3, 1),
+ DEF_FIXED("s0d1", R8A77995_CLK_S0D1, CLK_S0, 1, 1),
+ DEF_FIXED("s1d1", R8A77995_CLK_S1D1, CLK_S1, 1, 1),
+ DEF_FIXED("s1d2", R8A77995_CLK_S1D2, CLK_S1, 2, 1),
+ DEF_FIXED("s1d4", R8A77995_CLK_S1D4, CLK_S1, 4, 1),
+ DEF_FIXED("s2d1", R8A77995_CLK_S2D1, CLK_S2, 1, 1),
+ DEF_FIXED("s2d2", R8A77995_CLK_S2D2, CLK_S2, 2, 1),
+ DEF_FIXED("s2d4", R8A77995_CLK_S2D4, CLK_S2, 4, 1),
+ DEF_FIXED("s3d1", R8A77995_CLK_S3D1, CLK_S3, 1, 1),
+ DEF_FIXED("s3d2", R8A77995_CLK_S3D2, CLK_S3, 2, 1),
+ DEF_FIXED("s3d4", R8A77995_CLK_S3D4, CLK_S3, 4, 1),
+
+ DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1),
+ DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1),
+ DEF_FIXED("osc", R8A77995_CLK_OSC, CLK_EXTAL, 384, 1),
+ DEF_FIXED("r", R8A77995_CLK_R, CLK_EXTAL, 1536, 1),
+
+ DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2),
+ DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
+ DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
+ DEF_GEN3_PE("s3d4c", R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
+
+ DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, CLK_SDSRC, 0x268),
+};
+
+static const struct mssr_mod_clk r8a77995_mod_clks[] = {
+ DEF_MOD("scif5", 202, R8A77995_CLK_S3D4C),
+ DEF_MOD("scif4", 203, R8A77995_CLK_S3D4C),
+ DEF_MOD("scif3", 204, R8A77995_CLK_S3D4C),
+ DEF_MOD("scif1", 206, R8A77995_CLK_S3D4C),
+ DEF_MOD("scif0", 207, R8A77995_CLK_S3D4C),
+ DEF_MOD("msiof3", 208, R8A77995_CLK_MSO),
+ DEF_MOD("msiof2", 209, R8A77995_CLK_MSO),
+ DEF_MOD("msiof1", 210, R8A77995_CLK_MSO),
+ DEF_MOD("msiof0", 211, R8A77995_CLK_MSO),
+ DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1),
+ DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1),
+ DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1),
+ DEF_MOD("cmt3", 300, R8A77995_CLK_R),
+ DEF_MOD("cmt2", 301, R8A77995_CLK_R),
+ DEF_MOD("cmt1", 302, R8A77995_CLK_R),
+ DEF_MOD("cmt0", 303, R8A77995_CLK_R),
+ DEF_MOD("scif2", 310, R8A77995_CLK_S3D4C),
+ DEF_MOD("emmc0", 312, R8A77995_CLK_SD0),
+ DEF_MOD("usb-dmac0", 330, R8A77995_CLK_S3D1),
+ DEF_MOD("usb-dmac1", 331, R8A77995_CLK_S3D1),
+ DEF_MOD("rwdt", 402, R8A77995_CLK_R),
+ DEF_MOD("intc-ex", 407, R8A77995_CLK_CP),
+ DEF_MOD("intc-ap", 408, R8A77995_CLK_S3D1),
+ DEF_MOD("audmac0", 502, R8A77995_CLK_S3D1),
+ DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C),
+ DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C),
+ DEF_MOD("thermal", 522, R8A77995_CLK_CP),
+ DEF_MOD("pwm", 523, R8A77995_CLK_S3D4C),
+ DEF_MOD("fcpvd1", 602, R8A77995_CLK_S1D2),
+ DEF_MOD("fcpvd0", 603, R8A77995_CLK_S1D2),
+ DEF_MOD("fcpvbs", 607, R8A77995_CLK_S0D1),
+ DEF_MOD("vspd1", 622, R8A77995_CLK_S1D2),
+ DEF_MOD("vspd0", 623, R8A77995_CLK_S1D2),
+ DEF_MOD("vspbs", 627, R8A77995_CLK_S0D1),
+ DEF_MOD("ehci0", 703, R8A77995_CLK_S3D2),
+ DEF_MOD("hsusb", 704, R8A77995_CLK_S3D2),
+ DEF_MOD("du1", 723, R8A77995_CLK_S2D1),
+ DEF_MOD("du0", 724, R8A77995_CLK_S2D1),
+ DEF_MOD("lvds", 727, R8A77995_CLK_S2D1),
+ DEF_MOD("vin7", 804, R8A77995_CLK_S1D2),
+ DEF_MOD("vin6", 805, R8A77995_CLK_S1D2),
+ DEF_MOD("vin5", 806, R8A77995_CLK_S1D2),
+ DEF_MOD("vin4", 807, R8A77995_CLK_S1D2),
+ DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2),
+ DEF_MOD("imr0", 823, R8A77995_CLK_S1D2),
+ DEF_MOD("gpio6", 906, R8A77995_CLK_S3D4),
+ DEF_MOD("gpio5", 907, R8A77995_CLK_S3D4),
+ DEF_MOD("gpio4", 908, R8A77995_CLK_S3D4),
+ DEF_MOD("gpio3", 909, R8A77995_CLK_S3D4),
+ DEF_MOD("gpio2", 910, R8A77995_CLK_S3D4),
+ DEF_MOD("gpio1", 911, R8A77995_CLK_S3D4),
+ DEF_MOD("gpio0", 912, R8A77995_CLK_S3D4),
+ DEF_MOD("can-fd", 914, R8A77995_CLK_S3D2),
+ DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4),
+ DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4),
+ DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2),
+ DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2),
+ DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2),
+ DEF_MOD("i2c0", 931, R8A77995_CLK_S3D2),
+ DEF_MOD("ssi-all", 1005, R8A77995_CLK_S3D4),
+ DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
+ DEF_MOD("scu-all", 1017, R8A77995_CLK_S3D4),
+ DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
+};
+
+static const struct mstp_stop_table r8a77995_mstp_table[] = {
+ { 0x00200000, 0x0 }, { 0xFFFFFFFF, 0x0 },
+ { 0x340E2FDC, 0x2040 }, { 0xFFFFFFDF, 0x400 },
+ { 0x80000184, 0x180 }, { 0xC3FFFFFF, 0x0 },
+ { 0xFFFFFFFF, 0x0 }, { 0xFFFFFFFF, 0x0 },
+ { 0x01F1FFF7, 0x0 }, { 0xFFFFFFFE, 0x0 },
+ { 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 },
+};
+
+static const struct cpg_mssr_info r8a77995_cpg_mssr_info = {
+ .core_clk = r8a77995_core_clks,
+ .core_clk_size = ARRAY_SIZE(r8a77995_core_clks),
+ .mod_clk = r8a77995_mod_clks,
+ .mod_clk_size = ARRAY_SIZE(r8a77995_mod_clks),
+ .mstp_table = r8a77995_mstp_table,
+ .mstp_table_size = ARRAY_SIZE(r8a77995_mstp_table),
+ .reset_node = "renesas,r8a77995-rst",
+};
+
+static const struct udevice_id r8a77995_clk_ids[] = {
+ {
+ .compatible = "renesas,r8a77995-cpg-mssr",
+ .data = (ulong)&r8a77995_cpg_mssr_info
+ },
+ { }
+};
+
+U_BOOT_DRIVER(clk_r8a77995) = {
+ .name = "clk_r8a77995",
+ .id = UCLASS_CLK,
+ .of_match = r8a77995_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
+ .ops = &gen3_clk_ops,
+ .probe = gen3_clk_probe,
+ .remove = gen3_clk_remove,
+};
--- /dev/null
+/*
+ * Renesas RCar Gen3 CPG MSSR driver
+ *
+ * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Based on the following driver from Linux kernel:
+ * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2016 Glider bvba
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DRIVERS_CLK_RENESAS_CPG_MSSR__
+#define __DRIVERS_CLK_RENESAS_CPG_MSSR__
+
+struct cpg_mssr_info {
+ const struct cpg_core_clk *core_clk;
+ unsigned int core_clk_size;
+ const struct mssr_mod_clk *mod_clk;
+ unsigned int mod_clk_size;
+ const struct mstp_stop_table *mstp_table;
+ unsigned int mstp_table_size;
+ const char *reset_node;
+ const char *extalr_node;
+};
+
+struct gen3_clk_priv {
+ void __iomem *base;
+ struct cpg_mssr_info *info;
+ struct clk clk_extal;
+ struct clk clk_extalr;
+ const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
+};
+
+/*
+ * Definitions of CPG Core Clocks
+ *
+ * These include:
+ * - Clock outputs exported to DT
+ * - External input clocks
+ * - Internal CPG clocks
+ */
+struct cpg_core_clk {
+ /* Common */
+ const char *name;
+ unsigned int id;
+ unsigned int type;
+ /* Depending on type */
+ unsigned int parent; /* Core Clocks only */
+ unsigned int div;
+ unsigned int mult;
+ unsigned int offset;
+};
+
+enum clk_types {
+ /* Generic */
+ CLK_TYPE_IN, /* External Clock Input */
+ CLK_TYPE_FF, /* Fixed Factor Clock */
+
+ /* Custom definitions start here */
+ CLK_TYPE_CUSTOM,
+};
+
+#define DEF_TYPE(_name, _id, _type...) \
+ { .name = _name, .id = _id, .type = _type }
+#define DEF_BASE(_name, _id, _type, _parent...) \
+ DEF_TYPE(_name, _id, _type, .parent = _parent)
+
+#define DEF_INPUT(_name, _id) \
+ DEF_TYPE(_name, _id, CLK_TYPE_IN)
+#define DEF_FIXED(_name, _id, _parent, _div, _mult) \
+ DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
+#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
+ DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
+#define DEF_GEN3_RPC(_name, _id, _parent, _offset) \
+ DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset)
+#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
+ _div_clean) \
+ DEF_BASE(_name, _id, CLK_TYPE_FF, \
+ (_parent_clean), .div = (_div_clean), 1)
+
+/*
+ * Definitions of Module Clocks
+ */
+struct mssr_mod_clk {
+ const char *name;
+ unsigned int id;
+ unsigned int parent; /* Add MOD_CLK_BASE for Module Clocks */
+};
+
+/* Convert from sparse base-100 to packed index space */
+#define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
+
+#define MOD_CLK_ID(x) (MOD_CLK_BASE + MOD_CLK_PACK(x))
+
+#define DEF_MOD(_name, _mod, _parent...) \
+ { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
+
+enum rcar_gen3_clk_types {
+ CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
+ CLK_TYPE_GEN3_PLL0,
+ CLK_TYPE_GEN3_PLL1,
+ CLK_TYPE_GEN3_PLL2,
+ CLK_TYPE_GEN3_PLL3,
+ CLK_TYPE_GEN3_PLL4,
+ CLK_TYPE_GEN3_SD,
+ CLK_TYPE_GEN3_RPC,
+ CLK_TYPE_GEN3_R,
+ CLK_TYPE_GEN3_PE,
+ CLK_TYPE_GEN3_Z2,
+};
+
+struct rcar_gen3_cpg_pll_config {
+ unsigned int extal_div;
+ unsigned int pll1_mult;
+ unsigned int pll3_mult;
+};
+
+#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R8A7796_CLK_OSC,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+ CLK_EXTALR,
+
+ /* Internal Core Clocks */
+ CLK_MAIN,
+ CLK_PLL0,
+ CLK_PLL1,
+ CLK_PLL2,
+ CLK_PLL3,
+ CLK_PLL4,
+ CLK_PLL1_DIV2,
+ CLK_PLL1_DIV4,
+ CLK_PLL0D2,
+ CLK_PLL0D3,
+ CLK_PLL0D5,
+ CLK_PLL1D2,
+ CLK_PE,
+ CLK_S0,
+ CLK_S1,
+ CLK_S2,
+ CLK_S3,
+ CLK_SDSRC,
+ CLK_RPCSRC,
+ CLK_SSPSRC,
+ CLK_RINT,
+
+ /* Module Clocks */
+ MOD_CLK_BASE
+};
+
+struct mstp_stop_table {
+ u32 dis;
+ u32 en;
+};
+
+#define TSTR0 0x04
+#define TSTR0_STR0 BIT(0)
+
+int gen3_clk_probe(struct udevice *dev);
+int gen3_clk_remove(struct udevice *dev);
+
+extern const struct clk_ops gen3_clk_ops;
+
+#endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */
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