void socfpga_per_reset(u32 reset, int set);
void socfpga_per_reset_all(void);
-#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
-#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
-#else
#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
-#endif
/*
* Define a reset identifier, from which a permodrst bank ID
setbits_le32(&scu_regs->sacr, 0xfff);
/* Configure the L2 controller to make SDRAM start at 0 */
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
- writel(0x2, &nic301_regs->remap);
-#else
writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
writel(0x1, &pl310->pl310_addr_filter_start);
-#endif
/* Add device descriptor to FPGA device table */
socfpga_fpga_add();
setbits_le32(&reset_manager_base->per0modrst, mask_ecc_ocp);
}
-#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
-int socfpga_bridges_reset(void)
-{
- /* For SoCFPGA-VT, this is NOP. */
- return 0;
-}
-#else
int socfpga_bridges_reset(void)
{
int ret;
return 0;
}
-#endif
writel(0, &reset_manager_base->per_mod_reset);
}
-#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
-void socfpga_bridges_reset(int enable)
-{
- /* For SoCFPGA-VT, this is NOP. */
- return;
-}
-#else
-
#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
#define L3REGS_REMAP_HPS2FPGA_MASK 0x08
#define L3REGS_REMAP_OCRAM_MASK 0x01
}
return;
}
-#endif
void board_init_f(ulong dummy)
{
-#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
const struct cm_config *cm_default_cfg = cm_get_default_config();
-#endif
unsigned long sdram_size;
unsigned long reg;
writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
writel(0x1, &pl310->pl310_addr_filter_start);
-#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
debug("Freezing all I/O banks\n");
/* freeze all IO banks */
sys_mgr_frzctrl_freeze_req();
sysmgr_pinmux_init();
sysmgr_config_warmrstcfgio(0);
-#endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
-
/* De-assert reset for peripherals and bridges based on handoff */
reset_deassert_peripherals_handoff();
socfpga_bridges_reset(0);
#ifndef __CONFIG_SOCFPGA_COMMON_H__
#define __CONFIG_SOCFPGA_COMMON_H__
-/* Virtual target or real hardware */
-#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
-
/*
* High level configuration
*/
/*
* Ethernet on SoC (EMAC)
*/
-#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
+#ifdef CONFIG_CMD_NET
#define CONFIG_DW_ALTDESCRIPTOR
#define CONFIG_MII
#endif
#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_SYS_TIMER_RATE 2400000
-#else
#define CONFIG_SYS_TIMER_RATE 25000000
-#endif
/*
* L4 Watchdog
*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_SYS_NS16550_CLK 1000000
-#elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS
#define CONFIG_SYS_NS16550_CLK 100000000
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
CONFIG_SMSTP7_ENA
CONFIG_SMSTP8_ENA
CONFIG_SMSTP9_ENA
-CONFIG_SOCFPGA_VIRTUAL_TARGET
CONFIG_SOCRATES
CONFIG_SOC_AU1000
CONFIG_SOC_AU1100