]> git.sur5r.net Git - u-boot/commitdiff
net: sh-eth: Add cache writeback control after setting bit of DMA descriptor
authorNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Tue, 4 Nov 2014 00:15:48 +0000 (09:15 +0900)
committerNobuhiro Iwamatsu <iwamatsu@nigauri.org>
Tue, 4 Nov 2014 00:28:47 +0000 (09:28 +0900)
A bit field of DMA descriptor is on memory area of DMA. If we set data
to bit of DMA descriptor, we must be writeback data of DMA descriptor.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
drivers/net/sh_eth.c

index d1d3b6898dd433849d1cfa082f13638d60851475..4bf493ed4532688bd5c8f40cd80e04b1cea4bc4e 100644 (file)
@@ -2,9 +2,9 @@
  * sh_eth.c - Driver for Renesas ethernet controler.
  *
  * Copyright (C) 2008, 2011 Renesas Solutions Corp.
- * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
+ * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
  * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
- * Copyright (C) 2013  Renesas Electronics Corporation
+ * Copyright (C) 2013, 2014 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -83,6 +83,8 @@ int sh_eth_send(struct eth_device *dev, void *packet, int len)
        else
                port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
 
+       flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s));
+
        /* Restart the transmitter if disabled */
        if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS))
                sh_eth_write(eth, EDTRR_TRNS, EDTRR);
@@ -133,6 +135,10 @@ int sh_eth_recv(struct eth_device *dev)
                        port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
                else
                        port_info->rx_desc_cur->rd0 = RD_RACT;
+
+               flush_cache_wback(port_info->rx_desc_cur,
+                                 sizeof(struct rx_desc_s));
+
                /* Point to the next descriptor */
                port_info->rx_desc_cur++;
                if (port_info->rx_desc_cur >=