when DDR driver is used:
DDR + 1MB (0xC0100000)
+source "board/st/stm32mp1/Kconfig"
+
endif
--- /dev/null
+if TARGET_STM32MP1
+
+config SYS_BOARD
+ default "stm32mp1"
+
+config SYS_VENDOR
+ default "st"
+
+config SYS_CONFIG_NAME
+ default "stm32mp1"
+
+endif
--- /dev/null
+STM32MP1 BOARD
+M: Patrick Delaunay <patrick.delaunay@st.com>
+S: Maintained
+F: board/st/stm32mp1
+F: include/configs/stm32mp1.h
+F: configs/stm32mp15_basic_defconfig
+F: arch/arm/dts/stm32mp157*
--- /dev/null
+#
+# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+#
+# SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
+obj-y += stm32mp1.o
+endif
+
+obj-y += board.o
--- /dev/null
+#
+# Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+#
+# SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+#
+
+U-Boot on STMicroelectronics STM32MP1
+======================================
+
+1. Summary
+==========
+This is a quick instruction for setup stm32mp1 boards.
+
+2. Supported devices
+====================
+U-Boot supports one STMP32MP1 SoCs: STM32MP157
+
+The STM32MP157 is a Cortex-A MPU aimed at various applications.
+It features:
+- Dual core Cortex-A7 application core
+- 2D/3D image composition with GPU
+- Standard memories interface support
+- Standard connectivity, widely inherited from the STM32 MCU family
+- Comprehensive security support
+
+Everything is supported in Linux but U-Boot is limited to:
+1. UART
+2. SDCard/MMC controller (SDMMC)
+
+And the necessary drivers
+1. I2C
+2. STPMU1
+3. Clock, Reset
+
+Currently the following boards are supported:
++ stm32mp157c-ed1
+
+3. Boot Sequences
+=================
+
+BootRom => FSBL in SYSRAM => SSBL in DDR => OS (Linux Kernel)
+
+with FSBL = First Stage Bootloader
+ SSBL = Second Stage Bootloader
+
+One boot configuration is supported:
+
+ The "Basic" boot chain (defconfig_file : stm32mp15_basic_defconfig)
+ BootRom => FSBL = U-Boot SPL => SSBL = U-Boot
+ SPL has limited security initialisation
+ U-Boot is running in secure mode and provide a secure monitor to the kernel
+ with only PSCI support (Power State Coordination Interface defined by ARM)
+
+All the STM32MP1 board supported by U-Boot use the same generic board
+stm32mp1 which support all the bootable devices.
+
+Each board is configurated only with the associated device tree.
+
+4. Device Tree Selection
+========================
+
+You need to select the appropriate device tree for your board,
+the supported device trees for stm32mp157 are:
+
++ ed1: daughter board with pmic stpmu1
+ dts: stm32mp157c-ed1
+
+5. Build Procedure
+==================
+
+1. Install required tools for U-Boot
+
+ + install package needed in U-Boot makefile
+ (libssl-dev, swig, libpython-dev...)
+ + install ARMv7 toolchain for 32bit Cortex-A (from Linaro,
+ from SDK for STM32MP1, or any crosstoolchains from your distribution)
+
+2. Set the cross compiler:
+
+ # export CROSS_COMPILE=/path/to/toolchain/arm-linux-gnueabi-
+ (you can use any gcc cross compiler compatible with U-Boot)
+
+3. Select the output directory (optional)
+
+ # export KBUILD_OUTPUT=/path/to/output
+
+ for example: use one output directory for each configuration
+ # export KBUILD_OUTPUT=stm32mp15_basic
+
+4. Configure the U-Boot:
+
+ # make <defconfig_file>
+
+ - For basic boot mode: "stm32mp15_basic_defconfig"
+
+5. Configure the device-tree and build the U-Boot image:
+
+ # make DEVICE_TREE=<name> all
+
+
+ example:
+ basic boot on ed1
+ # export KBUILD_OUTPUT=stm32mp15_basic
+ # make stm32mp15_basic_defconfig
+ # make DEVICE_TREE=stm32mp157c-ed1 all
+
+6. Output files
+
+ BootRom and ATF expect binaries with STM32 image header
+ SPL expects file with U-Boot uImage header
+
+ So in the output directory (selected by KBUILD_OUTPUT),
+ you can found the needed files:
+
+ + FSBL = spl/u-boot-spl.stm32
+ + SSBL = u-boot.img
+
+6. Prepare an SDCard
+===================
+
+The minimal requirements for STMP32MP1 boot up to U-Boot are:
+- GPT partitioning (with gdisk or with sgdisk)
+- 2 fsbl partitions, named fsbl1 and fsbl2, size at least 256KiB
+- one ssbl partition for U-Boot
+
+Then the minimal GPT partition is:
+ ----- ------- --------- -------------
+ | Num | Name | Size | Content |
+ ----- ------- -------- --------------
+ | 1 | fsbl1 | 256 KiB | ATF or SPL |
+ | 2 | fsbl2 | 256 KiB | ATF or SPL |
+ | 3 | ssbl | enought | U-Boot |
+ | * | - | - | Boot/Rootfs|
+ ----- ------- --------- -------------
+
+(*) add bootable partition for extlinux.conf
+ following Generic Distribution
+ (doc/README.distro for use)
+
+ according the used card reader select the block device
+ (/dev/sdx or /dev/mmcblk0)
+ in the next example I use /dev/mmcblk0
+
+for example: with gpt table with 128 entries
+
+ a) remove previous formatting
+ # sgdisk -o /dev/<SDCard dev>
+
+ b) create minimal image
+ # sgdisk --resize-table=128 -a 1 \
+ -n 1:34:545 -c 1:fsbl1 \
+ -n 2:546:1057 -c 2:fsbl2 \
+ -n 3:1058:5153 -c 3:ssbl \
+ -p /dev/<SDCard dev>
+
+ you can add other partition for kernel (rootfs)
+
+ c) copy the FSBL (2 times) and SSBL file on the correct partition.
+ in this example in partition 1 to 3
+
+ for basic boot mode : <SDCard dev> = /dev/mmcblk0
+ # dd if=u-boot-spl.stm32 of=/dev/mmcblk0p1
+ # dd if=u-boot-spl.stm32 of=/dev/mmcblk0p2
+ # dd if=u-boot.img of=/dev/mmcblk0p3
+
+7. Switch Setting
+==================
+
+You can select the boot mode, on the board ed1 with the switch SW1
+
+ -----------------------------------
+ Boot Mode BOOT2 BOOT1 BOOT0
+ -----------------------------------
+ Reserved 0 0 0
+ NOR 0 0 1
+ SD-Card 1 1 1
+ SD-Card 1 0 1
+ eMMC 0 1 0
+ NAND 0 1 1
+ Recovery 1 1 0
+ Recovery 0 0 0
+
+
+To boot from SDCard, select BootPinMode = 1 1 1 and reset.
+
+Recovery is a boot from serial link (UART/USB) and it is used with
+STM32CubeProgrammer tool to load executable in RAM and to update the flash
+devices available on the board (NOR/NAND/eMMC/SDCARD).
+The communication between HOST and board is based on
+- for UARTs : the uart protocol used with all MCU STM32
+- for USB : based on USB DFU 1.1 (without the ST extensions used on MCU STM32)
--- /dev/null
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <power/pmic.h>
+#include <power/stpmu1.h>
+
+#ifdef CONFIG_PMIC_STPMU1
+int board_ddr_power_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_PMIC,
+ DM_GET_DRIVER(pmic_stpmu1), &dev);
+ if (ret)
+ /* No PMIC on board */
+ return 0;
+
+ /* Set LDO3 to sync mode */
+ ret = pmic_reg_read(dev, STPMU1_LDOX_CTRL_REG(STPMU1_LDO3));
+ if (ret < 0)
+ return ret;
+
+ ret &= ~STPMU1_LDO3_MODE;
+ ret &= ~STPMU1_LDO12356_OUTPUT_MASK;
+ ret |= STPMU1_LDO3_DDR_SEL << STPMU1_LDO12356_OUTPUT_SHIFT;
+
+ ret = pmic_reg_write(dev, STPMU1_LDOX_CTRL_REG(STPMU1_LDO3),
+ ret);
+ if (ret < 0)
+ return ret;
+
+ /* Set BUCK2 to 1.35V */
+ ret = pmic_clrsetbits(dev,
+ STPMU1_BUCKX_CTRL_REG(STPMU1_BUCK2),
+ STPMU1_BUCK_OUTPUT_MASK,
+ STPMU1_BUCK2_1350000V);
+ if (ret < 0)
+ return ret;
+
+ /* Enable BUCK2 and VREF */
+ ret = pmic_clrsetbits(dev,
+ STPMU1_BUCKX_CTRL_REG(STPMU1_BUCK2),
+ STPMU1_BUCK_EN, STPMU1_BUCK_EN);
+ if (ret < 0)
+ return ret;
+
+ mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
+
+ ret = pmic_clrsetbits(dev, STPMU1_VREF_CTRL_REG,
+ STPMU1_VREF_EN, STPMU1_VREF_EN);
+ if (ret < 0)
+ return ret;
+
+ mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
+
+ /* Enable LDO3 */
+ ret = pmic_clrsetbits(dev,
+ STPMU1_LDOX_CTRL_REG(STPMU1_LDO3),
+ STPMU1_LDO_EN, STPMU1_LDO_EN);
+ if (ret < 0)
+ return ret;
+
+ mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
+
+ return 0;
+}
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#include <config.h>
+#include <common.h>
+#include <spl.h>
+#include <dm.h>
+#include <ram.h>
+#include <asm/io.h>
+#include <post.h>
+#include <power/pmic.h>
+#include <power/stpmu1.h>
+#include <asm/arch/ddr.h>
+
+void spl_board_init(void)
+{
+ /* Keep vdd on during the reset cycle */
+#if defined(CONFIG_PMIC_STPMU1) && defined(CONFIG_SPL_POWER_SUPPORT)
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_PMIC,
+ DM_GET_DRIVER(pmic_stpmu1), &dev);
+ if (!ret)
+ pmic_clrsetbits(dev,
+ STPMU1_MASK_RESET_BUCK,
+ STPMU1_MASK_RESET_BUCK3,
+ STPMU1_MASK_RESET_BUCK3);
+#endif
+}
--- /dev/null
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+#include <config.h>
+#include <common.h>
+#include <asm/arch/stm32.h>
+
+/*
+ * Get a global data pointer
+ */
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+/* board dependent setup after realloc */
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
+
+ return 0;
+}
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_STM32MP=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_TARGET_STM32MP1=y
+CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ed1"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SYS_PROMPT="STM32MP> "
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_STM32F7=y
+CONFIG_DM_MMC=y
+CONFIG_STM32_SDMMC2=y
+# CONFIG_SPL_PINCTRL_FULL is not set
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_STPMU1=y
+CONFIG_STM32_SERIAL=y
+# CONFIG_EFI_LOADER is not set
--- /dev/null
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * Configuration settings for the STM32MP15x CPU
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <linux/sizes.h>
+#include <asm/arch/stm32.h>
+
+#define CONFIG_PREBOOT
+
+/*
+ * Number of clock ticks in 1 sec
+ */
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_ARCH_TIMER
+#define CONFIG_SYS_HZ_CLOCK 64000000
+
+/*
+ * malloc() pool size
+ */
+#define CONFIG_SYS_MALLOC_LEN SZ_32M
+
+/*
+ * Configuration of the external SRAM memory used by U-Boot
+ */
+#define CONFIG_SYS_SDRAM_BASE STM32_DDR_BASE
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_NR_DRAM_BANKS 1
+
+/*
+ * Console I/O buffer size
+ */
+#define CONFIG_SYS_CBSIZE SZ_1K
+
+/*
+ * Needed by "loadb"
+ */
+#define CONFIG_SYS_LOAD_ADDR STM32_DDR_BASE
+
+/*
+ * Env parameters
+ */
+#define CONFIG_ENV_SIZE SZ_4K
+
+/* ATAGs */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/* SPL support */
+#ifdef CONFIG_SPL
+/* BOOTROM load address */
+#define CONFIG_SPL_TEXT_BASE 0x2FFC2500
+/* SPL use DDR */
+#define CONFIG_SPL_BSS_START_ADDR 0xC0200000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
+#define CONFIG_SYS_SPL_MALLOC_START 0xC0300000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
+
+/* limit SYSRAM usage to first 128 KB */
+#define CONFIG_SPL_MAX_SIZE 0x00020000
+#define CONFIG_SPL_STACK (STM32_SYSRAM_BASE + \
+ STM32_SYSRAM_SIZE)
+#endif /* #ifdef CONFIG_SPL */
+
+/*MMC SD*/
+#define CONFIG_SYS_MMC_MAX_DEVICE 3
+
+#if !defined(CONFIG_SPL) || !defined(CONFIG_SPL_BUILD)
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 0) \
+ func(MMC, mmc, 2)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "scriptaddr=0xC0000000\0" \
+ "pxefile_addr_r=0xC0000000\0" \
+ "kernel_addr_r=0xC1000000\0" \
+ "fdt_addr_r=0xC4000000\0" \
+ "ramdisk_addr_r=0xC4100000\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ BOOTENV
+
+#endif /* ifndef CONFIG_SPL_BUILD */
+
+#endif /* __CONFIG_H */
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