+commit f30ad49b16bf998b03c1a5228b6c86369d61c258
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Mon Nov 19 10:02:13 2007 -0500
+
+ Move CONFIG_QE out of CONFIG_PCI wrap for MPC8568MDS
+
+ CONFIG_QE shouldn't be in the wrap of CONFIG_PCI, fix it.
+
+ Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+
+commit f8c320609366176b31104d9bf5e295232e1c7f1d
+Author: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+Date: Mon Nov 19 11:14:16 2007 +0900
+
+ [MIPS] board/gth2/lowlevel_init.S: Fix a build warning
+
+ lowlevel_init.S: Assembler messages:
+ lowlevel_init.S:413: Warning: Pretending global symbol used as branch target is local.
+
+ Looking at codes, the `memtest' and `clearmem' are intentional mixed
+ use of `global symbols' and `label' for debugging purpose. To make it
+ build, just disable global-symbols-use for now. As a result `memtest'
+ still remains as unused, but leave it be...
+
+ Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
+
+commit e8da58f2bc092891e8cc92b927ed5c4bd0cb0cab
+Author: Wolfgang Denk <wd@denx.de>
+Date: Mon Nov 19 12:59:14 2007 +0100
+
+ Fix build problems with mp2usb board
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 6bf4c686afca1e86e1c384d59218f914605713bf
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sun Nov 18 18:36:11 2007 +0100
+
+ s3c24x0: Fix usb_ohci.c missing in Makefile
+ and usb_ohci.c warning differ in signedness
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 6073f61e078da5ddb521b56256bcc36508589883
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sun Nov 18 12:55:02 2007 +0100
+
+ pb1x00 board: Fix u16 status declaration when PCMCIA is defined
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 8412d814ce8bf5570a2b747f1e7fd321097fe987
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Nov 18 17:11:09 2007 +0100
+
+ Fix compiler warnings for ARM systems.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 409ecdc0bb47dd28b0af6c25ffd658d22cc36b37
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Nov 18 16:36:27 2007 +0100
+
+ Fix compiler warnings for PPC systems. Update CHANGELOG.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 079c2c4fa71c0d1ebef394508df9088df8a308d3
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat Nov 17 11:31:10 2007 +0100
+
+ Fix warning differ in signedness in net/net.c and net/nfs.c
+
+commit 7e14fc65368cbd2861b1207453da55a4fc7b3f81
+Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+Date: Sat Nov 17 20:42:45 2007 +0900
+
+ gth2.c: Fix a warning on gth2 build.
+
+ gth2.c: In function 'misc_init_r':
+ gth2.c:434: warning: pointer targets in passing argument 2 of 'setenv' differ in signedness
+
+ Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit 2309c130aa4c84b91bd874a41269c923eb61b555
+Author: Stefan Roese <sr@denx.de>
+Date: Sat Nov 17 07:58:25 2007 +0100
+
+ Fix warning differ in signedness in common/cmd_scsi.c
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 7e1d884b7cb602007329c517ec1c453e3a6a5d9c
+Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+Date: Sat Nov 17 20:05:26 2007 +0900
+
+ [MIPS] cpu/mips/config.mk: Fix GNU assembler minor version picker
+
+ Current trick to pick up GNU assembler minor version does not work with the
+ latest binutils (2007-03-01 or later) due to ${PKGVERSION} now default to
+ "(GNU Binutils) ".
+
+ $ sde-as --version |grep "GNU assembler"
+ GNU assembler 2.15.94 mipssde-6.02.02-20050602
+ $ sde-as --version |grep "GNU assembler" |awk '{print $3}'
+ 2.15.94
+ $ sde-as --version |grep "GNU assembler" |awk '{print $3}' |awk -F. '{print $2}'
+ 15
+ $
+
+ $ mips-linux-as --version |grep "GNU assembler"
+ GNU assembler (GNU Binutils) 2.18
+ $ mips-linux-as --version |grep "GNU assembler" |awk '{print $3}'
+ (GNU
+ $ mips-linux-as --version |grep "GNU assembler" |awk '{print $3}' |awk -F. '{print $2}'
+ (no output)
+ $
+
+ As a result of above, you'll see many noises with such binutils:
+
+ make -C cpu/mips/
+ /bin/sh: line 0: [: : integer expression expected
+ /bin/sh: line 0: [: : integer expression expected
+ make[1]: Entering directory `/home/skuribay/devel/u-boot.git/cpu/mips'
+ mips-linux-gcc -D__ASSEMBLY__ -g -Os -D__KERNEL__ -DTEXT_BASE=0xB0000000 -I/home/skuribay/devel/u-boot.git/include -fno-builtin -ffreestanding -nostdinc -isystem /home/skuribay/devel/buildroot/build_mips/staging_dir/usr/bin/../lib/gcc/mips-linux-uclibc/4.2.1/include -pipe -DCONFIG_MIPS -D__MIPS__ -G 0 -mabicalls -fpic -pipe -msoft-float -march=4kc -mtune=4kc -EB -c -o incaip_wdt.o incaip_wdt.S
+ /bin/sh: line 0: [: : integer expression expected
+ mips-linux-gcc -D__ASSEMBLY__ -g -Os -D__KERNEL__ -DTEXT_BASE=0xB0000000 -I/home/skuribay/devel/u-boot.git/include -fno-builtin -ffreestanding -nostdinc -isystem /home/skuribay/devel/buildroot/build_mips/staging_dir/usr/bin/../lib/gcc/mips-linux-uclibc/4.2.1/include -pipe -DCONFIG_MIPS -D__MIPS__ -G 0 -mabicalls -fpic -pipe -msoft-float -march=4kc -mtune=4kc -EB -c -o cache.o cache.S
+ /bin/sh: line 0: [: : integer expression expected
+ mips-linux-gcc -g -Os -D__KERNEL__ -DTEXT_BASE=0xB0000000 -I/home/skuribay/devel/u-boot.git/include -fno-builtin -ffreestanding -nostdinc -isystem /home/skuribay/devel/buildroot/build_mips/staging_dir/usr/bin/../lib/gcc/mips-linux-uclibc/4.2.1/include -pipe -DCONFIG_MIPS -D__MIPS__ -G 0 -mabicalls -fpic -pipe -msoft-float -march=4kc -mtune=4kc -EB -Wall -Wstrict-prototypes -c -o asc_serial.o asc_serial.c
+ /bin/sh: line 0: [: : integer expression expected
+
+ This patch simplifies the trick and makes it work with both versions of gas.
+ I also replace an expensive `awk (or gawk)' with `cut'.
+
+ Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit 16664f72850846e645616da1c0fa5afcd6d15f15
+Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+Date: Sat Nov 17 20:05:26 2007 +0900
+
+ [MIPS] Remove useless instructions for initializing $gp.
+
+ Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit 03c031d5660ea946c39af6e2e16267da857c609f
+Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+Date: Sat Oct 27 15:27:06 2007 +0900
+
+ [MIPS] MIPS 4K core: Coding style cleanups
+
+ No logical changes.
+
+ Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit f5e429d3860bba4c6ae8bead8f78349fa24491b2
+Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+Date: Sat Nov 17 20:05:20 2007 +0900
+
+ [MIPS] gth2.c: Fix a warning on gth2 build.
+
+ gth2.c: In function 'misc_init_r':
+ gth2.c:434: warning: pointer targets in passing argument 2 of 'setenv' differ in signedness
+
+ Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit 4fbd0741b2b6441da10be93e10267122581b7079
+Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+Date: Sat Oct 27 15:22:33 2007 +0900
+
+ [MIPS] au1x00_eth.c: Fixed a warning on pb1000 build.
+
+ au1x00_eth.c: In function 'au1x00_miiphy_write':
+ au1x00_eth.c:139: warning: 'return' with no value, in function returning non-void
+
+ Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit f01320459736f156707425cf8112f98606301aa4
+Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+Date: Sat Oct 27 15:00:25 2007 +0900
+
+ [MIPS] au1x00_eth.c: Fix au1x00_miiphy_{read,write} build error
+
+ au1x00_eth.c: In function 'au1x00_enet_initialize':
+ au1x00_eth.c:246: error: 'au1x00_miiphy_read' undeclared (first use in this function)
+ au1x00_eth.c:246: error: (Each undeclared identifier is reported only once
+ au1x00_eth.c:246: error: for each function it appears in.)
+ au1x00_eth.c:246: error: 'au1x00_miiphy_write' undeclared (first use in this function)
+ au1x00_eth.c: In function 'au1x00_miiphy_write':
+ au1x00_eth.c:298: warning: 'return' with no value, in function returning non-void
+ make[1]: *** [au1x00_eth.o] Error 1
+
+ Fixed by moving these two functions forward.
+
+ Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit b09258c5393edd1087c5f39ae68338f16b49f8b3
+Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+Date: Sat Oct 27 15:00:25 2007 +0900
+
+ MAKEALL: Added missing pb1000 board
+
+ Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit 2e4a6e3667a1e39c0e6e99498686b15d2718b369
+Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+Date: Sat Oct 27 15:00:24 2007 +0900
+
+ [MIPS] pb1000: Replace obsolete memsetup.S with lowlevel_init.S
+
+ Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit 662e5cb397249c3ea88a4c3255e9ccfc40b98d82
+Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+Date: Sat Oct 27 15:00:24 2007 +0900
+
+ [MIPS] u-boot.lds: Cleanup __u_boot_cmd_{start,end}
+
+ Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit 5947f6999aafa7c54c1390983d264a8463dfea8e
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat Nov 17 02:34:38 2007 +0100
+
+ Update CHANGELOIG, prepare for -rc4
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
commit fd329e6f05bbdfe6bd71b0e09f0c76d3b0a025a5
Author: Luotao Fu <l.fu@pengutronix.de>
Date: Wed Nov 14 18:58:33 2007 +0100
LIST_au1xx0_el=" \
dbau1550_el \
+ pb1000 \
"
LIST_mips_el=" \
VERSION = 1
PATCHLEVEL = 3
SUBLEVEL = 0
-EXTRAVERSION = -rc4
+EXTRAVERSION =
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
VERSION_FILE = $(obj)include/version_autogenerated.h
.sdata : { *(.sdata) }
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_cmd : {
+ __u_boot_cmd_start = .;
+ *(.u_boot_cmd)
+ __u_boot_cmd_end = .;
+ }
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
* Activate ULI1575 legacy chip by performing a fake
* memory access. Needed to make ULI RTC work.
*/
- in_be32(CFG_PCIE3_MEM_BASE);
+ in_be32((u32 *)CFG_PCIE3_MEM_BASE);
} else {
printf (" PCIE3: disabled\n");
}
(Rx[8] != ':') | (Rx[11] != ':') | (Rx[14] != ':')) {
printf ("*** ethernet addr invalid, using default ***\n");
} else {
- setenv ("ethaddr", Rx);
+ setenv ("ethaddr", (char *)Rx);
}
return (0);
}
j clearmem
nop
+#if 0
.globl memtest
+#endif
memtest:
/* Fill memory with address */
li t0, 0x80000000
bne t1, zero, mt1
nop
nop
+#if 0
.globl clearmem
+#endif
clearmem:
/* Clear memory */
li t0, 0x80000000
.sdata : { *(.sdata) }
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_cmd : {
+ __u_boot_cmd_start = .;
+ *(.u_boot_cmd)
+ __u_boot_cmd_end = .;
+ }
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
.sdata : { *(.sdata) }
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_cmd : {
+ __u_boot_cmd_start = .;
+ *(.u_boot_cmd)
+ __u_boot_cmd_end = .;
+ }
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
* Copy memory to flash
*/
-volatile static int write_hword (flash_info_t * info, ulong dest, ushort data)
+static int write_hword (flash_info_t * info, ulong dest, ushort data)
{
vu_short *addr = (vu_short *) dest;
ushort result;
} /*__attribute__((__packed__))*/ VCMA9_PLD;
#define VCMA9_PLD_BASE 0x2C000100
-static inline VCMA9_PLD * const VCMA9_GetBase_PLD(void)
+static inline VCMA9_PLD * VCMA9_GetBase_PLD(void)
{
return (VCMA9_PLD * const)VCMA9_PLD_BASE;
}
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o flash.o
-SOBJS = memsetup.o
+SOBJS = lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
--- /dev/null
+/* Memory sub-system initialization code */
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+#include <asm/au1x00.h>
+#include <asm/mipsregs.h>
+
+#define AU1500_SYS_ADDR 0xB1900000
+#define sys_endian 0x0038
+#define CP0_Config0 $16
+#define MEM_1MS ((396000000/1000000) * 1000)
+
+ .text
+ .set noreorder
+ .set mips32
+
+ .globl lowlevel_init
+lowlevel_init:
+ /*
+ * Step 1) Establish CPU endian mode.
+ * NOTE: A fair amount of code is necessary on the Pb1000 to
+ * obtain the value of Switch S8.1 which is used to determine
+ * endian at run-time.
+ */
+
+ /* RCE1 */
+ li t0, MEM_STCFG1
+ li t1, 0x00000083
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME1
+ li t1, 0x33030A10
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR1
+ li t1, 0x11803E40
+ sw t1, 0(t0)
+
+ /* Set DSTRB bits so switch will read correctly */
+ li t1, 0xBE00000C
+ lw t2, 0(t1)
+ or t2, t2, 0x00000300
+ sw t2, 0(t1)
+
+ /* Check switch setting */
+ li t1, 0xBE000014
+ lw t2, 0(t1)
+ and t2, t2, 0x00000100
+ bne t2, zero, big_endian
+ nop
+
+little_endian:
+
+ /* Change Au1 core to little endian */
+ li t0, AU1500_SYS_ADDR
+ li t1, 1
+ sw t1, sys_endian(t0)
+ mfc0 t2, CP0_CONFIG
+ mtc0 t2, CP0_CONFIG
+ nop
+ nop
+
+ /* Big Endian is default so nothing to do but fall through */
+
+big_endian:
+
+ /*
+ * Step 2) Establish Status Register
+ * (set BEV, clear ERL, clear EXL, clear IE)
+ */
+ li t1, 0x00400000
+ mtc0 t1, CP0_STATUS
+
+ /*
+ * Step 3) Establish CP0 Config0
+ * (set OD, set K0=3)
+ */
+ li t1, 0x00080003
+ mtc0 t1, CP0_CONFIG
+
+ /*
+ * Step 4) Disable Watchpoint facilities
+ */
+ li t1, 0x00000000
+ mtc0 t1, CP0_WATCHLO
+ mtc0 t1, CP0_IWATCHLO
+ /*
+ * Step 5) Disable the performance counters
+ */
+ mtc0 zero, CP0_PERFORMANCE
+ nop
+
+ /*
+ * Step 6) Establish EJTAG Debug register
+ */
+ mtc0 zero, CP0_DEBUG
+ nop
+
+ /*
+ * Step 7) Establish Cause
+ * (set IV bit)
+ */
+ li t1, 0x00800000
+ mtc0 t1, CP0_CAUSE
+
+ /* Establish Wired (and Random) */
+ mtc0 zero, CP0_WIRED
+ nop
+
+ /* First setup pll:s to make serial work ok */
+ /* We have a 12 MHz crystal */
+ li t0, SYS_CPUPLL
+ li t1, 0x21 /* 396 MHz */
+ sw t1, 0(t0)
+ sync
+ nop
+ nop
+
+ /* wait 1mS for clocks to settle */
+ li t1, MEM_1MS
+1: add t1, -1
+ bne t1, zero, 1b
+ nop
+ /* Setup AUX PLL */
+ li t0, SYS_AUXPLL
+ li t1, 8 /* 96 MHz */
+ sw t1, 0(t0) /* aux pll */
+ sync
+
+ /* Static memory controller */
+
+ /* RCE0 8MB AMD29D323 Flash */
+ li t0, MEM_STCFG0
+ li t1, 0x00001403
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME0
+ li t1, 0xFFFFFFDD
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR0
+ li t1, 0x11F83FE0
+ sw t1, 0(t0)
+
+ /* RCE1 CPLD Board Logic */
+ li t0, MEM_STCFG1
+ li t1, 0x00000083
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME1
+ li t1, 0x33030A10
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR1
+ li t1, 0x11803E40
+ sw t1, 0(t0)
+
+ /* RCE2 CPLD Board Logic */
+ li t0, MEM_STCFG2
+ li t1, 0x00000004
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME2
+ li t1, 0x08061908
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR2
+ li t1, 0x12A03FC0
+ sw t1, 0(t0)
+
+ /* RCE3 PCMCIA 250ns */
+ li t0, MEM_STCFG3
+ li t1, 0x00000002
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME3
+ li t1, 0x280E3E07
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR3
+ li t1, 0x10000000
+ sw t1, 0(t0)
+
+ sync
+
+ /* Set peripherals to a known state */
+ li t0, IC0_CFG0CLR
+ li t1, 0xFFFFFFFF
+ sw t1, 0(t0)
+
+ li t0, IC0_CFG0CLR
+ sw t1, 0(t0)
+
+ li t0, IC0_CFG1CLR
+ sw t1, 0(t0)
+
+ li t0, IC0_CFG2CLR
+ sw t1, 0(t0)
+
+ li t0, IC0_SRCSET
+ sw t1, 0(t0)
+
+ li t0, IC0_ASSIGNSET
+ sw t1, 0(t0)
+
+ li t0, IC0_WAKECLR
+ sw t1, 0(t0)
+
+ li t0, IC0_RISINGCLR
+ sw t1, 0(t0)
+
+ li t0, IC0_FALLINGCLR
+ sw t1, 0(t0)
+
+ li t0, IC0_TESTBIT
+ li t1, 0x00000000
+ sw t1, 0(t0)
+ sync
+
+ li t0, IC1_CFG0CLR
+ li t1, 0xFFFFFFFF
+ sw t1, 0(t0)
+
+ li t0, IC1_CFG0CLR
+ sw t1, 0(t0)
+
+ li t0, IC1_CFG1CLR
+ sw t1, 0(t0)
+
+ li t0, IC1_CFG2CLR
+ sw t1, 0(t0)
+
+ li t0, IC1_SRCSET
+ sw t1, 0(t0)
+
+ li t0, IC1_ASSIGNSET
+ sw t1, 0(t0)
+
+ li t0, IC1_WAKECLR
+ sw t1, 0(t0)
+
+ li t0, IC1_RISINGCLR
+ sw t1, 0(t0)
+
+ li t0, IC1_FALLINGCLR
+ sw t1, 0(t0)
+
+ li t0, IC1_TESTBIT
+ li t1, 0x00000000
+ sw t1, 0(t0)
+ sync
+
+ li t0, SYS_FREQCTRL0
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, SYS_FREQCTRL1
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, SYS_CLKSRC
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, SYS_PININPUTEN
+ li t1, 0x00000000
+ sw t1, 0(t0)
+ sync
+
+ li t0, 0xB1100100
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, 0xB1400100
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+
+ li t0, SYS_WAKEMSK
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, SYS_WAKESRC
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ /* wait 1mS before setup */
+ li t1, MEM_1MS
+1: add t1, -1
+ bne t1, zero, 1b
+ nop
+
+ /*
+ * Skip memory setup if we are running from memory
+ */
+ li t0, 0x90000000
+ sub t0, ra, t0
+ bltz t0, skip_memsetup
+ nop
+
+ /*
+ * SDCS0 - Not used, for SMROM
+ * SDCS1 - 32MB Micron 48LCBM16A2
+ * SDCS2 - 32MB Micron 48LCBM16A2
+ */
+ li t0, MEM_SDMODE0
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, MEM_SDMODE1
+ li t1, 0x00552229
+ sw t1, 0(t0)
+
+ li t0, MEM_SDMODE2
+ li t1, 0x00552229
+ sw t1, 0(t0)
+
+ li t0, MEM_SDADDR0
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, MEM_SDADDR1
+ li t1, 0x001003F8
+ sw t1, 0(t0)
+
+ li t0, MEM_SDADDR2
+ li t1, 0x001023F8
+ sw t1, 0(t0)
+
+ sync
+
+ li t0, MEM_SDREFCFG
+ li t1, 0x74000c30 /* Disable */
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDPRECMD
+ sw zero, 0(t0)
+ sync
+
+ li t0, MEM_SDAUTOREF
+ sw zero, 0(t0)
+ sync
+ sw zero, 0(t0)
+ sync
+
+ li t0, MEM_SDREFCFG
+ li t1, 0x76000c30 /* Enable */
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDWRMD0
+ li t1, 0x00000023
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDWRMD1
+ li t1, 0x00000023
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDWRMD2
+ li t1, 0x00000023
+ sw t1, 0(t0)
+ sync
+
+ /* wait 1mS after setup */
+ li t1, MEM_1MS
+1: add t1, -1
+ bne t1, zero, 1b
+ nop
+
+skip_memsetup:
+
+ li t0, SYS_PINFUNC
+ li t1, 0/*0x00008080*/
+ sw t1, 0(t0)
+
+ /*
+ li t0, SYS_TRIOUTCLR
+ li t1, 0x00001FFF
+ sw t1, 0(t0)
+
+ li t0, SYS_OUTPUTCLR
+ li t1, 0x00008000
+ sw t1, 0(t0)
+ */
+ sync
+
+ j ra
+ nop
+++ /dev/null
-/* Memory sub-system initialization code */
-
-#include <config.h>
-#include <version.h>
-#include <asm/regdef.h>
-#include <asm/au1x00.h>
-#include <asm/mipsregs.h>
-
-#define AU1500_SYS_ADDR 0xB1900000
-#define sys_endian 0x0038
-#define CP0_Config0 $16
-#define MEM_1MS ((396000000/1000000) * 1000)
-
- .text
- .set noreorder
- .set mips32
-
- .globl memsetup
-memsetup:
- /*
- * Step 1) Establish CPU endian mode.
- * NOTE: A fair amount of code is necessary on the Pb1000 to
- * obtain the value of Switch S8.1 which is used to determine
- * endian at run-time.
- */
-
- /* RCE1 */
- li t0, MEM_STCFG1
- li t1, 0x00000083
- sw t1, 0(t0)
-
- li t0, MEM_STTIME1
- li t1, 0x33030A10
- sw t1, 0(t0)
-
- li t0, MEM_STADDR1
- li t1, 0x11803E40
- sw t1, 0(t0)
-
- /* Set DSTRB bits so switch will read correctly */
- li t1, 0xBE00000C
- lw t2, 0(t1)
- or t2, t2, 0x00000300
- sw t2, 0(t1)
-
- /* Check switch setting */
- li t1, 0xBE000014
- lw t2, 0(t1)
- and t2, t2, 0x00000100
- bne t2, zero, big_endian
- nop
-
-little_endian:
-
- /* Change Au1 core to little endian */
- li t0, AU1500_SYS_ADDR
- li t1, 1
- sw t1, sys_endian(t0)
- mfc0 t2, CP0_CONFIG
- mtc0 t2, CP0_CONFIG
- nop
- nop
-
- /* Big Endian is default so nothing to do but fall through */
-
-big_endian:
-
- /*
- * Step 2) Establish Status Register
- * (set BEV, clear ERL, clear EXL, clear IE)
- */
- li t1, 0x00400000
- mtc0 t1, CP0_STATUS
-
- /*
- * Step 3) Establish CP0 Config0
- * (set OD, set K0=3)
- */
- li t1, 0x00080003
- mtc0 t1, CP0_CONFIG
-
- /*
- * Step 4) Disable Watchpoint facilities
- */
- li t1, 0x00000000
- mtc0 t1, CP0_WATCHLO
- mtc0 t1, CP0_IWATCHLO
- /*
- * Step 5) Disable the performance counters
- */
- mtc0 zero, CP0_PERFORMANCE
- nop
-
- /*
- * Step 6) Establish EJTAG Debug register
- */
- mtc0 zero, CP0_DEBUG
- nop
-
- /*
- * Step 7) Establish Cause
- * (set IV bit)
- */
- li t1, 0x00800000
- mtc0 t1, CP0_CAUSE
-
- /* Establish Wired (and Random) */
- mtc0 zero, CP0_WIRED
- nop
-
- /* First setup pll:s to make serial work ok */
- /* We have a 12 MHz crystal */
- li t0, SYS_CPUPLL
- li t1, 0x21 /* 396 MHz */
- sw t1, 0(t0)
- sync
- nop
- nop
-
- /* wait 1mS for clocks to settle */
- li t1, MEM_1MS
-1: add t1, -1
- bne t1, zero, 1b
- nop
- /* Setup AUX PLL */
- li t0, SYS_AUXPLL
- li t1, 8 /* 96 MHz */
- sw t1, 0(t0) /* aux pll */
- sync
-
- /* Static memory controller */
-
- /* RCE0 8MB AMD29D323 Flash */
- li t0, MEM_STCFG0
- li t1, 0x00001403
- sw t1, 0(t0)
-
- li t0, MEM_STTIME0
- li t1, 0xFFFFFFDD
- sw t1, 0(t0)
-
- li t0, MEM_STADDR0
- li t1, 0x11F83FE0
- sw t1, 0(t0)
-
- /* RCE1 CPLD Board Logic */
- li t0, MEM_STCFG1
- li t1, 0x00000083
- sw t1, 0(t0)
-
- li t0, MEM_STTIME1
- li t1, 0x33030A10
- sw t1, 0(t0)
-
- li t0, MEM_STADDR1
- li t1, 0x11803E40
- sw t1, 0(t0)
-
- /* RCE2 CPLD Board Logic */
- li t0, MEM_STCFG2
- li t1, 0x00000004
- sw t1, 0(t0)
-
- li t0, MEM_STTIME2
- li t1, 0x08061908
- sw t1, 0(t0)
-
- li t0, MEM_STADDR2
- li t1, 0x12A03FC0
- sw t1, 0(t0)
-
- /* RCE3 PCMCIA 250ns */
- li t0, MEM_STCFG3
- li t1, 0x00000002
- sw t1, 0(t0)
-
- li t0, MEM_STTIME3
- li t1, 0x280E3E07
- sw t1, 0(t0)
-
- li t0, MEM_STADDR3
- li t1, 0x10000000
- sw t1, 0(t0)
-
- sync
-
- /* Set peripherals to a known state */
- li t0, IC0_CFG0CLR
- li t1, 0xFFFFFFFF
- sw t1, 0(t0)
-
- li t0, IC0_CFG0CLR
- sw t1, 0(t0)
-
- li t0, IC0_CFG1CLR
- sw t1, 0(t0)
-
- li t0, IC0_CFG2CLR
- sw t1, 0(t0)
-
- li t0, IC0_SRCSET
- sw t1, 0(t0)
-
- li t0, IC0_ASSIGNSET
- sw t1, 0(t0)
-
- li t0, IC0_WAKECLR
- sw t1, 0(t0)
-
- li t0, IC0_RISINGCLR
- sw t1, 0(t0)
-
- li t0, IC0_FALLINGCLR
- sw t1, 0(t0)
-
- li t0, IC0_TESTBIT
- li t1, 0x00000000
- sw t1, 0(t0)
- sync
-
- li t0, IC1_CFG0CLR
- li t1, 0xFFFFFFFF
- sw t1, 0(t0)
-
- li t0, IC1_CFG0CLR
- sw t1, 0(t0)
-
- li t0, IC1_CFG1CLR
- sw t1, 0(t0)
-
- li t0, IC1_CFG2CLR
- sw t1, 0(t0)
-
- li t0, IC1_SRCSET
- sw t1, 0(t0)
-
- li t0, IC1_ASSIGNSET
- sw t1, 0(t0)
-
- li t0, IC1_WAKECLR
- sw t1, 0(t0)
-
- li t0, IC1_RISINGCLR
- sw t1, 0(t0)
-
- li t0, IC1_FALLINGCLR
- sw t1, 0(t0)
-
- li t0, IC1_TESTBIT
- li t1, 0x00000000
- sw t1, 0(t0)
- sync
-
- li t0, SYS_FREQCTRL0
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, SYS_FREQCTRL1
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, SYS_CLKSRC
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, SYS_PININPUTEN
- li t1, 0x00000000
- sw t1, 0(t0)
- sync
-
- li t0, 0xB1100100
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, 0xB1400100
- li t1, 0x00000000
- sw t1, 0(t0)
-
-
- li t0, SYS_WAKEMSK
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, SYS_WAKESRC
- li t1, 0x00000000
- sw t1, 0(t0)
-
- /* wait 1mS before setup */
- li t1, MEM_1MS
-1: add t1, -1
- bne t1, zero, 1b
- nop
-
- /*
- * Skip memory setup if we are running from memory
- */
- li t0, 0x90000000
- sub t0, ra, t0
- bltz t0, skip_memsetup
- nop
-
- /*
- * SDCS0 - Not used, for SMROM
- * SDCS1 - 32MB Micron 48LCBM16A2
- * SDCS2 - 32MB Micron 48LCBM16A2
- */
- li t0, MEM_SDMODE0
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, MEM_SDMODE1
- li t1, 0x00552229
- sw t1, 0(t0)
-
- li t0, MEM_SDMODE2
- li t1, 0x00552229
- sw t1, 0(t0)
-
- li t0, MEM_SDADDR0
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, MEM_SDADDR1
- li t1, 0x001003F8
- sw t1, 0(t0)
-
- li t0, MEM_SDADDR2
- li t1, 0x001023F8
- sw t1, 0(t0)
-
- sync
-
- li t0, MEM_SDREFCFG
- li t1, 0x74000c30 /* Disable */
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDPRECMD
- sw zero, 0(t0)
- sync
-
- li t0, MEM_SDAUTOREF
- sw zero, 0(t0)
- sync
- sw zero, 0(t0)
- sync
-
- li t0, MEM_SDREFCFG
- li t1, 0x76000c30 /* Enable */
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDWRMD0
- li t1, 0x00000023
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDWRMD1
- li t1, 0x00000023
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDWRMD2
- li t1, 0x00000023
- sw t1, 0(t0)
- sync
-
- /* wait 1mS after setup */
- li t1, MEM_1MS
-1: add t1, -1
- bne t1, zero, 1b
- nop
-
-skip_memsetup:
-
- li t0, SYS_PINFUNC
- li t1, 0/*0x00008080*/
- sw t1, 0(t0)
-
- /*
- li t0, SYS_TRIOUTCLR
- li t1, 0x00001FFF
- sw t1, 0(t0)
-
- li t0, SYS_OUTPUTCLR
- li t1, 0x00008000
- sw t1, 0(t0)
- */
- sync
-
- j ra
- nop
int checkboard (void)
{
+#if defined(CONFIG_IDE_PCMCIA) && 0
u16 status;
+#endif
/* volatile u32 *pcmcia_bcsr = (u32*)(DB1000_BCSR_ADDR+0x10); */
volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
u32 proc_id;
.sdata : { *(.sdata) }
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_cmd : {
+ __u_boot_cmd_start = .;
+ *(.u_boot_cmd)
+ __u_boot_cmd_end = .;
+ }
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
int i;
uchar *boottype;
uchar *bootletter;
- uchar *fmt;
+ char *fmt;
uchar botbootletter[] = "B";
uchar topbootletter[] = "T";
uchar botboottype[] = "bottom boot sector";
.sdata : { *(.sdata) }
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_cmd : {
+ __u_boot_cmd_start = .;
+ *(.u_boot_cmd)
+ __u_boot_cmd_end = .;
+ }
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
* Copy memory to flash
*/
-volatile static int write_hword (flash_info_t * info, ulong dest, ushort data)
+static int write_hword (flash_info_t * info, ulong dest, ushort data)
{
vu_short *addr = (vu_short *) dest;
ushort result;
* Copy memory to flash
*/
-volatile static int write_hword (flash_info_t * info, ulong dest, ushort data)
+static int write_hword (flash_info_t * info, ulong dest, ushort data)
{
vu_short *addr = (vu_short *) dest;
ushort result;
.sdata : { *(.sdata) }
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_cmd : {
+ __u_boot_cmd_start = .;
+ *(.u_boot_cmd)
+ __u_boot_cmd_end = .;
+ }
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
#ifdef CONFIG_BOARD_EARLY_INIT_R
int board_early_init_r (void)
{
+ extern int usb_cpu_init(void);
+
#ifdef CONFIG_PS2MULT
ps2mult_early_init();
#endif /* CONFIG_PS2MULT */
disable_ctrlc(1);
}
#endif
+#endif /* !CONFIG_TQM5200S */
return 0;
-#endif /* !CONFIG_TQM5200S */
}
#ifdef CONFIG_VIDEO_SM501
#if ( WEP_FLASH_BUS_WIDTH == 1 )
# define FLASH_BUS vu_char
+# define FLASH_BUS_RET u_char
# if ( WEP_FLASH_INTERLEAVE == 1 )
# define FLASH_CMD( x ) x
# else
#elif ( WEP_FLASH_BUS_WIDTH == 2 )
# define FLASH_BUS vu_short
+# define FLASH_BUS_RET u_short
# if ( WEP_FLASH_INTERLEAVE == 1 )
# define FLASH_CMD( x ) x
# elif ( WEP_FLASH_INTERLEAVE == 2 )
#elif ( WEP_FLASH_BUS_WIDTH == 4 )
# define FLASH_BUS vu_long
+# define FLASH_BUS_RET u_long
# if ( WEP_FLASH_INTERLEAVE == 1 )
# define FLASH_CMD( x ) x
# elif ( WEP_FLASH_INTERLEAVE == 2 )
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
-static FLASH_BUS flash_status_reg (void)
+static FLASH_BUS_RET flash_status_reg (void)
{
FLASH_BUS *addr = (FLASH_BUS *) 0;
if((modi&0x80)==0x80) /* drive is removable */
scsi_dev_desc[scsi_max_devs].removable=TRUE;
/* get info for this device */
- scsi_ident_cpy(&scsi_dev_desc[scsi_max_devs].vendor[0],&tempbuff[8],8);
- scsi_ident_cpy(&scsi_dev_desc[scsi_max_devs].product[0],&tempbuff[16],16);
- scsi_ident_cpy(&scsi_dev_desc[scsi_max_devs].revision[0],&tempbuff[32],4);
+ scsi_ident_cpy((unsigned char *)&scsi_dev_desc[scsi_max_devs].vendor[0],
+ &tempbuff[8], 8);
+ scsi_ident_cpy((unsigned char *)&scsi_dev_desc[scsi_max_devs].product[0],
+ &tempbuff[16], 16);
+ scsi_ident_cpy((unsigned char *)&scsi_dev_desc[scsi_max_devs].revision[0],
+ &tempbuff[32], 4);
scsi_dev_desc[scsi_max_devs].target=pccb->target;
scsi_dev_desc[scsi_max_devs].lun=pccb->lun;
dev_desc->product[16] = 0;
dev_desc->revision[4] = 0;
#ifdef CONFIG_USB_BIN_FIXUP
- usb_bin_fixup(dev->descriptor, dev_desc->vendor, dev_desc->product);
+ usb_bin_fixup(dev->descriptor, (uchar *)dev_desc->vendor, (uchar *)dev_desc->product);
#endif /* CONFIG_USB_BIN_FIXUP */
USB_STOR_PRINTF("ISO Vers %X, Response Data %X\n",usb_stor_buf[2],usb_stor_buf[3]);
if(usb_test_unit_ready(pccb,ss)) {
LIB = $(obj)lib$(SOC).a
COBJS = i2c.o interrupts.o serial.o speed.o \
- usb.o
+ usb.o usb_ohci.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
if (ohci->ed_controltail == NULL) {
writel (ed, &ohci->regs->ed_controlhead);
} else {
- ohci->ed_controltail->hwNextED = m32_swap (ed);
+ ohci->ed_controltail->hwNextED = (__u32)m32_swap (ed);
}
ed->ed_prev = ohci->ed_controltail;
if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
if (ohci->ed_bulktail == NULL) {
writel (ed, &ohci->regs->ed_bulkhead);
} else {
- ohci->ed_bulktail->hwNextED = m32_swap (ed);
+ ohci->ed_bulktail->hwNextED = (__u32)m32_swap (ed);
}
ed->ed_prev = ohci->ed_bulktail;
if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
/* dummy td; end of td list for ed */
td = td_alloc (usb_dev);
- ed->hwTailP = m32_swap (td);
+ ed->hwTailP = (__u32)m32_swap (td);
ed->hwHeadP = ed->hwTailP;
ed->state = ED_UNLINK;
ed->type = usb_pipetype (pipe);
if (!len)
data = 0;
- td->hwINFO = m32_swap (info);
- td->hwCBP = m32_swap (data);
+ td->hwINFO = (__u32)m32_swap (info);
+ td->hwCBP = (__u32)m32_swap (data);
if (data)
- td->hwBE = m32_swap (data + len - 1);
+ td->hwBE = (__u32)m32_swap (data + len - 1);
else
td->hwBE = 0;
- td->hwNextTD = m32_swap (td_pt);
+ td->hwNextTD = (__u32)m32_swap (td_pt);
/* append to queue */
td->ed->hwTailP = td->hwNextTD;
#define MAX_WAIT 1000
+#if defined(CONFIG_CMD_MII)
+int au1x00_miiphy_read(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short * value)
+{
+ volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
+ volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
+ u32 mii_control;
+ unsigned int timedout = 20;
+
+ while (*mii_control_reg & MAC_MII_BUSY) {
+ udelay(1000);
+ if (--timedout == 0) {
+ printf("au1x00_eth: miiphy_read busy timeout!!\n");
+ return -1;
+ }
+ }
+
+ mii_control = MAC_SET_MII_SELECT_REG(reg) |
+ MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ;
+
+ *mii_control_reg = mii_control;
+
+ timedout = 20;
+ while (*mii_control_reg & MAC_MII_BUSY) {
+ udelay(1000);
+ if (--timedout == 0) {
+ printf("au1x00_eth: miiphy_read busy timeout!!\n");
+ return -1;
+ }
+ }
+ *value = *mii_data_reg;
+ return 0;
+}
+
+int au1x00_miiphy_write(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value)
+{
+ volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
+ volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
+ u32 mii_control;
+ unsigned int timedout = 20;
+
+ while (*mii_control_reg & MAC_MII_BUSY) {
+ udelay(1000);
+ if (--timedout == 0) {
+ printf("au1x00_eth: miiphy_write busy timeout!!\n");
+ return -1;
+ }
+ }
+
+ mii_control = MAC_SET_MII_SELECT_REG(reg) |
+ MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE;
+
+ *mii_data_reg = value;
+ *mii_control_reg = mii_control;
+ return 0;
+}
+#endif
+
static int au1x00_send(struct eth_device* dev, volatile void *packet, int length){
volatile mac_fifo_t *fifo_tx =
(volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
return 1;
}
-#if defined(CONFIG_CMD_MII)
-int au1x00_miiphy_read(char *devname, unsigned char addr,
- unsigned char reg, unsigned short * value)
-{
- volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
- volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
- u32 mii_control;
- unsigned int timedout = 20;
-
- while (*mii_control_reg & MAC_MII_BUSY) {
- udelay(1000);
- if (--timedout == 0) {
- printf("au1x00_eth: miiphy_read busy timeout!!\n");
- return -1;
- }
- }
-
- mii_control = MAC_SET_MII_SELECT_REG(reg) |
- MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ;
-
- *mii_control_reg = mii_control;
-
- timedout = 20;
- while (*mii_control_reg & MAC_MII_BUSY) {
- udelay(1000);
- if (--timedout == 0) {
- printf("au1x00_eth: miiphy_read busy timeout!!\n");
- return -1;
- }
- }
- *value = *mii_data_reg;
- return 0;
-}
-
-int au1x00_miiphy_write(char *devname, unsigned char addr,
- unsigned char reg, unsigned short value)
-{
- volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
- volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
- u32 mii_control;
- unsigned int timedout = 20;
-
- while (*mii_control_reg & MAC_MII_BUSY) {
- udelay(1000);
- if (--timedout == 0) {
- printf("au1x00_eth: miiphy_write busy timeout!!\n");
- return;
- }
- }
-
- mii_control = MAC_SET_MII_SELECT_REG(reg) |
- MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE;
-
- *mii_data_reg = value;
- *mii_control_reg = mii_control;
- return 0;
-}
-#endif
-
#endif /* CONFIG_AU1X00 */
* MA 02111-1307 USA
*/
-
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include <asm/addrspace.h>
#include <asm/cacheops.h>
-
/* 16KB is the maximum size of instruction and data caches on
* MIPS 4K.
*/
#define MIPS_MAX_CACHE_SIZE 0x4000
-
/*
* cacheop macro to automate cache operations
* first some helpers...
li t4, CFG_CACHELINE_SIZE
move t5, t4
-
li v0, MIPS_MAX_CACHE_SIZE
/* Now clear that much memory starting from zero.
li a0, KSEG1
addu a1, a0, v0
-
-2: sw zero, 0(a0)
+2:
+ sw zero, 0(a0)
sw zero, 4(a0)
sw zero, 8(a0)
sw zero, 12(a0)
mtc0 zero, CP0_TAGLO
- /*
- * The caches are probably in an indeterminate state,
- * so we force good parity into them by doing an
- * invalidate, load/fill, invalidate for each line.
- */
+ /*
+ * The caches are probably in an indeterminate state,
+ * so we force good parity into them by doing an
+ * invalidate, load/fill, invalidate for each line.
+ */
/* Assume bottom of RAM will generate good parity for the cache.
*/
move a1, a2
icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
- j ra
- .end mips_cache_reset
+ j ra
+ .end mips_cache_reset
/*******************************************************************************
*
andi v0, v0, 1
j ra
- .end dcache_status
+ .end dcache_status
/*******************************************************************************
*
li t1, -8
and t0, t0, t1
ori t0, t0, CONF_CM_UNCACHED
- mtc0 t0, CP0_CONFIG
+ mtc0 t0, CP0_CONFIG
j ra
- .end dcache_disable
-
+ .end dcache_disable
/*******************************************************************************
*
icacheop(a0,a1,a2,a3,0x1d)
j ra
+
.end mips_cache_lock
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
-v=$(shell \
-$(CROSS_COMPILE)as --version|grep "GNU assembler"|awk '{print $$3}'|awk -F . '{print $$2}')
+v=$(shell $(AS) --version |grep "GNU assembler" |cut -d. -f2)
MIPSFLAGS=$(shell \
if [ "$v" -lt "14" ]; then \
echo "-mcpu=4kc"; \
return 0;
}
-void flush_cache (ulong start_addr, ulong size)
+void flush_cache(ulong start_addr, ulong size)
{
-
}
-void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ){
+void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
+{
write_32bit_cp0_register(CP0_ENTRYLO0, low0);
write_32bit_cp0_register(CP0_PAGEMASK, pagemask);
write_32bit_cp0_register(CP0_ENTRYLO1, low1);
* MA 02111-1307 USA
*/
-
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
-
#define RVECENT(f,n) \
b f; nop
#define XVECENT(f,bev) \
.word 0x00000000
.word 0x03e00008
.word 0x00000000
- .word 0x00000000
+ .word 0x00000000
/* 0xbfc00428 */
.word 0xdc870000
.word 0xfca70000
.word 0x00000000
.word 0x03e00008
.word 0x00000000
- .word 0x00000000
+ .word 0x00000000
#endif /* CONFIG_PURPLE */
.align 4
reset:
mtc0 t0, CP0_CONFIG
/* Initialize $gp.
- */
- bal 1f
+ */
+ bal 1f
nop
.word _gp
- 1:
- move gp, ra
- lw t1, 0(ra)
- move gp, t1
+1:
+ lw gp, 0(ra)
#ifdef CONFIG_INCA_IP
/* Disable INCA-IP Watchdog.
*/
- la t9, disable_incaip_wdt
- jalr t9
+ la t9, disable_incaip_wdt
+ jalr t9
nop
#endif
/* Initialize any external memory.
*/
- la t9, lowlevel_init
- jalr t9
+ la t9, lowlevel_init
+ jalr t9
nop
/* Initialize caches...
*/
- la t9, mips_cache_reset
- jalr t9
+ la t9, mips_cache_reset
+ jalr t9
nop
/* ... and enable them.
li t0, CONF_CM_CACHABLE_NONCOHERENT
mtc0 t0, CP0_CONFIG
-
/* Set up temporary stack.
*/
li a0, CFG_INIT_SP_OFFSET
- la t9, mips_cache_lock
- jalr t9
+ la t9, mips_cache_lock
+ jalr t9
nop
li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET
j t9
nop
-
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
.globl relocate_code
.ent relocate_code
relocate_code:
- move sp, a0 /* Set new stack pointer */
+ move sp, a0 /* Set new stack pointer */
li t0, CFG_MONITOR_BASE
la t3, in_ram
*/
move t6, gp
sub gp, CFG_MONITOR_BASE
- add gp, a2 /* gp now adjusted */
- sub t6, gp, t6 /* t6 <-- relocation offset */
+ add gp, a2 /* gp now adjusted */
+ sub t6, gp, t6 /* t6 <-- relocation offset */
/*
* t0 = source address
sw t3, 0(t1)
addu t0, 4
ble t0, t2, 1b
- addu t1, 4 /* delay slot */
+ addu t1, 4 /* delay slot */
#endif
/* If caches were enabled, we would have to flush them here.
add t2, t6
sub t1, 4
-1: addi t1, 4
+1:
+ addi t1, 4
bltl t1, t2, 1b
sw zero, 0(t1) /* delay slot */
.end relocate_code
-
/* Exception handlers.
*/
romReserved:
- b romReserved
+ b romReserved
romExcHandle:
- b romExcHandle
+ b romExcHandle
int memsize_ddr1 = 0;
unsigned int law_size_ddr1;
volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
+#ifdef CONFIG_DDR_INTERLEAVE
+ volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
+#endif
#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
int memsize_ddr2_dimm1 = 0;
DECLARE_GLOBAL_DATA_PTR;
+/* used in some defintiions of CONFIG_SYS_CLK_FREQ */
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+
void get_sys_info(sys_info_t *sysInfo)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
uchar i2c_reg_read (uchar chip, uchar reg)
{
- char buf;
+ uchar buf;
PRINTD(("i2c_reg_read(chip=0x%02x, reg=0x%02x)\n",chip,reg));
i2c_read(chip, reg, 1, &buf, 1);
u32 val;
} reg_val;
-
+#if 0 /* unused ? -> scheduled for removal */
/* these common regs are cleared before mode setting so they do not
* interfere with anything
*/
{ CAP0_TRIG_CNTL, 0 },
{ CAP1_TRIG_CNTL, 0 },
};
-
+#endif /* 0 */
void radeon_setmode(void)
{
- int i;
struct radeon_regs *mode = malloc(sizeof(struct radeon_regs));
mode->crtc_gen_cntl = 0x03000200;
radeon_write_pll_regs(rinfo, mode);
}
+#include "bios_emulator/include/biosemu.h"
+extern int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo ** pVGAInfo, int cleanUp);
+
int radeon_probe(struct radeonfb_info *rinfo)
{
pci_dev_t pdev;
else if (addr >= 0xFFFF5 && addr < 0xFFFFE) {
/* Return a faked BIOS date string for non-x86 machines */
DB(printf("BE_memaddr - Returning BIOS date\n");)
- return BE_biosDate + addr - 0xFFFF5;
+ return (u8 *)(BE_biosDate + addr - 0xFFFF5);
} else if (addr == 0xFFFFE) {
/* Return system model identifier for non-x86 machines */
DB(printf("BE_memaddr - Returning model\n");)
return 0;
}
- M.mem_base = (unsigned long)malloc(memSize);
+ M.mem_base = malloc(memSize);
if (M.mem_base == NULL){
printf("Biosemu:Out of memory!");
_BE_env.emulateVGA = 0;
_BE_env.busmem_base = (unsigned long)malloc(128 * 1024);
- if (_BE_env.busmem_base == NULL){
+ if ((void *)_BE_env.busmem_base == NULL){
printf("Biosemu:Out of memory!");
return 0;
}
void X86API BE_exit(void)
{
free(M.mem_base);
- free(_BE_env.busmem_base);
+ free((void *)_BE_env.busmem_base);
}
/****************************************************************************
}
/* copy user data into frame data pointer */
- memcpy((void *)(eth->m_curTX_FD->m_frameDataPtr.bf.dataPtr),
+ memcpy((void *)((u32)(eth->m_curTX_FD->m_frameDataPtr.bf.dataPtr)),
(void *)packet,
length);
void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
static void adjust_link(struct eth_device *dev);
static void relocate_cmds(void);
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
+ && !defined(BITBANGMII)
static int tsec_miiphy_write(char *devname, unsigned char addr,
unsigned char reg, unsigned short value);
static int tsec_miiphy_read(char *devname, unsigned char addr,
unsigned char reg, unsigned short *value);
+#endif
#ifdef CONFIG_MCAST_TFTP
static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set);
#endif
* The Tsi108 HW doesn't support sending just the chip address
* and checkong for an <ACK> back.
*/
- return i2c_read (chip, 0, 1, (char *)&tmp, 1);
+ return i2c_read (chip, 0, 1, (uchar *)&tmp, 1);
}
#endif
#include <pci.h>
#include <asm/io.h>
#include <tsi108.h>
+#ifdef CONFIG_OF_FLAT_TREE
+#include <ft_build.h>
+#endif
struct pci_controller local_hose;
#include <usb.h>
#include "usb_ohci.h"
+#ifdef CONFIG_AT91RM9200
+#include <asm/arch/hardware.h> /* needed for AT91_USB_HOST_BASE */
+#endif
+
#if defined(CONFIG_ARM920T) || \
defined(CONFIG_S3C2400) || \
defined(CONFIG_S3C2410) || \
#ifndef __ASSEMBLY__
#include "AT91RM9200.h"
-#else
-#include "AT91RM9200_inc.h"
#endif
/* Virtual and Physical base address for system peripherals */
#define CFG_SRIO_MEM_BASE 0xc0000000
-#if defined(CONFIG_PCI)
-
-#define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
#ifdef CONFIG_QE
/*
* QE UEC ethernet configuration
#endif
#endif /* CONFIG_QE */
+#if defined(CONFIG_PCI)
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#if defined(CONFIG_CMD_NET)
-#define TIMEOUT 5 /* Seconds before trying BOOTP again */
+#define TIMEOUT 5UL /* Seconds before trying BOOTP again */
#ifndef CONFIG_NET_RETRY_COUNT
# define TIMEOUT_COUNT 5 /* # of timeouts before giving up */
#else
#define DHCP_NAK 6
#define DHCP_RELEASE 7
-#define SELECT_TIMEOUT 3 /* Seconds to wait for offers */
+#define SELECT_TIMEOUT 3UL /* Seconds to wait for offers */
/**********************************************************************/
DECLARE_GLOBAL_DATA_PTR;
-#define ARP_TIMEOUT 5 /* Seconds before trying ARP again */
+#define ARP_TIMEOUT 5UL /* Seconds before trying ARP again */
#ifndef CONFIG_NET_RETRY_COUNT
# define ARP_TIMEOUT_COUNT 5 /* # of timeouts before giving up */
#else
return;
}
#ifndef CONFIG_NET_MULTI
- NetSetTimeout (10 * CFG_HZ, startAgainTimeout);
+ NetSetTimeout (10UL * CFG_HZ, startAgainTimeout);
NetSetHandler (startAgainHandler);
#else /* !CONFIG_NET_MULTI*/
eth_halt ();
if (NetRestartWrap) {
NetRestartWrap = 0;
if (NetDevExists && !once) {
- NetSetTimeout (10 * CFG_HZ, startAgainTimeout);
+ NetSetTimeout (10UL * CFG_HZ, startAgainTimeout);
NetSetHandler (startAgainHandler);
} else {
NetState = NETLOOP_FAIL;
#if defined(CONFIG_NET_MULTI)
printf ("Using %s device\n", eth_get_name());
#endif /* CONFIG_NET_MULTI */
- NetSetTimeout (10 * CFG_HZ, PingTimeout);
+ NetSetTimeout (10UL * CFG_HZ, PingTimeout);
NetSetHandler (PingHandler);
PingSend();
#if defined(CONFIG_CMD_NET) && defined(CONFIG_CMD_NFS)
#define HASHES_PER_LINE 65 /* Number of "loading" hashes per line */
-#define NFS_TIMEOUT 60
+#define NFS_TIMEOUT 60UL
static int fs_mounted = 0;
static unsigned long rpc_id = 0;
#if defined(CONFIG_CMD_NET)
-#define TIMEOUT 5 /* Seconds before trying BOOTP again */
+#define TIMEOUT 5UL /* Seconds before trying BOOTP again */
#ifndef CONFIG_NET_RETRY_COUNT
# define TIMEOUT_COUNT 5 /* # of timeouts before giving up */
#else
#if defined(CONFIG_CMD_NET)
#define WELL_KNOWN_PORT 69 /* Well known TFTP port # */
-#define TIMEOUT 5 /* Seconds to timeout for a lost pkt */
+#define TIMEOUT 5UL /* Seconds to timeout for a lost pkt */
#ifndef CONFIG_NET_RETRY_COUNT
# define TIMEOUT_COUNT 10 /* # of timeouts before giving up */
#else
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