"All Rights Reserved" conflicts with the GPL.
Signed-off-by: Wolfgang Denk <wd@denx.de>
+++ /dev/null
-/* most of this is taken from the file */
-/* hal/powerpc/cogent/current/src/hal_diag.c in the */
-/* Cygnus eCos source. Here is the copyright notice: */
-/* */
-/*============================================================================= */
-/* */
-/* hal_diag.c */
-/* */
-/* HAL diagnostic output code */
-/* */
-/*============================================================================= */
-/*####COPYRIGHTBEGIN#### */
-/* */
-/* ------------------------------------------- */
-/* The contents of this file are subject to the Cygnus eCos Public License */
-/* Version 1.0 (the "License"); you may not use this file except in */
-/* compliance with the License. You may obtain a copy of the License at */
-/* http://sourceware.cygnus.com/ecos */
-/* */
-/* Software distributed under the License is distributed on an "AS IS" */
-/* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the */
-/* License for the specific language governing rights and limitations under */
-/* the License. */
-/* */
-/* The Original Code is eCos - Embedded Cygnus Operating System, released */
-/* September 30, 1998. */
-/* */
-/* The Initial Developer of the Original Code is Cygnus. Portions created */
-/* by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. */
-/* ------------------------------------------- */
-/* */
-/*####COPYRIGHTEND#### */
-/*============================================================================= */
-/*#####DESCRIPTIONBEGIN#### */
-/* */
-/* Author(s): nickg, jskov */
-/* Contributors: nickg, jskov */
-/* Date: 1999-03-23 */
-/* Purpose: HAL diagnostic output */
-/* Description: Implementations of HAL diagnostic output support. */
-/* */
-/*####DESCRIPTIONEND#### */
-/* */
-/*============================================================================= */
-
-/*----------------------------------------------------------------------------- */
-/* Cogent board specific LCD code */
-
-#include <common.h>
-#include <stdarg.h>
-#include <board/cogent/lcd.h>
-
-static char lines[2][LCD_LINE_LENGTH+1];
-static int curline;
-static int linepos;
-static int heartbeat_active;
-/* make the next two strings exactly LCD_LINE_LENGTH (16) chars long */
-/* pad to the right with spaces if necessary */
-static char init_line0[LCD_LINE_LENGTH+1] = "U-Boot Cogent ";
-static char init_line1[LCD_LINE_LENGTH+1] = "mjj, 11 Aug 2000";
-
-static inline unsigned char
-lcd_read_status(cma_mb_lcd *clp)
-{
- /* read the Busy Status Register */
- return (cma_mb_reg_read(&clp->lcd_bsr));
-}
-
-static inline void
-lcd_wait_not_busy(cma_mb_lcd *clp)
-{
- /*
- * wait for not busy
- * Note: It seems that the LCD isn't quite ready to process commands
- * when it clears the BUSY flag. Reading the status address an extra
- * time seems to give it enough breathing room.
- */
-
- while (lcd_read_status(clp) & LCD_STAT_BUSY)
- ;
-
- (void)lcd_read_status(clp);
-}
-
-static inline void
-lcd_write_command(cma_mb_lcd *clp, unsigned char cmd)
-{
- lcd_wait_not_busy(clp);
-
- /* write the Command Register */
- cma_mb_reg_write(&clp->lcd_cmd, cmd);
-}
-
-static inline void
-lcd_write_data(cma_mb_lcd *clp, unsigned char data)
-{
- lcd_wait_not_busy(clp);
-
- /* write the Current Character Register */
- cma_mb_reg_write(&clp->lcd_ccr, data);
-}
-
-static inline void
-lcd_dis(int addr, char *string)
-{
- cma_mb_lcd *clp = (cma_mb_lcd *)CMA_MB_LCD_BASE;
- int pos, linelen;
-
- linelen = LCD_LINE_LENGTH;
- if (heartbeat_active && addr == LCD_LINE0)
- linelen--;
-
- lcd_write_command(clp, LCD_CMD_ADD + addr);
- for (pos = 0; *string != '\0' && pos < linelen; pos++)
- lcd_write_data(clp, *string++);
-}
-
-void
-lcd_init(void)
-{
- cma_mb_lcd *clp = (cma_mb_lcd *)CMA_MB_LCD_BASE;
- int i;
-
- /* configure the lcd for 8 bits/char, 2 lines and 5x7 dot matrix */
- lcd_write_command(clp, LCD_CMD_MODE);
-
- /* turn the LCD display on */
- lcd_write_command(clp, LCD_CMD_DON);
-
- curline = 0;
- linepos = 0;
-
- for (i = 0; i < LCD_LINE_LENGTH; i++) {
- lines[0][i] = init_line0[i];
- lines[1][i] = init_line1[i];
- }
-
- lines[0][LCD_LINE_LENGTH] = lines[1][LCD_LINE_LENGTH] = 0;
-
- lcd_dis(LCD_LINE0, lines[0]);
- lcd_dis(LCD_LINE1, lines[1]);
-
- printf("HD44780 2 line x %d char display\n", LCD_LINE_LENGTH);
-}
-
-void
-lcd_write_char(const char c)
-{
- int i, linelen;
-
- /* ignore CR */
- if (c == '\r')
- return;
-
- linelen = LCD_LINE_LENGTH;
- if (heartbeat_active && curline == 0)
- linelen--;
-
- if (c == '\n') {
- lcd_dis(LCD_LINE0, &lines[curline^1][0]);
- lcd_dis(LCD_LINE1, &lines[curline][0]);
-
- /* Do a line feed */
- curline ^= 1;
- linelen = LCD_LINE_LENGTH;
- if (heartbeat_active && curline == 0)
- linelen--;
- linepos = 0;
-
- for (i = 0; i < linelen; i++)
- lines[curline][i] = ' ';
-
- return;
- }
-
- /* Only allow to be output if there is room on the LCD line */
- if (linepos < linelen)
- lines[curline][linepos++] = c;
-}
-
-void
-lcd_flush(void)
-{
- lcd_dis(LCD_LINE1, &lines[curline][0]);
-}
-
-void
-lcd_write_string(const char *s)
-{
- char *p;
-
- for (p = (char *)s; *p != '\0'; p++)
- lcd_write_char(*p);
-}
-
-void
-lcd_printf(const char *fmt, ...)
-{
- va_list args;
- char buf[CONFIG_SYS_PBSIZE];
-
- va_start(args, fmt);
- (void)vsprintf(buf, fmt, args);
- va_end(args);
-
- lcd_write_string(buf);
-}
-
-void
-lcd_heartbeat(void)
-{
- cma_mb_lcd *clp = (cma_mb_lcd *)CMA_MB_LCD_BASE;
-#if 0
- static char rotchars[] = { '|', '/', '-', '\\' };
-#else
- /* HD44780 Rom Code A00 has no backslash */
- static char rotchars[] = { '|', '/', '-', '\315' };
-#endif
- static int rotator_index = 0;
-
- heartbeat_active = 1;
-
- /* write the address */
- lcd_write_command(clp, LCD_CMD_ADD + LCD_LINE0 + (LCD_LINE_LENGTH - 1));
-
- /* write the next char in the sequence */
- lcd_write_data(clp, rotchars[rotator_index]);
-
- if (++rotator_index >= (sizeof rotchars / sizeof rotchars[0]))
- rotator_index = 0;
-}
-
-#ifdef CONFIG_SHOW_ACTIVITY
-void board_show_activity (ulong timestamp)
-{
-#ifdef CONFIG_STATUS_LED
- if ((timestamp % (CONFIG_SYS_HZ / 2) == 0)
- lcd_heartbeat ();
-#endif
-}
-
-void show_activity(int arg)
-{
-}
-#endif
+++ /dev/null
-/* most of this is taken from the file */
-/* hal/powerpc/cogent/current/src/hal_diag.c in the */
-/* Cygnus eCos source. Here is the copyright notice: */
-/* */
-/*============================================================================= */
-/* */
-/* hal_diag.c */
-/* */
-/* HAL diagnostic output code */
-/* */
-/*============================================================================= */
-/*####COPYRIGHTBEGIN#### */
-/* */
-/* ------------------------------------------- */
-/* The contents of this file are subject to the Cygnus eCos Public License */
-/* Version 1.0 (the "License"); you may not use this file except in */
-/* compliance with the License. You may obtain a copy of the License at */
-/* http://sourceware.cygnus.com/ecos */
-/* */
-/* Software distributed under the License is distributed on an "AS IS" */
-/* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the */
-/* License for the specific language governing rights and limitations under */
-/* the License. */
-/* */
-/* The Original Code is eCos - Embedded Cygnus Operating System, released */
-/* September 30, 1998. */
-/* */
-/* The Initial Developer of the Original Code is Cygnus. Portions created */
-/* by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. */
-/* ------------------------------------------- */
-/* */
-/*####COPYRIGHTEND#### */
-/*============================================================================= */
-/*#####DESCRIPTIONBEGIN#### */
-/* */
-/* Author(s): nickg, jskov */
-/* Contributors: nickg, jskov */
-/* Date: 1999-03-23 */
-/* Purpose: HAL diagnostic output */
-/* Description: Implementations of HAL diagnostic output support. */
-/* */
-/*####DESCRIPTIONEND#### */
-/* */
-/*============================================================================= */
-
-/* FEMA 162B 16 character x 2 line LCD */
-
-/* status register bit definitions */
-#define LCD_STAT_BUSY 0x80 /* 1 = display busy */
-#define LCD_STAT_ADD 0x7F /* bits 0-6 return current display address */
-
-/* command register definitions */
-#define LCD_CMD_RST 0x01 /* clear entire display and reset display addr */
-#define LCD_CMD_HOME 0x02 /* reset display address and reset any shifting */
-#define LCD_CMD_ECL 0x04 /* move cursor left one pos on next data write */
-#define LCD_CMD_ESL 0x05 /* shift display left one pos on next data write */
-#define LCD_CMD_ECR 0x06 /* move cursor right one pos on next data write */
-#define LCD_CMD_ESR 0x07 /* shift disp right one pos on next data write */
-#define LCD_CMD_DOFF 0x08 /* display off, cursor off, blinking off */
-#define LCD_CMD_BL 0x09 /* blink character at current cursor position */
-#define LCD_CMD_CUR 0x0A /* enable cursor on */
-#define LCD_CMD_DON 0x0C /* turn display on */
-#define LCD_CMD_CL 0x10 /* move cursor left one position */
-#define LCD_CMD_SL 0x14 /* shift display left one position */
-#define LCD_CMD_CR 0x18 /* move cursor right one position */
-#define LCD_CMD_SR 0x1C /* shift display right one position */
-#define LCD_CMD_MODE 0x38 /* sets 8 bits, 2 lines, 5x7 characters */
-#define LCD_CMD_ACG 0x40 /* bits 0-5 sets character generator address */
-#define LCD_CMD_ADD 0x80 /* bits 0-6 sets display data addr to line 1 + */
-
-/* LCD status values */
-#define LCD_OK 0x00
-#define LCD_ERR 0x01
-
-#define LCD_LINE0 0x00
-#define LCD_LINE1 0x40
-
-#define LCD_LINE_LENGTH 16
-
-extern void lcd_init(void);
-extern void lcd_write_char(const char);
-extern void lcd_flush(void);
-extern void lcd_write_string(const char *);
-extern void lcd_printf(const char *, ...);
+++ /dev/null
-/*
- *
- * Generic Header information generated by 13704CFG.EXE (Build 10)
- *
- * Copyright (c) 2000,2001 Epson Research and Development, Inc.
- * All rights reserved.
- *
- * Panel: 320x240x4bpp 78Hz Mono 4-Bit STN, Disabled (PCLK=6.666MHz)
- *
- * This file defines the configuration environment and registers,
- * which can be used by any software, such as display drivers.
- *
- * PLEASE NOTE: If you FTP this file to a non-Windows platform, make
- * sure you transfer this file using ASCII, not BINARY
- * mode.
- *
- */
-
-static S1D_REGS regs_13704_320_240_4bpp[] =
-{
- { 0x00, 0x00 }, /* Revision Code Register */
- { 0x01, 0x04 }, /*00*/ /* Mode Register 0 Register */
- { 0x02, 0xA4 }, /*a0*/ /* Mode Register 1 Register */
- { 0x03, 0x83 }, /*03*/ /* Mode Register 2 Register - bit7 is LUT bypass */
- { 0x04, 0x27 }, /* Horizontal Panel Size Register */
- { 0x05, 0xEF }, /* Vertical Panel Size Register (LSB) */
- { 0x06, 0x00 }, /* Vertical Panel Size Register (MSB) */
- { 0x07, 0x00 }, /* FPLINE Start Position Register */
- { 0x08, 0x00 }, /* Horizontal Non-Display Period Register */
- { 0x09, 0x00 }, /* FPFRAME Start Position Register */
- { 0x0A, 0x02 }, /* Vertical Non-Display Period Register */
- { 0x0B, 0x00 }, /* MOD Rate Register */
- { 0x0C, 0x00 }, /* Screen 1 Start Address Register (LSB) */
- { 0x0D, 0x00 }, /* Screen 1 Start Address Register (MSB) */
- { 0x0E, 0x00 }, /* Not Used */
- { 0x0F, 0x00 }, /* Screen 2 Start Address Register (LSB) */
- { 0x10, 0x00 }, /* Screen 2 Start Address Register (MSB) */
- { 0x11, 0x00 }, /* Not Used */
- { 0x12, 0x00 }, /* Memory Address Offset Register */
- { 0x13, 0xFF }, /* Screen 1 Vertical Size Register (LSB) */
- { 0x14, 0x03 }, /* Screen 1 Vertical Size Register (MSB) */
- { 0x15, 0x00 }, /* Look-Up Table Address Register */
- { 0x16, 0x00 }, /* Look-Up Table Bank Select Register */
- { 0x17, 0x00 }, /* Look-Up Table Data Register */
- { 0x18, 0x01 }, /* GPIO Configuration Control Register */
- { 0x19, 0x01 }, /* GPIO Status/Control Register */
- { 0x1A, 0x00 }, /* Scratch Pad Register */
- { 0x1B, 0x00 }, /* SwivelView Mode Register */
- { 0x1C, 0xA0 }, /* Line Byte Count Register */
- { 0x1D, 0x00 }, /* Not Used */
- { 0x1E, 0x00 }, /* Not Used */
- { 0x1F, 0x00 }, /* Not Used */
-};
+++ /dev/null
-/*
- *
- * Generic Header information generated by 13704CFG.EXE (Build 10)
- *
- * Copyright (c) 2000,2001 Epson Research and Development, Inc.
- * All rights reserved.
- *
- * Panel: 320x240x8bpp 78Hz Mono 8-Bit STN, Disabled (PCLK=6.666MHz)
- *
- * This file defines the configuration environment and registers,
- * which can be used by any software, such as display drivers.
- *
- * PLEASE NOTE: If you FTP this file to a non-Windows platform, make
- * sure you transfer this file using ASCII, not BINARY
- * mode.
- *
- */
-
-static S1D_REGS regs_13705_320_240_8bpp[] =
-{
- { 0x00, 0x00 }, /* Revision Code Register */
- { 0x01, 0x23 }, /* Mode Register 0 Register */
- { 0x02, 0xE0 }, /* Mode Register 1 Register */
- { 0x03, 0x03 }, /* Mode Register 2 Register - bit7 is LUT bypass */
- { 0x04, 0x27 }, /* Horizontal Panel Size Register */
- { 0x05, 0xEF }, /* Vertical Panel Size Register (LSB) */
- { 0x06, 0x00 }, /* Vertical Panel Size Register (MSB) */
- { 0x07, 0x00 }, /* FPLINE Start Position Register */
- { 0x08, 0x00 }, /* Horizontal Non-Display Period Register */
- { 0x09, 0x01 }, /* FPFRAME Start Position Register */
- { 0x0A, 0x02 }, /* Vertical Non-Display Period Register */
- { 0x0B, 0x00 }, /* MOD Rate Register */
- { 0x0C, 0x00 }, /* Screen 1 Start Address Register (LSB) */
- { 0x0D, 0x00 }, /* Screen 1 Start Address Register (MSB) */
- { 0x0E, 0x00 }, /* Not Used */
- { 0x0F, 0x00 }, /* Screen 2 Start Address Register (LSB) */
- { 0x10, 0x00 }, /* Screen 2 Start Address Register (MSB) */
- { 0x11, 0x00 }, /* Not Used */
- { 0x12, 0x00 }, /* Memory Address Offset Register */
- { 0x13, 0xFF }, /* Screen 1 Vertical Size Register (LSB) */
- { 0x14, 0x03 }, /* Screen 1 Vertical Size Register (MSB) */
- { 0x15, 0x00 }, /* Look-Up Table Address Register */
- { 0x16, 0x00 }, /* Look-Up Table Bank Select Register */
- { 0x17, 0x00 }, /* Look-Up Table Data Register */
- { 0x18, 0x01 }, /* GPIO Configuration Control Register */
- { 0x19, 0x01 }, /* GPIO Status/Control Register */
- { 0x1A, 0x00 }, /* Scratch Pad Register */
- { 0x1B, 0x00 }, /* SwivelView Mode Register */
- { 0x1C, 0xFF }, /* Line Byte Count Register */
- { 0x1D, 0x00 }, /* Not Used */
- { 0x1E, 0x00 }, /* Not Used */
- { 0x1F, 0x00 }, /* Not Used */
-};
+++ /dev/null
-/*
- *
- * File generated by S1D13806CFG.EXE
- *
- * Copyright (c) 2000,2001 Epson Research and Development, Inc.
- * All rights reserved.
- *
- * PLEASE NOTE: If you FTP this file to a non-Windows platform, make
- * sure you transfer this file using ASCII, not BINARY mode.
- *
- * Panel: (active) 1024x768 34Hz TFT Single 12-bit (PCLK=BUSCLK=33.333MHz)
- * Memory: Embedded SDRAM (MCLK=CLKI=49.100MHz) (BUSCLK=33.333MHz)
- *
- */
-
-static S1D_REGS regs_13806_1024_768_8bpp[] =
-{
- {0x0001,0x00}, /* Miscellaneous Register */
- {0x01FC,0x00}, /* Display Mode Register */
- {0x0004,0x00}, /* General IO Pins Configuration Register 0 */
- {0x0005,0x00}, /* General IO Pins Configuration Register 1 */
- {0x0008,0x00}, /* General IO Pins Control Register 0 */
- {0x0009,0x00}, /* General IO Pins Control Register 1 */
- {0x0010,0x00}, /* Memory Clock Configuration Register */
- {0x0014,0x01}, /* LCD Pixel Clock Configuration Register */
- {0x0018,0x00}, /* CRT/TV Pixel Clock Configuration Register */
- {0x001C,0x02}, /* MediaPlug Clock Configuration Register */
- {0x001E,0x01}, /* CPU To Memory Wait State Select Register */
- {0x0021,0x03}, /* DRAM Refresh Rate Register */
- {0x002A,0x00}, /* DRAM Timings Control Register 0 */
- {0x002B,0x01}, /* DRAM Timings Control Register 1 */
- {0x0020,0x80}, /* Memory Configuration Register */
- {0x0030,0x55}, /* Panel Type Register */
- {0x0031,0x00}, /* MOD Rate Register */
- {0x0032,0x7F}, /* LCD Horizontal Display Width Register */
- {0x0034,0x12}, /* LCD Horizontal Non-Display Period Register */
- {0x0035,0x01}, /* TFT FPLINE Start Position Register */
- {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */
- {0x0038,0xFF}, /* LCD Vertical Display Height Register 0 */
- {0x0039,0x02}, /* LCD Vertical Display Height Register 1 */
- {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */
- {0x003B,0x0A}, /* TFT FPFRAME Start Position Register */
- {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */
- {0x0040,0x03}, /* LCD Display Mode Register */
- {0x0041,0x00}, /* LCD Miscellaneous Register */
- {0x0042,0x00}, /* LCD Display Start Address Register 0 */
- {0x0043,0x00}, /* LCD Display Start Address Register 1 */
- {0x0044,0x00}, /* LCD Display Start Address Register 2 */
- {0x0046,0x00}, /* LCD Memory Address Offset Register 0 */
- {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */
- {0x0048,0x00}, /* LCD Pixel Panning Register */
- {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */
- {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */
- {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */
- {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */
- {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */
- {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */
- {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */
- {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */
- {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */
- {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */
- {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */
- {0x005B,0x10}, /* TV Output Control Register */
- {0x0060,0x03}, /* CRT/TV Display Mode Register */
- {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */
- {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */
- {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */
- {0x0066,0x40}, /* CRT/TV Memory Address Offset Register 0 */
- {0x0067,0x01}, /* CRT/TV Memory Address Offset Register 1 */
- {0x0068,0x00}, /* CRT/TV Pixel Panning Register */
- {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */
- {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */
- {0x0070,0x00}, /* LCD Ink/Cursor Control Register */
- {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */
- {0x0072,0x00}, /* LCD Cursor X Position Register 0 */
- {0x0073,0x00}, /* LCD Cursor X Position Register 1 */
- {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */
- {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */
- {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */
- {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */
- {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */
- {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */
- {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */
- {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */
- {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */
- {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */
- {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */
- {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */
- {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */
- {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */
- {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */
- {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */
- {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */
- {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */
- {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */
- {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */
- {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */
- {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */
- {0x0100,0x00}, /* BitBlt Control Register 0 */
- {0x0101,0x00}, /* BitBlt Control Register 1 */
- {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */
- {0x0103,0x00}, /* BitBlt Operation Register */
- {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */
- {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */
- {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */
- {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */
- {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */
- {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */
- {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */
- {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */
- {0x0110,0x00}, /* BitBlt Width Register 0 */
- {0x0111,0x00}, /* BitBlt Width Register 1 */
- {0x0112,0x00}, /* BitBlt Height Register 0 */
- {0x0113,0x00}, /* BitBlt Height Register 1 */
- {0x0114,0x00}, /* BitBlt Background Color Register 0 */
- {0x0115,0x00}, /* BitBlt Background Color Register 1 */
- {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */
- {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */
- {0x01E0,0x00}, /* Look-Up Table Mode Register */
- {0x01E2,0x00}, /* Look-Up Table Address Register */
- {0x01F0,0x10}, /* Power Save Configuration Register */
- {0x01F1,0x00}, /* Power Save Status Register */
- {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */
- {0x01FC,0x01}, /* Display Mode Register */
-};
+++ /dev/null
-/*
- *
- * File generated by S1D13806CFG.EXE
- *
- * Copyright (c) 2000,2001 Epson Research and Development, Inc.
- * All rights reserved.
- *
- * PLEASE NOTE: If you FTP this file to a non-Windows platform, make
- * sure you transfer this file using ASCII, not BINARY mode.
- *
- * Panel: (active) 320x240 62Hz STN Single 4-bit (PCLK=CLKI2/4=6.250MHz)
- * Memory: Embedded SDRAM (MCLK=CLKI=49.500MHz) (BUSCLK=33.333MHz)
- *
- */
-
-static S1D_REGS regs_13806_320_240_4bpp[] =
-{
- {0x0001,0x00}, /* Miscellaneous Register */
- {0x01FC,0x00}, /* Display Mode Register */
- {0x0004,0x08}, /* General IO Pins Configuration Register 0 */
- {0x0005,0x08}, /* General IO Pins Configuration Register 1 */
- {0x0008,0x08}, /* General IO Pins Control Register 0 */
- {0x0009,0x00}, /* General IO Pins Control Register 1 */
- {0x0010,0x00}, /* Memory Clock Configuration Register */
- {0x0014,0x32}, /* LCD Pixel Clock Configuration Register */
- {0x0018,0x00}, /* CRT/TV Pixel Clock Configuration Register */
- {0x001C,0x02}, /* MediaPlug Clock Configuration Register */
- {0x001E,0x01}, /* CPU To Memory Wait State Select Register */
- {0x0021,0x03}, /* DRAM Refresh Rate Register */
- {0x002A,0x00}, /* DRAM Timings Control Register 0 */
- {0x002B,0x01}, /* DRAM Timings Control Register 1 */
- {0x0020,0x80}, /* Memory Configuration Register */
- {0x0030,0x00}, /* Panel Type Register */
- {0x0031,0x00}, /* MOD Rate Register */
- {0x0032,0x27}, /* LCD Horizontal Display Width Register */
- {0x0034,0x03}, /* LCD Horizontal Non-Display Period Register */
- {0x0035,0x01}, /* TFT FPLINE Start Position Register */
- {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */
- {0x0038,0xEF}, /* LCD Vertical Display Height Register 0 */
- {0x0039,0x00}, /* LCD Vertical Display Height Register 1 */
- {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */
- {0x003B,0x0A}, /* TFT FPFRAME Start Position Register */
- {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */
- {0x0040,0x02}, /* LCD Display Mode Register */
- {0x0041,0x00}, /* LCD Miscellaneous Register */
- {0x0042,0x00}, /* LCD Display Start Address Register 0 */
- {0x0043,0x00}, /* LCD Display Start Address Register 1 */
- {0x0044,0x00}, /* LCD Display Start Address Register 2 */
- {0x0046,0x50}, /* LCD Memory Address Offset Register 0 */
- {0x0047,0x00}, /* LCD Memory Address Offset Register 1 */
- {0x0048,0x00}, /* LCD Pixel Panning Register */
- {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */
- {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */
- {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */
- {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */
- {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */
- {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */
- {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */
- {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */
- {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */
- {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */
- {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */
- {0x005B,0x10}, /* TV Output Control Register */
- {0x0060,0x03}, /* CRT/TV Display Mode Register */
- {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */
- {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */
- {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */
- {0x0066,0x40}, /* CRT/TV Memory Address Offset Register 0 */
- {0x0067,0x01}, /* CRT/TV Memory Address Offset Register 1 */
- {0x0068,0x00}, /* CRT/TV Pixel Panning Register */
- {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */
- {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */
- {0x0070,0x00}, /* LCD Ink/Cursor Control Register */
- {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */
- {0x0072,0x00}, /* LCD Cursor X Position Register 0 */
- {0x0073,0x00}, /* LCD Cursor X Position Register 1 */
- {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */
- {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */
- {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */
- {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */
- {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */
- {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */
- {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */
- {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */
- {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */
- {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */
- {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */
- {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */
- {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */
- {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */
- {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */
- {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */
- {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */
- {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */
- {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */
- {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */
- {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */
- {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */
- {0x0100,0x00}, /* BitBlt Control Register 0 */
- {0x0101,0x00}, /* BitBlt Control Register 1 */
- {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */
- {0x0103,0x00}, /* BitBlt Operation Register */
- {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */
- {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */
- {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */
- {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */
- {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */
- {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */
- {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */
- {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */
- {0x0110,0x00}, /* BitBlt Width Register 0 */
- {0x0111,0x00}, /* BitBlt Width Register 1 */
- {0x0112,0x00}, /* BitBlt Height Register 0 */
- {0x0113,0x00}, /* BitBlt Height Register 1 */
- {0x0114,0x00}, /* BitBlt Background Color Register 0 */
- {0x0115,0x00}, /* BitBlt Background Color Register 1 */
- {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */
- {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */
- {0x01E0,0x00}, /* Look-Up Table Mode Register */
- {0x01E2,0x00}, /* Look-Up Table Address Register */
- {0x01F0,0x10}, /* Power Save Configuration Register */
- {0x01F1,0x00}, /* Power Save Status Register */
- {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */
- {0x01FC,0x01}, /* Display Mode Register */
-};
+++ /dev/null
-/*
- *
- * File generated by S1D13806CFG.EXE
- *
- * Copyright (c) 2000,2001 Epson Research and Development, Inc.
- * All rights reserved.
- *
- * PLEASE NOTE: If you FTP this file to a non-Windows platform, make
- * sure you transfer this file using ASCII, not BINARY mode.
- *
- * Panel: (active) 640x480 59Hz TFT Single 18-bit (PCLK=CLKI2=25.000MHz)
- * Memory: Embedded SDRAM (MCLK=CLKI=49.152MHz) (BUSCLK=33.333MHz)
- *
- */
-
-static S1D_REGS regs_13806_640_480_16bpp[] =
-{
- {0x0001,0x00}, /* Miscellaneous Register */
- {0x01FC,0x00}, /* Display Mode Register */
- {0x0004,0x18}, /* General IO Pins Configuration Register 0 */
- {0x0005,0x00}, /* General IO Pins Configuration Register 1 */
- {0x0008,0x18}, /* General IO Pins Control Register 0 */
- {0x0009,0x00}, /* General IO Pins Control Register 1 */
- {0x0010,0x00}, /* Memory Clock Configuration Register */
- {0x0014,0x02}, /* LCD Pixel Clock Configuration Register */
- {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */
- {0x001C,0x02}, /* MediaPlug Clock Configuration Register */
- {0x001E,0x01}, /* CPU To Memory Wait State Select Register */
- {0x0021,0x03}, /* DRAM Refresh Rate Register */
- {0x002A,0x00}, /* DRAM Timings Control Register 0 */
- {0x002B,0x01}, /* DRAM Timings Control Register 1 */
- {0x0020,0x80}, /* Memory Configuration Register */
- {0x0030,0x25}, /* Panel Type Register */
- {0x0031,0x00}, /* MOD Rate Register */
- {0x0032,0x4F}, /* LCD Horizontal Display Width Register */
- {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */
- {0x0035,0x00}, /* TFT FPLINE Start Position Register */
- {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */
- {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */
- {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */
- {0x003A,0x24}, /* LCD Vertical Non-Display Period Register */
- {0x003B,0x00}, /* TFT FPFRAME Start Position Register */
- {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */
- {0x0040,0x05}, /* LCD Display Mode Register */
- {0x0041,0x00}, /* LCD Miscellaneous Register */
- {0x0042,0x00}, /* LCD Display Start Address Register 0 */
- {0x0043,0x00}, /* LCD Display Start Address Register 1 */
- {0x0044,0x00}, /* LCD Display Start Address Register 2 */
- {0x0046,0x80}, /* LCD Memory Address Offset Register 0 */
- {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */
- {0x0048,0x00}, /* LCD Pixel Panning Register */
- {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */
- {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */
- {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */
- {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */
- {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */
- {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */
- {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */
- {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */
- {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */
- {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */
- {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */
- {0x005B,0x10}, /* TV Output Control Register */
- {0x0060,0x05}, /* CRT/TV Display Mode Register */
- {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */
- {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */
- {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */
- {0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */
- {0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */
- {0x0068,0x00}, /* CRT/TV Pixel Panning Register */
- {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */
- {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */
- {0x0070,0x00}, /* LCD Ink/Cursor Control Register */
- {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */
- {0x0072,0x00}, /* LCD Cursor X Position Register 0 */
- {0x0073,0x00}, /* LCD Cursor X Position Register 1 */
- {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */
- {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */
- {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */
- {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */
- {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */
- {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */
- {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */
- {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */
- {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */
- {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */
- {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */
- {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */
- {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */
- {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */
- {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */
- {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */
- {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */
- {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */
- {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */
- {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */
- {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */
- {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */
- {0x0100,0x00}, /* BitBlt Control Register 0 */
- {0x0101,0x00}, /* BitBlt Control Register 1 */
- {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */
- {0x0103,0x00}, /* BitBlt Operation Register */
- {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */
- {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */
- {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */
- {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */
- {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */
- {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */
- {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */
- {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */
- {0x0110,0x00}, /* BitBlt Width Register 0 */
- {0x0111,0x00}, /* BitBlt Width Register 1 */
- {0x0112,0x00}, /* BitBlt Height Register 0 */
- {0x0113,0x00}, /* BitBlt Height Register 1 */
- {0x0114,0x00}, /* BitBlt Background Color Register 0 */
- {0x0115,0x00}, /* BitBlt Background Color Register 1 */
- {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */
- {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */
- {0x01E0,0x00}, /* Look-Up Table Mode Register */
- {0x01E2,0x00}, /* Look-Up Table Address Register */
- {0x01F0,0x10}, /* Power Save Configuration Register */
- {0x01F1,0x00}, /* Power Save Status Register */
- {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */
- {0x01FC,0x01}, /* Display Mode Register */
-};
+++ /dev/null
-/*
- *
- * File generated by S1D13806CFG.EXE
- *
- * Copyright (c) 2000,2001 Epson Research and Development, Inc.
- * All rights reserved.
- *
- * PLEASE NOTE: If you FTP this file to a non-Windows platform, make
- * sure you transfer this file using ASCII, not BINARY mode.
- *
- * Panel: (active) 640x480 59Hz TFT Single 18-bit (PCLK=CLKI2=25.000MHz)
- * Memory: Embedded SDRAM (MCLK=CLKI=49.152MHz) (BUSCLK=33.333MHz)
- *
- */
-
-static S1D_REGS regs_13806_640_320_16bpp[] =
-{
- {0x0001,0x00}, /* Miscellaneous Register */
- {0x01FC,0x00}, /* Display Mode Register */
- {0x0004,0x18}, /* General IO Pins Configuration Register 0 */
- {0x0005,0x00}, /* General IO Pins Configuration Register 1 */
- {0x0008,0x18}, /* General IO Pins Control Register 0 */
- {0x0009,0x00}, /* General IO Pins Control Register 1 */
- {0x0010,0x00}, /* Memory Clock Configuration Register */
- {0x0014,0x02}, /* LCD Pixel Clock Configuration Register */
- {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */
- {0x001C,0x02}, /* MediaPlug Clock Configuration Register */
- {0x001E,0x01}, /* CPU To Memory Wait State Select Register */
- {0x0021,0x03}, /* DRAM Refresh Rate Register */
- {0x002A,0x00}, /* DRAM Timings Control Register 0 */
- {0x002B,0x01}, /* DRAM Timings Control Register 1 */
- {0x0020,0x80}, /* Memory Configuration Register */
- {0x0030,0x25}, /* Panel Type Register */
- {0x0031,0x00}, /* MOD Rate Register */
- {0x0032,0x4F}, /* LCD Horizontal Display Width Register */
- {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */
- {0x0035,0x00}, /* TFT FPLINE Start Position Register */
- {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */
- {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */
- {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */
- {0x003A,0x24}, /* LCD Vertical Non-Display Period Register */
- {0x003B,0x00}, /* TFT FPFRAME Start Position Register */
- {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */
- {0x0040,0x03}, /* LCD Display Mode Register (8bpp) */
- {0x0041,0x00}, /* LCD Miscellaneous Register */
- {0x0042,0x00}, /* LCD Display Start Address Register 0 */
- {0x0043,0x00}, /* LCD Display Start Address Register 1 */
- {0x0044,0x00}, /* LCD Display Start Address Register 2 */
- {0x0046,0x80}, /* LCD Memory Address Offset Register 0 */
- {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */
- {0x0048,0x00}, /* LCD Pixel Panning Register */
- {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */
- {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */
- {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */
- {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */
- {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */
- {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */
- {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */
- {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */
- {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */
- {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */
- {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */
- {0x005B,0x10}, /* TV Output Control Register */
- {0x0060,0x05}, /* CRT/TV Display Mode Register */
- {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */
- {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */
- {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */
- {0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */
- {0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */
- {0x0068,0x00}, /* CRT/TV Pixel Panning Register */
- {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */
- {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */
- {0x0070,0x00}, /* LCD Ink/Cursor Control Register */
- {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */
- {0x0072,0x00}, /* LCD Cursor X Position Register 0 */
- {0x0073,0x00}, /* LCD Cursor X Position Register 1 */
- {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */
- {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */
- {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */
- {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */
- {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */
- {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */
- {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */
- {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */
- {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */
- {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */
- {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */
- {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */
- {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */
- {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */
- {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */
- {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */
- {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */
- {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */
- {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */
- {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */
- {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */
- {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */
- {0x0100,0x00}, /* BitBlt Control Register 0 */
- {0x0101,0x00}, /* BitBlt Control Register 1 */
- {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */
- {0x0103,0x00}, /* BitBlt Operation Register */
- {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */
- {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */
- {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */
- {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */
- {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */
- {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */
- {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */
- {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */
- {0x0110,0x00}, /* BitBlt Width Register 0 */
- {0x0111,0x00}, /* BitBlt Width Register 1 */
- {0x0112,0x00}, /* BitBlt Height Register 0 */
- {0x0113,0x00}, /* BitBlt Height Register 1 */
- {0x0114,0x00}, /* BitBlt Background Color Register 0 */
- {0x0115,0x00}, /* BitBlt Background Color Register 1 */
- {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */
- {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */
- {0x01E0,0x00}, /* Look-Up Table Mode Register */
- {0x01E2,0x00}, /* Look-Up Table Address Register */
- {0x01F0,0x10}, /* Power Save Configuration Register */
- {0x01F1,0x00}, /* Power Save Status Register */
- {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */
- {0x01FC,0x01}, /* Display Mode Register */
-};
+++ /dev/null
-/*---------------------------------------------------------------------------- */
-/* */
-/* File generated by S1D13706CFG.EXE */
-/* */
-/* Copyright (c) 2000,2001 Epson Research and Development, Inc. */
-/* All rights reserved. */
-/* */
-/*---------------------------------------------------------------------------- */
-
-/* Panel: 320x240x8bpp 70Hz Color Single STN 8-bit (PCLK=6.250MHz) (Format 2) */
-
-#define S1D_DISPLAY_WIDTH 320
-#define S1D_DISPLAY_HEIGHT 240
-#define S1D_DISPLAY_BPP 8
-#define S1D_DISPLAY_SCANLINE_BYTES 320
-#define S1D_PHYSICAL_VMEM_ADDR 0x800A0000L
-#define S1D_PHYSICAL_VMEM_SIZE 0x14000L
-#define S1D_PHYSICAL_REG_ADDR 0x80080000L
-#define S1D_PHYSICAL_REG_SIZE 0x100
-#define S1D_DISPLAY_PCLK 6250
-#define S1D_PALETTE_SIZE 256
-#define S1D_REGDELAYOFF 0xFFFE
-#define S1D_REGDELAYON 0xFFFF
-
-#define S1D_WRITE_PALETTE(p,i,r,g,b) \
-{ \
- ((volatile S1D_VALUE*)(p))[0x0A/sizeof(S1D_VALUE)] = (S1D_VALUE)((r)>>4); \
- ((volatile S1D_VALUE*)(p))[0x09/sizeof(S1D_VALUE)] = (S1D_VALUE)((g)>>4); \
- ((volatile S1D_VALUE*)(p))[0x08/sizeof(S1D_VALUE)] = (S1D_VALUE)((b)>>4); \
- ((volatile S1D_VALUE*)(p))[0x0B/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \
-}
-
-#define S1D_READ_PALETTE(p,i,r,g,b) \
-{ \
- ((volatile S1D_VALUE*)(p))[0x0F/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \
- r = ((volatile S1D_VALUE*)(p))[0x0E/sizeof(S1D_VALUE)]; \
- g = ((volatile S1D_VALUE*)(p))[0x0D/sizeof(S1D_VALUE)]; \
- b = ((volatile S1D_VALUE*)(p))[0x0C/sizeof(S1D_VALUE)]; \
-}
-
-typedef unsigned short S1D_INDEX;
-typedef unsigned char S1D_VALUE;
-
-
-typedef struct
-{
- S1D_INDEX Index;
- S1D_VALUE Value;
-} S1D_REGS;
-
-
-static S1D_REGS aS1DRegs_prelimn[] =
-{
- {0x10,0x00}, /* PANEL Type Register */
- {0xA8,0x00}, /* GPIO Config Register 0 */
- {0xA9,0x80}, /* GPIO Config Register 1 */
-
-};
-
-static S1D_REGS aS1DRegs_stn[] =
-{
- {0x04,0x10}, /* BUSCLK MEMCLK Config Register */
- {0x10,0xD0}, /* PANEL Type Register */
- {0x11,0x00}, /* MOD Rate Register */
- {0x14,0x27}, /* Horizontal Display Period Register */
- {0x16,0x00}, /* Horizontal Display Period Start Pos Register 0 */
- {0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */
- {0x18,0xF0}, /* Vertical Total Register 0 */
- {0x19,0x00}, /* Vertical Total Register 1 */
- {0x1C,0xEF}, /* Vertical Display Period Register 0 */
- {0x1D,0x00}, /* Vertical Display Period Register 1 */
- {0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */
- {0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */
- {0x20,0x87}, /* Horizontal Sync Pulse Width Register */
- {0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */
- {0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */
- {0x24,0x80}, /* Vertical Sync Pulse Width Register */
- {0x26,0x01}, /* Vertical Sync Pulse Start Pos Register 0 */
- {0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */
- {0x70,0x83}, /* Display Mode Register */
- {0x71,0x00}, /* Special Effects Register */
- {0x74,0x00}, /* Main Window Display Start Address Register 0 */
- {0x75,0x00}, /* Main Window Display Start Address Register 1 */
- {0x76,0x00}, /* Main Window Display Start Address Register 2 */
- {0x78,0x50}, /* Main Window Address Offset Register 0 */
- {0x79,0x00}, /* Main Window Address Offset Register 1 */
- {0x7C,0x00}, /* Sub Window Display Start Address Register 0 */
- {0x7D,0x00}, /* Sub Window Display Start Address Register 1 */
- {0x7E,0x00}, /* Sub Window Display Start Address Register 2 */
- {0x80,0x50}, /* Sub Window Address Offset Register 0 */
- {0x81,0x00}, /* Sub Window Address Offset Register 1 */
- {0x84,0x00}, /* Sub Window X Start Pos Register 0 */
- {0x85,0x00}, /* Sub Window X Start Pos Register 1 */
- {0x88,0x00}, /* Sub Window Y Start Pos Register 0 */
- {0x89,0x00}, /* Sub Window Y Start Pos Register 1 */
- {0x8C,0x4F}, /* Sub Window X End Pos Register 0 */
- {0x8D,0x00}, /* Sub Window X End Pos Register 1 */
- {0x90,0xEF}, /* Sub Window Y End Pos Register 0 */
- {0x91,0x00}, /* Sub Window Y End Pos Register 1 */
- {0xA0,0x00}, /* Power Save Config Register */
- {0xA1,0x00}, /* CPU Access Control Register */
- {0xA2,0x00}, /* Software Reset Register */
- {0xA3,0x00}, /* BIG Endian Support Register */
- {0xA4,0x00}, /* Scratch Pad Register 0 */
- {0xA5,0x00}, /* Scratch Pad Register 1 */
- {0xA8,0x01}, /* GPIO Config Register 0 */
- {0xA9,0x80}, /* GPIO Config Register 1 */
- {0xAC,0x01}, /* GPIO Status Control Register 0 */
- {0xAD,0x00}, /* GPIO Status Control Register 1 */
- {0xB0,0x10}, /* PWM CV Clock Control Register */
- {0xB1,0x80}, /* PWM CV Clock Config Register */
- {0xB2,0x00}, /* CV Clock Burst Length Register */
- {0xAD,0x80}, /* reset seq */
- {0x70,0x03},
-};
-
-static S1D_REGS aS1DRegs_tft[] =
-{
- {0x04,0x10}, /* BUSCLK MEMCLK Config Register */
- {0x05,0x42}, /* PCLK Config Register */
- {0x10,0x61}, /* PANEL Type Register */
- {0x11,0x00}, /* MOD Rate Register */
- {0x12,0x30}, /* Horizontal Total Register */
- {0x14,0x27}, /* Horizontal Display Period Register */
- {0x16,0x11}, /* Horizontal Display Period Start Pos Register 0 */
- {0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */
- {0x18,0xFA}, /* Vertical Total Register 0 */
- {0x19,0x00}, /* Vertical Total Register 1 */
- {0x1C,0xEF}, /* Vertical Display Period Register 0 */
- {0x1D,0x00}, /* Vertical Display Period Register 1 */
- {0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */
- {0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */
- {0x20,0x07}, /* Horizontal Sync Pulse Width Register */
- {0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */
- {0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */
- {0x24,0x00}, /* Vertical Sync Pulse Width Register */
- {0x26,0x00}, /* Vertical Sync Pulse Start Pos Register 0 */
- {0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */
- {0x70,0x03}, /* Display Mode Register */
- {0x71,0x00}, /* Special Effects Register */
- {0x74,0x00}, /* Main Window Display Start Address Register 0 */
- {0x75,0x00}, /* Main Window Display Start Address Register 1 */
- {0x76,0x00}, /* Main Window Display Start Address Register 2 */
- {0x78,0x50}, /* Main Window Address Offset Register 0 */
- {0x79,0x00}, /* Main Window Address Offset Register 1 */
- {0x7C,0x00}, /* Sub Window Display Start Address Register 0 */
- {0x7D,0x00}, /* Sub Window Display Start Address Register 1 */
- {0x7E,0x00}, /* Sub Window Display Start Address Register 2 */
- {0x80,0x50}, /* Sub Window Address Offset Register 0 */
- {0x81,0x00}, /* Sub Window Address Offset Register 1 */
- {0x84,0x00}, /* Sub Window X Start Pos Register 0 */
- {0x85,0x00}, /* Sub Window X Start Pos Register 1 */
- {0x88,0x00}, /* Sub Window Y Start Pos Register 0 */
- {0x89,0x00}, /* Sub Window Y Start Pos Register 1 */
- {0x8C,0x4F}, /* Sub Window X End Pos Register 0 */
- {0x8D,0x00}, /* Sub Window X End Pos Register 1 */
- {0x90,0xEF}, /* Sub Window Y End Pos Register 0 */
- {0x91,0x00}, /* Sub Window Y End Pos Register 1 */
- {0xA0,0x00}, /* Power Save Config Register */
- {0xA1,0x00}, /* CPU Access Control Register */
- {0xA2,0x00}, /* Software Reset Register */
- {0xA3,0x00}, /* BIG Endian Support Register */
- {0xA4,0x00}, /* Scratch Pad Register 0 */
- {0xA5,0x00}, /* Scratch Pad Register 1 */
- {0xA8,0x01}, /* GPIO Config Register 0 */
- {0xA9,0x80}, /* GPIO Config Register 1 */
- {0xAC,0x01}, /* GPIO Status Control Register 0 */
- {0xAD,0x00}, /* GPIO Status Control Register 1 */
- {0xB0,0x10}, /* PWM CV Clock Control Register */
- {0xB1,0x80}, /* PWM CV Clock Config Register */
- {0xB2,0x00}, /* CV Clock Burst Length Register */
- {0xAD,0x80}, /* reset seq */
- {0x70,0x03},
-};
+++ /dev/null
-#ifndef __dimm_h
-#define __dimm_h
-
-/*
- * Module name: %M%
- * Description:
- * Serial Presence Detect Definitions Module
- * SCCS identification: %I%
- * Branch: %B%
- * Sequence: %S%
- * Date newest applied delta was created (MM/DD/YY): %G%
- * Time newest applied delta was created (HH:MM:SS): %U%
- * SCCS file name %F%
- * Fully qualified SCCS file name:
- * %P%
- * Copyright:
- * (C) COPYRIGHT MOTOROLA, INC. 1996
- * ALL RIGHTS RESERVED
- * Notes:
- * 1. All data was taken from an IBM application note titled
- * "Serial Presence Detect Definitions".
- * History:
- * Date Who
- *
- * 10/24/96 Rob Baxter
- * Initial release.
- *
- */
-
-/*
- * serial PD byte assignment address map (256 byte EEPROM)
- */
-typedef struct dimm
-{
- uchar n_bytes; /* 00 number of bytes written/used */
- uchar t_bytes; /* 01 total number of bytes in serial PD device */
- uchar fmt; /* 02 fundamental memory type (FPM/EDO/SDRAM) */
- uchar n_row; /* 03 number of rows */
- uchar n_col; /* 04 number of columns */
- uchar n_banks; /* 05 number of banks */
- uchar data_w_lo; /* 06 data width */
- uchar data_w_hi; /* 07 data width */
- uchar ifl; /* 08 interface levels */
- uchar a_ras; /* 09 RAS access */
- uchar a_cas; /* 0A CAS access */
- uchar ct; /* 0B configuration type (non-parity/parity/ECC) */
- uchar refresh_rt; /* 0C refresh rate/type */
- uchar p_dram_o; /* 0D primary DRAM organization */
- uchar s_dram_o; /* 0E secondary DRAM organization (parity/ECC-checkbits) */
- uchar reserved[17]; /* 0F reserved fields for future offerings */
- uchar ss_info[32]; /* 20 superset information (may be used in the future) */
- uchar m_info[64]; /* 40 manufacturer information (optional) */
- uchar unused[128]; /* 80 unused storage locations */
-} dimm_t;
-
-/*
- * memory type definitions
- */
-#define DIMM_MT_FPM 1 /* standard FPM (fast page mode) DRAM */
-#define DIMM_MT_EDO 2 /* EDO (extended data out) */
-#define DIMM_MT_PN 3 /* pipelined nibble */
-#define DIMM_MT_SDRAM 4 /* SDRAM (synchronous DRAM) */
-
-/*
- * row addresses definitions
- */
-#define DIMM_RA_RDNDNT (1<<7) /* redundant addressing */
-#define DIMM_RA_MASK 0x7f /* number of row addresses mask */
-
-/*
- * module interface levels definitions
- */
-#define DIMM_IFL_TTL 0 /* TTL/5V tolerant */
-#define DIMM_IFL_LVTTL 1 /* LVTTL (not 5V tolerant) */
-#define DIMM_IFL_HSTL15 2 /* HSTL 1.5 */
-#define DIMM_IFL_SSTL33 3 /* SSTL 3.3 */
-#define DIMM_IFL_SSTL25 4 /* SSTL 2.5 */
-
-/*
- * DIMM configuration type definitions
- */
-#define DIMM_CT_NONE 0 /* none */
-#define DIMM_CT_PARITY 1 /* parity */
-#define DIMM_CT_ECC 2 /* ECC */
-
-/*
- * row addresses definitions
- */
-#define DIMM_RRT_SR (1<<7) /* self refresh flag */
-#define DIMM_RRT_MASK 0x7f /* refresh rate mask */
-#define DIMM_RRT_NRML 0x00 /* normal (15.625us) */
-#define DIMM_RRT_R_3_9 0x01 /* reduced .25x (3.9us) */
-#define DIMM_RRT_R_7_8 0x02 /* reduced .5x (7.8us) */
-#define DIMM_RRT_E_31_3 0x03 /* extended 2x (31.3us) */
-#define DIMM_RRT_E_62_5 0x04 /* extended 4x (62.5us) */
-#define DIMM_RRT_E_125 0x05 /* extended 8x (125us) */
-
-#endif /* __dimm_h */
+++ /dev/null
-#ifndef __vpd_h
-#define __vpd_h
-
-/*
- * Module name: %M%
- * Description:
- * Vital Product Data (VPD) Header Module
- * SCCS identification: %I%
- * Branch: %B%
- * Sequence: %S%
- * Date newest applied delta was created (MM/DD/YY): %G%
- * Time newest applied delta was created (HH:MM:SS): %U%
- * SCCS file name %F%
- * Fully qualified SCCS file name:
- * %P%
- * Copyright:
- * (C) COPYRIGHT MOTOROLA, INC. 1996
- * ALL RIGHTS RESERVED
- * Notes:
- * History:
- * Date Who
- *
- * 10/24/96 Rob Baxter
- * Initial release.
- *
- */
-
-#define VPD_EEPROM_SIZE 256 /* EEPROM size in bytes */
-
-/*
- * packet tuple identifiers
- *
- * 0x0D - 0xBF reserved
- * 0xC0 - 0xFE user defined
- */
-#define VPD_PID_GI 0x00 /* guaranteed illegal */
-#define VPD_PID_PID 0x01 /* product identifier (ASCII) */
-#define VPD_PID_FAN 0x02 /* factory assembly-number (ASCII) */
-#define VPD_PID_SN 0x03 /* serial-number (ASCII) */
-#define VPD_PID_PCO 0x04 /* product configuration options(binary) */
-#define VPD_PID_ICS 0x05 /* internal clock speed in HZ (integer) */
-#define VPD_PID_ECS 0x06 /* external clock speed in HZ (integer) */
-#define VPD_PID_RCS 0x07 /* reference clock speed in HZ(integer) */
-#define VPD_PID_EA 0x08 /* ethernet address (binary) */
-#define VPD_PID_MT 0x09 /* microprocessor type (ASCII) */
-#define VPD_PID_CRC 0x0A /* EEPROM CRC (integer) */
-#define VPD_PID_FMC 0x0B /* FLASH memory configuration (binary) */
-#define VPD_PID_VLSI 0x0C /* VLSI revisions/versions (binary) */
-#define VPD_PID_TERM 0xFF /* termination */
-
-/*
- * VPD structure (format)
- */
-#define VPD_EYE_SIZE 8 /* eyecatcher size */
-typedef struct vpd_header
-{
- uchar eyecatcher[VPD_EYE_SIZE]; /* eyecatcher - "MOTOROLA" */
- ushort size; /* size of EEPROM */
-} vpd_header_t;
-
-#define VPD_DATA_SIZE (VPD_EEPROM_SIZE-sizeof(vpd_header_t))
-typedef struct vpd
-{
- vpd_header_t header; /* header */
- uchar packets[VPD_DATA_SIZE]; /* data */
-} vpd_t;
-
-/*
- * packet tuple structure (format)
- */
-typedef struct vpd_packet
-{
- uchar identifier; /* identifier (PIDs above) */
- uchar size; /* size of the following data area */
- uchar data[1]; /* data (size is dependent upon PID) */
-} vpd_packet_t;
-
-/*
- * MBX product configuration options bit definitions
- *
- * Notes:
- * 1. The bit numbering is reversed in perspective with the C compiler.
- */
-#define PCO_BBRAM (1<<0) /* battery-backed RAM (BBRAM) and socket */
-#define PCO_BOOTROM (1<<1) /* boot ROM and socket (i.e., socketed FLASH) */
-#define PCO_KAPWR (1<<2) /* keep alive power source (lithium battey) and control circuit */
-#define PCO_ENET_TP (1<<3) /* ethernet twisted pair (TP) connector (RJ45) */
-#define PCO_ENET_AUI (1<<4) /* ethernet attachment unit interface (AUI) header */
-#define PCO_PCMCIA (1<<5) /* PCMCIA socket */
-#define PCO_DIMM (1<<6) /* DIMM module socket */
-#define PCO_DTT (1<<7) /* digital thermometer and thermostat (DTT) device */
-#define PCO_LCD (1<<8) /* liquid crystal display (LCD) device */
-#define PCO_PCI (1<<9) /* PCI-Bus bridge device (QSpan) and ISA-Bus bridge device (Winbond) */
-#define PCO_PCIO (1<<10) /* PC I/O (COM1, COM2, FDC, LPT, Keyboard/Mouse) */
-#define PCO_EIDE (1<<11) /* enhanced IDE (EIDE) header */
-#define PCO_FDC (1<<12) /* floppy disk controller (FDC) header */
-#define PCO_LPT_8XX (1<<13) /* parallel port header via MPC8xx */
-#define PCO_LPT_PCIO (1<<14) /* parallel port header via PC I/O */
-
-/*
- * FLASH memory configuration packet data
- */
-typedef struct vpd_fmc
-{
- ushort mid; /* manufacturer's idenitfier */
- ushort did; /* manufacturer's device idenitfier */
- uchar ddw; /* device data width (e.g., 8-bits, 16-bits) */
- uchar nod; /* number of devices present */
- uchar noc; /* number of columns */
- uchar cw; /* column width in bits */
- uchar wedw; /* write/erase data width */
-} vpd_fmc_t;
-
-/* function prototypes */
-extern void vpd_init(void);
-extern int vpd_read(uint iic_device, uchar *buf, int count, int offset);
-extern vpd_packet_t *vpd_find_packet(u_char ident);
-
-#endif /* __vpd_h */
+++ /dev/null
-/*
- * Copyright (C) 2002 ETC s.r.o.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the ETC s.r.o. nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Written by Marcel Telka <marcel@telka.sk>, 2002.
- *
- * Documentation:
- * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A,
- * 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011
- * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18,
- * 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005
- *
- * This file is taken from OpenWinCE project hosted by SourceForge.net
- *
- */
-
-#ifndef FLASH_INTEL_H
-#define FLASH_INTEL_H
-
-#include <common.h>
-
-/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */
-
-#define CFI_INTEL_CMD_READ_ARRAY 0xFF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_READ_IDENTIFIER 0x90 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_READ_QUERY 0x98 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x70 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x50 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_PROGRAM1 0x40 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_PROGRAM2 0x10 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_WRITE_TO_BUFFER 0xE8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_CONFIRM 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_BLOCK_ERASE 0x20 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_SUSPEND 0xB0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_RESUME 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_LOCK_SETUP 0x60 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_LOCK_BLOCK 0x01 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_UNLOCK_BLOCK 0xD0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x2F /* 28FxxxK3, 28FxxxK18 */
-
-/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */
-
-#define CFI_INTEL_SR_READY 1 << 7 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_ERASE_SUSPEND 1 << 6 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_ERASE_ERROR 1 << 5 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_PROGRAM_ERROR 1 << 4 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_VPEN_ERROR 1 << 3 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_PROGRAM_SUSPEND 1 << 2 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_BLOCK_LOCKED 1 << 1 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_BEFP 1 << 0 /* 28FxxxK3, 28FxxxK18 */
-
-/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */
-
-#define CFI_CHIP_INTEL_28F320J3A 0x0016
-#define CFI_CHIPN_INTEL_28F320J3A "28F320J3A"
-#define CFI_CHIP_INTEL_28F640J3A 0x0017
-#define CFI_CHIPN_INTEL_28F640J3A "28F640J3A"
-#define CFI_CHIP_INTEL_28F128J3A 0x0018
-#define CFI_CHIPN_INTEL_28F128J3A "28F128J3A"
-
-/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */
-
-#define CFI_CHIP_INTEL_28F640K3 0x8801
-#define CFI_CHIPN_INTEL_28F640K3 "28F640K3"
-#define CFI_CHIP_INTEL_28F128K3 0x8802
-#define CFI_CHIPN_INTEL_28F128K3 "28F128K3"
-#define CFI_CHIP_INTEL_28F256K3 0x8803
-#define CFI_CHIPN_INTEL_28F256K3 "28F256K3"
-#define CFI_CHIP_INTEL_28F640K18 0x8805
-#define CFI_CHIPN_INTEL_28F640K18 "28F640K18"
-#define CFI_CHIP_INTEL_28F128K18 0x8806
-#define CFI_CHIPN_INTEL_28F128K18 "28F128K18"
-#define CFI_CHIP_INTEL_28F256K18 0x8807
-#define CFI_CHIPN_INTEL_28F256K18 "28F256K18"
-
-#endif /* FLASH_INTEL_H */
+++ /dev/null
-/***********************************************************************
- *
- * Copyright (C) 2004 by FS Forth-Systeme GmbH.
- * All rights reserved.
- *
- * $Id: led.c,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
- * @Author: Markus Pietrek
- * @Descr: Defines helper functions for toggeling LEDs
- * @Usage:
- * @References: [1]
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- ***********************************************************************/
-
-#ifdef CONFIG_STATUS_LED
-
-#include <ns9750_bbus.h>
-
-static inline void __led_init( led_id_t mask, int state )
-{
- XXXX;
-}
-
-static inline void __led_toggle( led_id_t mask )
-{
-}
-
-static inline void __led_set( led_id_t mask, int state )
-{
-}
-
-#endif /* CONFIG_STATUS_LED */
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * Copyright (C) 2004 by FS Forth-Systeme GmbH.
- * All rights reserved.
- * Markus Pietrek <mpietrek@fsforth.de>
- * derived from omap1610innovator.c
- * @References: [1] NS9750 Hardware Reference/December 2003
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#if defined(CONFIG_NS9750DEV)
-# include <./configs/ns9750dev.h>
-# include <./ns9750_bbus.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void flash__init( void );
-void ether__init( void );
-
-static inline void delay( unsigned long loops )
-{
- __asm__ volatile ("1:\n"
- "subs %0, %1, #1\n"
- "bne 1b":"=r" (loops):"0" (loops));
-}
-
-
-/***********************************************************************
- * @Function: board_init
- * @Return: 0
- * @Descr: Enables BBUS modules and other devices
- ***********************************************************************/
-
-int board_init( void )
-{
- /* Active BBUS modules */
- *get_bbus_reg_addr( NS9750_BBUS_MASTER_RESET ) = 0;
-
-#warning Please register your machine at http://www.arm.linux.org.uk/developer/machines/?action=new
- /* arch number of OMAP 1510-Board */
- /* to be changed for OMAP 1610 Board */
- gd->bd->bi_arch_number = 234;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0x10000100;
-
-
-/* this speeds up your boot a quite a bit. However to make it
- * work, you need make sure your kernel startup flush bug is fixed.
- * ... rkw ...
- */
- icache_enable();
-
- flash__init();
- ether__init();
- return 0;
-}
-
-
-int misc_init_r (void)
-{
- /* currently empty */
- return (0);
-}
-
-/******************************
- Routine:
- Description:
-******************************/
-void flash__init (void)
-{
-}
-/*************************************************************
- Routine:ether__init
- Description: take the Ethernet controller out of reset and wait
- for the EEPROM load to complete.
-*************************************************************/
-void ether__init (void)
-{
-}
-
-/******************************
- Routine:
- Description:
-******************************/
-int dram_init (void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-#if CONFIG_NR_DRAM_BANKS > 1
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-#endif
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2002 ETC s.r.o.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the ETC s.r.o. nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Written by Marcel Telka <marcel@telka.sk>, 2002.
- *
- * Documentation:
- * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A,
- * 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011
- * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18,
- * 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005
- *
- * This file is taken from OpenWinCE project hosted by SourceForge.net
- *
- */
-
-#ifndef FLASH_INTEL_H
-#define FLASH_INTEL_H
-
-#include <common.h>
-
-/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */
-
-#define CFI_INTEL_CMD_READ_ARRAY 0xFF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_READ_IDENTIFIER 0x90 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_READ_QUERY 0x98 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x70 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x50 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_PROGRAM1 0x40 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_PROGRAM2 0x10 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_WRITE_TO_BUFFER 0xE8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_CONFIRM 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_BLOCK_ERASE 0x20 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_SUSPEND 0xB0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_RESUME 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_LOCK_SETUP 0x60 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_LOCK_BLOCK 0x01 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_UNLOCK_BLOCK 0xD0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x2F /* 28FxxxK3, 28FxxxK18 */
-
-/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */
-
-#define CFI_INTEL_SR_READY 1 << 7 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_ERASE_SUSPEND 1 << 6 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_ERASE_ERROR 1 << 5 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_PROGRAM_ERROR 1 << 4 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_VPEN_ERROR 1 << 3 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_PROGRAM_SUSPEND 1 << 2 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_BLOCK_LOCKED 1 << 1 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_BEFP 1 << 0 /* 28FxxxK3, 28FxxxK18 */
-
-/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */
-
-#define CFI_CHIP_INTEL_28F320J3A 0x0016
-#define CFI_CHIPN_INTEL_28F320J3A "28F320J3A"
-#define CFI_CHIP_INTEL_28F640J3A 0x0017
-#define CFI_CHIPN_INTEL_28F640J3A "28F640J3A"
-#define CFI_CHIP_INTEL_28F128J3A 0x0018
-#define CFI_CHIPN_INTEL_28F128J3A "28F128J3A"
-
-/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */
-
-#define CFI_CHIP_INTEL_28F640K3 0x8801
-#define CFI_CHIPN_INTEL_28F640K3 "28F640K3"
-#define CFI_CHIP_INTEL_28F128K3 0x8802
-#define CFI_CHIPN_INTEL_28F128K3 "28F128K3"
-#define CFI_CHIP_INTEL_28F256K3 0x8803
-#define CFI_CHIPN_INTEL_28F256K3 "28F256K3"
-#define CFI_CHIP_INTEL_28F640K18 0x8805
-#define CFI_CHIPN_INTEL_28F640K18 "28F640K18"
-#define CFI_CHIP_INTEL_28F128K18 0x8806
-#define CFI_CHIPN_INTEL_28F128K18 "28F128K18"
-#define CFI_CHIP_INTEL_28F256K18 0x8807
-#define CFI_CHIPN_INTEL_28F256K18 "28F256K18"
-
-#endif /* FLASH_INTEL_H */
+++ /dev/null
-/*
- * Copyright (C) 2002 ETC s.r.o.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the ETC s.r.o. nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Written by Marcel Telka <marcel@telka.sk>, 2002.
- *
- * Documentation:
- * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A,
- * 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011
- * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18,
- * 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005
- *
- * This file is taken from OpenWinCE project hosted by SourceForge.net
- *
- */
-
-#ifndef FLASH_INTEL_H
-#define FLASH_INTEL_H
-
-#include <common.h>
-
-/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */
-
-#define CFI_INTEL_CMD_READ_ARRAY 0xFF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_READ_IDENTIFIER 0x90 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_READ_QUERY 0x98 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x70 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x50 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_PROGRAM1 0x40 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_PROGRAM2 0x10 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_WRITE_TO_BUFFER 0xE8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_CONFIRM 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_BLOCK_ERASE 0x20 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_SUSPEND 0xB0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_RESUME 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_LOCK_SETUP 0x60 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_LOCK_BLOCK 0x01 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_UNLOCK_BLOCK 0xD0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x2F /* 28FxxxK3, 28FxxxK18 */
-
-/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */
-
-#define CFI_INTEL_SR_READY 1 << 7 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_ERASE_SUSPEND 1 << 6 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_ERASE_ERROR 1 << 5 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_PROGRAM_ERROR 1 << 4 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_VPEN_ERROR 1 << 3 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_PROGRAM_SUSPEND 1 << 2 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_BLOCK_LOCKED 1 << 1 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_BEFP 1 << 0 /* 28FxxxK3, 28FxxxK18 */
-
-/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */
-
-#define CFI_CHIP_INTEL_28F320J3A 0x0016
-#define CFI_CHIPN_INTEL_28F320J3A "28F320J3A"
-#define CFI_CHIP_INTEL_28F640J3A 0x0017
-#define CFI_CHIPN_INTEL_28F640J3A "28F640J3A"
-#define CFI_CHIP_INTEL_28F128J3A 0x0018
-#define CFI_CHIPN_INTEL_28F128J3A "28F128J3A"
-
-/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */
-
-#define CFI_CHIP_INTEL_28F640K3 0x8801
-#define CFI_CHIPN_INTEL_28F640K3 "28F640K3"
-#define CFI_CHIP_INTEL_28F128K3 0x8802
-#define CFI_CHIPN_INTEL_28F128K3 "28F128K3"
-#define CFI_CHIP_INTEL_28F256K3 0x8803
-#define CFI_CHIPN_INTEL_28F256K3 "28F256K3"
-#define CFI_CHIP_INTEL_28F640K18 0x8805
-#define CFI_CHIPN_INTEL_28F640K18 "28F640K18"
-#define CFI_CHIP_INTEL_28F128K18 0x8806
-#define CFI_CHIPN_INTEL_28F128K18 "28F128K18"
-#define CFI_CHIP_INTEL_28F256K18 0x8807
-#define CFI_CHIPN_INTEL_28F256K18 "28F256K18"
-
-#endif /* FLASH_INTEL_H */
+++ /dev/null
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
- *
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xbasic_types.c
-*
-* This file contains basic functions for Xilinx software IP.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a rpm 11/07/03 Added XNullHandler function as a stub interrupt handler
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xbasic_types.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-/**
- * This variable allows testing to be done easier with asserts. An assert
- * sets this variable such that a driver can evaluate this variable
- * to determine if an assert occurred.
- */
-unsigned int XAssertStatus;
-
-/**
- * This variable allows the assert functionality to be changed for testing
- * such that it does not wait infinitely. Use the debugger to disable the
- * waiting during testing of asserts.
- */
-u32 XWaitInAssert = TRUE;
-
-/* The callback function to be invoked when an assert is taken */
-static XAssertCallback XAssertCallbackRoutine = (XAssertCallback) NULL;
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-*
-* Implements assert. Currently, it calls a user-defined callback function
-* if one has been set. Then, it potentially enters an infinite loop depending
-* on the value of the XWaitInAssert variable.
-*
-* @param File is the name of the filename of the source
-* @param Line is the linenumber within File
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-void
-XAssert(char *File, int Line)
-{
- /* if the callback has been set then invoke it */
- if (XAssertCallbackRoutine != NULL) {
- (*XAssertCallbackRoutine) (File, Line);
- }
-
- /* if specified, wait indefinitely such that the assert will show up
- * in testing
- */
- while (XWaitInAssert) {
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* Sets up a callback function to be invoked when an assert occurs. If there
-* was already a callback installed, then it is replaced.
-*
-* @param Routine is the callback to be invoked when an assert is taken
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* This function has no effect if NDEBUG is set
-*
-******************************************************************************/
-void
-XAssertSetCallback(XAssertCallback Routine)
-{
- XAssertCallbackRoutine = Routine;
-}
-
-/*****************************************************************************/
-/**
-*
-* Null handler function. This follows the XInterruptHandler signature for
-* interrupt handlers. It can be used to assign a null handler (a stub) to an
-* interrupt controller vector table.
-*
-* @param NullParameter is an arbitrary void pointer and not used.
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-void
-XNullHandler(void *NullParameter)
-{
-}
+++ /dev/null
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xbasic_types.h
-*
-* This file contains basic types for Xilinx software IP. These types do not
-* follow the standard naming convention with respect to using the component
-* name in front of each name because they are considered to be primitives.
-*
-* @note
-*
-* This file contains items which are architecture dependent.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a rmm 12/14/01 First release
-* rmm 05/09/03 Added "xassert always" macros to rid ourselves of diab
-* compiler warnings
-* 1.00a rpm 11/07/03 Added XNullHandler function as a stub interrupt handler
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
-#define XBASIC_TYPES_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-/************************** Constant Definitions *****************************/
-
-#ifndef TRUE
-#define TRUE 1
-#endif
-#ifndef FALSE
-#define FALSE 0
-#endif
-
-#ifndef NULL
-#define NULL 0
-#endif
-/** Null */
-
-#define XCOMPONENT_IS_READY 0x11111111 /* component has been initialized */
-#define XCOMPONENT_IS_STARTED 0x22222222 /* component has been started */
-
-/* the following constants and declarations are for unit test purposes and are
- * designed to be used in test applications.
- */
-#define XTEST_PASSED 0
-#define XTEST_FAILED 1
-
-#define XASSERT_NONE 0
-#define XASSERT_OCCURRED 1
-
-extern unsigned int XAssertStatus;
-extern void XAssert(char *, int);
-
-/**************************** Type Definitions *******************************/
-
-/** @name Primitive types
- * These primitive types are created for transportability.
- * They are dependent upon the target architecture.
- * @{
- */
-#include <linux/types.h>
-
-typedef struct {
- u32 Upper;
- u32 Lower;
-} Xuint64;
-
-/*@}*/
-
-/**
- * This data type defines an interrupt handler for a device.
- * The argument points to the instance of the component
- */
-typedef void (*XInterruptHandler) (void *InstancePtr);
-
-/**
- * This data type defines a callback to be invoked when an
- * assert occurs. The callback is invoked only when asserts are enabled
- */
-typedef void (*XAssertCallback) (char *FilenamePtr, int LineNumber);
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
-* Return the most significant half of the 64 bit data type.
-*
-* @param x is the 64 bit word.
-*
-* @return
-*
-* The upper 32 bits of the 64 bit word.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#define XUINT64_MSW(x) ((x).Upper)
-
-/*****************************************************************************/
-/**
-* Return the least significant half of the 64 bit data type.
-*
-* @param x is the 64 bit word.
-*
-* @return
-*
-* The lower 32 bits of the 64 bit word.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#define XUINT64_LSW(x) ((x).Lower)
-
-#ifndef NDEBUG
-
-/*****************************************************************************/
-/**
-* This assert macro is to be used for functions that do not return anything
-* (void). This in conjunction with the XWaitInAssert boolean can be used to
-* accomodate tests so that asserts which fail allow execution to continue.
-*
-* @param expression is the expression to evaluate. If it evaluates to false,
-* the assert occurs.
-*
-* @return
-*
-* Returns void unless the XWaitInAssert variable is true, in which case
-* no return is made and an infinite loop is entered.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#define XASSERT_VOID(expression) \
-{ \
- if (expression) { \
- XAssertStatus = XASSERT_NONE; \
- } else { \
- XAssert(__FILE__, __LINE__); \
- XAssertStatus = XASSERT_OCCURRED; \
- return; \
- } \
-}
-
-/*****************************************************************************/
-/**
-* This assert macro is to be used for functions that do return a value. This in
-* conjunction with the XWaitInAssert boolean can be used to accomodate tests so
-* that asserts which fail allow execution to continue.
-*
-* @param expression is the expression to evaluate. If it evaluates to false,
-* the assert occurs.
-*
-* @return
-*
-* Returns 0 unless the XWaitInAssert variable is true, in which case
-* no return is made and an infinite loop is entered.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#define XASSERT_NONVOID(expression) \
-{ \
- if (expression) { \
- XAssertStatus = XASSERT_NONE; \
- } else { \
- XAssert(__FILE__, __LINE__); \
- XAssertStatus = XASSERT_OCCURRED; \
- return 0; \
- } \
-}
-
-/*****************************************************************************/
-/**
-* Always assert. This assert macro is to be used for functions that do not
-* return anything (void). Use for instances where an assert should always
-* occur.
-*
-* @return
-*
-* Returns void unless the XWaitInAssert variable is true, in which case
-* no return is made and an infinite loop is entered.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#define XASSERT_VOID_ALWAYS() \
-{ \
- XAssert(__FILE__, __LINE__); \
- XAssertStatus = XASSERT_OCCURRED; \
- return; \
-}
-
-/*****************************************************************************/
-/**
-* Always assert. This assert macro is to be used for functions that do return
-* a value. Use for instances where an assert should always occur.
-*
-* @return
-*
-* Returns void unless the XWaitInAssert variable is true, in which case
-* no return is made and an infinite loop is entered.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#define XASSERT_NONVOID_ALWAYS() \
-{ \
- XAssert(__FILE__, __LINE__); \
- XAssertStatus = XASSERT_OCCURRED; \
- return 0; \
-}
-
-#else
-
-#define XASSERT_VOID(expression)
-#define XASSERT_VOID_ALWAYS()
-#define XASSERT_NONVOID(expression)
-#define XASSERT_NONVOID_ALWAYS()
-#endif
-
-/************************** Function Prototypes ******************************/
-
-void XAssertSetCallback(XAssertCallback Routine);
-void XNullHandler(void *NullParameter);
-
-#endif /* end of protection macro */
+++ /dev/null
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-* FILENAME:
-*
-* xbuf_descriptor.h
-*
-* DESCRIPTION:
-*
-* This file contains the interface for the XBufDescriptor component.
-* The XBufDescriptor component is a passive component that only maps over
-* a buffer descriptor data structure shared by the scatter gather DMA hardware
-* and software. The component's primary purpose is to provide encapsulation of
-* the buffer descriptor processing. See the source file xbuf_descriptor.c for
-* details.
-*
-* NOTES:
-*
-* Most of the functions of this component are implemented as macros in order
-* to optimize the processing. The names are not all uppercase such that they
-* can be switched between macros and functions easily.
-*
-******************************************************************************/
-
-#ifndef XBUF_DESCRIPTOR_H /* prevent circular inclusions */
-#define XBUF_DESCRIPTOR_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xbasic_types.h"
-#include "xdma_channel_i.h"
-
-/************************** Constant Definitions *****************************/
-
-/* The following constants allow access to all fields of a buffer descriptor
- * and are necessary at this level of visibility to allow macros to access
- * and modify the fields of a buffer descriptor. It is not expected that the
- * user of a buffer descriptor would need to use these constants.
- */
-
-#define XBD_DEVICE_STATUS_OFFSET 0
-#define XBD_CONTROL_OFFSET 1
-#define XBD_SOURCE_OFFSET 2
-#define XBD_DESTINATION_OFFSET 3
-#define XBD_LENGTH_OFFSET 4
-#define XBD_STATUS_OFFSET 5
-#define XBD_NEXT_PTR_OFFSET 6
-#define XBD_ID_OFFSET 7
-#define XBD_FLAGS_OFFSET 8
-#define XBD_RQSTED_LENGTH_OFFSET 9
-
-#define XBD_SIZE_IN_WORDS 10
-
-/*
- * The following constants define the bits of the flags field of a buffer
- * descriptor
- */
-
-#define XBD_FLAGS_LOCKED_MASK 1UL
-
-/**************************** Type Definitions *******************************/
-
-typedef u32 XBufDescriptor[XBD_SIZE_IN_WORDS];
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/* each of the following macros are named the same as functions rather than all
- * upper case in order to allow either the macros or the functions to be
- * used, see the source file xbuf_descriptor.c for documentation
- */
-
-#define XBufDescriptor_Initialize(InstancePtr) \
-{ \
- (*((u32 *)InstancePtr + XBD_CONTROL_OFFSET) = 0); \
- (*((u32 *)InstancePtr + XBD_SOURCE_OFFSET) = 0); \
- (*((u32 *)InstancePtr + XBD_DESTINATION_OFFSET) = 0); \
- (*((u32 *)InstancePtr + XBD_LENGTH_OFFSET) = 0); \
- (*((u32 *)InstancePtr + XBD_STATUS_OFFSET) = 0); \
- (*((u32 *)InstancePtr + XBD_DEVICE_STATUS_OFFSET) = 0); \
- (*((u32 *)InstancePtr + XBD_NEXT_PTR_OFFSET) = 0); \
- (*((u32 *)InstancePtr + XBD_ID_OFFSET) = 0); \
- (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) = 0); \
- (*((u32 *)InstancePtr + XBD_RQSTED_LENGTH_OFFSET) = 0); \
-}
-
-#define XBufDescriptor_GetControl(InstancePtr) \
- (u32)(*((u32 *)InstancePtr + XBD_CONTROL_OFFSET))
-
-#define XBufDescriptor_SetControl(InstancePtr, Control) \
- (*((u32 *)InstancePtr + XBD_CONTROL_OFFSET) = (u32)Control)
-
-#define XBufDescriptor_IsLastControl(InstancePtr) \
- (u32)(*((u32 *)InstancePtr + XBD_CONTROL_OFFSET) & \
- XDC_CONTROL_LAST_BD_MASK)
-
-#define XBufDescriptor_SetLast(InstancePtr) \
- (*((u32 *)InstancePtr + XBD_CONTROL_OFFSET) |= XDC_CONTROL_LAST_BD_MASK)
-
-#define XBufDescriptor_GetSrcAddress(InstancePtr) \
- ((u32 *)(*((u32 *)InstancePtr + XBD_SOURCE_OFFSET)))
-
-#define XBufDescriptor_SetSrcAddress(InstancePtr, Source) \
- (*((u32 *)InstancePtr + XBD_SOURCE_OFFSET) = (u32)Source)
-
-#define XBufDescriptor_GetDestAddress(InstancePtr) \
- ((u32 *)(*((u32 *)InstancePtr + XBD_DESTINATION_OFFSET)))
-
-#define XBufDescriptor_SetDestAddress(InstancePtr, Destination) \
- (*((u32 *)InstancePtr + XBD_DESTINATION_OFFSET) = (u32)Destination)
-
-#define XBufDescriptor_GetLength(InstancePtr) \
- (u32)(*((u32 *)InstancePtr + XBD_RQSTED_LENGTH_OFFSET) - \
- *((u32 *)InstancePtr + XBD_LENGTH_OFFSET))
-
-#define XBufDescriptor_SetLength(InstancePtr, Length) \
-{ \
- (*((u32 *)InstancePtr + XBD_LENGTH_OFFSET) = (u32)(Length)); \
- (*((u32 *)InstancePtr + XBD_RQSTED_LENGTH_OFFSET) = (u32)(Length));\
-}
-
-#define XBufDescriptor_GetStatus(InstancePtr) \
- (u32)(*((u32 *)InstancePtr + XBD_STATUS_OFFSET))
-
-#define XBufDescriptor_SetStatus(InstancePtr, Status) \
- (*((u32 *)InstancePtr + XBD_STATUS_OFFSET) = (u32)Status)
-
-#define XBufDescriptor_IsLastStatus(InstancePtr) \
- (u32)(*((u32 *)InstancePtr + XBD_STATUS_OFFSET) & \
- XDC_STATUS_LAST_BD_MASK)
-
-#define XBufDescriptor_GetDeviceStatus(InstancePtr) \
- ((u32)(*((u32 *)InstancePtr + XBD_DEVICE_STATUS_OFFSET)))
-
-#define XBufDescriptor_SetDeviceStatus(InstancePtr, Status) \
- (*((u32 *)InstancePtr + XBD_DEVICE_STATUS_OFFSET) = (u32)Status)
-
-#define XBufDescriptor_GetNextPtr(InstancePtr) \
- (XBufDescriptor *)(*((u32 *)InstancePtr + XBD_NEXT_PTR_OFFSET))
-
-#define XBufDescriptor_SetNextPtr(InstancePtr, NextPtr) \
- (*((u32 *)InstancePtr + XBD_NEXT_PTR_OFFSET) = (u32)NextPtr)
-
-#define XBufDescriptor_GetId(InstancePtr) \
- (u32)(*((u32 *)InstancePtr + XBD_ID_OFFSET))
-
-#define XBufDescriptor_SetId(InstancePtr, Id) \
- (*((u32 *)InstancePtr + XBD_ID_OFFSET) = (u32)Id)
-
-#define XBufDescriptor_GetFlags(InstancePtr) \
- (u32)(*((u32 *)InstancePtr + XBD_FLAGS_OFFSET))
-
-#define XBufDescriptor_SetFlags(InstancePtr, Flags) \
- (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) = (u32)Flags)
-
-#define XBufDescriptor_Lock(InstancePtr) \
- (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) |= XBD_FLAGS_LOCKED_MASK)
-
-#define XBufDescriptor_Unlock(InstancePtr) \
- (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) &= ~XBD_FLAGS_LOCKED_MASK)
-
-#define XBufDescriptor_IsLocked(InstancePtr) \
- (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) & XBD_FLAGS_LOCKED_MASK)
-
-/************************** Function Prototypes ******************************/
-
-/* The following prototypes are provided to allow each of the functions to
- * be implemented as a function rather than a macro, and to provide the
- * syntax to allow users to understand how to call the macros, they are
- * commented out to prevent linker errors
- *
-
-u32 XBufDescriptor_Initialize(XBufDescriptor* InstancePtr);
-
-u32 XBufDescriptor_GetControl(XBufDescriptor* InstancePtr);
-void XBufDescriptor_SetControl(XBufDescriptor* InstancePtr, u32 Control);
-
-u32 XBufDescriptor_IsLastControl(XBufDescriptor* InstancePtr);
-void XBufDescriptor_SetLast(XBufDescriptor* InstancePtr);
-
-u32 XBufDescriptor_GetLength(XBufDescriptor* InstancePtr);
-void XBufDescriptor_SetLength(XBufDescriptor* InstancePtr, u32 Length);
-
-u32 XBufDescriptor_GetStatus(XBufDescriptor* InstancePtr);
-void XBufDescriptor_SetStatus(XBufDescriptor* InstancePtr, u32 Status);
-u32 XBufDescriptor_IsLastStatus(XBufDescriptor* InstancePtr);
-
-u32 XBufDescriptor_GetDeviceStatus(XBufDescriptor* InstancePtr);
-void XBufDescriptor_SetDeviceStatus(XBufDescriptor* InstancePtr,
- u32 Status);
-
-u32 XBufDescriptor_GetSrcAddress(XBufDescriptor* InstancePtr);
-void XBufDescriptor_SetSrcAddress(XBufDescriptor* InstancePtr,
- u32 SourceAddress);
-
-u32 XBufDescriptor_GetDestAddress(XBufDescriptor* InstancePtr);
-void XBufDescriptor_SetDestAddress(XBufDescriptor* InstancePtr,
- u32 DestinationAddress);
-
-XBufDescriptor* XBufDescriptor_GetNextPtr(XBufDescriptor* InstancePtr);
-void XBufDescriptor_SetNextPtr(XBufDescriptor* InstancePtr,
- XBufDescriptor* NextPtr);
-
-u32 XBufDescriptor_GetId(XBufDescriptor* InstancePtr);
-void XBufDescriptor_SetId(XBufDescriptor* InstancePtr, u32 Id);
-
-u32 XBufDescriptor_GetFlags(XBufDescriptor* InstancePtr);
-void XBufDescriptor_SetFlags(XBufDescriptor* InstancePtr, u32 Flags);
-
-void XBufDescriptor_Lock(XBufDescriptor* InstancePtr);
-void XBufDescriptor_Unlock(XBufDescriptor* InstancePtr);
-u32 XBufDescriptor_IsLocked(XBufDescriptor* InstancePtr);
-
-void XBufDescriptor_Copy(XBufDescriptor* InstancePtr,
- XBufDescriptor* DestinationPtr);
-
-*/
-
-#endif /* end of protection macro */
+++ /dev/null
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-* FILENAME:
-*
-* xdma_channel.c
-*
-* DESCRIPTION:
-*
-* This file contains the DMA channel component. This component supports
-* a distributed DMA design in which each device can have it's own dedicated
-* DMA channel, as opposed to a centralized DMA design. This component
-* performs processing for DMA on all devices.
-*
-* See xdma_channel.h for more information about this component.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xdma_channel.h"
-#include "xbasic_types.h"
-#include "xio.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_Initialize
-*
-* DESCRIPTION:
-*
-* This function initializes a DMA channel. This function must be called
-* prior to using a DMA channel. Initialization of a channel includes setting
-* up the registers base address, and resetting the channel such that it's in a
-* known state. Interrupts for the channel are disabled when the channel is
-* reset.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* BaseAddress contains the base address of the registers for the DMA channel.
-*
-* RETURN VALUE:
-*
-* XST_SUCCESS indicating initialization was successful.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-XStatus
-XDmaChannel_Initialize(XDmaChannel * InstancePtr, u32 BaseAddress)
-{
- /* assert to verify input arguments, don't assert base address */
-
- XASSERT_NONVOID(InstancePtr != NULL);
-
- /* setup the base address of the registers for the DMA channel such
- * that register accesses can be done
- */
- InstancePtr->RegBaseAddress = BaseAddress;
-
- /* initialize the scatter gather list such that it indicates it has not
- * been created yet and the DMA channel is ready to use (initialized)
- */
- InstancePtr->GetPtr = NULL;
- InstancePtr->PutPtr = NULL;
- InstancePtr->CommitPtr = NULL;
- InstancePtr->LastPtr = NULL;
-
- InstancePtr->TotalDescriptorCount = 0;
- InstancePtr->ActiveDescriptorCount = 0;
- InstancePtr->IsReady = XCOMPONENT_IS_READY;
-
- /* initialize the version of the component
- */
- XVersion_FromString(&InstancePtr->Version, (s8 *)"1.00a");
-
- /* reset the DMA channel such that it's in a known state and ready
- * and indicate the initialization occured with no errors, note that
- * the is ready variable must be set before this call or reset will assert
- */
- XDmaChannel_Reset(InstancePtr);
-
- return XST_SUCCESS;
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_IsReady
-*
-* DESCRIPTION:
-*
-* This function determines if a DMA channel component has been successfully
-* initialized such that it's ready to use.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* RETURN VALUE:
-*
-* TRUE if the DMA channel component is ready, FALSE otherwise.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-u32
-XDmaChannel_IsReady(XDmaChannel * InstancePtr)
-{
- /* assert to verify input arguments used by the base component */
-
- XASSERT_NONVOID(InstancePtr != NULL);
-
- return InstancePtr->IsReady == XCOMPONENT_IS_READY;
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_GetVersion
-*
-* DESCRIPTION:
-*
-* This function gets the software version for the specified DMA channel
-* component.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* RETURN VALUE:
-*
-* A pointer to the software version of the specified DMA channel.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-XVersion *
-XDmaChannel_GetVersion(XDmaChannel * InstancePtr)
-{
- /* assert to verify input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* return a pointer to the version of the DMA channel */
-
- return &InstancePtr->Version;
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_SelfTest
-*
-* DESCRIPTION:
-*
-* This function performs a self test on the specified DMA channel. This self
-* test is destructive as the DMA channel is reset and a register default is
-* verified.
-*
-* ARGUMENTS:
-*
-* InstancePtr is a pointer to the DMA channel to be operated on.
-*
-* RETURN VALUE:
-*
-* XST_SUCCESS is returned if the self test is successful, or one of the
-* following errors.
-*
-* XST_DMA_RESET_REGISTER_ERROR Indicates the control register value
-* after a reset was not correct
-*
-* NOTES:
-*
-* This test does not performs a DMA transfer to test the channel because the
-* DMA hardware will not currently allow a non-local memory transfer to non-local
-* memory (memory copy), but only allows a non-local memory to or from the device
-* memory (typically a FIFO).
-*
-******************************************************************************/
-
-#define XDC_CONTROL_REG_RESET_MASK 0x98000000UL /* control reg reset value */
-
-XStatus
-XDmaChannel_SelfTest(XDmaChannel * InstancePtr)
-{
- u32 ControlReg;
-
- /* assert to verify input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* reset the DMA channel such that it's in a known state before the test
- * it resets to no interrupts enabled, the desired state for the test
- */
- XDmaChannel_Reset(InstancePtr);
-
- /* this should be the first test to help prevent a lock up with the polling
- * loop that occurs later in the test, check the reset value of the DMA
- * control register to make sure it's correct, return with an error if not
- */
- ControlReg = XDmaChannel_GetControl(InstancePtr);
- if (ControlReg != XDC_CONTROL_REG_RESET_MASK) {
- return XST_DMA_RESET_REGISTER_ERROR;
- }
-
- return XST_SUCCESS;
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_Reset
-*
-* DESCRIPTION:
-*
-* This function resets the DMA channel. This is a destructive operation such
-* that it should not be done while a channel is being used. If the DMA channel
-* is transferring data into other blocks, such as a FIFO, it may be necessary
-* to reset other blocks. This function does not modify the contents of a
-* scatter gather list for a DMA channel such that the user is responsible for
-* getting buffer descriptors from the list if necessary.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-void
-XDmaChannel_Reset(XDmaChannel * InstancePtr)
-{
- /* assert to verify input arguments */
-
- XASSERT_VOID(InstancePtr != NULL);
- XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* reset the DMA channel such that it's in a known state, the reset
- * register is self clearing such that it only has to be set
- */
- XIo_Out32(InstancePtr->RegBaseAddress + XDC_RST_REG_OFFSET,
- XDC_RESET_MASK);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_GetControl
-*
-* DESCRIPTION:
-*
-* This function gets the control register contents of the DMA channel.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* RETURN VALUE:
-*
-* The control register contents of the DMA channel. One or more of the
-* following values may be contained the register. Each of the values are
-* unique bit masks.
-*
-* XDC_DMACR_SOURCE_INCR_MASK Increment the source address
-* XDC_DMACR_DEST_INCR_MASK Increment the destination address
-* XDC_DMACR_SOURCE_LOCAL_MASK Local source address
-* XDC_DMACR_DEST_LOCAL_MASK Local destination address
-* XDC_DMACR_SG_ENABLE_MASK Scatter gather enable
-* XDC_DMACR_GEN_BD_INTR_MASK Individual buffer descriptor interrupt
-* XDC_DMACR_LAST_BD_MASK Last buffer descriptor in a packet
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-u32
-XDmaChannel_GetControl(XDmaChannel * InstancePtr)
-{
- /* assert to verify input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* return the contents of the DMA control register */
-
- return XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_SetControl
-*
-* DESCRIPTION:
-*
-* This function sets the control register of the specified DMA channel.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* Control contains the value to be written to the control register of the DMA
-* channel. One or more of the following values may be contained the register.
-* Each of the values are unique bit masks such that they may be ORed together
-* to enable multiple bits or inverted and ANDed to disable multiple bits.
-*
-* XDC_DMACR_SOURCE_INCR_MASK Increment the source address
-* XDC_DMACR_DEST_INCR_MASK Increment the destination address
-* XDC_DMACR_SOURCE_LOCAL_MASK Local source address
-* XDC_DMACR_DEST_LOCAL_MASK Local destination address
-* XDC_DMACR_SG_ENABLE_MASK Scatter gather enable
-* XDC_DMACR_GEN_BD_INTR_MASK Individual buffer descriptor interrupt
-* XDC_DMACR_LAST_BD_MASK Last buffer descriptor in a packet
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-void
-XDmaChannel_SetControl(XDmaChannel * InstancePtr, u32 Control)
-{
- /* assert to verify input arguments except the control which can't be
- * asserted since all values are valid
- */
- XASSERT_VOID(InstancePtr != NULL);
- XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* set the DMA control register to the specified value */
-
- XIo_Out32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET, Control);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_GetStatus
-*
-* DESCRIPTION:
-*
-* This function gets the status register contents of the DMA channel.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* RETURN VALUE:
-*
-* The status register contents of the DMA channel. One or more of the
-* following values may be contained the register. Each of the values are
-* unique bit masks.
-*
-* XDC_DMASR_BUSY_MASK The DMA channel is busy
-* XDC_DMASR_BUS_ERROR_MASK A bus error occurred
-* XDC_DMASR_BUS_TIMEOUT_MASK A bus timeout occurred
-* XDC_DMASR_LAST_BD_MASK The last buffer descriptor of a packet
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-u32
-XDmaChannel_GetStatus(XDmaChannel * InstancePtr)
-{
- /* assert to verify input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* return the contents of the DMA status register */
-
- return XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAS_REG_OFFSET);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_SetIntrStatus
-*
-* DESCRIPTION:
-*
-* This function sets the interrupt status register of the specified DMA channel.
-* Setting any bit of the interrupt status register will clear the bit to
-* indicate the interrupt processing has been completed. The definitions of each
-* bit in the register match the definition of the bits in the interrupt enable
-* register.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* Status contains the value to be written to the status register of the DMA
-* channel. One or more of the following values may be contained the register.
-* Each of the values are unique bit masks such that they may be ORed together
-* to enable multiple bits or inverted and ANDed to disable multiple bits.
-*
-* XDC_IXR_DMA_DONE_MASK The dma operation is done
-* XDC_IXR_DMA_ERROR_MASK The dma operation had an error
-* XDC_IXR_PKT_DONE_MASK A packet is complete
-* XDC_IXR_PKT_THRESHOLD_MASK The packet count threshold reached
-* XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
-* XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
-* XDC_IXR_BD_MASK A buffer descriptor is done
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-void
-XDmaChannel_SetIntrStatus(XDmaChannel * InstancePtr, u32 Status)
-{
- /* assert to verify input arguments except the status which can't be
- * asserted since all values are valid
- */
- XASSERT_VOID(InstancePtr != NULL);
- XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* set the interrupt status register with the specified value such that
- * all bits which are set in the register are cleared effectively clearing
- * any active interrupts
- */
- XIo_Out32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET, Status);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_GetIntrStatus
-*
-* DESCRIPTION:
-*
-* This function gets the interrupt status register of the specified DMA channel.
-* The interrupt status register indicates which interrupts are active
-* for the DMA channel. If an interrupt is active, the status register must be
-* set (written) with the bit set for each interrupt which has been processed
-* in order to clear the interrupts. The definitions of each bit in the register
-* match the definition of the bits in the interrupt enable register.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* RETURN VALUE:
-*
-* The interrupt status register contents of the specified DMA channel.
-* One or more of the following values may be contained the register.
-* Each of the values are unique bit masks.
-*
-* XDC_IXR_DMA_DONE_MASK The dma operation is done
-* XDC_IXR_DMA_ERROR_MASK The dma operation had an error
-* XDC_IXR_PKT_DONE_MASK A packet is complete
-* XDC_IXR_PKT_THRESHOLD_MASK The packet count threshold reached
-* XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
-* XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
-* XDC_IXR_SG_END_MASK Current descriptor was the end of the list
-* XDC_IXR_BD_MASK A buffer descriptor is done
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-u32
-XDmaChannel_GetIntrStatus(XDmaChannel * InstancePtr)
-{
- /* assert to verify input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* return the contents of the interrupt status register */
-
- return XIo_In32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_SetIntrEnable
-*
-* DESCRIPTION:
-*
-* This function sets the interrupt enable register of the specified DMA
-* channel. The interrupt enable register contains bits which enable
-* individual interrupts for the DMA channel. The definitions of each bit
-* in the register match the definition of the bits in the interrupt status
-* register.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* Enable contains the interrupt enable register contents to be written
-* in the DMA channel. One or more of the following values may be contained
-* the register. Each of the values are unique bit masks such that they may be
-* ORed together to enable multiple bits or inverted and ANDed to disable
-* multiple bits.
-*
-* XDC_IXR_DMA_DONE_MASK The dma operation is done
-* XDC_IXR_DMA_ERROR_MASK The dma operation had an error
-* XDC_IXR_PKT_DONE_MASK A packet is complete
-* XDC_IXR_PKT_THRESHOLD_MASK The packet count threshold reached
-* XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
-* XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
-* XDC_IXR_SG_END_MASK Current descriptor was the end of the list
-* XDC_IXR_BD_MASK A buffer descriptor is done
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-void
-XDmaChannel_SetIntrEnable(XDmaChannel * InstancePtr, u32 Enable)
-{
- /* assert to verify input arguments except the enable which can't be
- * asserted since all values are valid
- */
- XASSERT_VOID(InstancePtr != NULL);
- XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* set the interrupt enable register to the specified value */
-
- XIo_Out32(InstancePtr->RegBaseAddress + XDC_IE_REG_OFFSET, Enable);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_GetIntrEnable
-*
-* DESCRIPTION:
-*
-* This function gets the interrupt enable of the DMA channel. The
-* interrupt enable contains flags which enable individual interrupts for the
-* DMA channel. The definitions of each bit in the register match the definition
-* of the bits in the interrupt status register.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* RETURN VALUE:
-*
-* The interrupt enable of the DMA channel. One or more of the following values
-* may be contained the register. Each of the values are unique bit masks.
-*
-* XDC_IXR_DMA_DONE_MASK The dma operation is done
-* XDC_IXR_DMA_ERROR_MASK The dma operation had an error
-* XDC_IXR_PKT_DONE_MASK A packet is complete
-* XDC_IXR_PKT_THRESHOLD_MASK The packet count threshold reached
-* XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
-* XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
-* XDC_IXR_BD_MASK A buffer descriptor is done
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-u32
-XDmaChannel_GetIntrEnable(XDmaChannel * InstancePtr)
-{
- /* assert to verify input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* return the contents of the interrupt enable register */
-
- return XIo_In32(InstancePtr->RegBaseAddress + XDC_IE_REG_OFFSET);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_Transfer
-*
-* DESCRIPTION:
-*
-* This function starts the DMA channel transferring data from a memory source
-* to a memory destination. This function only starts the operation and returns
-* before the operation may be complete. If the interrupt is enabled, an
-* interrupt will be generated when the operation is complete, otherwise it is
-* necessary to poll the channel status to determine when it's complete. It is
-* the responsibility of the caller to determine when the operation is complete
-* by handling the generated interrupt or polling the status. It is also the
-* responsibility of the caller to ensure that the DMA channel is not busy with
-* another transfer before calling this function.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* SourcePtr contains a pointer to the source memory where the data is to
-* be tranferred from and must be 32 bit aligned.
-*
-* DestinationPtr contains a pointer to the destination memory where the data
-* is to be transferred and must be 32 bit aligned.
-*
-* ByteCount contains the number of bytes to transfer during the DMA operation.
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* The DMA h/w will not currently allow a non-local memory transfer to non-local
-* memory (memory copy), but only allows a non-local memory to or from the device
-* memory (typically a FIFO).
-*
-* It is the responsibility of the caller to ensure that the cache is
-* flushed and invalidated both before and after the DMA operation completes
-* if the memory pointed to is cached. The caller must also ensure that the
-* pointers contain a physical address rather than a virtual address
-* if address translation is being used.
-*
-******************************************************************************/
-void
-XDmaChannel_Transfer(XDmaChannel * InstancePtr,
- u32 * SourcePtr, u32 * DestinationPtr, u32 ByteCount)
-{
- /* assert to verify input arguments and the alignment of any arguments
- * which have expected alignments
- */
- XASSERT_VOID(InstancePtr != NULL);
- XASSERT_VOID(SourcePtr != NULL);
- XASSERT_VOID(((u32) SourcePtr & 3) == 0);
- XASSERT_VOID(DestinationPtr != NULL);
- XASSERT_VOID(((u32) DestinationPtr & 3) == 0);
- XASSERT_VOID(ByteCount != 0);
- XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* setup the source and destination address registers for the transfer */
-
- XIo_Out32(InstancePtr->RegBaseAddress + XDC_SA_REG_OFFSET,
- (u32) SourcePtr);
-
- XIo_Out32(InstancePtr->RegBaseAddress + XDC_DA_REG_OFFSET,
- (u32) DestinationPtr);
-
- /* start the DMA transfer to copy from the source buffer to the
- * destination buffer by writing the length to the length register
- */
- XIo_Out32(InstancePtr->RegBaseAddress + XDC_LEN_REG_OFFSET, ByteCount);
-}
+++ /dev/null
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-* FILENAME:
-*
-* xdma_channel.h
-*
-* DESCRIPTION:
-*
-* This file contains the DMA channel component implementation. This component
-* supports a distributed DMA design in which each device can have it's own
-* dedicated DMA channel, as opposed to a centralized DMA design.
-* A device which uses DMA typically contains two DMA channels, one for
-* sending data and the other for receiving data.
-*
-* This component is designed to be used as a basic building block for
-* designing a device driver. It provides registers accesses such that all
-* DMA processing can be maintained easier, but the device driver designer
-* must still understand all the details of the DMA channel.
-*
-* The DMA channel allows a CPU to minimize the CPU interaction required to move
-* data between a memory and a device. The CPU requests the DMA channel to
-* perform a DMA operation and typically continues performing other processing
-* until the DMA operation completes. DMA could be considered a primitive form
-* of multiprocessing such that caching and address translation can be an issue.
-*
-* Scatter Gather Operations
-*
-* The DMA channel may support scatter gather operations. A scatter gather
-* operation automates the DMA channel such that multiple buffers can be
-* sent or received with minimal software interaction with the hardware. Buffer
-* descriptors, contained in the XBufDescriptor component, are used by the
-* scatter gather operations of the DMA channel to describe the buffers to be
-* processed.
-*
-* Scatter Gather List Operations
-*
-* A scatter gather list may be supported by each DMA channel. The scatter
-* gather list allows buffer descriptors to be put into the list by a device
-* driver which requires scatter gather. The hardware processes the buffer
-* descriptors which are contained in the list and modifies the buffer
-* descriptors to reflect the status of the DMA operations. The device driver
-* is notified by interrupt that specific DMA events occur including scatter
-* gather events. The device driver removes the completed buffer descriptors
-* from the scatter gather list to evaluate the status of each DMA operation.
-*
-* The scatter gather list is created and buffer descriptors are inserted into
-* the list. Buffer descriptors are never removed from the list after it's
-* creation such that a put operation copies from a temporary buffer descriptor
-* to a buffer descriptor in the list. Get operations don't copy from the list
-* to a temporary, but return a pointer to the buffer descriptor in the list.
-* A buffer descriptor in the list may be locked to prevent it from being
-* overwritten by a put operation. This allows the device driver to get a
-* descriptor from a scatter gather list and prevent it from being overwritten
-* until the buffer associated with the buffer descriptor has been processed.
-*
-* Typical Scatter Gather Processing
-*
-* The following steps illustrate the typical processing to use the
-* scatter gather features of a DMA channel.
-*
-* 1. Create a scatter gather list for the DMA channel which puts empty buffer
-* descriptors into the list.
-* 2. Create buffer descriptors which describe the buffers to be filled with
-* receive data or the buffers which contain data to be sent.
-* 3. Put buffer descriptors into the DMA channel scatter list such that scatter
-* gather operations are requested.
-* 4. Commit the buffer descriptors in the list such that they are ready to be
-* used by the DMA channel hardware.
-* 5. Start the scatter gather operations of the DMA channel.
-* 6. Process any interrupts which occur as a result of the scatter gather
-* operations or poll the DMA channel to determine the status.
-*
-* Interrupts
-*
-* Each DMA channel has the ability to generate an interrupt. This component
-* does not perform processing for the interrupt as this processing is typically
-* tightly coupled with the device which is using the DMA channel. It is the
-* responsibility of the caller of DMA functions to manage the interrupt
-* including connecting to the interrupt and enabling/disabling the interrupt.
-*
-* Critical Sections
-*
-* It is the responsibility of the device driver designer to use critical
-* sections as necessary when calling functions of the DMA channel. This
-* component does not use critical sections and it does access registers using
-* read-modify-write operations. Calls to DMA functions from a main thread
-* and from an interrupt context could produce unpredictable behavior such that
-* the caller must provide the appropriate critical sections.
-*
-* Address Translation
-*
-* All addresses of data structures which are passed to DMA functions must
-* be physical (real) addresses as opposed to logical (virtual) addresses.
-*
-* Caching
-*
-* The memory which is passed to the function which creates the scatter gather
-* list must not be cached such that buffer descriptors are non-cached. This
-* is necessary because the buffer descriptors are kept in a ring buffer and
-* not directly accessible to the caller of DMA functions.
-*
-* The caller of DMA functions is responsible for ensuring that any data
-* buffers which are passed to the DMA channel are cache-line aligned if
-* necessary.
-*
-* The caller of DMA functions is responsible for ensuring that any data
-* buffers which are passed to the DMA channel have been flushed from the cache.
-*
-* The caller of DMA functions is responsible for ensuring that the cache is
-* invalidated prior to using any data buffers which are the result of a DMA
-* operation.
-*
-* Memory Alignment
-*
-* The addresses of data buffers which are passed to DMA functions must be
-* 32 bit word aligned since the DMA hardware performs 32 bit word transfers.
-*
-* Mutual Exclusion
-*
-* The functions of the DMA channel are not thread safe such that the caller
-* of all DMA functions is responsible for ensuring mutual exclusion for a
-* DMA channel. Mutual exclusion across multiple DMA channels is not
-* necessary.
-*
-* NOTES:
-*
-* Many of the provided functions which are register accessors don't provide
-* a lot of error detection. The caller is expected to understand the impact
-* of a function call based upon the current state of the DMA channel. This
-* is done to minimize the overhead in this component.
-*
-******************************************************************************/
-
-#ifndef XDMA_CHANNEL_H /* prevent circular inclusions */
-#define XDMA_CHANNEL_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xdma_channel_i.h" /* constants shared with buffer descriptor */
-#include "xbasic_types.h"
-#include "xstatus.h"
-#include "xversion.h"
-#include "xbuf_descriptor.h"
-
-/************************** Constant Definitions *****************************/
-
-/* the following constants provide access to the bit fields of the DMA control
- * register (DMACR)
- */
-#define XDC_DMACR_SOURCE_INCR_MASK 0x80000000UL /* increment source address */
-#define XDC_DMACR_DEST_INCR_MASK 0x40000000UL /* increment dest address */
-#define XDC_DMACR_SOURCE_LOCAL_MASK 0x20000000UL /* local source address */
-#define XDC_DMACR_DEST_LOCAL_MASK 0x10000000UL /* local dest address */
-#define XDC_DMACR_SG_DISABLE_MASK 0x08000000UL /* scatter gather disable */
-#define XDC_DMACR_GEN_BD_INTR_MASK 0x04000000UL /* descriptor interrupt */
-#define XDC_DMACR_LAST_BD_MASK XDC_CONTROL_LAST_BD_MASK /* last buffer */
- /* descriptor */
-
-/* the following constants provide access to the bit fields of the DMA status
- * register (DMASR)
- */
-#define XDC_DMASR_BUSY_MASK 0x80000000UL /* channel is busy */
-#define XDC_DMASR_BUS_ERROR_MASK 0x40000000UL /* bus error occurred */
-#define XDC_DMASR_BUS_TIMEOUT_MASK 0x20000000UL /* bus timeout occurred */
-#define XDC_DMASR_LAST_BD_MASK XDC_STATUS_LAST_BD_MASK /* last buffer */
- /* descriptor */
-#define XDC_DMASR_SG_BUSY_MASK 0x08000000UL /* scatter gather is busy */
-
-/* the following constants provide access to the bit fields of the interrupt
- * status register (ISR) and the interrupt enable register (IER), bit masks
- * match for both registers such that they are named IXR
- */
-#define XDC_IXR_DMA_DONE_MASK 0x1UL /* dma operation done */
-#define XDC_IXR_DMA_ERROR_MASK 0x2UL /* dma operation error */
-#define XDC_IXR_PKT_DONE_MASK 0x4UL /* packet done */
-#define XDC_IXR_PKT_THRESHOLD_MASK 0x8UL /* packet count threshold */
-#define XDC_IXR_PKT_WAIT_BOUND_MASK 0x10UL /* packet wait bound reached */
-#define XDC_IXR_SG_DISABLE_ACK_MASK 0x20UL /* scatter gather disable
- acknowledge occurred */
-#define XDC_IXR_SG_END_MASK 0x40UL /* last buffer descriptor
- disabled scatter gather */
-#define XDC_IXR_BD_MASK 0x80UL /* buffer descriptor done */
-
-/**************************** Type Definitions *******************************/
-
-/*
- * the following structure contains data which is on a per instance basis
- * for the XDmaChannel component
- */
-typedef struct XDmaChannelTag {
- XVersion Version; /* version of the driver */
- u32 RegBaseAddress; /* base address of registers */
- u32 IsReady; /* device is initialized and ready */
-
- XBufDescriptor *PutPtr; /* keep track of where to put into list */
- XBufDescriptor *GetPtr; /* keep track of where to get from list */
- XBufDescriptor *CommitPtr; /* keep track of where to commit in list */
- XBufDescriptor *LastPtr; /* keep track of the last put in the list */
- u32 TotalDescriptorCount; /* total # of descriptors in the list */
- u32 ActiveDescriptorCount; /* # of descriptors pointing to buffers
- * in the buffer descriptor list */
-} XDmaChannel;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-XStatus XDmaChannel_Initialize(XDmaChannel * InstancePtr, u32 BaseAddress);
-u32 XDmaChannel_IsReady(XDmaChannel * InstancePtr);
-XVersion *XDmaChannel_GetVersion(XDmaChannel * InstancePtr);
-XStatus XDmaChannel_SelfTest(XDmaChannel * InstancePtr);
-void XDmaChannel_Reset(XDmaChannel * InstancePtr);
-
-/* Control functions */
-
-u32 XDmaChannel_GetControl(XDmaChannel * InstancePtr);
-void XDmaChannel_SetControl(XDmaChannel * InstancePtr, u32 Control);
-
-/* Status functions */
-
-u32 XDmaChannel_GetStatus(XDmaChannel * InstancePtr);
-void XDmaChannel_SetIntrStatus(XDmaChannel * InstancePtr, u32 Status);
-u32 XDmaChannel_GetIntrStatus(XDmaChannel * InstancePtr);
-void XDmaChannel_SetIntrEnable(XDmaChannel * InstancePtr, u32 Enable);
-u32 XDmaChannel_GetIntrEnable(XDmaChannel * InstancePtr);
-
-/* DMA without scatter gather functions */
-
-void XDmaChannel_Transfer(XDmaChannel * InstancePtr,
- u32 * SourcePtr, u32 * DestinationPtr, u32 ByteCount);
-
-/* Scatter gather functions */
-
-XStatus XDmaChannel_SgStart(XDmaChannel * InstancePtr);
-XStatus XDmaChannel_SgStop(XDmaChannel * InstancePtr,
- XBufDescriptor ** BufDescriptorPtr);
-XStatus XDmaChannel_CreateSgList(XDmaChannel * InstancePtr,
- u32 * MemoryPtr, u32 ByteCount);
-u32 XDmaChannel_IsSgListEmpty(XDmaChannel * InstancePtr);
-
-XStatus XDmaChannel_PutDescriptor(XDmaChannel * InstancePtr,
- XBufDescriptor * BufDescriptorPtr);
-XStatus XDmaChannel_CommitPuts(XDmaChannel * InstancePtr);
-XStatus XDmaChannel_GetDescriptor(XDmaChannel * InstancePtr,
- XBufDescriptor ** BufDescriptorPtr);
-
-/* Packet functions for interrupt collescing */
-
-u32 XDmaChannel_GetPktCount(XDmaChannel * InstancePtr);
-void XDmaChannel_DecrementPktCount(XDmaChannel * InstancePtr);
-XStatus XDmaChannel_SetPktThreshold(XDmaChannel * InstancePtr, u8 Threshold);
-u8 XDmaChannel_GetPktThreshold(XDmaChannel * InstancePtr);
-void XDmaChannel_SetPktWaitBound(XDmaChannel * InstancePtr, u32 WaitBound);
-u32 XDmaChannel_GetPktWaitBound(XDmaChannel * InstancePtr);
-
-#endif /* end of protection macro */
+++ /dev/null
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-* FILENAME:
-*
-* xdma_channel_i.h
-*
-* DESCRIPTION:
-*
-* This file contains data which is shared internal data for the DMA channel
-* component. It is also shared with the buffer descriptor component which is
-* very tightly coupled with the DMA channel component.
-*
-* NOTES:
-*
-* The last buffer descriptor constants must be located here to prevent a
-* circular dependency between the DMA channel component and the buffer
-* descriptor component.
-*
-******************************************************************************/
-
-#ifndef XDMA_CHANNEL_I_H /* prevent circular inclusions */
-#define XDMA_CHANNEL_I_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xbasic_types.h"
-#include "xstatus.h"
-#include "xversion.h"
-
-/************************** Constant Definitions *****************************/
-
-#define XDC_DMA_CHANNEL_V1_00_A "1.00a"
-
-/* the following constant provides access to the bit fields of the DMA control
- * register (DMACR) which must be shared between the DMA channel component
- * and the buffer descriptor component
- */
-#define XDC_CONTROL_LAST_BD_MASK 0x02000000UL /* last buffer descriptor */
-
-/* the following constant provides access to the bit fields of the DMA status
- * register (DMASR) which must be shared between the DMA channel component
- * and the buffer descriptor component
- */
-#define XDC_STATUS_LAST_BD_MASK 0x10000000UL /* last buffer descriptor */
-
-/* the following constants provide access to each of the registers of a DMA
- * channel
- */
-#define XDC_RST_REG_OFFSET 0 /* reset register */
-#define XDC_MI_REG_OFFSET 0 /* module information register */
-#define XDC_DMAC_REG_OFFSET 4 /* DMA control register */
-#define XDC_SA_REG_OFFSET 8 /* source address register */
-#define XDC_DA_REG_OFFSET 12 /* destination address register */
-#define XDC_LEN_REG_OFFSET 16 /* length register */
-#define XDC_DMAS_REG_OFFSET 20 /* DMA status register */
-#define XDC_BDA_REG_OFFSET 24 /* buffer descriptor address register */
-#define XDC_SWCR_REG_OFFSET 28 /* software control register */
-#define XDC_UPC_REG_OFFSET 32 /* unserviced packet count register */
-#define XDC_PCT_REG_OFFSET 36 /* packet count threshold register */
-#define XDC_PWB_REG_OFFSET 40 /* packet wait bound register */
-#define XDC_IS_REG_OFFSET 44 /* interrupt status register */
-#define XDC_IE_REG_OFFSET 48 /* interrupt enable register */
-
-/* the following constant is written to the reset register to reset the
- * DMA channel
- */
-#define XDC_RESET_MASK 0x0000000AUL
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-#endif /* end of protection macro */
+++ /dev/null
-/* $Id: xdma_channel_sg.c,v 1.6 2003/02/03 19:50:33 moleres Exp $ */
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-* FILENAME:
-*
-* xdma_channel_sg.c
-*
-* DESCRIPTION:
-*
-* This file contains the implementation of the XDmaChannel component which is
-* related to scatter gather operations.
-*
-* Scatter Gather Operations
-*
-* The DMA channel may support scatter gather operations. A scatter gather
-* operation automates the DMA channel such that multiple buffers can be
-* sent or received with minimal software interaction with the hardware. Buffer
-* descriptors, contained in the XBufDescriptor component, are used by the
-* scatter gather operations of the DMA channel to describe the buffers to be
-* processed.
-*
-* Scatter Gather List Operations
-*
-* A scatter gather list may be supported by each DMA channel. The scatter
-* gather list allows buffer descriptors to be put into the list by a device
-* driver which requires scatter gather. The hardware processes the buffer
-* descriptors which are contained in the list and modifies the buffer
-* descriptors to reflect the status of the DMA operations. The device driver
-* is notified by interrupt that specific DMA events occur including scatter
-* gather events. The device driver removes the completed buffer descriptors
-* from the scatter gather list to evaluate the status of each DMA operation.
-*
-* The scatter gather list is created and buffer descriptors are inserted into
-* the list. Buffer descriptors are never removed from the list after it's
-* creation such that a put operation copies from a temporary buffer descriptor
-* to a buffer descriptor in the list. Get operations don't copy from the list
-* to a temporary, but return a pointer to the buffer descriptor in the list.
-* A buffer descriptor in the list may be locked to prevent it from being
-* overwritten by a put operation. This allows the device driver to get a
-* descriptor from a scatter gather list and prevent it from being overwritten
-* until the buffer associated with the buffer descriptor has been processed.
-*
-* The get and put functions only operate on the list and are asynchronous from
-* the hardware which may be using the list of descriptors. This is important
-* because there are no checks in the get and put functions to ensure that the
-* hardware has processed the descriptors. This must be handled by the driver
-* using the DMA scatter gather channel through the use of the other functions.
-* When a scatter gather operation is started, the start function does ensure
-* that the descriptor to start has not already been processed by the hardware
-* and is not the first of a series of descriptors that have not been committed
-* yet.
-*
-* Descriptors are put into the list but not marked as ready to use by the
-* hardware until a commit operation is done. This allows multiple descriptors
-* which may contain a single packet of information for a protocol to be
-* guaranteed not to cause any underflow conditions during transmission. The
-* hardware design only allows descriptors to cause it to stop after a descriptor
-* has been processed rather than before it is processed. A series of
-* descriptors are put into the list followed by a commit operation, or each
-* descriptor may be commited. A commit operation is performed by changing a
-* single descriptor, the first of the series of puts, to indicate that the
-* hardware may now use all descriptors after it. The last descriptor in the
-* list is always set to cause the hardware to stop after it is processed.
-*
-* Typical Scatter Gather Processing
-*
-* The following steps illustrate the typical processing to use the
-* scatter gather features of a DMA channel.
-*
-* 1. Create a scatter gather list for the DMA channel which puts empty buffer
-* descriptors into the list.
-* 2. Create buffer descriptors which describe the buffers to be filled with
-* receive data or the buffers which contain data to be sent.
-* 3. Put buffer descriptors into the DMA channel scatter list such that scatter
-* gather operations are requested.
-* 4. Commit the buffer descriptors in the list such that they are ready to be
-* used by the DMA channel hardware.
-* 5. Start the scatter gather operations of the DMA channel.
-* 6. Process any interrupts which occur as a result of the scatter gather
-* operations or poll the DMA channel to determine the status. This may
-* be accomplished by getting the packet count for the channel and then
-* getting the appropriate number of descriptors from the list for that
-* number of packets.
-*
-* Minimizing Interrupts
-*
-* The Scatter Gather operating mode is designed to reduce the amount of CPU
-* throughput necessary to manage the hardware for devices. A key to the CPU
-* throughput is the number and rate of interrupts that the CPU must service.
-* Devices with higher data rates can cause larger numbers of interrupts and
-* higher frequency interrupts. Ideally the number of interrupts can be reduced
-* by only generating an interrupt when a specific amount of data has been
-* received from the interface. This design suffers from a lack of interrupts
-* when the amount of data received is less than the specified amount of data
-* to generate an interrupt. In order to help minimize the number of interrupts
-* which the CPU must service, an algorithm referred to as "interrupt coalescing"
-* is utilized.
-*
-* Interrupt Coalescing
-*
-* The principle of interrupt coalescing is to wait before generating an
-* interrupt until a certain number of packets have been received or sent. An
-* interrupt is also generated if a smaller number of packets have been received
-* followed by a certain period of time with no packet reception. This is a
-* trade-off of latency for bandwidth and is accomplished using several
-* mechanisms of the hardware including a counter for packets received or
-* transmitted and a packet timer. These two hardware mechanisms work in
-* combination to allow a reduction in the number of interrupts processed by the
-* CPU for packet reception.
-*
-* Unserviced Packet Count
-*
-* The purpose of the packet counter is to count the number of packets received
-* or transmitted and provide an interrupt when a specific number of packets
-* have been processed by the hardware. An interrupt is generated whenever the
-* counter is greater than or equal to the Packet Count Threshold. This counter
-* contains an accurate count of the number of packets that the hardware has
-* processed, either received or transmitted, and the software has not serviced.
-*
-* The packet counter allows the number of interrupts to be reduced by waiting
-* to generate an interrupt until enough packets are received. For packet
-* reception, packet counts of less than the number to generate an interrupt
-* would not be serviced without the addition of a packet timer. This counter is
-* continuously updated by the hardware, not latched to the value at the time
-* the interrupt occurred.
-*
-* The packet counter can be used within the interrupt service routine for the
-* device to reduce the number of interrupts. The interrupt service routine
-* loops while performing processing for each packet which has been received or
-* transmitted and decrements the counter by a specified value. At the same time,
-* the hardware is possibly continuing to receive or transmit more packets such
-* that the software may choose, based upon the value in the packet counter, to
-* remain in the interrupt service routine rather than exiting and immediately
-* returning. This feature should be used with caution as reducing the number of
-* interrupts is beneficial, but unbounded interrupt processing is not desirable.
-*
-* Since the hardware may be incrementing the packet counter simultaneously
-* with the software decrementing the counter, there is a need for atomic
-* operations. The hardware ensures that the operation is atomic such that
-* simultaneous accesses are properly handled.
-*
-* Packet Wait Bound
-*
-* The purpose of the packet wait bound is to augment the unserviced packet
-* count. Whenever there is no pending interrupt for the channel and the
-* unserviced packet count is non-zero, a timer starts counting timeout at the
-* value contained the the packet wait bound register. If the timeout is
-* reached, an interrupt is generated such that the software may service the
-* data which was buffered.
-*
-* NOTES:
-*
-* Special Test Conditions:
-*
-* The scatter gather list processing must be thoroughly tested if changes are
-* made. Testing should include putting and committing single descriptors and
-* putting multiple descriptors followed by a single commit. There are some
-* conditions in the code which handle the exception conditions.
-*
-* The Put Pointer points to the next location in the descriptor list to copy
-* in a new descriptor. The Get Pointer points to the next location in the
-* list to get a descriptor from. The Get Pointer only allows software to
-* have a traverse the list after the hardware has finished processing some
-* number of descriptors. The Commit Pointer points to the descriptor in the
-* list which is to be committed. It is also used to determine that no
-* descriptor is waiting to be commited (NULL). The Last Pointer points to
-* the last descriptor that was put into the list. It typically points
-* to the previous descriptor to the one pointed to by the Put Pointer.
-* Comparisons are done between these pointers to determine when the following
-* special conditions exist.
-
-* Single Put And Commit
-*
-* The buffer descriptor is ready to be used by the hardware so it is important
-* for the descriptor to not appear to be waiting to be committed. The commit
-* pointer is reset when a commit is done indicating there are no descriptors
-* waiting to be committed. In all cases but this one, the descriptor is
-* changed to cause the hardware to go to the next descriptor after processing
-* this one. But in this case, this is the last descriptor in the list such
-* that it must not be changed.
-*
-* 3 Or More Puts And Commit
-*
-* A series of 3 or more puts followed by a single commit is different in that
-* only the 1st descriptor put into the list is changed when the commit is done.
-* This requires each put starting on the 3rd to change the previous descriptor
-* so that it allows the hardware to continue to the next descriptor in the list.
-*
-* The 1st Put Following A Commit
-*
-* The commit caused the commit pointer to be NULL indicating that there are no
-* descriptors waiting to be committed. It is necessary for the next put to set
-* the commit pointer so that a commit must follow the put for the hardware to
-* use the descriptor.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ------------------------------------------------------
-* 1.00a rpm 02/03/03 Removed the XST_DMA_SG_COUNT_EXCEEDED return code
-* from SetPktThreshold.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xdma_channel.h"
-#include "xbasic_types.h"
-#include "xio.h"
-#include "xbuf_descriptor.h"
-#include "xstatus.h"
-
-/************************** Constant Definitions *****************************/
-
-#define XDC_SWCR_SG_ENABLE_MASK 0x80000000UL /* scatter gather enable */
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/* the following macro copies selected fields of a buffer descriptor to another
- * buffer descriptor, this was provided by the buffer descriptor component but
- * was moved here since it is only used internally to this component and since
- * it does not copy all fields
- */
-#define CopyBufferDescriptor(InstancePtr, DestinationPtr) \
-{ \
- *((u32 *)DestinationPtr + XBD_CONTROL_OFFSET) = \
- *((u32 *)InstancePtr + XBD_CONTROL_OFFSET); \
- *((u32 *)DestinationPtr + XBD_SOURCE_OFFSET) = \
- *((u32 *)InstancePtr + XBD_SOURCE_OFFSET); \
- *((u32 *)DestinationPtr + XBD_DESTINATION_OFFSET) = \
- *((u32 *)InstancePtr + XBD_DESTINATION_OFFSET); \
- *((u32 *)DestinationPtr + XBD_LENGTH_OFFSET) = \
- *((u32 *)InstancePtr + XBD_LENGTH_OFFSET); \
- *((u32 *)DestinationPtr + XBD_STATUS_OFFSET) = \
- *((u32 *)InstancePtr + XBD_STATUS_OFFSET); \
- *((u32 *)DestinationPtr + XBD_DEVICE_STATUS_OFFSET) = \
- *((u32 *)InstancePtr + XBD_DEVICE_STATUS_OFFSET); \
- *((u32 *)DestinationPtr + XBD_ID_OFFSET) = \
- *((u32 *)InstancePtr + XBD_ID_OFFSET); \
- *((u32 *)DestinationPtr + XBD_FLAGS_OFFSET) = \
- *((u32 *)InstancePtr + XBD_FLAGS_OFFSET); \
- *((u32 *)DestinationPtr + XBD_RQSTED_LENGTH_OFFSET) = \
- *((u32 *)InstancePtr + XBD_RQSTED_LENGTH_OFFSET); \
-}
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_SgStart
-*
-* DESCRIPTION:
-*
-* This function starts a scatter gather operation for a scatter gather
-* DMA channel. The first buffer descriptor in the buffer descriptor list
-* will be started with the scatter gather operation. A scatter gather list
-* should have previously been created for the DMA channel and buffer
-* descriptors put into the scatter gather list such that there are scatter
-* operations ready to be performed.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on. The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* RETURN VALUE:
-*
-* A status containing XST_SUCCESS if scatter gather was started successfully
-* for the DMA channel.
-*
-* A value of XST_DMA_SG_NO_LIST indicates the scatter gather list has not
-* been created.
-*
-* A value of XST_DMA_SG_LIST_EMPTY indicates scatter gather was not started
-* because the scatter gather list of the DMA channel does not contain any
-* buffer descriptors that are ready to be processed by the hardware.
-*
-* A value of XST_DMA_SG_IS_STARTED indicates scatter gather was not started
-* because the scatter gather was not stopped, but was already started.
-*
-* A value of XST_DMA_SG_BD_NOT_COMMITTED indicates the buffer descriptor of
-* scatter gather list which was to be started is not committed to the list.
-* This status is more likely if this function is being called from an ISR
-* and non-ISR processing is putting descriptors into the list.
-*
-* A value of XST_DMA_SG_NO_DATA indicates that the buffer descriptor of the
-* scatter gather list which was to be started had already been used by the
-* hardware for a DMA transfer that has been completed.
-*
-* NOTES:
-*
-* It is the responsibility of the caller to get all the buffer descriptors
-* after performing a stop operation and before performing a start operation.
-* If buffer descriptors are not retrieved between stop and start operations,
-* buffer descriptors may be processed by the hardware more than once.
-*
-******************************************************************************/
-XStatus
-XDmaChannel_SgStart(XDmaChannel * InstancePtr)
-{
- u32 Register;
- XBufDescriptor *LastDescriptorPtr;
-
- /* assert to verify input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* if a scatter gather list has not been created yet, return a status */
-
- if (InstancePtr->TotalDescriptorCount == 0) {
- return XST_DMA_SG_NO_LIST;
- }
-
- /* if the scatter gather list exists but is empty then return a status */
-
- if (XDmaChannel_IsSgListEmpty(InstancePtr)) {
- return XST_DMA_SG_LIST_EMPTY;
- }
-
- /* if scatter gather is busy for the DMA channel, return a status because
- * restarting it could lose data
- */
-
- Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAS_REG_OFFSET);
- if (Register & XDC_DMASR_SG_BUSY_MASK) {
- return XST_DMA_SG_IS_STARTED;
- }
-
- /* get the address of the last buffer descriptor which the DMA hardware
- * finished processing
- */
- LastDescriptorPtr =
- (XBufDescriptor *) XIo_In32(InstancePtr->RegBaseAddress +
- XDC_BDA_REG_OFFSET);
-
- /* setup the first buffer descriptor that will be sent when the scatter
- * gather channel is enabled, this is only necessary one time since
- * the BDA register of the channel maintains the last buffer descriptor
- * processed
- */
- if (LastDescriptorPtr == NULL) {
- XIo_Out32(InstancePtr->RegBaseAddress + XDC_BDA_REG_OFFSET,
- (u32) InstancePtr->GetPtr);
- } else {
- XBufDescriptor *NextDescriptorPtr;
-
- /* get the next descriptor to be started, if the status indicates it
- * hasn't already been used by the h/w, then it's OK to start it,
- * s/w sets the status of each descriptor to busy and then h/w clears
- * the busy when it is complete
- */
- NextDescriptorPtr =
- XBufDescriptor_GetNextPtr(LastDescriptorPtr);
-
- if ((XBufDescriptor_GetStatus(NextDescriptorPtr) &
- XDC_DMASR_BUSY_MASK) == 0) {
- return XST_DMA_SG_NO_DATA;
- }
- /* don't start the DMA SG channel if the descriptor to be processed
- * by h/w is to be committed by the s/w, this function can be called
- * such that it interrupts a thread that was putting into the list
- */
- if (NextDescriptorPtr == InstancePtr->CommitPtr) {
- return XST_DMA_SG_BD_NOT_COMMITTED;
- }
- }
-
- /* start the scatter gather operation by clearing the stop bit in the
- * control register and setting the enable bit in the s/w control register,
- * both of these are necessary to cause it to start, right now the order of
- * these statements is important, the software control register should be
- * set 1st. The other order can cause the CPU to have a loss of sync
- * because it cannot read/write the register while the DMA operation is
- * running
- */
-
- Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_SWCR_REG_OFFSET);
-
- XIo_Out32(InstancePtr->RegBaseAddress + XDC_SWCR_REG_OFFSET,
- Register | XDC_SWCR_SG_ENABLE_MASK);
-
- Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET);
-
- XIo_Out32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET,
- Register & ~XDC_DMACR_SG_DISABLE_MASK);
-
- /* indicate the DMA channel scatter gather operation was started
- * successfully
- */
- return XST_SUCCESS;
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_SgStop
-*
-* DESCRIPTION:
-*
-* This function stops a scatter gather operation for a scatter gather
-* DMA channel. This function starts the process of stopping a scatter
-* gather operation that is in progress and waits for the stop to be completed.
-* Since it waits for the operation to stopped before returning, this function
-* could take an amount of time relative to the size of the DMA scatter gather
-* operation which is in progress. The scatter gather list of the DMA channel
-* is not modified by this function such that starting the scatter gather
-* channel after stopping it will cause it to resume. This operation is
-* considered to be a graceful stop in that the scatter gather operation
-* completes the current buffer descriptor before stopping.
-*
-* If the interrupt is enabled, an interrupt will be generated when the
-* operation is stopped and the caller is responsible for handling the
-* interrupt.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on. The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* BufDescriptorPtr is also a return value which contains a pointer to the
-* buffer descriptor which the scatter gather operation completed when it
-* was stopped.
-*
-* RETURN VALUE:
-*
-* A status containing XST_SUCCESS if scatter gather was stopped successfully
-* for the DMA channel.
-*
-* A value of XST_DMA_SG_IS_STOPPED indicates scatter gather was not stoppped
-* because the scatter gather is not started, but was already stopped.
-*
-* BufDescriptorPtr contains a pointer to the buffer descriptor which was
-* completed when the operation was stopped.
-*
-* NOTES:
-*
-* This function implements a loop which polls the hardware for an infinite
-* amount of time. If the hardware is not operating correctly, this function
-* may never return.
-*
-******************************************************************************/
-XStatus
-XDmaChannel_SgStop(XDmaChannel * InstancePtr,
- XBufDescriptor ** BufDescriptorPtr)
-{
- u32 Register;
-
- /* assert to verify input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(BufDescriptorPtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* get the contents of the software control register, if scatter gather is not
- * enabled (started), then return a status because the disable acknowledge
- * would not be generated
- */
- Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_SWCR_REG_OFFSET);
-
- if ((Register & XDC_SWCR_SG_ENABLE_MASK) == 0) {
- return XST_DMA_SG_IS_STOPPED;
- }
-
- /* Ensure the interrupt status for the scatter gather is cleared such
- * that this function will wait til the disable has occurred, writing
- * a 1 to only that bit in the register will clear only it
- */
- XIo_Out32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET,
- XDC_IXR_SG_DISABLE_ACK_MASK);
-
- /* disable scatter gather by writing to the software control register
- * without modifying any other bits of the register
- */
- XIo_Out32(InstancePtr->RegBaseAddress + XDC_SWCR_REG_OFFSET,
- Register & ~XDC_SWCR_SG_ENABLE_MASK);
-
- /* scatter gather does not disable immediately, but after the current
- * buffer descriptor is complete, so wait for the DMA channel to indicate
- * the disable is complete
- */
- do {
- Register =
- XIo_In32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET);
- } while ((Register & XDC_IXR_SG_DISABLE_ACK_MASK) == 0);
-
- /* Ensure the interrupt status for the scatter gather disable is cleared,
- * writing a 1 to only that bit in the register will clear only it
- */
- XIo_Out32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET,
- XDC_IXR_SG_DISABLE_ACK_MASK);
-
- /* set the specified buffer descriptor pointer to point to the buffer
- * descriptor that the scatter gather DMA channel was processing
- */
- *BufDescriptorPtr =
- (XBufDescriptor *) XIo_In32(InstancePtr->RegBaseAddress +
- XDC_BDA_REG_OFFSET);
-
- return XST_SUCCESS;
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_CreateSgList
-*
-* DESCRIPTION:
-*
-* This function creates a scatter gather list in the DMA channel. A scatter
-* gather list consists of a list of buffer descriptors that are available to
-* be used for scatter gather operations. Buffer descriptors are put into the
-* list to request a scatter gather operation to be performed.
-*
-* A number of buffer descriptors are created from the specified memory and put
-* into a buffer descriptor list as empty buffer descriptors. This function must
-* be called before non-empty buffer descriptors may be put into the DMA channel
-* to request scatter gather operations.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on. The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* MemoryPtr contains a pointer to the memory which is to be used for buffer
-* descriptors and must not be cached.
-*
-* ByteCount contains the number of bytes for the specified memory to be used
-* for buffer descriptors.
-*
-* RETURN VALUE:
-*
-* A status contains XST_SUCCESS if the scatter gather list was successfully
-* created.
-*
-* A value of XST_DMA_SG_LIST_EXISTS indicates that the scatter gather list
-* was not created because the list has already been created.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-XStatus
-XDmaChannel_CreateSgList(XDmaChannel * InstancePtr,
- u32 * MemoryPtr, u32 ByteCount)
-{
- XBufDescriptor *BufferDescriptorPtr = (XBufDescriptor *) MemoryPtr;
- XBufDescriptor *PreviousDescriptorPtr = NULL;
- XBufDescriptor *StartOfListPtr = BufferDescriptorPtr;
- u32 UsedByteCount;
-
- /* assert to verify valid input arguments, alignment for those
- * arguments that have alignment restrictions, and at least enough
- * memory for one buffer descriptor
- */
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(MemoryPtr != NULL);
- XASSERT_NONVOID(((u32) MemoryPtr & 3) == 0);
- XASSERT_NONVOID(ByteCount != 0);
- XASSERT_NONVOID(ByteCount >= sizeof (XBufDescriptor));
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* if the scatter gather list has already been created, then return
- * with a status
- */
- if (InstancePtr->TotalDescriptorCount != 0) {
- return XST_DMA_SG_LIST_EXISTS;
- }
-
- /* loop thru the specified memory block and create as many buffer
- * descriptors as possible putting each into the list which is
- * implemented as a ring buffer, make sure not to use any memory which
- * is not large enough for a complete buffer descriptor
- */
- UsedByteCount = 0;
- while ((UsedByteCount + sizeof (XBufDescriptor)) <= ByteCount) {
- /* setup a pointer to the next buffer descriptor in the memory and
- * update # of used bytes to know when all of memory is used
- */
- BufferDescriptorPtr = (XBufDescriptor *) ((u32) MemoryPtr +
- UsedByteCount);
-
- /* initialize the new buffer descriptor such that it doesn't contain
- * garbage which could be used by the DMA hardware
- */
- XBufDescriptor_Initialize(BufferDescriptorPtr);
-
- /* if this is not the first buffer descriptor to be created,
- * then link it to the last created buffer descriptor
- */
- if (PreviousDescriptorPtr != NULL) {
- XBufDescriptor_SetNextPtr(PreviousDescriptorPtr,
- BufferDescriptorPtr);
- }
-
- /* always keep a pointer to the last created buffer descriptor such
- * that they can be linked together in the ring buffer
- */
- PreviousDescriptorPtr = BufferDescriptorPtr;
-
- /* keep a count of the number of descriptors in the list to allow
- * error processing to be performed
- */
- InstancePtr->TotalDescriptorCount++;
-
- UsedByteCount += sizeof (XBufDescriptor);
- }
-
- /* connect the last buffer descriptor created and inserted in the list
- * to the first such that a ring buffer is created
- */
- XBufDescriptor_SetNextPtr(BufferDescriptorPtr, StartOfListPtr);
-
- /* initialize the ring buffer to indicate that there are no
- * buffer descriptors in the list which point to valid data buffers
- */
- InstancePtr->PutPtr = BufferDescriptorPtr;
- InstancePtr->GetPtr = BufferDescriptorPtr;
- InstancePtr->CommitPtr = NULL;
- InstancePtr->LastPtr = BufferDescriptorPtr;
- InstancePtr->ActiveDescriptorCount = 0;
-
- /* indicate the scatter gather list was successfully created */
-
- return XST_SUCCESS;
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_IsSgListEmpty
-*
-* DESCRIPTION:
-*
-* This function determines if the scatter gather list of a DMA channel is
-* empty with regard to buffer descriptors which are pointing to buffers to be
-* used for scatter gather operations.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on. The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* RETURN VALUE:
-*
-* A value of TRUE if the scatter gather list is empty, otherwise a value of
-* FALSE.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-u32
-XDmaChannel_IsSgListEmpty(XDmaChannel * InstancePtr)
-{
- /* assert to verify valid input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* if the number of descriptors which are being used in the list is zero
- * then the list is empty
- */
- return (InstancePtr->ActiveDescriptorCount == 0);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_PutDescriptor
-*
-* DESCRIPTION:
-*
-* This function puts a buffer descriptor into the DMA channel scatter
-* gather list. A DMA channel maintains a list of buffer descriptors which are
-* to be processed. This function puts the specified buffer descriptor
-* at the next location in the list. Note that since the list is already intact,
-* the information in the parameter is copied into the list (rather than modify
-* list pointers on the fly).
-*
-* After buffer descriptors are put into the list, they must also be committed
-* by calling another function. This allows multiple buffer descriptors which
-* span a single packet to be put into the list while preventing the hardware
-* from starting the first buffer descriptor of the packet.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on. The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* BufferDescriptorPtr is a pointer to the buffer descriptor to be put into
-* the next available location of the scatter gather list.
-*
-* RETURN VALUE:
-*
-* A status which indicates XST_SUCCESS if the buffer descriptor was
-* successfully put into the scatter gather list.
-*
-* A value of XST_DMA_SG_NO_LIST indicates the scatter gather list has not
-* been created.
-*
-* A value of XST_DMA_SG_LIST_FULL indicates the buffer descriptor was not
-* put into the list because the list was full.
-*
-* A value of XST_DMA_SG_BD_LOCKED indicates the buffer descriptor was not
-* put into the list because the buffer descriptor in the list which is to
-* be overwritten was locked. A locked buffer descriptor indicates the higher
-* layered software is still using the buffer descriptor.
-*
-* NOTES:
-*
-* It is necessary to create a scatter gather list for a DMA channel before
-* putting buffer descriptors into it.
-*
-******************************************************************************/
-XStatus
-XDmaChannel_PutDescriptor(XDmaChannel * InstancePtr,
- XBufDescriptor * BufferDescriptorPtr)
-{
- u32 Control;
-
- /* assert to verify valid input arguments and alignment for those
- * arguments that have alignment restrictions
- */
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(BufferDescriptorPtr != NULL);
- XASSERT_NONVOID(((u32) BufferDescriptorPtr & 3) == 0);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* if a scatter gather list has not been created yet, return a status */
-
- if (InstancePtr->TotalDescriptorCount == 0) {
- return XST_DMA_SG_NO_LIST;
- }
-
- /* if the list is full because all descriptors are pointing to valid
- * buffers, then indicate an error, this code assumes no list or an
- * empty list is detected above
- */
- if (InstancePtr->ActiveDescriptorCount ==
- InstancePtr->TotalDescriptorCount) {
- return XST_DMA_SG_LIST_FULL;
- }
-
- /* if the buffer descriptor in the list which is to be overwritten is
- * locked, then don't overwrite it and return a status
- */
- if (XBufDescriptor_IsLocked(InstancePtr->PutPtr)) {
- return XST_DMA_SG_BD_LOCKED;
- }
-
- /* set the scatter gather stop bit in the control word of the descriptor
- * to cause the h/w to stop after it processes this descriptor since it
- * will be the last in the list
- */
- Control = XBufDescriptor_GetControl(BufferDescriptorPtr);
- XBufDescriptor_SetControl(BufferDescriptorPtr,
- Control | XDC_DMACR_SG_DISABLE_MASK);
-
- /* set both statuses in the descriptor so we tell if they are updated with
- * the status of the transfer, the hardware should change the busy in the
- * DMA status to be false when it completes
- */
- XBufDescriptor_SetStatus(BufferDescriptorPtr, XDC_DMASR_BUSY_MASK);
- XBufDescriptor_SetDeviceStatus(BufferDescriptorPtr, 0);
-
- /* copy the descriptor into the next position in the list so it's ready to
- * be used by the h/w, this assumes the descriptor in the list prior to this
- * one still has the stop bit in the control word set such that the h/w
- * use this one yet
- */
- CopyBufferDescriptor(BufferDescriptorPtr, InstancePtr->PutPtr);
-
- /* only the last in the list and the one to be committed have scatter gather
- * disabled in the control word, a commit requires only one descriptor
- * to be changed, when # of descriptors to commit > 2 all others except the
- * 1st and last have scatter gather enabled
- */
- if ((InstancePtr->CommitPtr != InstancePtr->LastPtr) &&
- (InstancePtr->CommitPtr != NULL)) {
- Control = XBufDescriptor_GetControl(InstancePtr->LastPtr);
- XBufDescriptor_SetControl(InstancePtr->LastPtr,
- Control & ~XDC_DMACR_SG_DISABLE_MASK);
- }
-
- /* update the list data based upon putting a descriptor into the list,
- * these operations must be last
- */
- InstancePtr->ActiveDescriptorCount++;
-
- /* only update the commit pointer if it is not already active, this allows
- * it to be deactivated after every commit such that a single descriptor
- * which is committed does not appear to be waiting to be committed
- */
- if (InstancePtr->CommitPtr == NULL) {
- InstancePtr->CommitPtr = InstancePtr->LastPtr;
- }
-
- /* these updates MUST BE LAST after the commit pointer update in order for
- * the commit pointer to track the correct descriptor to be committed
- */
- InstancePtr->LastPtr = InstancePtr->PutPtr;
- InstancePtr->PutPtr = XBufDescriptor_GetNextPtr(InstancePtr->PutPtr);
-
- return XST_SUCCESS;
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_CommitPuts
-*
-* DESCRIPTION:
-*
-* This function commits the buffer descriptors which have been put into the
-* scatter list for the DMA channel since the last commit operation was
-* performed. This enables the calling functions to put several buffer
-* descriptors into the list (e.g.,a packet's worth) before allowing the scatter
-* gather operations to start. This prevents the DMA channel hardware from
-* starting to use the buffer descriptors in the list before they are ready
-* to be used (multiple buffer descriptors for a single packet).
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on. The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* RETURN VALUE:
-*
-* A status indicating XST_SUCCESS if the buffer descriptors of the list were
-* successfully committed.
-*
-* A value of XST_DMA_SG_NOTHING_TO_COMMIT indicates that the buffer descriptors
-* were not committed because there was nothing to commit in the list. All the
-* buffer descriptors which are in the list are commited.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-XStatus
-XDmaChannel_CommitPuts(XDmaChannel * InstancePtr)
-{
- /* assert to verify input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* if the buffer descriptor to be committed is already committed or
- * the list is empty (none have been put in), then indicate an error
- */
- if ((InstancePtr->CommitPtr == NULL) ||
- XDmaChannel_IsSgListEmpty(InstancePtr)) {
- return XST_DMA_SG_NOTHING_TO_COMMIT;
- }
-
- /* last descriptor in the list must have scatter gather disabled so the end
- * of the list is hit by h/w, if descriptor to commit is not last in list,
- * commit descriptors by enabling scatter gather in the descriptor
- */
- if (InstancePtr->CommitPtr != InstancePtr->LastPtr) {
- u32 Control;
-
- Control = XBufDescriptor_GetControl(InstancePtr->CommitPtr);
- XBufDescriptor_SetControl(InstancePtr->CommitPtr, Control &
- ~XDC_DMACR_SG_DISABLE_MASK);
- }
- /* Update the commit pointer to indicate that there is nothing to be
- * committed, this state is used by start processing to know that the
- * buffer descriptor to start is not waiting to be committed
- */
- InstancePtr->CommitPtr = NULL;
-
- return XST_SUCCESS;
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_GetDescriptor
-*
-* DESCRIPTION:
-*
-* This function gets a buffer descriptor from the scatter gather list of the
-* DMA channel. The buffer descriptor is retrieved from the scatter gather list
-* and the scatter gather list is updated to not include the retrieved buffer
-* descriptor. This is typically done after a scatter gather operation
-* completes indicating that a data buffer has been successfully sent or data
-* has been received into the data buffer. The purpose of this function is to
-* allow the device using the scatter gather operation to get the results of the
-* operation.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on. The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* BufDescriptorPtr is a pointer to a pointer to the buffer descriptor which
-* was retrieved from the list. The buffer descriptor is not really removed
-* from the list, but it is changed to a state such that the hardware will not
-* use it again until it is put into the scatter gather list of the DMA channel.
-*
-* RETURN VALUE:
-*
-* A status indicating XST_SUCCESS if a buffer descriptor was retrieved from
-* the scatter gather list of the DMA channel.
-*
-* A value of XST_DMA_SG_NO_LIST indicates the scatter gather list has not
-* been created.
-*
-* A value of XST_DMA_SG_LIST_EMPTY indicates no buffer descriptor was
-* retrieved from the list because there are no buffer descriptors to be
-* processed in the list.
-*
-* BufDescriptorPtr is updated to point to the buffer descriptor which was
-* retrieved from the list if the status indicates success.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-XStatus
-XDmaChannel_GetDescriptor(XDmaChannel * InstancePtr,
- XBufDescriptor ** BufDescriptorPtr)
-{
- u32 Control;
-
- /* assert to verify input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(BufDescriptorPtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* if a scatter gather list has not been created yet, return a status */
-
- if (InstancePtr->TotalDescriptorCount == 0) {
- return XST_DMA_SG_NO_LIST;
- }
-
- /* if the buffer descriptor list is empty, then indicate an error */
-
- if (XDmaChannel_IsSgListEmpty(InstancePtr)) {
- return XST_DMA_SG_LIST_EMPTY;
- }
-
- /* retrieve the next buffer descriptor which is ready to be processed from
- * the buffer descriptor list for the DMA channel, set the control word
- * such that hardware will stop after the descriptor has been processed
- */
- Control = XBufDescriptor_GetControl(InstancePtr->GetPtr);
- XBufDescriptor_SetControl(InstancePtr->GetPtr,
- Control | XDC_DMACR_SG_DISABLE_MASK);
-
- /* set the input argument, which is also an output, to point to the
- * buffer descriptor which is to be retrieved from the list
- */
- *BufDescriptorPtr = InstancePtr->GetPtr;
-
- /* update the pointer of the DMA channel to reflect the buffer descriptor
- * was retrieved from the list by setting it to the next buffer descriptor
- * in the list and indicate one less descriptor in the list now
- */
- InstancePtr->GetPtr = XBufDescriptor_GetNextPtr(InstancePtr->GetPtr);
- InstancePtr->ActiveDescriptorCount--;
-
- return XST_SUCCESS;
-}
-
-/*********************** Interrupt Collescing Functions **********************/
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_GetPktCount
-*
-* DESCRIPTION:
-*
-* This function returns the value of the unserviced packet count register of
-* the DMA channel. This count represents the number of packets that have been
-* sent or received by the hardware, but not processed by software.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on. The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* RETURN VALUE:
-*
-* The unserviced packet counter register contents for the DMA channel.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-u32
-XDmaChannel_GetPktCount(XDmaChannel * InstancePtr)
-{
- /* assert to verify input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* get the unserviced packet count from the register and return it */
-
- return XIo_In32(InstancePtr->RegBaseAddress + XDC_UPC_REG_OFFSET);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_DecrementPktCount
-*
-* DESCRIPTION:
-*
-* This function decrements the value of the unserviced packet count register.
-* This informs the hardware that the software has processed a packet. The
-* unserviced packet count register may only be decremented by one in the
-* hardware.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on. The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-void
-XDmaChannel_DecrementPktCount(XDmaChannel * InstancePtr)
-{
- u32 Register;
-
- /* assert to verify input arguments */
-
- XASSERT_VOID(InstancePtr != NULL);
- XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* if the unserviced packet count register can be decremented (rather
- * than rolling over) decrement it by writing a 1 to the register,
- * this is the only valid write to the register as it serves as an
- * acknowledge that a packet was handled by the software
- */
- Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_UPC_REG_OFFSET);
- if (Register > 0) {
- XIo_Out32(InstancePtr->RegBaseAddress + XDC_UPC_REG_OFFSET,
- 1UL);
- }
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_SetPktThreshold
-*
-* DESCRIPTION:
-*
-* This function sets the value of the packet count threshold register of the
-* DMA channel. It reflects the number of packets that must be sent or
-* received before generating an interrupt. This value helps implement
-* a concept called "interrupt coalescing", which is used to reduce the number
-* of interrupts from devices with high data rates.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on. The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* Threshold is the value that is written to the threshold register of the
-* DMA channel.
-*
-* RETURN VALUE:
-*
-* A status containing XST_SUCCESS if the packet count threshold was
-* successfully set.
-*
-* NOTES:
-*
-* The packet threshold could be set to larger than the number of descriptors
-* allocated to the DMA channel. In this case, the wait bound will take over
-* and always indicate data arrival. There was a check in this function that
-* returned an error if the treshold was larger than the number of descriptors,
-* but that was removed because users would then have to set the threshold
-* only after they set descriptor space, which is an order dependency that
-* caused confustion.
-*
-******************************************************************************/
-XStatus
-XDmaChannel_SetPktThreshold(XDmaChannel * InstancePtr, u8 Threshold)
-{
- /* assert to verify input arguments, don't assert the threshold since
- * it's range is unknown
- */
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* set the packet count threshold in the register such that an interrupt
- * may be generated, if enabled, when the packet count threshold is
- * reached or exceeded
- */
- XIo_Out32(InstancePtr->RegBaseAddress + XDC_PCT_REG_OFFSET,
- (u32) Threshold);
-
- /* indicate the packet count threshold was successfully set */
-
- return XST_SUCCESS;
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_GetPktThreshold
-*
-* DESCRIPTION:
-*
-* This function gets the value of the packet count threshold register of the
-* DMA channel. This value reflects the number of packets that must be sent or
-* received before generating an interrupt. This value helps implement a concept
-* called "interrupt coalescing", which is used to reduce the number of
-* interrupts from devices with high data rates.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on. The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* RETURN VALUE:
-*
-* The packet threshold register contents for the DMA channel and is a value in
-* the range 0 - 1023. A value of 0 indicates the packet wait bound timer is
-* disabled.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-u8
-XDmaChannel_GetPktThreshold(XDmaChannel * InstancePtr)
-{
- /* assert to verify input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* get the packet count threshold from the register and return it,
- * since only 8 bits are used, cast it to return only those bits */
-
- return (u8) XIo_In32(InstancePtr->RegBaseAddress + XDC_PCT_REG_OFFSET);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_SetPktWaitBound
-*
-* DESCRIPTION:
-*
-* This function sets the value of the packet wait bound register of the
-* DMA channel. This value reflects the timer value used to trigger an
-* interrupt when not enough packets have been received to reach the packet
-* count threshold.
-*
-* The timer is in millisecond units with +/- 33% accuracy.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on. The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* WaitBound is the value, in milliseconds, to be stored in the wait bound
-* register of the DMA channel and is a value in the range 0 - 1023. A value
-* of 0 disables the packet wait bound timer.
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-void
-XDmaChannel_SetPktWaitBound(XDmaChannel * InstancePtr, u32 WaitBound)
-{
- /* assert to verify input arguments */
-
- XASSERT_VOID(InstancePtr != NULL);
- XASSERT_VOID(WaitBound < 1024);
- XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* set the packet wait bound in the register such that interrupt may be
- * generated, if enabled, when packets have not been handled for a specific
- * amount of time
- */
- XIo_Out32(InstancePtr->RegBaseAddress + XDC_PWB_REG_OFFSET, WaitBound);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_GetPktWaitBound
-*
-* DESCRIPTION:
-*
-* This function gets the value of the packet wait bound register of the
-* DMA channel. This value contains the timer value used to trigger an
-* interrupt when not enough packets have been received to reach the packet
-* count threshold.
-*
-* The timer is in millisecond units with +/- 33% accuracy.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on. The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* RETURN VALUE:
-*
-* The packet wait bound register contents for the DMA channel.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-u32
-XDmaChannel_GetPktWaitBound(XDmaChannel * InstancePtr)
-{
- /* assert to verify input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* get the packet wait bound from the register and return it */
-
- return XIo_In32(InstancePtr->RegBaseAddress + XDC_PWB_REG_OFFSET);
-}
+++ /dev/null
-/* $Id: xipif_v1_23_b.c,v 1.1 2002/03/18 23:24:52 linnj Exp $ */
-/******************************************************************************
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
-* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
-* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
-* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
-* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE.
-*
-* (c) Copyright 2002 Xilinx Inc.
-* All rights reserved.
-*
-******************************************************************************/
-/******************************************************************************
-*
-* FILENAME:
-*
-* xipif.c
-*
-* DESCRIPTION:
-*
-* This file contains the implementation of the XIpIf component. The
-* XIpIf component encapsulates the IPIF, which is the standard interface
-* that IP must adhere to when connecting to a bus. The purpose of this
-* component is to encapsulate the IPIF processing such that maintainability
-* is increased. This component does not provide a lot of abstraction from
-* from the details of the IPIF as it is considered a building block for
-* device drivers. A device driver designer must be familiar with the
-* details of the IPIF hardware to use this component.
-*
-* The IPIF hardware provides a building block for all hardware devices such
-* that each device does not need to reimplement these building blocks. The
-* IPIF contains other building blocks, such as FIFOs and DMA channels, which
-* are also common to many devices. These blocks are implemented as separate
-* hardware blocks and instantiated within the IPIF. The primary hardware of
-* the IPIF which is implemented by this software component is the interrupt
-* architecture. Since there are many blocks of a device which may generate
-* interrupts, all the interrupt processing is contained in the common part
-* of the device, the IPIF. This interrupt processing is for the device level
-* only and does not include any processing for the interrupt controller.
-*
-* A device is a mechanism such as an Ethernet MAC. The device is made
-* up of several parts which include an IPIF and the IP. The IPIF contains most
-* of the device infrastructure which is common to all devices, such as
-* interrupt processing, DMA channels, and FIFOs. The infrastructure may also
-* be referred to as IPIF internal blocks since they are part of the IPIF and
-* are separate blocks that can be selected based upon the needs of the device.
-* The IP of the device is the logic that is unique to the device and interfaces
-* to the IPIF of the device.
-*
-* In general, there are two levels of registers within the IPIF. The first
-* level, referred to as the device level, contains registers which are for the
-* entire device. The second level, referred to as the IP level, contains
-* registers which are specific to the IP of the device. The two levels of
-* registers are designed to be hierarchical such that the device level is
-* is a more general register set above the more specific registers of the IP.
-* The IP level of registers provides functionality which is typically common
-* across all devices and allows IP designers to focus on the unique aspects
-* of the IP.
-*
-* The interrupt registers of the IPIF are parameterizable such that the only
-* the number of bits necessary for the device are implemented. The functions
-* of this component do not attempt to validate that the passed in arguments are
-* valid based upon the number of implemented bits. This is necessary to
-* maintain the level of performance required for the common components. Bits
-* of the registers are assigned starting at the least significant bit of the
-* registers.
-*
-* Critical Sections
-*
-* It is the responsibility of the device driver designer to use critical
-* sections as necessary when calling functions of the IPIF. This component
-* does not use critical sections and it does access registers using
-* read-modify-write operations. Calls to IPIF functions from a main thread
-* and from an interrupt context could produce unpredictable behavior such that
-* the caller must provide the appropriate critical sections.
-*
-* Mutual Exclusion
-*
-* The functions of the IPIF are not thread safe such that the caller of all
-* functions is responsible for ensuring mutual exclusion for an IPIF. Mutual
-* exclusion across multiple IPIF components is not necessary.
-*
-* NOTES:
-*
-* None.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.23b jhl 02/27/01 Repartioned to reduce size
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xipif_v1_23_b.h"
-#include "xio.h"
-
-/************************** Constant Definitions *****************************/
-
-/* the following constant is used to generate bit masks for register testing
- * in the self test functions, it defines the starting bit mask that is to be
- * shifted from the LSB to MSB in creating a register test mask
- */
-#define XIIF_V123B_FIRST_BIT_MASK 1UL
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-static XStatus IpIntrSelfTest(u32 RegBaseAddress, u32 IpRegistersWidth);
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XIpIf_SelfTest
-*
-* DESCRIPTION:
-*
-* This function performs a self test on the specified IPIF component. Many
-* of the registers in the IPIF are tested to ensure proper operation. This
-* function is destructive because the IPIF is reset at the start of the test
-* and at the end of the test to ensure predictable results. The IPIF reset
-* also resets the entire device that uses the IPIF. This function exits with
-* all interrupts for the device disabled.
-*
-* ARGUMENTS:
-*
-* InstancePtr points to the XIpIf to operate on.
-*
-* DeviceRegistersWidth contains the number of bits in the device interrupt
-* registers. The hardware is parameterizable such that only the number of bits
-* necessary to support a device are implemented. This value must be between 0
-* and 32 with 0 indicating there are no device interrupt registers used.
-*
-* IpRegistersWidth contains the number of bits in the IP interrupt registers
-* of the device. The hardware is parameterizable such that only the number of
-* bits necessary to support a device are implemented. This value must be
-* between 0 and 32 with 0 indicating there are no IP interrupt registers used.
-*
-* RETURN VALUE:
-*
-* A value of XST_SUCCESS indicates the test was successful with no errors.
-* Any one of the following error values may also be returned.
-*
-* XST_IPIF_RESET_REGISTER_ERROR The value of a register at reset was
-* not valid
-* XST_IPIF_IP_STATUS_ERROR A write to the IP interrupt status
-* register did not read back correctly
-* XST_IPIF_IP_ACK_ERROR One or more bits in the IP interrupt
-* status register did not reset when acked
-* XST_IPIF_IP_ENABLE_ERROR The IP interrupt enable register
-* did not read back correctly based upon
-* what was written to it
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-
-/* the following constant defines the maximum number of bits which may be
- * used in the registers at the device and IP levels, this is based upon the
- * number of bits available in the registers
- */
-#define XIIF_V123B_MAX_REG_BIT_COUNT 32
-
-XStatus
-XIpIfV123b_SelfTest(u32 RegBaseAddress, u8 IpRegistersWidth)
-{
- XStatus Status;
-
- /* assert to verify arguments are valid */
-
- XASSERT_NONVOID(IpRegistersWidth <= XIIF_V123B_MAX_REG_BIT_COUNT);
-
- /* reset the IPIF such that it's in a known state before the test
- * and interrupts are globally disabled
- */
- XIIF_V123B_RESET(RegBaseAddress);
-
- /* perform the self test on the IP interrupt registers, if
- * it is not successful exit with the status
- */
- Status = IpIntrSelfTest(RegBaseAddress, IpRegistersWidth);
- if (Status != XST_SUCCESS) {
- return Status;
- }
-
- /* reset the IPIF such that it's in a known state before exiting test */
-
- XIIF_V123B_RESET(RegBaseAddress);
-
- /* reaching this point means there were no errors, return success */
-
- return XST_SUCCESS;
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* IpIntrSelfTest
-*
-* DESCRIPTION:
-*
-* Perform a self test on the IP interrupt registers of the IPIF. This
-* function modifies registers of the IPIF such that they are not guaranteed
-* to be in the same state when it returns. Any bits in the IP interrupt
-* status register which are set are assumed to be set by default after a reset
-* and are not tested in the test.
-*
-* ARGUMENTS:
-*
-* InstancePtr points to the XIpIf to operate on.
-*
-* IpRegistersWidth contains the number of bits in the IP interrupt registers
-* of the device. The hardware is parameterizable such that only the number of
-* bits necessary to support a device are implemented. This value must be
-* between 0 and 32 with 0 indicating there are no IP interrupt registers used.
-*
-* RETURN VALUE:
-*
-* A status indicating XST_SUCCESS if the test was successful. Otherwise, one
-* of the following values is returned.
-*
-* XST_IPIF_RESET_REGISTER_ERROR The value of a register at reset was
-* not valid
-* XST_IPIF_IP_STATUS_ERROR A write to the IP interrupt status
-* register did not read back correctly
-* XST_IPIF_IP_ACK_ERROR One or more bits in the IP status
-* register did not reset when acked
-* XST_IPIF_IP_ENABLE_ERROR The IP interrupt enable register
-* did not read back correctly based upon
-* what was written to it
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-static XStatus
-IpIntrSelfTest(u32 RegBaseAddress, u32 IpRegistersWidth)
-{
- /* ensure that the IP interrupt interrupt enable register is zero
- * as it should be at reset, the interrupt status is dependent upon the
- * IP such that it's reset value is not known
- */
- if (XIIF_V123B_READ_IIER(RegBaseAddress) != 0) {
- return XST_IPIF_RESET_REGISTER_ERROR;
- }
-
- /* if there are any used IP interrupts, then test all of the interrupt
- * bits in all testable registers
- */
- if (IpRegistersWidth > 0) {
- u32 BitCount;
- u32 IpInterruptMask = XIIF_V123B_FIRST_BIT_MASK;
- u32 Mask = XIIF_V123B_FIRST_BIT_MASK; /* bits assigned MSB to LSB */
- u32 InterruptStatus;
-
- /* generate the register masks to be used for IP register tests, the
- * number of bits supported by the hardware is parameterizable such
- * that only that number of bits are implemented in the registers, the
- * bits are allocated starting at the MSB of the registers
- */
- for (BitCount = 1; BitCount < IpRegistersWidth; BitCount++) {
- Mask = Mask << 1;
- IpInterruptMask |= Mask;
- }
-
- /* get the current IP interrupt status register contents, any bits
- * already set must default to 1 at reset in the device and these
- * bits can't be tested in the following test, remove these bits from
- * the mask that was generated for the test
- */
- InterruptStatus = XIIF_V123B_READ_IISR(RegBaseAddress);
- IpInterruptMask &= ~InterruptStatus;
-
- /* set the bits in the device status register and verify them by reading
- * the register again, all bits of the register are latched
- */
- XIIF_V123B_WRITE_IISR(RegBaseAddress, IpInterruptMask);
- InterruptStatus = XIIF_V123B_READ_IISR(RegBaseAddress);
- if ((InterruptStatus & IpInterruptMask) != IpInterruptMask)
- {
- return XST_IPIF_IP_STATUS_ERROR;
- }
-
- /* test to ensure that the bits set in the IP interrupt status register
- * can be cleared by acknowledging them in the IP interrupt status
- * register then read it again and verify it was cleared
- */
- XIIF_V123B_WRITE_IISR(RegBaseAddress, IpInterruptMask);
- InterruptStatus = XIIF_V123B_READ_IISR(RegBaseAddress);
- if ((InterruptStatus & IpInterruptMask) != 0) {
- return XST_IPIF_IP_ACK_ERROR;
- }
-
- /* set the IP interrupt enable set register and then read the IP
- * interrupt enable register and verify the interrupts were enabled
- */
- XIIF_V123B_WRITE_IIER(RegBaseAddress, IpInterruptMask);
- if (XIIF_V123B_READ_IIER(RegBaseAddress) != IpInterruptMask) {
- return XST_IPIF_IP_ENABLE_ERROR;
- }
-
- /* clear the IP interrupt enable register and then read the
- * IP interrupt enable register and verify the interrupts were disabled
- */
- XIIF_V123B_WRITE_IIER(RegBaseAddress, 0);
- if (XIIF_V123B_READ_IIER(RegBaseAddress) != 0) {
- return XST_IPIF_IP_ENABLE_ERROR;
- }
- }
- return XST_SUCCESS;
-}
+++ /dev/null
-/* $Id: xipif_v1_23_b.h,v 1.1 2002/03/18 23:24:52 linnj Exp $ */
-/******************************************************************************
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
-* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
-* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
-* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
-* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE.
-*
-* (c) Copyright 2002 Xilinx Inc.
-* All rights reserved.
-*
-******************************************************************************/
-/******************************************************************************
-*
-* FILENAME:
-*
-* xipif.h
-*
-* DESCRIPTION:
-*
-* The XIpIf component encapsulates the IPIF, which is the standard interface
-* that IP must adhere to when connecting to a bus. The purpose of this
-* component is to encapsulate the IPIF processing such that maintainability
-* is increased. This component does not provide a lot of abstraction from
-* from the details of the IPIF as it is considered a building block for
-* device drivers. A device driver designer must be familiar with the
-* details of the IPIF hardware to use this component.
-*
-* The IPIF hardware provides a building block for all hardware devices such
-* that each device does not need to reimplement these building blocks. The
-* IPIF contains other building blocks, such as FIFOs and DMA channels, which
-* are also common to many devices. These blocks are implemented as separate
-* hardware blocks and instantiated within the IPIF. The primary hardware of
-* the IPIF which is implemented by this software component is the interrupt
-* architecture. Since there are many blocks of a device which may generate
-* interrupts, all the interrupt processing is contained in the common part
-* of the device, the IPIF. This interrupt processing is for the device level
-* only and does not include any processing for the interrupt controller.
-*
-* A device is a mechanism such as an Ethernet MAC. The device is made
-* up of several parts which include an IPIF and the IP. The IPIF contains most
-* of the device infrastructure which is common to all devices, such as
-* interrupt processing, DMA channels, and FIFOs. The infrastructure may also
-* be referred to as IPIF internal blocks since they are part of the IPIF and
-* are separate blocks that can be selected based upon the needs of the device.
-* The IP of the device is the logic that is unique to the device and interfaces
-* to the IPIF of the device.
-*
-* In general, there are two levels of registers within the IPIF. The first
-* level, referred to as the device level, contains registers which are for the
-* entire device. The second level, referred to as the IP level, contains
-* registers which are specific to the IP of the device. The two levels of
-* registers are designed to be hierarchical such that the device level is
-* is a more general register set above the more specific registers of the IP.
-* The IP level of registers provides functionality which is typically common
-* across all devices and allows IP designers to focus on the unique aspects
-* of the IP.
-*
-* Critical Sections
-*
-* It is the responsibility of the device driver designer to use critical
-* sections as necessary when calling functions of the IPIF. This component
-* does not use critical sections and it does access registers using
-* read-modify-write operations. Calls to IPIF functions from a main thread
-* and from an interrupt context could produce unpredictable behavior such that
-* the caller must provide the appropriate critical sections.
-*
-* Mutual Exclusion
-*
-* The functions of the IPIF are not thread safe such that the caller of all
-* functions is responsible for ensuring mutual exclusion for an IPIF. Mutual
-* exclusion across multiple IPIF components is not necessary.
-*
-* NOTES:
-*
-* None.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.23b jhl 02/27/01 Repartioned to minimize size
-*
-******************************************************************************/
-
-#ifndef XIPIF_H /* prevent circular inclusions */
-#define XIPIF_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-#include "xbasic_types.h"
-#include "xstatus.h"
-#include "xversion.h"
-
-/************************** Constant Definitions *****************************/
-
-/* the following constants define the register offsets for the registers of the
- * IPIF, there are some holes in the memory map for reserved addresses to allow
- * other registers to be added and still match the memory map of the interrupt
- * controller registers
- */
-#define XIIF_V123B_DISR_OFFSET 0UL /* device interrupt status register */
-#define XIIF_V123B_DIPR_OFFSET 4UL /* device interrupt pending register */
-#define XIIF_V123B_DIER_OFFSET 8UL /* device interrupt enable register */
-#define XIIF_V123B_DIIR_OFFSET 24UL /* device interrupt ID register */
-#define XIIF_V123B_DGIER_OFFSET 28UL /* device global interrupt enable reg */
-#define XIIF_V123B_IISR_OFFSET 32UL /* IP interrupt status register */
-#define XIIF_V123B_IIER_OFFSET 40UL /* IP interrupt enable register */
-#define XIIF_V123B_RESETR_OFFSET 64UL /* reset register */
-
-#define XIIF_V123B_RESET_MASK 0xAUL
-
-/* the following constant is used for the device global interrupt enable
- * register, to enable all interrupts for the device, this is the only bit
- * in the register
- */
-#define XIIF_V123B_GINTR_ENABLE_MASK 0x80000000UL
-
-/* the following constants contain the masks to identify each internal IPIF
- * condition in the device registers of the IPIF, interrupts are assigned
- * in the register from LSB to the MSB
- */
-#define XIIF_V123B_ERROR_MASK 1UL /* LSB of the register */
-
-/* The following constants contain interrupt IDs which identify each internal
- * IPIF condition, this value must correlate with the mask constant for the
- * error
- */
-#define XIIF_V123B_ERROR_INTERRUPT_ID 0 /* interrupt bit #, (LSB = 0) */
-#define XIIF_V123B_NO_INTERRUPT_ID 128 /* no interrupts are pending */
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_RESET
-*
-* DESCRIPTION:
-*
-* Reset the IPIF component and hardware. This is a destructive operation that
-* could cause the loss of data since resetting the IPIF of a device also
-* resets the device using the IPIF and any blocks, such as FIFOs or DMA
-* channels, within the IPIF. All registers of the IPIF will contain their
-* reset value when this function returns.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-
-/* the following constant is used in the reset register to cause the IPIF to
- * reset
- */
-#define XIIF_V123B_RESET(RegBaseAddress) \
- XIo_Out32(RegBaseAddress + XIIF_V123B_RESETR_OFFSET, XIIF_V123B_RESET_MASK)
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_WRITE_DISR
-*
-* DESCRIPTION:
-*
-* This function sets the device interrupt status register to the value.
-* This register indicates the status of interrupt sources for a device
-* which contains the IPIF. The status is independent of whether interrupts
-* are enabled and could be used for polling a device at a higher level rather
-* than a more detailed level.
-*
-* Each bit of the register correlates to a specific interrupt source within the
-* device which contains the IPIF. With the exception of some internal IPIF
-* conditions, the contents of this register are not latched but indicate
-* the live status of the interrupt sources within the device. Writing any of
-* the non-latched bits of the register will have no effect on the register.
-*
-* For the latched bits of this register only, setting a bit which is zero
-* within this register causes an interrupt to generated. The device global
-* interrupt enable register and the device interrupt enable register must be set
-* appropriately to allow an interrupt to be passed out of the device. The
-* interrupt is cleared by writing to this register with the bits to be
-* cleared set to a one and all others to zero. This register implements a
-* toggle on write functionality meaning any bits which are set in the value
-* written cause the bits in the register to change to the opposite state.
-*
-* This function writes the specified value to the register such that
-* some bits may be set and others cleared. It is the caller's responsibility
-* to get the value of the register prior to setting the value to prevent a
-* destructive behavior.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* Status contains the value to be written to the interrupt status register of
-* the device. The only bits which can be written are the latched bits which
-* contain the internal IPIF conditions. The following values may be used to
-* set the status register or clear an interrupt condition.
-*
-* XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-#define XIIF_V123B_WRITE_DISR(RegBaseAddress, Status) \
- XIo_Out32((RegBaseAddress) + XIIF_V123B_DISR_OFFSET, (Status))
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_READ_DISR
-*
-* DESCRIPTION:
-*
-* This function gets the device interrupt status register contents.
-* This register indicates the status of interrupt sources for a device
-* which contains the IPIF. The status is independent of whether interrupts
-* are enabled and could be used for polling a device at a higher level.
-*
-* Each bit of the register correlates to a specific interrupt source within the
-* device which contains the IPIF. With the exception of some internal IPIF
-* conditions, the contents of this register are not latched but indicate
-* the live status of the interrupt sources within the device.
-*
-* For only the latched bits of this register, the interrupt may be cleared by
-* writing to these bits in the status register.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* RETURN VALUE:
-*
-* A status which contains the value read from the interrupt status register of
-* the device. The bit definitions are specific to the device with
-* the exception of the latched internal IPIF condition bits. The following
-* values may be used to detect internal IPIF conditions in the status.
-*
-* XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-#define XIIF_V123B_READ_DISR(RegBaseAddress) \
- XIo_In32((RegBaseAddress) + XIIF_V123B_DISR_OFFSET)
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_WRITE_DIER
-*
-* DESCRIPTION:
-*
-* This function sets the device interrupt enable register contents.
-* This register controls which interrupt sources of the device are allowed to
-* generate an interrupt. The device global interrupt enable register must also
-* be set appropriately for an interrupt to be passed out of the device.
-*
-* Each bit of the register correlates to a specific interrupt source within the
-* device which contains the IPIF. Setting a bit in this register enables that
-* interrupt source to generate an interrupt. Clearing a bit in this register
-* disables interrupt generation for that interrupt source.
-*
-* This function writes only the specified value to the register such that
-* some interrupts source may be enabled and others disabled. It is the
-* caller's responsibility to get the value of the interrupt enable register
-* prior to setting the value to prevent an destructive behavior.
-*
-* An interrupt source may not be enabled to generate an interrupt, but can
-* still be polled in the interrupt status register.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* Enable contains the value to be written to the interrupt enable register
-* of the device. The bit definitions are specific to the device with
-* the exception of the internal IPIF conditions. The following
-* values may be used to enable the internal IPIF conditions interrupts.
-*
-* XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* Signature: u32 XIIF_V123B_WRITE_DIER(u32 RegBaseAddress,
-* u32 Enable)
-*
-******************************************************************************/
-#define XIIF_V123B_WRITE_DIER(RegBaseAddress, Enable) \
- XIo_Out32((RegBaseAddress) + XIIF_V123B_DIER_OFFSET, (Enable))
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_READ_DIER
-*
-* DESCRIPTION:
-*
-* This function gets the device interrupt enable register contents.
-* This register controls which interrupt sources of the device
-* are allowed to generate an interrupt. The device global interrupt enable
-* register and the device interrupt enable register must also be set
-* appropriately for an interrupt to be passed out of the device.
-*
-* Each bit of the register correlates to a specific interrupt source within the
-* device which contains the IPIF. Setting a bit in this register enables that
-* interrupt source to generate an interrupt if the global enable is set
-* appropriately. Clearing a bit in this register disables interrupt generation
-* for that interrupt source regardless of the global interrupt enable.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* RETURN VALUE:
-*
-* The value read from the interrupt enable register of the device. The bit
-* definitions are specific to the device with the exception of the internal
-* IPIF conditions. The following values may be used to determine from the
-* value if the internal IPIF conditions interrupts are enabled.
-*
-* XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-#define XIIF_V123B_READ_DIER(RegBaseAddress) \
- XIo_In32((RegBaseAddress) + XIIF_V123B_DIER_OFFSET)
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_READ_DIPR
-*
-* DESCRIPTION:
-*
-* This function gets the device interrupt pending register contents.
-* This register indicates the pending interrupt sources, those that are waiting
-* to be serviced by the software, for a device which contains the IPIF.
-* An interrupt must be enabled in the interrupt enable register of the IPIF to
-* be pending.
-*
-* Each bit of the register correlates to a specific interrupt source within the
-* the device which contains the IPIF. With the exception of some internal IPIF
-* conditions, the contents of this register are not latched since the condition
-* is latched in the IP interrupt status register, by an internal block of the
-* IPIF such as a FIFO or DMA channel, or by the IP of the device. This register
-* is read only and is not latched, but it is necessary to acknowledge (clear)
-* the interrupt condition by performing the appropriate processing for the IP
-* or block within the IPIF.
-*
-* This register can be thought of as the contents of the interrupt status
-* register ANDed with the contents of the interrupt enable register.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* RETURN VALUE:
-*
-* The value read from the interrupt pending register of the device. The bit
-* definitions are specific to the device with the exception of the latched
-* internal IPIF condition bits. The following values may be used to detect
-* internal IPIF conditions in the value.
-*
-* XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-#define XIIF_V123B_READ_DIPR(RegBaseAddress) \
- XIo_In32((RegBaseAddress) + XIIF_V123B_DIPR_OFFSET)
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_READ_DIIR
-*
-* DESCRIPTION:
-*
-* This function gets the device interrupt ID for the highest priority interrupt
-* which is pending from the interrupt ID register. This function provides
-* priority resolution such that faster interrupt processing is possible.
-* Without priority resolution, it is necessary for the software to read the
-* interrupt pending register and then check each interrupt source to determine
-* if an interrupt is pending. Priority resolution becomes more important as the
-* number of interrupt sources becomes larger.
-*
-* Interrupt priorities are based upon the bit position of the interrupt in the
-* interrupt pending register with bit 0 being the highest priority. The
-* interrupt ID is the priority of the interrupt, 0 - 31, with 0 being the
-* highest priority. The interrupt ID register is live rather than latched such
-* that multiple calls to this function may not yield the same results. A
-* special value, outside of the interrupt priority range of 0 - 31, is
-* contained in the register which indicates that no interrupt is pending. This
-* may be useful for allowing software to continue processing interrupts in a
-* loop until there are no longer any interrupts pending.
-*
-* The interrupt ID is designed to allow a function pointer table to be used
-* in the software such that the interrupt ID is used as an index into that
-* table. The function pointer table could contain an instance pointer, such
-* as to DMA channel, and a function pointer to the function which handles
-* that interrupt. This design requires the interrupt processing of the device
-* driver to be partitioned into smaller more granular pieces based upon
-* hardware used by the device, such as DMA channels and FIFOs.
-*
-* It is not mandatory that this function be used by the device driver software.
-* It may choose to read the pending register and resolve the pending interrupt
-* priorities on it's own.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* RETURN VALUE:
-*
-* An interrupt ID, 0 - 31, which identifies the highest priority interrupt
-* which is pending. A value of XIIF_NO_INTERRUPT_ID indicates that there is
-* no interrupt pending. The following values may be used to identify the
-* interrupt ID for the internal IPIF interrupts.
-*
-* XIIF_V123B_ERROR_INTERRUPT_ID Indicates a device error in the IPIF
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-#define XIIF_V123B_READ_DIIR(RegBaseAddress) \
- XIo_In32((RegBaseAddress) + XIIF_V123B_DIIR_OFFSET)
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_GLOBAL_INTR_DISABLE
-*
-* DESCRIPTION:
-*
-* This function disables all interrupts for the device by writing to the global
-* interrupt enable register. This register provides the ability to disable
-* interrupts without any modifications to the interrupt enable register such
-* that it is minimal effort to restore the interrupts to the previous enabled
-* state. The corresponding function, XIpIf_GlobalIntrEnable, is provided to
-* restore the interrupts to the previous enabled state. This function is
-* designed to be used in critical sections of device drivers such that it is
-* not necessary to disable other device interrupts.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-#define XIIF_V123B_GINTR_DISABLE(RegBaseAddress) \
- XIo_Out32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET, 0)
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_GINTR_ENABLE
-*
-* DESCRIPTION:
-*
-* This function writes to the global interrupt enable register to enable
-* interrupts from the device. This register provides the ability to enable
-* interrupts without any modifications to the interrupt enable register such
-* that it is minimal effort to restore the interrupts to the previous enabled
-* state. This function does not enable individual interrupts as the interrupt
-* enable register must be set appropriately. This function is designed to be
-* used in critical sections of device drivers such that it is not necessary to
-* disable other device interrupts.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-#define XIIF_V123B_GINTR_ENABLE(RegBaseAddress) \
- XIo_Out32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET, \
- XIIF_V123B_GINTR_ENABLE_MASK)
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_IS_GINTR_ENABLED
-*
-* DESCRIPTION:
-*
-* This function determines if interrupts are enabled at the global level by
-* reading the gloabl interrupt register. This register provides the ability to
-* disable interrupts without any modifications to the interrupt enable register
-* such that it is minimal effort to restore the interrupts to the previous
-* enabled state.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* RETURN VALUE:
-*
-* XTRUE if interrupts are enabled for the IPIF, XFALSE otherwise.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-#define XIIF_V123B_IS_GINTR_ENABLED(RegBaseAddress) \
- (XIo_In32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET) == \
- XIIF_V123B_GINTR_ENABLE_MASK)
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_WRITE_IISR
-*
-* DESCRIPTION:
-*
-* This function sets the IP interrupt status register to the specified value.
-* This register indicates the status of interrupt sources for the IP of the
-* device. The IP is defined as the part of the device that connects to the
-* IPIF. The status is independent of whether interrupts are enabled such that
-* the status register may also be polled when interrupts are not enabled.
-*
-* Each bit of the register correlates to a specific interrupt source within the
-* IP. All bits of this register are latched. Setting a bit which is zero
-* within this register causes an interrupt to be generated. The device global
-* interrupt enable register and the device interrupt enable register must be set
-* appropriately to allow an interrupt to be passed out of the device. The
-* interrupt is cleared by writing to this register with the bits to be
-* cleared set to a one and all others to zero. This register implements a
-* toggle on write functionality meaning any bits which are set in the value
-* written cause the bits in the register to change to the opposite state.
-*
-* This function writes only the specified value to the register such that
-* some status bits may be set and others cleared. It is the caller's
-* responsibility to get the value of the register prior to setting the value
-* to prevent an destructive behavior.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* Status contains the value to be written to the IP interrupt status
-* register. The bit definitions are specific to the device IP.
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-#define XIIF_V123B_WRITE_IISR(RegBaseAddress, Status) \
- XIo_Out32((RegBaseAddress) + XIIF_V123B_IISR_OFFSET, (Status))
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_READ_IISR
-*
-* DESCRIPTION:
-*
-* This function gets the contents of the IP interrupt status register.
-* This register indicates the status of interrupt sources for the IP of the
-* device. The IP is defined as the part of the device that connects to the
-* IPIF. The status is independent of whether interrupts are enabled such
-* that the status register may also be polled when interrupts are not enabled.
-*
-* Each bit of the register correlates to a specific interrupt source within the
-* device. All bits of this register are latched. Writing a 1 to a bit within
-* this register causes an interrupt to be generated if enabled in the interrupt
-* enable register and the global interrupt enable is set. Since the status is
-* latched, each status bit must be acknowledged in order for the bit in the
-* status register to be updated. Each bit can be acknowledged by writing a
-* 0 to the bit in the status register.
-
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* RETURN VALUE:
-*
-* A status which contains the value read from the IP interrupt status register.
-* The bit definitions are specific to the device IP.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-#define XIIF_V123B_READ_IISR(RegBaseAddress) \
- XIo_In32((RegBaseAddress) + XIIF_V123B_IISR_OFFSET)
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_WRITE_IIER
-*
-* DESCRIPTION:
-*
-* This function sets the IP interrupt enable register contents. This register
-* controls which interrupt sources of the IP are allowed to generate an
-* interrupt. The global interrupt enable register and the device interrupt
-* enable register must also be set appropriately for an interrupt to be
-* passed out of the device containing the IPIF and the IP.
-*
-* Each bit of the register correlates to a specific interrupt source within the
-* IP. Setting a bit in this register enables the interrupt source to generate
-* an interrupt. Clearing a bit in this register disables interrupt generation
-* for that interrupt source.
-*
-* This function writes only the specified value to the register such that
-* some interrupt sources may be enabled and others disabled. It is the
-* caller's responsibility to get the value of the interrupt enable register
-* prior to setting the value to prevent an destructive behavior.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* Enable contains the value to be written to the IP interrupt enable register.
-* The bit definitions are specific to the device IP.
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-#define XIIF_V123B_WRITE_IIER(RegBaseAddress, Enable) \
- XIo_Out32((RegBaseAddress) + XIIF_V123B_IIER_OFFSET, (Enable))
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_READ_IIER
-*
-* DESCRIPTION:
-*
-*
-* This function gets the IP interrupt enable register contents. This register
-* controls which interrupt sources of the IP are allowed to generate an
-* interrupt. The global interrupt enable register and the device interrupt
-* enable register must also be set appropriately for an interrupt to be
-* passed out of the device containing the IPIF and the IP.
-*
-* Each bit of the register correlates to a specific interrupt source within the
-* IP. Setting a bit in this register enables the interrupt source to generate
-* an interrupt. Clearing a bit in this register disables interrupt generation
-* for that interrupt source.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* RETURN VALUE:
-*
-* The contents read from the IP interrupt enable register. The bit definitions
-* are specific to the device IP.
-*
-* NOTES:
-*
-* Signature: u32 XIIF_V123B_READ_IIER(u32 RegBaseAddress)
-*
-******************************************************************************/
-#define XIIF_V123B_READ_IIER(RegBaseAddress) \
- XIo_In32((RegBaseAddress) + XIIF_V123B_IIER_OFFSET)
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Initialization Functions
- */
-XStatus XIpIfV123b_SelfTest(u32 RegBaseAddress, u8 IpRegistersWidth);
-
-#endif /* end of protection macro */
+++ /dev/null
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-/*****************************************************************************/
-/*
-*
-* @file xpacket_fifo_v1_00_b.c
-*
-* Contains functions for the XPacketFifoV100b component. See xpacket_fifo_v1_00_b.h
-* for more information about the component.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b rpm 03/26/02 First release
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xbasic_types.h"
-#include "xio.h"
-#include "xstatus.h"
-#include "xpacket_fifo_v1_00_b.h"
-
-/************************** Constant Definitions *****************************/
-
-/* width of a FIFO word */
-
-#define XPF_FIFO_WIDTH_BYTE_COUNT 4UL
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************* Variable Definitions ******************************/
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/*
-*
-* This function initializes a packet FIFO. Initialization resets the
-* FIFO such that it's empty and ready to use.
-*
-* @param InstancePtr contains a pointer to the FIFO to operate on.
-* @param RegBaseAddress contains the base address of the registers for
-* the packet FIFO.
-* @param DataBaseAddress contains the base address of the data for
-* the packet FIFO.
-*
-* @return
-*
-* Always returns XST_SUCCESS.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-XStatus
-XPacketFifoV100b_Initialize(XPacketFifoV100b * InstancePtr,
- u32 RegBaseAddress, u32 DataBaseAddress)
-{
- /* assert to verify input argument are valid */
-
- XASSERT_NONVOID(InstancePtr != NULL);
-
- /* initialize the component variables to the specified state */
-
- InstancePtr->RegBaseAddress = RegBaseAddress;
- InstancePtr->DataBaseAddress = DataBaseAddress;
- InstancePtr->IsReady = XCOMPONENT_IS_READY;
-
- /* reset the FIFO such that it's empty and ready to use and indicate the
- * initialization was successful, note that the is ready variable must be
- * set prior to calling the reset function to prevent an assert
- */
- XPF_V100B_RESET(InstancePtr);
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/*
-*
-* This function performs a self-test on the specified packet FIFO. The self
-* test resets the FIFO and reads a register to determine if it is the correct
-* reset value. This test is destructive in that any data in the FIFO will
-* be lost.
-*
-* @param InstancePtr is a pointer to the packet FIFO to be operated on.
-*
-* @param FifoType specifies the type of FIFO, read or write, for the self test.
-* The FIFO type is specified by the values XPF_READ_FIFO_TYPE or
-* XPF_WRITE_FIFO_TYPE.
-*
-* @return
-*
-* XST_SUCCESS is returned if the selftest is successful, or
-* XST_PFIFO_BAD_REG_VALUE indicating that the value readback from the
-* occupancy/vacancy count register after a reset does not match the
-* specified reset value.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-XStatus
-XPacketFifoV100b_SelfTest(XPacketFifoV100b * InstancePtr, u32 FifoType)
-{
- u32 Register;
-
- /* assert to verify valid input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID((FifoType == XPF_READ_FIFO_TYPE) ||
- (FifoType == XPF_WRITE_FIFO_TYPE));
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* reset the fifo and then check to make sure the occupancy/vacancy
- * register contents are correct for a reset condition
- */
- XPF_V100B_RESET(InstancePtr);
-
- Register = XIo_In32(InstancePtr->RegBaseAddress +
- XPF_COUNT_STATUS_REG_OFFSET);
-
- /* check the value of the register to ensure that it's correct for the
- * specified FIFO type since both FIFO types reset to empty, but a bit
- * in the register changes definition based upon FIFO type
- */
-
- if (FifoType == XPF_READ_FIFO_TYPE) {
- /* check the regiser value for a read FIFO which should be empty */
-
- if (Register != XPF_EMPTY_FULL_MASK) {
- return XST_PFIFO_BAD_REG_VALUE;
- }
- } else {
- /* check the register value for a write FIFO which should not be full
- * on reset
- */
- if ((Register & XPF_EMPTY_FULL_MASK) != 0) {
- return XST_PFIFO_BAD_REG_VALUE;
- }
- }
-
- /* the test was successful */
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/*
-*
-* Read data from a FIFO and puts it into a specified buffer. The packet FIFO is
-* currently 32 bits wide such that an input buffer which is a series of bytes
-* is filled from the FIFO a word at a time. If the requested byte count is not
-* a multiple of 32 bit words, it is necessary for this function to format the
-* remaining 32 bit word from the FIFO into a series of bytes in the buffer.
-* There may be up to 3 extra bytes which must be extracted from the last word
-* of the FIFO and put into the buffer.
-*
-* @param InstancePtr contains a pointer to the FIFO to operate on.
-* @param BufferPtr points to the memory buffer to write the data into. This
-* buffer must be 32 bit aligned or an alignment exception could be
-* generated. Since this buffer is a byte buffer, the data is assumed to
-* be endian independent.
-* @param ByteCount contains the number of bytes to read from the FIFO. This
-* number of bytes must be present in the FIFO or an error will be
-* returned.
-*
-* @return
-*
-* XST_SUCCESS indicates the operation was successful. If the number of
-* bytes specified by the byte count is not present in the FIFO
-* XST_PFIFO_LACK_OF_DATA is returned.
-*
-* If the function was successful, the specified buffer is modified to contain
-* the bytes which were removed from the FIFO.
-*
-* @note
-*
-* Note that the exact number of bytes which are present in the FIFO is
-* not known by this function. It can only check for a number of 32 bit
-* words such that if the byte count specified is incorrect, but is still
-* possible based on the number of words in the FIFO, up to 3 garbage bytes
-* may be present at the end of the buffer.
-* <br><br>
-* This function assumes that if the device consuming data from the FIFO is
-* a byte device, the order of the bytes to be consumed is from the most
-* significant byte to the least significant byte of a 32 bit word removed
-* from the FIFO.
-*
-******************************************************************************/
-XStatus
-XPacketFifoV100b_Read(XPacketFifoV100b * InstancePtr,
- u8 * BufferPtr, u32 ByteCount)
-{
- u32 FifoCount;
- u32 WordCount;
- u32 ExtraByteCount;
- u32 *WordBuffer = (u32 *) BufferPtr;
-
- /* assert to verify valid input arguments including 32 bit alignment of
- * the buffer pointer
- */
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(BufferPtr != NULL);
- XASSERT_NONVOID(((u32) BufferPtr &
- (XPF_FIFO_WIDTH_BYTE_COUNT - 1)) == 0);
- XASSERT_NONVOID(ByteCount != 0);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* get the count of how many 32 bit words are in the FIFO, if there aren't
- * enought words to satisfy the request, return an error
- */
-
- FifoCount = XIo_In32(InstancePtr->RegBaseAddress +
- XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK;
-
- if ((FifoCount * XPF_FIFO_WIDTH_BYTE_COUNT) < ByteCount) {
- return XST_PFIFO_LACK_OF_DATA;
- }
-
- /* calculate the number of words to read from the FIFO before the word
- * containing the extra bytes, and calculate the number of extra bytes
- * the extra bytes are defined as those at the end of the buffer when
- * the buffer does not end on a 32 bit boundary
- */
- WordCount = ByteCount / XPF_FIFO_WIDTH_BYTE_COUNT;
- ExtraByteCount = ByteCount % XPF_FIFO_WIDTH_BYTE_COUNT;
-
- /* Read the 32 bit words from the FIFO for all the buffer except the
- * last word which contains the extra bytes, the following code assumes
- * that the buffer is 32 bit aligned, otherwise an alignment exception could
- * be generated
- */
- for (FifoCount = 0; FifoCount < WordCount; FifoCount++) {
- WordBuffer[FifoCount] = XIo_In32(InstancePtr->DataBaseAddress);
- }
-
- /* if there are extra bytes to handle, read the last word from the FIFO
- * and insert the extra bytes into the buffer
- */
- if (ExtraByteCount > 0) {
- u32 LastWord;
- u8 *ExtraBytesBuffer = (u8 *) (WordBuffer + WordCount);
-
- /* get the last word from the FIFO for the extra bytes */
-
- LastWord = XIo_In32(InstancePtr->DataBaseAddress);
-
- /* one extra byte in the last word, put the byte into the next location
- * of the buffer, bytes in a word of the FIFO are ordered from most
- * significant byte to least
- */
- if (ExtraByteCount == 1) {
- ExtraBytesBuffer[0] = (u8) (LastWord >> 24);
- }
-
- /* two extra bytes in the last word, put each byte into the next two
- * locations of the buffer
- */
- else if (ExtraByteCount == 2) {
- ExtraBytesBuffer[0] = (u8) (LastWord >> 24);
- ExtraBytesBuffer[1] = (u8) (LastWord >> 16);
- }
- /* three extra bytes in the last word, put each byte into the next three
- * locations of the buffer
- */
- else if (ExtraByteCount == 3) {
- ExtraBytesBuffer[0] = (u8) (LastWord >> 24);
- ExtraBytesBuffer[1] = (u8) (LastWord >> 16);
- ExtraBytesBuffer[2] = (u8) (LastWord >> 8);
- }
- }
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/*
-*
-* Write data into a packet FIFO. The packet FIFO is currently 32 bits wide
-* such that an input buffer which is a series of bytes must be written into the
-* FIFO a word at a time. If the buffer is not a multiple of 32 bit words, it is
-* necessary for this function to format the remaining bytes into a single 32
-* bit word to be inserted into the FIFO. This is necessary to avoid any
-* accesses past the end of the buffer.
-*
-* @param InstancePtr contains a pointer to the FIFO to operate on.
-* @param BufferPtr points to the memory buffer that data is to be read from
-* and written into the FIFO. Since this buffer is a byte buffer, the data
-* is assumed to be endian independent. This buffer must be 32 bit aligned
-* or an alignment exception could be generated.
-* @param ByteCount contains the number of bytes to read from the buffer and to
-* write to the FIFO.
-*
-* @return
-*
-* XST_SUCCESS is returned if the operation succeeded. If there is not enough
-* room in the FIFO to hold the specified bytes, XST_PFIFO_NO_ROOM is
-* returned.
-*
-* @note
-*
-* This function assumes that if the device inserting data into the FIFO is
-* a byte device, the order of the bytes in each 32 bit word is from the most
-* significant byte to the least significant byte.
-*
-******************************************************************************/
-XStatus
-XPacketFifoV100b_Write(XPacketFifoV100b * InstancePtr,
- u8 * BufferPtr, u32 ByteCount)
-{
- u32 FifoCount;
- u32 WordCount;
- u32 ExtraByteCount;
- u32 *WordBuffer = (u32 *) BufferPtr;
-
- /* assert to verify valid input arguments including 32 bit alignment of
- * the buffer pointer
- */
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(BufferPtr != NULL);
- XASSERT_NONVOID(((u32) BufferPtr &
- (XPF_FIFO_WIDTH_BYTE_COUNT - 1)) == 0);
- XASSERT_NONVOID(ByteCount != 0);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* get the count of how many words may be inserted into the FIFO */
-
- FifoCount = XIo_In32(InstancePtr->RegBaseAddress +
- XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK;
-
- /* Calculate the number of 32 bit words required to insert the specified
- * number of bytes in the FIFO and determine the number of extra bytes
- * if the buffer length is not a multiple of 32 bit words
- */
-
- WordCount = ByteCount / XPF_FIFO_WIDTH_BYTE_COUNT;
- ExtraByteCount = ByteCount % XPF_FIFO_WIDTH_BYTE_COUNT;
-
- /* take into account the extra bytes in the total word count */
-
- if (ExtraByteCount > 0) {
- WordCount++;
- }
-
- /* if there's not enough room in the FIFO to hold the specified
- * number of bytes, then indicate an error,
- */
- if (FifoCount < WordCount) {
- return XST_PFIFO_NO_ROOM;
- }
-
- /* readjust the word count to not take into account the extra bytes */
-
- if (ExtraByteCount > 0) {
- WordCount--;
- }
-
- /* Write all the bytes of the buffer which can be written as 32 bit
- * words into the FIFO, waiting to handle the extra bytes seperately
- */
- for (FifoCount = 0; FifoCount < WordCount; FifoCount++) {
- XIo_Out32(InstancePtr->DataBaseAddress, WordBuffer[FifoCount]);
- }
-
- /* if there are extra bytes to handle, extract them from the buffer
- * and create a 32 bit word and write it to the FIFO
- */
- if (ExtraByteCount > 0) {
- u32 LastWord = 0;
- u8 *ExtraBytesBuffer = (u8 *) (WordBuffer + WordCount);
-
- /* one extra byte in the buffer, put the byte into the last word
- * to be inserted into the FIFO, perform this processing inline rather
- * than in a loop to help performance
- */
- if (ExtraByteCount == 1) {
- LastWord = ExtraBytesBuffer[0] << 24;
- }
-
- /* two extra bytes in the buffer, put each byte into the last word
- * to be inserted into the FIFO
- */
- else if (ExtraByteCount == 2) {
- LastWord = ExtraBytesBuffer[0] << 24 |
- ExtraBytesBuffer[1] << 16;
- }
-
- /* three extra bytes in the buffer, put each byte into the last word
- * to be inserted into the FIFO
- */
- else if (ExtraByteCount == 3) {
- LastWord = ExtraBytesBuffer[0] << 24 |
- ExtraBytesBuffer[1] << 16 |
- ExtraBytesBuffer[2] << 8;
- }
-
- /* write the last 32 bit word to the FIFO and return with no errors */
-
- XIo_Out32(InstancePtr->DataBaseAddress, LastWord);
- }
-
- return XST_SUCCESS;
-}
+++ /dev/null
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-/*****************************************************************************/
-/*
-*
-* @file xpacket_fifo_v1_00_b.h
-*
-* This component is a common component because it's primary purpose is to
-* prevent code duplication in drivers. A driver which must handle a packet
-* FIFO uses this component rather than directly manipulating a packet FIFO.
-*
-* A FIFO is a device which has dual port memory such that one user may be
-* inserting data into the FIFO while another is consuming data from the FIFO.
-* A packet FIFO is designed for use with packet protocols such as Ethernet and
-* ATM. It is typically only used with devices when DMA and/or Scatter Gather
-* is used. It differs from a nonpacket FIFO in that it does not provide any
-* interrupts for thresholds of the FIFO such that it is less useful without
-* DMA.
-*
-* @note
-*
-* This component has the capability to generate an interrupt when an error
-* condition occurs. It is the user's responsibility to provide the interrupt
-* processing to handle the interrupt. This component provides the ability to
-* determine if that interrupt is active, a deadlock condition, and the ability
-* to reset the FIFO to clear the condition. In this condition, the device which
-* is using the FIFO should also be reset to prevent other problems. This error
-* condition could occur as a normal part of operation if the size of the FIFO
-* is not setup correctly. See the hardware IP specification for more details.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b rpm 03/26/02 First release
-* </pre>
-*
-*****************************************************************************/
-#ifndef XPACKET_FIFO_H /* prevent circular inclusions */
-#define XPACKET_FIFO_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xbasic_types.h"
-#include "xstatus.h"
-
-/************************** Constant Definitions *****************************/
-
-/*
- * These constants specify the FIFO type and are mutually exclusive
- */
-#define XPF_READ_FIFO_TYPE 0 /* a read FIFO */
-#define XPF_WRITE_FIFO_TYPE 1 /* a write FIFO */
-
-/*
- * These constants define the offsets to each of the registers from the
- * register base address, each of the constants are a number of bytes
- */
-#define XPF_RESET_REG_OFFSET 0UL
-#define XPF_MODULE_INFO_REG_OFFSET 0UL
-#define XPF_COUNT_STATUS_REG_OFFSET 4UL
-
-/*
- * This constant is used with the Reset Register
- */
-#define XPF_RESET_FIFO_MASK 0x0000000A
-
-/*
- * These constants are used with the Occupancy/Vacancy Count Register. This
- * register also contains FIFO status
- */
-#define XPF_COUNT_MASK 0x0000FFFF
-#define XPF_DEADLOCK_MASK 0x20000000
-#define XPF_ALMOST_EMPTY_FULL_MASK 0x40000000
-#define XPF_EMPTY_FULL_MASK 0x80000000
-
-/**************************** Type Definitions *******************************/
-
-/*
- * The XPacketFifo driver instance data. The driver is required to allocate a
- * variable of this type for every packet FIFO in the device.
- */
-typedef struct {
- u32 RegBaseAddress; /* Base address of registers */
- u32 IsReady; /* Device is initialized and ready */
- u32 DataBaseAddress; /* Base address of data for FIFOs */
-} XPacketFifoV100b;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/*
-*
-* Reset the specified packet FIFO. Resetting a FIFO will cause any data
-* contained in the FIFO to be lost.
-*
-* @param InstancePtr contains a pointer to the FIFO to operate on.
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* Signature: void XPF_V100B_RESET(XPacketFifoV100b *InstancePtr)
-*
-******************************************************************************/
-#define XPF_V100B_RESET(InstancePtr) \
- XIo_Out32((InstancePtr)->RegBaseAddress + XPF_RESET_REG_OFFSET, XPF_RESET_FIFO_MASK);
-
-/*****************************************************************************/
-/*
-*
-* Get the occupancy count for a read packet FIFO and the vacancy count for a
-* write packet FIFO. These counts indicate the number of 32-bit words
-* contained (occupancy) in the FIFO or the number of 32-bit words available
-* to write (vacancy) in the FIFO.
-*
-* @param InstancePtr contains a pointer to the FIFO to operate on.
-*
-* @return
-*
-* The occupancy or vacancy count for the specified packet FIFO.
-*
-* @note
-*
-* Signature: u32 XPF_V100B_GET_COUNT(XPacketFifoV100b *InstancePtr)
-*
-******************************************************************************/
-#define XPF_V100B_GET_COUNT(InstancePtr) \
- (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
- XPF_COUNT_MASK)
-
-/*****************************************************************************/
-/*
-*
-* Determine if the specified packet FIFO is almost empty. Almost empty is
-* defined for a read FIFO when there is only one data word in the FIFO.
-*
-* @param InstancePtr contains a pointer to the FIFO to operate on.
-*
-* @return
-*
-* TRUE if the packet FIFO is almost empty, FALSE otherwise.
-*
-* @note
-*
-* Signature: u32 XPF_V100B_IS_ALMOST_EMPTY(XPacketFifoV100b *InstancePtr)
-*
-******************************************************************************/
-#define XPF_V100B_IS_ALMOST_EMPTY(InstancePtr) \
- (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
- XPF_ALMOST_EMPTY_FULL_MASK)
-
-/*****************************************************************************/
-/*
-*
-* Determine if the specified packet FIFO is almost full. Almost full is
-* defined for a write FIFO when there is only one available data word in the
-* FIFO.
-*
-* @param InstancePtr contains a pointer to the FIFO to operate on.
-*
-* @return
-*
-* TRUE if the packet FIFO is almost full, FALSE otherwise.
-*
-* @note
-*
-* Signature: u32 XPF_V100B_IS_ALMOST_FULL(XPacketFifoV100b *InstancePtr)
-*
-******************************************************************************/
-#define XPF_V100B_IS_ALMOST_FULL(InstancePtr) \
- (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
- XPF_ALMOST_EMPTY_FULL_MASK)
-
-/*****************************************************************************/
-/*
-*
-* Determine if the specified packet FIFO is empty. This applies only to a
-* read FIFO.
-*
-* @param InstancePtr contains a pointer to the FIFO to operate on.
-*
-* @return
-*
-* TRUE if the packet FIFO is empty, FALSE otherwise.
-*
-* @note
-*
-* Signature: u32 XPF_V100B_IS_EMPTY(XPacketFifoV100b *InstancePtr)
-*
-******************************************************************************/
-#define XPF_V100B_IS_EMPTY(InstancePtr) \
- (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
- XPF_EMPTY_FULL_MASK)
-
-/*****************************************************************************/
-/*
-*
-* Determine if the specified packet FIFO is full. This applies only to a
-* write FIFO.
-*
-* @param InstancePtr contains a pointer to the FIFO to operate on.
-*
-* @return
-*
-* TRUE if the packet FIFO is full, FALSE otherwise.
-*
-* @note
-*
-* Signature: u32 XPF_V100B_IS_FULL(XPacketFifoV100b *InstancePtr)
-*
-******************************************************************************/
-#define XPF_V100B_IS_FULL(InstancePtr) \
- (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
- XPF_EMPTY_FULL_MASK)
-
-/*****************************************************************************/
-/*
-*
-* Determine if the specified packet FIFO is deadlocked. This condition occurs
-* when the FIFO is full and empty at the same time and is caused by a packet
-* being written to the FIFO which exceeds the total data capacity of the FIFO.
-* It occurs because of the mark/restore features of the packet FIFO which allow
-* retransmission of a packet. The software should reset the FIFO and any devices
-* using the FIFO when this condition occurs.
-*
-* @param InstancePtr contains a pointer to the FIFO to operate on.
-*
-* @return
-*
-* TRUE if the packet FIFO is deadlocked, FALSE otherwise.
-*
-* @note
-*
-* This component has the capability to generate an interrupt when an error
-* condition occurs. It is the user's responsibility to provide the interrupt
-* processing to handle the interrupt. This function provides the ability to
-* determine if a deadlock condition, and the ability to reset the FIFO to
-* clear the condition.
-*
-* In this condition, the device which is using the FIFO should also be reset
-* to prevent other problems. This error condition could occur as a normal part
-* of operation if the size of the FIFO is not setup correctly.
-*
-* Signature: u32 XPF_V100B_IS_DEADLOCKED(XPacketFifoV100b *InstancePtr)
-*
-******************************************************************************/
-#define XPF_V100B_IS_DEADLOCKED(InstancePtr) \
- (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
- XPF_DEADLOCK_MASK)
-
-/************************** Function Prototypes ******************************/
-
-/* Standard functions */
-
-XStatus XPacketFifoV100b_Initialize(XPacketFifoV100b * InstancePtr,
- u32 RegBaseAddress, u32 DataBaseAddress);
-XStatus XPacketFifoV100b_SelfTest(XPacketFifoV100b * InstancePtr, u32 FifoType);
-
-/* Data functions */
-
-XStatus XPacketFifoV100b_Read(XPacketFifoV100b * InstancePtr,
- u8 * ReadBufferPtr, u32 ByteCount);
-XStatus XPacketFifoV100b_Write(XPacketFifoV100b * InstancePtr,
- u8 * WriteBufferPtr, u32 ByteCount);
-
-#endif /* end of protection macro */
+++ /dev/null
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xstatus.h
-*
-* This file contains Xilinx software status codes. Status codes have their
-* own data type called XStatus. These codes are used throughout the Xilinx
-* device drivers.
-*
-******************************************************************************/
-
-#ifndef XSTATUS_H /* prevent circular inclusions */
-#define XSTATUS_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xbasic_types.h"
-
-/************************** Constant Definitions *****************************/
-
-/*********************** Common statuses 0 - 500 *****************************/
-
-#define XST_SUCCESS 0L
-#define XST_FAILURE 1L
-#define XST_DEVICE_NOT_FOUND 2L
-#define XST_DEVICE_BLOCK_NOT_FOUND 3L
-#define XST_INVALID_VERSION 4L
-#define XST_DEVICE_IS_STARTED 5L
-#define XST_DEVICE_IS_STOPPED 6L
-#define XST_FIFO_ERROR 7L /* an error occurred during an
- operation with a FIFO such as
- an underrun or overrun, this
- error requires the device to
- be reset */
-#define XST_RESET_ERROR 8L /* an error occurred which requires
- the device to be reset */
-#define XST_DMA_ERROR 9L /* a DMA error occurred, this error
- typically requires the device
- using the DMA to be reset */
-#define XST_NOT_POLLED 10L /* the device is not configured for
- polled mode operation */
-#define XST_FIFO_NO_ROOM 11L /* a FIFO did not have room to put
- the specified data into */
-#define XST_BUFFER_TOO_SMALL 12L /* the buffer is not large enough
- to hold the expected data */
-#define XST_NO_DATA 13L /* there was no data available */
-#define XST_REGISTER_ERROR 14L /* a register did not contain the
- expected value */
-#define XST_INVALID_PARAM 15L /* an invalid parameter was passed
- into the function */
-#define XST_NOT_SGDMA 16L /* the device is not configured for
- scatter-gather DMA operation */
-#define XST_LOOPBACK_ERROR 17L /* a loopback test failed */
-#define XST_NO_CALLBACK 18L /* a callback has not yet been
- * registered */
-#define XST_NO_FEATURE 19L /* device is not configured with
- * the requested feature */
-#define XST_NOT_INTERRUPT 20L /* device is not configured for
- * interrupt mode operation */
-#define XST_DEVICE_BUSY 21L /* device is busy */
-#define XST_ERROR_COUNT_MAX 22L /* the error counters of a device
- * have maxed out */
-#define XST_IS_STARTED 23L /* used when part of device is
- * already started i.e.
- * sub channel */
-#define XST_IS_STOPPED 24L /* used when part of device is
- * already stopped i.e.
- * sub channel */
-
-/***************** Utility Component statuses 401 - 500 *********************/
-
-#define XST_MEMTEST_FAILED 401L /* memory test failed */
-
-/***************** Common Components statuses 501 - 1000 *********************/
-
-/********************* Packet Fifo statuses 501 - 510 ************************/
-
-#define XST_PFIFO_LACK_OF_DATA 501L /* not enough data in FIFO */
-#define XST_PFIFO_NO_ROOM 502L /* not enough room in FIFO */
-#define XST_PFIFO_BAD_REG_VALUE 503L /* self test, a register value
- was invalid after reset */
-
-/************************** DMA statuses 511 - 530 ***************************/
-
-#define XST_DMA_TRANSFER_ERROR 511L /* self test, DMA transfer
- failed */
-#define XST_DMA_RESET_REGISTER_ERROR 512L /* self test, a register value
- was invalid after reset */
-#define XST_DMA_SG_LIST_EMPTY 513L /* scatter gather list contains
- no buffer descriptors ready
- to be processed */
-#define XST_DMA_SG_IS_STARTED 514L /* scatter gather not stopped */
-#define XST_DMA_SG_IS_STOPPED 515L /* scatter gather not running */
-#define XST_DMA_SG_LIST_FULL 517L /* all the buffer desciptors of
- the scatter gather list are
- being used */
-#define XST_DMA_SG_BD_LOCKED 518L /* the scatter gather buffer
- descriptor which is to be
- copied over in the scatter
- list is locked */
-#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /* no buffer descriptors have been
- put into the scatter gather
- list to be commited */
-#define XST_DMA_SG_COUNT_EXCEEDED 521L /* the packet count threshold
- specified was larger than the
- total # of buffer descriptors
- in the scatter gather list */
-#define XST_DMA_SG_LIST_EXISTS 522L /* the scatter gather list has
- already been created */
-#define XST_DMA_SG_NO_LIST 523L /* no scatter gather list has
- been created */
-#define XST_DMA_SG_BD_NOT_COMMITTED 524L /* the buffer descriptor which was
- being started was not committed
- to the list */
-#define XST_DMA_SG_NO_DATA 525L /* the buffer descriptor to start
- has already been used by the
- hardware so it can't be reused
- */
-
-/************************** IPIF statuses 531 - 550 ***************************/
-
-#define XST_IPIF_REG_WIDTH_ERROR 531L /* an invalid register width
- was passed into the function */
-#define XST_IPIF_RESET_REGISTER_ERROR 532L /* the value of a register at
- reset was not valid */
-#define XST_IPIF_DEVICE_STATUS_ERROR 533L /* a write to the device interrupt
- status register did not read
- back correctly */
-#define XST_IPIF_DEVICE_ACK_ERROR 534L /* the device interrupt status
- register did not reset when
- acked */
-#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /* the device interrupt enable
- register was not updated when
- other registers changed */
-#define XST_IPIF_IP_STATUS_ERROR 536L /* a write to the IP interrupt
- status register did not read
- back correctly */
-#define XST_IPIF_IP_ACK_ERROR 537L /* the IP interrupt status register
- did not reset when acked */
-#define XST_IPIF_IP_ENABLE_ERROR 538L /* IP interrupt enable register was
- not updated correctly when other
- registers changed */
-#define XST_IPIF_DEVICE_PENDING_ERROR 539L /* The device interrupt pending
- register did not indicate the
- expected value */
-#define XST_IPIF_DEVICE_ID_ERROR 540L /* The device interrupt ID register
- did not indicate the expected
- value */
-
-/****************** Device specific statuses 1001 - 4095 *********************/
-
-/********************* Ethernet statuses 1001 - 1050 *************************/
-
-#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /* Memory space is not big enough
- * to hold the minimum number of
- * buffers or descriptors */
-#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /* Memory allocation failed */
-#define XST_EMAC_MII_READ_ERROR 1003L /* MII read error */
-#define XST_EMAC_MII_BUSY 1004L /* An MII operation is in progress */
-#define XST_EMAC_OUT_OF_BUFFERS 1005L /* Adapter is out of buffers */
-#define XST_EMAC_PARSE_ERROR 1006L /* Invalid adapter init string */
-#define XST_EMAC_COLLISION_ERROR 1007L /* Excess deferral or late
- * collision on polled send */
-
-/*********************** UART statuses 1051 - 1075 ***************************/
-#define XST_UART
-
-#define XST_UART_INIT_ERROR 1051L
-#define XST_UART_START_ERROR 1052L
-#define XST_UART_CONFIG_ERROR 1053L
-#define XST_UART_TEST_FAIL 1054L
-#define XST_UART_BAUD_ERROR 1055L
-#define XST_UART_BAUD_RANGE 1056L
-
-/************************ IIC statuses 1076 - 1100 ***************************/
-
-#define XST_IIC_SELFTEST_FAILED 1076 /* self test failed */
-#define XST_IIC_BUS_BUSY 1077 /* bus found busy */
-#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /* mastersend attempted with */
- /* general call address */
-#define XST_IIC_STAND_REG_RESET_ERROR 1079 /* A non parameterizable reg */
- /* value after reset not valid */
-#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /* Tx fifo included in design */
- /* value after reset not valid */
-#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /* Rx fifo included in design */
- /* value after reset not valid */
-#define XST_IIC_TBA_REG_RESET_ERROR 1082 /* 10 bit addr incl in design */
- /* value after reset not valid */
-#define XST_IIC_CR_READBACK_ERROR 1083 /* Read of the control register */
- /* didn't return value written */
-#define XST_IIC_DTR_READBACK_ERROR 1084 /* Read of the data Tx reg */
- /* didn't return value written */
-#define XST_IIC_DRR_READBACK_ERROR 1085 /* Read of the data Receive reg */
- /* didn't return value written */
-#define XST_IIC_ADR_READBACK_ERROR 1086 /* Read of the data Tx reg */
- /* didn't return value written */
-#define XST_IIC_TBA_READBACK_ERROR 1087 /* Read of the 10 bit addr reg */
- /* didn't return written value */
-#define XST_IIC_NOT_SLAVE 1088 /* The device isn't a slave */
-
-/*********************** ATMC statuses 1101 - 1125 ***************************/
-
-#define XST_ATMC_ERROR_COUNT_MAX 1101L /* the error counters in the ATM
- controller hit the max value
- which requires the statistics
- to be cleared */
-
-/*********************** Flash statuses 1126 - 1150 **************************/
-
-#define XST_FLASH_BUSY 1126L /* Flash is erasing or programming */
-#define XST_FLASH_READY 1127L /* Flash is ready for commands */
-#define XST_FLASH_ERROR 1128L /* Flash had detected an internal
- error. Use XFlash_DeviceControl
- to retrieve device specific codes */
-#define XST_FLASH_ERASE_SUSPENDED 1129L /* Flash is in suspended erase state */
-#define XST_FLASH_WRITE_SUSPENDED 1130L /* Flash is in suspended write state */
-#define XST_FLASH_PART_NOT_SUPPORTED 1131L /* Flash type not supported by
- driver */
-#define XST_FLASH_NOT_SUPPORTED 1132L /* Operation not supported */
-#define XST_FLASH_TOO_MANY_REGIONS 1133L /* Too many erase regions */
-#define XST_FLASH_TIMEOUT_ERROR 1134L /* Programming or erase operation
- aborted due to a timeout */
-#define XST_FLASH_ADDRESS_ERROR 1135L /* Accessed flash outside its
- addressible range */
-#define XST_FLASH_ALIGNMENT_ERROR 1136L /* Write alignment error */
-#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /* Couldn't return immediately from
- write/erase function with
- XFL_NON_BLOCKING_WRITE/ERASE
- option cleared */
-#define XST_FLASH_CFI_QUERY_ERROR 1138L /* Failed to query the device */
-
-/*********************** SPI statuses 1151 - 1175 ****************************/
-
-#define XST_SPI_MODE_FAULT 1151 /* master was selected as slave */
-#define XST_SPI_TRANSFER_DONE 1152 /* data transfer is complete */
-#define XST_SPI_TRANSMIT_UNDERRUN 1153 /* slave underruns transmit register */
-#define XST_SPI_RECEIVE_OVERRUN 1154 /* device overruns receive register */
-#define XST_SPI_NO_SLAVE 1155 /* no slave has been selected yet */
-#define XST_SPI_TOO_MANY_SLAVES 1156 /* more than one slave is being
- * selected */
-#define XST_SPI_NOT_MASTER 1157 /* operation is valid only as master */
-#define XST_SPI_SLAVE_ONLY 1158 /* device is configured as slave-only */
-#define XST_SPI_SLAVE_MODE_FAULT 1159 /* slave was selected while disabled */
-
-/********************** OPB Arbiter statuses 1176 - 1200 *********************/
-
-#define XST_OPBARB_INVALID_PRIORITY 1176 /* the priority registers have either
- * one master assigned to two or more
- * priorities, or one master not
- * assigned to any priority
- */
-#define XST_OPBARB_NOT_SUSPENDED 1177 /* an attempt was made to modify the
- * priority levels without first
- * suspending the use of priority
- * levels
- */
-#define XST_OPBARB_PARK_NOT_ENABLED 1178 /* bus parking by id was enabled but
- * bus parking was not enabled
- */
-#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /* the arbiter must be in fixed
- * priority mode to allow the
- * priorities to be changed
- */
-
-/************************ Intc statuses 1201 - 1225 **************************/
-
-#define XST_INTC_FAIL_SELFTEST 1201 /* self test failed */
-#define XST_INTC_CONNECT_ERROR 1202 /* interrupt already in use */
-
-/********************** TmrCtr statuses 1226 - 1250 **************************/
-
-#define XST_TMRCTR_TIMER_FAILED 1226 /* self test failed */
-
-/********************** WdtTb statuses 1251 - 1275 ***************************/
-
-#define XST_WDTTB_TIMER_FAILED 1251L
-
-/********************** PlbArb statuses 1276 - 1300 **************************/
-
-#define XST_PLBARB_FAIL_SELFTEST 1276L
-
-/********************** Plb2Opb statuses 1301 - 1325 *************************/
-
-#define XST_PLB2OPB_FAIL_SELFTEST 1301L
-
-/********************** Opb2Plb statuses 1326 - 1350 *************************/
-
-#define XST_OPB2PLB_FAIL_SELFTEST 1326L
-
-/********************** SysAce statuses 1351 - 1360 **************************/
-
-#define XST_SYSACE_NO_LOCK 1351L /* No MPU lock has been granted */
-
-/********************** PCI Bridge statuses 1361 - 1375 **********************/
-
-#define XST_PCI_INVALID_ADDRESS 1361L
-
-/**************************** Type Definitions *******************************/
-
-/**
- * The status typedef.
- */
-typedef u32 XStatus;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-#endif /* end of protection macro */
+++ /dev/null
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-/*****************************************************************************
-*
-* This file contains the implementation of the XVersion component. This
-* component represents a version ID. It is encapsulated within a component
-* so that it's type and implementation can change without affecting users of
-* it.
-*
-* The version is formatted as X.YYZ where X = 0 - 9, Y = 00 - 99, Z = a - z
-* X is the major revision, YY is the minor revision, and Z is the
-* compatability revision.
-*
-* Packed versions are also utilized for the configuration ROM such that
-* memory is minimized. A packed version consumes only 16 bits and is
-* formatted as follows.
-*
-* <pre>
-* Revision Range Bit Positions
-*
-* Major Revision 0 - 9 Bits 15 - 12
-* Minor Revision 0 - 99 Bits 11 - 5
-* Compatability Revision a - z Bits 4 - 0
-</pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xbasic_types.h"
-#include "xversion.h"
-
-/************************** Constant Definitions *****************************/
-
-/* the following constants define the masks and shift values to allow the
- * revisions to be packed and unpacked, a packed version is packed into a 16
- * bit value in the following format, XXXXYYYYYYYZZZZZ, where XXXX is the
- * major revision, YYYYYYY is the minor revision, and ZZZZZ is the compatability
- * revision
- */
-#define XVE_MAJOR_SHIFT_VALUE 12
-#define XVE_MINOR_ONLY_MASK 0x0FE0
-#define XVE_MINOR_SHIFT_VALUE 5
-#define XVE_COMP_ONLY_MASK 0x001F
-
-/* the following constants define the specific characters of a version string
- * for each character of the revision, a version string is in the following
- * format, "X.YYZ" where X is the major revision (0 - 9), YY is the minor
- * revision (00 - 99), and Z is the compatability revision (a - z)
- */
-#define XVE_MAJOR_CHAR 0 /* major revision 0 - 9 */
-#define XVE_MINOR_TENS_CHAR 2 /* minor revision tens 0 - 9 */
-#define XVE_MINOR_ONES_CHAR 3 /* minor revision ones 0 - 9 */
-#define XVE_COMP_CHAR 4 /* compatability revision a - z */
-#define XVE_END_STRING_CHAR 5
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-static u32 IsVersionStringValid(s8 * StringPtr);
-
-/*****************************************************************************
-*
-* Unpacks a packed version into the specified version. Versions are packed
-* into the configuration ROM to reduce the amount storage. A packed version
-* is a binary format as oppossed to a non-packed version which is implemented
-* as a string.
-*
-* @param InstancePtr points to the version to unpack the packed version into.
-* @param PackedVersion contains the packed version to unpack.
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-void
-XVersion_UnPack(XVersion * InstancePtr, u16 PackedVersion)
-{
- /* not implemented yet since CROM related */
-}
-
-/*****************************************************************************
-*
-* Packs a version into the specified packed version. Versions are packed into
-* the configuration ROM to reduce the amount storage.
-*
-* @param InstancePtr points to the version to pack.
-* @param PackedVersionPtr points to the packed version which will receive
-* the new packed version.
-*
-* @return
-*
-* A status, XST_SUCCESS, indicating the packing was accomplished
-* successfully, or an error, XST_INVALID_VERSION, indicating the specified
-* input version was not valid such that the pack did not occur
-* <br><br>
-* The packed version pointed to by PackedVersionPtr is modified with the new
-* packed version if the status indicates success.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-XStatus
-XVersion_Pack(XVersion * InstancePtr, u16 * PackedVersionPtr)
-{
- /* not implemented yet since CROM related */
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************
-*
-* Determines if two versions are equal.
-*
-* @param InstancePtr points to the first version to be compared.
-* @param VersionPtr points to a second version to be compared.
-*
-* @return
-*
-* TRUE if the versions are equal, FALSE otherwise.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-u32
-XVersion_IsEqual(XVersion * InstancePtr, XVersion * VersionPtr)
-{
- u8 *Version1 = (u8 *) InstancePtr;
- u8 *Version2 = (u8 *) VersionPtr;
- int Index;
-
- /* assert to verify input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(VersionPtr != NULL);
-
- /* check each byte of the versions to see if they are the same,
- * return at any point a byte differs between them
- */
- for (Index = 0; Index < sizeof (XVersion); Index++) {
- if (Version1[Index] != Version2[Index]) {
- return FALSE;
- }
- }
-
- /* No byte was found to be different between the versions, so indicate
- * the versions are equal
- */
- return TRUE;
-}
-
-/*****************************************************************************
-*
-* Converts a version to a null terminated string.
-*
-* @param InstancePtr points to the version to convert.
-* @param StringPtr points to the string which will be the result of the
-* conversion. This does not need to point to a null terminated
-* string as an input, but must point to storage which is an adequate
-* amount to hold the result string.
-*
-* @return
-*
-* The null terminated string is inserted at the location pointed to by
-* StringPtr if the status indicates success.
-*
-* @note
-*
-* It is necessary for the caller to have already allocated the storage to
-* contain the string. The amount of memory necessary for the string is
-* specified in the version header file.
-*
-******************************************************************************/
-void
-XVersion_ToString(XVersion * InstancePtr, s8 * StringPtr)
-{
- /* assert to verify input arguments */
-
- XASSERT_VOID(InstancePtr != NULL);
- XASSERT_VOID(StringPtr != NULL);
-
- /* since version is implemented as a string, just copy the specified
- * input into the specified output
- */
- XVersion_Copy(InstancePtr, (XVersion *) StringPtr);
-}
-
-/*****************************************************************************
-*
-* Initializes a version from a null terminated string. Since the string may not
-* be a format which is compatible with the version, an error could occur.
-*
-* @param InstancePtr points to the version which is to be initialized.
-* @param StringPtr points to a null terminated string which will be
-* converted to a version. The format of the string must match the
-* version string format which is X.YYX where X = 0 - 9, YY = 00 - 99,
-* Z = a - z.
-*
-* @return
-*
-* A status, XST_SUCCESS, indicating the conversion was accomplished
-* successfully, or XST_INVALID_VERSION indicating the version string format
-* was not valid.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-XStatus
-XVersion_FromString(XVersion * InstancePtr, s8 * StringPtr)
-{
- /* assert to verify input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(StringPtr != NULL);
-
- /* if the version string specified is not valid, return an error */
-
- if (!IsVersionStringValid(StringPtr)) {
- return XST_INVALID_VERSION;
- }
-
- /* copy the specified string into the specified version and indicate the
- * conversion was successful
- */
- XVersion_Copy((XVersion *) StringPtr, InstancePtr);
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************
-*
-* Copies the contents of a version to another version.
-*
-* @param InstancePtr points to the version which is the source of data for
-* the copy operation.
-* @param VersionPtr points to another version which is the destination of
-* the copy operation.
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-void
-XVersion_Copy(XVersion * InstancePtr, XVersion * VersionPtr)
-{
- u8 *Source = (u8 *) InstancePtr;
- u8 *Destination = (u8 *) VersionPtr;
- int Index;
-
- /* assert to verify input arguments */
-
- XASSERT_VOID(InstancePtr != NULL);
- XASSERT_VOID(VersionPtr != NULL);
-
- /* copy each byte of the source version to the destination version */
-
- for (Index = 0; Index < sizeof (XVersion); Index++) {
- Destination[Index] = Source[Index];
- }
-}
-
-/*****************************************************************************
-*
-* Determines if the specified version is valid.
-*
-* @param StringPtr points to the string to be validated.
-*
-* @return
-*
-* TRUE if the version string is a valid format, FALSE otherwise.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-static u32
-IsVersionStringValid(s8 * StringPtr)
-{
- /* if the input string is not a valid format, "X.YYZ" where X = 0 - 9,
- * YY = 00 - 99, and Z = a - z, then indicate it's not valid
- */
- if ((StringPtr[XVE_MAJOR_CHAR] < '0') ||
- (StringPtr[XVE_MAJOR_CHAR] > '9') ||
- (StringPtr[XVE_MINOR_TENS_CHAR] < '0') ||
- (StringPtr[XVE_MINOR_TENS_CHAR] > '9') ||
- (StringPtr[XVE_MINOR_ONES_CHAR] < '0') ||
- (StringPtr[XVE_MINOR_ONES_CHAR] > '9') ||
- (StringPtr[XVE_COMP_CHAR] < 'a') ||
- (StringPtr[XVE_COMP_CHAR] > 'z')) {
- return FALSE;
- }
-
- return TRUE;
-}
+++ /dev/null
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-/*****************************************************************************
-*
-* This file contains the interface for the XVersion component. This
-* component represents a version ID. It is encapsulated within a component
-* so that it's type and implementation can change without affecting users of
-* it.
-*
-* The version is formatted as X.YYZ where X = 0 - 9, Y = 00 - 99, Z = a - z
-* X is the major revision, YY is the minor revision, and Z is the
-* compatability revision.
-*
-* Packed versions are also utilized for the configuration ROM such that
-* memory is minimized. A packed version consumes only 16 bits and is
-* formatted as follows.
-*
-* <pre>
-* Revision Range Bit Positions
-*
-* Major Revision 0 - 9 Bits 15 - 12
-* Minor Revision 0 - 99 Bits 11 - 5
-* Compatability Revision a - z Bits 4 - 0
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XVERSION_H /* prevent circular inclusions */
-#define XVERSION_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xbasic_types.h"
-#include "xstatus.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/* the following data type is used to hold a null terminated version string
- * consisting of the following format, "X.YYX"
- */
-typedef s8 XVersion[6];
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-void XVersion_UnPack(XVersion * InstancePtr, u16 PackedVersion);
-
-XStatus XVersion_Pack(XVersion * InstancePtr, u16 * PackedVersion);
-
-u32 XVersion_IsEqual(XVersion * InstancePtr, XVersion * VersionPtr);
-
-void XVersion_ToString(XVersion * InstancePtr, s8 * StringPtr);
-
-XStatus XVersion_FromString(XVersion * InstancePtr, s8 * StringPtr);
-
-void XVersion_Copy(XVersion * InstancePtr, XVersion * VersionPtr);
-
-#endif /* end of protection macro */
+++ /dev/null
-/*
- * init.S: Stubs for U-Boot initialization
- *
- * Author: Xilinx, Inc.
- *
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- *
- * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
- * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
- * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
- * XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
- * FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
- * ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
- * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
- * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
- * WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
- * CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
- * FITNESS FOR A PARTICULAR PURPOSE.
- *
- *
- * Xilinx hardware products are not intended for use in life support
- * appliances, devices, or systems. Use in such applications is
- * expressly prohibited.
- *
- *
- * (c) Copyright 2002-2004 Xilinx Inc.
- * All rights reserved.
- *
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- *
- */
-
- .globl ext_bus_cntlr_init
-ext_bus_cntlr_init:
- blr
+++ /dev/null
-/*
- * ml300.c: U-Boot platform support for Xilinx ML300 board
- *
- * Author: Xilinx, Inc.
- *
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- *
- * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
- * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
- * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
- * XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
- * FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
- * ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
- * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
- * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
- * WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
- * CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
- * FITNESS FOR A PARTICULAR PURPOSE.
- *
- *
- * Xilinx hardware products are not intended for use in life support
- * appliances, devices, or systems. Use in such applications is
- * expressly prohibited.
- *
- *
- * (c) Copyright 2002-2004 Xilinx Inc.
- * All rights reserved.
- *
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/processor.h>
-
-#ifdef CONFIG_ENV_IS_IN_EEPROM
-extern void convert_env(void);
-#endif
-
-int
-board_pre_init(void)
-{
- return 0;
-}
-
-int
-checkboard(void)
-{
- char tmp[64]; /* long enough for environment variables */
- char *s, *e;
- int i = getenv_r("L", tmp, sizeof (tmp));
-
- if (i < 0) {
- printf("### No HW ID - assuming ML300");
- } else {
- for (e = tmp; *e; ++e) {
- if (*e == ' ')
- break;
- }
-
- printf("### Board Serial# is ");
-
- for (s = tmp; s < e; ++s) {
- putc(*s);
- }
-
- }
- putc('\n');
-
- return (0);
-}
-
-phys_size_t
-initdram(int board_type)
-{
- return 128 * 1024 * 1024;
-}
-
-int
-testdram(void)
-{
- printf("test: xxx MB - ok\n");
-
- return (0);
-}
-
-/* implement functions originally in cpu/ppc4xx/speed.c */
-void
-get_sys_info(sys_info_t * sysInfo)
-{
- sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
-
- /* only correct if the PLB and OPB run at the same frequency */
- sysInfo->freqPLB = XPAR_UARTNS550_0_CLOCK_FREQ_HZ;
- sysInfo->freqPCI = XPAR_UARTNS550_0_CLOCK_FREQ_HZ / 3;
-}
-
-ulong
-get_PCI_freq(void)
-{
- ulong val;
- PPC4xx_SYS_INFO sys_info;
-
- get_sys_info(&sys_info);
- val = sys_info.freqPCI;
- return val;
-}
-
-#ifdef CONFIG_MISC_INIT_R
-
-int
-misc_init_r()
-{
- /* convert env name and value to u-boot standard */
- convert_env();
- return 0;
-}
-
-#endif
+++ /dev/null
-/*
- * Author: Xilinx, Inc.
- *
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- *
- * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
- * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
- * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
- * XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
- * FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
- * ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
- * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
- * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
- * WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
- * CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
- * FITNESS FOR A PARTICULAR PURPOSE.
- *
- *
- * Xilinx hardware products are not intended for use in life support
- * appliances, devices, or systems. Use in such applications is
- * expressly prohibited.
- *
- *
- * (c) Copyright 2002-2004 Xilinx Inc.
- * All rights reserved.
- *
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#include <common.h>
-#include <asm/u-boot.h>
-#include <asm/processor.h>
-#include <command.h>
-#include <config.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define USE_CHAN1 \
- ((defined XPAR_UARTNS550_0_BASEADDR) && (defined CONFIG_SYS_INIT_CHAN1))
-#define USE_CHAN2 \
- ((defined XPAR_UARTNS550_1_BASEADDR) && (defined CONFIG_SYS_INIT_CHAN2))
-
-#if USE_CHAN1
-#include <ns16550.h>
-#endif
-
-#if USE_CHAN1
-const NS16550_t COM_PORTS[] = { (NS16550_t) (XPAR_UARTNS550_0_BASEADDR + 3)
-#if USE_CHAN2
- , (NS16550_t) (XPAR_UARTNS550_1_BASEADDR + 3)
-#endif
-};
-#endif
-
-int
-serial_init(void)
-{
-#if USE_CHAN1
- int clock_divisor;
-
- clock_divisor = XPAR_UARTNS550_0_CLOCK_FREQ_HZ / 16 / gd->baudrate;
- (void) NS16550_init(COM_PORTS[0], clock_divisor);
-#if USE_CHAN2
- clock_divisor = XPAR_UARTNS550_1_CLOCK_FREQ_HZ / 16 / gd->baudrate;
- (void) NS16550_init(COM_PORTS[1], clock_divisor);
-#endif
-#endif
- return 0;
-
-}
-
-void
-serial_putc(const char c)
-{
- if (c == '\n')
- NS16550_putc(COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r');
-
- NS16550_putc(COM_PORTS[CONFIG_SYS_DUART_CHAN], c);
-}
-
-int
-serial_getc(void)
-{
- return NS16550_getc(COM_PORTS[CONFIG_SYS_DUART_CHAN]);
-}
-
-int
-serial_tstc(void)
-{
- return NS16550_tstc(COM_PORTS[CONFIG_SYS_DUART_CHAN]);
-}
-
-void
-serial_setbrg(void)
-{
-#if USE_CHAN1
- int clock_divisor;
-
- clock_divisor = XPAR_UARTNS550_0_CLOCK_FREQ_HZ / 16 / gd->baudrate;
- NS16550_reinit(COM_PORTS[0], clock_divisor);
-#if USE_CHAN2
- clock_divisor = XPAR_UARTNS550_1_CLOCK_FREQ_HZ / 16 / gd->baudrate;
- NS16550_reinit(COM_PORTS[1], clock_divisor);
-#endif
-#endif
-}
-
-void
-serial_puts(const char *s)
-{
- while (*s) {
- serial_putc(*s++);
- }
-}
-
-#if defined(CONFIG_CMD_KGDB)
-void
-kgdb_serial_init(void)
-{
-}
-
-void
-putDebugChar(int c)
-{
- serial_putc(c);
-}
-
-void
-putDebugStr(const char *str)
-{
- serial_puts(str);
-}
-
-int
-getDebugChar(void)
-{
- return serial_getc();
-}
-
-void
-kgdb_interruptible(int yes)
-{
- return;
-}
-#endif
+++ /dev/null
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by libgen.
-* Version: Xilinx EDK 6.2 EDK_Gm.11
-* DO NOT EDIT.
-*
-* Copyright (c) 2003 Xilinx, Inc. All rights reserved.
-*
-* Description: Driver parameters
-*
-*******************************************************************/
-
-/******************************************************************/
-
-/* U-Boot Redefines */
-
-/******************************************************************/
-
-#define XPAR_UARTNS550_0_BASEADDR (XPAR_OPB_UART16550_0_BASEADDR+0x1000)
-#define XPAR_UARTNS550_0_HIGHADDR XPAR_OPB_UART16550_0_HIGHADDR
-#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ
-#define XPAR_UARTNS550_0_DEVICE_ID XPAR_OPB_UART16550_0_DEVICE_ID
-#define XPAR_UARTNS550_1_BASEADDR (XPAR_OPB_UART16550_1_BASEADDR+0x1000)
-#define XPAR_UARTNS550_1_HIGHADDR XPAR_OPB_UART16550_1_HIGHADDR
-#define XPAR_UARTNS550_1_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ
-#define XPAR_UARTNS550_1_DEVICE_ID XPAR_OPB_UART16550_1_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_IIC_0_BASEADDR XPAR_OPB_IIC_0_BASEADDR
-#define XPAR_IIC_0_HIGHADDR XPAR_OPB_IIC_0_HIGHADDR
-#define XPAR_IIC_0_TEN_BIT_ADR XPAR_OPB_IIC_0_TEN_BIT_ADR
-#define XPAR_IIC_0_DEVICE_ID XPAR_OPB_IIC_0_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_EMAC_0_BASEADDR XPAR_OPB_ETHERNET_0_BASEADDR
-#define XPAR_EMAC_0_HIGHADDR XPAR_OPB_ETHERNET_0_HIGHADDR
-#define XPAR_EMAC_0_DMA_PRESENT XPAR_OPB_ETHERNET_0_DMA_PRESENT
-#define XPAR_EMAC_0_MII_EXIST XPAR_OPB_ETHERNET_0_MII_EXIST
-#define XPAR_EMAC_0_ERR_COUNT_EXIST XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST
-#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ
-
-/******************************************************************/
-
-#define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0x00000400
-#define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 0x000007FF
-#define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0
-
-/******************************************************************/
-
-#define XPAR_XPCI_NUM_INSTANCES 1
-#define XPAR_XPCI_CLOCK_HZ 33333333
-#define XPAR_OPB_PCI_REF_0_DEVICE_ID 0
-#define XPAR_OPB_PCI_REF_0_BASEADDR 0x20000000
-#define XPAR_OPB_PCI_REF_0_HIGHADDR 0x3FFFFFFF
-#define XPAR_OPB_PCI_REF_0_CONFIG_ADDR 0x3C000000
-#define XPAR_OPB_PCI_REF_0_CONFIG_DATA 0x3C000004
-#define XPAR_OPB_PCI_REF_0_LCONFIG_ADDR 0x3E000000
-#define XPAR_OPB_PCI_REF_0_MEM_BASEADDR 0x20000000
-#define XPAR_OPB_PCI_REF_0_MEM_HIGHADDR 0x37FFFFFF
-#define XPAR_OPB_PCI_REF_0_IO_BASEADDR 0x38000000
-#define XPAR_OPB_PCI_REF_0_IO_HIGHADDR 0x3BFFFFFF
-
-/******************************************************************/
-
-#define XPAR_XEMAC_NUM_INSTANCES 1
-#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000
-#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF
-#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
-#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
-#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
-#define XPAR_OPB_ETHERNET_0_MII_EXIST 1
-
-/******************************************************************/
-
-#define XPAR_MY_OPB_GPIO_0_DEVICE_ID_0 0
-#define XPAR_MY_OPB_GPIO_0_BASEADDR_0 0x90000000
-#define XPAR_MY_OPB_GPIO_0_HIGHADDR_0 (0x90000000+0x7)
-#define XPAR_MY_OPB_GPIO_0_DEVICE_ID_1 1
-#define XPAR_MY_OPB_GPIO_0_BASEADDR_1 (0x90000000+0x8)
-#define XPAR_MY_OPB_GPIO_0_HIGHADDR_1 (0x90000000+0x1F)
-#define XPAR_XGPIO_NUM_INSTANCES 2
-
-/******************************************************************/
-
-#define XPAR_XIIC_NUM_INSTANCES 1
-#define XPAR_OPB_IIC_0_BASEADDR 0xA8000000
-#define XPAR_OPB_IIC_0_HIGHADDR 0xA80001FF
-#define XPAR_OPB_IIC_0_DEVICE_ID 0
-#define XPAR_OPB_IIC_0_TEN_BIT_ADR 0
-
-/******************************************************************/
-
-#define XPAR_XUARTNS550_NUM_INSTANCES 2
-#define XPAR_XUARTNS550_CLOCK_HZ 100000000
-#define XPAR_OPB_UART16550_0_BASEADDR 0xA0000000
-#define XPAR_OPB_UART16550_0_HIGHADDR 0xA0001FFF
-#define XPAR_OPB_UART16550_0_DEVICE_ID 0
-#define XPAR_OPB_UART16550_1_BASEADDR 0xA0010000
-#define XPAR_OPB_UART16550_1_HIGHADDR 0xA0011FFF
-#define XPAR_OPB_UART16550_1_DEVICE_ID 1
-
-/******************************************************************/
-
-#define XPAR_XSPI_NUM_INSTANCES 1
-#define XPAR_OPB_SPI_0_BASEADDR 0xA4000000
-#define XPAR_OPB_SPI_0_HIGHADDR 0xA400007F
-#define XPAR_OPB_SPI_0_DEVICE_ID 0
-#define XPAR_OPB_SPI_0_FIFO_EXIST 1
-#define XPAR_OPB_SPI_0_SPI_SLAVE_ONLY 0
-#define XPAR_OPB_SPI_0_NUM_SS_BITS 1
-
-/******************************************************************/
-
-#define XPAR_XPS2_NUM_INSTANCES 2
-#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 0
-#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 0xA9000000
-#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 (0xA9000000+0x3F)
-#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 1
-#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 (0xA9000000+0x1000)
-#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 (0xA9000000+0x103F)
-
-/******************************************************************/
-
-#define XPAR_XTOUCHSCREEN_NUM_INSTANCES 1
-#define XPAR_OPB_TSD_REF_0_BASEADDR 0xAA000000
-#define XPAR_OPB_TSD_REF_0_HIGHADDR 0xAA000007
-#define XPAR_OPB_TSD_REF_0_DEVICE_ID 0
-
-/******************************************************************/
-
-#define XPAR_OPB_AC97_CONTROLLER_REF_0_BASEADDR 0xA6000000
-#define XPAR_OPB_AC97_CONTROLLER_REF_0_HIGHADDR 0xA60000FF
-#define XPAR_OPB_PAR_PORT_REF_0_BASEADDR 0x90010000
-#define XPAR_OPB_PAR_PORT_REF_0_HIGHADDR 0x900100FF
-#define XPAR_PLB_DDR_0_BASEADDR 0x00000000
-#define XPAR_PLB_DDR_0_HIGHADDR 0x0FFFFFFF
-
-/******************************************************************/
-
-#define XPAR_XINTC_HAS_IPR 1
-#define XPAR_INTC_MAX_NUM_INTR_INPUTS 18
-#define XPAR_XINTC_USE_DCR 0
-#define XPAR_XINTC_NUM_INSTANCES 1
-#define XPAR_DCR_INTC_0_BASEADDR 0xD0000FC0
-#define XPAR_DCR_INTC_0_HIGHADDR 0xD0000FDF
-#define XPAR_DCR_INTC_0_DEVICE_ID 0
-#define XPAR_DCR_INTC_0_KIND_OF_INTR 0x00038000
-
-/******************************************************************/
-
-#define XPAR_DCR_INTC_0_MISC_LOGIC_0_PHY_MII_INT_INTR 0
-#define XPAR_DCR_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR 1
-#define XPAR_DCR_INTC_0_MISC_LOGIC_0_IIC_TEMP_CRIT_INTR 2
-#define XPAR_DCR_INTC_0_MISC_LOGIC_0_IIC_IRQ_INTR 3
-#define XPAR_DCR_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR 4
-#define XPAR_DCR_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR 5
-#define XPAR_DCR_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR 6
-#define XPAR_DCR_INTC_0_OPB_UART16550_1_IP2INTC_IRPT_INTR 7
-#define XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR 8
-#define XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR 9
-#define XPAR_DCR_INTC_0_OPB_SPI_0_IP2INTC_IRPT_INTR 10
-#define XPAR_DCR_INTC_0_OPB_TSD_REF_0_INTR_INTR 11
-#define XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR 12
-#define XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR 13
-#define XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR 14
-#define XPAR_DCR_INTC_0_PLB2OPB_BRIDGE_0_BUS_ERROR_DET_INTR 15
-#define XPAR_DCR_INTC_0_PLB_V34_0_BUS_ERROR_DET_INTR 16
-#define XPAR_DCR_INTC_0_OPB2PLB_BRIDGE_0_BUS_ERROR_DET_INTR 17
-
-/******************************************************************/
-
-#define XPAR_XTFT_NUM_INSTANCES 1
-#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR 0xD0000200
-#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_HIGHADDR 0xD0000207
-#define XPAR_PLB_TFT_CNTLR_REF_0_DEVICE_ID 0
-
-/******************************************************************/
-
-#define XPAR_XSYSACE_MEM_WIDTH 8
-#define XPAR_XSYSACE_NUM_INSTANCES 1
-#define XPAR_OPB_SYSACE_0_BASEADDR 0xCF000000
-#define XPAR_OPB_SYSACE_0_HIGHADDR 0xCF0001FF
-#define XPAR_OPB_SYSACE_0_DEVICE_ID 0
-#define XPAR_OPB_SYSACE_0_MEM_WIDTH 8
-
-/******************************************************************/
-
-#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000
-
-/******************************************************************/
+++ /dev/null
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-
-#include <config.h>
-#include <common.h>
-#include <net.h>
-#include "xemac.h"
-
-#if defined(XPAR_EMAC_0_DEVICE_ID)
-/*
- * ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
- * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
- */
-
-#define ENET_MAX_MTU PKTSIZE
-#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
-#define ENET_ADDR_LENGTH 6
-
-static XEmac Emac;
-static char etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */
-
-/* hardcoded MAC address for the Xilinx EMAC Core when env is nowhere*/
-#ifdef CONFIG_ENV_IS_NOWHERE
-static u8 EMACAddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 };
-#endif
-
-static int initialized = 0;
-
-void
-eth_halt(void)
-{
- if (initialized)
- (void) XEmac_Stop(&Emac);
-}
-
-int
-eth_init(bd_t * bis)
-{
- u32 Options;
- XStatus Result;
- uchar enetaddr[6];
-
-#ifdef DEBUG
- printf("EMAC Initialization Started\n\r");
-#endif
-
- Result = XEmac_Initialize(&Emac, XPAR_EMAC_0_DEVICE_ID);
- if (Result != XST_SUCCESS) {
- return 0;
- }
-
- /* make sure the Emac is stopped before it is started */
- (void) XEmac_Stop(&Emac);
-
- if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
-#ifdef CONFIG_ENV_IS_NOWHERE
- memcpy(enetaddr, EMACAddr, 6);
- eth_setenv_enetaddr("ethaddr", enetaddr);
-#endif
- }
-
- Result = XEmac_SetMacAddress(&Emac, enetaddr);
- if (Result != XST_SUCCESS) {
- return 0;
- }
-
- Options =
- (XEM_POLLED_OPTION | XEM_UNICAST_OPTION | XEM_BROADCAST_OPTION |
- XEM_FDUPLEX_OPTION | XEM_INSERT_FCS_OPTION |
- XEM_INSERT_PAD_OPTION);
- Result = XEmac_SetOptions(&Emac, Options);
- if (Result != XST_SUCCESS) {
- return 0;
- }
-
- Result = XEmac_Start(&Emac);
- if (Result != XST_SUCCESS) {
- return 0;
- }
-#ifdef DEBUG
- printf("EMAC Initialization complete\n\r");
-#endif
-
- initialized = 1;
-
- return (0);
-}
-
-/*-----------------------------------------------------------------------------+
-+-----------------------------------------------------------------------------*/
-int
-eth_send(volatile void *ptr, int len)
-{
- XStatus Result;
-
- if (len > ENET_MAX_MTU)
- len = ENET_MAX_MTU;
-
- Result = XEmac_PollSend(&Emac, (u8 *) ptr, len);
- if (Result == XST_SUCCESS) {
- return (1);
- } else {
- printf("Error while sending frame\n\r");
- return (0);
- }
-
-}
-
-int
-eth_rx(void)
-{
- u32 RecvFrameLength;
- XStatus Result;
-
- RecvFrameLength = PKTSIZE;
- Result = XEmac_PollRecv(&Emac, (u8 *) etherrxbuff, &RecvFrameLength);
- if (Result == XST_SUCCESS) {
-#ifndef CONFIG_EMACLITE
- NetReceive((uchar *)etherrxbuff, RecvFrameLength);
-#else
- NetReceive(etherrxbuff, RecvFrameLength);
-#endif
- return (1);
- } else {
- return (0);
- }
-}
-
-#endif
+++ /dev/null
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xemac.c
-*
-* The XEmac driver. Functions in this file are the minimum required functions
-* for this driver. See xemac.h for a detailed description of the driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a rpm 07/31/01 First release
-* 1.00b rpm 02/20/02 Repartitioned files and functions
-* 1.00b rpm 07/23/02 Removed the PHY reset from Initialize()
-* 1.00b rmm 09/23/02 Removed commented code in Initialize(). Recycled as
-* XEmac_mPhyReset macro in xemac_l.h.
-* 1.00c rpm 12/05/02 New version includes support for simple DMA
-* 1.00c rpm 12/12/02 Changed location of IsStarted assignment in XEmac_Start
-* to be sure the flag is set before the device and
-* interrupts are enabled.
-* 1.00c rpm 02/03/03 SelfTest was not clearing polled mode. Take driver out
-* of polled mode in XEmac_Reset() to fix this problem.
-* 1.00c rmm 05/13/03 Fixed diab compiler warnings relating to asserts.
-* </pre>
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xbasic_types.h"
-#include "xemac_i.h"
-#include "xio.h"
-#include "xipif_v1_23_b.h" /* Uses v1.23b of the IPIF */
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-static XStatus ConfigureDma(XEmac * InstancePtr);
-static XStatus ConfigureFifo(XEmac * InstancePtr);
-static void StubFifoHandler(void *CallBackRef);
-static void StubErrorHandler(void *CallBackRef, XStatus ErrorCode);
-static void StubSgHandler(void *CallBackRef, XBufDescriptor * BdPtr,
- u32 NumBds);
-
-/************************** Variable Definitions *****************************/
-
-/*****************************************************************************/
-/**
-*
-* Initialize a specific XEmac instance/driver. The initialization entails:
-* - Initialize fields of the XEmac structure
-* - Clear the Ethernet statistics for this device
-* - Initialize the IPIF component with its register base address
-* - Configure the FIFO components with their register base addresses.
-* - If the device is configured with DMA, configure the DMA channel components
-* with their register base addresses. At some later time, memory pools for
-* the scatter-gather descriptor lists may be passed to the driver.
-* - Reset the Ethernet MAC
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-* @param DeviceId is the unique id of the device controlled by this XEmac
-* instance. Passing in a device id associates the generic XEmac
-* instance to a specific device, as chosen by the caller or application
-* developer.
-*
-* @return
-*
-* - XST_SUCCESS if initialization was successful
-* - XST_DEVICE_IS_STARTED if the device has already been started
-* - XST_DEVICE_NOT_FOUND if device configuration information was not found for
-* a device with the supplied device ID.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-XStatus
-XEmac_Initialize(XEmac * InstancePtr, u16 DeviceId)
-{
- XStatus Result;
- XEmac_Config *ConfigPtr; /* configuration information */
-
- XASSERT_NONVOID(InstancePtr != NULL);
-
- /*
- * If the device is started, disallow the initialize and return a status
- * indicating it is started. This allows the user to stop the device
- * and reinitialize, but prevents a user from inadvertently initializing
- */
- if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) {
- return XST_DEVICE_IS_STARTED;
- }
-
- /*
- * Lookup the device configuration in the temporary CROM table. Use this
- * configuration info down below when initializing this component.
- */
- ConfigPtr = XEmac_LookupConfig(DeviceId);
- if (ConfigPtr == NULL) {
- return XST_DEVICE_NOT_FOUND;
- }
-
- /*
- * Set some default values
- */
- InstancePtr->IsReady = 0;
- InstancePtr->IsStarted = 0;
- InstancePtr->IpIfDmaConfig = ConfigPtr->IpIfDmaConfig;
- InstancePtr->HasMii = ConfigPtr->HasMii;
- InstancePtr->HasMulticastHash = FALSE;
-
- /* Always default polled to false, let user configure this mode */
- InstancePtr->IsPolled = FALSE;
- InstancePtr->FifoRecvHandler = StubFifoHandler;
- InstancePtr->FifoSendHandler = StubFifoHandler;
- InstancePtr->ErrorHandler = StubErrorHandler;
- InstancePtr->SgRecvHandler = StubSgHandler;
- InstancePtr->SgSendHandler = StubSgHandler;
-
- /*
- * Clear the statistics for this driver
- */
- XEmac_mClearStruct((u8 *) & InstancePtr->Stats, sizeof (XEmac_Stats));
-
- /*
- * Initialize the device register base addresses
- */
- InstancePtr->BaseAddress = ConfigPtr->BaseAddress;
-
- /*
- * Configure the send and receive FIFOs in the MAC
- */
- Result = ConfigureFifo(InstancePtr);
- if (Result != XST_SUCCESS) {
- return Result;
- }
-
- /*
- * If the device is configured for DMA, configure the send and receive DMA
- * channels in the MAC.
- */
- if (XEmac_mIsDma(InstancePtr)) {
- Result = ConfigureDma(InstancePtr);
- if (Result != XST_SUCCESS) {
- return Result;
- }
- }
-
- /*
- * Indicate the component is now ready to use. Note that this is done before
- * we reset the device and the PHY below, which may seem a bit odd. The
- * choice was made to move it here rather than remove the asserts in various
- * functions (e.g., Reset() and all functions that it calls). Applications
- * that use multiple threads, one to initialize the XEmac driver and one
- * waiting on the IsReady condition could have a problem with this sequence.
- */
- InstancePtr->IsReady = XCOMPONENT_IS_READY;
-
- /*
- * Reset the MAC to get it into its initial state. It is expected that
- * device configuration by the user will take place after this
- * initialization is done, but before the device is started.
- */
- XEmac_Reset(InstancePtr);
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Start the Ethernet controller as follows:
-* - If not in polled mode
-* - Set the internal interrupt enable registers appropriately
-* - Enable interrupts within the device itself. Note that connection of
-* the driver's interrupt handler to the interrupt source (typically
-* done using the interrupt controller component) is done by the higher
-* layer software.
-* - If the device is configured with scatter-gather DMA, start the DMA
-* channels if the descriptor lists are not empty
-* - Enable the transmitter
-* - Enable the receiver
-*
-* The PHY is enabled after driver initialization. We assume the upper layer
-* software has configured it and the EMAC appropriately before this function
-* is called.
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-*
-* @return
-*
-* - XST_SUCCESS if the device was started successfully
-* - XST_NO_CALLBACK if a callback function has not yet been registered using
-* the SetxxxHandler function. This is required if in interrupt mode.
-* - XST_DEVICE_IS_STARTED if the device is already started
-* - XST_DMA_SG_NO_LIST if configured for scatter-gather DMA and a descriptor
-* list has not yet been created for the send or receive channel.
-*
-* @note
-*
-* The driver tries to match the hardware configuration. So if the hardware
-* is configured with scatter-gather DMA, the driver expects to start the
-* scatter-gather channels and expects that the user has set up the buffer
-* descriptor lists already. If the user expects to use the driver in a mode
-* different than how the hardware is configured, the user should modify the
-* configuration table to reflect the mode to be used. Modifying the config
-* table is a workaround for now until we get some experience with how users
-* are intending to use the hardware in its different configurations. For
-* example, if the hardware is built with scatter-gather DMA but the user is
-* intending to use only simple DMA, the user either needs to modify the config
-* table as a workaround or rebuild the hardware with only simple DMA.
-*
-* This function makes use of internal resources that are shared between the
-* Start, Stop, and SetOptions functions. So if one task might be setting device
-* options while another is trying to start the device, the user is required to
-* provide protection of this shared data (typically using a semaphore).
-*
-******************************************************************************/
-XStatus
-XEmac_Start(XEmac * InstancePtr)
-{
- u32 ControlReg;
- XStatus Result;
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /*
- * If it is already started, return a status indicating so
- */
- if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) {
- return XST_DEVICE_IS_STARTED;
- }
-
- /*
- * If not polled, enable interrupts
- */
- if (!InstancePtr->IsPolled) {
- /*
- * Verify that the callbacks have been registered, then enable
- * interrupts
- */
- if (XEmac_mIsSgDma(InstancePtr)) {
- if ((InstancePtr->SgRecvHandler == StubSgHandler) ||
- (InstancePtr->SgSendHandler == StubSgHandler)) {
- return XST_NO_CALLBACK;
- }
-
- /* Enable IPIF interrupts */
- XIIF_V123B_WRITE_DIER(InstancePtr->BaseAddress,
- XEM_IPIF_DMA_DFT_MASK |
- XIIF_V123B_ERROR_MASK);
- XIIF_V123B_WRITE_IIER(InstancePtr->BaseAddress,
- XEM_EIR_DFT_SG_MASK);
-
- /* Enable scatter-gather DMA interrupts */
- XDmaChannel_SetIntrEnable(&InstancePtr->RecvChannel,
- XEM_DMA_SG_INTR_MASK);
- XDmaChannel_SetIntrEnable(&InstancePtr->SendChannel,
- XEM_DMA_SG_INTR_MASK);
- } else {
- if ((InstancePtr->FifoRecvHandler == StubFifoHandler) ||
- (InstancePtr->FifoSendHandler == StubFifoHandler)) {
- return XST_NO_CALLBACK;
- }
-
- /* Enable IPIF interrupts (used by simple DMA also) */
- XIIF_V123B_WRITE_DIER(InstancePtr->BaseAddress,
- XEM_IPIF_FIFO_DFT_MASK |
- XIIF_V123B_ERROR_MASK);
- XIIF_V123B_WRITE_IIER(InstancePtr->BaseAddress,
- XEM_EIR_DFT_FIFO_MASK);
- }
-
- /* Enable the global IPIF interrupt output */
- XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress);
- }
-
- /*
- * Indicate that the device is started before we enable the transmitter
- * or receiver. This needs to be done before because as soon as the
- * receiver is enabled we may get an interrupt, and there are functions
- * in the interrupt handling path that rely on the IsStarted flag.
- */
- InstancePtr->IsStarted = XCOMPONENT_IS_STARTED;
-
- /*
- * Enable the transmitter, and receiver (do a read/modify/write to preserve
- * current settings). There is no critical section here since this register
- * is not modified during interrupt context.
- */
- ControlReg = XIo_In32(InstancePtr->BaseAddress + XEM_ECR_OFFSET);
- ControlReg &= ~(XEM_ECR_XMIT_RESET_MASK | XEM_ECR_RECV_RESET_MASK);
- ControlReg |= (XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK);
-
- XIo_Out32(InstancePtr->BaseAddress + XEM_ECR_OFFSET, ControlReg);
-
- /*
- * If configured with scatter-gather DMA and not polled, restart the
- * DMA channels in case there are buffers ready to be sent or received into.
- * The DMA SgStart function uses data that can be modified during interrupt
- * context, so a critical section is required here.
- */
- if ((XEmac_mIsSgDma(InstancePtr)) && (!InstancePtr->IsPolled)) {
- XIIF_V123B_GINTR_DISABLE(InstancePtr->BaseAddress);
-
- /*
- * The only error we care about is if the list has not yet been
- * created, or on receive, if no buffer descriptors have been
- * added yet (the list is empty). Other errors are benign at this point.
- */
- Result = XDmaChannel_SgStart(&InstancePtr->RecvChannel);
- if ((Result == XST_DMA_SG_NO_LIST)
- || (Result == XST_DMA_SG_LIST_EMPTY)) {
- XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress);
- return Result;
- }
-
- Result = XDmaChannel_SgStart(&InstancePtr->SendChannel);
- if (Result == XST_DMA_SG_NO_LIST) {
- XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress);
- return Result;
- }
-
- XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress);
- }
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Stop the Ethernet MAC as follows:
-* - If the device is configured with scatter-gather DMA, stop the DMA
-* channels (wait for acknowledgment of stop)
-* - Disable the transmitter and receiver
-* - Disable interrupts if not in polled mode (the higher layer software is
-* responsible for disabling interrupts at the interrupt controller)
-*
-* The PHY is left enabled after a Stop is called.
-*
-* If the device is configured for scatter-gather DMA, the DMA engine stops at
-* the next buffer descriptor in its list. The remaining descriptors in the list
-* are not removed, so anything in the list will be transmitted or received when
-* the device is restarted. The side effect of doing this is that the last
-* buffer descriptor processed by the DMA engine before stopping may not be the
-* last descriptor in the Ethernet frame. So when the device is restarted, a
-* partial frame (i.e., a bad frame) may be transmitted/received. This is only a
-* concern if a frame can span multiple buffer descriptors, which is dependent
-* on the size of the network buffers.
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-*
-* @return
-*
-* - XST_SUCCESS if the device was stopped successfully
-* - XST_DEVICE_IS_STOPPED if the device is already stopped
-*
-* @note
-*
-* This function makes use of internal resources that are shared between the
-* Start, Stop, and SetOptions functions. So if one task might be setting device
-* options while another is trying to start the device, the user is required to
-* provide protection of this shared data (typically using a semaphore).
-*
-******************************************************************************/
-XStatus
-XEmac_Stop(XEmac * InstancePtr)
-{
- u32 ControlReg;
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /*
- * If the device is already stopped, do nothing but return a status
- * indicating so
- */
- if (InstancePtr->IsStarted != XCOMPONENT_IS_STARTED) {
- return XST_DEVICE_IS_STOPPED;
- }
-
- /*
- * If configured for scatter-gather DMA, stop the DMA channels. Ignore
- * the XST_DMA_SG_IS_STOPPED return code. There is a critical section
- * here between SgStart and SgStop, and SgStart can be called in interrupt
- * context, so disable interrupts while calling SgStop.
- */
- if (XEmac_mIsSgDma(InstancePtr)) {
- XBufDescriptor *BdTemp; /* temporary descriptor pointer */
-
- XIIF_V123B_GINTR_DISABLE(InstancePtr->BaseAddress);
-
- (void) XDmaChannel_SgStop(&InstancePtr->SendChannel, &BdTemp);
- (void) XDmaChannel_SgStop(&InstancePtr->RecvChannel, &BdTemp);
-
- XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress);
- }
-
- /*
- * Disable the transmitter and receiver. There is no critical section
- * here since this register is not modified during interrupt context.
- */
- ControlReg = XIo_In32(InstancePtr->BaseAddress + XEM_ECR_OFFSET);
- ControlReg &= ~(XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK);
- XIo_Out32(InstancePtr->BaseAddress + XEM_ECR_OFFSET, ControlReg);
-
- /*
- * If not in polled mode, disable interrupts for IPIF (includes MAC and
- * DMAs)
- */
- if (!InstancePtr->IsPolled) {
- XIIF_V123B_GINTR_DISABLE(InstancePtr->BaseAddress);
- }
-
- InstancePtr->IsStarted = 0;
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Reset the Ethernet MAC. This is a graceful reset in that the device is stopped
-* first. Resets the DMA channels, the FIFOs, the transmitter, and the receiver.
-* The PHY is not reset. Any frames in the scatter-gather descriptor lists will
-* remain in the lists. The side effect of doing this is that after a reset and
-* following a restart of the device, frames that were in the list before the
-* reset may be transmitted or received. Reset must only be called after the
-* driver has been initialized.
-*
-* The driver is also taken out of polled mode if polled mode was set. The user
-* is responsbile for re-configuring the driver into polled mode after the
-* reset if desired.
-*
-* The configuration after this reset is as follows:
-* - Half duplex
-* - Disabled transmitter and receiver
-* - Enabled PHY (the PHY is not reset)
-* - MAC transmitter does pad insertion, FCS insertion, and source address
-* overwrite.
-* - MAC receiver does not strip padding or FCS
-* - Interframe Gap as recommended by IEEE Std. 802.3 (96 bit times)
-* - Unicast addressing enabled
-* - Broadcast addressing enabled
-* - Multicast addressing disabled (addresses are preserved)
-* - Promiscuous addressing disabled
-* - Default packet threshold and packet wait bound register values for
-* scatter-gather DMA operation
-* - MAC address of all zeros
-* - Non-polled mode
-*
-* The upper layer software is responsible for re-configuring (if necessary)
-* and restarting the MAC after the reset. Note that the PHY is not reset. PHY
-* control is left to the upper layer software. Note also that driver statistics
-* are not cleared on reset. It is up to the upper layer software to clear the
-* statistics if needed.
-*
-* When a reset is required due to an internal error, the driver notifies the
-* upper layer software of this need through the ErrorHandler callback and
-* specific status codes. The upper layer software is responsible for calling
-* this Reset function and then re-configuring the device.
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* None.
-*
-* @internal
-*
-* The reset is accomplished by setting the IPIF reset register. This takes
-* care of resetting all hardware blocks, including the MAC.
-*
-******************************************************************************/
-void
-XEmac_Reset(XEmac * InstancePtr)
-{
- XASSERT_VOID(InstancePtr != NULL);
- XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /*
- * Stop the device first
- */
- (void) XEmac_Stop(InstancePtr);
-
- /*
- * Take the driver out of polled mode
- */
- InstancePtr->IsPolled = FALSE;
-
- /*
- * Reset the entire IPIF at once. If we choose someday to reset each
- * hardware block separately, the reset should occur in the direction of
- * data flow. For example, for the send direction the reset order is DMA
- * first, then FIFO, then the MAC transmitter.
- */
- XIIF_V123B_RESET(InstancePtr->BaseAddress);
-
- if (XEmac_mIsSgDma(InstancePtr)) {
- /*
- * After reset, configure the scatter-gather DMA packet threshold and
- * packet wait bound registers to default values. Ignore the return
- * values of these functions since they only return error if the device
- * is not stopped.
- */
- (void) XEmac_SetPktThreshold(InstancePtr, XEM_SEND,
- XEM_SGDMA_DFT_THRESHOLD);
- (void) XEmac_SetPktThreshold(InstancePtr, XEM_RECV,
- XEM_SGDMA_DFT_THRESHOLD);
- (void) XEmac_SetPktWaitBound(InstancePtr, XEM_SEND,
- XEM_SGDMA_DFT_WAITBOUND);
- (void) XEmac_SetPktWaitBound(InstancePtr, XEM_RECV,
- XEM_SGDMA_DFT_WAITBOUND);
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* Set the MAC address for this driver/device. The address is a 48-bit value.
-* The device must be stopped before calling this function.
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-* @param AddressPtr is a pointer to a 6-byte MAC address.
-*
-* @return
-*
-* - XST_SUCCESS if the MAC address was set successfully
-* - XST_DEVICE_IS_STARTED if the device has not yet been stopped
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-XStatus
-XEmac_SetMacAddress(XEmac * InstancePtr, u8 * AddressPtr)
-{
- u32 MacAddr = 0;
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(AddressPtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /*
- * The device must be stopped before setting the MAC address
- */
- if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) {
- return XST_DEVICE_IS_STARTED;
- }
-
- /*
- * Set the device station address high and low registers
- */
- MacAddr = (AddressPtr[0] << 8) | AddressPtr[1];
- XIo_Out32(InstancePtr->BaseAddress + XEM_SAH_OFFSET, MacAddr);
-
- MacAddr = (AddressPtr[2] << 24) | (AddressPtr[3] << 16) |
- (AddressPtr[4] << 8) | AddressPtr[5];
-
- XIo_Out32(InstancePtr->BaseAddress + XEM_SAL_OFFSET, MacAddr);
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Get the MAC address for this driver/device.
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-* @param BufferPtr is an output parameter, and is a pointer to a buffer into
-* which the current MAC address will be copied. The buffer must be at
-* least 6 bytes.
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-void
-XEmac_GetMacAddress(XEmac * InstancePtr, u8 * BufferPtr)
-{
- u32 MacAddrHi;
- u32 MacAddrLo;
-
- XASSERT_VOID(InstancePtr != NULL);
- XASSERT_VOID(BufferPtr != NULL);
- XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- MacAddrHi = XIo_In32(InstancePtr->BaseAddress + XEM_SAH_OFFSET);
- MacAddrLo = XIo_In32(InstancePtr->BaseAddress + XEM_SAL_OFFSET);
-
- BufferPtr[0] = (u8) (MacAddrHi >> 8);
- BufferPtr[1] = (u8) MacAddrHi;
- BufferPtr[2] = (u8) (MacAddrLo >> 24);
- BufferPtr[3] = (u8) (MacAddrLo >> 16);
- BufferPtr[4] = (u8) (MacAddrLo >> 8);
- BufferPtr[5] = (u8) MacAddrLo;
-}
-
-/******************************************************************************/
-/**
-*
-* Configure DMA capabilities.
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-*
-* @return
-*
-* - XST_SUCCESS if successful initialization of DMA
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-static XStatus
-ConfigureDma(XEmac * InstancePtr)
-{
- XStatus Result;
-
- /*
- * Initialize the DMA channels with their base addresses. We assume
- * scatter-gather DMA is the only possible configuration. Descriptor space
- * will need to be set later by the upper layer.
- */
- Result = XDmaChannel_Initialize(&InstancePtr->RecvChannel,
- InstancePtr->BaseAddress +
- XEM_DMA_RECV_OFFSET);
- if (Result != XST_SUCCESS) {
- return Result;
- }
-
- Result = XDmaChannel_Initialize(&InstancePtr->SendChannel,
- InstancePtr->BaseAddress +
- XEM_DMA_SEND_OFFSET);
-
- return Result;
-}
-
-/******************************************************************************/
-/**
-*
-* Configure the send and receive FIFO components with their base addresses
-* and interrupt masks. Currently the base addresses are defined constants.
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-*
-* @return
-*
-* XST_SUCCESS if successful initialization of the packet FIFOs
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-static XStatus
-ConfigureFifo(XEmac * InstancePtr)
-{
- XStatus Result;
-
- /*
- * Return status from the packet FIFOs initialization is ignored since
- * they always return success.
- */
- Result = XPacketFifoV100b_Initialize(&InstancePtr->RecvFifo,
- InstancePtr->BaseAddress +
- XEM_PFIFO_RXREG_OFFSET,
- InstancePtr->BaseAddress +
- XEM_PFIFO_RXDATA_OFFSET);
- if (Result != XST_SUCCESS) {
- return Result;
- }
-
- Result = XPacketFifoV100b_Initialize(&InstancePtr->SendFifo,
- InstancePtr->BaseAddress +
- XEM_PFIFO_TXREG_OFFSET,
- InstancePtr->BaseAddress +
- XEM_PFIFO_TXDATA_OFFSET);
- return Result;
-}
-
-/******************************************************************************/
-/**
-*
-* This is a stub for the scatter-gather send and recv callbacks. The stub
-* is here in case the upper layers forget to set the handlers.
-*
-* @param CallBackRef is a pointer to the upper layer callback reference
-* @param BdPtr is a pointer to the first buffer descriptor in a list
-* @param NumBds is the number of descriptors in the list.
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-static void
-StubSgHandler(void *CallBackRef, XBufDescriptor * BdPtr, u32 NumBds)
-{
- XASSERT_VOID_ALWAYS();
-}
-
-/******************************************************************************/
-/**
-*
-* This is a stub for the non-DMA send and recv callbacks. The stub is here in
-* case the upper layers forget to set the handlers.
-*
-* @param CallBackRef is a pointer to the upper layer callback reference
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-static void
-StubFifoHandler(void *CallBackRef)
-{
- XASSERT_VOID_ALWAYS();
-}
-
-/******************************************************************************/
-/**
-*
-* This is a stub for the asynchronous error callback. The stub is here in
-* case the upper layers forget to set the handler.
-*
-* @param CallBackRef is a pointer to the upper layer callback reference
-* @param ErrorCode is the Xilinx error code, indicating the cause of the error
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-static void
-StubErrorHandler(void *CallBackRef, XStatus ErrorCode)
-{
- XASSERT_VOID_ALWAYS();
-}
-
-/*****************************************************************************/
-/**
-*
-* Lookup the device configuration based on the unique device ID. The table
-* EmacConfigTable contains the configuration info for each device in the system.
-*
-* @param DeviceId is the unique device ID of the device being looked up.
-*
-* @return
-*
-* A pointer to the configuration table entry corresponding to the given
-* device ID, or NULL if no match is found.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-XEmac_Config *
-XEmac_LookupConfig(u16 DeviceId)
-{
- XEmac_Config *CfgPtr = NULL;
- int i;
-
- for (i = 0; i < XPAR_XEMAC_NUM_INSTANCES; i++) {
- if (XEmac_ConfigTable[i].DeviceId == DeviceId) {
- CfgPtr = &XEmac_ConfigTable[i];
- break;
- }
- }
-
- return CfgPtr;
-}
+++ /dev/null
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xemac.h
-*
-* The Xilinx Ethernet driver component. This component supports the Xilinx
-* Ethernet 10/100 MAC (EMAC).
-*
-* The Xilinx Ethernet 10/100 MAC supports the following features:
-* - Simple and scatter-gather DMA operations, as well as simple memory
-* mapped direct I/O interface (FIFOs).
-* - Media Independent Interface (MII) for connection to external
-* 10/100 Mbps PHY transceivers.
-* - MII management control reads and writes with MII PHYs
-* - Independent internal transmit and receive FIFOs
-* - CSMA/CD compliant operations for half-duplex modes
-* - Programmable PHY reset signal
-* - Unicast, broadcast, and promiscuous address filtering (no multicast yet)
-* - Internal loopback
-* - Automatic source address insertion or overwrite (programmable)
-* - Automatic FCS insertion and stripping (programmable)
-* - Automatic pad insertion and stripping (programmable)
-* - Pause frame (flow control) detection in full-duplex mode
-* - Programmable interframe gap
-* - VLAN frame support.
-* - Pause frame support
-*
-* The device driver supports all the features listed above.
-*
-* <b>Driver Description</b>
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate to the EMAC. The driver handles transmission and reception of
-* Ethernet frames, as well as configuration of the controller. It does not
-* handle protocol stack functionality such as Link Layer Control (LLC) or the
-* Address Resolution Protocol (ARP). The protocol stack that makes use of the
-* driver handles this functionality. This implies that the driver is simply a
-* pass-through mechanism between a protocol stack and the EMAC. A single device
-* driver can support multiple EMACs.
-*
-* The driver is designed for a zero-copy buffer scheme. That is, the driver will
-* not copy buffers. This avoids potential throughput bottlenecks within the
-* driver.
-*
-* Since the driver is a simple pass-through mechanism between a protocol stack
-* and the EMAC, no assembly or disassembly of Ethernet frames is done at the
-* driver-level. This assumes that the protocol stack passes a correctly
-* formatted Ethernet frame to the driver for transmission, and that the driver
-* does not validate the contents of an incoming frame
-*
-* <b>PHY Communication</b>
-*
-* The driver provides rudimentary read and write functions to allow the higher
-* layer software to access the PHY. The EMAC provides MII registers for the
-* driver to access. This management interface can be parameterized away in the
-* FPGA implementation process. If this is the case, the PHY read and write
-* functions of the driver return XST_NO_FEATURE.
-*
-* External loopback is usually supported at the PHY. It is up to the user to
-* turn external loopback on or off at the PHY. The driver simply provides pass-
-* through functions for configuring the PHY. The driver does not read, write,
-* or reset the PHY on its own. All control of the PHY must be done by the user.
-*
-* <b>Asynchronous Callbacks</b>
-*
-* The driver services interrupts and passes Ethernet frames to the higher layer
-* software through asynchronous callback functions. When using the driver
-* directly (i.e., not with the RTOS protocol stack), the higher layer
-* software must register its callback functions during initialization. The
-* driver requires callback functions for received frames, for confirmation of
-* transmitted frames, and for asynchronous errors.
-*
-* <b>Interrupts</b>
-*
-* The driver has no dependencies on the interrupt controller. The driver
-* provides two interrupt handlers. XEmac_IntrHandlerDma() handles interrupts
-* when the EMAC is configured with scatter-gather DMA. XEmac_IntrHandlerFifo()
-* handles interrupts when the EMAC is configured for direct FIFO I/O or simple
-* DMA. Either of these routines can be connected to the system interrupt
-* controller by the user.
-*
-* <b>Interrupt Frequency</b>
-*
-* When the EMAC is configured with scatter-gather DMA, the frequency of
-* interrupts can be controlled with the interrupt coalescing features of the
-* scatter-gather DMA engine. The frequency of interrupts can be adjusted using
-* the driver API functions for setting the packet count threshold and the packet
-* wait bound values.
-*
-* The scatter-gather DMA engine only interrupts when the packet count threshold
-* is reached, instead of interrupting for each packet. A packet is a generic
-* term used by the scatter-gather DMA engine, and is equivalent to an Ethernet
-* frame in our case.
-*
-* The packet wait bound is a timer value used during interrupt coalescing to
-* trigger an interrupt when not enough packets have been received to reach the
-* packet count threshold.
-*
-* These values can be tuned by the user to meet their needs. If there appear to
-* be interrupt latency problems or delays in packet arrival that are longer than
-* might be expected, the user should verify that the packet count threshold is
-* set low enough to receive interrupts before the wait bound timer goes off.
-*
-* <b>Device Reset</b>
-*
-* Some errors that can occur in the device require a device reset. These errors
-* are listed in the XEmac_SetErrorHandler() function header. The user's error
-* handler is responsible for resetting the device and re-configuring it based on
-* its needs (the driver does not save the current configuration). When
-* integrating into an RTOS, these reset and re-configure obligations are
-* taken care of by the Xilinx adapter software if it exists for that RTOS.
-*
-* <b>Device Configuration</b>
-*
-* The device can be configured in various ways during the FPGA implementation
-* process. Configuration parameters are stored in the xemac_g.c files.
-* A table is defined where each entry contains configuration information
-* for an EMAC device. This information includes such things as the base address
-* of the memory-mapped device, the base addresses of IPIF, DMA, and FIFO modules
-* within the device, and whether the device has DMA, counter registers,
-* multicast support, MII support, and flow control.
-*
-* The driver tries to use the features built into the device. So if, for
-* example, the hardware is configured with scatter-gather DMA, the driver
-* expects to start the scatter-gather channels and expects that the user has set
-* up the buffer descriptor lists already. If the user expects to use the driver
-* in a mode different than how the hardware is configured, the user should
-* modify the configuration table to reflect the mode to be used. Modifying the
-* configuration table is a workaround for now until we get some experience with
-* how users are intending to use the hardware in its different configurations.
-* For example, if the hardware is built with scatter-gather DMA but the user is
-* intending to use only simple DMA, the user either needs to modify the config
-* table as a workaround or rebuild the hardware with only simple DMA. The
-* recommendation at this point is to build the hardware with the features you
-* intend to use. If you're inclined to modify the table, do so before the call
-* to XEmac_Initialize(). Here is a snippet of code that changes a device to
-* simple DMA (the hardware needs to have DMA for this to work of course):
-* <pre>
-* XEmac_Config *ConfigPtr;
-*
-* ConfigPtr = XEmac_LookupConfig(DeviceId);
-* ConfigPtr->IpIfDmaConfig = XEM_CFG_SIMPLE_DMA;
-* </pre>
-*
-* <b>Simple DMA</b>
-*
-* Simple DMA is supported through the FIFO functions, FifoSend and FifoRecv, of
-* the driver (i.e., there is no separate interface for it). The driver makes use
-* of the DMA engine for a simple DMA transfer if the device is configured with
-* DMA, otherwise it uses the FIFOs directly. While the simple DMA interface is
-* therefore transparent to the user, the caching of network buffers is not.
-* If the device is configured with DMA and the FIFO interface is used, the user
-* must ensure that the network buffers are not cached or are cache coherent,
-* since DMA will be used to transfer to and from the Emac device. If the device
-* is configured with DMA and the user really wants to use the FIFOs directly,
-* the user should rebuild the hardware without DMA. If unable to do this, there
-* is a workaround (described above in Device Configuration) to modify the
-* configuration table of the driver to fake the driver into thinking the device
-* has no DMA. A code snippet follows:
-* <pre>
-* XEmac_Config *ConfigPtr;
-*
-* ConfigPtr = XEmac_LookupConfig(DeviceId);
-* ConfigPtr->IpIfDmaConfig = XEM_CFG_NO_DMA;
-* </pre>
-*
-* <b>Asserts</b>
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-* <b>Building the driver</b>
-*
-* The XEmac driver is composed of several source files. Why so many? This
-* allows the user to build and link only those parts of the driver that are
-* necessary. Since the EMAC hardware can be configured in various ways (e.g.,
-* with or without DMA), the driver too can be built with varying features.
-* For the most part, this means that besides always linking in xemac.c, you
-* link in only the driver functionality you want. Some of the choices you have
-* are polled vs. interrupt, interrupt with FIFOs only vs. interrupt with DMA,
-* self-test diagnostics, and driver statistics. Note that currently the DMA code
-* must be linked in, even if you don't have DMA in the device.
-*
-* @note
-*
-* Xilinx drivers are typically composed of two components, one is the driver
-* and the other is the adapter. The driver is independent of OS and processor
-* and is intended to be highly portable. The adapter is OS-specific and
-* facilitates communication between the driver and an OS.
-* <br><br>
-* This driver is intended to be RTOS and processor independent. It works
-* with physical addresses only. Any needs for dynamic memory management,
-* threads or thread mutual exclusion, virtual memory, or cache control must
-* be satisfied by the layer above this driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a rpm 07/31/01 First release
-* 1.00b rpm 02/20/02 Repartitioned files and functions
-* 1.00b rpm 10/08/02 Replaced HasSgDma boolean with IpifDmaConfig enumerated
-* configuration parameter
-* 1.00c rpm 12/05/02 New version includes support for simple DMA and the delay
-* argument to SgSend
-* 1.00c rpm 02/03/03 The XST_DMA_SG_COUNT_EXCEEDED return code was removed
-* from SetPktThreshold in the internal DMA driver. Also
-* avoided compiler warnings by initializing Result in the
-* DMA interrupt service routines.
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XEMAC_H /* prevent circular inclusions */
-#define XEMAC_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include <config.h>
-#include "xbasic_types.h"
-#include "xstatus.h"
-#include "xpacket_fifo_v1_00_b.h" /* Uses v1.00b of Packet Fifo */
-#include "xdma_channel.h"
-
-/************************** Constant Definitions *****************************/
-
-/*
- * Device information
- */
-#define XEM_DEVICE_NAME "xemac"
-#define XEM_DEVICE_DESC "Xilinx Ethernet 10/100 MAC"
-
-/** @name Configuration options
- *
- * Device configuration options (see the XEmac_SetOptions() and
- * XEmac_GetOptions() for information on how to use these options)
- * @{
- */
-/**
- * <pre>
- * XEM_BROADCAST_OPTION Broadcast addressing on or off (default is on)
- * XEM_UNICAST_OPTION Unicast addressing on or off (default is on)
- * XEM_PROMISC_OPTION Promiscuous addressing on or off (default is off)
- * XEM_FDUPLEX_OPTION Full duplex on or off (default is off)
- * XEM_POLLED_OPTION Polled mode on or off (default is off)
- * XEM_LOOPBACK_OPTION Internal loopback on or off (default is off)
- * XEM_FLOW_CONTROL_OPTION Interpret pause frames in full duplex mode
- * (default is off)
- * XEM_INSERT_PAD_OPTION Pad short frames on transmit (default is on)
- * XEM_INSERT_FCS_OPTION Insert FCS (CRC) on transmit (default is on)
- * XEM_INSERT_ADDR_OPTION Insert source address on transmit (default is on)
- * XEM_OVWRT_ADDR_OPTION Overwrite source address on transmit. This is
- * only used if source address insertion is on.
- * (default is on)
- * XEM_STRIP_PAD_FCS_OPTION Strip FCS and padding from received frames
- * (default is off)
- * </pre>
- */
-#define XEM_UNICAST_OPTION 0x00000001UL
-#define XEM_BROADCAST_OPTION 0x00000002UL
-#define XEM_PROMISC_OPTION 0x00000004UL
-#define XEM_FDUPLEX_OPTION 0x00000008UL
-#define XEM_POLLED_OPTION 0x00000010UL
-#define XEM_LOOPBACK_OPTION 0x00000020UL
-#define XEM_FLOW_CONTROL_OPTION 0x00000080UL
-#define XEM_INSERT_PAD_OPTION 0x00000100UL
-#define XEM_INSERT_FCS_OPTION 0x00000200UL
-#define XEM_INSERT_ADDR_OPTION 0x00000400UL
-#define XEM_OVWRT_ADDR_OPTION 0x00000800UL
-#define XEM_STRIP_PAD_FCS_OPTION 0x00002000UL
-/*@}*/
-/*
- * Not supported yet:
- * XEM_MULTICAST_OPTION Multicast addressing on or off (default is off)
- */
-/* NOT SUPPORTED YET... */
-#define XEM_MULTICAST_OPTION 0x00000040UL
-
-/*
- * Some default values for interrupt coalescing within the scatter-gather
- * DMA engine.
- */
-#define XEM_SGDMA_DFT_THRESHOLD 1 /* Default pkt threshold */
-#define XEM_SGDMA_MAX_THRESHOLD 255 /* Maximum pkt theshold */
-#define XEM_SGDMA_DFT_WAITBOUND 5 /* Default pkt wait bound (msec) */
-#define XEM_SGDMA_MAX_WAITBOUND 1023 /* Maximum pkt wait bound (msec) */
-
-/*
- * Direction identifiers. These are used for setting values like packet
- * thresholds and wait bound for specific channels
- */
-#define XEM_SEND 1
-#define XEM_RECV 2
-
-/*
- * Arguments to SgSend function to indicate whether to hold off starting
- * the scatter-gather engine.
- */
-#define XEM_SGDMA_NODELAY 0 /* start SG DMA immediately */
-#define XEM_SGDMA_DELAY 1 /* do not start SG DMA */
-
-/*
- * Constants to determine the configuration of the hardware device. They are
- * used to allow the driver to verify it can operate with the hardware.
- */
-#define XEM_CFG_NO_IPIF 0 /* Not supported by the driver */
-#define XEM_CFG_NO_DMA 1 /* No DMA */
-#define XEM_CFG_SIMPLE_DMA 2 /* Simple DMA */
-#define XEM_CFG_DMA_SG 3 /* DMA scatter gather */
-
-/*
- * The next few constants help upper layers determine the size of memory
- * pools used for Ethernet buffers and descriptor lists.
- */
-#define XEM_MAC_ADDR_SIZE 6 /* six-byte MAC address */
-#define XEM_MTU 1500 /* max size of Ethernet frame */
-#define XEM_HDR_SIZE 14 /* size of Ethernet header */
-#define XEM_HDR_VLAN_SIZE 18 /* size of Ethernet header with VLAN */
-#define XEM_TRL_SIZE 4 /* size of Ethernet trailer (FCS) */
-#define XEM_MAX_FRAME_SIZE (XEM_MTU + XEM_HDR_SIZE + XEM_TRL_SIZE)
-#define XEM_MAX_VLAN_FRAME_SIZE (XEM_MTU + XEM_HDR_VLAN_SIZE + XEM_TRL_SIZE)
-
-/*
- * Define a default number of send and receive buffers
- */
-#define XEM_MIN_RECV_BUFS 32 /* minimum # of recv buffers */
-#define XEM_DFT_RECV_BUFS 64 /* default # of recv buffers */
-
-#define XEM_MIN_SEND_BUFS 16 /* minimum # of send buffers */
-#define XEM_DFT_SEND_BUFS 32 /* default # of send buffers */
-
-#define XEM_MIN_BUFFERS (XEM_MIN_RECV_BUFS + XEM_MIN_SEND_BUFS)
-#define XEM_DFT_BUFFERS (XEM_DFT_RECV_BUFS + XEM_DFT_SEND_BUFS)
-
-/*
- * Define the number of send and receive buffer descriptors, used for
- * scatter-gather DMA
- */
-#define XEM_MIN_RECV_DESC 16 /* minimum # of recv descriptors */
-#define XEM_DFT_RECV_DESC 32 /* default # of recv descriptors */
-
-#define XEM_MIN_SEND_DESC 8 /* minimum # of send descriptors */
-#define XEM_DFT_SEND_DESC 16 /* default # of send descriptors */
-
-/**************************** Type Definitions *******************************/
-
-/**
- * Ethernet statistics (see XEmac_GetStats() and XEmac_ClearStats())
- */
-typedef struct {
- u32 XmitFrames; /**< Number of frames transmitted */
- u32 XmitBytes; /**< Number of bytes transmitted */
- u32 XmitLateCollisionErrors;
- /**< Number of transmission failures
- due to late collisions */
- u32 XmitExcessDeferral; /**< Number of transmission failures
- due o excess collision deferrals */
- u32 XmitOverrunErrors; /**< Number of transmit overrun errors */
- u32 XmitUnderrunErrors; /**< Number of transmit underrun errors */
- u32 RecvFrames; /**< Number of frames received */
- u32 RecvBytes; /**< Number of bytes received */
- u32 RecvFcsErrors; /**< Number of frames discarded due
- to FCS errors */
- u32 RecvAlignmentErrors; /**< Number of frames received with
- alignment errors */
- u32 RecvOverrunErrors; /**< Number of frames discarded due
- to overrun errors */
- u32 RecvUnderrunErrors; /**< Number of recv underrun errors */
- u32 RecvMissedFrameErrors;
- /**< Number of frames missed by MAC */
- u32 RecvCollisionErrors; /**< Number of frames discarded due
- to collisions */
- u32 RecvLengthFieldErrors;
- /**< Number of frames discarded with
- invalid length field */
- u32 RecvShortErrors; /**< Number of short frames discarded */
- u32 RecvLongErrors; /**< Number of long frames discarded */
- u32 DmaErrors; /**< Number of DMA errors since init */
- u32 FifoErrors; /**< Number of FIFO errors since init */
- u32 RecvInterrupts; /**< Number of receive interrupts */
- u32 XmitInterrupts; /**< Number of transmit interrupts */
- u32 EmacInterrupts; /**< Number of MAC (device) interrupts */
- u32 TotalIntrs; /**< Total interrupts */
-} XEmac_Stats;
-
-/**
- * This typedef contains configuration information for a device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Register base address */
- u32 HasCounters; /**< Does device have counters? */
- u8 IpIfDmaConfig; /**< IPIF/DMA hardware configuration */
- u32 HasMii; /**< Does device support MII? */
-
-} XEmac_Config;
-
-/** @name Typedefs for callbacks
- * Callback functions.
- * @{
- */
-/**
- * Callback when data is sent or received with scatter-gather DMA.
- *
- * @param CallBackRef is a callback reference passed in by the upper layer
- * when setting the callback functions, and passed back to the upper
- * layer when the callback is invoked.
- * @param BdPtr is a pointer to the first buffer descriptor in a list of
- * buffer descriptors.
- * @param NumBds is the number of buffer descriptors in the list pointed
- * to by BdPtr.
- */
-typedef void (*XEmac_SgHandler) (void *CallBackRef, XBufDescriptor * BdPtr,
- u32 NumBds);
-
-/**
- * Callback when data is sent or received with direct FIFO communication or
- * simple DMA. The user typically defines two callacks, one for send and one
- * for receive.
- *
- * @param CallBackRef is a callback reference passed in by the upper layer
- * when setting the callback functions, and passed back to the upper
- * layer when the callback is invoked.
- */
-typedef void (*XEmac_FifoHandler) (void *CallBackRef);
-
-/**
- * Callback when an asynchronous error occurs.
- *
- * @param CallBackRef is a callback reference passed in by the upper layer
- * when setting the callback functions, and passed back to the upper
- * layer when the callback is invoked.
- * @param ErrorCode is a Xilinx error code defined in xstatus.h. Also see
- * XEmac_SetErrorHandler() for a description of possible errors.
- */
-typedef void (*XEmac_ErrorHandler) (void *CallBackRef, XStatus ErrorCode);
-/*@}*/
-
-/**
- * The XEmac driver instance data. The user is required to allocate a
- * variable of this type for every EMAC device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- u32 BaseAddress; /* Base address (of IPIF) */
- u32 IsStarted; /* Device is currently started */
- u32 IsReady; /* Device is initialized and ready */
- u32 IsPolled; /* Device is in polled mode */
- u8 IpIfDmaConfig; /* IPIF/DMA hardware configuration */
- u32 HasMii; /* Does device support MII? */
- u32 HasMulticastHash; /* Does device support multicast hash table? */
-
- XEmac_Stats Stats;
- XPacketFifoV100b RecvFifo; /* FIFO used to receive frames */
- XPacketFifoV100b SendFifo; /* FIFO used to send frames */
-
- /*
- * Callbacks
- */
- XEmac_FifoHandler FifoRecvHandler; /* for non-DMA/simple DMA interrupts */
- void *FifoRecvRef;
- XEmac_FifoHandler FifoSendHandler; /* for non-DMA/simple DMA interrupts */
- void *FifoSendRef;
- XEmac_ErrorHandler ErrorHandler; /* for asynchronous errors */
- void *ErrorRef;
-
- XDmaChannel RecvChannel; /* DMA receive channel driver */
- XDmaChannel SendChannel; /* DMA send channel driver */
-
- XEmac_SgHandler SgRecvHandler; /* callback for scatter-gather DMA */
- void *SgRecvRef;
- XEmac_SgHandler SgSendHandler; /* callback for scatter-gather DMA */
- void *SgSendRef;
-} XEmac;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
-*
-* This macro determines if the device is currently configured for
-* scatter-gather DMA.
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-*
-* @return
-*
-* Boolean TRUE if the device is configured for scatter-gather DMA, or FALSE
-* if it is not.
-*
-* @note
-*
-* Signature: u32 XEmac_mIsSgDma(XEmac *InstancePtr)
-*
-******************************************************************************/
-#define XEmac_mIsSgDma(InstancePtr) \
- ((InstancePtr)->IpIfDmaConfig == XEM_CFG_DMA_SG)
-
-/*****************************************************************************/
-/**
-*
-* This macro determines if the device is currently configured for simple DMA.
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-*
-* @return
-*
-* Boolean TRUE if the device is configured for simple DMA, or FALSE otherwise
-*
-* @note
-*
-* Signature: u32 XEmac_mIsSimpleDma(XEmac *InstancePtr)
-*
-******************************************************************************/
-#define XEmac_mIsSimpleDma(InstancePtr) \
- ((InstancePtr)->IpIfDmaConfig == XEM_CFG_SIMPLE_DMA)
-
-/*****************************************************************************/
-/**
-*
-* This macro determines if the device is currently configured with DMA (either
-* simple DMA or scatter-gather DMA)
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-*
-* @return
-*
-* Boolean TRUE if the device is configured with DMA, or FALSE otherwise
-*
-* @note
-*
-* Signature: u32 XEmac_mIsDma(XEmac *InstancePtr)
-*
-******************************************************************************/
-#define XEmac_mIsDma(InstancePtr) \
- (XEmac_mIsSimpleDma(InstancePtr) || XEmac_mIsSgDma(InstancePtr))
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Initialization functions in xemac.c
- */
-XStatus XEmac_Initialize(XEmac * InstancePtr, u16 DeviceId);
-XStatus XEmac_Start(XEmac * InstancePtr);
-XStatus XEmac_Stop(XEmac * InstancePtr);
-void XEmac_Reset(XEmac * InstancePtr);
-XEmac_Config *XEmac_LookupConfig(u16 DeviceId);
-
-/*
- * Diagnostic functions in xemac_selftest.c
- */
-XStatus XEmac_SelfTest(XEmac * InstancePtr);
-
-/*
- * Polled functions in xemac_polled.c
- */
-XStatus XEmac_PollSend(XEmac * InstancePtr, u8 * BufPtr, u32 ByteCount);
-XStatus XEmac_PollRecv(XEmac * InstancePtr, u8 * BufPtr, u32 * ByteCountPtr);
-
-/*
- * Interrupts with scatter-gather DMA functions in xemac_intr_dma.c
- */
-XStatus XEmac_SgSend(XEmac * InstancePtr, XBufDescriptor * BdPtr, int Delay);
-XStatus XEmac_SgRecv(XEmac * InstancePtr, XBufDescriptor * BdPtr);
-XStatus XEmac_SetPktThreshold(XEmac * InstancePtr, u32 Direction, u8 Threshold);
-XStatus XEmac_GetPktThreshold(XEmac * InstancePtr, u32 Direction,
- u8 * ThreshPtr);
-XStatus XEmac_SetPktWaitBound(XEmac * InstancePtr, u32 Direction,
- u32 TimerValue);
-XStatus XEmac_GetPktWaitBound(XEmac * InstancePtr, u32 Direction,
- u32 * WaitPtr);
-XStatus XEmac_SetSgRecvSpace(XEmac * InstancePtr, u32 * MemoryPtr,
- u32 ByteCount);
-XStatus XEmac_SetSgSendSpace(XEmac * InstancePtr, u32 * MemoryPtr,
- u32 ByteCount);
-void XEmac_SetSgRecvHandler(XEmac * InstancePtr, void *CallBackRef,
- XEmac_SgHandler FuncPtr);
-void XEmac_SetSgSendHandler(XEmac * InstancePtr, void *CallBackRef,
- XEmac_SgHandler FuncPtr);
-
-void XEmac_IntrHandlerDma(void *InstancePtr); /* interrupt handler */
-
-/*
- * Interrupts with direct FIFO functions in xemac_intr_fifo.c. Also used
- * for simple DMA.
- */
-XStatus XEmac_FifoSend(XEmac * InstancePtr, u8 * BufPtr, u32 ByteCount);
-XStatus XEmac_FifoRecv(XEmac * InstancePtr, u8 * BufPtr, u32 * ByteCountPtr);
-void XEmac_SetFifoRecvHandler(XEmac * InstancePtr, void *CallBackRef,
- XEmac_FifoHandler FuncPtr);
-void XEmac_SetFifoSendHandler(XEmac * InstancePtr, void *CallBackRef,
- XEmac_FifoHandler FuncPtr);
-
-void XEmac_IntrHandlerFifo(void *InstancePtr); /* interrupt handler */
-
-/*
- * General interrupt-related functions in xemac_intr.c
- */
-void XEmac_SetErrorHandler(XEmac * InstancePtr, void *CallBackRef,
- XEmac_ErrorHandler FuncPtr);
-
-/*
- * MAC configuration in xemac_options.c
- */
-XStatus XEmac_SetOptions(XEmac * InstancePtr, u32 OptionFlag);
-u32 XEmac_GetOptions(XEmac * InstancePtr);
-XStatus XEmac_SetMacAddress(XEmac * InstancePtr, u8 * AddressPtr);
-void XEmac_GetMacAddress(XEmac * InstancePtr, u8 * BufferPtr);
-XStatus XEmac_SetInterframeGap(XEmac * InstancePtr, u8 Part1, u8 Part2);
-void XEmac_GetInterframeGap(XEmac * InstancePtr, u8 * Part1Ptr, u8 * Part2Ptr);
-
-/*
- * Multicast functions in xemac_multicast.c (not supported by EMAC yet)
- */
-XStatus XEmac_MulticastAdd(XEmac * InstancePtr, u8 * AddressPtr);
-XStatus XEmac_MulticastClear(XEmac * InstancePtr);
-
-/*
- * PHY configuration in xemac_phy.c
- */
-XStatus XEmac_PhyRead(XEmac * InstancePtr, u32 PhyAddress,
- u32 RegisterNum, u16 * PhyDataPtr);
-XStatus XEmac_PhyWrite(XEmac * InstancePtr, u32 PhyAddress,
- u32 RegisterNum, u16 PhyData);
-
-/*
- * Statistics in xemac_stats.c
- */
-void XEmac_GetStats(XEmac * InstancePtr, XEmac_Stats * StatsPtr);
-void XEmac_ClearStats(XEmac * InstancePtr);
-
-#endif /* end of protection macro */
+++ /dev/null
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by libgen.
-* Version: Xilinx EDK 6.1.2 EDK_G.14
-* DO NOT EDIT.
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include <config.h>
-#include "xemac.h"
-
-/*
-* The configuration table for devices
-*/
-
-XEmac_Config XEmac_ConfigTable[] = {
- {
- XPAR_OPB_ETHERNET_0_DEVICE_ID,
- XPAR_OPB_ETHERNET_0_BASEADDR,
- XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST,
- XPAR_OPB_ETHERNET_0_DMA_PRESENT,
- XPAR_OPB_ETHERNET_0_MII_EXIST}
-};
+++ /dev/null
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xemac_i.h
-*
-* This header file contains internal identifiers, which are those shared
-* between XEmac components. The identifiers in this file are not intended for
-* use external to the driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rpm 07/31/01 First release
-* 1.00b rpm 02/20/02 Repartitioned files and functions
-* 1.00b rpm 04/29/02 Moved register definitions to xemac_l.h
-* 1.00c rpm 12/05/02 New version includes support for simple DMA
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XEMAC_I_H /* prevent circular inclusions */
-#define XEMAC_I_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xemac.h"
-#include "xemac_l.h"
-
-/************************** Constant Definitions *****************************/
-
-/*
- * Default buffer descriptor control word masks. The default send BD control
- * is set for incrementing the source address by one for each byte transferred,
- * and specify that the destination address (FIFO) is local to the device. The
- * default receive BD control is set for incrementing the destination address
- * by one for each byte transferred, and specify that the source address is
- * local to the device.
- */
-#define XEM_DFT_SEND_BD_MASK (XDC_DMACR_SOURCE_INCR_MASK | \
- XDC_DMACR_DEST_LOCAL_MASK)
-#define XEM_DFT_RECV_BD_MASK (XDC_DMACR_DEST_INCR_MASK | \
- XDC_DMACR_SOURCE_LOCAL_MASK)
-
-/*
- * Masks for the IPIF Device Interrupt enable and status registers.
- */
-#define XEM_IPIF_EMAC_MASK 0x00000004UL /* MAC interrupt */
-#define XEM_IPIF_SEND_DMA_MASK 0x00000008UL /* Send DMA interrupt */
-#define XEM_IPIF_RECV_DMA_MASK 0x00000010UL /* Receive DMA interrupt */
-#define XEM_IPIF_RECV_FIFO_MASK 0x00000020UL /* Receive FIFO interrupt */
-#define XEM_IPIF_SEND_FIFO_MASK 0x00000040UL /* Send FIFO interrupt */
-
-/*
- * Default IPIF Device Interrupt mask when configured for DMA
- */
-#define XEM_IPIF_DMA_DFT_MASK (XEM_IPIF_SEND_DMA_MASK | \
- XEM_IPIF_RECV_DMA_MASK | \
- XEM_IPIF_EMAC_MASK | \
- XEM_IPIF_SEND_FIFO_MASK | \
- XEM_IPIF_RECV_FIFO_MASK)
-
-/*
- * Default IPIF Device Interrupt mask when configured without DMA
- */
-#define XEM_IPIF_FIFO_DFT_MASK (XEM_IPIF_EMAC_MASK | \
- XEM_IPIF_SEND_FIFO_MASK | \
- XEM_IPIF_RECV_FIFO_MASK)
-
-#define XEM_IPIF_DMA_DEV_INTR_COUNT 7 /* Number of interrupt sources */
-#define XEM_IPIF_FIFO_DEV_INTR_COUNT 5 /* Number of interrupt sources */
-#define XEM_IPIF_DEVICE_INTR_COUNT 7 /* Number of interrupt sources */
-#define XEM_IPIF_IP_INTR_COUNT 22 /* Number of MAC interrupts */
-
-/* a mask for all transmit interrupts, used in polled mode */
-#define XEM_EIR_XMIT_ALL_MASK (XEM_EIR_XMIT_DONE_MASK | \
- XEM_EIR_XMIT_ERROR_MASK | \
- XEM_EIR_XMIT_SFIFO_EMPTY_MASK | \
- XEM_EIR_XMIT_LFIFO_FULL_MASK)
-
-/* a mask for all receive interrupts, used in polled mode */
-#define XEM_EIR_RECV_ALL_MASK (XEM_EIR_RECV_DONE_MASK | \
- XEM_EIR_RECV_ERROR_MASK | \
- XEM_EIR_RECV_LFIFO_EMPTY_MASK | \
- XEM_EIR_RECV_LFIFO_OVER_MASK | \
- XEM_EIR_RECV_LFIFO_UNDER_MASK | \
- XEM_EIR_RECV_DFIFO_OVER_MASK | \
- XEM_EIR_RECV_MISSED_FRAME_MASK | \
- XEM_EIR_RECV_COLLISION_MASK | \
- XEM_EIR_RECV_FCS_ERROR_MASK | \
- XEM_EIR_RECV_LEN_ERROR_MASK | \
- XEM_EIR_RECV_SHORT_ERROR_MASK | \
- XEM_EIR_RECV_LONG_ERROR_MASK | \
- XEM_EIR_RECV_ALIGN_ERROR_MASK)
-
-/* a default interrupt mask for scatter-gather DMA operation */
-#define XEM_EIR_DFT_SG_MASK (XEM_EIR_RECV_ERROR_MASK | \
- XEM_EIR_RECV_LFIFO_OVER_MASK | \
- XEM_EIR_RECV_LFIFO_UNDER_MASK | \
- XEM_EIR_XMIT_SFIFO_OVER_MASK | \
- XEM_EIR_XMIT_SFIFO_UNDER_MASK | \
- XEM_EIR_XMIT_LFIFO_OVER_MASK | \
- XEM_EIR_XMIT_LFIFO_UNDER_MASK | \
- XEM_EIR_RECV_DFIFO_OVER_MASK | \
- XEM_EIR_RECV_MISSED_FRAME_MASK | \
- XEM_EIR_RECV_COLLISION_MASK | \
- XEM_EIR_RECV_FCS_ERROR_MASK | \
- XEM_EIR_RECV_LEN_ERROR_MASK | \
- XEM_EIR_RECV_SHORT_ERROR_MASK | \
- XEM_EIR_RECV_LONG_ERROR_MASK | \
- XEM_EIR_RECV_ALIGN_ERROR_MASK)
-
-/* a default interrupt mask for non-DMA operation (direct FIFOs) */
-#define XEM_EIR_DFT_FIFO_MASK (XEM_EIR_XMIT_DONE_MASK | \
- XEM_EIR_RECV_DONE_MASK | \
- XEM_EIR_DFT_SG_MASK)
-
-/*
- * Mask for the DMA interrupt enable and status registers when configured
- * for scatter-gather DMA.
- */
-#define XEM_DMA_SG_INTR_MASK (XDC_IXR_DMA_ERROR_MASK | \
- XDC_IXR_PKT_THRESHOLD_MASK | \
- XDC_IXR_PKT_WAIT_BOUND_MASK | \
- XDC_IXR_SG_END_MASK)
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/*
-*
-* Clears a structure of given size, in bytes, by setting each byte to 0.
-*
-* @param StructPtr is a pointer to the structure to be cleared.
-* @param NumBytes is the number of bytes in the structure.
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* Signature: void XEmac_mClearStruct(u8 *StructPtr, unsigned int NumBytes)
-*
-******************************************************************************/
-#define XEmac_mClearStruct(StructPtr, NumBytes) \
-{ \
- int i; \
- u8 *BytePtr = (u8 *)(StructPtr); \
- for (i=0; i < (unsigned int)(NumBytes); i++) \
- { \
- *BytePtr++ = 0; \
- } \
-}
-
-/************************** Variable Definitions *****************************/
-
-extern XEmac_Config XEmac_ConfigTable[];
-
-/************************** Function Prototypes ******************************/
-
-void XEmac_CheckEmacError(XEmac * InstancePtr, u32 IntrStatus);
-void XEmac_CheckFifoRecvError(XEmac * InstancePtr);
-void XEmac_CheckFifoSendError(XEmac * InstancePtr);
-
-#endif /* end of protection macro */
+++ /dev/null
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xemac_intr.c
-*
-* This file contains general interrupt-related functions of the XEmac driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rpm 07/31/01 First release
-* 1.00b rpm 02/20/02 Repartitioned files and functions
-* 1.00c rpm 12/05/02 New version includes support for simple DMA
-* 1.00c rpm 03/31/03 Added comment to indicate that no Receive Length FIFO
-* overrun interrupts occur in v1.00l and later of the EMAC
-* device. This avoids the need to reset the device on
-* receive overruns.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xbasic_types.h"
-#include "xemac_i.h"
-#include "xio.h"
-#include "xipif_v1_23_b.h" /* Uses v1.23b of the IPIF */
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-*
-* Set the callback function for handling asynchronous errors. The upper layer
-* software should call this function during initialization.
-*
-* The error callback is invoked by the driver within interrupt context, so it
-* needs to do its job quickly. If there are potentially slow operations within
-* the callback, these should be done at task-level.
-*
-* The Xilinx errors that must be handled by the callback are:
-* - XST_DMA_ERROR indicates an unrecoverable DMA error occurred. This is
-* typically a bus error or bus timeout. The handler must reset and
-* re-configure the device.
-* - XST_FIFO_ERROR indicates an unrecoverable FIFO error occurred. This is a
-* deadlock condition in the packet FIFO. The handler must reset and
-* re-configure the device.
-* - XST_RESET_ERROR indicates an unrecoverable MAC error occurred, usually an
-* overrun or underrun. The handler must reset and re-configure the device.
-* - XST_DMA_SG_NO_LIST indicates an attempt was made to access a scatter-gather
-* DMA list that has not yet been created.
-* - XST_DMA_SG_LIST_EMPTY indicates the driver tried to get a descriptor from
-* the receive descriptor list, but the list was empty.
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-* @param CallBackRef is a reference pointer to be passed back to the adapter in
-* the callback. This helps the adapter correlate the callback to a
-* particular driver.
-* @param FuncPtr is the pointer to the callback function.
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-void
-XEmac_SetErrorHandler(XEmac * InstancePtr, void *CallBackRef,
- XEmac_ErrorHandler FuncPtr)
-{
- XASSERT_VOID(InstancePtr != NULL);
- XASSERT_VOID(FuncPtr != NULL);
- XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- InstancePtr->ErrorHandler = FuncPtr;
- InstancePtr->ErrorRef = CallBackRef;
-}
-
-/****************************************************************************/
-/*
-*
-* Check the interrupt status bits of the Ethernet MAC for errors. Errors
-* currently handled are:
-* - Receive length FIFO overrun. Indicates data was lost due to the receive
-* length FIFO becoming full during the reception of a packet. Only a device
-* reset clears this condition.
-* - Receive length FIFO underrun. An attempt to read an empty FIFO. Only a
-* device reset clears this condition.
-* - Transmit status FIFO overrun. Indicates data was lost due to the transmit
-* status FIFO becoming full following the transmission of a packet. Only a
-* device reset clears this condition.
-* - Transmit status FIFO underrun. An attempt to read an empty FIFO. Only a
-* device reset clears this condition.
-* - Transmit length FIFO overrun. Indicates data was lost due to the transmit
-* length FIFO becoming full following the transmission of a packet. Only a
-* device reset clears this condition.
-* - Transmit length FIFO underrun. An attempt to read an empty FIFO. Only a
-* device reset clears this condition.
-* - Receive data FIFO overrun. Indicates data was lost due to the receive data
-* FIFO becoming full during the reception of a packet.
-* - Receive data errors:
-* - Receive missed frame error. Valid data was lost by the MAC.
-* - Receive collision error. Data was lost by the MAC due to a collision.
-* - Receive FCS error. Data was dicarded by the MAC due to FCS error.
-* - Receive length field error. Data was dicarded by the MAC due to an invalid
-* length field in the packet.
-* - Receive short error. Data was dicarded by the MAC because a packet was
-* shorter than allowed.
-* - Receive long error. Data was dicarded by the MAC because a packet was
-* longer than allowed.
-* - Receive alignment error. Data was truncated by the MAC because its length
-* was not byte-aligned.
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-* @param IntrStatus is the contents of the interrupt status register to be checked
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* This function is intended for internal use only.
-*
-******************************************************************************/
-void
-XEmac_CheckEmacError(XEmac * InstancePtr, u32 IntrStatus)
-{
- u32 ResetError = FALSE;
-
- /*
- * First check for receive fifo overrun/underrun errors. Most require a
- * reset by the user to clear, but the data FIFO overrun error does not.
- */
- if (IntrStatus & XEM_EIR_RECV_DFIFO_OVER_MASK) {
- InstancePtr->Stats.RecvOverrunErrors++;
- InstancePtr->Stats.FifoErrors++;
- }
-
- if (IntrStatus & XEM_EIR_RECV_LFIFO_OVER_MASK) {
- /*
- * Receive Length FIFO overrun interrupts no longer occur in v1.00l
- * and later of the EMAC device. Frames are just dropped by the EMAC
- * if the length FIFO is full. The user would notice the Receive Missed
- * Frame count incrementing without any other errors being reported.
- * This code is left here for backward compatibility with v1.00k and
- * older EMAC devices.
- */
- InstancePtr->Stats.RecvOverrunErrors++;
- InstancePtr->Stats.FifoErrors++;
- ResetError = TRUE; /* requires a reset */
- }
-
- if (IntrStatus & XEM_EIR_RECV_LFIFO_UNDER_MASK) {
- InstancePtr->Stats.RecvUnderrunErrors++;
- InstancePtr->Stats.FifoErrors++;
- ResetError = TRUE; /* requires a reset */
- }
-
- /*
- * Now check for general receive errors. Get the latest count where
- * available, otherwise just bump the statistic so we know the interrupt
- * occurred.
- */
- if (IntrStatus & XEM_EIR_RECV_ERROR_MASK) {
- if (IntrStatus & XEM_EIR_RECV_MISSED_FRAME_MASK) {
- /*
- * Caused by length FIFO or data FIFO overruns on receive side
- */
- InstancePtr->Stats.RecvMissedFrameErrors =
- XIo_In32(InstancePtr->BaseAddress +
- XEM_RMFC_OFFSET);
- }
-
- if (IntrStatus & XEM_EIR_RECV_COLLISION_MASK) {
- InstancePtr->Stats.RecvCollisionErrors =
- XIo_In32(InstancePtr->BaseAddress + XEM_RCC_OFFSET);
- }
-
- if (IntrStatus & XEM_EIR_RECV_FCS_ERROR_MASK) {
- InstancePtr->Stats.RecvFcsErrors =
- XIo_In32(InstancePtr->BaseAddress +
- XEM_RFCSEC_OFFSET);
- }
-
- if (IntrStatus & XEM_EIR_RECV_LEN_ERROR_MASK) {
- InstancePtr->Stats.RecvLengthFieldErrors++;
- }
-
- if (IntrStatus & XEM_EIR_RECV_SHORT_ERROR_MASK) {
- InstancePtr->Stats.RecvShortErrors++;
- }
-
- if (IntrStatus & XEM_EIR_RECV_LONG_ERROR_MASK) {
- InstancePtr->Stats.RecvLongErrors++;
- }
-
- if (IntrStatus & XEM_EIR_RECV_ALIGN_ERROR_MASK) {
- InstancePtr->Stats.RecvAlignmentErrors =
- XIo_In32(InstancePtr->BaseAddress +
- XEM_RAEC_OFFSET);
- }
-
- /*
- * Bump recv interrupts stats only if not scatter-gather DMA (this
- * stat gets bumped elsewhere in that case)
- */
- if (!XEmac_mIsSgDma(InstancePtr)) {
- InstancePtr->Stats.RecvInterrupts++; /* TODO: double bump? */
- }
-
- }
-
- /*
- * Check for transmit errors. These apply to both DMA and non-DMA modes
- * of operation. The entire device should be reset after overruns or
- * underruns.
- */
- if (IntrStatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
- XEM_EIR_XMIT_LFIFO_OVER_MASK)) {
- InstancePtr->Stats.XmitOverrunErrors++;
- InstancePtr->Stats.FifoErrors++;
- ResetError = TRUE;
- }
-
- if (IntrStatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
- XEM_EIR_XMIT_LFIFO_UNDER_MASK)) {
- InstancePtr->Stats.XmitUnderrunErrors++;
- InstancePtr->Stats.FifoErrors++;
- ResetError = TRUE;
- }
-
- if (ResetError) {
- /*
- * If a reset error occurred, disable the EMAC interrupts since the
- * reset-causing interrupt(s) is latched in the EMAC - meaning it will
- * keep occurring until the device is reset. In order to give the higher
- * layer software time to reset the device, we have to disable the
- * overrun/underrun interrupts until that happens. We trust that the
- * higher layer resets the device. We are able to get away with disabling
- * all EMAC interrupts since the only interrupts it generates are for
- * error conditions, and we don't care about any more errors right now.
- */
- XIIF_V123B_WRITE_IIER(InstancePtr->BaseAddress, 0);
-
- /*
- * Invoke the error handler callback, which should result in a reset
- * of the device by the upper layer software.
- */
- InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
- XST_RESET_ERROR);
- }
-}
-
-/*****************************************************************************/
-/*
-*
-* Check the receive packet FIFO for errors. FIFO error interrupts are:
-* - Deadlock. See the XPacketFifo component for a description of deadlock on a
-* FIFO.
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-*
-* @return
-*
-* Although the function returns void, it can return an asynchronous error to the
-* application through the error handler. It can return XST_FIFO_ERROR if a FIFO
-* error occurred.
-*
-* @note
-*
-* This function is intended for internal use only.
-*
-******************************************************************************/
-void
-XEmac_CheckFifoRecvError(XEmac * InstancePtr)
-{
- /*
- * Although the deadlock is currently the only interrupt from a packet
- * FIFO, make sure it is deadlocked before taking action. There is no
- * need to clear this interrupt since it requires a reset of the device.
- */
- if (XPF_V100B_IS_DEADLOCKED(&InstancePtr->RecvFifo)) {
- u32 IntrEnable;
-
- InstancePtr->Stats.FifoErrors++;
-
- /*
- * Invoke the error callback function, which should result in a reset
- * of the device by the upper layer software. We first need to disable
- * the FIFO interrupt, since otherwise the upper layer thread that
- * handles the reset may never run because this interrupt condition
- * doesn't go away until a reset occurs (there is no way to ack it).
- */
- IntrEnable = XIIF_V123B_READ_DIER(InstancePtr->BaseAddress);
- XIIF_V123B_WRITE_DIER(InstancePtr->BaseAddress,
- IntrEnable & ~XEM_IPIF_RECV_FIFO_MASK);
-
- InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
- XST_FIFO_ERROR);
- }
-}
-
-/*****************************************************************************/
-/*
-*
-* Check the send packet FIFO for errors. FIFO error interrupts are:
-* - Deadlock. See the XPacketFifo component for a description of deadlock on a
-* FIFO.
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-*
-* @return
-*
-* Although the function returns void, it can return an asynchronous error to the
-* application through the error handler. It can return XST_FIFO_ERROR if a FIFO
-* error occurred.
-*
-* @note
-*
-* This function is intended for internal use only.
-*
-******************************************************************************/
-void
-XEmac_CheckFifoSendError(XEmac * InstancePtr)
-{
- /*
- * Although the deadlock is currently the only interrupt from a packet
- * FIFO, make sure it is deadlocked before taking action. There is no
- * need to clear this interrupt since it requires a reset of the device.
- */
- if (XPF_V100B_IS_DEADLOCKED(&InstancePtr->SendFifo)) {
- u32 IntrEnable;
-
- InstancePtr->Stats.FifoErrors++;
-
- /*
- * Invoke the error callback function, which should result in a reset
- * of the device by the upper layer software. We first need to disable
- * the FIFO interrupt, since otherwise the upper layer thread that
- * handles the reset may never run because this interrupt condition
- * doesn't go away until a reset occurs (there is no way to ack it).
- */
- IntrEnable = XIIF_V123B_READ_DIER(InstancePtr->BaseAddress);
- XIIF_V123B_WRITE_DIER(InstancePtr->BaseAddress,
- IntrEnable & ~XEM_IPIF_SEND_FIFO_MASK);
-
- InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
- XST_FIFO_ERROR);
- }
-}
+++ /dev/null
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xemac_intr_dma.c
-*
-* Contains functions used in interrupt mode when configured with scatter-gather
-* DMA.
-*
-* The interrupt handler, XEmac_IntrHandlerDma(), must be connected by the user
-* to the interrupt controller.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------------
-* 1.00a rpm 07/31/01 First release
-* 1.00b rpm 02/20/02 Repartitioned files and functions
-* 1.00c rpm 12/05/02 New version includes support for simple DMA and the delay
-* argument to SgSend
-* 1.00c rpm 02/03/03 The XST_DMA_SG_COUNT_EXCEEDED return code was removed
-* from SetPktThreshold in the internal DMA driver. Also
-* avoided compiler warnings by initializing Result in the
-* interrupt service routines.
-* 1.00c rpm 03/26/03 Fixed a problem in the interrupt service routines where
-* the interrupt status was toggled clear after a call to
-* ErrorHandler, but if ErrorHandler reset the device the
-* toggle actually asserted the interrupt because the
-* reset had cleared it.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xbasic_types.h"
-#include "xemac_i.h"
-#include "xio.h"
-#include "xbuf_descriptor.h"
-#include "xdma_channel.h"
-#include "xipif_v1_23_b.h" /* Uses v1.23b of the IPIF */
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-static void HandleDmaRecvIntr(XEmac * InstancePtr);
-static void HandleDmaSendIntr(XEmac * InstancePtr);
-static void HandleEmacDmaIntr(XEmac * InstancePtr);
-
-/*****************************************************************************/
-/**
-*
-* Send an Ethernet frame using scatter-gather DMA. The caller attaches the
-* frame to one or more buffer descriptors, then calls this function once for
-* each descriptor. The caller is responsible for allocating and setting up the
-* descriptor. An entire Ethernet frame may or may not be contained within one
-* descriptor. This function simply inserts the descriptor into the scatter-
-* gather engine's transmit list. The caller is responsible for providing mutual
-* exclusion to guarantee that a frame is contiguous in the transmit list. The
-* buffer attached to the descriptor must be word-aligned.
-*
-* The driver updates the descriptor with the device control register before
-* being inserted into the transmit list. If this is the last descriptor in
-* the frame, the inserts are committed, which means the descriptors for this
-* frame are now available for transmission.
-*
-* It is assumed that the upper layer software supplies a correctly formatted
-* Ethernet frame, including the destination and source addresses, the
-* type/length field, and the data field. It is also assumed that upper layer
-* software does not append FCS at the end of the frame.
-*
-* The buffer attached to the descriptor must be word-aligned on the front end.
-*
-* This call is non-blocking. Notification of error or successful transmission
-* is done asynchronously through the send or error callback function.
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-* @param BdPtr is the address of a descriptor to be inserted into the transmit
-* ring.
-* @param Delay indicates whether to start the scatter-gather DMA channel
-* immediately, or whether to wait. This allows the user to build up a
-* list of more than one descriptor before starting the transmission of
-* the packets, which allows the application to keep up with DMA and have
-* a constant stream of frames being transmitted. Use XEM_SGDMA_NODELAY or
-* XEM_SGDMA_DELAY, defined in xemac.h, as the value of this argument. If
-* the user chooses to delay and build a list, the user must call this
-* function with the XEM_SGDMA_NODELAY option or call XEmac_Start() to
-* kick off the tranmissions.
-*
-* @return
-*
-* - XST_SUCCESS if the buffer was successfull sent
-* - XST_DEVICE_IS_STOPPED if the Ethernet MAC has not been started yet
-* - XST_NOT_SGDMA if the device is not in scatter-gather DMA mode
-* - XST_DMA_SG_LIST_FULL if the descriptor list for the DMA channel is full
-* - XST_DMA_SG_BD_LOCKED if the DMA channel cannot insert the descriptor into
-* the list because a locked descriptor exists at the insert point
-* - XST_DMA_SG_NOTHING_TO_COMMIT if even after inserting a descriptor into the
-* list, the DMA channel believes there are no new descriptors to commit. If
-* this is ever encountered, there is likely a thread mutual exclusion problem
-* on transmit.
-*
-* @note
-*
-* This function is not thread-safe. The user must provide mutually exclusive
-* access to this function if there are to be multiple threads that can call it.
-*
-* @internal
-*
-* A status that should never be returned from this function, although
-* the code is set up to handle it, is XST_DMA_SG_NO_LIST. Starting the device
-* requires a list to be created, and this function requires the device to be
-* started.
-*
-******************************************************************************/
-XStatus
-XEmac_SgSend(XEmac * InstancePtr, XBufDescriptor * BdPtr, int Delay)
-{
- XStatus Result;
- u32 BdControl;
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(BdPtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /*
- * Be sure the device is configured for scatter-gather DMA, then be sure
- * it is started.
- */
- if (!XEmac_mIsSgDma(InstancePtr)) {
- return XST_NOT_SGDMA;
- }
-
- /*
- * Set some descriptor control word defaults (source address increment
- * and local destination address) and the destination address
- * (the FIFO). These are the same for every transmit descriptor.
- */
- BdControl = XBufDescriptor_GetControl(BdPtr);
- XBufDescriptor_SetControl(BdPtr, BdControl | XEM_DFT_SEND_BD_MASK);
-
- XBufDescriptor_SetDestAddress(BdPtr,
- InstancePtr->BaseAddress +
- XEM_PFIFO_TXDATA_OFFSET);
-
- /*
- * Put the descriptor in the send list. The DMA component accesses data
- * here that can also be modified in interrupt context, so a critical
- * section is required.
- */
- XIIF_V123B_GINTR_DISABLE(InstancePtr->BaseAddress);
-
- Result = XDmaChannel_PutDescriptor(&InstancePtr->SendChannel, BdPtr);
- if (Result != XST_SUCCESS) {
- XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress);
- return Result;
- }
-
- /*
- * If this is the last buffer in the frame, commit the inserts and start
- * the DMA engine if necessary
- */
- if (XBufDescriptor_IsLastControl(BdPtr)) {
- Result = XDmaChannel_CommitPuts(&InstancePtr->SendChannel);
- if (Result != XST_SUCCESS) {
- XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress);
- return Result;
- }
-
- if (Delay == XEM_SGDMA_NODELAY) {
- /*
- * Start the DMA channel. Ignore the return status since we know the
- * list exists and has at least one entry and we don't care if the
- * channel is already started. The DMA component accesses data here
- * that can be modified at interrupt or task levels, so a critical
- * section is required.
- */
- (void) XDmaChannel_SgStart(&InstancePtr->SendChannel);
- }
- }
-
- XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress);
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Add a descriptor, with an attached empty buffer, into the receive descriptor
-* list. The buffer attached to the descriptor must be word-aligned. This is
-* used by the upper layer software during initialization when first setting up
-* the receive descriptors, and also during reception of frames to replace
-* filled buffers with empty buffers. This function can be called when the
-* device is started or stopped. Note that it does start the scatter-gather DMA
-* engine. Although this is not necessary during initialization, it is not a
-* problem during initialization because the MAC receiver is not yet started.
-*
-* The buffer attached to the descriptor must be word-aligned on both the front
-* end and the back end.
-*
-* Notification of received frames are done asynchronously through the receive
-* callback function.
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-* @param BdPtr is a pointer to the buffer descriptor that will be added to the
-* descriptor list.
-*
-* @return
-*
-* - XST_SUCCESS if a descriptor was successfully returned to the driver
-* - XST_NOT_SGDMA if the device is not in scatter-gather DMA mode
-* - XST_DMA_SG_LIST_FULL if the receive descriptor list is full
-* - XST_DMA_SG_BD_LOCKED if the DMA channel cannot insert the descriptor into
-* the list because a locked descriptor exists at the insert point.
-* - XST_DMA_SG_NOTHING_TO_COMMIT if even after inserting a descriptor into the
-* list, the DMA channel believes there are no new descriptors to commit.
-*
-* @internal
-*
-* A status that should never be returned from this function, although
-* the code is set up to handle it, is XST_DMA_SG_NO_LIST. Starting the device
-* requires a list to be created, and this function requires the device to be
-* started.
-*
-******************************************************************************/
-XStatus
-XEmac_SgRecv(XEmac * InstancePtr, XBufDescriptor * BdPtr)
-{
- XStatus Result;
- u32 BdControl;
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(BdPtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /*
- * Be sure the device is configured for scatter-gather DMA
- */
- if (!XEmac_mIsSgDma(InstancePtr)) {
- return XST_NOT_SGDMA;
- }
-
- /*
- * Set some descriptor control word defaults (destination address increment
- * and local source address) and the source address (the FIFO). These are
- * the same for every receive descriptor.
- */
- BdControl = XBufDescriptor_GetControl(BdPtr);
- XBufDescriptor_SetControl(BdPtr, BdControl | XEM_DFT_RECV_BD_MASK);
- XBufDescriptor_SetSrcAddress(BdPtr,
- InstancePtr->BaseAddress +
- XEM_PFIFO_RXDATA_OFFSET);
-
- /*
- * Put the descriptor into the channel's descriptor list and commit.
- * Although this function is likely called within interrupt context, there
- * is the possibility that the upper layer software queues it to a task.
- * In this case, a critical section is needed here to protect shared data
- * in the DMA component.
- */
- XIIF_V123B_GINTR_DISABLE(InstancePtr->BaseAddress);
-
- Result = XDmaChannel_PutDescriptor(&InstancePtr->RecvChannel, BdPtr);
- if (Result != XST_SUCCESS) {
- XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress);
- return Result;
- }
-
- Result = XDmaChannel_CommitPuts(&InstancePtr->RecvChannel);
- if (Result != XST_SUCCESS) {
- XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress);
- return Result;
- }
-
- /*
- * Start the DMA channel. Ignore the return status since we know the list
- * exists and has at least one entry and we don't care if the channel is
- * already started. The DMA component accesses data here that can be
- * modified at interrupt or task levels, so a critical section is required.
- */
- (void) XDmaChannel_SgStart(&InstancePtr->RecvChannel);
-
- XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress);
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* The interrupt handler for the Ethernet driver when configured with scatter-
-* gather DMA.
-*
-* Get the interrupt status from the IpIf to determine the source of the
-* interrupt. The source can be: MAC, Recv Packet FIFO, Send Packet FIFO, Recv
-* DMA channel, or Send DMA channel. The packet FIFOs only interrupt during
-* "deadlock" conditions.
-*
-* @param InstancePtr is a pointer to the XEmac instance that just interrupted.
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-void
-XEmac_IntrHandlerDma(void *InstancePtr)
-{
- u32 IntrStatus;
- XEmac *EmacPtr = (XEmac *) InstancePtr;
-
- EmacPtr->Stats.TotalIntrs++;
-
- /*
- * Get the interrupt status from the IPIF. There is no clearing of
- * interrupts in the IPIF. Interrupts must be cleared at the source.
- */
- IntrStatus = XIIF_V123B_READ_DIPR(EmacPtr->BaseAddress);
-
- /*
- * See which type of interrupt is being requested, and service it
- */
- if (IntrStatus & XEM_IPIF_RECV_DMA_MASK) { /* Receive DMA interrupt */
- EmacPtr->Stats.RecvInterrupts++;
- HandleDmaRecvIntr(EmacPtr);
- }
-
- if (IntrStatus & XEM_IPIF_SEND_DMA_MASK) { /* Send DMA interrupt */
- EmacPtr->Stats.XmitInterrupts++;
- HandleDmaSendIntr(EmacPtr);
- }
-
- if (IntrStatus & XEM_IPIF_EMAC_MASK) { /* MAC interrupt */
- EmacPtr->Stats.EmacInterrupts++;
- HandleEmacDmaIntr(EmacPtr);
- }
-
- if (IntrStatus & XEM_IPIF_RECV_FIFO_MASK) { /* Receive FIFO interrupt */
- EmacPtr->Stats.RecvInterrupts++;
- XEmac_CheckFifoRecvError(EmacPtr);
- }
-
- if (IntrStatus & XEM_IPIF_SEND_FIFO_MASK) { /* Send FIFO interrupt */
- EmacPtr->Stats.XmitInterrupts++;
- XEmac_CheckFifoSendError(EmacPtr);
- }
-
- if (IntrStatus & XIIF_V123B_ERROR_MASK) {
- /*
- * An error occurred internal to the IPIF. This is more of a debug and
- * integration issue rather than a production error. Don't do anything
- * other than clear it, which provides a spot for software to trap
- * on the interrupt and begin debugging.
- */
- XIIF_V123B_WRITE_DISR(EmacPtr->BaseAddress,
- XIIF_V123B_ERROR_MASK);
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* Set the packet count threshold for this device. The device must be stopped
-* before setting the threshold. The packet count threshold is used for interrupt
-* coalescing, which reduces the frequency of interrupts from the device to the
-* processor. In this case, the scatter-gather DMA engine only interrupts when
-* the packet count threshold is reached, instead of interrupting for each packet.
-* A packet is a generic term used by the scatter-gather DMA engine, and is
-* equivalent to an Ethernet frame in our case.
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-* @param Direction indicates the channel, send or receive, from which the
-* threshold register is read.
-* @param Threshold is the value of the packet threshold count used during
-* interrupt coalescing. A value of 0 disables the use of packet threshold
-* by the hardware.
-*
-* @return
-*
-* - XST_SUCCESS if the threshold was successfully set
-* - XST_NOT_SGDMA if the MAC is not configured for scatter-gather DMA
-* - XST_DEVICE_IS_STARTED if the device has not been stopped
-* - XST_INVALID_PARAM if the Direction parameter is invalid. Turning on
-* asserts would also catch this error.
-*
-* @note
-*
-* The packet threshold could be set to larger than the number of descriptors
-* allocated to the DMA channel. In this case, the wait bound will take over
-* and always indicate data arrival. There was a check in this function that
-* returned an error if the treshold was larger than the number of descriptors,
-* but that was removed because users would then have to set the threshold
-* only after they set descriptor space, which is an order dependency that
-* caused confustion.
-*
-******************************************************************************/
-XStatus
-XEmac_SetPktThreshold(XEmac * InstancePtr, u32 Direction, u8 Threshold)
-{
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(Direction == XEM_SEND || Direction == XEM_RECV);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /*
- * Be sure device is configured for scatter-gather DMA and has been stopped
- */
- if (!XEmac_mIsSgDma(InstancePtr)) {
- return XST_NOT_SGDMA;
- }
-
- if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) {
- return XST_DEVICE_IS_STARTED;
- }
-
- /*
- * Based on the direction, set the packet threshold in the
- * corresponding DMA channel component. Default to the receive
- * channel threshold register (if an invalid Direction is passed).
- */
- switch (Direction) {
- case XEM_SEND:
- return XDmaChannel_SetPktThreshold(&InstancePtr->SendChannel,
- Threshold);
-
- case XEM_RECV:
- return XDmaChannel_SetPktThreshold(&InstancePtr->RecvChannel,
- Threshold);
-
- default:
- return XST_INVALID_PARAM;
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* Get the value of the packet count threshold for this driver/device. The packet
-* count threshold is used for interrupt coalescing, which reduces the frequency
-* of interrupts from the device to the processor. In this case, the
-* scatter-gather DMA engine only interrupts when the packet count threshold is
-* reached, instead of interrupting for each packet. A packet is a generic term
-* used by the scatter-gather DMA engine, and is equivalent to an Ethernet frame
-* in our case.
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-* @param Direction indicates the channel, send or receive, from which the
-* threshold register is read.
-* @param ThreshPtr is a pointer to the byte into which the current value of the
-* packet threshold register will be copied. An output parameter. A value
-* of 0 indicates the use of packet threshold by the hardware is disabled.
-*
-* @return
-*
-* - XST_SUCCESS if the packet threshold was retrieved successfully
-* - XST_NOT_SGDMA if the MAC is not configured for scatter-gather DMA
-* - XST_INVALID_PARAM if the Direction parameter is invalid. Turning on
-* asserts would also catch this error.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-XStatus
-XEmac_GetPktThreshold(XEmac * InstancePtr, u32 Direction, u8 * ThreshPtr)
-{
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(Direction == XEM_SEND || Direction == XEM_RECV);
- XASSERT_NONVOID(ThreshPtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- if (!XEmac_mIsSgDma(InstancePtr)) {
- return XST_NOT_SGDMA;
- }
-
- /*
- * Based on the direction, return the packet threshold set in the
- * corresponding DMA channel component. Default to the value in
- * the receive channel threshold register (if an invalid Direction
- * is passed).
- */
- switch (Direction) {
- case XEM_SEND:
- *ThreshPtr =
- XDmaChannel_GetPktThreshold(&InstancePtr->SendChannel);
- break;
-
- case XEM_RECV:
- *ThreshPtr =
- XDmaChannel_GetPktThreshold(&InstancePtr->RecvChannel);
- break;
-
- default:
- return XST_INVALID_PARAM;
- }
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Set the packet wait bound timer for this driver/device. The device must be
-* stopped before setting the timer value. The packet wait bound is used during
-* interrupt coalescing to trigger an interrupt when not enough packets have been
-* received to reach the packet count threshold. A packet is a generic term used
-* by the scatter-gather DMA engine, and is equivalent to an Ethernet frame in
-* our case. The timer is in milliseconds.
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-* @param Direction indicates the channel, send or receive, from which the
-* threshold register is read.
-* @param TimerValue is the value of the packet wait bound used during interrupt
-* coalescing. It is in milliseconds in the range 0 - 1023. A value of 0
-* disables the packet wait bound timer.
-*
-* @return
-*
-* - XST_SUCCESS if the packet wait bound was set successfully
-* - XST_NOT_SGDMA if the MAC is not configured for scatter-gather DMA
-* - XST_DEVICE_IS_STARTED if the device has not been stopped
-* - XST_INVALID_PARAM if the Direction parameter is invalid. Turning on
-* asserts would also catch this error.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-XStatus
-XEmac_SetPktWaitBound(XEmac * InstancePtr, u32 Direction, u32 TimerValue)
-{
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(Direction == XEM_SEND || Direction == XEM_RECV);
- XASSERT_NONVOID(TimerValue <= XEM_SGDMA_MAX_WAITBOUND);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /*
- * Be sure device is configured for scatter-gather DMA and has been stopped
- */
- if (!XEmac_mIsSgDma(InstancePtr)) {
- return XST_NOT_SGDMA;
- }
-
- if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) {
- return XST_DEVICE_IS_STARTED;
- }
-
- /*
- * Based on the direction, set the packet wait bound in the
- * corresponding DMA channel component. Default to the receive
- * channel wait bound register (if an invalid Direction is passed).
- */
- switch (Direction) {
- case XEM_SEND:
- XDmaChannel_SetPktWaitBound(&InstancePtr->SendChannel,
- TimerValue);
- break;
-
- case XEM_RECV:
- XDmaChannel_SetPktWaitBound(&InstancePtr->RecvChannel,
- TimerValue);
- break;
-
- default:
- return XST_INVALID_PARAM;
- }
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Get the packet wait bound timer for this driver/device. The packet wait bound
-* is used during interrupt coalescing to trigger an interrupt when not enough
-* packets have been received to reach the packet count threshold. A packet is a
-* generic term used by the scatter-gather DMA engine, and is equivalent to an
-* Ethernet frame in our case. The timer is in milliseconds.
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-* @param Direction indicates the channel, send or receive, from which the
-* threshold register is read.
-* @param WaitPtr is a pointer to the byte into which the current value of the
-* packet wait bound register will be copied. An output parameter. Units
-* are in milliseconds in the range 0 - 1023. A value of 0 indicates the
-* packet wait bound timer is disabled.
-*
-* @return
-*
-* - XST_SUCCESS if the packet wait bound was retrieved successfully
-* - XST_NOT_SGDMA if the MAC is not configured for scatter-gather DMA
-* - XST_INVALID_PARAM if the Direction parameter is invalid. Turning on
-* asserts would also catch this error.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-XStatus
-XEmac_GetPktWaitBound(XEmac * InstancePtr, u32 Direction, u32 * WaitPtr)
-{
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(Direction == XEM_SEND || Direction == XEM_RECV);
- XASSERT_NONVOID(WaitPtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- if (!XEmac_mIsSgDma(InstancePtr)) {
- return XST_NOT_SGDMA;
- }
-
- /*
- * Based on the direction, return the packet wait bound set in the
- * corresponding DMA channel component. Default to the value in
- * the receive channel wait bound register (if an invalid Direction
- * is passed).
- */
- switch (Direction) {
- case XEM_SEND:
- *WaitPtr =
- XDmaChannel_GetPktWaitBound(&InstancePtr->SendChannel);
- break;
-
- case XEM_RECV:
- *WaitPtr =
- XDmaChannel_GetPktWaitBound(&InstancePtr->RecvChannel);
- break;
-
- default:
- return XST_INVALID_PARAM;
- }
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Give the driver the memory space to be used for the scatter-gather DMA
-* receive descriptor list. This function should only be called once, during
-* initialization of the Ethernet driver. The memory space must be big enough
-* to hold some number of descriptors, depending on the needs of the system.
-* The xemac.h file defines minimum and default numbers of descriptors
-* which can be used to allocate this memory space.
-*
-* The memory space must be word-aligned. An assert will occur if asserts are
-* turned on and the memory is not word-aligned.
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-* @param MemoryPtr is a pointer to the word-aligned memory.
-* @param ByteCount is the length, in bytes, of the memory space.
-*
-* @return
-*
-* - XST_SUCCESS if the space was initialized successfully
-* - XST_NOT_SGDMA if the MAC is not configured for scatter-gather DMA
-* - XST_DMA_SG_LIST_EXISTS if this list space has already been created
-*
-* @note
-*
-* If the device is configured for scatter-gather DMA, this function must be
-* called AFTER the XEmac_Initialize() function because the DMA channel
-* components must be initialized before the memory space is set.
-*
-******************************************************************************/
-XStatus
-XEmac_SetSgRecvSpace(XEmac * InstancePtr, u32 * MemoryPtr, u32 ByteCount)
-{
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(MemoryPtr != NULL);
- XASSERT_NONVOID(ByteCount != 0);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- if (!XEmac_mIsSgDma(InstancePtr)) {
- return XST_NOT_SGDMA;
- }
-
- return XDmaChannel_CreateSgList(&InstancePtr->RecvChannel, MemoryPtr,
- ByteCount);
-}
-
-/*****************************************************************************/
-/**
-*
-* Give the driver the memory space to be used for the scatter-gather DMA
-* transmit descriptor list. This function should only be called once, during
-* initialization of the Ethernet driver. The memory space must be big enough
-* to hold some number of descriptors, depending on the needs of the system.
-* The xemac.h file defines minimum and default numbers of descriptors
-* which can be used to allocate this memory space.
-*
-* The memory space must be word-aligned. An assert will occur if asserts are
-* turned on and the memory is not word-aligned.
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-* @param MemoryPtr is a pointer to the word-aligned memory.
-* @param ByteCount is the length, in bytes, of the memory space.
-*
-* @return
-*
-* - XST_SUCCESS if the space was initialized successfully
-* - XST_NOT_SGDMA if the MAC is not configured for scatter-gather DMA
-* - XST_DMA_SG_LIST_EXISTS if this list space has already been created
-*
-* @note
-*
-* If the device is configured for scatter-gather DMA, this function must be
-* called AFTER the XEmac_Initialize() function because the DMA channel
-* components must be initialized before the memory space is set.
-*
-******************************************************************************/
-XStatus
-XEmac_SetSgSendSpace(XEmac * InstancePtr, u32 * MemoryPtr, u32 ByteCount)
-{
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(MemoryPtr != NULL);
- XASSERT_NONVOID(ByteCount != 0);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- if (!XEmac_mIsSgDma(InstancePtr)) {
- return XST_NOT_SGDMA;
- }
-
- return XDmaChannel_CreateSgList(&InstancePtr->SendChannel, MemoryPtr,
- ByteCount);
-}
-
-/*****************************************************************************/
-/**
-*
-* Set the callback function for handling received frames in scatter-gather DMA
-* mode. The upper layer software should call this function during
-* initialization. The callback is called once per frame received. The head of
-* a descriptor list is passed in along with the number of descriptors in the
-* list. Before leaving the callback, the upper layer software should attach a
-* new buffer to each descriptor in the list.
-*
-* The callback is invoked by the driver within interrupt context, so it needs
-* to do its job quickly. Sending the received frame up the protocol stack
-* should be done at task-level. If there are other potentially slow operations
-* within the callback, these too should be done at task-level.
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-* @param CallBackRef is a reference pointer to be passed back to the adapter in
-* the callback. This helps the adapter correlate the callback to a
-* particular driver.
-* @param FuncPtr is the pointer to the callback function.
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-void
-XEmac_SetSgRecvHandler(XEmac * InstancePtr, void *CallBackRef,
- XEmac_SgHandler FuncPtr)
-{
- /*
- * Asserted IsDmaSg here instead of run-time check because there is really
- * no ill-effects of setting these when not configured for scatter-gather.
- */
- XASSERT_VOID(InstancePtr != NULL);
- XASSERT_VOID(FuncPtr != NULL);
- XASSERT_VOID(XEmac_mIsSgDma(InstancePtr));
- XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- InstancePtr->SgRecvHandler = FuncPtr;
- InstancePtr->SgRecvRef = CallBackRef;
-}
-
-/*****************************************************************************/
-/**
-*
-* Set the callback function for handling confirmation of transmitted frames in
-* scatter-gather DMA mode. The upper layer software should call this function
-* during initialization. The callback is called once per frame sent. The head
-* of a descriptor list is passed in along with the number of descriptors in
-* the list. The callback is responsible for freeing buffers attached to these
-* descriptors.
-*
-* The callback is invoked by the driver within interrupt context, so it needs
-* to do its job quickly. If there are potentially slow operations within the
-* callback, these should be done at task-level.
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-* @param CallBackRef is a reference pointer to be passed back to the adapter in
-* the callback. This helps the adapter correlate the callback to a
-* particular driver.
-* @param FuncPtr is the pointer to the callback function.
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-void
-XEmac_SetSgSendHandler(XEmac * InstancePtr, void *CallBackRef,
- XEmac_SgHandler FuncPtr)
-{
- /*
- * Asserted IsDmaSg here instead of run-time check because there is really
- * no ill-effects of setting these when not configured for scatter-gather.
- */
- XASSERT_VOID(InstancePtr != NULL);
- XASSERT_VOID(FuncPtr != NULL);
- XASSERT_VOID(XEmac_mIsSgDma(InstancePtr));
- XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- InstancePtr->SgSendHandler = FuncPtr;
- InstancePtr->SgSendRef = CallBackRef;
-}
-
-/*****************************************************************************/
-/*
-*
-* Handle an interrupt from the DMA receive channel. DMA interrupts are:
-*
-* - DMA error. DMA encountered a bus error or timeout. This is a fatal error
-* that requires reset of the channel. The driver calls the error handler
-* of the upper layer software with an error code indicating the device should
-* be reset.
-* - Packet count threshold reached. For scatter-gather operations, indicates
-* the threshold for the number of packets not serviced by software has been
-* reached. The driver behaves as follows:
-* - Get the value of the packet counter, which tells us how many packets
-* are ready to be serviced
-* - For each packet
-* - For each descriptor, remove it from the scatter-gather list
-* - Check for the last descriptor in the frame, and if set
-* - Bump frame statistics
-* - Call the scatter-gather receive callback function
-* - Decrement the packet counter by one
-* Note that there are no receive errors reported in the status word of
-* the buffer descriptor. If receive errors occur, the MAC drops the
-* packet, and we only find out about the errors through various error
-* count registers.
-* - Packet wait bound reached. For scatter-gather, indicates the time to wait
-* for the next packet has expired. The driver follows the same logic as when
-* the packet count threshold interrupt is received.
-* - Scatter-gather end acknowledge. Hardware has reached the end of the
-* descriptor list. The driver follows the same logic as when the packet count
-* threshold interrupt is received. In addition, the driver restarts the DMA
-* scatter-gather channel in case there are newly inserted descriptors.
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-*
-* @return
-*
-* Although the function returns void, there are asynchronous errors that can
-* be generated (by calling the ErrorHandler) from this function. These are:
-* - XST_DMA_SG_LIST_EMPTY indicates we tried to get a buffer descriptor from the
-* DMA channel, but there was not one ready for software.
-* - XST_DMA_ERROR indicates a DMA bus error or timeout occurred. This is a fatal
-* error that requires reset.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-static void
-HandleDmaRecvIntr(XEmac * InstancePtr)
-{
- u32 IntrStatus;
-
- /*
- * Read the interrupt status
- */
- IntrStatus = XDmaChannel_GetIntrStatus(&InstancePtr->RecvChannel);
-
- /*
- * For packet threshold or wait bound interrupts, process desciptors. Also
- * process descriptors on a SG end acknowledgement, which means the end of
- * the descriptor list has been reached by the hardware. For receive, this
- * is potentially trouble since it means the descriptor list is full,
- * unless software can process enough packets quickly enough so the
- * hardware has room to put new packets.
- */
- if (IntrStatus & (XDC_IXR_PKT_THRESHOLD_MASK |
- XDC_IXR_PKT_WAIT_BOUND_MASK | XDC_IXR_SG_END_MASK)) {
- XStatus Result = XST_SUCCESS;
- u32 NumFrames;
- u32 NumProcessed;
- u32 NumBuffers;
- u32 NumBytes;
- u32 IsLast;
- XBufDescriptor *FirstBdPtr;
- XBufDescriptor *BdPtr;
-
- /*
- * Get the number of unserviced packets
- */
- NumFrames = XDmaChannel_GetPktCount(&InstancePtr->RecvChannel);
-
- for (NumProcessed = 0; NumProcessed < NumFrames; NumProcessed++) {
- IsLast = FALSE;
- FirstBdPtr = NULL;
- NumBuffers = 0;
- NumBytes = 0;
-
- /*
- * For each packet, get the descriptor from the list. On the
- * last one in the frame, make the callback to the upper layer.
- */
- while (!IsLast) {
- Result =
- XDmaChannel_GetDescriptor(&InstancePtr->
- RecvChannel,
- &BdPtr);
- if (Result != XST_SUCCESS) {
- /*
- * An error getting a buffer descriptor from the list.
- * This should not happen, but if it does, report it to
- * the error callback and break out of the loops to service
- * other interrupts.
- */
- InstancePtr->ErrorHandler(InstancePtr->
- ErrorRef,
- Result);
- break;
- }
-
- /*
- * Keep a pointer to the first descriptor in the list, as it
- * will be passed to the upper layers in a bit. By the fact
- * that we received this packet means no errors occurred, so
- * no need to check the device status word for errors.
- */
- if (FirstBdPtr == NULL) {
- FirstBdPtr = BdPtr;
- }
-
- NumBytes += XBufDescriptor_GetLength(BdPtr);
-
- /*
- * Check to see if this is the last descriptor in the frame,
- * and if so, set the IsLast flag to get out of the loop.
- */
- if (XBufDescriptor_IsLastStatus(BdPtr)) {
- IsLast = TRUE;
- }
-
- /*
- * Bump the number of buffers in this packet
- */
- NumBuffers++;
-
- } /* end while loop */
-
- /*
- * Check for error that occurred inside the while loop, and break
- * out of the for loop if there was one so other interrupts can
- * be serviced.
- */
- if (Result != XST_SUCCESS) {
- break;
- }
-
- InstancePtr->Stats.RecvFrames++;
- InstancePtr->Stats.RecvBytes += NumBytes;
-
- /*
- * Make the callback to the upper layers, passing it the first
- * descriptor in the packet and the number of descriptors in the
- * packet.
- */
- InstancePtr->SgRecvHandler(InstancePtr->SgRecvRef,
- FirstBdPtr, NumBuffers);
-
- /*
- * Decrement the packet count register to reflect the fact we
- * just processed a packet
- */
- XDmaChannel_DecrementPktCount(&InstancePtr->
- RecvChannel);
-
- } /* end for loop */
-
- /*
- * If the interrupt was an end-ack, check the descriptor list again to
- * see if it is empty. If not, go ahead and restart the scatter-gather
- * channel. This is to fix a possible race condition where, on receive,
- * the driver attempted to start a scatter-gather channel that was
- * already started, which resulted in no action from the XDmaChannel
- * component. But, just after the XDmaChannel component saw that the
- * hardware was already started, the hardware stopped because it
- * reached the end of the list. In that case, this interrupt is
- * generated and we can restart the hardware here.
- */
- if (IntrStatus & XDC_IXR_SG_END_MASK) {
- /*
- * Ignore the return status since we know the list exists and we
- * don't care if the list is empty or the channel is already started.
- */
- (void) XDmaChannel_SgStart(&InstancePtr->RecvChannel);
- }
- }
-
- /*
- * All interrupts are handled (except the error below) so acknowledge
- * (clear) the interrupts by writing the value read above back to the status
- * register. The packet count interrupt must be acknowledged after the
- * decrement, otherwise it will come right back. We clear the interrupts
- * before we handle the error interrupt because the ErrorHandler should
- * result in a reset, which clears the interrupt status register. So we
- * don't want to toggle the interrupt back on by writing the interrupt
- * status register with an old value after a reset.
- */
- XDmaChannel_SetIntrStatus(&InstancePtr->RecvChannel, IntrStatus);
-
- /*
- * Check for DMA errors and call the error callback function if an error
- * occurred (DMA bus or timeout error), which should result in a reset of
- * the device by the upper layer software.
- */
- if (IntrStatus & XDC_IXR_DMA_ERROR_MASK) {
- InstancePtr->Stats.DmaErrors++;
- InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XST_DMA_ERROR);
- }
-}
-
-/*****************************************************************************/
-/*
-*
-* Handle an interrupt from the DMA send channel. DMA interrupts are:
-*
-* - DMA error. DMA encountered a bus error or timeout. This is a fatal error
-* that requires reset of the channel. The driver calls the error handler
-* of the upper layer software with an error code indicating the device should
-* be reset.
-* - Packet count threshold reached. For scatter-gather operations, indicates
-* the threshold for the number of packets not serviced by software has been
-* reached. The driver behaves as follows:
-* - Get the value of the packet counter, which tells us how many packets
-* are ready to be serviced
-* - For each packet
-* - For each descriptor, remove it from the scatter-gather list
-* - Check for the last descriptor in the frame, and if set
-* - Bump frame statistics
-* - Call the scatter-gather receive callback function
-* - Decrement the packet counter by one
-* Note that there are no receive errors reported in the status word of
-* the buffer descriptor. If receive errors occur, the MAC drops the
-* packet, and we only find out about the errors through various error
-* count registers.
-* - Packet wait bound reached. For scatter-gather, indicates the time to wait
-* for the next packet has expired. The driver follows the same logic as when
-* the packet count threshold interrupt is received.
-* - Scatter-gather end acknowledge. Hardware has reached the end of the
-* descriptor list. The driver follows the same logic as when the packet count
-* threshold interrupt is received. In addition, the driver restarts the DMA
-* scatter-gather channel in case there are newly inserted descriptors.
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-*
-* @return
-*
-* Although the function returns void, there are asynchronous errors
-* that can be generated from this function. These are:
-* - XST_DMA_SG_LIST_EMPTY indicates we tried to get a buffer descriptor from
-* the DMA channel, but there was not one ready for software.
-* - XST_DMA_ERROR indicates a DMA bus error or timeout occurred. This is a
-* fatal error that requires reset.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-static void
-HandleDmaSendIntr(XEmac * InstancePtr)
-{
- u32 IntrStatus;
-
- /*
- * Read the interrupt status
- */
- IntrStatus = XDmaChannel_GetIntrStatus(&InstancePtr->SendChannel);
-
- /*
- * For packet threshold or wait bound interrupt, process descriptors. Also
- * process descriptors on a SG end acknowledgement, which means the end of
- * the descriptor list has been reached by the hardware. For transmit,
- * this is a normal condition during times of light traffic. In fact, the
- * wait bound interrupt may be masked for transmit since the end-ack would
- * always occur before the wait bound expires.
- */
- if (IntrStatus & (XDC_IXR_PKT_THRESHOLD_MASK |
- XDC_IXR_PKT_WAIT_BOUND_MASK | XDC_IXR_SG_END_MASK)) {
- XStatus Result = XST_SUCCESS;
- u32 NumFrames;
- u32 NumProcessed;
- u32 NumBuffers;
- u32 NumBytes;
- u32 IsLast;
- XBufDescriptor *FirstBdPtr;
- XBufDescriptor *BdPtr;
-
- /*
- * Get the number of unserviced packets
- */
- NumFrames = XDmaChannel_GetPktCount(&InstancePtr->SendChannel);
-
- for (NumProcessed = 0; NumProcessed < NumFrames; NumProcessed++) {
- IsLast = FALSE;
- FirstBdPtr = NULL;
- NumBuffers = 0;
- NumBytes = 0;
-
- /*
- * For each frame, traverse the descriptor list and look for
- * errors. On the last one in the frame, make the callback.
- */
- while (!IsLast) {
- Result =
- XDmaChannel_GetDescriptor(&InstancePtr->
- SendChannel,
- &BdPtr);
- if (Result != XST_SUCCESS) {
- /*
- * An error getting a buffer descriptor from the list.
- * This should not happen, but if it does, report it to
- * the error callback and break out of the loops to service
- * other interrupts
- */
- InstancePtr->ErrorHandler(InstancePtr->
- ErrorRef,
- Result);
- break;
- }
-
- /*
- * Keep a pointer to the first descriptor in the list and
- * check the device status for errors. The device status is
- * only available in the first descriptor of a packet.
- */
- if (FirstBdPtr == NULL) {
- u32 XmitStatus;
-
- FirstBdPtr = BdPtr;
-
- XmitStatus =
- XBufDescriptor_GetDeviceStatus
- (BdPtr);
- if (XmitStatus &
- XEM_TSR_EXCESS_DEFERRAL_MASK) {
- InstancePtr->Stats.
- XmitExcessDeferral++;
- }
-
- if (XmitStatus &
- XEM_TSR_LATE_COLLISION_MASK) {
- InstancePtr->Stats.
- XmitLateCollisionErrors++;
- }
- }
-
- NumBytes += XBufDescriptor_GetLength(BdPtr);
-
- /*
- * Check to see if this is the last descriptor in the frame,
- * and if so, set the IsLast flag to get out of the loop. The
- * transmit channel must check the last bit in the control
- * word, not the status word (the DMA engine does not update
- * the last bit in the status word for the transmit direction).
- */
- if (XBufDescriptor_IsLastControl(BdPtr)) {
- IsLast = TRUE;
- }
-
- /*
- * Bump the number of buffers in this packet
- */
- NumBuffers++;
-
- } /* end while loop */
-
- /*
- * Check for error that occurred inside the while loop, and break
- * out of the for loop if there was one so other interrupts can
- * be serviced.
- */
- if (Result != XST_SUCCESS) {
- break;
- }
-
- InstancePtr->Stats.XmitFrames++;
- InstancePtr->Stats.XmitBytes += NumBytes;
-
- /*
- * Make the callback to the upper layers, passing it the first
- * descriptor in the packet and the number of descriptors in the
- * packet.
- */
- InstancePtr->SgSendHandler(InstancePtr->SgSendRef,
- FirstBdPtr, NumBuffers);
-
- /*
- * Decrement the packet count register to reflect the fact we
- * just processed a packet
- */
- XDmaChannel_DecrementPktCount(&InstancePtr->
- SendChannel);
-
- } /* end for loop */
-
- /*
- * If the interrupt was an end-ack, check the descriptor list again to
- * see if it is empty. If not, go ahead and restart the scatter-gather
- * channel. This is to fix a possible race condition where, on transmit,
- * the driver attempted to start a scatter-gather channel that was
- * already started, which resulted in no action from the XDmaChannel
- * component. But, just after the XDmaChannel component saw that the
- * hardware was already started, the hardware stopped because it
- * reached the end of the list. In that case, this interrupt is
- * generated and we can restart the hardware here.
- */
- if (IntrStatus & XDC_IXR_SG_END_MASK) {
- /*
- * Ignore the return status since we know the list exists and we
- * don't care if the list is empty or the channel is already started.
- */
- (void) XDmaChannel_SgStart(&InstancePtr->SendChannel);
- }
- }
-
- /*
- * All interrupts are handled (except the error below) so acknowledge
- * (clear) the interrupts by writing the value read above back to the status
- * register. The packet count interrupt must be acknowledged after the
- * decrement, otherwise it will come right back. We clear the interrupts
- * before we handle the error interrupt because the ErrorHandler should
- * result in a reset, which clears the interrupt status register. So we
- * don't want to toggle the interrupt back on by writing the interrupt
- * status register with an old value after a reset.
- */
- XDmaChannel_SetIntrStatus(&InstancePtr->SendChannel, IntrStatus);
-
- /*
- * Check for DMA errors and call the error callback function if an error
- * occurred (DMA bus or timeout error), which should result in a reset of
- * the device by the upper layer software.
- */
- if (IntrStatus & XDC_IXR_DMA_ERROR_MASK) {
- InstancePtr->Stats.DmaErrors++;
- InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XST_DMA_ERROR);
- }
-}
-
-/*****************************************************************************/
-/*
-*
-* Handle an interrupt from the Ethernet MAC when configured with scatter-gather
-* DMA. The only interrupts handled in this case are errors.
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-static void
-HandleEmacDmaIntr(XEmac * InstancePtr)
-{
- u32 IntrStatus;
-
- /*
- * When configured with DMA, the EMAC generates interrupts only when errors
- * occur. We clear the interrupts immediately so that any latched status
- * interrupt bits will reflect the true status of the device, and so any
- * pulsed interrupts (non-status) generated during the Isr will not be lost.
- */
- IntrStatus = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress);
- XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress, IntrStatus);
-
- /*
- * Check the MAC for errors
- */
- XEmac_CheckEmacError(InstancePtr, IntrStatus);
-}
+++ /dev/null
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xemac_l.h
-*
-* This header file contains identifiers and low-level driver functions (or
-* macros) that can be used to access the device. High-level driver functions
-* are defined in xemac.h.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b rpm 04/26/02 First release
-* 1.00b rmm 09/23/02 Added XEmac_mPhyReset macro
-* 1.00c rpm 12/05/02 New version includes support for simple DMA
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XEMAC_L_H /* prevent circular inclusions */
-#define XEMAC_L_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xbasic_types.h"
-#include "xio.h"
-
-/************************** Constant Definitions *****************************/
-
-/* Offset of the MAC registers from the IPIF base address */
-#define XEM_REG_OFFSET 0x1100UL
-
-/*
- * Register offsets for the Ethernet MAC. Each register is 32 bits.
- */
-#define XEM_EMIR_OFFSET (XEM_REG_OFFSET + 0x0) /* EMAC Module ID */
-#define XEM_ECR_OFFSET (XEM_REG_OFFSET + 0x4) /* MAC Control */
-#define XEM_IFGP_OFFSET (XEM_REG_OFFSET + 0x8) /* Interframe Gap */
-#define XEM_SAH_OFFSET (XEM_REG_OFFSET + 0xC) /* Station addr, high */
-#define XEM_SAL_OFFSET (XEM_REG_OFFSET + 0x10) /* Station addr, low */
-#define XEM_MGTCR_OFFSET (XEM_REG_OFFSET + 0x14) /* MII mgmt control */
-#define XEM_MGTDR_OFFSET (XEM_REG_OFFSET + 0x18) /* MII mgmt data */
-#define XEM_RPLR_OFFSET (XEM_REG_OFFSET + 0x1C) /* Rx packet length */
-#define XEM_TPLR_OFFSET (XEM_REG_OFFSET + 0x20) /* Tx packet length */
-#define XEM_TSR_OFFSET (XEM_REG_OFFSET + 0x24) /* Tx status */
-#define XEM_RMFC_OFFSET (XEM_REG_OFFSET + 0x28) /* Rx missed frames */
-#define XEM_RCC_OFFSET (XEM_REG_OFFSET + 0x2C) /* Rx collisions */
-#define XEM_RFCSEC_OFFSET (XEM_REG_OFFSET + 0x30) /* Rx FCS errors */
-#define XEM_RAEC_OFFSET (XEM_REG_OFFSET + 0x34) /* Rx alignment errors */
-#define XEM_TEDC_OFFSET (XEM_REG_OFFSET + 0x38) /* Transmit excess
- * deferral cnt */
-
-/*
- * Register offsets for the IPIF components
- */
-#define XEM_ISR_OFFSET 0x20UL /* Interrupt status */
-
-#define XEM_DMA_OFFSET 0x2300UL
-#define XEM_DMA_SEND_OFFSET (XEM_DMA_OFFSET + 0x0) /* DMA send channel */
-#define XEM_DMA_RECV_OFFSET (XEM_DMA_OFFSET + 0x40) /* DMA recv channel */
-
-#define XEM_PFIFO_OFFSET 0x2000UL
-#define XEM_PFIFO_TXREG_OFFSET (XEM_PFIFO_OFFSET + 0x0) /* Tx registers */
-#define XEM_PFIFO_RXREG_OFFSET (XEM_PFIFO_OFFSET + 0x10) /* Rx registers */
-#define XEM_PFIFO_TXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x100) /* Tx keyhole */
-#define XEM_PFIFO_RXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x200) /* Rx keyhole */
-
-/*
- * EMAC Module Identification Register (EMIR)
- */
-#define XEM_EMIR_VERSION_MASK 0xFFFF0000UL /* Device version */
-#define XEM_EMIR_TYPE_MASK 0x0000FF00UL /* Device type */
-
-/*
- * EMAC Control Register (ECR)
- */
-#define XEM_ECR_FULL_DUPLEX_MASK 0x80000000UL /* Full duplex mode */
-#define XEM_ECR_XMIT_RESET_MASK 0x40000000UL /* Reset transmitter */
-#define XEM_ECR_XMIT_ENABLE_MASK 0x20000000UL /* Enable transmitter */
-#define XEM_ECR_RECV_RESET_MASK 0x10000000UL /* Reset receiver */
-#define XEM_ECR_RECV_ENABLE_MASK 0x08000000UL /* Enable receiver */
-#define XEM_ECR_PHY_ENABLE_MASK 0x04000000UL /* Enable PHY */
-#define XEM_ECR_XMIT_PAD_ENABLE_MASK 0x02000000UL /* Enable xmit pad insert */
-#define XEM_ECR_XMIT_FCS_ENABLE_MASK 0x01000000UL /* Enable xmit FCS insert */
-#define XEM_ECR_XMIT_ADDR_INSERT_MASK 0x00800000UL /* Enable xmit source addr
- * insertion */
-#define XEM_ECR_XMIT_ERROR_INSERT_MASK 0x00400000UL /* Insert xmit error */
-#define XEM_ECR_XMIT_ADDR_OVWRT_MASK 0x00200000UL /* Enable xmit source addr
- * overwrite */
-#define XEM_ECR_LOOPBACK_MASK 0x00100000UL /* Enable internal
- * loopback */
-#define XEM_ECR_RECV_STRIP_ENABLE_MASK 0x00080000UL /* Enable recv pad/fcs strip */
-#define XEM_ECR_UNICAST_ENABLE_MASK 0x00020000UL /* Enable unicast addr */
-#define XEM_ECR_MULTI_ENABLE_MASK 0x00010000UL /* Enable multicast addr */
-#define XEM_ECR_BROAD_ENABLE_MASK 0x00008000UL /* Enable broadcast addr */
-#define XEM_ECR_PROMISC_ENABLE_MASK 0x00004000UL /* Enable promiscuous mode */
-#define XEM_ECR_RECV_ALL_MASK 0x00002000UL /* Receive all frames */
-#define XEM_ECR_RESERVED2_MASK 0x00001000UL /* Reserved */
-#define XEM_ECR_MULTI_HASH_ENABLE_MASK 0x00000800UL /* Enable multicast hash */
-#define XEM_ECR_PAUSE_FRAME_MASK 0x00000400UL /* Interpret pause frames */
-#define XEM_ECR_CLEAR_HASH_MASK 0x00000200UL /* Clear hash table */
-#define XEM_ECR_ADD_HASH_ADDR_MASK 0x00000100UL /* Add hash table address */
-
-/*
- * Interframe Gap Register (IFGR)
- */
-#define XEM_IFGP_PART1_MASK 0xF8000000UL /* Interframe Gap Part1 */
-#define XEM_IFGP_PART1_SHIFT 27
-#define XEM_IFGP_PART2_MASK 0x07C00000UL /* Interframe Gap Part2 */
-#define XEM_IFGP_PART2_SHIFT 22
-
-/*
- * Station Address High Register (SAH)
- */
-#define XEM_SAH_ADDR_MASK 0x0000FFFFUL /* Station address high bytes */
-
-/*
- * Station Address Low Register (SAL)
- */
-#define XEM_SAL_ADDR_MASK 0xFFFFFFFFUL /* Station address low bytes */
-
-/*
- * MII Management Control Register (MGTCR)
- */
-#define XEM_MGTCR_START_MASK 0x80000000UL /* Start/Busy */
-#define XEM_MGTCR_RW_NOT_MASK 0x40000000UL /* Read/Write Not (direction) */
-#define XEM_MGTCR_PHY_ADDR_MASK 0x3E000000UL /* PHY address */
-#define XEM_MGTCR_PHY_ADDR_SHIFT 25 /* PHY address shift */
-#define XEM_MGTCR_REG_ADDR_MASK 0x01F00000UL /* Register address */
-#define XEM_MGTCR_REG_ADDR_SHIFT 20 /* Register addr shift */
-#define XEM_MGTCR_MII_ENABLE_MASK 0x00080000UL /* Enable MII from EMAC */
-#define XEM_MGTCR_RD_ERROR_MASK 0x00040000UL /* MII mgmt read error */
-
-/*
- * MII Management Data Register (MGTDR)
- */
-#define XEM_MGTDR_DATA_MASK 0x0000FFFFUL /* MII data */
-
-/*
- * Receive Packet Length Register (RPLR)
- */
-#define XEM_RPLR_LENGTH_MASK 0x0000FFFFUL /* Receive packet length */
-
-/*
- * Transmit Packet Length Register (TPLR)
- */
-#define XEM_TPLR_LENGTH_MASK 0x0000FFFFUL /* Transmit packet length */
-
-/*
- * Transmit Status Register (TSR)
- */
-#define XEM_TSR_EXCESS_DEFERRAL_MASK 0x80000000UL /* Transmit excess deferral */
-#define XEM_TSR_FIFO_UNDERRUN_MASK 0x40000000UL /* Packet FIFO underrun */
-#define XEM_TSR_ATTEMPTS_MASK 0x3E000000UL /* Transmission attempts */
-#define XEM_TSR_LATE_COLLISION_MASK 0x01000000UL /* Transmit late collision */
-
-/*
- * Receive Missed Frame Count (RMFC)
- */
-#define XEM_RMFC_DATA_MASK 0x0000FFFFUL
-
-/*
- * Receive Collision Count (RCC)
- */
-#define XEM_RCC_DATA_MASK 0x0000FFFFUL
-
-/*
- * Receive FCS Error Count (RFCSEC)
- */
-#define XEM_RFCSEC_DATA_MASK 0x0000FFFFUL
-
-/*
- * Receive Alignment Error Count (RALN)
- */
-#define XEM_RAEC_DATA_MASK 0x0000FFFFUL
-
-/*
- * Transmit Excess Deferral Count (TEDC)
- */
-#define XEM_TEDC_DATA_MASK 0x0000FFFFUL
-
-/*
- * EMAC Interrupt Registers (Status and Enable) masks. These registers are
- * part of the IPIF IP Interrupt registers
- */
-#define XEM_EIR_XMIT_DONE_MASK 0x00000001UL /* Xmit complete */
-#define XEM_EIR_RECV_DONE_MASK 0x00000002UL /* Recv complete */
-#define XEM_EIR_XMIT_ERROR_MASK 0x00000004UL /* Xmit error */
-#define XEM_EIR_RECV_ERROR_MASK 0x00000008UL /* Recv error */
-#define XEM_EIR_XMIT_SFIFO_EMPTY_MASK 0x00000010UL /* Xmit status fifo empty */
-#define XEM_EIR_RECV_LFIFO_EMPTY_MASK 0x00000020UL /* Recv length fifo empty */
-#define XEM_EIR_XMIT_LFIFO_FULL_MASK 0x00000040UL /* Xmit length fifo full */
-#define XEM_EIR_RECV_LFIFO_OVER_MASK 0x00000080UL /* Recv length fifo
- * overrun */
-#define XEM_EIR_RECV_LFIFO_UNDER_MASK 0x00000100UL /* Recv length fifo
- * underrun */
-#define XEM_EIR_XMIT_SFIFO_OVER_MASK 0x00000200UL /* Xmit status fifo
- * overrun */
-#define XEM_EIR_XMIT_SFIFO_UNDER_MASK 0x00000400UL /* Transmit status fifo
- * underrun */
-#define XEM_EIR_XMIT_LFIFO_OVER_MASK 0x00000800UL /* Transmit length fifo
- * overrun */
-#define XEM_EIR_XMIT_LFIFO_UNDER_MASK 0x00001000UL /* Transmit length fifo
- * underrun */
-#define XEM_EIR_XMIT_PAUSE_MASK 0x00002000UL /* Transmit pause pkt
- * received */
-#define XEM_EIR_RECV_DFIFO_OVER_MASK 0x00004000UL /* Receive data fifo
- * overrun */
-#define XEM_EIR_RECV_MISSED_FRAME_MASK 0x00008000UL /* Receive missed frame
- * error */
-#define XEM_EIR_RECV_COLLISION_MASK 0x00010000UL /* Receive collision
- * error */
-#define XEM_EIR_RECV_FCS_ERROR_MASK 0x00020000UL /* Receive FCS error */
-#define XEM_EIR_RECV_LEN_ERROR_MASK 0x00040000UL /* Receive length field
- * error */
-#define XEM_EIR_RECV_SHORT_ERROR_MASK 0x00080000UL /* Receive short frame
- * error */
-#define XEM_EIR_RECV_LONG_ERROR_MASK 0x00100000UL /* Receive long frame
- * error */
-#define XEM_EIR_RECV_ALIGN_ERROR_MASK 0x00200000UL /* Receive alignment
- * error */
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************
-*
-* Low-level driver macros and functions. The list below provides signatures
-* to help the user use the macros.
-*
-* u32 XEmac_mReadReg(u32 BaseAddress, int RegOffset)
-* void XEmac_mWriteReg(u32 BaseAddress, int RegOffset, u32 Mask)
-*
-* void XEmac_mSetControlReg(u32 BaseAddress, u32 Mask)
-* void XEmac_mSetMacAddress(u32 BaseAddress, u8 *AddressPtr)
-*
-* void XEmac_mEnable(u32 BaseAddress)
-* void XEmac_mDisable(u32 BaseAddress)
-*
-* u32 XEmac_mIsTxDone(u32 BaseAddress)
-* u32 XEmac_mIsRxEmpty(u32 BaseAddress)
-*
-* void XEmac_SendFrame(u32 BaseAddress, u8 *FramePtr, int Size)
-* int XEmac_RecvFrame(u32 BaseAddress, u8 *FramePtr)
-*
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* Read the given register.
-*
-* @param BaseAddress is the base address of the device
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note None.
-*
-*****************************************************************************/
-#define XEmac_mReadReg(BaseAddress, RegOffset) \
- XIo_In32((BaseAddress) + (RegOffset))
-
-/****************************************************************************/
-/**
-*
-* Write the given register.
-*
-* @param BaseAddress is the base address of the device
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XEmac_mWriteReg(BaseAddress, RegOffset, Data) \
- XIo_Out32((BaseAddress) + (RegOffset), (Data))
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the control register. Use the XEM_ECR_* constants
-* defined above to create the bit-mask to be written to the register.
-*
-* @param BaseAddress is the base address of the device
-* @param Mask is the 16-bit value to write to the control register
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XEmac_mSetControlReg(BaseAddress, Mask) \
- XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, (Mask))
-
-/****************************************************************************/
-/**
-*
-* Set the station address of the EMAC device.
-*
-* @param BaseAddress is the base address of the device
-* @param AddressPtr is a pointer to a 6-byte MAC address
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XEmac_mSetMacAddress(BaseAddress, AddressPtr) \
-{ \
- u32 MacAddr; \
- \
- MacAddr = ((AddressPtr)[0] << 8) | (AddressPtr)[1]; \
- XIo_Out32((BaseAddress) + XEM_SAH_OFFSET, MacAddr); \
- \
- MacAddr = ((AddressPtr)[2] << 24) | ((AddressPtr)[3] << 16) | \
- ((AddressPtr)[4] << 8) | (AddressPtr)[5]; \
- \
- XIo_Out32((BaseAddress) + XEM_SAL_OFFSET, MacAddr); \
-}
-
-/****************************************************************************/
-/**
-*
-* Enable the transmitter and receiver. Preserve the contents of the control
-* register.
-*
-* @param BaseAddress is the base address of the device
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XEmac_mEnable(BaseAddress) \
-{ \
- u32 Control; \
- Control = XIo_In32((BaseAddress) + XEM_ECR_OFFSET); \
- Control &= ~(XEM_ECR_XMIT_RESET_MASK | XEM_ECR_RECV_RESET_MASK); \
- Control |= (XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK); \
- XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, Control); \
-}
-
-/****************************************************************************/
-/**
-*
-* Disable the transmitter and receiver. Preserve the contents of the control
-* register.
-*
-* @param BaseAddress is the base address of the device
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XEmac_mDisable(BaseAddress) \
- XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, \
- XIo_In32((BaseAddress) + XEM_ECR_OFFSET) & \
- ~(XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK))
-
-/****************************************************************************/
-/**
-*
-* Check to see if the transmission is complete.
-*
-* @param BaseAddress is the base address of the device
-*
-* @return TRUE if it is done, or FALSE if it is not.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XEmac_mIsTxDone(BaseAddress) \
- (XIo_In32((BaseAddress) + XEM_ISR_OFFSET) & XEM_EIR_XMIT_DONE_MASK)
-
-/****************************************************************************/
-/**
-*
-* Check to see if the receive FIFO is empty.
-*
-* @param BaseAddress is the base address of the device
-*
-* @return TRUE if it is empty, or FALSE if it is not.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XEmac_mIsRxEmpty(BaseAddress) \
- (!(XIo_In32((BaseAddress) + XEM_ISR_OFFSET) & XEM_EIR_RECV_DONE_MASK))
-
-/****************************************************************************/
-/**
-*
-* Reset MII compliant PHY
-*
-* @param BaseAddress is the base address of the device
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XEmac_mPhyReset(BaseAddress) \
-{ \
- u32 Control; \
- Control = XIo_In32((BaseAddress) + XEM_ECR_OFFSET); \
- Control &= ~XEM_ECR_PHY_ENABLE_MASK; \
- XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, Control); \
- Control |= XEM_ECR_PHY_ENABLE_MASK; \
- XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, Control); \
-}
-
-/************************** Function Prototypes ******************************/
-
-void XEmac_SendFrame(u32 BaseAddress, u8 * FramePtr, int Size);
-int XEmac_RecvFrame(u32 BaseAddress, u8 * FramePtr);
-
-#endif /* end of protection macro */
+++ /dev/null
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xemac_options.c
-*
-* Functions in this file handle configuration of the XEmac driver.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rpm 07/31/01 First release
-* 1.00b rpm 02/20/02 Repartitioned files and functions
-* 1.00c rpm 12/05/02 New version includes support for simple DMA
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xbasic_types.h"
-#include "xemac_i.h"
-#include "xio.h"
-
-/************************** Constant Definitions *****************************/
-
-#define XEM_MAX_IFG 32 /* Maximum Interframe gap value */
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/*
- * A table of options and masks. This table maps the user-visible options with
- * the control register masks. It is used in Set/GetOptions as an alternative
- * to a series of if/else pairs. Note that the polled options does not have a
- * corresponding entry in the control register, so it does not exist in the
- * table.
- */
-typedef struct {
- u32 Option;
- u32 Mask;
-} OptionMap;
-
-static OptionMap OptionsTable[] = {
- {XEM_UNICAST_OPTION, XEM_ECR_UNICAST_ENABLE_MASK},
- {XEM_BROADCAST_OPTION, XEM_ECR_BROAD_ENABLE_MASK},
- {XEM_PROMISC_OPTION, XEM_ECR_PROMISC_ENABLE_MASK},
- {XEM_FDUPLEX_OPTION, XEM_ECR_FULL_DUPLEX_MASK},
- {XEM_LOOPBACK_OPTION, XEM_ECR_LOOPBACK_MASK},
- {XEM_MULTICAST_OPTION, XEM_ECR_MULTI_ENABLE_MASK},
- {XEM_FLOW_CONTROL_OPTION, XEM_ECR_PAUSE_FRAME_MASK},
- {XEM_INSERT_PAD_OPTION, XEM_ECR_XMIT_PAD_ENABLE_MASK},
- {XEM_INSERT_FCS_OPTION, XEM_ECR_XMIT_FCS_ENABLE_MASK},
- {XEM_INSERT_ADDR_OPTION, XEM_ECR_XMIT_ADDR_INSERT_MASK},
- {XEM_OVWRT_ADDR_OPTION, XEM_ECR_XMIT_ADDR_OVWRT_MASK},
- {XEM_STRIP_PAD_FCS_OPTION, XEM_ECR_RECV_STRIP_ENABLE_MASK}
-};
-
-#define XEM_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(OptionMap))
-
-/*****************************************************************************/
-/**
-*
-* Set Ethernet driver/device options. The device must be stopped before
-* calling this function. The options are contained within a bit-mask with each
-* bit representing an option (i.e., you can OR the options together). A one (1)
-* in the bit-mask turns an option on, and a zero (0) turns the option off.
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-* @param OptionsFlag is a bit-mask representing the Ethernet options to turn on
-* or off. See xemac.h for a description of the available options.
-*
-* @return
-*
-* - XST_SUCCESS if the options were set successfully
-* - XST_DEVICE_IS_STARTED if the device has not yet been stopped
-*
-* @note
-*
-* This function is not thread-safe and makes use of internal resources that are
-* shared between the Start, Stop, and SetOptions functions, so if one task
-* might be setting device options while another is trying to start the device,
-* protection of this shared data (typically using a semaphore) is required.
-*
-******************************************************************************/
-XStatus
-XEmac_SetOptions(XEmac * InstancePtr, u32 OptionsFlag)
-{
- u32 ControlReg;
- int Index;
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) {
- return XST_DEVICE_IS_STARTED;
- }
-
- ControlReg = XIo_In32(InstancePtr->BaseAddress + XEM_ECR_OFFSET);
-
- /*
- * Loop through the options table, turning the option on or off
- * depending on whether the bit is set in the incoming options flag.
- */
- for (Index = 0; Index < XEM_NUM_OPTIONS; Index++) {
- if (OptionsFlag & OptionsTable[Index].Option) {
- ControlReg |= OptionsTable[Index].Mask; /* turn it on */
- } else {
- ControlReg &= ~OptionsTable[Index].Mask; /* turn it off */
- }
- }
-
- /*
- * TODO: need to validate addr-overwrite only if addr-insert?
- */
-
- /*
- * Now write the control register. Leave it to the upper layers
- * to restart the device.
- */
- XIo_Out32(InstancePtr->BaseAddress + XEM_ECR_OFFSET, ControlReg);
-
- /*
- * Check the polled option
- */
- if (OptionsFlag & XEM_POLLED_OPTION) {
- InstancePtr->IsPolled = TRUE;
- } else {
- InstancePtr->IsPolled = FALSE;
- }
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Get Ethernet driver/device options. The 32-bit value returned is a bit-mask
-* representing the options. A one (1) in the bit-mask means the option is on,
-* and a zero (0) means the option is off.
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-*
-* @return
-*
-* The 32-bit value of the Ethernet options. The value is a bit-mask
-* representing all options that are currently enabled. See xemac.h for a
-* description of the available options.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-u32
-XEmac_GetOptions(XEmac * InstancePtr)
-{
- u32 OptionsFlag = 0;
- u32 ControlReg;
- int Index;
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /*
- * Get the control register to determine which options are currently set.
- */
- ControlReg = XIo_In32(InstancePtr->BaseAddress + XEM_ECR_OFFSET);
-
- /*
- * Loop through the options table to determine which options are set
- */
- for (Index = 0; Index < XEM_NUM_OPTIONS; Index++) {
- if (ControlReg & OptionsTable[Index].Mask) {
- OptionsFlag |= OptionsTable[Index].Option;
- }
- }
-
- if (InstancePtr->IsPolled) {
- OptionsFlag |= XEM_POLLED_OPTION;
- }
-
- return OptionsFlag;
-}
-
-/*****************************************************************************/
-/**
-*
-* Set the Interframe Gap (IFG), which is the time the MAC delays between
-* transmitting frames. There are two parts required. The total interframe gap
-* is the total of the two parts. The values provided for the Part1 and Part2
-* parameters are multiplied by 4 to obtain the bit-time interval. The first
-* part should be the first 2/3 of the total interframe gap. The MAC will reset
-* the interframe gap timer if carrier sense becomes true during the period
-* defined by interframe gap Part1. Part1 may be shorter than 2/3 the total and
-* can be as small as zero. The second part should be the last 1/3 of the total
-* interframe gap, but can be as large as the total interframe gap. The MAC
-* will not reset the interframe gap timer if carrier sense becomes true during
-* the period defined by interframe gap Part2.
-*
-* The device must be stopped before setting the interframe gap.
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-* @param Part1 is the interframe gap part 1 (which will be multiplied by 4 to
-* get the bit-time interval).
-* @param Part2 is the interframe gap part 2 (which will be multiplied by 4 to
-* get the bit-time interval).
-*
-* @return
-*
-* - XST_SUCCESS if the interframe gap was set successfully
-* - XST_DEVICE_IS_STARTED if the device has not been stopped
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-XStatus
-XEmac_SetInterframeGap(XEmac * InstancePtr, u8 Part1, u8 Part2)
-{
- u32 Ifg;
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(Part1 < XEM_MAX_IFG);
- XASSERT_NONVOID(Part2 < XEM_MAX_IFG);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /*
- * Be sure device has been stopped
- */
- if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) {
- return XST_DEVICE_IS_STARTED;
- }
-
- Ifg = Part1 << XEM_IFGP_PART1_SHIFT;
- Ifg |= (Part2 << XEM_IFGP_PART2_SHIFT);
- XIo_Out32(InstancePtr->BaseAddress + XEM_IFGP_OFFSET, Ifg);
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Get the interframe gap, parts 1 and 2. See the description of interframe gap
-* above in XEmac_SetInterframeGap().
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-* @param Part1Ptr is a pointer to an 8-bit buffer into which the interframe gap
-* part 1 value will be copied.
-* @param Part2Ptr is a pointer to an 8-bit buffer into which the interframe gap
-* part 2 value will be copied.
-*
-* @return
-*
-* None. The values of the interframe gap parts are copied into the
-* output parameters.
-*
-******************************************************************************/
-void
-XEmac_GetInterframeGap(XEmac * InstancePtr, u8 * Part1Ptr, u8 * Part2Ptr)
-{
- u32 Ifg;
-
- XASSERT_VOID(InstancePtr != NULL);
- XASSERT_VOID(Part1Ptr != NULL);
- XASSERT_VOID(Part2Ptr != NULL);
- XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- Ifg = XIo_In32(InstancePtr->BaseAddress + XEM_IFGP_OFFSET);
- *Part1Ptr = (Ifg & XEM_IFGP_PART1_MASK) >> XEM_IFGP_PART1_SHIFT;
- *Part2Ptr = (Ifg & XEM_IFGP_PART2_MASK) >> XEM_IFGP_PART2_SHIFT;
-}
+++ /dev/null
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xemac_polled.c
-*
-* Contains functions used when the driver is in polled mode. Use the
-* XEmac_SetOptions() function to put the driver into polled mode.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rpm 07/31/01 First release
-* 1.00b rpm 02/20/02 Repartitioned files and functions
-* 1.00c rpm 12/05/02 New version includes support for simple DMA
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xbasic_types.h"
-#include "xemac_i.h"
-#include "xio.h"
-#include "xipif_v1_23_b.h" /* Uses v1.23b of the IPIF */
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-*
-* Send an Ethernet frame in polled mode. The device/driver must be in polled
-* mode before calling this function. The driver writes the frame directly to
-* the MAC's packet FIFO, then enters a loop checking the device status for
-* completion or error. Statistics are updated if an error occurs. The buffer
-* to be sent must be word-aligned.
-*
-* It is assumed that the upper layer software supplies a correctly formatted
-* Ethernet frame, including the destination and source addresses, the
-* type/length field, and the data field. It is also assumed that upper layer
-* software does not append FCS at the end of the frame.
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-* @param BufPtr is a pointer to a word-aligned buffer containing the Ethernet
-* frame to be sent.
-* @param ByteCount is the size of the Ethernet frame.
-*
-* @return
-*
-* - XST_SUCCESS if the frame was sent successfully
-* - XST_DEVICE_IS_STOPPED if the device has not yet been started
-* - XST_NOT_POLLED if the device is not in polled mode
-* - XST_FIFO_NO_ROOM if there is no room in the EMAC's length FIFO for this frame
-* - XST_FIFO_ERROR if the FIFO was overrun or underrun. This error is critical
-* and requires the caller to reset the device.
-* - XST_EMAC_COLLISION if the send failed due to excess deferral or late
-* collision
-*
-* @note
-*
-* There is the possibility that this function will not return if the hardware
-* is broken (i.e., it never sets the status bit indicating that transmission is
-* done). If this is of concern to the user, the user should provide protection
-* from this problem - perhaps by using a different timer thread to monitor the
-* PollSend thread. On a 10Mbps MAC, it takes about 1.21 msecs to transmit a
-* maximum size Ethernet frame (1518 bytes). On a 100Mbps MAC, it takes about
-* 121 usecs to transmit a maximum size Ethernet frame.
-*
-* @internal
-*
-* The EMAC uses FIFOs behind its length and status registers. For this reason,
-* it is important to keep the length, status, and data FIFOs in sync when
-* reading or writing to them.
-*
-******************************************************************************/
-XStatus
-XEmac_PollSend(XEmac * InstancePtr, u8 * BufPtr, u32 ByteCount)
-{
- u32 IntrStatus;
- u32 XmitStatus;
- XStatus Result;
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(BufPtr != NULL);
- XASSERT_NONVOID(ByteCount > XEM_HDR_SIZE); /* send at least 1 byte */
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /*
- * Be sure the device is configured for polled mode and it is started
- */
- if (!InstancePtr->IsPolled) {
- return XST_NOT_POLLED;
- }
-
- if (InstancePtr->IsStarted != XCOMPONENT_IS_STARTED) {
- return XST_DEVICE_IS_STOPPED;
- }
-
- /*
- * Check for overruns and underruns for the transmit status and length
- * FIFOs and make sure the send packet FIFO is not deadlocked. Any of these
- * conditions is bad enough that we do not want to continue. The upper layer
- * software should reset the device to resolve the error.
- */
- IntrStatus = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress);
-
- /*
- * Overrun errors
- */
- if (IntrStatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
- XEM_EIR_XMIT_LFIFO_OVER_MASK)) {
- InstancePtr->Stats.XmitOverrunErrors++;
- InstancePtr->Stats.FifoErrors++;
- return XST_FIFO_ERROR;
- }
-
- /*
- * Underrun errors
- */
- if (IntrStatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
- XEM_EIR_XMIT_LFIFO_UNDER_MASK)) {
- InstancePtr->Stats.XmitUnderrunErrors++;
- InstancePtr->Stats.FifoErrors++;
- return XST_FIFO_ERROR;
- }
-
- if (XPF_V100B_IS_DEADLOCKED(&InstancePtr->SendFifo)) {
- InstancePtr->Stats.FifoErrors++;
- return XST_FIFO_ERROR;
- }
-
- /*
- * Before writing to the data FIFO, make sure the length FIFO is not
- * full. The data FIFO might not be full yet even though the length FIFO
- * is. This avoids an overrun condition on the length FIFO and keeps the
- * FIFOs in sync.
- */
- if (IntrStatus & XEM_EIR_XMIT_LFIFO_FULL_MASK) {
- /*
- * Clear the latched LFIFO_FULL bit so next time around the most
- * current status is represented
- */
- XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress,
- XEM_EIR_XMIT_LFIFO_FULL_MASK);
- return XST_FIFO_NO_ROOM;
- }
-
- /*
- * This is a non-blocking write. The packet FIFO returns an error if there
- * is not enough room in the FIFO for this frame.
- */
- Result =
- XPacketFifoV100b_Write(&InstancePtr->SendFifo, BufPtr, ByteCount);
- if (Result != XST_SUCCESS) {
- return Result;
- }
-
- /*
- * Loop on the MAC's status to wait for any pause to complete.
- */
- IntrStatus = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress);
-
- while ((IntrStatus & XEM_EIR_XMIT_PAUSE_MASK) != 0) {
- IntrStatus = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress);
- /*
- * Clear the pause status from the transmit status register
- */
- XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress,
- IntrStatus & XEM_EIR_XMIT_PAUSE_MASK);
- }
-
- /*
- * Set the MAC's transmit packet length register to tell it to transmit
- */
- XIo_Out32(InstancePtr->BaseAddress + XEM_TPLR_OFFSET, ByteCount);
-
- /*
- * Loop on the MAC's status to wait for the transmit to complete. The
- * transmit status is in the FIFO when the XMIT_DONE bit is set.
- */
- do {
- IntrStatus = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress);
- }
- while ((IntrStatus & XEM_EIR_XMIT_DONE_MASK) == 0);
-
- XmitStatus = XIo_In32(InstancePtr->BaseAddress + XEM_TSR_OFFSET);
-
- InstancePtr->Stats.XmitFrames++;
- InstancePtr->Stats.XmitBytes += ByteCount;
-
- /*
- * Check for various errors, bump statistics, and return an error status.
- */
-
- /*
- * Overrun errors
- */
- if (IntrStatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
- XEM_EIR_XMIT_LFIFO_OVER_MASK)) {
- InstancePtr->Stats.XmitOverrunErrors++;
- InstancePtr->Stats.FifoErrors++;
- return XST_FIFO_ERROR;
- }
-
- /*
- * Underrun errors
- */
- if (IntrStatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
- XEM_EIR_XMIT_LFIFO_UNDER_MASK)) {
- InstancePtr->Stats.XmitUnderrunErrors++;
- InstancePtr->Stats.FifoErrors++;
- return XST_FIFO_ERROR;
- }
-
- /*
- * Clear the interrupt status register of transmit statuses
- */
- XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress,
- IntrStatus & XEM_EIR_XMIT_ALL_MASK);
-
- /*
- * Collision errors are stored in the transmit status register
- * instead of the interrupt status register
- */
- if (XmitStatus & XEM_TSR_EXCESS_DEFERRAL_MASK) {
- InstancePtr->Stats.XmitExcessDeferral++;
- return XST_EMAC_COLLISION_ERROR;
- }
-
- if (XmitStatus & XEM_TSR_LATE_COLLISION_MASK) {
- InstancePtr->Stats.XmitLateCollisionErrors++;
- return XST_EMAC_COLLISION_ERROR;
- }
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Receive an Ethernet frame in polled mode. The device/driver must be in polled
-* mode before calling this function. The driver receives the frame directly
-* from the MAC's packet FIFO. This is a non-blocking receive, in that if there
-* is no frame ready to be received at the device, the function returns with an
-* error. The MAC's error status is not checked, so statistics are not updated
-* for polled receive. The buffer into which the frame will be received must be
-* word-aligned.
-*
-* @param InstancePtr is a pointer to the XEmac instance to be worked on.
-* @param BufPtr is a pointer to a word-aligned buffer into which the received
-* Ethernet frame will be copied.
-* @param ByteCountPtr is both an input and an output parameter. It is a pointer
-* to a 32-bit word that contains the size of the buffer on entry into the
-* function and the size the received frame on return from the function.
-*
-* @return
-*
-* - XST_SUCCESS if the frame was sent successfully
-* - XST_DEVICE_IS_STOPPED if the device has not yet been started
-* - XST_NOT_POLLED if the device is not in polled mode
-* - XST_NO_DATA if there is no frame to be received from the FIFO
-* - XST_BUFFER_TOO_SMALL if the buffer to receive the frame is too small for
-* the frame waiting in the FIFO.
-*
-* @note
-*
-* Input buffer must be big enough to hold the largest Ethernet frame. Buffer
-* must also be 32-bit aligned.
-*
-* @internal
-*
-* The EMAC uses FIFOs behind its length and status registers. For this reason,
-* it is important to keep the length, status, and data FIFOs in sync when
-* reading or writing to them.
-*
-******************************************************************************/
-XStatus
-XEmac_PollRecv(XEmac * InstancePtr, u8 * BufPtr, u32 * ByteCountPtr)
-{
- XStatus Result;
- u32 PktLength;
- u32 IntrStatus;
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(BufPtr != NULL);
- XASSERT_NONVOID(ByteCountPtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /*
- * Be sure the device is configured for polled mode and it is started
- */
- if (!InstancePtr->IsPolled) {
- return XST_NOT_POLLED;
- }
-
- if (InstancePtr->IsStarted != XCOMPONENT_IS_STARTED) {
- return XST_DEVICE_IS_STOPPED;
- }
-
- /*
- * Make sure the buffer is big enough to hold the maximum frame size.
- * We need to do this because as soon as we read the MAC's packet length
- * register, which is actually a FIFO, we remove that length from the
- * FIFO. We do not want to read the length FIFO without also reading the
- * data FIFO since this would get the FIFOs out of sync. So we have to
- * make this restriction.
- */
- if (*ByteCountPtr < XEM_MAX_FRAME_SIZE) {
- return XST_BUFFER_TOO_SMALL;
- }
-
- /*
- * First check for packet FIFO deadlock and return an error if it has
- * occurred. A reset by the caller is necessary to correct this problem.
- */
- if (XPF_V100B_IS_DEADLOCKED(&InstancePtr->RecvFifo)) {
- InstancePtr->Stats.FifoErrors++;
- return XST_FIFO_ERROR;
- }
-
- /*
- * Get the interrupt status to know what happened (whether an error occurred
- * and/or whether frames have been received successfully). When clearing the
- * intr status register, clear only statuses that pertain to receive.
- */
- IntrStatus = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress);
- XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress,
- IntrStatus & XEM_EIR_RECV_ALL_MASK);
-
- /*
- * Check receive errors and bump statistics so the caller will have a clue
- * as to why data may not have been received. We continue on if an error
- * occurred since there still may be frames that were received successfully.
- */
- if (IntrStatus & (XEM_EIR_RECV_LFIFO_OVER_MASK |
- XEM_EIR_RECV_DFIFO_OVER_MASK)) {
- InstancePtr->Stats.RecvOverrunErrors++;
- InstancePtr->Stats.FifoErrors++;
- }
-
- if (IntrStatus & XEM_EIR_RECV_LFIFO_UNDER_MASK) {
- InstancePtr->Stats.RecvUnderrunErrors++;
- InstancePtr->Stats.FifoErrors++;
- }
-
- /*
- * General receive errors
- */
- if (IntrStatus & XEM_EIR_RECV_ERROR_MASK) {
- if (IntrStatus & XEM_EIR_RECV_MISSED_FRAME_MASK) {
- InstancePtr->Stats.RecvMissedFrameErrors =
- XIo_In32(InstancePtr->BaseAddress +
- XEM_RMFC_OFFSET);
- }
-
- if (IntrStatus & XEM_EIR_RECV_COLLISION_MASK) {
- InstancePtr->Stats.RecvCollisionErrors =
- XIo_In32(InstancePtr->BaseAddress + XEM_RCC_OFFSET);
- }
-
- if (IntrStatus & XEM_EIR_RECV_FCS_ERROR_MASK) {
- InstancePtr->Stats.RecvFcsErrors =
- XIo_In32(InstancePtr->BaseAddress +
- XEM_RFCSEC_OFFSET);
- }
-
- if (IntrStatus & XEM_EIR_RECV_LEN_ERROR_MASK) {
- InstancePtr->Stats.RecvLengthFieldErrors++;
- }
-
- if (IntrStatus & XEM_EIR_RECV_SHORT_ERROR_MASK) {
- InstancePtr->Stats.RecvShortErrors++;
- }
-
- if (IntrStatus & XEM_EIR_RECV_LONG_ERROR_MASK) {
- InstancePtr->Stats.RecvLongErrors++;
- }
-
- if (IntrStatus & XEM_EIR_RECV_ALIGN_ERROR_MASK) {
- InstancePtr->Stats.RecvAlignmentErrors =
- XIo_In32(InstancePtr->BaseAddress +
- XEM_RAEC_OFFSET);
- }
- }
-
- /*
- * Before reading from the length FIFO, make sure the length FIFO is not
- * empty. We could cause an underrun error if we try to read from an
- * empty FIFO.
- */
- if ((IntrStatus & XEM_EIR_RECV_DONE_MASK) == 0) {
- return XST_NO_DATA;
- }
-
- /*
- * Determine, from the MAC, the length of the next packet available
- * in the data FIFO (there should be a non-zero length here)
- */
- PktLength = XIo_In32(InstancePtr->BaseAddress + XEM_RPLR_OFFSET);
- if (PktLength == 0) {
- return XST_NO_DATA;
- }
-
- /*
- * Write the RECV_DONE bit in the status register to clear it. This bit
- * indicates the RPLR is non-empty, and we know it's set at this point.
- * We clear it so that subsequent entry into this routine will reflect the
- * current status. This is done because the non-empty bit is latched in the
- * IPIF, which means it may indicate a non-empty condition even though
- * there is something in the FIFO.
- */
- XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress, XEM_EIR_RECV_DONE_MASK);
-
- /*
- * We assume that the MAC never has a length bigger than the largest
- * Ethernet frame, so no need to make another check here.
- */
-
- /*
- * This is a non-blocking read. The FIFO returns an error if there is
- * not at least the requested amount of data in the FIFO.
- */
- Result =
- XPacketFifoV100b_Read(&InstancePtr->RecvFifo, BufPtr, PktLength);
- if (Result != XST_SUCCESS) {
- return Result;
- }
-
- InstancePtr->Stats.RecvFrames++;
- InstancePtr->Stats.RecvBytes += PktLength;
-
- *ByteCountPtr = PktLength;
-
- return XST_SUCCESS;
-}
+++ /dev/null
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-
-#include <config.h>
-#include <common.h>
-#include <environment.h>
-#include <net.h>
-
-#ifdef CONFIG_ENV_IS_IN_EEPROM
-#include <i2c.h>
-#include "xiic_l.h"
-
-#define IIC_DELAY 5000
-
-static u8 envStep = 0; /* 0 means crc has not been read */
-const u8 hex[] = "0123456789ABCDEF"; /* lookup table for ML300 CRC */
-
-/************************************************************************
- * Use Xilinx provided driver to send data to EEPROM using iic bus.
- */
-static void
-send(u32 adr, u8 * data, u32 len)
-{
- u8 sendBuf[34]; /* first 2-bit is address and others are data */
- u32 pos, wlen;
- u32 ret;
-
- wlen = 32;
- for (pos = 0; pos < len; pos += 32) {
- if ((len - pos) < 32)
- wlen = len - pos;
-
- /* Put address and data bits together */
- sendBuf[0] = (u8) ((adr + pos) >> 8);
- sendBuf[1] = (u8) (adr + pos);
- memcpy(&sendBuf[2], &data[pos], wlen);
-
- /* Send to EEPROM through iic bus */
- ret = XIic_Send(XPAR_IIC_0_BASEADDR, CONFIG_SYS_I2C_EEPROM_ADDR >> 1,
- sendBuf, wlen + 2);
-
- udelay(IIC_DELAY);
- }
-}
-
-/************************************************************************
- * Use Xilinx provided driver to read data from EEPROM using the iic bus.
- */
-static void
-receive(u32 adr, u8 * data, u32 len)
-{
- u8 address[2];
- u32 ret;
-
- address[0] = (u8) (adr >> 8);
- address[1] = (u8) adr;
-
- /* Provide EEPROM address */
- ret =
- XIic_Send(XPAR_IIC_0_BASEADDR, CONFIG_SYS_I2C_EEPROM_ADDR >> 1, address,
- 2);
- /* Receive data from EEPROM */
- ret =
- XIic_Recv(XPAR_IIC_0_BASEADDR, CONFIG_SYS_I2C_EEPROM_ADDR >> 1, data, len);
-}
-
-/************************************************************************
- * Convert a hexadecimal string to its equivalent integer value.
- */
-static u8
-axtoi(u8 * hexStg)
-{
- u8 n; /* position in string */
- u8 m; /* position in digit[] to shift */
- u8 count; /* loop index */
- u8 intValue; /* integer value of hex string */
- u8 digit[2]; /* hold values to convert */
-
- for (n = 0; n < 2; n++) {
- if (hexStg[n] == '\0')
- break;
- if (hexStg[n] > 0x29 && hexStg[n] < 0x40)
- digit[n] = hexStg[n] & 0x0f;
- else if (hexStg[n] >= 'a' && hexStg[n] <= 'f')
- digit[n] = (hexStg[n] & 0x0f) + 9;
- else if (hexStg[n] >= 'A' && hexStg[n] <= 'F')
- digit[n] = (hexStg[n] & 0x0f) + 9;
- else
- break;
- }
-
- intValue = 0;
- count = n;
- m = n - 1;
- n = 0;
- while (n < count) {
- intValue = intValue | (digit[n] << (m << 2));
- m--; /* adjust the position to set */
- n++; /* next digit to process */
- }
-
- return (intValue);
-}
-
-/************************************************************************
- * Convert an integer string to its equivalent value.
- */
-static u8
-atoi(uchar * string)
-{
- u8 res = 0;
- while (*string >= '0' && *string <= '9') {
- res *= 10;
- res += *string - '0';
- string++;
- }
-
- return res;
-}
-
-/************************************************************************
- * Key-value pairs are separated by "=" sign.
- */
-static void
-findKey(uchar * buffer, int *loc, u8 len)
-{
- u32 i;
-
- for (i = 0; i < len; i++)
- if (buffer[i] == '=') {
- *loc = i;
- return;
- }
-
- /* return -1 is no "=" sign found */
- *loc = -1;
-}
-
-/************************************************************************
- * Compute a new ML300 CRC when user calls the saveenv command.
- * Also update EEPROM with new CRC value.
- */
-static u8
-update_crc(u32 len, uchar * data)
-{
- uchar temp[6] = { 'C', '=', 0x00, 0x00, 0x00, 0x00 };
- u32 crc; /* new crc value */
- u32 i;
-
- crc = 0;
-
- /* calculate new CRC */
- for (i = 0; i < len; i++)
- crc += data[i];
-
- /* CRC includes key for check sum */
- crc += 'C' + '=';
-
- /* compose new CRC to be updated */
- temp[2] = hex[(crc >> 4) & 0xf];
- temp[3] = hex[crc & 0xf];
-
- /* check to see if env size exceeded */
- if (len + 6 > ENV_SIZE) {
- printf("ERROR: not enough space to store CRC on EEPROM");
- return 1;
- }
-
- memcpy(data + len, temp, 6);
- return 0;
-}
-
-/************************************************************************
- * Read out ML300 CRC and compare it with a runtime calculated ML300 CRC.
- * If equal, then pass back a u-boot CRC value, otherwise pass back
- * junk to indicate CRC error.
-*/
-static void
-read_crc(uchar * buffer, int len)
-{
- u32 addr, n;
- u32 crc; /* runtime crc */
- u8 old[2] = { 0xff, 0xff }; /* current CRC in EEPROM */
- u8 stop; /* indication of end of env data */
- u8 pre; /* previous EEPROM data bit */
- int i, loc;
-
- addr = CONFIG_ENV_OFFSET; /* start from first env address */
- n = 0;
- pre = 1;
- stop = 1;
- crc = 0;
-
- /* calculate runtime CRC according to ML300 and read back
- old CRC stored in the EEPROM */
- while (n < CONFIG_ENV_SIZE) {
- receive(addr, buffer, len);
-
- /* found two null chars, end of env */
- if ((pre || buffer[0]) == 0)
- break;
-
- findKey(buffer, &loc, len);
-
- /* found old check sum, read and store old CRC */
- if ((loc == 0 && pre == 'C')
- || (loc > 0 && buffer[loc - 1] == 'C'))
- receive(addr + loc + 1, old, 2);
-
- pre = buffer[len - 1];
-
- /* calculate runtime ML300 CRC */
- crc += buffer[0];
- i = 1;
- do {
- crc += buffer[i];
- stop = buffer[i] || buffer[i - 1];
- i++;
- } while (stop && (i < len));
-
- if (stop == 0)
- break;
-
- n += len;
- addr += len;
- }
-
- /* exclude old CRC from runtime calculation */
- crc -= (old[0] + old[1]);
-
- /* match CRC values, send back u-boot CRC */
- if ((old[0] == hex[(crc >> 4) & 0xf])
- && (old[1] == hex[crc & 0xf])) {
- crc = 0;
- n = 0;
- addr =
- CONFIG_ENV_OFFSET - offsetof(env_t, crc) + offsetof(env_t,
- data);
- /* calculate u-boot crc */
- while (n < ENV_SIZE) {
- receive(addr, buffer, len);
- crc = crc32(crc, buffer, len);
- n += len;
- addr += len;
- }
-
- memcpy(buffer, &crc, 4);
- }
-}
-
-/************************************************************************
- * Convert IP address to hexadecimals.
- */
-static void
-ip_ml300(uchar * s, uchar * res)
-{
- char temp[2];
- u8 i;
-
- res[0] = 0x00;
-
- for (i = 0; i < 4; i++) {
- sprintf(temp, "%02x", atoi(s));
- s = (uchar *)strchr((char *)s, '.') + 1;
- strcat((char *)res, temp);
- }
-}
-
-/************************************************************************
- * Change 0xff (255), a dummy null char to 0x00.
- */
-static void
-change_null(uchar * s)
-{
- if (s != NULL) {
- change_null((uchar *)strchr((char *)s + 1, 255));
- *(strchr((char *)s, 255)) = '\0';
- }
-}
-
-/************************************************************************
- * Update environment variable name and values to u-boot standard.
- */
-void
-convert_env(void)
-{
- char *s; /* pointer to env value */
- char temp[20]; /* temp storage for addresses */
-
- /* E -> ethaddr */
- s = getenv("E");
- if (s != NULL) {
- sprintf(temp, "%c%c.%c%c.%c%c.%c%c.%c%c.%c%c",
- s[0], s[1], s[ 2], s[ 3],
- s[4], s[5], s[ 6], s[ 7],
- s[8], s[9], s[10], s[11] );
- setenv("ethaddr", temp);
- setenv("E", NULL);
- }
-
- /* L -> serial# */
- s = getenv("L");
- if (s != NULL) {
- setenv("serial#", s);
- setenv("L", NULL);
- }
-
- /* I -> ipaddr */
- s = getenv("I");
- if (s != NULL) {
- sprintf(temp, "%d.%d.%d.%d", axtoi((u8 *)s), axtoi((u8 *)(s + 2)),
- axtoi((u8 *)(s + 4)), axtoi((u8 *)(s + 6)));
- setenv("ipaddr", temp);
- setenv("I", NULL);
- }
-
- /* S -> serverip */
- s = getenv("S");
- if (s != NULL) {
- sprintf(temp, "%d.%d.%d.%d", axtoi((u8 *)s), axtoi((u8 *)(s + 2)),
- axtoi((u8 *)(s + 4)), axtoi((u8 *)(s + 6)));
- setenv("serverip", temp);
- setenv("S", NULL);
- }
-
- /* A -> bootargs */
- s = getenv("A");
- if (s != NULL) {
- setenv("bootargs", s);
- setenv("A", NULL);
- }
-
- /* F -> bootfile */
- s = getenv("F");
- if (s != NULL) {
- setenv("bootfile", s);
- setenv("F", NULL);
- }
-
- /* M -> bootcmd */
- s = getenv("M");
- if (s != NULL) {
- setenv("bootcmd", s);
- setenv("M", NULL);
- }
-
- /* Don't include C (CRC) */
- setenv("C", NULL);
-}
-
-/************************************************************************
- * Save user modified environment values back to EEPROM.
- */
-static void
-save_env(void)
-{
- char eprom[ENV_SIZE]; /* buffer to be written back to EEPROM */
- char *s, temp[20];
- char ff[] = { 0xff, 0x00 }; /* dummy null value */
- u32 len; /* length of env to be written to EEPROM */
-
- eprom[0] = 0x00;
-
- /* ethaddr -> E */
- s = getenv("ethaddr");
- if (s != NULL) {
- strcat(eprom, "E=");
- sprintf(temp, "%c%c%c%c%c%c%c%c%c%c%c%c",
- *s, *(s + 1), *(s + 3), *(s + 4), *(s + 6), *(s + 7),
- *(s + 9), *(s + 10), *(s + 12), *(s + 13), *(s + 15),
- *(s + 16));
- strcat(eprom, temp);
- strcat(eprom, ff);
- }
-
- /* serial# -> L */
- s = getenv("serial#");
- if (s != NULL) {
- strcat(eprom, "L=");
- strcat(eprom, s);
- strcat(eprom, ff);
- }
-
- /* ipaddr -> I */
- s = getenv("ipaddr");
- if (s != NULL) {
- strcat(eprom, "I=");
- ip_ml300((uchar *)s, (uchar *)temp);
- strcat(eprom, temp);
- strcat(eprom, ff);
- }
-
- /* serverip -> S */
- s = getenv("serverip");
- if (s != NULL) {
- strcat(eprom, "S=");
- ip_ml300((uchar *)s, (uchar *)temp);
- strcat(eprom, temp);
- strcat(eprom, ff);
- }
-
- /* bootargs -> A */
- s = getenv("bootargs");
- if (s != NULL) {
- strcat(eprom, "A=");
- strcat(eprom, s);
- strcat(eprom, ff);
- }
-
- /* bootfile -> F */
- s = getenv("bootfile");
- if (s != NULL) {
- strcat(eprom, "F=");
- strcat(eprom, s);
- strcat(eprom, ff);
- }
-
- /* bootcmd -> M */
- s = getenv("bootcmd");
- if (s != NULL) {
- strcat(eprom, "M=");
- strcat(eprom, s);
- strcat(eprom, ff);
- }
-
- len = strlen(eprom); /* find env length without crc */
- change_null((uchar *)eprom); /* change 0xff to 0x00 */
-
- /* update EEPROM env values if there is enough space */
- if (update_crc(len, (uchar *)eprom) == 0)
- send(CONFIG_ENV_OFFSET, (uchar *)eprom, len + 6);
-}
-
-/************************************************************************
- * U-boot call for EEPROM read associated activities.
- */
-int
-i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len)
-{
-
- if (envStep == 0) {
- /* first read call is for crc */
- read_crc(buffer, len);
- ++envStep;
- return 0;
- } else if (envStep == 1) {
- /* then read out EEPROM content for runtime u-boot CRC calculation */
- receive(addr, buffer, len);
-
- if (addr + len - CONFIG_ENV_OFFSET == CONFIG_ENV_SIZE)
- /* end of runtime crc read */
- ++envStep;
- return 0;
- }
-
- if (len < 2) {
- /* when call getenv_r */
- receive(addr, buffer, len);
- } else if (addr + len < CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) {
- /* calling env_relocate(), but don't read out
- crc value from EEPROM */
- receive(addr, buffer + 4, len);
- } else {
- receive(addr, buffer + 4, len - 4);
- }
-
- return 0;
-
-}
-
-/************************************************************************
- * U-boot call for EEPROM write acativities.
- */
-int
-i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len)
-{
- /* save env on last page write called by u-boot */
- if (addr + len >= CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
- save_env();
-
- return 0;
-}
-
-/************************************************************************
- * Dummy function.
- */
-int
-i2c_probe(uchar chip)
-{
- return 1;
-}
-
-#endif
+++ /dev/null
-/* $Id: xiic_l.c,v 1.2 2002/12/05 19:32:40 meinelte Exp $ */
-/******************************************************************************
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
-* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
-* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
-* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
-* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE.
-*
-* (c) Copyright 2002 Xilinx Inc.
-* All rights reserved.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xiic_l.c
-*
-* This file contains low-level driver functions that can be used to access the
-* device. The user should refer to the hardware device specification for more
-* details of the device operation.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- ------- -----------------------------------------------
-* 1.01b jhl 5/13/02 First release
-* 1.01b jhl 10/14/02 Corrected bug in the receive function, the setup of the
-* interrupt status mask was not being done in the loop such
-* that a read would sometimes fail on the last byte because
-* the transmit error which should have been ignored was
-* being used. This would leave an extra byte in the FIFO
-* and the bus throttled such that the next operation would
-* also fail. Also updated the receive function to not
-* disable the device after the last byte until after the
-* bus transitions to not busy which is more consistent
-* with the expected behavior.
-* 1.01c ecm 12/05/02 new rev
-* </pre>
-*
-****************************************************************************/
-
-/***************************** Include Files *******************************/
-
-#include "xbasic_types.h"
-#include "xio.h"
-#include "xipif_v1_23_b.h"
-#include "xiic_l.h"
-
-/************************** Constant Definitions ***************************/
-
-/**************************** Type Definitions *****************************/
-
-
-/***************** Macros (Inline Functions) Definitions *******************/
-
-
-/******************************************************************************
-*
-* This macro clears the specified interrupt in the IPIF interrupt status
-* register. It is non-destructive in that the register is read and only the
-* interrupt specified is cleared. Clearing an interrupt acknowledges it.
-*
-* @param BaseAddress contains the IPIF registers base address.
-*
-* @param InterruptMask contains the interrupts to be disabled
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* Signature: void XIic_mClearIisr(u32 BaseAddress,
-* u32 InterruptMask);
-*
-******************************************************************************/
-#define XIic_mClearIisr(BaseAddress, InterruptMask) \
- XIIF_V123B_WRITE_IISR((BaseAddress), \
- XIIF_V123B_READ_IISR(BaseAddress) & (InterruptMask))
-
-/******************************************************************************
-*
-* This macro sends the address for a 7 bit address during both read and write
-* operations. It takes care of the details to format the address correctly.
-* This macro is designed to be called internally to the drivers.
-*
-* @param SlaveAddress contains the address of the slave to send to.
-*
-* @param Operation indicates XIIC_READ_OPERATION or XIIC_WRITE_OPERATION
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* Signature: void XIic_mSend7BitAddr(u16 SlaveAddress, u8 Operation);
-*
-******************************************************************************/
-#define XIic_mSend7BitAddress(BaseAddress, SlaveAddress, Operation) \
-{ \
- u8 LocalAddr = (u8)(SlaveAddress << 1); \
- LocalAddr = (LocalAddr & 0xFE) | (Operation); \
- XIo_Out8(BaseAddress + XIIC_DTR_REG_OFFSET, LocalAddr); \
-}
-
-/************************** Function Prototypes ****************************/
-
-static unsigned RecvData (u32 BaseAddress, u8 * BufferPtr,
- unsigned ByteCount);
-static unsigned SendData (u32 BaseAddress, u8 * BufferPtr,
- unsigned ByteCount);
-
-/************************** Variable Definitions **************************/
-
-
-/****************************************************************************/
-/**
-* Receive data as a master on the IIC bus. This function receives the data
-* using polled I/O and blocks until the data has been received. It only
-* supports 7 bit addressing and non-repeated start modes of operation. The
-* user is responsible for ensuring the bus is not busy if multiple masters
-* are present on the bus.
-*
-* @param BaseAddress contains the base address of the IIC device.
-* @param Address contains the 7 bit IIC address of the device to send the
-* specified data to.
-* @param BufferPtr points to the data to be sent.
-* @param ByteCount is the number of bytes to be sent.
-*
-* @return
-*
-* The number of bytes received.
-*
-* @note
-*
-* None
-*
-******************************************************************************/
-unsigned XIic_Recv (u32 BaseAddress, u8 Address,
- u8 * BufferPtr, unsigned ByteCount)
-{
- u8 CntlReg;
- unsigned RemainingByteCount;
-
- /* Tx error is enabled incase the address (7 or 10) has no device to answer
- * with Ack. When only one byte of data, must set NO ACK before address goes
- * out therefore Tx error must not be enabled as it will go off immediately
- * and the Rx full interrupt will be checked. If full, then the one byte
- * was received and the Tx error will be disabled without sending an error
- * callback msg.
- */
- XIic_mClearIisr (BaseAddress,
- XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK |
- XIIC_INTR_ARB_LOST_MASK);
-
- /* Set receive FIFO occupancy depth for 1 byte (zero based)
- */
- XIo_Out8 (BaseAddress + XIIC_RFD_REG_OFFSET, 0);
-
- /* 7 bit slave address, send the address for a read operation
- * and set the state to indicate the address has been sent
- */
- XIic_mSend7BitAddress (BaseAddress, Address, XIIC_READ_OPERATION);
-
- /* MSMS gets set after putting data in FIFO. Start the master receive
- * operation by setting CR Bits MSMS to Master, if the buffer is only one
- * byte, then it should not be acknowledged to indicate the end of data
- */
- CntlReg = XIIC_CR_MSMS_MASK | XIIC_CR_ENABLE_DEVICE_MASK;
- if (ByteCount == 1) {
- CntlReg |= XIIC_CR_NO_ACK_MASK;
- }
-
- /* Write out the control register to start receiving data and call the
- * function to receive each byte into the buffer
- */
- XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET, CntlReg);
-
- /* Clear the latched interrupt status for the bus not busy bit which must
- * be done while the bus is busy
- */
- XIic_mClearIisr (BaseAddress, XIIC_INTR_BNB_MASK);
-
- /* Try to receive the data from the IIC bus */
-
- RemainingByteCount = RecvData (BaseAddress, BufferPtr, ByteCount);
- /*
- * The receive is complete, disable the IIC device and return the number of
- * bytes that was received
- */
- XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET, 0);
-
- /* Return the number of bytes that was received */
-
- return ByteCount - RemainingByteCount;
-}
-
-/******************************************************************************
-*
-* Receive the specified data from the device that has been previously addressed
-* on the IIC bus. This function assumes that the 7 bit address has been sent
-* and it should wait for the transmit of the address to complete.
-*
-* @param BaseAddress contains the base address of the IIC device.
-* @param BufferPtr points to the buffer to hold the data that is received.
-* @param ByteCount is the number of bytes to be received.
-*
-* @return
-*
-* The number of bytes remaining to be received.
-*
-* @note
-*
-* This function does not take advantage of the receive FIFO because it is
-* designed for minimal code space and complexity. It contains loops that
-* that could cause the function not to return if the hardware is not working.
-*
-* This function assumes that the calling function will disable the IIC device
-* after this function returns.
-*
-******************************************************************************/
-static unsigned RecvData (u32 BaseAddress, u8 * BufferPtr, unsigned ByteCount)
-{
- u8 CntlReg;
- u32 IntrStatusMask;
- u32 IntrStatus;
-
- /* Attempt to receive the specified number of bytes on the IIC bus */
-
- while (ByteCount > 0) {
- /* Setup the mask to use for checking errors because when receiving one
- * byte OR the last byte of a multibyte message an error naturally
- * occurs when the no ack is done to tell the slave the last byte
- */
- if (ByteCount == 1) {
- IntrStatusMask =
- XIIC_INTR_ARB_LOST_MASK | XIIC_INTR_BNB_MASK;
- } else {
- IntrStatusMask =
- XIIC_INTR_ARB_LOST_MASK |
- XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_BNB_MASK;
- }
-
- /* Wait for the previous transmit and the 1st receive to complete
- * by checking the interrupt status register of the IPIF
- */
- while (1) {
- IntrStatus = XIIF_V123B_READ_IISR (BaseAddress);
- if (IntrStatus & XIIC_INTR_RX_FULL_MASK) {
- break;
- }
- /* Check the transmit error after the receive full because when
- * sending only one byte transmit error will occur because of the
- * no ack to indicate the end of the data
- */
- if (IntrStatus & IntrStatusMask) {
- return ByteCount;
- }
- }
-
- CntlReg = XIo_In8 (BaseAddress + XIIC_CR_REG_OFFSET);
-
- /* Special conditions exist for the last two bytes so check for them
- * Note that the control register must be setup for these conditions
- * before the data byte which was already received is read from the
- * receive FIFO (while the bus is throttled
- */
- if (ByteCount == 1) {
- /* For the last data byte, it has already been read and no ack
- * has been done, so clear MSMS while leaving the device enabled
- * so it can get off the IIC bus appropriately with a stop.
- */
- XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET,
- XIIC_CR_ENABLE_DEVICE_MASK);
- }
-
- /* Before the last byte is received, set NOACK to tell the slave IIC
- * device that it is the end, this must be done before reading the byte
- * from the FIFO
- */
- if (ByteCount == 2) {
- /* Write control reg with NO ACK allowing last byte to
- * have the No ack set to indicate to slave last byte read.
- */
- XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET,
- CntlReg | XIIC_CR_NO_ACK_MASK);
- }
-
- /* Read in data from the FIFO and unthrottle the bus such that the
- * next byte is read from the IIC bus
- */
- *BufferPtr++ = XIo_In8 (BaseAddress + XIIC_DRR_REG_OFFSET);
-
- /* Clear the latched interrupt status so that it will be updated with
- * the new state when it changes, this must be done after the receive
- * register is read
- */
- XIic_mClearIisr (BaseAddress, XIIC_INTR_RX_FULL_MASK |
- XIIC_INTR_TX_ERROR_MASK |
- XIIC_INTR_ARB_LOST_MASK);
- ByteCount--;
- }
-
- /* Wait for the bus to transition to not busy before returning, the IIC
- * device cannot be disabled until this occurs. It should transition as
- * the MSMS bit of the control register was cleared before the last byte
- * was read from the FIFO.
- */
- while (1) {
- if (XIIF_V123B_READ_IISR (BaseAddress) & XIIC_INTR_BNB_MASK) {
- break;
- }
- }
-
- return ByteCount;
-}
-
-/****************************************************************************/
-/**
-* Send data as a master on the IIC bus. This function sends the data
-* using polled I/O and blocks until the data has been sent. It only supports
-* 7 bit addressing and non-repeated start modes of operation. The user is
-* responsible for ensuring the bus is not busy if multiple masters are present
-* on the bus.
-*
-* @param BaseAddress contains the base address of the IIC device.
-* @param Address contains the 7 bit IIC address of the device to send the
-* specified data to.
-* @param BufferPtr points to the data to be sent.
-* @param ByteCount is the number of bytes to be sent.
-*
-* @return
-*
-* The number of bytes sent.
-*
-* @note
-*
-* None
-*
-******************************************************************************/
-unsigned XIic_Send (u32 BaseAddress, u8 Address,
- u8 * BufferPtr, unsigned ByteCount)
-{
- unsigned RemainingByteCount;
-
- /* Put the address into the FIFO to be sent and indicate that the operation
- * to be performed on the bus is a write operation
- */
- XIic_mSend7BitAddress (BaseAddress, Address, XIIC_WRITE_OPERATION);
-
- /* Clear the latched interrupt status so that it will be updated with the
- * new state when it changes, this must be done after the address is put
- * in the FIFO
- */
- XIic_mClearIisr (BaseAddress, XIIC_INTR_TX_EMPTY_MASK |
- XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_ARB_LOST_MASK);
-
- /* MSMS must be set after putting data into transmit FIFO, indicate the
- * direction is transmit, this device is master and enable the IIC device
- */
- XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET,
- XIIC_CR_MSMS_MASK | XIIC_CR_DIR_IS_TX_MASK |
- XIIC_CR_ENABLE_DEVICE_MASK);
-
- /* Clear the latched interrupt
- * status for the bus not busy bit which must be done while the bus is busy
- */
- XIic_mClearIisr (BaseAddress, XIIC_INTR_BNB_MASK);
-
- /* Send the specified data to the device on the IIC bus specified by the
- * the address
- */
- RemainingByteCount = SendData (BaseAddress, BufferPtr, ByteCount);
-
- /*
- * The send is complete, disable the IIC device and return the number of
- * bytes that was sent
- */
- XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET, 0);
-
- return ByteCount - RemainingByteCount;
-}
-
-/******************************************************************************
-*
-* Send the specified buffer to the device that has been previously addressed
-* on the IIC bus. This function assumes that the 7 bit address has been sent
-* and it should wait for the transmit of the address to complete.
-*
-* @param BaseAddress contains the base address of the IIC device.
-* @param BufferPtr points to the data to be sent.
-* @param ByteCount is the number of bytes to be sent.
-*
-* @return
-*
-* The number of bytes remaining to be sent.
-*
-* @note
-*
-* This function does not take advantage of the transmit FIFO because it is
-* designed for minimal code space and complexity. It contains loops that
-* that could cause the function not to return if the hardware is not working.
-*
-******************************************************************************/
-static unsigned SendData (u32 BaseAddress, u8 * BufferPtr, unsigned ByteCount)
-{
- u32 IntrStatus;
-
- /* Send the specified number of bytes in the specified buffer by polling
- * the device registers and blocking until complete
- */
- while (ByteCount > 0) {
- /* Wait for the transmit to be empty before sending any more data
- * by polling the interrupt status register
- */
- while (1) {
- IntrStatus = XIIF_V123B_READ_IISR (BaseAddress);
-
- if (IntrStatus & (XIIC_INTR_TX_ERROR_MASK |
- XIIC_INTR_ARB_LOST_MASK |
- XIIC_INTR_BNB_MASK)) {
- return ByteCount;
- }
-
- if (IntrStatus & XIIC_INTR_TX_EMPTY_MASK) {
- break;
- }
- }
- /* If there is more than one byte to send then put the next byte to send
- * into the transmit FIFO
- */
- if (ByteCount > 1) {
- XIo_Out8 (BaseAddress + XIIC_DTR_REG_OFFSET,
- *BufferPtr++);
- } else {
- /* Set the stop condition before sending the last byte of data so that
- * the stop condition will be generated immediately following the data
- * This is done by clearing the MSMS bit in the control register.
- */
- XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET,
- XIIC_CR_ENABLE_DEVICE_MASK |
- XIIC_CR_DIR_IS_TX_MASK);
-
- /* Put the last byte to send in the transmit FIFO */
-
- XIo_Out8 (BaseAddress + XIIC_DTR_REG_OFFSET,
- *BufferPtr++);
- }
-
- /* Clear the latched interrupt status register and this must be done after
- * the transmit FIFO has been written to or it won't clear
- */
- XIic_mClearIisr (BaseAddress, XIIC_INTR_TX_EMPTY_MASK);
-
- /* Update the byte count to reflect the byte sent and clear the latched
- * interrupt status so it will be updated for the new state
- */
- ByteCount--;
- }
-
- /* Wait for the bus to transition to not busy before returning, the IIC
- * device cannot be disabled until this occurs.
- * Note that this is different from a receive operation because the stop
- * condition causes the bus to go not busy.
- */
- while (1) {
- if (XIIF_V123B_READ_IISR (BaseAddress) & XIIC_INTR_BNB_MASK) {
- break;
- }
- }
-
- return ByteCount;
-}
+++ /dev/null
-/* $Id: xiic_l.h,v 1.2 2002/12/05 19:32:40 meinelte Exp $ */
-/*****************************************************************************
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
-* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
-* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
-* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
-* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE.
-*
-* (c) Copyright 2002 Xilinx Inc.
-* All rights reserved.
-*
-*****************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xiic_l.h
-*
-* This header file contains identifiers and low-level driver functions (or
-* macros) that can be used to access the device. High-level driver functions
-* are defined in xiic.h.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b jhl 05/07/02 First release
-* 1.01c ecm 12/05/02 new rev
-* </pre>
-*
-*****************************************************************************/
-
-#ifndef XIIC_L_H /* prevent circular inclusions */
-#define XIIC_L_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include "xbasic_types.h"
-
-/************************** Constant Definitions ****************************/
-
-#define XIIC_MSB_OFFSET 3
-
-#define XIIC_REG_OFFSET 0x100 + XIIC_MSB_OFFSET
-
-/*
- * Register offsets in bytes from RegisterBase. Three is added to the
- * base offset to access LSB (IBM style) of the word
- */
-#define XIIC_CR_REG_OFFSET 0x00+XIIC_REG_OFFSET /* Control Register */
-#define XIIC_SR_REG_OFFSET 0x04+XIIC_REG_OFFSET /* Status Register */
-#define XIIC_DTR_REG_OFFSET 0x08+XIIC_REG_OFFSET /* Data Tx Register */
-#define XIIC_DRR_REG_OFFSET 0x0C+XIIC_REG_OFFSET /* Data Rx Register */
-#define XIIC_ADR_REG_OFFSET 0x10+XIIC_REG_OFFSET /* Address Register */
-#define XIIC_TFO_REG_OFFSET 0x14+XIIC_REG_OFFSET /* Tx FIFO Occupancy */
-#define XIIC_RFO_REG_OFFSET 0x18+XIIC_REG_OFFSET /* Rx FIFO Occupancy */
-#define XIIC_TBA_REG_OFFSET 0x1C+XIIC_REG_OFFSET /* 10 Bit Address reg */
-#define XIIC_RFD_REG_OFFSET 0x20+XIIC_REG_OFFSET /* Rx FIFO Depth reg */
-
-/* Control Register masks */
-
-#define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */
-#define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */
-#define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */
-#define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */
-#define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */
-#define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */
-#define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */
-
-/* Status Register masks */
-
-#define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */
-#define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */
-#define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */
-#define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */
-#define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */
-#define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */
-#define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */
-
-/* IPIF Interrupt Status Register masks Interrupt occurs when... */
-
-#define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */
-#define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete*/
-#define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */
-#define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level*/
-#define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */
-#define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */
-#define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */
-#define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */
-
-/* IPIF Device Interrupt Register masks */
-
-#define XIIC_IPIF_IIC_MASK 0x00000004UL /* 1=inter enabled */
-#define XIIC_IPIF_ERROR_MASK 0x00000001UL /* 1=inter enabled */
-#define XIIC_IPIF_INTER_ENABLE_MASK (XIIC_IPIF_IIC_MASK | \
- XIIC_IPIF_ERROR_MASK)
-
-#define XIIC_TX_ADDR_SENT 0x00
-#define XIIC_TX_ADDR_MSTR_RECV_MASK 0x02
-
-/* The following constants specify the depth of the FIFOs */
-
-#define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */
-#define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */
-
-/* The following constants specify groups of interrupts that are typically
- * enabled or disables at the same time
- */
-#define XIIC_TX_INTERRUPTS \
- (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | \
- XIIC_INTR_TX_HALF_MASK)
-
-#define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)
-
-/* The following constants are used with the following macros to specify the
- * operation, a read or write operation.
- */
-#define XIIC_READ_OPERATION 1
-#define XIIC_WRITE_OPERATION 0
-
-/* The following constants are used with the transmit FIFO fill function to
- * specify the role which the IIC device is acting as, a master or a slave.
- */
-#define XIIC_MASTER_ROLE 1
-#define XIIC_SLAVE_ROLE 0
-
-/**************************** Type Definitions ******************************/
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-/************************** Function Prototypes *****************************/
-
-unsigned XIic_Recv(u32 BaseAddress, u8 Address,
- u8 *BufferPtr, unsigned ByteCount);
-
-unsigned XIic_Send(u32 BaseAddress, u8 Address,
- u8 *BufferPtr, unsigned ByteCount);
-
-#endif /* end of protection macro */
+++ /dev/null
-/* $Id$ */
-
-#include <common.h>
-
-#include <linux/ctype.h>
-#include <bedbug/bedbug.h>
-#include <bedbug/ppc.h>
-#include <bedbug/regs.h>
-#include <bedbug/tables.h>
-
-#define Elf32_Word unsigned long
-
-/* USE_SOURCE_CODE enables some symbolic debugging functions of this
- code. This is only useful if the program will have access to the
- source code for the binary being examined.
-*/
-
-/* #define USE_SOURCE_CODE 1 */
-
-#ifdef USE_SOURCE_CODE
-extern int line_info_from_addr __P ((Elf32_Word, char *, char *, int *));
-extern struct symreflist *symByAddr;
-extern char *symbol_name_from_addr __P ((Elf32_Word, int, int *));
-#endif /* USE_SOURCE_CODE */
-
-int print_operands __P ((struct ppc_ctx *));
-int get_operand_value __P ((struct opcode *, unsigned long,
- enum OP_FIELD, unsigned long *));
-struct opcode *find_opcode __P ((unsigned long));
-struct opcode *find_opcode_by_name __P ((char *));
-char *spr_name __P ((int));
-int spr_value __P ((char *));
-char *tbr_name __P ((int));
-int tbr_value __P ((char *));
-int parse_operand __P ((unsigned long, struct opcode *,
- struct operand *, char *, int *));
-int get_word __P ((char **, char *));
-long read_number __P ((char *));
-int downstring __P ((char *));
-\f
-
-/*======================================================================
- * Entry point for the PPC disassembler.
- *
- * Arguments:
- * memaddr The address to start disassembling from.
- *
- * virtual If this value is non-zero, then this will be
- * used as the base address for the output and
- * symbol lookups. If this value is zero then
- * memaddr is used as the absolute address.
- *
- * num_instr The number of instructions to disassemble. Since
- * each instruction is 32 bits long, this can be
- * computed if you know the total size of the region.
- *
- * pfunc The address of a function that is called to print
- * each line of output. The function should take a
- * single character pointer as its parameters a la puts.
- *
- * flags Sets options for the output. This is a
- * bitwise-inclusive-OR of the following
- * values. Note that only one of the radix
- * options may be set.
- *
- * F_RADOCTAL - output radix is unsigned base 8.
- * F_RADUDECIMAL - output radix is unsigned base 10.
- * F_RADSDECIMAL - output radix is signed base 10.
- * F_RADHEX - output radix is unsigned base 16.
- * F_SIMPLE - use simplified mnemonics.
- * F_SYMBOL - lookup symbols for addresses.
- * F_INSTR - output raw instruction.
- * F_LINENO - show line # info if available.
- *
- * Returns TRUE if the area was successfully disassembled or FALSE if
- * a problem was encountered with accessing the memory.
- */
-
-int disppc (unsigned char *memaddr, unsigned char *virtual, int num_instr,
- int (*pfunc) (const char *), unsigned long flags)
-{
- int i;
- struct ppc_ctx ctx;
-
-#ifdef USE_SOURCE_CODE
- int line_no = 0;
- int last_line_no = 0;
- char funcname[128] = { 0 };
- char filename[256] = { 0 };
- char last_funcname[128] = { 0 };
- int symoffset;
- char *symname;
- char *cursym = (char *) 0;
-#endif /* USE_SOURCE_CODE */
- /*------------------------------------------------------------*/
-
- ctx.flags = flags;
- ctx.virtual = virtual;
-
- /* Figure out the output radix before we go any further */
-
- if (ctx.flags & F_RADOCTAL) {
- /* Unsigned octal output */
- strcpy (ctx.radix_fmt, "O%o");
- } else if (ctx.flags & F_RADUDECIMAL) {
- /* Unsigned decimal output */
- strcpy (ctx.radix_fmt, "%u");
- } else if (ctx.flags & F_RADSDECIMAL) {
- /* Signed decimal output */
- strcpy (ctx.radix_fmt, "%d");
- } else {
- /* Unsigned hex output */
- strcpy (ctx.radix_fmt, "0x%x");
- }
-
- if (ctx.virtual == 0) {
- ctx.virtual = memaddr;
- }
-#ifdef USE_SOURCE_CODE
- if (ctx.flags & F_SYMBOL) {
- if (symByAddr == 0) /* no symbols loaded */
- ctx.flags &= ~F_SYMBOL;
- else {
- cursym = (char *) 0;
- symoffset = 0;
- }
- }
-#endif /* USE_SOURCE_CODE */
-
- /* format each line as "XXXXXXXX: <symbol> IIIIIIII disassembly" where,
- XXXXXXXX is the memory address in hex,
- <symbol> is the symbolic location if F_SYMBOL is set.
- IIIIIIII is the raw machine code in hex if F_INSTR is set,
- and disassembly is the disassembled machine code with numbers
- formatted according to the 'radix' parameter */
-
- for (i = 0; i < num_instr; ++i, memaddr += 4, ctx.virtual += 4) {
-#ifdef USE_SOURCE_CODE
- if (ctx.flags & F_LINENO) {
- if ((line_info_from_addr ((Elf32_Word) ctx.virtual, filename,
- funcname, &line_no) == TRUE) &&
- ((line_no != last_line_no) ||
- (strcmp (last_funcname, funcname) != 0))) {
- print_source_line (filename, funcname, line_no, pfunc);
- }
- last_line_no = line_no;
- strcpy (last_funcname, funcname);
- }
-#endif /* USE_SOURCE_CODE */
-
- sprintf (ctx.data, "%08lx: ", (unsigned long) ctx.virtual);
- ctx.datalen = 10;
-
-#ifdef USE_SOURCE_CODE
- if (ctx.flags & F_SYMBOL) {
- if ((symname =
- symbol_name_from_addr ((Elf32_Word) ctx.virtual,
- TRUE, 0)) != 0) {
- cursym = symname;
- symoffset = 0;
- } else {
- if ((cursym == 0) &&
- ((symname =
- symbol_name_from_addr ((Elf32_Word) ctx.virtual,
- FALSE, &symoffset)) != 0)) {
- cursym = symname;
- } else {
- symoffset += 4;
- }
- }
-
- if (cursym != 0) {
- sprintf (&ctx.data[ctx.datalen], "<%s+", cursym);
- ctx.datalen = strlen (ctx.data);
- sprintf (&ctx.data[ctx.datalen], ctx.radix_fmt, symoffset);
- strcat (ctx.data, ">");
- ctx.datalen = strlen (ctx.data);
- }
- }
-#endif /* USE_SOURCE_CODE */
-
- ctx.instr = INSTRUCTION (memaddr);
-
- if (ctx.flags & F_INSTR) {
- /* Find the opcode structure for this opcode. If one is not found
- then it must be an illegal instruction */
- sprintf (&ctx.data[ctx.datalen],
- " %02lx %02lx %02lx %02lx ",
- ((ctx.instr >> 24) & 0xff),
- ((ctx.instr >> 16) & 0xff), ((ctx.instr >> 8) & 0xff),
- (ctx.instr & 0xff));
- ctx.datalen += 18;
- } else {
- strcat (ctx.data, " ");
- ctx.datalen += 3;
- }
-
- if ((ctx.op = find_opcode (ctx.instr)) == 0) {
- /* Illegal Opcode */
- sprintf (&ctx.data[ctx.datalen], " .long 0x%08lx",
- ctx.instr);
- ctx.datalen += 24;
- (*pfunc) (ctx.data);
- continue;
- }
-
- if (((ctx.flags & F_SIMPLE) == 0) ||
- (ctx.op->hfunc == 0) || ((*ctx.op->hfunc) (&ctx) == FALSE)) {
- sprintf (&ctx.data[ctx.datalen], "%-7s ", ctx.op->name);
- ctx.datalen += 8;
- print_operands (&ctx);
- }
-
- (*pfunc) (ctx.data);
- }
-
- return TRUE;
-} /* disppc */
-\f
-
-
-/*======================================================================
- * Called by the disassembler to print the operands for an instruction.
- *
- * Arguments:
- * ctx A pointer to the disassembler context record.
- *
- * always returns 0.
- */
-
-int print_operands (struct ppc_ctx *ctx)
-{
- int open_parens = 0;
- int field;
- unsigned long operand;
- struct operand *opr;
-
-#ifdef USE_SOURCE_CODE
- char *symname;
- int offset;
-#endif /* USE_SOURCE_CODE */
- /*------------------------------------------------------------*/
-
- /* Walk through the operands and list each in order */
- for (field = 0; ctx->op->fields[field] != 0; ++field) {
- if (ctx->op->fields[field] > n_operands) {
- continue; /* bad operand ?! */
- }
-
- opr = &operands[ctx->op->fields[field] - 1];
-
- if (opr->hint & OH_SILENT) {
- continue;
- }
-
- if ((field > 0) && !open_parens) {
- strcat (ctx->data, ",");
- ctx->datalen++;
- }
-
- operand = (ctx->instr >> opr->shift) & ((1 << opr->bits) - 1);
-
- if (opr->hint & OH_ADDR) {
- if ((operand & (1 << (opr->bits - 1))) != 0) {
- operand = operand - (1 << opr->bits);
- }
-
- if (ctx->op->hint & H_RELATIVE)
- operand = (operand << 2) + (unsigned long) ctx->virtual;
- else
- operand = (operand << 2);
-
-
- sprintf (&ctx->data[ctx->datalen], "0x%lx", operand);
- ctx->datalen = strlen (ctx->data);
-
-#ifdef USE_SOURCE_CODE
- if ((ctx->flags & F_SYMBOL) &&
- ((symname =
- symbol_name_from_addr (operand, 0, &offset)) != 0)) {
- sprintf (&ctx->data[ctx->datalen], " <%s", symname);
- if (offset != 0) {
- strcat (ctx->data, "+");
- ctx->datalen = strlen (ctx->data);
- sprintf (&ctx->data[ctx->datalen], ctx->radix_fmt,
- offset);
- }
- strcat (ctx->data, ">");
- }
-#endif /* USE_SOURCE_CODE */
- }
-
- else if (opr->hint & OH_REG) {
- if ((operand == 0) &&
- (opr->field == O_rA) && (ctx->op->hint & H_RA0_IS_0)) {
- strcat (ctx->data, "0");
- } else {
- sprintf (&ctx->data[ctx->datalen], "r%d", (short) operand);
- }
-
- if (open_parens) {
- strcat (ctx->data, ")");
- open_parens--;
- }
- }
-
- else if (opr->hint & OH_SPR) {
- strcat (ctx->data, spr_name (operand));
- }
-
- else if (opr->hint & OH_TBR) {
- strcat (ctx->data, tbr_name (operand));
- }
-
- else if (opr->hint & OH_LITERAL) {
- switch (opr->field) {
- case O_cr2:
- strcat (ctx->data, "cr2");
- ctx->datalen += 3;
- break;
-
- default:
- break;
- }
- }
-
- else {
- sprintf (&ctx->data[ctx->datalen], ctx->radix_fmt,
- (unsigned short) operand);
-
- if (open_parens) {
- strcat (ctx->data, ")");
- open_parens--;
- }
-
- else if (opr->hint & OH_OFFSET) {
- strcat (ctx->data, "(");
- open_parens++;
- }
- }
-
- ctx->datalen = strlen (ctx->data);
- }
-
- return 0;
-} /* print_operands */
-\f
-
-
-/*======================================================================
- * Called to get the value of an arbitrary operand with in an instruction.
- *
- * Arguments:
- * op The pointer to the opcode structure to which
- * the operands belong.
- *
- * instr The instruction (32 bits) containing the opcode
- * and the operands to print. By the time that
- * this routine is called the operand has already
- * been added to the output.
- *
- * field The field (operand) to get the value of.
- *
- * value The address of an unsigned long to be filled in
- * with the value of the operand if it is found. This
- * will only be filled in if the function returns
- * TRUE. This may be passed as 0 if the value is
- * not required.
- *
- * Returns TRUE if the operand was found or FALSE if it was not.
- */
-
-int get_operand_value (struct opcode *op, unsigned long instr,
- enum OP_FIELD field, unsigned long *value)
-{
- int i;
- struct operand *opr;
-
- /*------------------------------------------------------------*/
-
- if (field > n_operands) {
- return FALSE; /* bad operand ?! */
- }
-
- /* Walk through the operands and list each in order */
- for (i = 0; op->fields[i] != 0; ++i) {
- if (op->fields[i] != field) {
- continue;
- }
-
- opr = &operands[op->fields[i] - 1];
-
- if (value) {
- *value = (instr >> opr->shift) & ((1 << opr->bits) - 1);
- }
- return TRUE;
- }
-
- return FALSE;
-} /* operand_value */
-\f
-
-
-/*======================================================================
- * Called by the disassembler to match an opcode value to an opcode structure.
- *
- * Arguments:
- * instr The instruction (32 bits) to match. This value
- * may contain operand values as well as the opcode
- * since they will be masked out anyway for this
- * search.
- *
- * Returns the address of an opcode struct (from the opcode table) if the
- * operand successfully matched an entry, or 0 if no match was found.
- */
-
-struct opcode *find_opcode (unsigned long instr)
-{
- struct opcode *ptr;
- int top = 0;
- int bottom = n_opcodes - 1;
- int idx;
-
- /*------------------------------------------------------------*/
-
- while (top <= bottom) {
- idx = (top + bottom) >> 1;
- ptr = &opcodes[idx];
-
- if ((instr & ptr->mask) < ptr->opcode) {
- bottom = idx - 1;
- } else if ((instr & ptr->mask) > ptr->opcode) {
- top = idx + 1;
- } else {
- return ptr;
- }
- }
-
- return (struct opcode *) 0;
-} /* find_opcode */
-\f
-
-
-/*======================================================================
- * Called by the assembler to match an opcode name to an opcode structure.
- *
- * Arguments:
- * name The text name of the opcode, e.g. "b", "mtspr", etc.
- *
- * The opcodes are sorted numerically by their instruction binary code
- * so a search for the name cannot use the binary search used by the
- * other find routine.
- *
- * Returns the address of an opcode struct (from the opcode table) if the
- * name successfully matched an entry, or 0 if no match was found.
- */
-
-struct opcode *find_opcode_by_name (char *name)
-{
- int idx;
-
- /*------------------------------------------------------------*/
-
- downstring (name);
-
- for (idx = 0; idx < n_opcodes; ++idx) {
- if (!strcmp (name, opcodes[idx].name))
- return &opcodes[idx];
- }
-
- return (struct opcode *) 0;
-} /* find_opcode_by_name */
-\f
-
-
-/*======================================================================
- * Convert the 'spr' operand from its numeric value to its symbolic name.
- *
- * Arguments:
- * value The value of the 'spr' operand. This value should
- * be unmodified from its encoding in the instruction.
- * the split-field computations will be performed
- * here before the switch.
- *
- * Returns the address of a character array containing the name of the
- * special purpose register defined by the 'value' parameter, or the
- * address of a character array containing "???" if no match was found.
- */
-
-char *spr_name (int value)
-{
- unsigned short spr;
- static char other[10];
- int i;
-
- /*------------------------------------------------------------*/
-
- /* spr is a 10 bit field whose interpretation has the high and low
- five-bit fields reversed from their encoding in the operand */
-
- spr = ((value >> 5) & 0x1f) | ((value & 0x1f) << 5);
-
- for (i = 0; i < n_sprs; ++i) {
- if (spr == spr_map[i].spr_val)
- return spr_map[i].spr_name;
- }
-
- sprintf (other, "%d", spr);
- return other;
-} /* spr_name */
-\f
-
-
-/*======================================================================
- * Convert the 'spr' operand from its symbolic name to its numeric value
- *
- * Arguments:
- * name The symbolic name of the 'spr' operand. The
- * split-field encoding will be done by this routine.
- * NOTE: name can be a number.
- *
- * Returns the numeric value for the spr appropriate for encoding a machine
- * instruction. Returns 0 if unable to find the SPR.
- */
-
-int spr_value (char *name)
-{
- struct spr_info *sprp;
- int spr;
- int i;
-
- /*------------------------------------------------------------*/
-
- if (!name || !*name)
- return 0;
-
- if (isdigit ((int) name[0])) {
- i = htonl (read_number (name));
- spr = ((i >> 5) & 0x1f) | ((i & 0x1f) << 5);
- return spr;
- }
-
- downstring (name);
-
- for (i = 0; i < n_sprs; ++i) {
- sprp = &spr_map[i];
-
- if (strcmp (name, sprp->spr_name) == 0) {
- /* spr is a 10 bit field whose interpretation has the high and low
- five-bit fields reversed from their encoding in the operand */
- i = htonl (sprp->spr_val);
- spr = ((i >> 5) & 0x1f) | ((i & 0x1f) << 5);
-
- return spr;
- }
- }
-
- return 0;
-} /* spr_value */
-\f
-
-
-/*======================================================================
- * Convert the 'tbr' operand from its numeric value to its symbolic name.
- *
- * Arguments:
- * value The value of the 'tbr' operand. This value should
- * be unmodified from its encoding in the instruction.
- * the split-field computations will be performed
- * here before the switch.
- *
- * Returns the address of a character array containing the name of the
- * time base register defined by the 'value' parameter, or the address
- * of a character array containing "???" if no match was found.
- */
-
-char *tbr_name (int value)
-{
- unsigned short tbr;
-
- /*------------------------------------------------------------*/
-
- /* tbr is a 10 bit field whose interpretation has the high and low
- five-bit fields reversed from their encoding in the operand */
-
- tbr = ((value >> 5) & 0x1f) | ((value & 0x1f) << 5);
-
- if (tbr == 268)
- return "TBL";
-
- else if (tbr == 269)
- return "TBU";
-
-
- return "???";
-} /* tbr_name */
-\f
-
-
-/*======================================================================
- * Convert the 'tbr' operand from its symbolic name to its numeric value.
- *
- * Arguments:
- * name The symbolic name of the 'tbr' operand. The
- * split-field encoding will be done by this routine.
- *
- * Returns the numeric value for the spr appropriate for encoding a machine
- * instruction. Returns 0 if unable to find the TBR.
- */
-
-int tbr_value (char *name)
-{
- int tbr;
- int val;
-
- /*------------------------------------------------------------*/
-
- if (!name || !*name)
- return 0;
-
- downstring (name);
-
- if (isdigit ((int) name[0])) {
- val = read_number (name);
-
- if (val != 268 && val != 269)
- return 0;
- } else if (strcmp (name, "tbl") == 0)
- val = 268;
- else if (strcmp (name, "tbu") == 0)
- val = 269;
- else
- return 0;
-
- /* tbr is a 10 bit field whose interpretation has the high and low
- five-bit fields reversed from their encoding in the operand */
-
- val = htonl (val);
- tbr = ((val >> 5) & 0x1f) | ((val & 0x1f) << 5);
- return tbr;
-} /* tbr_name */
-\f
-
-
-/*======================================================================
- * The next several functions (handle_xxx) are the routines that handle
- * disassembling the opcodes with simplified mnemonics.
- *
- * Arguments:
- * ctx A pointer to the disassembler context record.
- *
- * Returns TRUE if the simpler form was printed or FALSE if it was not.
- */
-
-int handle_bc (struct ppc_ctx *ctx)
-{
- unsigned long bo;
- unsigned long bi;
- static struct opcode blt = { B_OPCODE (16, 0, 0), B_MASK, {O_BD, 0},
- 0, "blt", H_RELATIVE
- };
- static struct opcode bne =
- { B_OPCODE (16, 0, 0), B_MASK, {O_cr2, O_BD, 0},
- 0, "bne", H_RELATIVE
- };
- static struct opcode bdnz = { B_OPCODE (16, 0, 0), B_MASK, {O_BD, 0},
- 0, "bdnz", H_RELATIVE
- };
-
- /*------------------------------------------------------------*/
-
- if (get_operand_value (ctx->op, ctx->instr, O_BO, &bo) == FALSE)
- return FALSE;
-
- if (get_operand_value (ctx->op, ctx->instr, O_BI, &bi) == FALSE)
- return FALSE;
-
- if ((bo == 12) && (bi == 0)) {
- ctx->op = &blt;
- sprintf (&ctx->data[ctx->datalen], "%-7s ", ctx->op->name);
- ctx->datalen += 8;
- print_operands (ctx);
- return TRUE;
- } else if ((bo == 4) && (bi == 10)) {
- ctx->op = =⃥
- sprintf (&ctx->data[ctx->datalen], "%-7s ", ctx->op->name);
- ctx->datalen += 8;
- print_operands (ctx);
- return TRUE;
- } else if ((bo == 16) && (bi == 0)) {
- ctx->op = &bdnz;
- sprintf (&ctx->data[ctx->datalen], "%-7s ", ctx->op->name);
- ctx->datalen += 8;
- print_operands (ctx);
- return TRUE;
- }
-
- return FALSE;
-} /* handle_blt */
-\f
-
-
-/*======================================================================
- * Outputs source line information for the disassembler. This should
- * be modified in the future to lookup the actual line of source code
- * from the file, but for now this will do.
- *
- * Arguments:
- * filename The address of a character array containing the
- * absolute path and file name of the source file.
- *
- * funcname The address of a character array containing the
- * name of the function (not C++ demangled (yet))
- * to which this code belongs.
- *
- * line_no An integer specifying the source line number that
- * generated this code.
- *
- * pfunc The address of a function to call to print the output.
- *
- *
- * Returns TRUE if it was able to output the line info, or false if it was
- * not.
- */
-
-int print_source_line (char *filename, char *funcname,
- int line_no, int (*pfunc) (const char *))
-{
- char out_buf[256];
-
- /*------------------------------------------------------------*/
-
- (*pfunc) (""); /* output a newline */
- sprintf (out_buf, "%s %s(): line %d", filename, funcname, line_no);
- (*pfunc) (out_buf);
-
- return TRUE;
-} /* print_source_line */
-\f
-
-
-/*======================================================================
- * Entry point for the PPC assembler.
- *
- * Arguments:
- * asm_buf An array of characters containing the assembly opcode
- * and operands to convert to a POWERPC machine
- * instruction.
- *
- * Returns the machine instruction or zero.
- */
-
-unsigned long asmppc (unsigned long memaddr, char *asm_buf, int *err)
-{
- struct opcode *opc;
- struct operand *oper[MAX_OPERANDS];
- unsigned long instr;
- unsigned long param;
- char *ptr = asm_buf;
- char scratch[20];
- int i;
- int w_operands = 0; /* wanted # of operands */
- int n_operands = 0; /* # of operands read */
- int asm_debug = 0;
-
- /*------------------------------------------------------------*/
-
- if (err)
- *err = 0;
-
- if (get_word (&ptr, scratch) == 0)
- return 0;
-
- /* Lookup the opcode structure based on the opcode name */
- if ((opc = find_opcode_by_name (scratch)) == (struct opcode *) 0) {
- if (err)
- *err = E_ASM_BAD_OPCODE;
- return 0;
- }
-
- if (asm_debug) {
- printf ("asmppc: Opcode = \"%s\"\n", opc->name);
- }
-
- for (i = 0; i < 8; ++i) {
- if (opc->fields[i] == 0)
- break;
- ++w_operands;
- }
-
- if (asm_debug) {
- printf ("asmppc: Expecting %d operands\n", w_operands);
- }
-
- instr = opc->opcode;
-
- /* read each operand */
- while (n_operands < w_operands) {
-
- oper[n_operands] = &operands[opc->fields[n_operands] - 1];
-
- if (oper[n_operands]->hint & OH_SILENT) {
- /* Skip silent operands, they are covered in opc->opcode */
-
- if (asm_debug) {
- printf ("asmppc: Operand %d \"%s\" SILENT\n", n_operands,
- oper[n_operands]->name);
- }
-
- ++n_operands;
- continue;
- }
-
- if (get_word (&ptr, scratch) == 0)
- break;
-
- if (asm_debug) {
- printf ("asmppc: Operand %d \"%s\" : \"%s\"\n", n_operands,
- oper[n_operands]->name, scratch);
- }
-
- if ((param = parse_operand (memaddr, opc, oper[n_operands],
- scratch, err)) == -1)
- return 0;
-
- instr |= param;
- ++n_operands;
- }
-
- if (n_operands < w_operands) {
- if (err)
- *err = E_ASM_NUM_OPERANDS;
- return 0;
- }
-
- if (asm_debug) {
- printf ("asmppc: Instruction = 0x%08lx\n", instr);
- }
-
- return instr;
-} /* asmppc */
-\f
-
-
-/*======================================================================
- * Called by the assembler to interpret a single operand
- *
- * Arguments:
- * ctx A pointer to the disassembler context record.
- *
- * Returns 0 if the operand is ok, or -1 if it is bad.
- */
-
-int parse_operand (unsigned long memaddr, struct opcode *opc,
- struct operand *oper, char *txt, int *err)
-{
- long data;
- long mask;
- int is_neg = 0;
-
- /*------------------------------------------------------------*/
-
- mask = (1 << oper->bits) - 1;
-
- if (oper->hint & OH_ADDR) {
- data = read_number (txt);
-
- if (opc->hint & H_RELATIVE)
- data = data - memaddr;
-
- if (data < 0)
- is_neg = 1;
-
- data >>= 2;
- data &= (mask >> 1);
-
- if (is_neg)
- data |= 1 << (oper->bits - 1);
- }
-
- else if (oper->hint & OH_REG) {
- if (txt[0] == 'r' || txt[0] == 'R')
- txt++;
- else if (txt[0] == '%' && (txt[1] == 'r' || txt[1] == 'R'))
- txt += 2;
-
- data = read_number (txt);
- if (data > 31) {
- if (err)
- *err = E_ASM_BAD_REGISTER;
- return -1;
- }
-
- data = htonl (data);
- }
-
- else if (oper->hint & OH_SPR) {
- if ((data = spr_value (txt)) == 0) {
- if (err)
- *err = E_ASM_BAD_SPR;
- return -1;
- }
- }
-
- else if (oper->hint & OH_TBR) {
- if ((data = tbr_value (txt)) == 0) {
- if (err)
- *err = E_ASM_BAD_TBR;
- return -1;
- }
- }
-
- else {
- data = htonl (read_number (txt));
- }
-
- return (data & mask) << oper->shift;
-} /* parse_operand */
-
-
-char *asm_error_str (int err)
-{
- switch (err) {
- case E_ASM_BAD_OPCODE:
- return "Bad opcode";
- case E_ASM_NUM_OPERANDS:
- return "Bad number of operands";
- case E_ASM_BAD_REGISTER:
- return "Bad register number";
- case E_ASM_BAD_SPR:
- return "Bad SPR name or number";
- case E_ASM_BAD_TBR:
- return "Bad TBR name or number";
- }
-
- return "";
-} /* asm_error_str */
-\f
-
-
-/*======================================================================
- * Copy a word from one buffer to another, ignores leading white spaces.
- *
- * Arguments:
- * src The address of a character pointer to the
- * source buffer.
- * dest A pointer to a character buffer to write the word
- * into.
- *
- * Returns the number of non-white space characters copied, or zero.
- */
-
-int get_word (char **src, char *dest)
-{
- char *ptr = *src;
- int nchars = 0;
-
- /*------------------------------------------------------------*/
-
- /* Eat white spaces */
- while (*ptr && isblank (*ptr))
- ptr++;
-
- if (*ptr == 0) {
- *src = ptr;
- return 0;
- }
-
- /* Find the text of the word */
- while (*ptr && !isblank (*ptr) && (*ptr != ','))
- dest[nchars++] = *ptr++;
- ptr = (*ptr == ',') ? ptr + 1 : ptr;
- dest[nchars] = 0;
-
- *src = ptr;
- return nchars;
-} /* get_word */
-\f
-
-
-/*======================================================================
- * Convert a numeric string to a number, be aware of base notations.
- *
- * Arguments:
- * txt The numeric string.
- *
- * Returns the converted numeric value.
- */
-
-long read_number (char *txt)
-{
- long val;
- int is_neg = 0;
-
- /*------------------------------------------------------------*/
-
- if (txt == 0 || *txt == 0)
- return 0;
-
- if (*txt == '-') {
- is_neg = 1;
- ++txt;
- }
-
- if (txt[0] == '0' && (txt[1] == 'x' || txt[1] == 'X')) /* hex */
- val = simple_strtoul (&txt[2], NULL, 16);
- else /* decimal */
- val = simple_strtoul (txt, NULL, 10);
-
- if (is_neg)
- val = -val;
-
- return val;
-} /* read_number */
-
-
-int downstring (char *s)
-{
- if (!s || !*s)
- return 0;
-
- while (*s) {
- if (isupper (*s))
- *s = tolower (*s);
- s++;
- }
-
- return 0;
-} /* downstring */
-\f
-
-
-/*======================================================================
- * Examines the instruction at the current address and determines the
- * next address to be executed. This will take into account branches
- * of different types so that a "step" and "next" operations can be
- * supported.
- *
- * Arguments:
- * nextaddr The address (to be filled in) of the next
- * instruction to execute. This will only be a valid
- * address if TRUE is returned.
- *
- * step_over A flag indicating how to compute addresses for
- * branch statements:
- * TRUE = Step over the branch (next)
- * FALSE = step into the branch (step)
- *
- * Returns TRUE if it was able to compute the address. Returns FALSE if
- * it has a problem reading the current instruction or one of the registers.
- */
-
-int find_next_address (unsigned char *nextaddr, int step_over,
- struct pt_regs *regs)
-{
- unsigned long pc; /* SRR0 register from PPC */
- unsigned long ctr; /* CTR register from PPC */
- unsigned long cr; /* CR register from PPC */
- unsigned long lr; /* LR register from PPC */
- unsigned long instr; /* instruction at SRR0 */
- unsigned long next; /* computed instruction for 'next' */
- unsigned long step; /* computed instruction for 'step' */
- unsigned long addr = 0; /* target address operand */
- unsigned long aa = 0; /* AA operand */
- unsigned long lk = 0; /* LK operand */
- unsigned long bo = 0; /* BO operand */
- unsigned long bi = 0; /* BI operand */
- struct opcode *op = 0; /* opcode structure for 'instr' */
- int ctr_ok = 0;
- int cond_ok = 0;
- int conditional = 0;
- int branch = 0;
-
- /*------------------------------------------------------------*/
-
- if (nextaddr == 0 || regs == 0) {
- printf ("find_next_address: bad args");
- return FALSE;
- }
-
- pc = regs->nip & 0xfffffffc;
- instr = INSTRUCTION (pc);
-
- if ((op = find_opcode (instr)) == (struct opcode *) 0) {
- printf ("find_next_address: can't parse opcode 0x%lx", instr);
- return FALSE;
- }
-
- ctr = regs->ctr;
- cr = regs->ccr;
- lr = regs->link;
-
- switch (op->opcode) {
- case B_OPCODE (16, 0, 0): /* bc */
- case B_OPCODE (16, 0, 1): /* bcl */
- case B_OPCODE (16, 1, 0): /* bca */
- case B_OPCODE (16, 1, 1): /* bcla */
- if (!get_operand_value (op, instr, O_BD, &addr) ||
- !get_operand_value (op, instr, O_BO, &bo) ||
- !get_operand_value (op, instr, O_BI, &bi) ||
- !get_operand_value (op, instr, O_AA, &aa) ||
- !get_operand_value (op, instr, O_LK, &lk))
- return FALSE;
-
- if ((addr & (1 << 13)) != 0)
- addr = addr - (1 << 14);
- addr <<= 2;
- conditional = 1;
- branch = 1;
- break;
-
- case I_OPCODE (18, 0, 0): /* b */
- case I_OPCODE (18, 0, 1): /* bl */
- case I_OPCODE (18, 1, 0): /* ba */
- case I_OPCODE (18, 1, 1): /* bla */
- if (!get_operand_value (op, instr, O_LI, &addr) ||
- !get_operand_value (op, instr, O_AA, &aa) ||
- !get_operand_value (op, instr, O_LK, &lk))
- return FALSE;
-
- if ((addr & (1 << 23)) != 0)
- addr = addr - (1 << 24);
- addr <<= 2;
- conditional = 0;
- branch = 1;
- break;
-
- case XL_OPCODE (19, 528, 0): /* bcctr */
- case XL_OPCODE (19, 528, 1): /* bcctrl */
- if (!get_operand_value (op, instr, O_BO, &bo) ||
- !get_operand_value (op, instr, O_BI, &bi) ||
- !get_operand_value (op, instr, O_LK, &lk))
- return FALSE;
-
- addr = ctr;
- aa = 1;
- conditional = 1;
- branch = 1;
- break;
-
- case XL_OPCODE (19, 16, 0): /* bclr */
- case XL_OPCODE (19, 16, 1): /* bclrl */
- if (!get_operand_value (op, instr, O_BO, &bo) ||
- !get_operand_value (op, instr, O_BI, &bi) ||
- !get_operand_value (op, instr, O_LK, &lk))
- return FALSE;
-
- addr = lr;
- aa = 1;
- conditional = 1;
- branch = 1;
- break;
-
- default:
- conditional = 0;
- branch = 0;
- break;
- }
-
- if (conditional) {
- switch ((bo & 0x1e) >> 1) {
- case 0: /* 0000y */
- if (--ctr != 0)
- ctr_ok = 1;
-
- cond_ok = !(cr & (1 << (31 - bi)));
- break;
-
- case 1: /* 0001y */
- if (--ctr == 0)
- ctr_ok = 1;
-
- cond_ok = !(cr & (1 << (31 - bi)));
- break;
-
- case 2: /* 001zy */
- ctr_ok = 1;
- cond_ok = !(cr & (1 << (31 - bi)));
- break;
-
- case 4: /* 0100y */
- if (--ctr != 0)
- ctr_ok = 1;
-
- cond_ok = cr & (1 << (31 - bi));
- break;
-
- case 5: /* 0101y */
- if (--ctr == 0)
- ctr_ok = 1;
-
- cond_ok = cr & (1 << (31 - bi));
- break;
-
- case 6: /* 011zy */
- ctr_ok = 1;
- cond_ok = cr & (1 << (31 - bi));
- break;
-
- case 8: /* 1z00y */
- if (--ctr != 0)
- ctr_ok = cond_ok = 1;
- break;
-
- case 9: /* 1z01y */
- if (--ctr == 0)
- ctr_ok = cond_ok = 1;
- break;
-
- case 10: /* 1z1zz */
- ctr_ok = cond_ok = 1;
- break;
- }
- }
-
- if (branch && (!conditional || (ctr_ok && cond_ok))) {
- if (aa)
- step = addr;
- else
- step = addr + pc;
-
- if (lk)
- next = pc + 4;
- else
- next = step;
- } else {
- step = next = pc + 4;
- }
-
- if (step_over == TRUE)
- *(unsigned long *) nextaddr = next;
- else
- *(unsigned long *) nextaddr = step;
-
- return TRUE;
-} /* find_next_address */
-
-
-/*
- * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are freely
- * permitted provided that the above copyright notice and this
- * paragraph and the following disclaimer are duplicated in all
- * such forms.
- *
- * This software is provided "AS IS" and without any express or
- * implied warranties, including, without limitation, the implied
- * warranties of merchantability and fitness for a particular
- * purpose.
- */
+++ /dev/null
-/*
- * BedBug Functions
- */
-
-#include <common.h>
-#include <command.h>
-#include <linux/ctype.h>
-#include <net.h>
-#include <bedbug/type.h>
-#include <bedbug/bedbug.h>
-#include <bedbug/regs.h>
-#include <bedbug/ppc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void show_regs __P ((struct pt_regs *));
-extern int run_command __P ((const char *, int));
-extern char console_buffer[];
-
-ulong dis_last_addr = 0; /* Last address disassembled */
-ulong dis_last_len = 20; /* Default disassembler length */
-CPU_DEBUG_CTX bug_ctx; /* Bedbug context structure */
-\f
-
-/* ======================================================================
- * U-Boot's puts function does not append a newline, so the bedbug stuff
- * will use this for the output of the dis/assembler.
- * ====================================================================== */
-
-int bedbug_puts (const char *str)
-{
- /* -------------------------------------------------- */
-
- printf ("%s\r\n", str);
- return 0;
-} /* bedbug_puts */
-\f
-
-
-/* ======================================================================
- * Initialize the bug_ctx structure used by the bedbug debugger. This is
- * specific to the CPU since each has different debug registers and
- * settings.
- * ====================================================================== */
-
-void bedbug_init (void)
-{
- /* -------------------------------------------------- */
-
-#if defined(CONFIG_4xx)
- void bedbug405_init (void);
-
- bedbug405_init ();
-#elif defined(CONFIG_8xx)
- void bedbug860_init (void);
-
- bedbug860_init ();
-#endif
-
-#if defined(CONFIG_MPC824X) || defined(CONFIG_MPC8260)
- /* Processors that are 603e core based */
- void bedbug603e_init (void);
-
- bedbug603e_init ();
-#endif
-
- return;
-} /* bedbug_init */
-\f
-
-
-/* ======================================================================
- * Entry point from the interpreter to the disassembler. Repeated calls
- * will resume from the last disassembled address.
- * ====================================================================== */
-int do_bedbug_dis (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
-{
- ulong addr; /* Address to start disassembly from */
- ulong len; /* # of instructions to disassemble */
-
- /* -------------------------------------------------- */
-
- /* Setup to go from the last address if none is given */
- addr = dis_last_addr;
- len = dis_last_len;
-
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
-
- if ((flag & CMD_FLAG_REPEAT) == 0) {
- /* New command */
- addr = simple_strtoul (argv[1], NULL, 16);
-
- /* If an extra param is given then it is the length */
- if (argc > 2)
- len = simple_strtoul (argv[2], NULL, 16);
- }
-
- /* Run the disassembler */
- disppc ((unsigned char *) addr, 0, len, bedbug_puts, F_RADHEX);
-
- dis_last_addr = addr + (len * 4);
- dis_last_len = len;
- return 0;
-} /* do_bedbug_dis */
-
-U_BOOT_CMD (ds, 3, 1, do_bedbug_dis,
- "disassemble memory",
- "ds <address> [# instructions]");
-\f
-/* ======================================================================
- * Entry point from the interpreter to the assembler. Assembles
- * instructions in consecutive memory locations until a '.' (period) is
- * entered on a line by itself.
- * ====================================================================== */
-int do_bedbug_asm (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
-{
- long mem_addr; /* Address to assemble into */
- unsigned long instr; /* Machine code for text */
- char prompt[15]; /* Prompt string for user input */
- int asm_err; /* Error code from the assembler */
-
- /* -------------------------------------------------- */
- int rcode = 0;
-
- if (argc < 2) {
- cmd_usage(cmdtp);
- return 1;
- }
-
- printf ("\nEnter '.' when done\n");
- mem_addr = simple_strtoul (argv[1], NULL, 16);
-
- while (1) {
- putc ('\n');
- disppc ((unsigned char *) mem_addr, 0, 1, bedbug_puts,
- F_RADHEX);
-
- sprintf (prompt, "%08lx: ", mem_addr);
- readline (prompt);
-
- if (console_buffer[0] && strcmp (console_buffer, ".")) {
- if ((instr =
- asmppc (mem_addr, console_buffer,
- &asm_err)) != 0) {
- *(unsigned long *) mem_addr = instr;
- mem_addr += 4;
- } else {
- printf ("*** Error: %s ***\n",
- asm_error_str (asm_err));
- rcode = 1;
- }
- } else {
- break;
- }
- }
- return rcode;
-} /* do_bedbug_asm */
-
-U_BOOT_CMD (as, 2, 0, do_bedbug_asm,
- "assemble memory", "as <address>");
-\f
-/* ======================================================================
- * Used to set a break point from the interpreter. Simply calls into the
- * CPU-specific break point set routine.
- * ====================================================================== */
-
-int do_bedbug_break (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
-{
- /* -------------------------------------------------- */
- if (bug_ctx.do_break)
- (*bug_ctx.do_break) (cmdtp, flag, argc, argv);
- return 0;
-
-} /* do_bedbug_break */
-
-U_BOOT_CMD (break, 3, 0, do_bedbug_break,
- "set or clear a breakpoint",
- " - Set or clear a breakpoint\n"
- "break <address> - Break at an address\n"
- "break off <bp#> - Disable breakpoint.\n"
- "break show - List breakpoints.");
-\f
-/* ======================================================================
- * Called from the debug interrupt routine. Simply calls the CPU-specific
- * breakpoint handling routine.
- * ====================================================================== */
-
-void do_bedbug_breakpoint (struct pt_regs *regs)
-{
- /* -------------------------------------------------- */
-
- if (bug_ctx.break_isr)
- (*bug_ctx.break_isr) (regs);
-
- return;
-} /* do_bedbug_breakpoint */
-\f
-
-
-/* ======================================================================
- * Called from the CPU-specific breakpoint handling routine. Enter a
- * mini main loop until the stopped flag is cleared from the breakpoint
- * context.
- *
- * This handles the parts of the debugger that are common to all CPU's.
- * ====================================================================== */
-
-void bedbug_main_loop (unsigned long addr, struct pt_regs *regs)
-{
- int len; /* Length of command line */
- int flag; /* Command flags */
- int rc = 0; /* Result from run_command */
- char prompt_str[20]; /* Prompt string */
- static char lastcommand[CONFIG_SYS_CBSIZE] = { 0 }; /* previous command */
- /* -------------------------------------------------- */
-
- if (bug_ctx.clear)
- (*bug_ctx.clear) (bug_ctx.current_bp);
-
- printf ("Breakpoint %d: ", bug_ctx.current_bp);
- disppc ((unsigned char *) addr, 0, 1, bedbug_puts, F_RADHEX);
-
- bug_ctx.stopped = 1;
- bug_ctx.regs = regs;
-
- sprintf (prompt_str, "BEDBUG.%d =>", bug_ctx.current_bp);
-
- /* A miniature main loop */
- while (bug_ctx.stopped) {
- len = readline (prompt_str);
-
- flag = 0; /* assume no special flags for now */
-
- if (len > 0)
- strcpy (lastcommand, console_buffer);
- else if (len == 0)
- flag |= CMD_FLAG_REPEAT;
-
- if (len == -1)
- printf ("<INTERRUPT>\n");
- else
- rc = run_command (lastcommand, flag);
-
- if (rc <= 0) {
- /* invalid command or not repeatable, forget it */
- lastcommand[0] = 0;
- }
- }
-
- bug_ctx.regs = NULL;
- bug_ctx.current_bp = 0;
-
- return;
-} /* bedbug_main_loop */
-\f
-
-
-/* ======================================================================
- * Interpreter command to continue from a breakpoint. Just clears the
- * stopped flag in the context so that the breakpoint routine will
- * return.
- * ====================================================================== */
-int do_bedbug_continue (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
-{
- /* -------------------------------------------------- */
-
- if (!bug_ctx.stopped) {
- printf ("Not at a breakpoint\n");
- return 1;
- }
-
- bug_ctx.stopped = 0;
- return 0;
-} /* do_bedbug_continue */
-
-U_BOOT_CMD (continue, 1, 0, do_bedbug_continue,
- "continue from a breakpoint",
- "");
-\f
-/* ======================================================================
- * Interpreter command to continue to the next instruction, stepping into
- * subroutines. Works by calling the find_next_addr() routine to compute
- * the address passes control to the CPU-specific set breakpoint routine
- * for the current breakpoint number.
- * ====================================================================== */
-int do_bedbug_step (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
-{
- unsigned long addr; /* Address to stop at */
-
- /* -------------------------------------------------- */
-
- if (!bug_ctx.stopped) {
- printf ("Not at a breakpoint\n");
- return 1;
- }
-
- if (!find_next_address ((unsigned char *) &addr, FALSE, bug_ctx.regs))
- return 1;
-
- if (bug_ctx.set)
- (*bug_ctx.set) (bug_ctx.current_bp, addr);
-
- bug_ctx.stopped = 0;
- return 0;
-} /* do_bedbug_step */
-
-U_BOOT_CMD (step, 1, 1, do_bedbug_step,
- "single step execution.",
- "");
-\f
-/* ======================================================================
- * Interpreter command to continue to the next instruction, stepping over
- * subroutines. Works by calling the find_next_addr() routine to compute
- * the address passes control to the CPU-specific set breakpoint routine
- * for the current breakpoint number.
- * ====================================================================== */
-int do_bedbug_next (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
-{
- unsigned long addr; /* Address to stop at */
-
- /* -------------------------------------------------- */
-
- if (!bug_ctx.stopped) {
- printf ("Not at a breakpoint\n");
- return 1;
- }
-
- if (!find_next_address ((unsigned char *) &addr, TRUE, bug_ctx.regs))
- return 1;
-
- if (bug_ctx.set)
- (*bug_ctx.set) (bug_ctx.current_bp, addr);
-
- bug_ctx.stopped = 0;
- return 0;
-} /* do_bedbug_next */
-
-U_BOOT_CMD (next, 1, 1, do_bedbug_next,
- "single step execution, stepping over subroutines.",
- "");
-\f
-/* ======================================================================
- * Interpreter command to print the current stack. This assumes an EABI
- * architecture, so it starts with GPR R1 and works back up the stack.
- * ====================================================================== */
-int do_bedbug_stack (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
-{
- unsigned long sp; /* Stack pointer */
- unsigned long func; /* LR from stack */
- int depth; /* Stack iteration level */
- int skip = 1; /* Flag to skip the first entry */
- unsigned long top; /* Top of memory address */
-
- /* -------------------------------------------------- */
-
- if (!bug_ctx.stopped) {
- printf ("Not at a breakpoint\n");
- return 1;
- }
-
- top = gd->bd->bi_memstart + gd->bd->bi_memsize;
- depth = 0;
-
- printf ("Depth PC\n");
- printf ("----- --------\n");
- printf ("%5d %08lx\n", depth++, bug_ctx.regs->nip);
-
- sp = bug_ctx.regs->gpr[1];
- func = *(unsigned long *) (sp + 4);
-
- while ((func < top) && (sp < top)) {
- if (!skip)
- printf ("%5d %08lx\n", depth++, func);
- else
- --skip;
-
- sp = *(unsigned long *) sp;
- func = *(unsigned long *) (sp + 4);
- }
- return 0;
-} /* do_bedbug_stack */
-
-U_BOOT_CMD (where, 1, 1, do_bedbug_stack,
- "Print the running stack.",
- "");
-\f
-/* ======================================================================
- * Interpreter command to dump the registers. Calls the CPU-specific
- * show registers routine.
- * ====================================================================== */
-int do_bedbug_rdump (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
-{
- /* -------------------------------------------------- */
-
- if (!bug_ctx.stopped) {
- printf ("Not at a breakpoint\n");
- return 1;
- }
-
- show_regs (bug_ctx.regs);
- return 0;
-} /* do_bedbug_rdump */
-
-U_BOOT_CMD (rdump, 1, 1, do_bedbug_rdump,
- "Show registers.", "");
-/* ====================================================================== */
-
-
-/*
- * Copyright (c) 2001 William L. Pitts
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are freely
- * permitted provided that the above copyright notice and this
- * paragraph and the following disclaimer are duplicated in all
- * such forms.
- *
- * This software is provided "AS IS" and without any express or
- * implied warranties, including, without limitation, the implied
- * warranties of merchantability and fitness for a particular
- * purpose.
- */
+++ /dev/null
-/*
- * Copyright (c) 2001 William L. Pitts
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are freely
- * permitted provided that the above copyright notice and this
- * paragraph and the following disclaimer are duplicated in all
- * such forms.
- *
- * This software is provided "AS IS" and without any express or
- * implied warranties, including, without limitation, the implied
- * warranties of merchantability and fitness for a particular
- * purpose.
- */
-
-#include <common.h>
-#include <command.h>
-#include <linux/ctype.h>
-#include <net.h>
-#include <elf.h>
-#include <vxworks.h>
-
-#if defined(CONFIG_WALNUT) || defined(CONFIG_SYS_VXWORKS_MAC_PTR)
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
-int valid_elf_image (unsigned long addr);
-unsigned long load_elf_image (unsigned long addr);
-
-/* Allow ports to override the default behavior */
-__attribute__((weak))
-unsigned long do_bootelf_exec (ulong (*entry)(int, char *[]), int argc, char *argv[])
-{
- unsigned long ret;
-
- /*
- * QNX images require the data cache is disabled.
- * Data cache is already flushed, so just turn it off.
- */
- int dcache = dcache_status ();
- if (dcache)
- dcache_disable ();
-
- /*
- * pass address parameter as argv[0] (aka command name),
- * and all remaining args
- */
- ret = entry (argc, argv);
-
- if (dcache)
- dcache_enable ();
-
- return ret;
-}
-
-/* ======================================================================
- * Interpreter command to boot an arbitrary ELF image from memory.
- * ====================================================================== */
-int do_bootelf (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- unsigned long addr; /* Address of the ELF image */
- unsigned long rc; /* Return value from user code */
-
- /* -------------------------------------------------- */
- int rcode = 0;
-
- if (argc < 2)
- addr = load_addr;
- else
- addr = simple_strtoul (argv[1], NULL, 16);
-
- if (!valid_elf_image (addr))
- return 1;
-
- addr = load_elf_image (addr);
-
- printf ("## Starting application at 0x%08lx ...\n", addr);
-
- /*
- * pass address parameter as argv[0] (aka command name),
- * and all remaining args
- */
- rc = do_bootelf_exec ((void *)addr, argc - 1, argv + 1);
- if (rc != 0)
- rcode = 1;
-
- printf ("## Application terminated, rc = 0x%lx\n", rc);
- return rcode;
-}
-
-/* ======================================================================
- * Interpreter command to boot VxWorks from a memory image. The image can
- * be either an ELF image or a raw binary. Will attempt to setup the
- * bootline and other parameters correctly.
- * ====================================================================== */
-int do_bootvx (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- unsigned long addr; /* Address of image */
- unsigned long bootaddr; /* Address to put the bootline */
- char *bootline; /* Text of the bootline */
- char *tmp; /* Temporary char pointer */
- char build_buf[128]; /* Buffer for building the bootline */
-
- /* ---------------------------------------------------
- *
- * Check the loadaddr variable.
- * If we don't know where the image is then we're done.
- */
-
- if (argc < 2)
- addr = load_addr;
- else
- addr = simple_strtoul (argv[1], NULL, 16);
-
-#if defined(CONFIG_CMD_NET)
- /* Check to see if we need to tftp the image ourselves before starting */
-
- if ((argc == 2) && (strcmp (argv[1], "tftp") == 0)) {
- if (NetLoop (TFTP) <= 0)
- return 1;
- printf ("Automatic boot of VxWorks image at address 0x%08lx ... \n",
- addr);
- }
-#endif
-
- /* This should equate
- * to NV_RAM_ADRS + NV_BOOT_OFFSET + NV_ENET_OFFSET
- * from the VxWorks BSP header files.
- * This will vary from board to board
- */
-
-#if defined(CONFIG_WALNUT)
- tmp = (char *) CONFIG_SYS_NVRAM_BASE_ADDR + 0x500;
- eth_getenv_enetaddr("ethaddr", (uchar *)build_buf);
- memcpy(tmp, &build_buf[3], 3);
-#elif defined(CONFIG_SYS_VXWORKS_MAC_PTR)
- tmp = (char *) CONFIG_SYS_VXWORKS_MAC_PTR;
- eth_getenv_enetaddr("ethaddr", (uchar *)build_buf);
- memcpy(tmp, build_buf, 6);
-#else
- puts ("## Ethernet MAC address not copied to NV RAM\n");
-#endif
-
- /*
- * Use bootaddr to find the location in memory that VxWorks
- * will look for the bootline string. The default value for
- * PowerPC is LOCAL_MEM_LOCAL_ADRS + BOOT_LINE_OFFSET which
- * defaults to 0x4200
- */
-
- if ((tmp = getenv ("bootaddr")) == NULL)
- bootaddr = CONFIG_SYS_VXWORKS_BOOT_ADDR;
- else
- bootaddr = simple_strtoul (tmp, NULL, 16);
-
- /*
- * Check to see if the bootline is defined in the 'bootargs'
- * parameter. If it is not defined, we may be able to
- * construct the info
- */
-
- if ((bootline = getenv ("bootargs")) != NULL) {
- memcpy ((void *) bootaddr, bootline,
- max (strlen (bootline), 255));
- flush_cache (bootaddr, max (strlen (bootline), 255));
- } else {
-
-
- sprintf (build_buf, CONFIG_SYS_VXWORKS_BOOT_DEVICE);
- if ((tmp = getenv ("bootfile")) != NULL) {
- sprintf (&build_buf[strlen (build_buf)],
- "%s:%s ", CONFIG_SYS_VXWORKS_SERVERNAME, tmp);
- } else {
- sprintf (&build_buf[strlen (build_buf)],
- "%s:file ", CONFIG_SYS_VXWORKS_SERVERNAME);
- }
-
- if ((tmp = getenv ("ipaddr")) != NULL) {
- sprintf (&build_buf[strlen (build_buf)], "e=%s ", tmp);
- }
-
- if ((tmp = getenv ("serverip")) != NULL) {
- sprintf (&build_buf[strlen (build_buf)], "h=%s ", tmp);
- }
-
- if ((tmp = getenv ("hostname")) != NULL) {
- sprintf (&build_buf[strlen (build_buf)], "tn=%s ", tmp);
- }
-#ifdef CONFIG_SYS_VXWORKS_ADD_PARAMS
- sprintf (&build_buf[strlen (build_buf)],
- CONFIG_SYS_VXWORKS_ADD_PARAMS);
-#endif
-
- memcpy ((void *) bootaddr, build_buf,
- max (strlen (build_buf), 255));
- flush_cache (bootaddr, max (strlen (build_buf), 255));
- }
-
- /*
- * If the data at the load address is an elf image, then
- * treat it like an elf image. Otherwise, assume that it is a
- * binary image
- */
-
- if (valid_elf_image (addr)) {
- addr = load_elf_image (addr);
- } else {
- puts ("## Not an ELF image, assuming binary\n");
- /* leave addr as load_addr */
- }
-
- printf ("## Using bootline (@ 0x%lx): %s\n", bootaddr,
- (char *) bootaddr);
- printf ("## Starting vxWorks at 0x%08lx ...\n", addr);
-
- ((void (*)(void)) addr) ();
-
- puts ("## vxWorks terminated\n");
- return 1;
-}
-
-/* ======================================================================
- * Determine if a valid ELF image exists at the given memory location.
- * First looks at the ELF header magic field, the makes sure that it is
- * executable and makes sure that it is for a PowerPC.
- * ====================================================================== */
-int valid_elf_image (unsigned long addr)
-{
- Elf32_Ehdr *ehdr; /* Elf header structure pointer */
-
- /* -------------------------------------------------- */
-
- ehdr = (Elf32_Ehdr *) addr;
-
- if (!IS_ELF (*ehdr)) {
- printf ("## No elf image at address 0x%08lx\n", addr);
- return 0;
- }
-
- if (ehdr->e_type != ET_EXEC) {
- printf ("## Not a 32-bit elf image at address 0x%08lx\n", addr);
- return 0;
- }
-
-#if 0
- if (ehdr->e_machine != EM_PPC) {
- printf ("## Not a PowerPC elf image at address 0x%08lx\n",
- addr);
- return 0;
- }
-#endif
-
- return 1;
-}
-
-/* ======================================================================
- * A very simple elf loader, assumes the image is valid, returns the
- * entry point address.
- * ====================================================================== */
-unsigned long load_elf_image (unsigned long addr)
-{
- Elf32_Ehdr *ehdr; /* Elf header structure pointer */
- Elf32_Shdr *shdr; /* Section header structure pointer */
- unsigned char *strtab = 0; /* String table pointer */
- unsigned char *image; /* Binary image pointer */
- int i; /* Loop counter */
-
- /* -------------------------------------------------- */
-
- ehdr = (Elf32_Ehdr *) addr;
-
- /* Find the section header string table for output info */
- shdr = (Elf32_Shdr *) (addr + ehdr->e_shoff +
- (ehdr->e_shstrndx * sizeof (Elf32_Shdr)));
-
- if (shdr->sh_type == SHT_STRTAB)
- strtab = (unsigned char *) (addr + shdr->sh_offset);
-
- /* Load each appropriate section */
- for (i = 0; i < ehdr->e_shnum; ++i) {
- shdr = (Elf32_Shdr *) (addr + ehdr->e_shoff +
- (i * sizeof (Elf32_Shdr)));
-
- if (!(shdr->sh_flags & SHF_ALLOC)
- || shdr->sh_addr == 0 || shdr->sh_size == 0) {
- continue;
- }
-
- if (strtab) {
- debug("%sing %s @ 0x%08lx (%ld bytes)\n",
- (shdr->sh_type == SHT_NOBITS) ?
- "Clear" : "Load",
- &strtab[shdr->sh_name],
- (unsigned long) shdr->sh_addr,
- (long) shdr->sh_size);
- }
-
- if (shdr->sh_type == SHT_NOBITS) {
- memset ((void *)shdr->sh_addr, 0, shdr->sh_size);
- } else {
- image = (unsigned char *) addr + shdr->sh_offset;
- memcpy ((void *) shdr->sh_addr,
- (const void *) image,
- shdr->sh_size);
- }
- flush_cache (shdr->sh_addr, shdr->sh_size);
- }
-
- return ehdr->e_entry;
-}
-
-/* ====================================================================== */
-U_BOOT_CMD(
- bootelf, 2, 0, do_bootelf,
- "Boot from an ELF image in memory",
- " [address] - load address of ELF image."
-);
-
-U_BOOT_CMD(
- bootvx, 2, 0, do_bootvx,
- "Boot vxWorks from an ELF image",
- " [address] - load address of vxWorks ELF image."
-);
+++ /dev/null
-/*
- * Copyright (C) 2000-2005, DENX Software Engineering
- * Wolfgang Denk <wd@denx.de>
- * Copyright (C) Procsys. All rights reserved.
- * Mushtaq Khan <mushtaq_k@procsys.com>
- * <mushtaqk_921@yahoo.co.in>
- * Copyright (C) 2008 Freescale Semiconductor, Inc.
- * Dave Liu <daveliu@freescale.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <part.h>
-#include <sata.h>
-
-int sata_curr_device = -1;
-block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
-
-int __sata_initialize(void)
-{
- int rc;
- int i;
-
- for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; i++) {
- memset(&sata_dev_desc[i], 0, sizeof(struct block_dev_desc));
- sata_dev_desc[i].if_type = IF_TYPE_SATA;
- sata_dev_desc[i].dev = i;
- sata_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
- sata_dev_desc[i].type = DEV_TYPE_HARDDISK;
- sata_dev_desc[i].lba = 0;
- sata_dev_desc[i].blksz = 512;
- sata_dev_desc[i].block_read = sata_read;
- sata_dev_desc[i].block_write = sata_write;
-
- rc = init_sata(i);
- rc = scan_sata(i);
- if ((sata_dev_desc[i].lba > 0) && (sata_dev_desc[i].blksz > 0))
- init_part(&sata_dev_desc[i]);
- }
- sata_curr_device = 0;
- return rc;
-}
-int sata_initialize(void) __attribute__((weak,alias("__sata_initialize")));
-
-block_dev_desc_t *sata_get_dev(int dev)
-{
- return (dev < CONFIG_SYS_SATA_MAX_DEVICE) ? &sata_dev_desc[dev] : NULL;
-}
-
-int do_sata(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- int rc = 0;
-
- if (argc == 2 && strcmp(argv[1], "init") == 0)
- return sata_initialize();
-
- /* If the user has not yet run `sata init`, do it now */
- if (sata_curr_device == -1)
- if (sata_initialize())
- return 1;
-
- switch (argc) {
- case 0:
- case 1:
- cmd_usage(cmdtp);
- return 1;
- case 2:
- if (strncmp(argv[1],"inf", 3) == 0) {
- int i;
- putc('\n');
- for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; ++i) {
- if (sata_dev_desc[i].type == DEV_TYPE_UNKNOWN)
- continue;
- printf ("SATA device %d: ", i);
- dev_print(&sata_dev_desc[i]);
- }
- return 0;
- } else if (strncmp(argv[1],"dev", 3) == 0) {
- if ((sata_curr_device < 0) || (sata_curr_device >= CONFIG_SYS_SATA_MAX_DEVICE)) {
- puts("\nno SATA devices available\n");
- return 1;
- }
- printf("\nSATA device %d: ", sata_curr_device);
- dev_print(&sata_dev_desc[sata_curr_device]);
- return 0;
- } else if (strncmp(argv[1],"part",4) == 0) {
- int dev, ok;
-
- for (ok = 0, dev = 0; dev < CONFIG_SYS_SATA_MAX_DEVICE; ++dev) {
- if (sata_dev_desc[dev].part_type != PART_TYPE_UNKNOWN) {
- ++ok;
- if (dev)
- putc ('\n');
- print_part(&sata_dev_desc[dev]);
- }
- }
- if (!ok) {
- puts("\nno SATA devices available\n");
- rc ++;
- }
- return rc;
- }
- cmd_usage(cmdtp);
- return 1;
- case 3:
- if (strncmp(argv[1], "dev", 3) == 0) {
- int dev = (int)simple_strtoul(argv[2], NULL, 10);
-
- printf("\nSATA device %d: ", dev);
- if (dev >= CONFIG_SYS_SATA_MAX_DEVICE) {
- puts ("unknown device\n");
- return 1;
- }
- dev_print(&sata_dev_desc[dev]);
-
- if (sata_dev_desc[dev].type == DEV_TYPE_UNKNOWN)
- return 1;
-
- sata_curr_device = dev;
-
- puts("... is now current device\n");
-
- return 0;
- } else if (strncmp(argv[1], "part", 4) == 0) {
- int dev = (int)simple_strtoul(argv[2], NULL, 10);
-
- if (sata_dev_desc[dev].part_type != PART_TYPE_UNKNOWN) {
- print_part(&sata_dev_desc[dev]);
- } else {
- printf("\nSATA device %d not available\n", dev);
- rc = 1;
- }
- return rc;
- }
- cmd_usage(cmdtp);
- return 1;
-
- default: /* at least 4 args */
- if (strcmp(argv[1], "read") == 0) {
- ulong addr = simple_strtoul(argv[2], NULL, 16);
- ulong cnt = simple_strtoul(argv[4], NULL, 16);
- ulong n;
- lbaint_t blk = simple_strtoul(argv[3], NULL, 16);
-
- printf("\nSATA read: device %d block # %ld, count %ld ... ",
- sata_curr_device, blk, cnt);
-
- n = sata_read(sata_curr_device, blk, cnt, (u32 *)addr);
-
- /* flush cache after read */
- flush_cache(addr, cnt * sata_dev_desc[sata_curr_device].blksz);
-
- printf("%ld blocks read: %s\n",
- n, (n==cnt) ? "OK" : "ERROR");
- return (n == cnt) ? 0 : 1;
- } else if (strcmp(argv[1], "write") == 0) {
- ulong addr = simple_strtoul(argv[2], NULL, 16);
- ulong cnt = simple_strtoul(argv[4], NULL, 16);
- ulong n;
-
- lbaint_t blk = simple_strtoul(argv[3], NULL, 16);
-
- printf("\nSATA write: device %d block # %ld, count %ld ... ",
- sata_curr_device, blk, cnt);
-
- n = sata_write(sata_curr_device, blk, cnt, (u32 *)addr);
-
- printf("%ld blocks written: %s\n",
- n, (n == cnt) ? "OK" : "ERROR");
- return (n == cnt) ? 0 : 1;
- } else {
- cmd_usage(cmdtp);
- rc = 1;
- }
-
- return rc;
- }
-}
-
-U_BOOT_CMD(
- sata, 5, 1, do_sata,
- "SATA sub system",
- "sata init - init SATA sub system\n"
- "sata info - show available SATA devices\n"
- "sata device [dev] - show or set current device\n"
- "sata part [dev] - print partition table\n"
- "sata read addr blk# cnt\n"
- "sata write addr blk# cnt"
-);
+++ /dev/null
-/*
- * Copyright (c) Orbacom Systems, Inc <www.orbacom.com>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are freely
- * permitted provided that the above copyright notice and this
- * paragraph and the following disclaimer are duplicated in all
- * such forms.
- *
- * This software is provided "AS IS" and without any express or
- * implied warranties, including, without limitation, the implied
- * warranties of merchantability and fitness for a particular
- * purpose.
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <image.h>
-#include <net.h>
-
-#include <lynxkdi.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_MPC8260) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
-void lynxkdi_boot (image_header_t *hdr)
-{
- void (*lynxkdi)(void) = (void(*)(void))image_get_ep (hdr);
- lynxos_bootparms_t *parms = (lynxos_bootparms_t *)0x0020;
- bd_t *kbd;
- u32 *psz = (u32 *)(image_get_load (hdr) + 0x0204);
-
- memset (parms, 0, sizeof(*parms));
- kbd = gd->bd;
- parms->clock_ref = kbd->bi_busfreq;
- parms->dramsz = kbd->bi_memsize;
- eth_getenv_enetaddr("ethaddr", parms->ethaddr);
- mtspr (SPRN_SPRG2, 0x0020);
-
- /* Do a simple check for Bluecat so we can pass the
- * kernel command line parameters.
- */
- if (le32_to_cpu (*psz) == image_get_data_size (hdr)) { /* FIXME: NOT SURE HERE ! */
- char *args;
- char *cmdline = (char *)(image_get_load (hdr) + 0x020c);
- int len;
-
- printf ("Booting Bluecat KDI ...\n");
- udelay (200*1000); /* Allow serial port to flush */
- if ((args = getenv ("bootargs")) == NULL)
- args = "";
- /* Prepend the cmdline */
- len = strlen (args);
- if (len && (len + strlen (cmdline) + 2 < (0x0400 - 0x020c))) {
- memmove (cmdline + strlen (args) + 1, cmdline, strlen (cmdline));
- strcpy (cmdline, args);
- cmdline[len] = ' ';
- }
- }
- else {
- printf ("Booting LynxOS KDI ...\n");
- }
-
- lynxkdi ();
-}
-#else
-#error "Lynx KDI support not implemented for configured CPU"
-#endif
+++ /dev/null
-/**
- * @file IxEthAcc.c
- *
- * @author Intel Corporation
- * @date 20-Feb-2001
- *
- * @brief This file contains the implementation of the IXP425 Ethernet Access Component
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-
-
-#include "IxEthAcc.h"
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
-#include "IxEthDB.h"
-#endif
-#include "IxFeatureCtrl.h"
-
-#include "IxEthAcc_p.h"
-#include "IxEthAccMac_p.h"
-#include "IxEthAccMii_p.h"
-
-/**
- * @addtogroup IxEthAcc
- *@{
- */
-
-
-/**
- * @brief System-wide information data strucure.
- *
- * @ingroup IxEthAccPri
- *
- */
-
-IxEthAccInfo ixEthAccDataInfo;
-extern PUBLIC IxEthAccMacState ixEthAccMacState[];
-extern PUBLIC IxOsalMutex ixEthAccControlInterfaceMutex;
-
-/**
- * @brief System-wide information
- *
- * @ingroup IxEthAccPri
- *
- */
-BOOL ixEthAccServiceInit = FALSE;
-
-/* global filtering bit mask */
-PUBLIC UINT32 ixEthAccNewSrcMask;
-
-/**
- * @brief Per port information data strucure.
- *
- * @ingroup IxEthAccPri
- *
- */
-
-IxEthAccPortDataInfo ixEthAccPortData[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-PUBLIC IxEthAccStatus ixEthAccInit()
-{
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
- /*
- * Initialize Control plane
- */
- if (ixEthDBInit() != IX_ETH_ACC_SUCCESS)
- {
- IX_ETH_ACC_WARNING_LOG("ixEthAccInit: EthDB init failed\n", 0, 0, 0, 0, 0, 0);
-
- return IX_ETH_ACC_FAIL;
- }
-#endif
-
- if (IX_FEATURE_CTRL_SWCONFIG_ENABLED == ixFeatureCtrlSwConfigurationCheck (IX_FEATURECTRL_ETH_LEARNING))
- {
- ixEthAccNewSrcMask = (~0); /* want all the bits */
- }
- else
- {
- ixEthAccNewSrcMask = (~IX_ETHACC_NE_NEWSRCMASK); /* want all but the NewSrc bit */
- }
-
- /*
- * Initialize Data plane
- */
- if ( ixEthAccInitDataPlane() != IX_ETH_ACC_SUCCESS )
- {
- IX_ETH_ACC_WARNING_LOG("ixEthAccInit: data plane init failed\n", 0, 0, 0, 0, 0, 0);
-
- return IX_ETH_ACC_FAIL;
- }
-
-
- if ( ixEthAccQMgrQueuesConfig() != IX_ETH_ACC_SUCCESS )
- {
- IX_ETH_ACC_WARNING_LOG("ixEthAccInit: queue config failed\n", 0, 0, 0, 0, 0, 0);
-
- return IX_ETH_ACC_FAIL;
- }
-
- /*
- * Initialize MII
- */
- if ( ixEthAccMiiInit() != IX_ETH_ACC_SUCCESS )
- {
- IX_ETH_ACC_WARNING_LOG("ixEthAccInit: Mii init failed\n", 0, 0, 0, 0, 0, 0);
-
- return IX_ETH_ACC_FAIL;
- }
-
- /*
- * Initialize MAC I/O memory
- */
- if (ixEthAccMacMemInit() != IX_ETH_ACC_SUCCESS)
- {
- IX_ETH_ACC_WARNING_LOG("ixEthAccInit: Mac init failed\n", 0, 0, 0, 0, 0, 0);
-
- return IX_ETH_ACC_FAIL;
- }
-
- /*
- * Initialize control plane interface lock
- */
- if (ixOsalMutexInit(&ixEthAccControlInterfaceMutex) != IX_SUCCESS)
- {
- IX_ETH_ACC_WARNING_LOG("ixEthAccInit: Control plane interface lock initialization failed\n", 0, 0, 0, 0, 0, 0);
-
- return IX_ETH_ACC_FAIL;
- }
-
- /* initialiasation is complete */
- ixEthAccServiceInit = TRUE;
-
- return IX_ETH_ACC_SUCCESS;
-
-}
-
-PUBLIC void ixEthAccUnload(void)
-{
- IxEthAccPortId portId;
-
- if ( IX_ETH_ACC_IS_SERVICE_INITIALIZED() )
- {
- /* check none of the port is still active */
- for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
- {
- if ( IX_ETH_IS_PORT_INITIALIZED(portId) )
- {
- if (ixEthAccMacState[portId].portDisableState == ACTIVE)
- {
- IX_ETH_ACC_WARNING_LOG("ixEthAccUnload: port %u still active, bail out\n", portId, 0, 0, 0, 0, 0);
- return;
- }
- }
- }
-
- /* unmap the memory areas */
- ixEthAccMiiUnload();
- ixEthAccMacUnload();
-
- /* set all ports as uninitialized */
- for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
- {
- ixEthAccPortData[portId].portInitialized = FALSE;
- }
-
- /* uninitialize the service */
- ixEthAccServiceInit = FALSE;
- }
-}
-
-PUBLIC IxEthAccStatus ixEthAccPortInit( IxEthAccPortId portId)
-{
-
- IxEthAccStatus ret=IX_ETH_ACC_SUCCESS;
-
- if ( ! IX_ETH_ACC_IS_SERVICE_INITIALIZED() )
- {
- return(IX_ETH_ACC_FAIL);
- }
-
- /*
- * Check for valid port
- */
-
- if ( ! IX_ETH_ACC_IS_PORT_VALID(portId) )
- {
- return (IX_ETH_ACC_INVALID_PORT);
- }
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot initialize Eth port.\n",(INT32) portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if ( IX_ETH_IS_PORT_INITIALIZED(portId) )
- {
- /* Already initialized */
- return(IX_ETH_ACC_FAIL);
- }
-
- if(ixEthAccMacInit(portId)!=IX_ETH_ACC_SUCCESS)
- {
- return IX_ETH_ACC_FAIL;
- }
-
- /*
- * Set the port init flag.
- */
-
- ixEthAccPortData[portId].portInitialized = TRUE;
-
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
- /* init learning/filtering database structures for this port */
- ixEthDBPortInit(portId);
-#endif
-
- return(ret);
-}
-
-
+++ /dev/null
-/**
- * @file IxEthAccCommon.c
- *
- * @author Intel Corporation
- * @date 12-Feb-2002
- *
- * @brief This file contains the implementation common support routines for the component
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-/*
- * Component header files
- */
-
-#include "IxOsal.h"
-#include "IxEthAcc.h"
-#include "IxEthDB.h"
-#include "IxNpeMh.h"
-#include "IxEthDBPortDefs.h"
-#include "IxFeatureCtrl.h"
-#include "IxEthAcc_p.h"
-#include "IxEthAccQueueAssign_p.h"
-
-#include "IxEthAccDataPlane_p.h"
-#include "IxEthAccMii_p.h"
-
-/**
- * @addtogroup IxEthAccPri
- *@{
- */
-
-extern IxEthAccInfo ixEthAccDataInfo;
-
-/**
- *
- * @brief Maximum number of RX queues set to be the maximum number
- * of traffic calsses.
- *
- */
-#define IX_ETHACC_MAX_RX_QUEUES \
- (IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY \
- - IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY \
- + 1)
-
-/**
- *
- * @brief Maximum number of 128 entry RX queues
- *
- */
-#define IX_ETHACC_MAX_LARGE_RX_QUEUES 4
-
-/**
- *
- * @brief Data structure template for Default RX Queues
- *
- */
-IX_ETH_ACC_PRIVATE
-IxEthAccQregInfo ixEthAccQmgrRxDefaultTemplate =
- {
- IX_ETH_ACC_RX_FRAME_ETH_Q, /**< Queue ID */
- "Eth Rx Q",
- ixEthRxFrameQMCallback, /**< Functional callback */
- (IxQMgrCallbackId) 0, /**< Callback tag */
- IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */
- IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */
- TRUE, /**< Enable Q notification at startup */
- IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback */
- IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */
- IX_QMGR_Q_WM_LEVEL1, /**< Q High water mark - needed by NPE */
- };
-
-/**
- *
- * @brief Data structure template for Small RX Queues
- *
- */
-IX_ETH_ACC_PRIVATE
-IxEthAccQregInfo ixEthAccQmgrRxSmallTemplate =
- {
- IX_ETH_ACC_RX_FRAME_ETH_Q, /**< Queue ID */
- "Eth Rx Q",
- ixEthRxFrameQMCallback, /**< Functional callback */
- (IxQMgrCallbackId) 0, /**< Callback tag */
- IX_QMGR_Q_SIZE64, /**< Allocate Smaller Q */
- IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */
- TRUE, /**< Enable Q notification at startup */
- IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback */
- IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */
- IX_QMGR_Q_WM_LEVEL1, /**< Q High water mark - needed by NPE */
- };
-
-
-/**
- *
- * @brief Data structure used to register & initialize the Queues
- *
- */
-IX_ETH_ACC_PRIVATE
-IxEthAccQregInfo ixEthAccQmgrStaticInfo[]=
-{
- {
- IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q,
- "Eth Rx Fr Q 1",
- ixEthRxFreeQMCallback,
- (IxQMgrCallbackId) IX_ETH_PORT_1,
- IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */
- IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */
- FALSE, /**< Disable Q notification at startup */
- IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q_SOURCE, /**< Q Condition to drive callback */
- IX_QMGR_Q_WM_LEVEL0, /***< Q Low water mark */
- IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */
- },
-
- {
- IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q,
- "Eth Rx Fr Q 2",
- ixEthRxFreeQMCallback,
- (IxQMgrCallbackId) IX_ETH_PORT_2,
- IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */
- IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */
- FALSE, /**< Disable Q notification at startup */
- IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q_SOURCE, /**< Q Condition to drive callback */
- IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */
- IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */
- },
-#ifdef __ixp46X
- {
- IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q,
- "Eth Rx Fr Q 3",
- ixEthRxFreeQMCallback,
- (IxQMgrCallbackId) IX_ETH_PORT_3,
- IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */
- IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */
- FALSE, /**< Disable Q notification at startup */
- IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q_SOURCE, /**< Q Condition to drive callback */
- IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */
- IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */
- },
-#endif
- {
- IX_ETH_ACC_TX_FRAME_ENET0_Q,
- "Eth Tx Q 1",
- ixEthTxFrameQMCallback,
- (IxQMgrCallbackId) IX_ETH_PORT_1,
- IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */
- IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */
- FALSE, /**< Disable Q notification at startup */
- IX_ETH_ACC_TX_FRAME_ENET0_Q_SOURCE, /**< Q Condition to drive callback */
- IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */
- IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */
- },
-
- {
- IX_ETH_ACC_TX_FRAME_ENET1_Q,
- "Eth Tx Q 2",
- ixEthTxFrameQMCallback,
- (IxQMgrCallbackId) IX_ETH_PORT_2,
- IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */
- IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */
- FALSE, /**< Disable Q notification at startup */
- IX_ETH_ACC_TX_FRAME_ENET1_Q_SOURCE, /**< Q Condition to drive callback */
- IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */
- IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */
- },
-#ifdef __ixp46X
- {
- IX_ETH_ACC_TX_FRAME_ENET2_Q,
- "Eth Tx Q 3",
- ixEthTxFrameQMCallback,
- (IxQMgrCallbackId) IX_ETH_PORT_3,
- IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */
- IX_QMGR_Q_ENTRY_SIZE1, /** Queue Entry Sizes - all Q entries are single ord entries */
- FALSE, /** Disable Q notification at startup */
- IX_ETH_ACC_TX_FRAME_ENET2_Q_SOURCE, /** Q Condition to drive callback */
- IX_QMGR_Q_WM_LEVEL0, /* No queues use almost empty */
- IX_QMGR_Q_WM_LEVEL64, /** Q High water mark - needed used */
- },
-#endif
- {
- IX_ETH_ACC_TX_FRAME_DONE_ETH_Q,
- "Eth Tx Done Q",
- ixEthTxFrameDoneQMCallback,
- (IxQMgrCallbackId) 0,
- IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */
- IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */
- TRUE, /**< Enable Q notification at startup */
- IX_ETH_ACC_TX_FRAME_DONE_ETH_Q_SOURCE, /**< Q Condition to drive callback */
- IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */
- IX_QMGR_Q_WM_LEVEL2, /**< Q High water mark - needed by NPE */
- },
-
- { /* Null Termination entry
- */
- (IxQMgrQId)0,
- (char *) NULL,
- (IxQMgrCallback) NULL,
- (IxQMgrCallbackId) 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- }
-
-};
-
-/**
- *
- * @brief Data structure used to register & initialize the Queues
- *
- * The structure will be filled at run time depending on the NPE
- * image already loaded and the QoS configured in ethDB.
- *
- */
-IX_ETH_ACC_PRIVATE
-IxEthAccQregInfo ixEthAccQmgrRxQueuesInfo[IX_ETHACC_MAX_RX_QUEUES+1]=
-{
- { /* PlaceHolder for rx queues
- * depending on the QoS configured
- */
- (IxQMgrQId)0,
- (char *) NULL,
- (IxQMgrCallback) NULL,
- (IxQMgrCallbackId) 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- },
-
- { /* PlaceHolder for rx queues
- * depending on the QoS configured
- */
- (IxQMgrQId)0,
- (char *) NULL,
- (IxQMgrCallback) NULL,
- (IxQMgrCallbackId) 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- },
-
- { /* PlaceHolder for rx queues
- * depending on the QoS configured
- */
- (IxQMgrQId)0,
- (char *) NULL,
- (IxQMgrCallback) NULL,
- (IxQMgrCallbackId) 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- },
-
- { /* PlaceHolder for rx queues
- * depending on the QoS configured
- */
- (IxQMgrQId)0,
- (char *) NULL,
- (IxQMgrCallback) NULL,
- (IxQMgrCallbackId) 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- },
-
- { /* PlaceHolder for rx queues
- * depending on the QoS configured
- */
- (IxQMgrQId)0,
- (char *) NULL,
- (IxQMgrCallback) NULL,
- (IxQMgrCallbackId) 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- },
-
- { /* PlaceHolder for rx queues
- * depending on the QoS configured
- */
- (IxQMgrQId)0,
- (char *) NULL,
- (IxQMgrCallback) NULL,
- (IxQMgrCallbackId) 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- },
-
- { /* PlaceHolder for rx queues
- * depending on the QoS configured
- */
- (IxQMgrQId)0,
- (char *) NULL,
- (IxQMgrCallback) NULL,
- (IxQMgrCallbackId) 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- },
-
- { /* PlaceHolder for rx queues
- * depending on the QoS configured
- */
- (IxQMgrQId)0,
- (char *) NULL,
- (IxQMgrCallback) NULL,
- (IxQMgrCallbackId) 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- },
-
- { /* Null Termination entry
- */
- (IxQMgrQId)0,
- (char *) NULL,
- (IxQMgrCallback) NULL,
- (IxQMgrCallbackId) 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- }
-
-};
-
-/* forward declarations */
-IX_ETH_ACC_PRIVATE IxEthAccStatus
-ixEthAccQMgrQueueSetup(IxEthAccQregInfo *qInfoDes);
-
-/**
- * @fn ixEthAccQMgrQueueSetup(void)
- *
- * @brief Setup one queue and its event, and register the callback required
- * by this component to the QMgr
- *
- * @internal
- */
-IX_ETH_ACC_PRIVATE IxEthAccStatus
-ixEthAccQMgrQueueSetup(IxEthAccQregInfo *qInfoDes)
-{
- /*
- * Configure each Q.
- */
- if ( ixQMgrQConfig( qInfoDes->qName,
- qInfoDes->qId,
- qInfoDes->qSize,
- qInfoDes->qWords) != IX_SUCCESS)
- {
- return IX_ETH_ACC_FAIL;
- }
-
- if ( ixQMgrWatermarkSet( qInfoDes->qId,
- qInfoDes->AlmostEmptyThreshold,
- qInfoDes->AlmostFullThreshold
- ) != IX_SUCCESS)
- {
- return IX_ETH_ACC_FAIL;
- }
-
- /*
- * Set dispatcher priority.
- */
- if ( ixQMgrDispatcherPrioritySet( qInfoDes->qId,
- IX_ETH_ACC_QM_QUEUE_DISPATCH_PRIORITY)
- != IX_SUCCESS)
- {
- return IX_ETH_ACC_FAIL;
- }
-
- /*
- * Register callbacks for each Q.
- */
- if ( ixQMgrNotificationCallbackSet(qInfoDes->qId,
- qInfoDes->qCallback,
- qInfoDes->callbackTag)
- != IX_SUCCESS )
- {
- return IX_ETH_ACC_FAIL;
- }
-
- /*
- * Set notification condition for Q
- */
- if ( qInfoDes->qNotificationEnableAtStartup == TRUE )
- {
- if ( ixQMgrNotificationEnable(qInfoDes->qId,
- qInfoDes->qConditionSource)
- != IX_SUCCESS )
- {
- return IX_ETH_ACC_FAIL;
- }
- }
-
- return(IX_ETH_ACC_SUCCESS);
-}
-
-/**
- * @fn ixEthAccQMgrQueuesConfig(void)
- *
- * @brief Setup all the queues and register all callbacks required
- * by this component to the QMgr
- *
- * The RxFree queues, tx queues, rx queues are configured statically
- *
- * Rx queues configuration is driven by QoS setup.
- * Many Rx queues may be required when QoS is enabled (this depends
- * on IxEthDB setup and the images being downloaded). The configuration
- * of the rxQueues is done in many steps as follows:
- *
- * @li select all Rx queues as configured by ethDB for all ports
- * @li sort the queues by traffic class
- * @li build the priority dependency for all queues
- * @li fill the configuration for all rx queues
- * @li configure all statically configured queues
- * @li configure all dynamically configured queues
- *
- * @param none
- *
- * @return IxEthAccStatus
- *
- * @internal
- */
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccQMgrQueuesConfig(void)
-{
- struct
- {
- int npeCount;
- UINT32 npeId;
- IxQMgrQId qId;
- IxEthDBProperty trafficClass;
- } rxQueues[IX_ETHACC_MAX_RX_QUEUES];
-
- UINT32 rxQueue = 0;
- UINT32 rxQueueCount = 0;
- IxQMgrQId ixQId =IX_QMGR_MAX_NUM_QUEUES;
- IxEthDBStatus ixEthDBStatus = IX_ETH_DB_SUCCESS;
- IxEthDBPortId ixEthDbPortId = 0;
- IxEthAccPortId ixEthAccPortId = 0;
- UINT32 ixNpeId = 0;
- UINT32 ixHighestNpeId = 0;
- UINT32 sortIterations = 0;
- IxEthAccStatus ret = IX_ETH_ACC_SUCCESS;
- IxEthAccQregInfo *qInfoDes = NULL;
- IxEthDBProperty ixEthDBTrafficClass = IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY;
- IxEthDBPropertyType ixEthDBPropertyType = IX_ETH_DB_INTEGER_PROPERTY;
- UINT32 ixEthDBParameter = 0;
- BOOL completelySorted = FALSE;
-
- /* Fill the corspondance between ports and queues
- * This defines the mapping from port to queue Ids.
- */
-
- ixEthAccPortData[IX_ETH_PORT_1].ixEthAccRxData.rxFreeQueue
- = IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q;
- ixEthAccPortData[IX_ETH_PORT_2].ixEthAccRxData.rxFreeQueue
- = IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q;
-#ifdef __ixp46X
- ixEthAccPortData[IX_ETH_PORT_3].ixEthAccRxData.rxFreeQueue
- = IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q;
-#endif
- ixEthAccPortData[IX_ETH_PORT_1].ixEthAccTxData.txQueue
- = IX_ETH_ACC_TX_FRAME_ENET0_Q;
- ixEthAccPortData[IX_ETH_PORT_2].ixEthAccTxData.txQueue
- = IX_ETH_ACC_TX_FRAME_ENET1_Q;
-#ifdef __ixp46X
- ixEthAccPortData[IX_ETH_PORT_3].ixEthAccTxData.txQueue
- = IX_ETH_ACC_TX_FRAME_ENET2_Q;
-#endif
- /* Fill the corspondance between ports and NPEs
- * This defines the mapping from port to npeIds.
- */
-
- ixEthAccPortData[IX_ETH_PORT_1].npeId = IX_NPEMH_NPEID_NPEB;
- ixEthAccPortData[IX_ETH_PORT_2].npeId = IX_NPEMH_NPEID_NPEC;
-#ifdef __ixp46X
- ixEthAccPortData[IX_ETH_PORT_3].npeId = IX_NPEMH_NPEID_NPEA;
-#endif
- /* set the default rx scheduling discipline */
- ixEthAccDataInfo.schDiscipline = FIFO_NO_PRIORITY;
-
- /*
- * Queue Selection step:
- *
- * The following code selects all the queues and build
- * a temporary array which contains for each queue
- * - the queue Id,
- * - the highest traffic class (in case of many
- * priorities configured for the same queue on different
- * ports)
- * - the number of different Npes which are
- * configured to write to this queue.
- *
- * The output of this loop is a temporary array of RX queues
- * in any order.
- *
- */
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
- for (ixEthAccPortId = 0;
- (ixEthAccPortId < IX_ETH_ACC_NUMBER_OF_PORTS)
- && (ret == IX_ETH_ACC_SUCCESS);
- ixEthAccPortId++)
- {
- /* map between ethDb and ethAcc port Ids */
- ixEthDbPortId = (IxEthDBPortId)ixEthAccPortId;
-
- /* map between npeId and ethAcc port Ids */
- ixNpeId = IX_ETH_ACC_PORT_TO_NPE_ID(ixEthAccPortId);
-
- /* Iterate thru the different priorities */
- for (ixEthDBTrafficClass = IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY;
- ixEthDBTrafficClass <= IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY;
- ixEthDBTrafficClass++)
- {
- ixEthDBStatus = ixEthDBFeaturePropertyGet(
- ixEthDbPortId,
- IX_ETH_DB_VLAN_QOS,
- ixEthDBTrafficClass,
- &ixEthDBPropertyType,
- (void *)&ixEthDBParameter);
-
- if (ixEthDBStatus == IX_ETH_DB_SUCCESS)
- {
- /* This port and QoS class are mapped to
- * a RX queue.
- */
- if (ixEthDBPropertyType == IX_ETH_DB_INTEGER_PROPERTY)
- {
- /* remember the highest npe Id supporting ethernet */
- if (ixNpeId > ixHighestNpeId)
- {
- ixHighestNpeId = ixNpeId;
- }
-
- /* search the queue in the list of queues
- * already used by an other port or QoS
- */
- for (rxQueue = 0;
- rxQueue < rxQueueCount;
- rxQueue++)
- {
- if (rxQueues[rxQueue].qId == (IxQMgrQId)ixEthDBParameter)
- {
- /* found an existing setup, update the number of ports
- * for this queue if the port maps to
- * a different NPE.
- */
- if (rxQueues[rxQueue].npeId != ixNpeId)
- {
- rxQueues[rxQueue].npeCount++;
- rxQueues[rxQueue].npeId = ixNpeId;
- }
- /* get the highest traffic class for this queue */
- if (rxQueues[rxQueue].trafficClass > ixEthDBTrafficClass)
- {
- rxQueues[rxQueue].trafficClass = ixEthDBTrafficClass;
- }
- break;
- }
- }
- if (rxQueue == rxQueueCount)
- {
- /* new queue not found in the current list,
- * add a new entry.
- */
- IX_OSAL_ASSERT(rxQueueCount < IX_ETHACC_MAX_RX_QUEUES);
- rxQueues[rxQueueCount].qId = ixEthDBParameter;
- rxQueues[rxQueueCount].npeCount = 1;
- rxQueues[rxQueueCount].npeId = ixNpeId;
- rxQueues[rxQueueCount].trafficClass = ixEthDBTrafficClass;
- rxQueueCount++;
- }
- }
- else
- {
- /* unexpected property type (not Integer) */
- ret = IX_ETH_ACC_FAIL;
-
- IX_ETH_ACC_WARNING_LOG("ixEthAccQMgrQueuesConfig: unexpected property type returned by EthDB\n", 0, 0, 0, 0, 0, 0);
-
- /* no point to continue to iterate */
- break;
- }
- }
- else
- {
- /* No Rx queue configured for this port
- * and this traffic class. Do nothing.
- */
- }
- }
-
- /* notify EthDB that queue initialization is complete and traffic class allocation is frozen */
- ixEthDBFeaturePropertySet(ixEthDbPortId,
- IX_ETH_DB_VLAN_QOS,
- IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE,
- NULL /* ignored */);
- }
-
-#else
-
- ixNpeId = IX_ETH_ACC_PORT_TO_NPE_ID(ixEthAccPortId);
- rxQueues[0].qId = 4;
- rxQueues[0].npeCount = 1;
- rxQueues[0].npeId = ixNpeId;
- rxQueues[0].trafficClass = IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY;
- rxQueueCount++;
-
-#endif
-
- /* check there is at least 1 rx queue : there is no point
- * to continue if there is no rx queue configured
- */
- if ((rxQueueCount == 0) || (ret == IX_ETH_ACC_FAIL))
- {
- IX_ETH_ACC_WARNING_LOG("ixEthAccQMgrQueuesConfig: no queues configured, bailing out\n", 0, 0, 0, 0, 0, 0);
- return (IX_ETH_ACC_FAIL);
- }
-
- /* Queue sort step:
- *
- * Re-order the array of queues by decreasing traffic class
- * using a bubble sort. (trafficClass 0 is the lowest
- * priority traffic, trafficClass 7 is the highest priority traffic)
- *
- * Primary sort order is traffic class
- * Secondary sort order is npeId
- *
- * Note that a bubble sort algorithm is not very efficient when
- * the number of queues grows . However, this is not a very bad choice
- * considering the very small number of entries to sort. Also, bubble
- * sort is extremely fast when the list is already sorted.
- *
- * The output of this loop is a sorted array of queues.
- *
- */
- sortIterations = 0;
- do
- {
- sortIterations++;
- completelySorted = TRUE;
- for (rxQueue = 0;
- rxQueue < rxQueueCount - sortIterations;
- rxQueue++)
- {
- /* compare adjacent elements */
- if ((rxQueues[rxQueue].trafficClass <
- rxQueues[rxQueue+1].trafficClass)
- || ((rxQueues[rxQueue].trafficClass ==
- rxQueues[rxQueue+1].trafficClass)
- &&(rxQueues[rxQueue].npeId <
- rxQueues[rxQueue+1].npeId)))
- {
- /* swap adjacent elements */
- int npeCount = rxQueues[rxQueue].npeCount;
- UINT32 npeId = rxQueues[rxQueue].npeId;
- IxQMgrQId qId = rxQueues[rxQueue].qId;
- IxEthDBProperty trafficClass = rxQueues[rxQueue].trafficClass;
- rxQueues[rxQueue].npeCount = rxQueues[rxQueue+1].npeCount;
- rxQueues[rxQueue].npeId = rxQueues[rxQueue+1].npeId;
- rxQueues[rxQueue].qId = rxQueues[rxQueue+1].qId;
- rxQueues[rxQueue].trafficClass = rxQueues[rxQueue+1].trafficClass;
- rxQueues[rxQueue+1].npeCount = npeCount;
- rxQueues[rxQueue+1].npeId = npeId;
- rxQueues[rxQueue+1].qId = qId;
- rxQueues[rxQueue+1].trafficClass = trafficClass;
- completelySorted = FALSE;
- }
- }
- }
- while (!completelySorted);
-
- /* Queue traffic class list:
- *
- * Fill an array of rx queues linked by ascending traffic classes.
- *
- * If the queues are configured as follows
- * qId 6 -> traffic class 0 (lowest)
- * qId 7 -> traffic class 0
- * qId 8 -> traffic class 6
- * qId 12 -> traffic class 7 (highest)
- *
- * Then the output of this loop will be
- *
- * higherPriorityQueue[6] = 8
- * higherPriorityQueue[7] = 8
- * higherPriorityQueue[8] = 12
- * higherPriorityQueue[12] = Invalid queueId
- * higherPriorityQueue[...] = Invalid queueId
- *
- * Note that this queue ordering does not handle all possibilities
- * that could result from different rules associated with different
- * ports, and inconsistencies in the rules. In all cases, the
- * output of this algorithm is a simple linked list of queues,
- * without closed circuit.
-
- * This list is implemented as an array with invalid values initialized
- * with an "invalid" queue id which is the maximum number of queues.
- *
- */
-
- /*
- * Initialise the rx queue list.
- */
- for (rxQueue = 0; rxQueue < IX_QMGR_MAX_NUM_QUEUES; rxQueue++)
- {
- ixEthAccDataInfo.higherPriorityQueue[rxQueue] = IX_QMGR_MAX_NUM_QUEUES;
- }
-
- /* build the linked list for this NPE.
- */
- for (ixNpeId = 0;
- ixNpeId <= ixHighestNpeId;
- ixNpeId++)
- {
- /* iterate thru the sorted list of queues
- */
- ixQId = IX_QMGR_MAX_NUM_QUEUES;
- for (rxQueue = 0;
- rxQueue < rxQueueCount;
- rxQueue++)
- {
- if (rxQueues[rxQueue].npeId == ixNpeId)
- {
- ixEthAccDataInfo.higherPriorityQueue[rxQueues[rxQueue].qId] = ixQId;
- /* iterate thru queues with the same traffic class
- * than the current queue. (queues are ordered by descending
- * traffic classes and npeIds).
- */
- while ((rxQueue < rxQueueCount - 1)
- && (rxQueues[rxQueue].trafficClass
- == rxQueues[rxQueue+1].trafficClass)
- && (ixNpeId == rxQueues[rxQueue].npeId))
- {
- rxQueue++;
- ixEthAccDataInfo.higherPriorityQueue[rxQueues[rxQueue].qId] = ixQId;
- }
- ixQId = rxQueues[rxQueue].qId;
- }
- }
- }
-
- /* point on the first dynamic queue description */
- qInfoDes = ixEthAccQmgrRxQueuesInfo;
-
- /* update the list of queues with the rx queues */
- for (rxQueue = 0;
- (rxQueue < rxQueueCount) && (ret == IX_ETH_ACC_SUCCESS);
- rxQueue++)
- {
- /* Don't utilize more than IX_ETHACC_MAX_LARGE_RX_QUEUES queues
- * with the full 128 entries. For the lower priority queues, use
- * a smaller number of entries. This ensures queue resources
- * remain available for other components.
- */
- if( (rxQueueCount > IX_ETHACC_MAX_LARGE_RX_QUEUES) &&
- (rxQueue < rxQueueCount - IX_ETHACC_MAX_LARGE_RX_QUEUES) )
- {
- /* add the small RX Queue setup template to the list of queues */
- memcpy(qInfoDes, &ixEthAccQmgrRxSmallTemplate, sizeof(*qInfoDes));
- } else {
- /* add the default RX Queue setup template to the list of queues */
- memcpy(qInfoDes, &ixEthAccQmgrRxDefaultTemplate, sizeof(*qInfoDes));
- }
-
- /* setup the RxQueue ID */
- qInfoDes->qId = rxQueues[rxQueue].qId;
-
- /* setup the RxQueue watermark level
- *
- * Each queue can be filled by many NPEs. To avoid the
- * NPEs to write to a full queue, need to set the
- * high watermark level for nearly full condition.
- * (the high watermark level are a power of 2
- * starting from the top of the queue)
- *
- * Number of watermark
- * ports level
- * 1 0
- * 2 1
- * 3 2
- * 4 4
- * 5 4
- * 6 8
- * n approx. 2**ceil(log2(n))
- */
- if (rxQueues[rxQueue].npeCount == 1)
- {
- qInfoDes->AlmostFullThreshold = IX_QMGR_Q_WM_LEVEL0;
- }
- else if (rxQueues[rxQueue].npeCount == 2)
- {
- qInfoDes->AlmostFullThreshold = IX_QMGR_Q_WM_LEVEL1;
- }
- else if (rxQueues[rxQueue].npeCount == 3)
- {
- qInfoDes->AlmostFullThreshold = IX_QMGR_Q_WM_LEVEL2;
- }
- else
- {
- /* reach the maximum number for CSR 2.0 */
- IX_ETH_ACC_WARNING_LOG("ixEthAccQMgrQueuesConfig: maximum number of NPEs per queue reached, bailing out\n", 0, 0, 0, 0, 0, 0);
- ret = IX_ETH_ACC_FAIL;
- break;
- }
-
- /* move to next queue entry */
- ++qInfoDes;
- }
-
- /* configure the static list (RxFree, Tx and TxDone queues) */
- for (qInfoDes = ixEthAccQmgrStaticInfo;
- (qInfoDes->qCallback != (IxQMgrCallback) NULL )
- && (ret == IX_ETH_ACC_SUCCESS);
- ++qInfoDes)
- {
- ret = ixEthAccQMgrQueueSetup(qInfoDes);
- }
-
- /* configure the dynamic list (Rx queues) */
- for (qInfoDes = ixEthAccQmgrRxQueuesInfo;
- (qInfoDes->qCallback != (IxQMgrCallback) NULL )
- && (ret == IX_ETH_ACC_SUCCESS);
- ++qInfoDes)
- {
- ret = ixEthAccQMgrQueueSetup(qInfoDes);
- }
-
- return(ret);
-}
-
-/**
- * @fn ixEthAccQMgrRxQEntryGet(UINT32 *rxQueueEntries)
- *
- * @brief Add and return the total number of entries in all Rx queues
- *
- * @param UINT32 rxQueueEntries[in] number of entries in all queues
- *
- * @return void
- *
- * @note Rx queues configuration is driven by Qos Setup. There is a
- * variable number of rx queues which are set at initialisation.
- *
- * @internal
- */
-IX_ETH_ACC_PUBLIC
-void ixEthAccQMgrRxQEntryGet(UINT32 *numRxQueueEntries)
-{
- UINT32 rxQueueLevel;
- IxEthAccQregInfo *qInfoDes;;
-
- *numRxQueueEntries = 0;
-
- /* iterate thru rx queues */
- for (qInfoDes = ixEthAccQmgrRxQueuesInfo;
- qInfoDes->qCallback != (IxQMgrCallback)NULL;
- ++qInfoDes)
- {
- /* retrieve the rx queue level */
- rxQueueLevel = 0;
- ixQMgrQNumEntriesGet(qInfoDes->qId, &rxQueueLevel);
- (*numRxQueueEntries) += rxQueueLevel;
- }
-}
-
-/**
- * @fn ixEthAccQMgrRxCallbacksRegister(IxQMgrCallback ixQMgrCallback)
- *
- * @brief Change the callback registered to all rx queues.
- *
- * @param IxQMgrCallback ixQMgrCallback[in] QMgr callback to register
- *
- * @return IxEthAccStatus
- *
- * @note The user may decide to use different Rx mechanisms
- * (e.g. receive many frames at the same time , or receive
- * one frame at a time, depending on the overall application
- * performances). A different QMgr callback is registered. This
- * way, there is no excessive pointer checks in the datapath.
- *
- * @internal
- */
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccQMgrRxCallbacksRegister(IxQMgrCallback ixQMgrCallback)
-{
- IxEthAccQregInfo *qInfoDes;
- IxEthAccStatus ret = IX_ETH_ACC_SUCCESS;
-
- /* parameter check */
- if (NULL == ixQMgrCallback)
- {
- ret = IX_ETH_ACC_FAIL;
- }
-
- /* iterate thru rx queues */
- for (qInfoDes = ixEthAccQmgrRxQueuesInfo;
- (qInfoDes->qCallback != (IxQMgrCallback) NULL )
- && (ret == IX_ETH_ACC_SUCCESS);
- ++qInfoDes)
- {
- /* register the rx callback for all queues */
- if (ixQMgrNotificationCallbackSet(qInfoDes->qId,
- ixQMgrCallback,
- qInfoDes->callbackTag
- ) != IX_SUCCESS)
- {
- ret = IX_ETH_ACC_FAIL;
- }
- }
- return(ret);
-}
-
-/**
- * @fn ixEthAccSingleEthNpeCheck(IxEthAccPortId portId)
- *
- * @brief Check the npe exists for this port
- *
- * @param IxEthAccPortId portId[in] port
- *
- * @return IxEthAccStatus
- *
- * @internal
- */
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccSingleEthNpeCheck(IxEthAccPortId portId)
-{
-
- /* If not IXP42X A0 stepping, proceed to check for existence of coprocessors */
- if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
- (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
- || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
- {
- if ((IX_ETH_PORT_1 == portId) &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) ==
- IX_FEATURE_CTRL_COMPONENT_ENABLED))
- {
- return IX_ETH_ACC_SUCCESS;
- }
-
- if ((IX_ETH_PORT_2 == portId) &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) ==
- IX_FEATURE_CTRL_COMPONENT_ENABLED))
- {
- return IX_ETH_ACC_SUCCESS;
- }
-
- if ((IX_ETH_PORT_3 == portId) &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA_ETH) ==
- IX_FEATURE_CTRL_COMPONENT_ENABLED))
- {
- return IX_ETH_ACC_SUCCESS;
- }
-
- return IX_ETH_ACC_FAIL;
- }
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-/**
- * @fn ixEthAccStatsShow(void)
- *
- * @brief Displays all EthAcc stats
- *
- * @return void
- *
- */
-void ixEthAccStatsShow(IxEthAccPortId portId)
-{
- ixEthAccMdioShow();
-
- printf("\nPort %u\nUnicast MAC : ", portId);
- ixEthAccPortUnicastAddressShow(portId);
- ixEthAccPortMulticastAddressShow(portId);
- printf("\n");
-
- ixEthAccDataPlaneShow();
-}
-
-
-
+++ /dev/null
-/**
- * @file IxEthAccControlInterface.c
- *
- * @author Intel Corporation
- * @date
- *
- * @brief IX_ETH_ACC_PUBLIC wrappers for control plane functions
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-#include "IxEthAcc.h"
-#include "IxEthAcc_p.h"
-
-PUBLIC IxOsalMutex ixEthAccControlInterfaceMutex;
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortEnable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- printf("EthAcc: (Mac) cannot enable port %d, service not initialized\n", portId);
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortEnablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortDisable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- /* check the context is iinitialized */
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortDisablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortEnabledQuery(IxEthAccPortId portId, BOOL *enabled)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortEnabledQueryPriv(portId, enabled);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortPromiscuousModeClear(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortPromiscuousModeClearPriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortPromiscuousModeSet(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortPromiscuousModeSetPriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortUnicastMacAddressSet(IxEthAccPortId portId, IxEthAccMacAddr *macAddr)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortUnicastMacAddressSetPriv(portId, macAddr);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortUnicastMacAddressGet(IxEthAccPortId portId, IxEthAccMacAddr *macAddr)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortUnicastMacAddressGetPriv(portId, macAddr);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressJoin(IxEthAccPortId portId, IxEthAccMacAddr *macAddr)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortMulticastAddressJoinPriv(portId, macAddr);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressJoinAll(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortMulticastAddressJoinAllPriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressLeave(IxEthAccPortId portId, IxEthAccMacAddr *macAddr)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortMulticastAddressLeavePriv(portId, macAddr);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressLeaveAll(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortMulticastAddressLeaveAllPriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortUnicastAddressShow(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortUnicastAddressShowPriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC void
-ixEthAccPortMulticastAddressShow(IxEthAccPortId portId)
-{
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return;
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- ixEthAccPortMulticastAddressShowPriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortDuplexModeSet(IxEthAccPortId portId, IxEthAccDuplexMode mode)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortDuplexModeSetPriv(portId, mode);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortDuplexModeGet(IxEthAccPortId portId, IxEthAccDuplexMode *mode)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortDuplexModeGetPriv(portId, mode);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendPaddingEnable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortTxFrameAppendPaddingEnablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendPaddingDisable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortTxFrameAppendPaddingDisablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendFCSEnable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortTxFrameAppendFCSEnablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendFCSDisable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortTxFrameAppendFCSDisablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortRxFrameAppendFCSEnable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortRxFrameAppendFCSEnablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortRxFrameAppendFCSDisable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortRxFrameAppendFCSDisablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccTxSchedulingDisciplineSet(IxEthAccPortId portId, IxEthAccSchedulerDiscipline sched)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccTxSchedulingDisciplineSetPriv(portId, sched);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccRxSchedulingDisciplineSet(IxEthAccSchedulerDiscipline sched)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccRxSchedulingDisciplineSetPriv(sched);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortNpeLoopbackEnable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccNpeLoopbackEnablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortTxEnable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortTxEnablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortRxEnable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortRxEnablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortNpeLoopbackDisable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccNpeLoopbackDisablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortTxDisable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortTxDisablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortRxDisable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortRxDisablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortMacReset(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortMacResetPriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
+++ /dev/null
-/**
- * @file IxEthDataPlane.c
- *
- * @author Intel Corporation
- * @date 12-Feb-2002
- *
- * @brief This file contains the implementation of the IXPxxx
- * Ethernet Access Data plane component
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxNpeMh.h"
-#include "IxEthAcc.h"
-#include "IxEthDB.h"
-#include "IxOsal.h"
-#include "IxEthDBPortDefs.h"
-#include "IxFeatureCtrl.h"
-#include "IxEthAcc_p.h"
-#include "IxEthAccQueueAssign_p.h"
-
-extern PUBLIC IxEthAccMacState ixEthAccMacState[];
-extern PUBLIC UINT32 ixEthAccNewSrcMask;
-
-/**
- * private functions prototype
- */
-PRIVATE IX_OSAL_MBUF *
-ixEthAccEntryFromQConvert(UINT32 qEntry, UINT32 mask);
-
-PRIVATE UINT32
-ixEthAccMbufRxQPrepare(IX_OSAL_MBUF *mbuf);
-
-PRIVATE UINT32
-ixEthAccMbufTxQPrepare(IX_OSAL_MBUF *mbuf);
-
-PRIVATE IxEthAccStatus
-ixEthAccTxSwQHighestPriorityGet(IxEthAccPortId portId,
- IxEthAccTxPriority *priorityPtr);
-
-PRIVATE IxEthAccStatus
-ixEthAccTxFromSwQ(IxEthAccPortId portId,
- IxEthAccTxPriority priority);
-
-PRIVATE IxEthAccStatus
-ixEthAccRxFreeFromSwQ(IxEthAccPortId portId);
-
-PRIVATE void
-ixEthAccMbufFromTxQ(IX_OSAL_MBUF *mbuf);
-
-PRIVATE void
-ixEthAccMbufFromRxQ(IX_OSAL_MBUF *mbuf);
-
-PRIVATE IX_STATUS
-ixEthAccQmgrLockTxWrite(IxEthAccPortId portId,
- UINT32 qBuffer);
-
-PRIVATE IX_STATUS
-ixEthAccQmgrLockRxWrite(IxEthAccPortId portId,
- UINT32 qBuffer);
-
-PRIVATE IX_STATUS
-ixEthAccQmgrTxWrite(IxEthAccPortId portId,
- UINT32 qBuffer,
- UINT32 priority);
-
-/**
- * @addtogroup IxEthAccPri
- *@{
- */
-
-/* increment a counter only when stats are enabled */
-#define TX_STATS_INC(port,field) \
- IX_ETH_ACC_STATS_INC(ixEthAccPortData[port].ixEthAccTxData.stats.field)
-#define RX_STATS_INC(port,field) \
- IX_ETH_ACC_STATS_INC(ixEthAccPortData[port].ixEthAccRxData.stats.field)
-
-/* always increment the counter (mainly used for unexpected errors) */
-#define TX_INC(port,field) \
- ixEthAccPortData[port].ixEthAccTxData.stats.field++
-#define RX_INC(port,field) \
- ixEthAccPortData[port].ixEthAccRxData.stats.field++
-
-PRIVATE IxEthAccDataPlaneStats ixEthAccDataStats;
-
-extern IxEthAccPortDataInfo ixEthAccPortData[];
-extern IxEthAccInfo ixEthAccDataInfo;
-
-PRIVATE IxOsalFastMutex txWriteMutex[IX_ETH_ACC_NUMBER_OF_PORTS];
-PRIVATE IxOsalFastMutex rxWriteMutex[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-/**
- *
- * @brief Mbuf header conversion macros : they implement the
- * different conversions using a temporary value. They also double-check
- * that the parameters can be converted to/from NPE format.
- *
- */
-#if defined(__wince) && !defined(IN_KERNEL)
-#define PTR_VIRT2NPE(ptrSrc,dst) \
- do { UINT32 temp; \
- IX_OSAL_ENSURE(sizeof(ptrSrc) == sizeof(UINT32), "Wrong parameter type"); \
- IX_OSAL_ENSURE(sizeof(dst) == sizeof(UINT32), "Wrong parameter type"); \
- temp = (UINT32)IX_OSAL_MBUF_MBUF_VIRTUAL_TO_PHYSICAL_TRANSLATION((IX_OSAL_MBUF*)ptrSrc); \
- (dst) = IX_OSAL_SWAP_BE_SHARED_LONG(temp); } \
- while(0)
-
-#define PTR_NPE2VIRT(type,src,ptrDst) \
- do { void *temp; \
- IX_OSAL_ENSURE(sizeof(type) == sizeof(UINT32), "Wrong parameter type"); \
- IX_OSAL_ENSURE(sizeof(src) == sizeof(UINT32), "Wrong parameter type"); \
- IX_OSAL_ENSURE(sizeof(ptrDst) == sizeof(UINT32), "Wrong parameter type"); \
- temp = (void *)IX_OSAL_SWAP_BE_SHARED_LONG(src); \
- (ptrDst) = (type)IX_OSAL_MBUF_MBUF_PHYSICAL_TO_VIRTUAL_TRANSLATION(temp); } \
- while(0)
-#else
-#define PTR_VIRT2NPE(ptrSrc,dst) \
- do { UINT32 temp; \
- IX_OSAL_ENSURE(sizeof(ptrSrc) == sizeof(UINT32), "Wrong parameter type"); \
- IX_OSAL_ENSURE(sizeof(dst) == sizeof(UINT32), "Wrong parameter type"); \
- temp = (UINT32)IX_OSAL_MMU_VIRT_TO_PHYS(ptrSrc); \
- (dst) = IX_OSAL_SWAP_BE_SHARED_LONG(temp); } \
- while(0)
-
-#define PTR_NPE2VIRT(type,src,ptrDst) \
- do { void *temp; \
- IX_OSAL_ENSURE(sizeof(type) == sizeof(UINT32), "Wrong parameter type"); \
- IX_OSAL_ENSURE(sizeof(src) == sizeof(UINT32), "Wrong parameter type"); \
- IX_OSAL_ENSURE(sizeof(ptrDst) == sizeof(UINT32), "Wrong parameter type"); \
- temp = (void *)IX_OSAL_SWAP_BE_SHARED_LONG(src); \
- (ptrDst) = (type)IX_OSAL_MMU_PHYS_TO_VIRT(temp); } \
- while(0)
-#endif
-
-/**
- *
- * @brief Mbuf payload pointer conversion macros : Wince has its own
- * method to convert the buffer pointers
- */
-#if defined(__wince) && !defined(IN_KERNEL)
-#define DATAPTR_VIRT2NPE(ptrSrc,dst) \
- do { UINT32 temp; \
- temp = (UINT32)IX_OSAL_MBUF_DATA_VIRTUAL_TO_PHYSICAL_TRANSLATION(ptrSrc); \
- (dst) = IX_OSAL_SWAP_BE_SHARED_LONG(temp); } \
- while(0)
-
-#else
-#define DATAPTR_VIRT2NPE(ptrSrc,dst) PTR_VIRT2NPE(IX_OSAL_MBUF_MDATA(ptrSrc),dst)
-#endif
-
-
-/* Flush the shared part of the mbuf header */
-#define IX_ETHACC_NE_CACHE_FLUSH(mbufPtr) \
- do { \
- IX_OSAL_CACHE_FLUSH(IX_ETHACC_NE_SHARED(mbufPtr), \
- sizeof(IxEthAccNe)); \
- } \
- while(0)
-
-/* Invalidate the shared part of the mbuf header */
-#define IX_ETHACC_NE_CACHE_INVALIDATE(mbufPtr) \
- do { \
- IX_OSAL_CACHE_INVALIDATE(IX_ETHACC_NE_SHARED(mbufPtr), \
- sizeof(IxEthAccNe)); \
- } \
- while(0)
-
-/* Preload one cache line (shared mbuf headers are aligned
- * and their size is 1 cache line)
- *
- * IX_OSAL_CACHED is defined when the mbuf headers are
- * allocated from cached memory.
- *
- * Other processor on emulation environment may not implement
- * preload function
- */
-#ifdef IX_OSAL_CACHED
- #if (CPU!=SIMSPARCSOLARIS) && !defined (__wince)
- #define IX_ACC_DATA_CACHE_PRELOAD(ptr) \
- do { /* preload a cache line (Xscale Processor) */ \
- __asm__ (" pld [%0]\n": : "r" (ptr)); \
- } \
- while(0)
- #else
- /* preload not implemented on different processor */
- #define IX_ACC_DATA_CACHE_PRELOAD(mbufPtr) \
- do { /* nothing */ } while (0)
- #endif
-#else
- /* preload not needed if cache is not enabled */
- #define IX_ACC_DATA_CACHE_PRELOAD(mbufPtr) \
- do { /* nothing */ } while (0)
-#endif
-
-/**
- *
- * @brief function to retrieve the correct pointer from
- * a queue entry posted by the NPE
- *
- * @param qEntry : entry from qmgr queue
- * mask : applicable mask for this queue
- * (4 most significant bits are used for additional informations)
- *
- * @return IX_OSAL_MBUF * pointer to mbuf header
- *
- * @internal
- */
-PRIVATE IX_OSAL_MBUF *
-ixEthAccEntryFromQConvert(UINT32 qEntry, UINT32 mask)
-{
- IX_OSAL_MBUF *mbufPtr;
-
- if (qEntry != 0)
- {
- /* mask NPE bits (e.g. priority, port ...) */
- qEntry &= mask;
-
-#if IX_ACC_DRAM_PHYS_OFFSET != 0
- /* restore the original address pointer (if PHYS_OFFSET is not 0) */
- qEntry |= (IX_ACC_DRAM_PHYS_OFFSET & ~IX_ETHNPE_QM_Q_RXENET_ADDR_MASK);
-#endif
- /* get the mbuf pointer address from the npe-shared address */
- qEntry -= offsetof(IX_OSAL_MBUF,ix_ne);
-
- /* phys2virt mbuf */
- mbufPtr = (IX_OSAL_MBUF *)IX_OSAL_MMU_PHYS_TO_VIRT(qEntry);
-
- /* preload the cacheline shared with NPE */
- IX_ACC_DATA_CACHE_PRELOAD(IX_ETHACC_NE_SHARED(mbufPtr));
-
- /* preload the cacheline used by xscale */
- IX_ACC_DATA_CACHE_PRELOAD(mbufPtr);
- }
- else
- {
- mbufPtr = NULL;
- }
-
- return mbufPtr;
-}
-
-/* Convert the mbuf header for NPE transmission */
-PRIVATE UINT32
-ixEthAccMbufTxQPrepare(IX_OSAL_MBUF *mbuf)
-{
- UINT32 qbuf;
- UINT32 len;
-
- /* endianess swap for tci and flags
- note: this is done only once, even for chained buffers */
- IX_ETHACC_NE_FLAGS(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_FLAGS(mbuf));
- IX_ETHACC_NE_VLANTCI(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_VLANTCI(mbuf));
-
- /* test for unchained mbufs */
- if (IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mbuf) == NULL)
- {
- /* "best case" scenario : unchained mbufs */
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedTxMBufs);
-
- /* payload pointer conversion */
- DATAPTR_VIRT2NPE(mbuf, IX_ETHACC_NE_DATA(mbuf));
-
- /* unchained mbufs : the frame length is the mbuf length
- * and the 2 identical lengths are stored in the same
- * word.
- */
- len = IX_OSAL_MBUF_MLEN(mbuf);
-
- /* set the length in both length and pktLen 16-bits fields */
- len |= (len << IX_ETHNPE_ACC_LENGTH_OFFSET);
- IX_ETHACC_NE_LEN(mbuf) = IX_OSAL_SWAP_BE_SHARED_LONG(len);
-
- /* unchained mbufs : next contains 0 */
- IX_ETHACC_NE_NEXT(mbuf) = 0;
-
- /* flush shared header after all address conversions */
- IX_ETHACC_NE_CACHE_FLUSH(mbuf);
- }
- else
- {
- /* chained mbufs */
- IX_OSAL_MBUF *ptr = mbuf;
- IX_OSAL_MBUF *nextPtr;
- UINT32 frmLen;
-
- /* get the frame length from the header of the first buffer */
- frmLen = IX_OSAL_MBUF_PKT_LEN(mbuf);
-
- do
- {
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedTxMBufs);
-
- /* payload pointer */
- DATAPTR_VIRT2NPE(ptr,IX_ETHACC_NE_DATA(ptr));
- /* Buffer length and frame length are stored in the same word */
- len = IX_OSAL_MBUF_MLEN(ptr);
- len = frmLen | (len << IX_ETHNPE_ACC_LENGTH_OFFSET);
- IX_ETHACC_NE_LEN(ptr) = IX_OSAL_SWAP_BE_SHARED_LONG(len);
-
- /* get the virtual next chain pointer */
- nextPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr);
- if (nextPtr != NULL)
- {
- /* shared pointer of the next buffer is chained */
- PTR_VIRT2NPE(IX_ETHACC_NE_SHARED(nextPtr),
- IX_ETHACC_NE_NEXT(ptr));
- }
- else
- {
- IX_ETHACC_NE_NEXT(ptr) = 0;
- }
-
- /* flush shared header after all address conversions */
- IX_ETHACC_NE_CACHE_FLUSH(ptr);
-
- /* move to next buffer */
- ptr = nextPtr;
-
- /* the frame length field is set only in the first buffer
- * and is zeroed in the next buffers
- */
- frmLen = 0;
- }
- while(ptr != NULL);
-
- }
-
- /* virt2phys mbuf itself */
- qbuf = (UINT32)IX_OSAL_MMU_VIRT_TO_PHYS(
- IX_ETHACC_NE_SHARED(mbuf));
-
- /* Ensure the bits which are reserved to exchange information with
- * the NPE are cleared
- *
- * If the mbuf address is not correctly aligned, or from an
- * incompatible memory range, there is no point to continue
- */
- IX_OSAL_ENSURE(((qbuf & ~IX_ETHNPE_QM_Q_TXENET_ADDR_MASK) == 0),
- "Invalid address range");
-
- return qbuf;
-}
-
-/* Convert the mbuf header for NPE reception */
-PRIVATE UINT32
-ixEthAccMbufRxQPrepare(IX_OSAL_MBUF *mbuf)
-{
- UINT32 len;
- UINT32 qbuf;
-
- if (IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mbuf) == NULL)
- {
- /* "best case" scenario : unchained mbufs */
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedRxFreeMBufs);
-
- /* unchained mbufs : payload pointer */
- DATAPTR_VIRT2NPE(mbuf, IX_ETHACC_NE_DATA(mbuf));
-
- /* unchained mbufs : set the buffer length
- * and the frame length field is zeroed
- */
- len = (IX_OSAL_MBUF_MLEN(mbuf) << IX_ETHNPE_ACC_LENGTH_OFFSET);
- IX_ETHACC_NE_LEN(mbuf) = IX_OSAL_SWAP_BE_SHARED_LONG(len);
-
- /* unchained mbufs : next pointer is null */
- IX_ETHACC_NE_NEXT(mbuf) = 0;
-
- /* flush shared header after all address conversions */
- IX_ETHACC_NE_CACHE_FLUSH(mbuf);
-
- /* remove shared header cache line */
- IX_ETHACC_NE_CACHE_INVALIDATE(mbuf);
- }
- else
- {
- /* chained mbufs */
- IX_OSAL_MBUF *ptr = mbuf;
- IX_OSAL_MBUF *nextPtr;
-
- do
- {
- /* chained mbufs */
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedRxFreeMBufs);
-
- /* we must save virtual next chain pointer */
- nextPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr);
-
- if (nextPtr != NULL)
- {
- /* chaining pointer for NPE */
- PTR_VIRT2NPE(IX_ETHACC_NE_SHARED(nextPtr),
- IX_ETHACC_NE_NEXT(ptr));
- }
- else
- {
- IX_ETHACC_NE_NEXT(ptr) = 0;
- }
-
- /* payload pointer */
- DATAPTR_VIRT2NPE(ptr,IX_ETHACC_NE_DATA(ptr));
-
- /* buffer length */
- len = (IX_OSAL_MBUF_MLEN(ptr) << IX_ETHNPE_ACC_LENGTH_OFFSET);
- IX_ETHACC_NE_LEN(ptr) = IX_OSAL_SWAP_BE_SHARED_LONG(len);
-
- /* flush shared header after all address conversions */
- IX_ETHACC_NE_CACHE_FLUSH(ptr);
-
- /* remove shared header cache line */
- IX_ETHACC_NE_CACHE_INVALIDATE(ptr);
-
- /* next mbuf in the chain */
- ptr = nextPtr;
- }
- while(ptr != NULL);
- }
-
- /* virt2phys mbuf itself */
- qbuf = (UINT32)IX_OSAL_MMU_VIRT_TO_PHYS(
- IX_ETHACC_NE_SHARED(mbuf));
-
- /* Ensure the bits which are reserved to exchange information with
- * the NPE are cleared
- *
- * If the mbuf address is not correctly aligned, or from an
- * incompatible memory range, there is no point to continue
- */
- IX_OSAL_ENSURE(((qbuf & ~IX_ETHNPE_QM_Q_RXENET_ADDR_MASK) == 0),
- "Invalid address range");
-
- return qbuf;
-}
-
-/* Convert the mbuf header after NPE transmission
- * Since there is nothing changed by the NPE, there is no need
- * to process anything but the update of internal stats
- * when they are enabled
-*/
-PRIVATE void
-ixEthAccMbufFromTxQ(IX_OSAL_MBUF *mbuf)
-{
-#ifndef NDEBUG
- /* test for unchained mbufs */
- if (IX_ETHACC_NE_NEXT(mbuf) == 0)
- {
- /* unchained mbufs : update the stats */
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedTxDoneMBufs);
- }
- else
- {
- /* chained mbufs : walk the chain and update the stats */
- IX_OSAL_MBUF *ptr = mbuf;
-
- do
- {
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedTxDoneMBufs);
- ptr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr);
- }
- while (ptr != NULL);
- }
-#endif
-}
-
-/* Convert the mbuf header after NPE reception */
-PRIVATE void
-ixEthAccMbufFromRxQ(IX_OSAL_MBUF *mbuf)
-{
- UINT32 len;
-
- /* endianess swap for tci and flags
- note: this is done only once, even for chained buffers */
- IX_ETHACC_NE_FLAGS(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_FLAGS(mbuf));
- IX_ETHACC_NE_VLANTCI(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_VLANTCI(mbuf));
-
- /* test for unchained mbufs */
- if (IX_ETHACC_NE_NEXT(mbuf) == 0)
- {
- /* unchained mbufs */
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedRxMBufs);
-
- /* get the frame length. it is the same than the buffer length */
- len = IX_OSAL_SWAP_BE_SHARED_LONG(IX_ETHACC_NE_LEN(mbuf));
- len &= IX_ETHNPE_ACC_PKTLENGTH_MASK;
- IX_OSAL_MBUF_PKT_LEN(mbuf) = IX_OSAL_MBUF_MLEN(mbuf) = len;
-
- /* clears the next packet field */
- IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mbuf) = NULL;
- }
- else
- {
- IX_OSAL_MBUF *ptr = mbuf;
- IX_OSAL_MBUF *nextPtr;
- UINT32 frmLen;
-
- /* convert the frame length */
- frmLen = IX_OSAL_SWAP_BE_SHARED_LONG(IX_ETHACC_NE_LEN(mbuf));
- IX_OSAL_MBUF_PKT_LEN(mbuf) = (frmLen & IX_ETHNPE_ACC_PKTLENGTH_MASK);
-
- /* chained mbufs */
- do
- {
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedRxMBufs);
-
- /* convert the length */
- len = IX_OSAL_SWAP_BE_SHARED_LONG(IX_ETHACC_NE_LEN(ptr));
- IX_OSAL_MBUF_MLEN(ptr) = (len >> IX_ETHNPE_ACC_LENGTH_OFFSET);
-
- /* get the next pointer */
- PTR_NPE2VIRT(IX_OSAL_MBUF *,IX_ETHACC_NE_NEXT(ptr), nextPtr);
- if (nextPtr != NULL)
- {
- nextPtr = (IX_OSAL_MBUF *)((UINT8 *)nextPtr - offsetof(IX_OSAL_MBUF,ix_ne));
- }
- /* set the next pointer */
- IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr) = nextPtr;
-
- /* move to the next buffer */
- ptr = nextPtr;
- }
- while (ptr != NULL);
- }
-}
-
-/* write to qmgr if possible and report an overflow if not possible
- * Use a fast lock to protect the queue write.
- * This way, the tx feature is reentrant.
- */
-PRIVATE IX_STATUS
-ixEthAccQmgrLockTxWrite(IxEthAccPortId portId, UINT32 qBuffer)
-{
- IX_STATUS qStatus;
- if (ixOsalFastMutexTryLock(&txWriteMutex[portId]) == IX_SUCCESS)
- {
- qStatus = ixQMgrQWrite(
- IX_ETH_ACC_PORT_TO_TX_Q_ID(portId),
- &qBuffer);
-#ifndef NDEBUG
- if (qStatus != IX_SUCCESS)
- {
- TX_STATS_INC(portId, txOverflow);
- }
-#endif
- ixOsalFastMutexUnlock(&txWriteMutex[portId]);
- }
- else
- {
- TX_STATS_INC(portId, txLock);
- qStatus = IX_QMGR_Q_OVERFLOW;
- }
- return qStatus;
-}
-
-/* write to qmgr if possible and report an overflow if not possible
- * Use a fast lock to protect the queue write.
- * This way, the Rx feature is reentrant.
- */
-PRIVATE IX_STATUS
-ixEthAccQmgrLockRxWrite(IxEthAccPortId portId, UINT32 qBuffer)
-{
- IX_STATUS qStatus;
- if (ixOsalFastMutexTryLock(&rxWriteMutex[portId]) == IX_SUCCESS)
- {
- qStatus = ixQMgrQWrite(
- IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId),
- &qBuffer);
-#ifndef NDEBUG
- if (qStatus != IX_SUCCESS)
- {
- RX_STATS_INC(portId, rxFreeOverflow);
- }
-#endif
- ixOsalFastMutexUnlock(&rxWriteMutex[portId]);
- }
- else
- {
- RX_STATS_INC(portId, rxFreeLock);
- qStatus = IX_QMGR_Q_OVERFLOW;
- }
- return qStatus;
-}
-
-/*
- * Set the priority and write to a qmgr queue.
- */
-PRIVATE IX_STATUS
-ixEthAccQmgrTxWrite(IxEthAccPortId portId, UINT32 qBuffer, UINT32 priority)
-{
- /* fill the priority field */
- qBuffer |= (priority << IX_ETHNPE_QM_Q_FIELD_PRIOR_R);
-
- return ixEthAccQmgrLockTxWrite(portId, qBuffer);
-}
-
-/**
- *
- * @brief This function will discover the highest priority S/W Tx Q that
- * has entries in it
- *
- * @param portId - (in) the id of the port whose S/W Tx queues are to be searched
- * priorityPtr - (out) the priority of the highest priority occupied q will be written
- * here
- *
- * @return IX_ETH_ACC_SUCCESS if an occupied Q is found
- * IX_ETH_ACC_FAIL if no Q has entries
- *
- * @internal
- */
-PRIVATE IxEthAccStatus
-ixEthAccTxSwQHighestPriorityGet(IxEthAccPortId portId,
- IxEthAccTxPriority *priorityPtr)
-{
- if (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline
- == FIFO_NO_PRIORITY)
- {
- if(IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId].
- ixEthAccTxData.txQ[IX_ETH_ACC_TX_DEFAULT_PRIORITY]))
- {
- return IX_ETH_ACC_FAIL;
- }
- else
- {
- *priorityPtr = IX_ETH_ACC_TX_DEFAULT_PRIORITY;
- TX_STATS_INC(portId,txPriority[*priorityPtr]);
- return IX_ETH_ACC_SUCCESS;
- }
- }
- else
- {
- IxEthAccTxPriority highestPriority = IX_ETH_ACC_TX_PRIORITY_7;
- while(1)
- {
- if(!IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId].
- ixEthAccTxData.txQ[highestPriority]))
- {
-
- *priorityPtr = highestPriority;
- TX_STATS_INC(portId,txPriority[highestPriority]);
- return IX_ETH_ACC_SUCCESS;
-
- }
- if (highestPriority == IX_ETH_ACC_TX_PRIORITY_0)
- {
- return IX_ETH_ACC_FAIL;
- }
- highestPriority--;
- }
- }
-}
-
-/**
- *
- * @brief This function will take a buffer from a TX S/W Q and attempt
- * to add it to the relevant TX H/W Q
- *
- * @param portId - the port whose TX queue is to be written to
- * priority - identifies the queue from which the entry is to be read
- *
- * @internal
- */
-PRIVATE IxEthAccStatus
-ixEthAccTxFromSwQ(IxEthAccPortId portId,
- IxEthAccTxPriority priority)
-{
- IX_OSAL_MBUF *mbuf;
- IX_STATUS qStatus;
-
- IX_OSAL_ENSURE((UINT32)priority <= (UINT32)7, "Invalid priority");
-
- IX_ETH_ACC_DATAPLANE_REMOVE_MBUF_FROM_Q_HEAD(
- ixEthAccPortData[portId].ixEthAccTxData.txQ[priority],
- mbuf);
-
- if (mbuf != NULL)
- {
- /*
- * Add the Tx buffer to the H/W Tx Q
- * We do not need to flush here as it is already done
- * in TxFrameSubmit().
- */
- qStatus = ixEthAccQmgrTxWrite(
- portId,
- IX_OSAL_MMU_VIRT_TO_PHYS((UINT32)IX_ETHACC_NE_SHARED(mbuf)),
- priority);
-
- if (qStatus == IX_SUCCESS)
- {
- TX_STATS_INC(portId,txFromSwQOK);
- return IX_SUCCESS;
- }
- else if (qStatus == IX_QMGR_Q_OVERFLOW)
- {
- /*
- * H/W Q overflow, need to save the buffer
- * back on the s/w Q.
- * we must put it back on the head of the q to avoid
- * reordering packet tx
- */
- TX_STATS_INC(portId,txFromSwQDelayed);
- IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD(
- ixEthAccPortData[portId].ixEthAccTxData.txQ[priority],
- mbuf);
-
- /*enable Q notification*/
- qStatus = ixQMgrNotificationEnable(
- IX_ETH_ACC_PORT_TO_TX_Q_ID(portId),
- IX_ETH_ACC_PORT_TO_TX_Q_SOURCE(portId));
-
- if (qStatus != IX_SUCCESS && qStatus != IX_QMGR_WARNING)
- {
- TX_INC(portId,txUnexpectedError);
- IX_ETH_ACC_FATAL_LOG(
- "ixEthAccTxFromSwQ:Unexpected Error: %u\n",
- qStatus, 0, 0, 0, 0, 0);
- }
- }
- else
- {
- TX_INC(portId,txUnexpectedError);
-
- /* recovery attempt */
- IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD(
- ixEthAccPortData[portId].ixEthAccTxData.txQ[priority],
- mbuf);
-
- IX_ETH_ACC_FATAL_LOG(
- "ixEthAccTxFromSwQ:Error: unexpected QM status 0x%08X\n",
- qStatus, 0, 0, 0, 0, 0);
- }
- }
- else
- {
- /* sw queue is empty */
- }
- return IX_ETH_ACC_FAIL;
-}
-
-/**
- *
- * @brief This function will take a buffer from a RXfree S/W Q and attempt
- * to add it to the relevant RxFree H/W Q
- *
- * @param portId - the port whose RXFree queue is to be written to
- *
- * @internal
- */
-PRIVATE IxEthAccStatus
-ixEthAccRxFreeFromSwQ(IxEthAccPortId portId)
-{
- IX_OSAL_MBUF *mbuf;
- IX_STATUS qStatus = IX_SUCCESS;
-
- IX_ETH_ACC_DATAPLANE_REMOVE_MBUF_FROM_Q_HEAD(
- ixEthAccPortData[portId].ixEthAccRxData.freeBufferList,
- mbuf);
- if (mbuf != NULL)
- {
- /*
- * Add The Rx Buffer to the H/W Free buffer Q if possible
- */
- qStatus = ixEthAccQmgrLockRxWrite(portId,
- IX_OSAL_MMU_VIRT_TO_PHYS(
- (UINT32)IX_ETHACC_NE_SHARED(mbuf)));
-
- if (qStatus == IX_SUCCESS)
- {
- RX_STATS_INC(portId,rxFreeRepFromSwQOK);
- /*
- * Buffer added to h/w Q.
- */
- return IX_SUCCESS;
- }
- else if (qStatus == IX_QMGR_Q_OVERFLOW)
- {
- /*
- * H/W Q overflow, need to save the buffer back on the s/w Q.
- */
- RX_STATS_INC(portId,rxFreeRepFromSwQDelayed);
-
- IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD(
- ixEthAccPortData[portId].ixEthAccRxData.freeBufferList,
- mbuf);
- }
- else
- {
- /* unexpected qmgr error */
- RX_INC(portId,rxUnexpectedError);
-
- IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD(
- ixEthAccPortData[portId].ixEthAccRxData.freeBufferList,
- mbuf);
-
- IX_ETH_ACC_FATAL_LOG("IxEthAccRxFreeFromSwQ:Error: unexpected QM status 0x%08X\n",
- qStatus, 0, 0, 0, 0, 0);
- }
- }
- else
- {
- /* sw queue is empty */
- }
- return IX_ETH_ACC_FAIL;
-}
-
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccInitDataPlane()
-{
- UINT32 portId;
-
- /*
- * Initialize the service and register callback to other services.
- */
-
- IX_ETH_ACC_MEMSET(&ixEthAccDataStats,
- 0,
- sizeof(ixEthAccDataStats));
-
- for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
- {
- ixOsalFastMutexInit(&txWriteMutex[portId]);
- ixOsalFastMutexInit(&rxWriteMutex[portId]);
-
- IX_ETH_ACC_MEMSET(&ixEthAccPortData[portId],
- 0,
- sizeof(ixEthAccPortData[portId]));
-
- ixEthAccPortData[portId].ixEthAccTxData.schDiscipline = FIFO_NO_PRIORITY;
- }
-
- return (IX_ETH_ACC_SUCCESS);
-}
-
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccPortTxDoneCallbackRegister(IxEthAccPortId portId,
- IxEthAccPortTxDoneCallback
- txCallbackFn,
- UINT32 callbackTag)
-{
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
- if (!IX_ETH_ACC_IS_PORT_VALID(portId))
- {
- return (IX_ETH_ACC_INVALID_PORT);
- }
-
-/* HACK: removing this code to enable NPE-A preliminary testing
- * if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- * {
- * IX_ETH_ACC_WARNING_LOG("ixEthAccPortTxDoneCallbackRegister: Unavailable Eth %d: Cannot register TxDone Callback.\n",(INT32)portId,0,0,0,0,0);
- * return IX_ETH_ACC_SUCCESS ;
- * }
- */
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
- if (txCallbackFn == 0)
- /* Check for null function pointer here. */
- {
- return (IX_ETH_ACC_INVALID_ARG);
- }
- ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn = txCallbackFn;
- ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag = callbackTag;
- return (IX_ETH_ACC_SUCCESS);
-}
-
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccPortRxCallbackRegister(IxEthAccPortId portId,
- IxEthAccPortRxCallback
- rxCallbackFn,
- UINT32 callbackTag)
-{
- IxEthAccPortId port;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
- if (!IX_ETH_ACC_IS_PORT_VALID(portId))
- {
- return (IX_ETH_ACC_INVALID_PORT);
- }
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("ixEthAccPortRxCallbackRegister: Unavailable Eth %d: Cannot register Rx Callback.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /* Check for null function pointer here. */
- if (rxCallbackFn == NULL)
- {
- return (IX_ETH_ACC_INVALID_ARG);
- }
-
- /* Check the user is not changing the callback type
- * when the port is enabled.
- */
- if (ixEthAccMacState[portId].portDisableState == ACTIVE)
- {
- for (port = 0; port < IX_ETH_ACC_NUMBER_OF_PORTS; port++)
- {
- if ((ixEthAccMacState[port].portDisableState == ACTIVE)
- && (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == TRUE))
- {
- /* one of the active ports has a different rx callback type.
- * Changing the callback type when the port is enabled
- * is not safe
- */
- return (IX_ETH_ACC_INVALID_ARG);
- }
- }
- }
-
- /* update the callback pointer : this is done before
- * registering the new qmgr callback
- */
- ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn = rxCallbackFn;
- ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag = callbackTag;
-
- /* update the qmgr callback for rx queues */
- if (ixEthAccQMgrRxCallbacksRegister(ixEthRxFrameQMCallback)
- != IX_ETH_ACC_SUCCESS)
- {
- /* unexpected qmgr error */
- IX_ETH_ACC_FATAL_LOG("ixEthAccPortRxCallbackRegister: unexpected QMgr error, " \
- "could not register Rx single-buffer callback\n", 0, 0, 0, 0, 0, 0);
-
- RX_INC(portId,rxUnexpectedError);
- return (IX_ETH_ACC_INVALID_ARG);
- }
-
- ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = FALSE;
-
- return (IX_ETH_ACC_SUCCESS);
-}
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccPortMultiBufferRxCallbackRegister(
- IxEthAccPortId portId,
- IxEthAccPortMultiBufferRxCallback
- rxCallbackFn,
- UINT32 callbackTag)
-{
- IxEthAccPortId port;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
- if (!IX_ETH_ACC_IS_PORT_VALID(portId))
- {
- return (IX_ETH_ACC_INVALID_PORT);
- }
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("ixEthAccPortMultiBufferRxCallbackRegister: Unavailable Eth %d: Cannot register Rx Callback.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /* Check for null function pointer here. */
- if (rxCallbackFn == NULL)
- {
- return (IX_ETH_ACC_INVALID_ARG);
- }
-
- /* Check the user is not changing the callback type
- * when the port is enabled.
- */
- if (ixEthAccMacState[portId].portDisableState == ACTIVE)
- {
- for (port = 0; port < IX_ETH_ACC_NUMBER_OF_PORTS; port++)
- {
- if ((ixEthAccMacState[port].portDisableState == ACTIVE)
- && (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == FALSE))
- {
- /* one of the active ports has a different rx callback type.
- * Changing the callback type when the port is enabled
- * is not safe
- */
- return (IX_ETH_ACC_INVALID_ARG);
- }
- }
- }
-
- /* update the callback pointer : this is done before
- * registering the new qmgr callback
- */
- ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn = rxCallbackFn;
- ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackTag = callbackTag;
-
- /* update the qmgr callback for rx queues */
- if (ixEthAccQMgrRxCallbacksRegister(ixEthRxMultiBufferQMCallback)
- != IX_ETH_ACC_SUCCESS)
- {
- /* unexpected qmgr error */
- RX_INC(portId,rxUnexpectedError);
-
- IX_ETH_ACC_FATAL_LOG("ixEthAccPortMultiBufferRxCallbackRegister: unexpected QMgr error, " \
- "could not register Rx multi-buffer callback\n", 0, 0, 0, 0, 0, 0);
-
- return (IX_ETH_ACC_INVALID_ARG);
- }
-
- ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = TRUE;
-
- return (IX_ETH_ACC_SUCCESS);
-}
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccPortTxFrameSubmit(IxEthAccPortId portId,
- IX_OSAL_MBUF *buffer,
- IxEthAccTxPriority priority)
-{
- IX_STATUS qStatus = IX_SUCCESS;
- UINT32 qBuffer;
- IxEthAccTxPriority highestPriority;
- IxQMgrQStatus txQStatus;
-
-#ifndef NDEBUG
- if (buffer == NULL)
- {
- return (IX_ETH_ACC_FAIL);
- }
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
- if (!IX_ETH_ACC_IS_PORT_VALID(portId))
- {
- return (IX_ETH_ACC_INVALID_PORT);
- }
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_FATAL_LOG("ixEthAccPortTxFrameSubmit: Unavailable Eth %d: Cannot submit Tx Frame.\n",
- (INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_PORT_UNINITIALIZED ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
- if ((UINT32)priority > (UINT32)IX_ETH_ACC_TX_PRIORITY_7)
- {
- return (IX_ETH_ACC_INVALID_ARG);
- }
-#endif
-
- /*
- * Need to Flush the MBUF and its contents (data) as it may be
- * read from the NPE. Convert virtual addresses to physical addresses also.
- */
- qBuffer = ixEthAccMbufTxQPrepare(buffer);
-
- /*
- * If no fifo priority set on Xscale ...
- */
- if (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline ==
- FIFO_NO_PRIORITY)
- {
- /*
- * Add The Tx Buffer to the H/W Tx Q if possible
- * (the priority is passed to the NPE, because
- * the NPE is able to reorder the frames
- * before transmission to the underlying hardware)
- */
- qStatus = ixEthAccQmgrTxWrite(portId,
- qBuffer,
- IX_ETH_ACC_TX_DEFAULT_PRIORITY);
-
- if (qStatus == IX_SUCCESS)
- {
- TX_STATS_INC(portId,txQOK);
-
- /*
- * "best case" scenario : Buffer added to h/w Q.
- */
- return (IX_SUCCESS);
- }
- else if (qStatus == IX_QMGR_Q_OVERFLOW)
- {
- /*
- * We were unable to write the buffer to the
- * appropriate H/W Q, Save it in the sw Q.
- * (use the default priority queue regardless of
- * input parameter)
- */
- priority = IX_ETH_ACC_TX_DEFAULT_PRIORITY;
- }
- else
- {
- /* unexpected qmgr error */
- TX_INC(portId,txUnexpectedError);
- IX_ETH_ACC_FATAL_LOG(
- "ixEthAccPortTxFrameSubmit:Error: qStatus = %u\n",
- (UINT32)qStatus, 0, 0, 0, 0, 0);
- return (IX_ETH_ACC_FAIL);
- }
- }
- else if (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline ==
- FIFO_PRIORITY)
- {
-
- /*
- * For priority transmission, put the frame directly on the H/W queue
- * if the H/W queue is empty, otherwise, put it in a S/W Q
- */
- ixQMgrQStatusGet(IX_ETH_ACC_PORT_TO_TX_Q_ID(portId), &txQStatus);
- if((txQStatus & IX_QMGR_Q_STATUS_E_BIT_MASK) != 0)
- {
- /*The tx queue is empty, check whether there are buffers on the s/w queues*/
- if(ixEthAccTxSwQHighestPriorityGet(portId, &highestPriority)
- !=IX_ETH_ACC_FAIL)
- {
- /*there are buffers on the s/w queues, submit them*/
- ixEthAccTxFromSwQ(portId, highestPriority);
-
- /* the queue was empty, 1 buffer is already supplied
- * but is likely to be immediately transmitted and the
- * hw queue is likely to be empty again, so submit
- * more from the sw queues
- */
- if(ixEthAccTxSwQHighestPriorityGet(portId, &highestPriority)
- !=IX_ETH_ACC_FAIL)
- {
- ixEthAccTxFromSwQ(portId, highestPriority);
- /*
- * and force the buffer supplied to be placed
- * on a priority queue
- */
- qStatus = IX_QMGR_Q_OVERFLOW;
- }
- else
- {
- /*there are no buffers in the s/w queues, submit directly*/
- qStatus = ixEthAccQmgrTxWrite(portId, qBuffer, priority);
- }
- }
- else
- {
- /*there are no buffers in the s/w queues, submit directly*/
- qStatus = ixEthAccQmgrTxWrite(portId, qBuffer, priority);
- }
- }
- else
- {
- qStatus = IX_QMGR_Q_OVERFLOW;
- }
- }
- else
- {
- TX_INC(portId,txUnexpectedError);
- IX_ETH_ACC_FATAL_LOG(
- "ixEthAccPortTxFrameSubmit:Error: wrong schedule discipline setup\n",
- 0, 0, 0, 0, 0, 0);
- return (IX_ETH_ACC_FAIL);
- }
-
- if(qStatus == IX_SUCCESS )
- {
- TX_STATS_INC(portId,txQOK);
- return IX_ETH_ACC_SUCCESS;
- }
- else if(qStatus == IX_QMGR_Q_OVERFLOW)
- {
- TX_STATS_INC(portId,txQDelayed);
- /*
- * We were unable to write the buffer to the
- * appropriate H/W Q, Save it in a s/w Q.
- */
- IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_TAIL(
- ixEthAccPortData[portId].
- ixEthAccTxData.txQ[priority],
- buffer);
-
- qStatus = ixQMgrNotificationEnable(
- IX_ETH_ACC_PORT_TO_TX_Q_ID(portId),
- IX_ETH_ACC_PORT_TO_TX_Q_SOURCE(portId));
-
- if (qStatus != IX_SUCCESS)
- {
- if (qStatus == IX_QMGR_WARNING)
- {
- /* notification is enabled for a queue
- * which is already empty (the condition is already met)
- * and there will be no more queue event to drain the sw queue
- */
- TX_STATS_INC(portId,txLateNotificationEnabled);
-
- /* pull a buffer from the sw queue */
- if(ixEthAccTxSwQHighestPriorityGet(portId, &highestPriority)
- !=IX_ETH_ACC_FAIL)
- {
- /*there are buffers on the s/w queues, submit from them*/
- ixEthAccTxFromSwQ(portId, highestPriority);
- }
- }
- else
- {
- TX_INC(portId,txUnexpectedError);
- IX_ETH_ACC_FATAL_LOG(
- "ixEthAccPortTxFrameSubmit: unexpected Error: %u\n",
- qStatus, 0, 0, 0, 0, 0);
- }
- }
- }
- else
- {
- TX_INC(portId,txUnexpectedError);
- IX_ETH_ACC_FATAL_LOG(
- "ixEthAccPortTxFrameSubmit: unexpected Error: %u\n",
- qStatus, 0, 0, 0, 0, 0);
- return (IX_ETH_ACC_FAIL);
- }
-
- return (IX_ETH_ACC_SUCCESS);
-}
-
-
-/**
- *
- * @brief replenish: convert a chain of mbufs to the format
- * expected by the NPE
- *
- */
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccPortRxFreeReplenish(IxEthAccPortId portId,
- IX_OSAL_MBUF *buffer)
-{
- IX_STATUS qStatus = IX_SUCCESS;
- UINT32 qBuffer;
-
- /*
- * Check buffer is valid.
- */
-
-#ifndef NDEBUG
- /* check parameter value */
- if (buffer == 0)
- {
- return (IX_ETH_ACC_FAIL);
- }
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
- if (!IX_ETH_ACC_IS_PORT_VALID(portId))
- {
- return (IX_ETH_ACC_INVALID_PORT);
- }
-
- /* check initialisation is done */
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_FATAL_LOG(" ixEthAccPortRxFreeReplenish: Unavailable Eth %d: Cannot replenish Rx Free Q.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_PORT_UNINITIALIZED ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
- /* check boundaries and constraints */
- if (IX_OSAL_MBUF_MLEN(buffer) < IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN)
- {
- return (IX_ETH_ACC_FAIL);
- }
-#endif
-
- qBuffer = ixEthAccMbufRxQPrepare(buffer);
-
- /*
- * Add The Rx Buffer to the H/W Free buffer Q if possible
- */
- qStatus = ixEthAccQmgrLockRxWrite(portId, qBuffer);
-
- if (qStatus == IX_SUCCESS)
- {
- RX_STATS_INC(portId,rxFreeRepOK);
- /*
- * Buffer added to h/w Q.
- */
- return (IX_SUCCESS);
- }
- else if (qStatus == IX_QMGR_Q_OVERFLOW)
- {
- RX_STATS_INC(portId,rxFreeRepDelayed);
- /*
- * We were unable to write the buffer to the approprate H/W Q,
- * Save it in a s/w Q.
- */
- IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_TAIL(
- ixEthAccPortData[portId].ixEthAccRxData.freeBufferList,
- buffer);
-
- qStatus = ixQMgrNotificationEnable(
- IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId),
- IX_ETH_ACC_PORT_TO_RX_FREE_Q_SOURCE(portId));
-
- if (qStatus != IX_SUCCESS)
- {
- if (qStatus == IX_QMGR_WARNING)
- {
- /* notification is enabled for a queue
- * which is already empty (the condition is already met)
- * and there will be no more queue event to drain the sw queue
- * move an entry from the sw queue to the hw queue */
- RX_STATS_INC(portId,rxFreeLateNotificationEnabled);
- ixEthAccRxFreeFromSwQ(portId);
- }
- else
- {
- RX_INC(portId,rxUnexpectedError);
- IX_ETH_ACC_FATAL_LOG(
- "ixEthAccRxPortFreeReplenish:Error: %u\n",
- qStatus, 0, 0, 0, 0, 0);
- }
- }
- }
- else
- {
- RX_INC(portId,rxUnexpectedError);
- IX_ETH_ACC_FATAL_LOG(
- "ixEthAccRxPortFreeReplenish:Error: qStatus = %u\n",
- (UINT32)qStatus, 0, 0, 0, 0, 0);
- return(IX_ETH_ACC_FAIL);
- }
- return (IX_ETH_ACC_SUCCESS);
-}
-
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccTxSchedulingDisciplineSetPriv(IxEthAccPortId portId,
- IxEthAccSchedulerDiscipline
- sched)
-{
- if (!IX_ETH_ACC_IS_PORT_VALID(portId))
- {
- return (IX_ETH_ACC_INVALID_PORT);
- }
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("ixEthAccTxSchedulingDisciplineSet: Unavailable Eth %d: Cannot set Tx Scheduling Discipline.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- if (sched != FIFO_PRIORITY && sched != FIFO_NO_PRIORITY)
- {
- return (IX_ETH_ACC_INVALID_ARG);
- }
-
- ixEthAccPortData[portId].ixEthAccTxData.schDiscipline = sched;
- return (IX_ETH_ACC_SUCCESS);
-}
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccRxSchedulingDisciplineSetPriv(IxEthAccSchedulerDiscipline
- sched)
-{
- if (sched != FIFO_PRIORITY && sched != FIFO_NO_PRIORITY)
- {
- return (IX_ETH_ACC_INVALID_ARG);
- }
-
- ixEthAccDataInfo.schDiscipline = sched;
-
- return (IX_ETH_ACC_SUCCESS);
-}
-
-
-/**
- * @fn ixEthRxFrameProcess(IxEthAccPortId portId, IX_OSAL_MBUF *mbufPtr)
- *
- * @brief process incoming frame :
- *
- * @param @ref IxQMgrCallback IxQMgrMultiBufferCallback
- *
- * @return none
- *
- * @internal
- *
- */
-IX_ETH_ACC_PRIVATE BOOL
-ixEthRxFrameProcess(IxEthAccPortId portId, IX_OSAL_MBUF *mbufPtr)
-{
- UINT32 flags;
- IxEthDBStatus result;
-
-#ifndef NDEBUG
- /* Prudent to at least check the port is within range */
- if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS)
- {
- ixEthAccDataStats.unexpectedError++;
- IX_ETH_ACC_FATAL_LOG(
- "ixEthRxFrameProcess: Illegal port: %u\n",
- (UINT32)portId, 0, 0, 0, 0, 0);
- return FALSE;
- }
-#endif
-
- /* convert fields from mbuf header */
- ixEthAccMbufFromRxQ(mbufPtr);
-
- /* check about any special processing for this frame */
- flags = IX_ETHACC_NE_FLAGS(mbufPtr);
- if ((flags & (IX_ETHACC_NE_FILTERMASK | IX_ETHACC_NE_NEWSRCMASK)) == 0)
- {
- /* "best case" scenario : nothing special to do for this frame */
- return TRUE;
- }
-
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
- /* if a new source MAC address is detected by the NPE,
- * update IxEthDB with the portId and the MAC address.
- */
- if ((flags & IX_ETHACC_NE_NEWSRCMASK & ixEthAccNewSrcMask) != 0)
- {
- result = ixEthDBFilteringDynamicEntryProvision(portId,
- (IxEthDBMacAddr *) IX_ETHACC_NE_SOURCEMAC(mbufPtr));
-
- if (result != IX_ETH_DB_SUCCESS && result != IX_ETH_DB_FEATURE_UNAVAILABLE)
- {
- if ((ixEthAccMacState[portId].portDisableState == ACTIVE) && (result != IX_ETH_DB_BUSY))
- {
- RX_STATS_INC(portId, rxUnexpectedError);
- IX_ETH_ACC_FATAL_LOG("ixEthRxFrameProcess: Failed to add source MAC \
- to the Learning/Filtering database\n", 0, 0, 0, 0, 0, 0);
- }
- else
- {
- /* we expect this to fail during PortDisable, as EthDB is disabled for
- * that port and will refuse to learn new addresses
- */
- }
- }
- else
- {
- RX_STATS_INC(portId, rxUnlearnedMacAddress);
- }
- }
-#endif
-
- /* check if this frame should have been filtered
- * by the NPE and take the appropriate action
- */
- if (((flags & IX_ETHACC_NE_FILTERMASK) != 0)
- && (ixEthAccMacState[portId].portDisableState == ACTIVE))
- {
- /* If the mbuf was allocated with a small data size, or the current data pointer is not
- * within the allocated data area, then the buffer is non-standard and has to be
- * replenished with the minimum size only
- */
- if( (IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(mbufPtr) < IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN)
- || ((UINT8 *)IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(mbufPtr) > IX_OSAL_MBUF_MDATA(mbufPtr))
- || ((UINT8 *)(IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(mbufPtr) +
- IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(mbufPtr))
- < IX_OSAL_MBUF_MDATA(mbufPtr)) )
- {
- /* set to minimum length */
- IX_OSAL_MBUF_MLEN(mbufPtr) = IX_OSAL_MBUF_PKT_LEN(mbufPtr) =
- IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN;
- }
- else
- {
- /* restore original length */
- IX_OSAL_MBUF_MLEN(mbufPtr) = IX_OSAL_MBUF_PKT_LEN(mbufPtr) =
- ( IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(mbufPtr) -
- (IX_OSAL_MBUF_MDATA(mbufPtr) - (UINT8 *)IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(mbufPtr)) );
- }
-
- /* replenish from here */
- if (ixEthAccPortRxFreeReplenish(portId, mbufPtr) != IX_ETH_ACC_SUCCESS)
- {
- IX_ETH_ACC_FATAL_LOG("ixEthRxFrameProcess: Failed to replenish with filtered frame\
- on port %d\n", portId, 0, 0, 0, 0, 0);
- }
-
- RX_STATS_INC(portId, rxFiltered);
-
- /* indicate that frame should not be subjected to further processing */
- return FALSE;
- }
-
- return TRUE;
-}
-
-
-/**
- * @fn ixEthRxFrameQMCallback
- *
- * @brief receive callback for Frame receive Q from NPE
- *
- * Frames are passed one-at-a-time to the user
- *
- * @param @ref IxQMgrCallback
- *
- * @return none
- *
- * @internal
- *
- * Design note : while processing the entry X, entry X+1 is preloaded
- * into memory to reduce the number of stall cycles
- *
- */
-void ixEthRxFrameQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId)
-{
- IX_OSAL_MBUF *mbufPtr;
- IX_OSAL_MBUF *nextMbufPtr;
- UINT32 qEntry;
- UINT32 nextQEntry;
- UINT32 *qEntryPtr;
- UINT32 portId;
- UINT32 destPortId;
- UINT32 npeId;
- UINT32 rxQReadStatus;
-
- /*
- * Design note : entries are read in a buffer, This buffer contains
- * an extra zeroed entry so the loop will
- * always terminate on a null entry, whatever the result of Burst read is.
- */
- UINT32 rxQEntry[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK + 1];
-
- /*
- * Indication of the number of times the callback is used.
- */
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackCounter);
-
- do
- {
- /*
- * Indication of the number of times the queue is drained
- */
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackBurstRead);
-
- /* ensure the last entry of the array contains a zeroed value */
- qEntryPtr = rxQEntry;
- qEntryPtr[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK] = 0;
-
- rxQReadStatus = ixQMgrQBurstRead(qId,
- IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK,
- qEntryPtr);
-
-#ifndef NDEBUG
- if ((rxQReadStatus != IX_QMGR_Q_UNDERFLOW)
- && (rxQReadStatus != IX_SUCCESS))
- {
- ixEthAccDataStats.unexpectedError++;
- /*major error*/
- IX_ETH_ACC_FATAL_LOG(
- "ixEthRxFrameQMCallback:Error: %u\n",
- (UINT32)rxQReadStatus, 0, 0, 0, 0, 0);
- return;
- }
-#endif
-
- /* convert and preload the next entry
- * (the conversion function takes care about null pointers which
- * are used to mark the end of the loop)
- */
- nextQEntry = *qEntryPtr;
- nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry,
- IX_ETHNPE_QM_Q_RXENET_ADDR_MASK);
-
- while(nextQEntry != 0)
- {
- /* get the next entry */
- qEntry = nextQEntry;
- mbufPtr = nextMbufPtr;
-
-#ifndef NDEBUG
- if (mbufPtr == NULL)
- {
- ixEthAccDataStats.unexpectedError++;
- IX_ETH_ACC_FATAL_LOG(
- "ixEthRxFrameQMCallback: Null Mbuf Ptr\n",
- 0, 0, 0, 0, 0, 0);
- return;
- }
-#endif
-
- /* convert the next entry
- * (the conversion function takes care about null pointers which
- * are used to mark the end of the loop)
- */
- nextQEntry = *(++qEntryPtr);
- nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry,
- IX_ETHNPE_QM_Q_RXENET_ADDR_MASK);
-
- /*
- * Get Port and Npe ID from message.
- */
- npeId = ((IX_ETHNPE_QM_Q_RXENET_NPEID_MASK &
- qEntry) >> IX_ETHNPE_QM_Q_FIELD_NPEID_R);
- portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);
-
- /* process frame, check the return code and skip the remaining of
- * the loop if the frame is to be filtered out
- */
- if (ixEthRxFrameProcess(portId, mbufPtr))
- {
- /* destination portId for this packet */
- destPortId = IX_ETHACC_NE_DESTPORTID(mbufPtr);
-
- if (destPortId != IX_ETH_DB_UNKNOWN_PORT)
- {
- destPortId = IX_ETH_DB_NPE_LOGICAL_ID_TO_PORT_ID(destPortId);
- }
-
- /* test if QoS is enabled in ethAcc
- */
- if (ixEthAccDataInfo.schDiscipline == FIFO_PRIORITY)
- {
- /* check if there is a higher priority queue
- * which may require processing and then process it.
- */
- if (ixEthAccDataInfo.higherPriorityQueue[qId] < IX_QMGR_MAX_NUM_QUEUES)
- {
- ixEthRxFrameQMCallback(ixEthAccDataInfo.higherPriorityQueue[qId],
- callbackId);
- }
- }
-
- /*
- * increment priority stats
- */
- RX_STATS_INC(portId,rxPriority[IX_ETHACC_NE_QOS(mbufPtr)]);
-
- /*
- * increment callback count stats
- */
- RX_STATS_INC(portId,rxFrameClientCallback);
-
- /*
- * Call user level callback.
- */
- ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn(
- ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag,
- mbufPtr,
- destPortId);
- }
- }
- } while (rxQReadStatus == IX_SUCCESS);
-}
-
-/**
- * @fn ixEthRxMultiBufferQMCallback
- *
- * @brief receive callback for Frame receive Q from NPE
- *
- * Frames are passed as an array to the user
- *
- * @param @ref IxQMgrCallback
- *
- * @return none
- *
- * @internal
- *
- * Design note : while processing the entry X, entry X+1 is preloaded
- * into memory to reduce the number of stall cycles
- *
- */
-void ixEthRxMultiBufferQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId)
-{
- IX_OSAL_MBUF *mbufPtr;
- IX_OSAL_MBUF *nextMbufPtr;
- UINT32 qEntry;
- UINT32 nextQEntry;
- UINT32 *qEntryPtr;
- UINT32 portId;
- UINT32 npeId;
- UINT32 rxQReadStatus;
- /*
- * Design note : entries are read in a static buffer, This buffer contains
- * an extra zeroed entry so the loop will
- * always terminate on a null entry, whatever the result of Burst read is.
- */
- static UINT32 rxQEntry[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK + 1];
- static IX_OSAL_MBUF *rxMbufPortArray[IX_ETH_ACC_NUMBER_OF_PORTS][IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK + 1];
- IX_OSAL_MBUF **rxMbufPtr[IX_ETH_ACC_NUMBER_OF_PORTS];
-
- for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
- {
- rxMbufPtr[portId] = rxMbufPortArray[portId];
- }
-
- /*
- * Indication of the number of times the callback is used.
- */
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackCounter);
-
- do
- {
- /*
- * Indication of the number of times the queue is drained
- */
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackBurstRead);
-
- /* ensure the last entry of the array contains a zeroed value */
- qEntryPtr = rxQEntry;
- qEntryPtr[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK] = 0;
-
- rxQReadStatus = ixQMgrQBurstRead(qId,
- IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK,
- qEntryPtr);
-
-#ifndef NDEBUG
- if ((rxQReadStatus != IX_QMGR_Q_UNDERFLOW)
- && (rxQReadStatus != IX_SUCCESS))
- {
- ixEthAccDataStats.unexpectedError++;
- /*major error*/
- IX_ETH_ACC_FATAL_LOG(
- "ixEthRxFrameMultiBufferQMCallback:Error: %u\n",
- (UINT32)rxQReadStatus, 0, 0, 0, 0, 0);
- return;
- }
-#endif
-
- /* convert and preload the next entry
- * (the conversion function takes care about null pointers which
- * are used to mark the end of the loop)
- */
- nextQEntry = *qEntryPtr;
- nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry,
- IX_ETHNPE_QM_Q_RXENET_ADDR_MASK);
-
- while(nextQEntry != 0)
- {
- /* get the next entry */
- qEntry = nextQEntry;
- mbufPtr = nextMbufPtr;
-
-#ifndef NDEBUG
- if (mbufPtr == NULL)
- {
- ixEthAccDataStats.unexpectedError++;
- IX_ETH_ACC_FATAL_LOG(
- "ixEthRxFrameMultiBufferQMCallback:Error: Null Mbuf Ptr\n",
- 0, 0, 0, 0, 0, 0);
- return;
- }
-#endif
-
- /* convert the next entry
- * (the conversion function takes care about null pointers which
- * are used to mark the end of the loop)
- */
- nextQEntry = *(++qEntryPtr);
- nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry,
- IX_ETHNPE_QM_Q_RXENET_ADDR_MASK);
-
- /*
- * Get Port and Npe ID from message.
- */
- npeId = ((IX_ETHNPE_QM_Q_RXENET_NPEID_MASK &
- qEntry) >>
- IX_ETHNPE_QM_Q_FIELD_NPEID_R);
- portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);
-
- /* skip the remaining of the loop if the frame is
- * to be filtered out
- */
- if (ixEthRxFrameProcess(portId, mbufPtr))
- {
- /* store a mbuf pointer in an array */
- *rxMbufPtr[portId]++ = mbufPtr;
-
- /*
- * increment priority stats
- */
- RX_STATS_INC(portId,rxPriority[IX_ETHACC_NE_QOS(mbufPtr)]);
- }
-
- /* test for QoS enabled in ethAcc */
- if (ixEthAccDataInfo.schDiscipline == FIFO_PRIORITY)
- {
- /* check if there is a higher priority queue
- * which may require processing and then process it.
- */
- if (ixEthAccDataInfo.higherPriorityQueue[qId] < IX_QMGR_MAX_NUM_QUEUES)
- {
- ixEthRxMultiBufferQMCallback(ixEthAccDataInfo.higherPriorityQueue[qId],
- callbackId);
- }
- }
- }
-
- /* check if any of the the arrays contains any entry */
- for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
- {
- if (rxMbufPtr[portId] != rxMbufPortArray[portId])
- {
- /* add a last NULL pointer at the end of the
- * array of mbuf pointers
- */
- *rxMbufPtr[portId] = NULL;
-
- /*
- * increment callback count stats
- */
- RX_STATS_INC(portId,rxFrameClientCallback);
-
- /*
- * Call user level callback with an array of
- * buffers (NULL terminated)
- */
- ixEthAccPortData[portId].ixEthAccRxData.
- rxMultiBufferCallbackFn(
- ixEthAccPortData[portId].ixEthAccRxData.
- rxMultiBufferCallbackTag,
- rxMbufPortArray[portId]);
-
- /* reset the buffer pointer to the beginning of
- * the array
- */
- rxMbufPtr[portId] = rxMbufPortArray[portId];
- }
- }
-
- } while (rxQReadStatus == IX_SUCCESS);
-}
-
-
-/**
- * @brief rxFree low event handler
- *
- */
-void ixEthRxFreeQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId)
-{
- IxEthAccPortId portId = (IxEthAccPortId) callbackId;
- int lockVal;
- UINT32 maxQWritesToPerform = IX_ETH_ACC_MAX_RX_FREE_BUFFERS_LOAD;
- IX_STATUS qStatus = IX_SUCCESS;
-
- /*
- * We have reached a low threshold on one of the Rx Free Qs
- */
-
- /*note that due to the fact that we are working off an Empty threshold, this callback
- need only write a single entry to the Rx Free queue in order to re-arm the notification
- */
-
- RX_STATS_INC(portId,rxFreeLowCallback);
-
- /*
- * Get buffers from approprite S/W Rx freeBufferList Q.
- */
-
-#ifndef NDEBUG
- if (!IX_ETH_ACC_IS_PORT_VALID(portId))
- {
- ixEthAccDataStats.unexpectedError++;
- IX_ETH_ACC_FATAL_LOG(
- "ixEthRxFreeQMCallback:Error: Invalid Port 0x%08X\n",
- portId, 0, 0, 0, 0, 0);
- return;
- }
-#endif
- IX_ETH_ACC_DATA_PLANE_LOCK(lockVal);
- if (IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId].
- ixEthAccRxData.freeBufferList))
- {
- /*
- * Turn off Q callback notification for Q in Question.
- */
- qStatus = ixQMgrNotificationDisable(
- IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId));
-
-
- IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);
-
- if (qStatus != IX_SUCCESS)
- {
- RX_INC(portId,rxUnexpectedError);
- IX_ETH_ACC_FATAL_LOG(
- "ixEthRxFreeQMCallback:Error: unexpected QM status 0x%08X\n",
- qStatus, 0, 0, 0, 0, 0);
- return;
- }
- }
- else
- {
- IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);
- /*
- * Load the H/W Q with buffers from the s/w Q.
- */
-
- do
- {
- /*
- * Consume Q entries. - Note Q contains Physical addresss,
- * and have already been flushed to memory,
- * And endianess converted if required.
- */
- if (ixEthAccRxFreeFromSwQ(portId) != IX_SUCCESS)
- {
- /*
- * No more entries in s/w Q.
- * Turn off Q callback indication
- */
-
- IX_ETH_ACC_DATA_PLANE_LOCK(lockVal);
- if (IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId].
- ixEthAccRxData.freeBufferList))
- {
- qStatus = ixQMgrNotificationDisable(
- IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId));
- }
- IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);
- break;
- }
- }
- while (--maxQWritesToPerform);
- }
-}
-/**
- * @fn Tx queue low event handler
- *
- */
-void
-ixEthTxFrameQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId)
-{
- IxEthAccPortId portId = (IxEthAccPortId) callbackId;
- int lockVal;
- UINT32 maxQWritesToPerform = IX_ETH_ACC_MAX_TX_FRAME_TX_CONSUME_PER_CALLBACK;
- IX_STATUS qStatus = IX_SUCCESS;
- IxEthAccTxPriority highestPriority;
-
-
- /*
- * We have reached a low threshold on the Tx Q, and are being asked to
- * supply a buffer for transmission from our S/W TX queues
- */
- TX_STATS_INC(portId,txLowThreshCallback);
-
- /*
- * Get buffers from approprite Q.
- */
-
-#ifndef NDEBUG
- if (!IX_ETH_ACC_IS_PORT_VALID(portId))
- {
- ixEthAccDataStats.unexpectedError++;
- IX_ETH_ACC_FATAL_LOG(
- "ixEthTxFrameQMCallback:Error: Invalid Port 0x%08X\n",
- portId, 0, 0, 0, 0, 0);
- return;
- }
-#endif
-
- do
- {
- /*
- * Consume Q entries. - Note Q contains Physical addresss,
- * and have already been flushed to memory,
- * and endianess already sone if required.
- */
-
- IX_ETH_ACC_DATA_PLANE_LOCK(lockVal);
-
- if(ixEthAccTxSwQHighestPriorityGet(portId, &highestPriority) ==
- IX_ETH_ACC_FAIL)
- {
- /*
- * No more entries in s/w Q.
- * Turn off Q callback indication
- */
- qStatus = ixQMgrNotificationDisable(
- IX_ETH_ACC_PORT_TO_TX_Q_ID(portId));
-
- IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);
-
- if (qStatus != IX_SUCCESS)
- {
- ixEthAccDataStats.unexpectedError++;
- IX_ETH_ACC_FATAL_LOG(
- "ixEthTxFrameQMCallback:Error: unexpected QM status 0x%08X\n",
- qStatus, 0, 0, 0, 0, 0);
- }
-
- return;
- }
- else
- {
- IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);
- if (ixEthAccTxFromSwQ(portId,highestPriority)!=IX_SUCCESS)
- {
- /* nothing left in the sw queue or the hw queues are
- * full. There is no point to continue to drain the
- * sw queues
- */
- return;
- }
- }
- }
- while (--maxQWritesToPerform);
-}
-
-/**
- * @brief TxDone event handler
- *
- * Design note : while processing the entry X, entry X+1 is preloaded
- * into memory to reduce the number of stall cycles
- *
- */
-
-void
-ixEthTxFrameDoneQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId)
-{
- IX_OSAL_MBUF *mbufPtr;
- UINT32 qEntry;
- UINT32 *qEntryPtr;
- UINT32 txDoneQReadStatus;
- UINT32 portId;
- UINT32 npeId;
-
- /*
- * Design note : entries are read in a static buffer, This buffer contains
- * an extra entyry (which is zeroed by the compiler), so the loop will
- * always terminate on a null entry, whatever the result of Burst read is.
- */
- static UINT32 txDoneQEntry[IX_ETH_ACC_MAX_TX_FRAME_DONE_CONSUME_PER_CALLBACK + 1];
-
- /*
- * Indication that Tx frames have been transmitted from the NPE.
- */
-
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.txDoneCallbackCounter);
-
- do{
- qEntryPtr = txDoneQEntry;
- txDoneQReadStatus = ixQMgrQBurstRead(IX_ETH_ACC_TX_FRAME_DONE_ETH_Q,
- IX_ETH_ACC_MAX_TX_FRAME_DONE_CONSUME_PER_CALLBACK,
- qEntryPtr);
-
-#ifndef NDEBUG
- if (txDoneQReadStatus != IX_QMGR_Q_UNDERFLOW
- && (txDoneQReadStatus != IX_SUCCESS))
- {
- /*major error*/
- ixEthAccDataStats.unexpectedError++;
- IX_ETH_ACC_FATAL_LOG(
- "ixEthTxFrameDoneQMCallback:Error: %u\n",
- (UINT32)txDoneQReadStatus, 0, 0, 0, 0, 0);
- return;
- }
-#endif
-
- qEntry = *qEntryPtr;
-
- while(qEntry != 0)
- {
- mbufPtr = ixEthAccEntryFromQConvert(qEntry,
- IX_ETHNPE_QM_Q_TXENET_ADDR_MASK);
-
-#ifndef NDEBUG
- if (mbufPtr == NULL)
- {
- ixEthAccDataStats.unexpectedError++;
- IX_ETH_ACC_FATAL_LOG(
- "ixEthTxFrameDoneQMCallback:Error: Null Mbuf Ptr\n",
- 0, 0, 0, 0, 0, 0);
- return;
- }
-#endif
-
- /* endianness conversions and stats updates */
- ixEthAccMbufFromTxQ(mbufPtr);
-
- /*
- * Get NPE id from message, then convert to portId.
- */
- npeId = ((IX_ETHNPE_QM_Q_TXENETDONE_NPEID_MASK &
- qEntry) >>
- IX_ETHNPE_QM_Q_FIELD_NPEID_R);
- portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);
-
-#ifndef NDEBUG
- /* Prudent to at least check the port is within range */
- if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS)
- {
- ixEthAccDataStats.unexpectedError++;
- IX_ETH_ACC_FATAL_LOG(
- "ixEthTxFrameDoneQMCallback: Illegal port: %u\n",
- (UINT32)portId, 0, 0, 0, 0, 0);
- return;
- }
-#endif
-
- TX_STATS_INC(portId,txDoneClientCallback);
-
- /*
- * Call user level callback.
- */
- ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn(
- ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag,
- mbufPtr);
-
- /* move to next queue entry */
- qEntry = *(++qEntryPtr);
-
- }
- } while( txDoneQReadStatus == IX_SUCCESS );
-}
-
-IX_ETH_ACC_PUBLIC
-void ixEthAccDataPlaneShow(void)
-{
- UINT32 numTx0Entries;
- UINT32 numTx1Entries;
- UINT32 numTxDoneEntries;
- UINT32 numRxEntries;
- UINT32 numRxFree0Entries;
- UINT32 numRxFree1Entries;
- UINT32 portId;
-#ifdef __ixp46X
- UINT32 numTx2Entries;
- UINT32 numRxFree2Entries;
-#endif
-#ifndef NDEBUG
- UINT32 priority;
- UINT32 numBuffersInRx=0;
- UINT32 numBuffersInTx=0;
- UINT32 numBuffersInSwQ=0;
- UINT32 totalBuffers=0;
- UINT32 rxFreeCallbackCounter = 0;
- UINT32 txCallbackCounter = 0;
-#endif
- UINT32 key;
-
- /* snapshot of stats */
- IxEthAccTxDataStats tx[IX_ETH_ACC_NUMBER_OF_PORTS];
- IxEthAccRxDataStats rx[IX_ETH_ACC_NUMBER_OF_PORTS];
- IxEthAccDataPlaneStats stats;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return;
- }
-
- /* get a reliable snapshot */
- key = ixOsalIrqLock();
-
- numTx0Entries = 0;
- ixQMgrQNumEntriesGet(IX_ETH_ACC_TX_FRAME_ENET0_Q, &numTx0Entries);
- numTx1Entries = 0;
- ixQMgrQNumEntriesGet(IX_ETH_ACC_TX_FRAME_ENET1_Q, &numTx1Entries);
- numTxDoneEntries = 0;
- ixQMgrQNumEntriesGet( IX_ETH_ACC_TX_FRAME_DONE_ETH_Q, &numTxDoneEntries);
- numRxEntries = 0;
- ixEthAccQMgrRxQEntryGet(&numRxEntries);
- numRxFree0Entries = 0;
- ixQMgrQNumEntriesGet(IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q, &numRxFree0Entries);
- numRxFree1Entries = 0;
- ixQMgrQNumEntriesGet(IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q, &numRxFree1Entries);
-
-#ifdef __ixp46X
- numTx2Entries = 0;
- ixQMgrQNumEntriesGet(IX_ETH_ACC_TX_FRAME_ENET2_Q, &numTx2Entries);
- numRxFree2Entries = 0;
- ixQMgrQNumEntriesGet(IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q, &numRxFree2Entries);
-#endif
-
- for(portId=IX_ETH_PORT_1; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
- {
- memcpy(&tx[portId],
- &ixEthAccPortData[portId].ixEthAccTxData.stats,
- sizeof(tx[portId]));
- memcpy(&rx[portId],
- &ixEthAccPortData[portId].ixEthAccRxData.stats,
- sizeof(rx[portId]));
- }
- memcpy(&stats, &ixEthAccDataStats, sizeof(stats));
-
- ixOsalIrqUnlock(key);
-
-#ifdef NDEBUG
- printf("Detailed statistics collection not supported in this load\n");
-#endif
-
- /* print snapshot */
- for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
- {
- /* If not IXP42X A0 stepping, proceed to check for existence of coprocessors */
- if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
- (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
- || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
- {
- if ((IX_ETH_PORT_1 == portId) &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED))
- {
- continue ;
- }
- if ((IX_ETH_PORT_2 == portId) &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED))
- {
- continue ;
- }
- if ((IX_ETH_PORT_3 == portId) &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA_ETH) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED))
- {
- continue ;
- }
- }
-
- printf("PORT %u --------------------------------\n",
- portId);
-#ifndef NDEBUG
- printf("Tx Done Frames : %u\n",
- tx[portId].txDoneClientCallback +
- tx[portId].txDoneSwQDuringDisable +
- tx[portId].txDoneDuringDisable);
- printf("Tx Frames : %u\n",
- tx[portId].txQOK + tx[portId].txQDelayed);
- printf("Tx H/W Q Added OK : %u\n",
- tx[portId].txQOK);
- printf("Tx H/W Q Delayed : %u\n",
- tx[portId].txQDelayed);
- printf("Tx From S/W Q Added OK : %u\n",
- tx[portId].txFromSwQOK);
- printf("Tx From S/W Q Delayed : %u\n",
- tx[portId].txFromSwQDelayed);
- printf("Tx Overflow : %u\n",
- tx[portId].txOverflow);
- printf("Tx Mutual Lock : %u\n",
- tx[portId].txLock);
- printf("Tx Late Ntf Enabled : %u\n",
- tx[portId].txLateNotificationEnabled);
- printf("Tx Low Thresh CB : %u\n",
- tx[portId].txLowThreshCallback);
- printf("Tx Done from H/W Q (Disable) : %u\n",
- tx[portId].txDoneDuringDisable);
- printf("Tx Done from S/W Q (Disable) : %u\n",
- tx[portId].txDoneSwQDuringDisable);
- for (priority = IX_ETH_ACC_TX_PRIORITY_0;
- priority <= IX_ETH_ACC_TX_PRIORITY_7;
- priority++)
- {
- if (tx[portId].txPriority[priority])
- {
- printf("Tx Priority %u : %u\n",
- priority,
- tx[portId].txPriority[priority]);
- }
- }
-#endif
- printf("Tx unexpected errors : %u (should be 0)\n",
- tx[portId].txUnexpectedError);
-
-#ifndef NDEBUG
- printf("Rx Frames : %u\n",
- rx[portId].rxFrameClientCallback +
- rx[portId].rxSwQDuringDisable+
- rx[portId].rxDuringDisable);
- printf("Rx Free Replenish : %u\n",
- rx[portId].rxFreeRepOK + rx[portId].rxFreeRepDelayed);
- printf("Rx Free H/W Q Added OK : %u\n",
- rx[portId].rxFreeRepOK);
- printf("Rx Free H/W Q Delayed : %u\n",
- rx[portId].rxFreeRepDelayed);
- printf("Rx Free From S/W Q Added OK : %u\n",
- rx[portId].rxFreeRepFromSwQOK);
- printf("Rx Free From S/W Q Delayed : %u\n",
- rx[portId].rxFreeRepFromSwQDelayed);
- printf("Rx Free Overflow : %u\n",
- rx[portId].rxFreeOverflow);
- printf("Rx Free Mutual Lock : %u\n",
- rx[portId].rxFreeLock);
- printf("Rx Free Late Ntf Enabled : %u\n",
- rx[portId].rxFreeLateNotificationEnabled);
- printf("Rx Free Low CB : %u\n",
- rx[portId].rxFreeLowCallback);
- printf("Rx From H/W Q (Disable) : %u\n",
- rx[portId].rxDuringDisable);
- printf("Rx From S/W Q (Disable) : %u\n",
- rx[portId].rxSwQDuringDisable);
- printf("Rx unlearned Mac Address : %u\n",
- rx[portId].rxUnlearnedMacAddress);
- printf("Rx Filtered (Rx => RxFree) : %u\n",
- rx[portId].rxFiltered);
-
- for (priority = IX_ETH_ACC_TX_PRIORITY_0;
- priority <= IX_ETH_ACC_TX_PRIORITY_7;
- priority++)
- {
- if (rx[portId].rxPriority[priority])
- {
- printf("Rx Priority %u : %u\n",
- priority,
- rx[portId].rxPriority[priority]);
- }
- }
-#endif
- printf("Rx unexpected errors : %u (should be 0)\n",
- rx[portId].rxUnexpectedError);
-
-#ifndef NDEBUG
- numBuffersInTx = tx[portId].txQOK +
- tx[portId].txQDelayed -
- tx[portId].txDoneClientCallback -
- tx[portId].txDoneSwQDuringDisable -
- tx[portId].txDoneDuringDisable;
-
- printf("# Tx Buffers currently for transmission : %u\n",
- numBuffersInTx);
-
- numBuffersInRx = rx[portId].rxFreeRepOK +
- rx[portId].rxFreeRepDelayed -
- rx[portId].rxFrameClientCallback -
- rx[portId].rxSwQDuringDisable -
- rx[portId].rxDuringDisable;
-
- printf("# Rx Buffers currently for reception : %u\n",
- numBuffersInRx);
-
- totalBuffers += numBuffersInRx + numBuffersInTx;
-#endif
- }
-
- printf("---------------------------------------\n");
-
-#ifndef NDEBUG
- printf("\n");
- printf("Mbufs :\n");
- printf("Tx Unchained mbufs : %u\n",
- stats.unchainedTxMBufs);
- printf("Tx Chained bufs : %u\n",
- stats.chainedTxMBufs);
- printf("TxDone Unchained mbufs : %u\n",
- stats.unchainedTxDoneMBufs);
- printf("TxDone Chained bufs : %u\n",
- stats.chainedTxDoneMBufs);
- printf("RxFree Unchained mbufs : %u\n",
- stats.unchainedRxFreeMBufs);
- printf("RxFree Chained bufs : %u\n",
- stats.chainedRxFreeMBufs);
- printf("Rx Unchained mbufs : %u\n",
- stats.unchainedRxMBufs);
- printf("Rx Chained bufs : %u\n",
- stats.chainedRxMBufs);
-
- printf("\n");
- printf("Software queue usage :\n");
- printf("Buffers added to S/W Q : %u\n",
- stats.addToSwQ);
- printf("Buffers removed from S/W Q : %u\n",
- stats.removeFromSwQ);
-
- printf("\n");
- printf("Hardware queues callbacks :\n");
-
- for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
- {
- rxFreeCallbackCounter += rx[portId].rxFreeLowCallback;
- txCallbackCounter += tx[portId].txLowThreshCallback;
- }
- printf("Tx Done QM Callback invoked : %u\n",
- stats.txDoneCallbackCounter);
- printf("Tx QM Callback invoked : %u\n",
- txCallbackCounter);
- printf("Rx QM Callback invoked : %u\n",
- stats.rxCallbackCounter);
- printf("Rx QM Callback burst read : %u\n",
- stats.rxCallbackBurstRead);
- printf("Rx Free QM Callback invoked : %u\n",
- rxFreeCallbackCounter);
-#endif
- printf("Unexpected errors in CB : %u (should be 0)\n",
- stats.unexpectedError);
- printf("\n");
-
- printf("Hardware queues levels :\n");
- printf("Transmit Port 1 Q : %u \n",numTx0Entries);
- printf("Transmit Port 2 Q : %u \n",numTx1Entries);
-#ifdef __ixp46X
- printf("Transmit Port 3 Q : %u \n",numTx2Entries);
-#endif
- printf("Transmit Done Q : %u \n",numTxDoneEntries);
- printf("Receive Q : %u \n",numRxEntries);
- printf("Receive Free Port 1 Q : %u \n",numRxFree0Entries);
- printf("Receive Free Port 2 Q : %u \n",numRxFree1Entries);
-#ifdef __ixp46X
- printf("Receive Free Port 3 Q : %u \n",numRxFree2Entries);
-#endif
-
-#ifndef NDEBUG
- printf("\n");
- printf("# Total Buffers accounted for : %u\n",
- totalBuffers);
-
- numBuffersInSwQ = ixEthAccDataStats.addToSwQ -
- ixEthAccDataStats.removeFromSwQ;
-
- printf(" Buffers in S/W Qs : %u\n",
- numBuffersInSwQ);
- printf(" Buffers in H/W Qs or NPEs : %u\n",
- totalBuffers - numBuffersInSwQ);
-#endif
-
- printf("Rx QoS Discipline : %s\n",
- (ixEthAccDataInfo.schDiscipline ==
- FIFO_PRIORITY ) ? "Enabled" : "Disabled");
-
- for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
- {
- printf("Tx QoS Discipline port %u : %s\n",
- portId,
- (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline ==
- FIFO_PRIORITY ) ? "Enabled" : "Disabled");
- }
- printf("\n");
-}
-
-
-
-
-
+++ /dev/null
-/**
- * @file IxEthAccMac.c
- *
- * @author Intel Corporation
- * @date
- *
- * @brief MAC control functions
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-#include "IxNpeMh.h"
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
-#include "IxEthDB.h"
-#endif
-#include "IxEthDBPortDefs.h"
-#include "IxEthNpe.h"
-#include "IxEthAcc.h"
-#include "IxEthAccDataPlane_p.h"
-#include "IxEthAcc_p.h"
-#include "IxEthAccMac_p.h"
-
-/* Maximum number of retries during ixEthAccPortDisable, which
- * is approximately 10 seconds
-*/
-#define IX_ETH_ACC_MAX_RETRY 500
-
-/* Maximum number of retries during ixEthAccPortDisable when expecting
- * timeout
- */
-#define IX_ETH_ACC_MAX_RETRY_TIMEOUT 5
-
-#define IX_ETH_ACC_VALIDATE_PORT_ID(portId) \
- do \
- { \
- if(!IX_ETH_ACC_IS_PORT_VALID(portId)) \
- { \
- return IX_ETH_ACC_INVALID_PORT; \
- } \
- } while(0)
-
-PUBLIC IxEthAccMacState ixEthAccMacState[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-PRIVATE UINT32 ixEthAccMacBase[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-/*Forward function declarations*/
-PRIVATE void
-ixEthAccPortDisableRx (IxEthAccPortId portId,
- IX_OSAL_MBUF * mBufPtr,
- BOOL useMultiBufferCallback);
-
-PRIVATE void
-ixEthAccPortDisableRxAndReplenish (IxEthAccPortId portId,
- IX_OSAL_MBUF * mBufPtr,
- BOOL useMultiBufferCallback);
-
-PRIVATE void
-ixEthAccPortDisableTxDone (UINT32 cbTag,
- IX_OSAL_MBUF *mbuf);
-
-PRIVATE void
-ixEthAccPortDisableTxDoneAndSubmit (UINT32 cbTag,
- IX_OSAL_MBUF *mbuf);
-
-PRIVATE void
-ixEthAccPortDisableRxCallback (UINT32 cbTag,
- IX_OSAL_MBUF * mBufPtr,
- UINT32 learnedPortId);
-
-PRIVATE void
-ixEthAccPortDisableMultiBufferRxCallback (UINT32 cbTag,
- IX_OSAL_MBUF **mBufPtr);
-
-PRIVATE IxEthAccStatus
-ixEthAccPortDisableTryTransmit(UINT32 portId);
-
-PRIVATE IxEthAccStatus
-ixEthAccPortDisableTryReplenish(UINT32 portId);
-
-PRIVATE IxEthAccStatus
-ixEthAccPortMulticastMacAddressGet (IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr);
-
-PRIVATE IxEthAccStatus
-ixEthAccPortMulticastMacFilterGet (IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr);
-
-PRIVATE void
-ixEthAccMacNpeStatsMessageCallback (IxNpeMhNpeId npeId,
- IxNpeMhMessage msg);
-
-PRIVATE void
-ixEthAccMacNpeStatsResetMessageCallback (IxNpeMhNpeId npeId,
- IxNpeMhMessage msg);
-
-PRIVATE void
-ixEthAccNpeLoopbackMessageCallback (IxNpeMhNpeId npeId,
- IxNpeMhMessage msg);
-
-PRIVATE void
-ixEthAccMulticastAddressSet(IxEthAccPortId portId);
-
-PRIVATE BOOL
-ixEthAccMacEqual(IxEthAccMacAddr *macAddr1,
- IxEthAccMacAddr *macAddr2);
-
-PRIVATE void
-ixEthAccMacPrint(IxEthAccMacAddr *m);
-
-PRIVATE void
-ixEthAccMacStateUpdate(IxEthAccPortId portId);
-
-IxEthAccStatus
-ixEthAccMacMemInit(void)
-{
- ixEthAccMacBase[IX_ETH_PORT_1] =
- (UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_0_BASE,
- IX_OSAL_IXP400_ETHA_MAP_SIZE);
- ixEthAccMacBase[IX_ETH_PORT_2] =
- (UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_1_BASE,
- IX_OSAL_IXP400_ETHB_MAP_SIZE);
-#ifdef __ixp46X
- ixEthAccMacBase[IX_ETH_PORT_3] =
- (UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_2_BASE,
- IX_OSAL_IXP400_ETH_NPEA_MAP_SIZE);
- if (ixEthAccMacBase[IX_ETH_PORT_3] == 0)
- {
- ixOsalLog(IX_OSAL_LOG_LVL_FATAL,
- IX_OSAL_LOG_DEV_STDOUT,
- "EthAcc: Could not map MAC I/O memory\n",
- 0, 0, 0, 0, 0 ,0);
-
- return IX_ETH_ACC_FAIL;
- }
-#endif
-
- if (ixEthAccMacBase[IX_ETH_PORT_1] == 0
- || ixEthAccMacBase[IX_ETH_PORT_2] == 0)
- {
- ixOsalLog(IX_OSAL_LOG_LVL_FATAL,
- IX_OSAL_LOG_DEV_STDOUT,
- "EthAcc: Could not map MAC I/O memory\n",
- 0, 0, 0, 0, 0 ,0);
-
- return IX_ETH_ACC_FAIL;
- }
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-void
-ixEthAccMacUnload(void)
-{
- IX_OSAL_MEM_UNMAP(ixEthAccMacBase[IX_ETH_PORT_1]);
- IX_OSAL_MEM_UNMAP(ixEthAccMacBase[IX_ETH_PORT_2]);
-#ifdef __ixp46X
- IX_OSAL_MEM_UNMAP(ixEthAccMacBase[IX_ETH_PORT_3]);
- ixEthAccMacBase[IX_ETH_PORT_3] = 0;
-#endif
- ixEthAccMacBase[IX_ETH_PORT_2] = 0;
- ixEthAccMacBase[IX_ETH_PORT_1] = 0;
-}
-
-IxEthAccStatus
-ixEthAccPortEnablePriv(IxEthAccPortId portId)
-{
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable port.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- printf("EthAcc: (Mac) cannot enable port %d, port not initialized\n", portId);
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- if (ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn == NULL)
- {
- /* TxDone callback not registered */
- printf("EthAcc: (Mac) cannot enable port %d, TxDone callback not registered\n", portId);
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- if ((ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn == NULL)
- && (ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn == NULL))
- {
- /* Receive callback not registered */
- printf("EthAcc: (Mac) cannot enable port %d, Rx callback not registered\n", portId);
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- if(!ixEthAccMacState[portId].initDone)
- {
- printf("EthAcc: (Mac) cannot enable port %d, MAC address not set\n", portId);
- return (IX_ETH_ACC_MAC_UNINITIALIZED);
- }
-
- /* if the state is being set to what it is already at, do nothing*/
- if (ixEthAccMacState[portId].enabled)
- {
- return IX_ETH_ACC_SUCCESS;
- }
-
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
- /* enable ethernet database for this port */
- if (ixEthDBPortEnable(portId) != IX_ETH_DB_SUCCESS)
- {
- printf("EthAcc: (Mac) cannot enable port %d, EthDB failure\n", portId);
- return IX_ETH_ACC_FAIL;
- }
-#endif
-
- /* set the MAC core registers */
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL2,
- IX_ETH_ACC_TX_CNTRL2_RETRIES_MASK);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RANDOM_SEED,
- IX_ETH_ACC_RANDOM_SEED_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_THRESH_P_EMPTY,
- IX_ETH_ACC_MAC_THRESH_P_EMPTY_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_THRESH_P_FULL,
- IX_ETH_ACC_MAC_THRESH_P_FULL_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_DEFER,
- IX_ETH_ACC_MAC_TX_DEFER_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_TWO_DEFER_1,
- IX_ETH_ACC_MAC_TX_TWO_DEFER_1_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_TWO_DEFER_2,
- IX_ETH_ACC_MAC_TX_TWO_DEFER_2_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_SLOT_TIME,
- IX_ETH_ACC_MAC_SLOT_TIME_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_INT_CLK_THRESH,
- IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_BUF_SIZE_TX,
- IX_ETH_ACC_MAC_BUF_SIZE_TX_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- IX_ETH_ACC_TX_CNTRL1_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- IX_ETH_ACC_RX_CNTRL1_DEFAULT);
-
- /* set the global state */
- ixEthAccMacState[portId].portDisableState = ACTIVE;
- ixEthAccMacState[portId].enabled = TRUE;
-
- /* rewrite the setup (including mac filtering) depending
- * on current options
- */
- ixEthAccMacStateUpdate(portId);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-/*
- * PortDisable local variables. They contain the intermediate steps
- * while the port is being disabled and the buffers being drained out
- * of the NPE.
- */
-typedef void (*IxEthAccPortDisableRx)(IxEthAccPortId portId,
- IX_OSAL_MBUF * mBufPtr,
- BOOL useMultiBufferCallback);
-static IxEthAccPortRxCallback
-ixEthAccPortDisableFn[IX_ETH_ACC_NUMBER_OF_PORTS];
-static IxEthAccPortMultiBufferRxCallback
-ixEthAccPortDisableMultiBufferFn[IX_ETH_ACC_NUMBER_OF_PORTS];
-static IxEthAccPortDisableRx
-ixEthAccPortDisableRxTable[IX_ETH_ACC_NUMBER_OF_PORTS];
-static UINT32
-ixEthAccPortDisableCbTag[IX_ETH_ACC_NUMBER_OF_PORTS];
-static UINT32
-ixEthAccPortDisableMultiBufferCbTag[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-static IxEthAccPortTxDoneCallback
-ixEthAccPortDisableTxDoneFn[IX_ETH_ACC_NUMBER_OF_PORTS];
-static UINT32
-ixEthAccPortDisableTxDoneCbTag[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-static UINT32
-ixEthAccPortDisableUserBufferCount[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-/*
- * PortDisable private callbacks functions. They handle the user
- * traffic, and the special buffers (one for tx, one for rx) used
- * in portDisable.
- */
-PRIVATE void
-ixEthAccPortDisableTxDone(UINT32 cbTag,
- IX_OSAL_MBUF *mbuf)
-{
- IxEthAccPortId portId = (IxEthAccPortId)cbTag;
- volatile IxEthAccPortDisableState *txState = &ixEthAccMacState[portId].txState;
-
- /* check for the special mbuf used in portDisable */
- if (mbuf == ixEthAccMacState[portId].portDisableTxMbufPtr)
- {
- *txState = TRANSMIT_DONE;
- }
- else
- {
- /* increment the count of user traffic during portDisable */
- ixEthAccPortDisableUserBufferCount[portId]++;
-
- /* call client TxDone function */
- ixEthAccPortDisableTxDoneFn[portId](ixEthAccPortDisableTxDoneCbTag[portId], mbuf);
- }
-}
-
-PRIVATE IxEthAccStatus
-ixEthAccPortDisableTryTransmit(UINT32 portId)
-{
- int key;
- IxEthAccStatus status = IX_ETH_ACC_SUCCESS;
- volatile IxEthAccPortDisableState *txState = &ixEthAccMacState[portId].txState;
- /* transmit the special buffer again if it is transmitted
- * and update the txState
- * This section is protected because the portDisable context
- * run an identical code, so the system keeps transmitting at the
- * maximum rate.
- */
- key = ixOsalIrqLock();
- if (*txState == TRANSMIT_DONE)
- {
- IX_OSAL_MBUF *mbufTxPtr = ixEthAccMacState[portId].portDisableTxMbufPtr;
- *txState = TRANSMIT;
- status = ixEthAccPortTxFrameSubmit(portId,
- mbufTxPtr,
- IX_ETH_ACC_TX_DEFAULT_PRIORITY);
- }
- ixOsalIrqUnlock(key);
-
- return status;
-}
-
-PRIVATE void
-ixEthAccPortDisableTxDoneAndSubmit(UINT32 cbTag,
- IX_OSAL_MBUF *mbuf)
-{
- IxEthAccPortId portId = (IxEthAccPortId)cbTag;
-
- /* call the callback which forwards the traffic to the client */
- ixEthAccPortDisableTxDone(cbTag, mbuf);
-
- /* try to transmit the buffer used in portDisable
- * if seen in TxDone
- */
- ixEthAccPortDisableTryTransmit(portId);
-}
-
-PRIVATE void
-ixEthAccPortDisableRx (IxEthAccPortId portId,
- IX_OSAL_MBUF * mBufPtr,
- BOOL useMultiBufferCallback)
-{
- volatile IxEthAccPortDisableState *rxState = &ixEthAccMacState[portId].rxState;
- IX_OSAL_MBUF *mNextPtr;
-
- while (mBufPtr)
- {
- mNextPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mBufPtr);
- IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mBufPtr) = NULL;
-
- /* check for the special mbuf used in portDisable */
- if (mBufPtr == ixEthAccMacState[portId].portDisableRxMbufPtr)
- {
- *rxState = RECEIVE;
- }
- else
- {
- /* increment the count of user traffic during portDisable */
- ixEthAccPortDisableUserBufferCount[portId]++;
-
- /* reset the received payload length during portDisable */
- IX_OSAL_MBUF_MLEN(mBufPtr) = 0;
- IX_OSAL_MBUF_PKT_LEN(mBufPtr) = 0;
-
- if (useMultiBufferCallback)
- {
- /* call the user callback with one unchained
- * buffer, without payload. A small array is built
- * to be used as a parameter (the user callback expects
- * to receive an array ended by a NULL pointer.
- */
- IX_OSAL_MBUF *mBufPtrArray[2];
-
- mBufPtrArray[0] = mBufPtr;
- mBufPtrArray[1] = NULL;
- ixEthAccPortDisableMultiBufferFn[portId](
- ixEthAccPortDisableMultiBufferCbTag[portId],
- mBufPtrArray);
- }
- else
- {
- /* call the user callback with a unchained
- * buffer, without payload and the destination port is
- * unknown.
- */
- ixEthAccPortDisableFn[portId](
- ixEthAccPortDisableCbTag[portId],
- mBufPtr,
- IX_ETH_DB_UNKNOWN_PORT /* port not found */);
- }
- }
-
- mBufPtr = mNextPtr;
- }
-}
-
-PRIVATE IxEthAccStatus
-ixEthAccPortDisableTryReplenish(UINT32 portId)
-{
- int key;
- IxEthAccStatus status = IX_ETH_ACC_SUCCESS;
- volatile IxEthAccPortDisableState *rxState = &ixEthAccMacState[portId].rxState;
- /* replenish with the special buffer again if it is received
- * and update the rxState
- * This section is protected because the portDisable context
- * run an identical code, so the system keeps replenishing at the
- * maximum rate.
- */
- key = ixOsalIrqLock();
- if (*rxState == RECEIVE)
- {
- IX_OSAL_MBUF *mbufRxPtr = ixEthAccMacState[portId].portDisableRxMbufPtr;
- *rxState = REPLENISH;
- IX_OSAL_MBUF_MLEN(mbufRxPtr) = IX_ETHACC_RX_MBUF_MIN_SIZE;
- status = ixEthAccPortRxFreeReplenish(portId, mbufRxPtr);
- }
- ixOsalIrqUnlock(key);
-
- return status;
-}
-
-PRIVATE void
-ixEthAccPortDisableRxAndReplenish (IxEthAccPortId portId,
- IX_OSAL_MBUF * mBufPtr,
- BOOL useMultiBufferCallback)
-{
- /* call the callback which forwards the traffic to the client */
- ixEthAccPortDisableRx(portId, mBufPtr, useMultiBufferCallback);
-
- /* try to replenish with the buffer used in portDisable
- * if seen in Rx
- */
- ixEthAccPortDisableTryReplenish(portId);
-}
-
-PRIVATE void
-ixEthAccPortDisableRxCallback (UINT32 cbTag,
- IX_OSAL_MBUF * mBufPtr,
- UINT32 learnedPortId)
-{
- IxEthAccPortId portId = (IxEthAccPortId)cbTag;
-
- /* call the portDisable receive callback */
- (ixEthAccPortDisableRxTable[portId])(portId, mBufPtr, FALSE);
-}
-
-PRIVATE void
-ixEthAccPortDisableMultiBufferRxCallback (UINT32 cbTag,
- IX_OSAL_MBUF **mBufPtr)
-{
- IxEthAccPortId portId = (IxEthAccPortId)cbTag;
-
- while (*mBufPtr)
- {
- /* call the portDisable receive callback with one buffer at a time */
- (ixEthAccPortDisableRxTable[portId])(portId, *mBufPtr++, TRUE);
- }
-}
-
-IxEthAccStatus
-ixEthAccPortDisablePriv(IxEthAccPortId portId)
-{
- IxEthAccStatus status = IX_ETH_ACC_SUCCESS;
- int key;
- int retry, retryTimeout;
- volatile IxEthAccPortDisableState *state = &ixEthAccMacState[portId].portDisableState;
- volatile IxEthAccPortDisableState *rxState = &ixEthAccMacState[portId].rxState;
- volatile IxEthAccPortDisableState *txState = &ixEthAccMacState[portId].txState;
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot disable port.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /* if the state is being set to what it is already at, do nothing */
- if (!ixEthAccMacState[portId].enabled)
- {
- return IX_ETH_ACC_SUCCESS;
- }
-
- *state = DISABLED;
-
- /* disable MAC receive first */
- ixEthAccPortRxDisablePriv(portId);
-
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
- /* disable ethernet database for this port - It is done now to avoid
- * issuing ELT maintenance after requesting 'port disable' in an NPE
- */
- if (ixEthDBPortDisable(portId) != IX_ETH_DB_SUCCESS)
- {
- status = IX_ETH_ACC_FAIL;
- IX_ETH_ACC_FATAL_LOG("ixEthAccPortDisable: failed to disable EthDB for this port\n", 0, 0, 0, 0, 0, 0);
- }
-#endif
-
- /* enter the critical section */
- key = ixOsalIrqLock();
-
- /* swap the Rx and TxDone callbacks */
- ixEthAccPortDisableFn[portId] = ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn;
- ixEthAccPortDisableMultiBufferFn[portId] = ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn;
- ixEthAccPortDisableCbTag[portId] = ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag;
- ixEthAccPortDisableMultiBufferCbTag[portId] = ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackTag;
- ixEthAccPortDisableTxDoneFn[portId] = ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn;
- ixEthAccPortDisableTxDoneCbTag[portId] = ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag;
- ixEthAccPortDisableRxTable[portId] = ixEthAccPortDisableRx;
-
- /* register temporary callbacks */
- ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn = ixEthAccPortDisableRxCallback;
- ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag = portId;
-
- ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn = ixEthAccPortDisableMultiBufferRxCallback;
- ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackTag = portId;
-
- ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn = ixEthAccPortDisableTxDone;
- ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag = portId;
-
- /* initialise the Rx state and Tx states */
- *txState = TRANSMIT_DONE;
- *rxState = RECEIVE;
-
- /* exit the critical section */
- ixOsalIrqUnlock(key);
-
- /* enable a NPE loopback */
- if (ixEthAccNpeLoopbackEnablePriv(portId) != IX_ETH_ACC_SUCCESS)
- {
- status = IX_ETH_ACC_FAIL;
- }
-
- if (status == IX_ETH_ACC_SUCCESS)
- {
- retry = 0;
-
- /* Step 1 : Drain Tx traffic and TxDone queues :
- *
- * Transmit and replenish at least once with the
- * special buffers until both of them are seen
- * in the callback hook
- *
- * (the receive callback keeps replenishing, so once we see
- * the special Tx buffer, we can be sure that Tx drain is complete)
- */
- ixEthAccPortDisableRxTable[portId]
- = ixEthAccPortDisableRxAndReplenish;
- ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn
- = ixEthAccPortDisableTxDone;
-
- do
- {
- /* keep replenishing */
- status = ixEthAccPortDisableTryReplenish(portId);
- if (status == IX_ETH_ACC_SUCCESS)
- {
- /* keep transmitting */
- status = ixEthAccPortDisableTryTransmit(portId);
- }
- if (status == IX_ETH_ACC_SUCCESS)
- {
- /* wait for some traffic being processed */
- ixOsalSleep(IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS);
- }
- }
- while ((status == IX_ETH_ACC_SUCCESS)
- && (retry++ < IX_ETH_ACC_MAX_RETRY)
- && (*txState == TRANSMIT));
-
- /* Step 2 : Drain Rx traffic, RxFree and Rx queues :
- *
- * Transmit and replenish at least once with the
- * special buffers until both of them are seen
- * in the callback hook
- * (the transmit callback keeps transmitting, and when we see
- * the special Rx buffer, we can be sure that rxFree drain
- * is complete)
- *
- * The nested loop helps to retry if the user was keeping
- * replenishing or transmitting during portDisable.
- *
- * The 2 nested loops ensure more retries if user traffic is
- * seen during portDisable : the user should not replenish
- * or transmit while portDisable is running. However, because of
- * the queueing possibilities in ethAcc dataplane, it is possible
- * that a lot of traffic is left in the queues (e.g. when
- * transmitting over a low speed link) and therefore, more
- * retries are allowed to help flushing the buffers out.
- */
- ixEthAccPortDisableRxTable[portId]
- = ixEthAccPortDisableRx;
- ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn
- = ixEthAccPortDisableTxDoneAndSubmit;
-
- do
- {
- do
- {
- ixEthAccPortDisableUserBufferCount[portId] = 0;
-
- /* keep replenishing */
- status = ixEthAccPortDisableTryReplenish(portId);
- if (status == IX_ETH_ACC_SUCCESS)
- {
- /* keep transmitting */
- status = ixEthAccPortDisableTryTransmit(portId);
- }
- if (status == IX_ETH_ACC_SUCCESS)
- {
- /* wait for some traffic being processed */
- ixOsalSleep(IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS);
- }
- }
- while ((status == IX_ETH_ACC_SUCCESS)
- && (retry++ < IX_ETH_ACC_MAX_RETRY)
- && ((ixEthAccPortDisableUserBufferCount[portId] != 0)
- || (*rxState == REPLENISH)));
-
- /* After the first iteration, change the receive callbacks,
- * to process only 1 buffer at a time
- */
- ixEthAccPortDisableRxTable[portId]
- = ixEthAccPortDisableRx;
- ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn
- = ixEthAccPortDisableTxDone;
-
- /* repeat the whole process while user traffic is seen in TxDone
- *
- * The conditions to stop the loop are
- * - Xscale has both Rx and Tx special buffers
- * (txState = transmit, rxState = receive)
- * - any error in txSubmit or rxReplenish
- * - no user traffic seen
- * - an excessive amount of retries
- */
- }
- while ((status == IX_ETH_ACC_SUCCESS)
- && (retry < IX_ETH_ACC_MAX_RETRY)
- && (*txState == TRANSMIT));
-
- /* check the loop exit conditions. The NPE should not hold
- * the special buffers.
- */
- if ((*rxState == REPLENISH) || (*txState == TRANSMIT))
- {
- status = IX_ETH_ACC_FAIL;
- }
-
- if (status == IX_ETH_ACC_SUCCESS)
- {
- /* Step 3 : Replenish without transmitting until a timeout
- * occurs, in order to drain the internal NPE fifos
- *
- * we can expect a few frames srill held
- * in the NPE.
- *
- * The 2 nested loops take care about the NPE dropping traffic
- * (including loopback traffic) when the Rx queue is full.
- *
- * The timeout value is very conservative
- * since the loopback used keeps replenishhing.
- *
- */
- do
- {
- ixEthAccPortDisableRxTable[portId] = ixEthAccPortDisableRxAndReplenish;
- ixEthAccPortDisableUserBufferCount[portId] = 0;
- retryTimeout = 0;
- do
- {
- /* keep replenishing */
- status = ixEthAccPortDisableTryReplenish(portId);
- if (status == IX_ETH_ACC_SUCCESS)
- {
- /* wait for some traffic being processed */
- ixOsalSleep(IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS);
- }
- }
- while ((status == IX_ETH_ACC_SUCCESS)
- && (retryTimeout++ < IX_ETH_ACC_MAX_RETRY_TIMEOUT));
-
- /* Step 4 : Transmit once. Stop replenish
- *
- * After the Rx timeout, we are sure that the NPE does not
- * hold any frame in its internal NPE fifos.
- *
- * At this point, the NPE still holds the last rxFree buffer.
- * By transmitting a single frame, this should unblock the
- * last rxFree buffer. This code just transmit once and
- * wait for both frames seen in TxDone and in rxFree.
- *
- */
- ixEthAccPortDisableRxTable[portId] = ixEthAccPortDisableRx;
- status = ixEthAccPortDisableTryTransmit(portId);
-
- /* the NPE should immediatelyt release
- * the last Rx buffer and the last transmitted buffer
- * unless the last Tx frame was dropped (rx queue full)
- */
- if (status == IX_ETH_ACC_SUCCESS)
- {
- retryTimeout = 0;
- do
- {
- ixOsalSleep(IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS);
- }
- while ((*rxState == REPLENISH)
- && (retryTimeout++ < IX_ETH_ACC_MAX_RETRY_TIMEOUT));
- }
-
- /* the NPE may have dropped the traffic because of Rx
- * queue being full. This code ensures that the last
- * Tx and Rx frames are both received.
- */
- }
- while ((status == IX_ETH_ACC_SUCCESS)
- && (retry++ < IX_ETH_ACC_MAX_RETRY)
- && ((*txState == TRANSMIT)
- || (*rxState == REPLENISH)
- || (ixEthAccPortDisableUserBufferCount[portId] != 0)));
-
- /* Step 5 : check the final states : the NPE has
- * no buffer left, nor in Tx , nor in Rx directions.
- */
- if ((*rxState == REPLENISH) || (*txState == TRANSMIT))
- {
- status = IX_ETH_ACC_FAIL;
- }
- }
-
- /* now all the buffers are drained, disable NPE loopback
- * This is done regardless of the logic to drain the queues and
- * the internal buffers held by the NPE.
- */
- if (ixEthAccNpeLoopbackDisablePriv(portId) != IX_ETH_ACC_SUCCESS)
- {
- status = IX_ETH_ACC_FAIL;
- }
- }
-
- /* disable MAC Tx and Rx services */
- ixEthAccMacState[portId].enabled = FALSE;
- ixEthAccMacStateUpdate(portId);
-
- /* restore the Rx and TxDone callbacks (within a critical section) */
- key = ixOsalIrqLock();
-
- ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn = ixEthAccPortDisableFn[portId];
- ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag = ixEthAccPortDisableCbTag[portId];
- ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn = ixEthAccPortDisableMultiBufferFn[portId];
- ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackTag = ixEthAccPortDisableMultiBufferCbTag[portId];
- ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn = ixEthAccPortDisableTxDoneFn[portId];
- ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag = ixEthAccPortDisableTxDoneCbTag[portId];
-
- ixOsalIrqUnlock(key);
-
- /* the MAC core rx/tx disable may left the MAC hardware in an
- * unpredictable state. A hw reset is executed before resetting
- * all the MAC parameters to a known value.
- */
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_CORE_CNTRL,
- IX_ETH_ACC_CORE_RESET);
-
- ixOsalSleep(IX_ETH_ACC_MAC_RESET_DELAY);
-
- /* rewrite all parameters to their current value */
- ixEthAccMacStateUpdate(portId);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_INT_CLK_THRESH,
- IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_CORE_CNTRL,
- IX_ETH_ACC_CORE_MDC_EN);
-
- return status;
-}
-
-IxEthAccStatus
-ixEthAccPortEnabledQueryPriv(IxEthAccPortId portId, BOOL *enabled)
-{
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable port.\n",(INT32)portId,0,0,0,0,0);
-
- /* Since Eth NPE is not available, port must be disabled */
- *enabled = FALSE ;
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- /* Since Eth NPE is not available, port must be disabled */
- *enabled = FALSE ;
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- *enabled = ixEthAccMacState[portId].enabled;
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortMacResetPriv(IxEthAccPortId portId)
-{
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot reset Ethernet coprocessor.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_CORE_CNTRL,
- IX_ETH_ACC_CORE_RESET);
-
- ixOsalSleep(IX_ETH_ACC_MAC_RESET_DELAY);
-
- /* rewrite all parameters to their current value */
- ixEthAccMacStateUpdate(portId);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_INT_CLK_THRESH,
- IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_CORE_CNTRL,
- IX_ETH_ACC_CORE_MDC_EN);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortLoopbackEnable(IxEthAccPortId portId)
-{
- UINT32 regval;
-
- /* Turn off promiscuous mode */
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable loopback.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /* read register */
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval);
-
- /* update register */
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval | IX_ETH_ACC_RX_CNTRL1_LOOP_EN);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-PRIVATE void
-ixEthAccNpeLoopbackMessageCallback (IxNpeMhNpeId npeId,
- IxNpeMhMessage msg)
-{
- IxEthAccPortId portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);
-
-#ifndef NDEBUG
- /* Prudent to at least check the port is within range */
- if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS)
- {
- IX_ETH_ACC_FATAL_LOG("IXETHACC:ixEthAccPortDisableMessageCallback: Illegal port: %u\n",
- (UINT32) portId, 0, 0, 0, 0, 0);
-
- return;
- }
-#endif
-
- /* unlock message reception mutex */
- ixOsalMutexUnlock(&ixEthAccMacState[portId].npeLoopbackMessageLock);
-}
-
-IxEthAccStatus
-ixEthAccNpeLoopbackEnablePriv(IxEthAccPortId portId)
-{
- IX_STATUS npeMhStatus;
- IxNpeMhMessage message;
- IxEthAccStatus status = IX_ETH_ACC_SUCCESS;
-
- /* Turn off promiscuous mode */
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable NPE loopback.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /* enable NPE loopback (lsb of the message contains the value 1) */
- message.data[0] = (IX_ETHNPE_SETLOOPBACK_MODE << IX_ETH_ACC_MAC_MSGID_SHL)
- | 0x01;
- message.data[1] = 0;
-
- npeMhStatus = ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId),
- message,
- IX_ETHNPE_SETLOOPBACK_MODE_ACK,
- ixEthAccNpeLoopbackMessageCallback,
- IX_NPEMH_SEND_RETRIES_DEFAULT);
-
- if (npeMhStatus != IX_SUCCESS)
- {
- status = IX_ETH_ACC_FAIL;
- }
- else
- {
- /* wait for NPE loopbackEnable response */
- if (ixOsalMutexLock(&ixEthAccMacState[portId]. npeLoopbackMessageLock,
- IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS)
- != IX_SUCCESS)
- {
- status = IX_ETH_ACC_FAIL;
- }
- }
-
- return status;
-}
-
-IxEthAccStatus
-ixEthAccPortTxEnablePriv(IxEthAccPortId portId)
-{
- UINT32 regval;
-
- /* Turn off promiscuous mode */
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable TX.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /* read register */
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval);
-
- /* update register */
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval | IX_ETH_ACC_TX_CNTRL1_TX_EN);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortRxEnablePriv(IxEthAccPortId portId)
-{
- UINT32 regval;
-
- /* Turn off promiscuous mode */
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable RX.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /* read register */
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval);
-
- /* update register */
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval | IX_ETH_ACC_RX_CNTRL1_RX_EN);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortLoopbackDisable(IxEthAccPortId portId)
-{
- UINT32 regval;
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot disable loopback.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /*disable MAC loopabck */
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- (regval & ~IX_ETH_ACC_RX_CNTRL1_LOOP_EN));
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccNpeLoopbackDisablePriv(IxEthAccPortId portId)
-{
- IX_STATUS npeMhStatus;
- IxNpeMhMessage message;
- IxEthAccStatus status = IX_ETH_ACC_SUCCESS;
-
- /* Turn off promiscuous mode */
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable NPE loopback.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /* disable NPE loopback (lsb of the message contains the value 0) */
- message.data[0] = (IX_ETHNPE_SETLOOPBACK_MODE << IX_ETH_ACC_MAC_MSGID_SHL);
- message.data[1] = 0;
-
- npeMhStatus = ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId),
- message,
- IX_ETHNPE_SETLOOPBACK_MODE_ACK,
- ixEthAccNpeLoopbackMessageCallback,
- IX_NPEMH_SEND_RETRIES_DEFAULT);
-
- if (npeMhStatus != IX_SUCCESS)
- {
- status = IX_ETH_ACC_FAIL;
- }
- else
- {
- /* wait for NPE loopbackEnable response */
- if (ixOsalMutexLock(&ixEthAccMacState[portId].npeLoopbackMessageLock,
- IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS)
- != IX_SUCCESS)
- {
- status = IX_ETH_ACC_FAIL;
- }
- }
-
- return status;
-}
-
-IxEthAccStatus
-ixEthAccPortTxDisablePriv(IxEthAccPortId portId)
-{
- UINT32 regval;
-
- /* Turn off promiscuous mode */
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot disable TX.\n", (INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /* read register */
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval);
-
- /* update register */
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- (regval & ~IX_ETH_ACC_TX_CNTRL1_TX_EN));
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortRxDisablePriv(IxEthAccPortId portId)
-{
- UINT32 regval;
-
- /* Turn off promiscuous mode */
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot disable RX.\n", (INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /* read register */
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval);
-
- /* update register */
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- (regval & ~IX_ETH_ACC_RX_CNTRL1_RX_EN));
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortPromiscuousModeClearPriv(IxEthAccPortId portId)
-{
- UINT32 regval;
-
- /* Turn off promiscuous mode */
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot clear promiscuous mode.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /*set bit 5 of Rx control 1 - enable address filtering*/
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval | IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN);
-
- ixEthAccMacState[portId].promiscuous = FALSE;
-
- ixEthAccMulticastAddressSet(portId);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortPromiscuousModeSetPriv(IxEthAccPortId portId)
-{
- UINT32 regval;
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot set promiscuous mode.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /*
- * Set bit 5 of Rx control 1 - We enable address filtering even in
- * promiscuous mode because we want the MAC to set the appropriate
- * bits in m_flags which doesn't happen if we turn off filtering.
- */
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval | IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN);
-
- ixEthAccMacState[portId].promiscuous = TRUE;
-
- ixEthAccMulticastAddressSet(portId);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortUnicastMacAddressSetPriv (IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr)
-{
- UINT32 i;
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot set Unicast Mac Address.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
-
- if (macAddr == NULL)
- {
- return IX_ETH_ACC_FAIL;
- }
-
- if ( macAddr->macAddress[0] & IX_ETH_ACC_ETH_MAC_BCAST_MCAST_BIT )
- {
- /* This is a multicast/broadcast address cant set it ! */
- return IX_ETH_ACC_FAIL;
- }
-
- if ( macAddr->macAddress[0] == 0 &&
- macAddr->macAddress[1] == 0 &&
- macAddr->macAddress[2] == 0 &&
- macAddr->macAddress[3] == 0 &&
- macAddr->macAddress[4] == 0 &&
- macAddr->macAddress[5] == 0 )
- {
- /* This is an invalid mac address cant set it ! */
- return IX_ETH_ACC_FAIL;
- }
-
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
- /* update the MAC address in the ethernet database */
- if (ixEthDBPortAddressSet(portId, (IxEthDBMacAddr *) macAddr) != IX_ETH_DB_SUCCESS)
- {
- return IX_ETH_ACC_FAIL;
- }
-#endif
-
- /*Set the Unicast MAC to the specified value*/
- for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
- {
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_UNI_ADDR_1 + i*sizeof(UINT32),
- macAddr->macAddress[i]);
- }
- ixEthAccMacState[portId].initDone = TRUE;
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortUnicastMacAddressGetPriv (IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr)
-{
- /*Return the current value of the Unicast MAC from h/w
- for the specified port*/
- UINT32 i;
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot get Unicast Mac Address.\n",(INT32)portId,0,0,0,0,0);
- /* Since Eth Npe is unavailable, return invalid MAC Address = 00:00:00:00:00:00 */
- for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
- {
- macAddr->macAddress[i] = 0;
- }
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if(!ixEthAccMacState[portId].initDone)
- {
- return (IX_ETH_ACC_MAC_UNINITIALIZED);
- }
-
- if (macAddr == NULL)
- {
- return IX_ETH_ACC_FAIL;
- }
-
-
- for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
- {
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_UNI_ADDR_1 + i*sizeof(UINT32),
- macAddr->macAddress[i]);
- }
- return IX_ETH_ACC_SUCCESS;
-}
-
-PRIVATE IxEthAccStatus
-ixEthAccPortMulticastMacAddressGet (IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr)
-{
- /*Return the current value of the Multicast MAC from h/w
- for the specified port*/
- UINT32 i;
-
- for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
- {
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_ADDR_1 + i*sizeof(UINT32),
- macAddr->macAddress[i]);
- }
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-PRIVATE IxEthAccStatus
-ixEthAccPortMulticastMacFilterGet (IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr)
-{
- /*Return the current value of the Multicast MAC from h/w
- for the specified port*/
- UINT32 i;
-
- for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
- {
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_ADDR_MASK_1 + i*sizeof(UINT32),
- macAddr->macAddress[i]);
- }
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortMulticastAddressJoinPriv (IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr)
-{
- UINT32 i;
- IxEthAccMacAddr broadcastAddr = {{0xff,0xff,0xff,0xff,0xff,0xff}};
-
- /*Check that the port parameter is valid*/
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot join Multicast Mac Address.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /*Check that the mac address is valid*/
- if(macAddr == NULL)
- {
- return IX_ETH_ACC_FAIL;
- }
-
- /* Check that this is a multicast address */
- if (!(macAddr->macAddress[0] & IX_ETH_ACC_ETH_MAC_BCAST_MCAST_BIT))
- {
- return IX_ETH_ACC_FAIL;
- }
-
- /* We don't add the Broadcast address */
- if(ixEthAccMacEqual(&broadcastAddr, macAddr))
- {
- return IX_ETH_ACC_FAIL;
- }
-
- for (i = 0;
- i<ixEthAccMacState[portId].mcastAddrIndex;
- i++)
- {
- /*Check if the current entry already match an existing matches*/
- if(ixEthAccMacEqual(&ixEthAccMacState[portId].mcastAddrsTable[i], macAddr))
- {
- /* Address found in the list and already configured,
- * return a success status
- */
- return IX_ETH_ACC_SUCCESS;
- }
- }
-
- /* check for availability at the end of the current table */
- if(ixEthAccMacState[portId].mcastAddrIndex >= IX_ETH_ACC_MAX_MULTICAST_ADDRESSES)
- {
- return IX_ETH_ACC_FAIL;
- }
-
- /*First add the address to the multicast table for the
- specified port*/
- i=ixEthAccMacState[portId].mcastAddrIndex;
-
- memcpy(&ixEthAccMacState[portId].mcastAddrsTable[i],
- &macAddr->macAddress,
- IX_IEEE803_MAC_ADDRESS_SIZE);
-
- /*Increment the index into the table, this must be done here
- as MulticastAddressSet below needs to know about the latest
- entry.
- */
- ixEthAccMacState[portId].mcastAddrIndex++;
-
- /*Then calculate the new value to be written to the address and
- address mask registers*/
- ixEthAccMulticastAddressSet(portId);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-
-IxEthAccStatus
-ixEthAccPortMulticastAddressJoinAllPriv (IxEthAccPortId portId)
-{
- IxEthAccMacAddr mcastMacAddr = {{0x1,0x0,0x0,0x0,0x0,0x0}};
-
- /*Check that the port parameter is valid*/
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot join all Multicast Address.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /* remove all entries from the database and
- * insert a multicast entry
- */
- memcpy(&ixEthAccMacState[portId].mcastAddrsTable[0],
- &mcastMacAddr.macAddress,
- IX_IEEE803_MAC_ADDRESS_SIZE);
-
- ixEthAccMacState[portId].mcastAddrIndex = 1;
- ixEthAccMacState[portId].joinAll = TRUE;
-
- ixEthAccMulticastAddressSet(portId);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortMulticastAddressLeavePriv (IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr)
-{
- UINT32 i;
- IxEthAccMacAddr mcastMacAddr = {{0x1,0x0,0x0,0x0,0x0,0x0}};
-
- /*Check that the port parameter is valid*/
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot leave Multicast Address.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /*Check that the mac address is valid*/
- if(macAddr == NULL)
- {
- return IX_ETH_ACC_FAIL;
- }
- /* Remove this mac address from the mask for the specified port
- * we copy down all entries above the blanked entry, and
- * decrement the index
- */
- i=0;
-
- while(i<ixEthAccMacState[portId].mcastAddrIndex)
- {
- /*Check if the current entry matches*/
- if(ixEthAccMacEqual(&ixEthAccMacState[portId].mcastAddrsTable[i],
- macAddr))
- {
- if(ixEthAccMacEqual(macAddr, &mcastMacAddr))
- {
- ixEthAccMacState[portId].joinAll = FALSE;
- }
- /*Decrement the index into the multicast address table
- for the current port*/
- ixEthAccMacState[portId].mcastAddrIndex--;
-
- /*Copy down all entries above the current entry*/
- while(i<ixEthAccMacState[portId].mcastAddrIndex)
- {
- memcpy(&ixEthAccMacState[portId].mcastAddrsTable[i],
- &ixEthAccMacState[portId].mcastAddrsTable[i+1],
- IX_IEEE803_MAC_ADDRESS_SIZE);
- i++;
- }
- /*recalculate the mask and write it to the MAC*/
- ixEthAccMulticastAddressSet(portId);
-
- return IX_ETH_ACC_SUCCESS;
- }
- /* search the next entry */
- i++;
- }
- /* no matching entry found */
- return IX_ETH_ACC_NO_SUCH_ADDR;
-}
-
-IxEthAccStatus
-ixEthAccPortMulticastAddressLeaveAllPriv (IxEthAccPortId portId)
-{
- /*Check that the port parameter is valid*/
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot leave all Multicast Address.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- ixEthAccMacState[portId].mcastAddrIndex = 0;
- ixEthAccMacState[portId].joinAll = FALSE;
-
- ixEthAccMulticastAddressSet(portId);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-
-IxEthAccStatus
-ixEthAccPortUnicastAddressShowPriv (IxEthAccPortId portId)
-{
- IxEthAccMacAddr macAddr;
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot show Unicast Address.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /*Get the MAC (UINICAST) address from hardware*/
- if(ixEthAccPortUnicastMacAddressGetPriv(portId, &macAddr) != IX_ETH_ACC_SUCCESS)
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: MAC address uninitialised port %u\n",
- (INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_MAC_UNINITIALIZED;
- }
-
- /*print it out*/
- ixEthAccMacPrint(&macAddr);
- printf("\n");
- return IX_ETH_ACC_SUCCESS;
-}
-
-
-
-void
-ixEthAccPortMulticastAddressShowPriv(IxEthAccPortId portId)
-{
- IxEthAccMacAddr macAddr;
- UINT32 i;
-
- if(!IX_ETH_ACC_IS_PORT_VALID(portId))
- {
- return;
- }
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot show Multicast Address.\n",(INT32)portId,0,0,0,0,0);
- return ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return;
- }
-
- printf("Multicast MAC: ");
- /*Get the MAC (MULTICAST) address from hardware*/
- ixEthAccPortMulticastMacAddressGet(portId, &macAddr);
- /*print it out*/
- ixEthAccMacPrint(&macAddr);
- /*Get the MAC (MULTICAST) filter from hardware*/
- ixEthAccPortMulticastMacFilterGet(portId, &macAddr);
- /*print it out*/
- printf(" ( ");
- ixEthAccMacPrint(&macAddr);
- printf(" )\n");
- printf("Constituent Addresses:\n");
- for(i=0;i<ixEthAccMacState[portId].mcastAddrIndex;i++)
- {
- ixEthAccMacPrint(&ixEthAccMacState[portId].mcastAddrsTable[i]);
- printf("\n");
- }
- return;
-}
-
-/*Set the duplex mode*/
-IxEthAccStatus
-ixEthAccPortDuplexModeSetPriv (IxEthAccPortId portId,
- IxEthAccDuplexMode mode)
-{
- UINT32 txregval;
- UINT32 rxregval;
-
- /*This is bit 1 of the transmit control reg, set to 1 for half
- duplex, 0 for full duplex*/
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot set Duplex Mode.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- txregval);
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- rxregval);
-
- if (mode == IX_ETH_ACC_FULL_DUPLEX)
- {
- /*Clear half duplex bit in TX*/
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- txregval & ~IX_ETH_ACC_TX_CNTRL1_DUPLEX);
-
- /*We must set the pause enable in the receive logic when in
- full duplex mode*/
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- rxregval | IX_ETH_ACC_RX_CNTRL1_PAUSE_EN);
- ixEthAccMacState[portId].fullDuplex = TRUE;
-
- }
- else if (mode == IX_ETH_ACC_HALF_DUPLEX)
- {
- /*Set half duplex bit in TX*/
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- txregval | IX_ETH_ACC_TX_CNTRL1_DUPLEX);
-
- /*We must clear pause enable in the receive logic when in
- half duplex mode*/
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- rxregval & ~IX_ETH_ACC_RX_CNTRL1_PAUSE_EN);
-
- ixEthAccMacState[portId].fullDuplex = FALSE;
- }
- else
- {
- return IX_ETH_ACC_FAIL;
- }
-
-
- return IX_ETH_ACC_SUCCESS;
-
-}
-
-
-
-IxEthAccStatus
-ixEthAccPortDuplexModeGetPriv (IxEthAccPortId portId,
- IxEthAccDuplexMode *mode)
-{
- /*Return the duplex mode for the specified port*/
- UINT32 regval;
-
- /*This is bit 1 of the transmit control reg, set to 1 for half
- duplex, 0 for full duplex*/
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot get Duplex Mode.\n",(INT32)portId,0,0,0,0,0);
- /* return hald duplex */
- *mode = IX_ETH_ACC_HALF_DUPLEX ;
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- if (mode == NULL)
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval);
-
- if( regval & IX_ETH_ACC_TX_CNTRL1_DUPLEX)
- {
- *mode = IX_ETH_ACC_HALF_DUPLEX;
- }
- else
- {
- *mode = IX_ETH_ACC_FULL_DUPLEX;
- }
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-
-
-IxEthAccStatus
-ixEthAccPortTxFrameAppendPaddingEnablePriv (IxEthAccPortId portId)
-{
- UINT32 regval;
- /*Enable FCS computation by the MAC and appending to the
- frame*/
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable Tx Frame Append Padding.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval |
- IX_ETH_ACC_TX_CNTRL1_PAD_EN);
-
- ixEthAccMacState[portId].txPADAppend = TRUE;
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortTxFrameAppendPaddingDisablePriv (IxEthAccPortId portId)
-{
- UINT32 regval;
-
- /*disable FCS computation and appending*/
- /*Set bit 4 of Tx control register one to zero*/
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot disble Tx Frame Append Padding.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval & ~IX_ETH_ACC_TX_CNTRL1_PAD_EN);
-
- ixEthAccMacState[portId].txPADAppend = FALSE;
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortTxFrameAppendFCSEnablePriv (IxEthAccPortId portId)
-{
- UINT32 regval;
-
- /*Enable FCS computation by the MAC and appending to the
- frame*/
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable Tx Frame Append FCS.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval | IX_ETH_ACC_TX_CNTRL1_FCS_EN);
-
- ixEthAccMacState[portId].txFCSAppend = TRUE;
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortTxFrameAppendFCSDisablePriv (IxEthAccPortId portId)
-{
- UINT32 regval;
-
- /*disable FCS computation and appending*/
- /*Set bit 4 of Tx control register one to zero*/
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot disable Tx Frame Append FCS.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval & ~IX_ETH_ACC_TX_CNTRL1_FCS_EN);
-
- ixEthAccMacState[portId].txFCSAppend = FALSE;
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortRxFrameAppendFCSEnablePriv (IxEthAccPortId portId)
-{
- /*Set bit 2 of Rx control 1*/
- UINT32 regval;
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable Rx Frame Append FCS.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval | IX_ETH_ACC_RX_CNTRL1_CRC_EN);
-
- ixEthAccMacState[portId].rxFCSAppend = TRUE;
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortRxFrameAppendFCSDisablePriv (IxEthAccPortId portId)
-{
- UINT32 regval;
-
- /*Clear bit 2 of Rx control 1*/
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot disable Rx Frame Append FCS.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval & ~IX_ETH_ACC_RX_CNTRL1_CRC_EN);
-
- ixEthAccMacState[portId].rxFCSAppend = FALSE;
- return IX_ETH_ACC_SUCCESS;
-}
-
-
-
-PRIVATE void
-ixEthAccMacNpeStatsMessageCallback (IxNpeMhNpeId npeId,
- IxNpeMhMessage msg)
-{
- IxEthAccPortId portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);
-
-#ifndef NDEBUG
- /* Prudent to at least check the port is within range */
- if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS)
- {
- IX_ETH_ACC_FATAL_LOG(
- "IXETHACC:ixEthAccMacNpeStatsMessageCallback: Illegal port: %u\n",
- (UINT32)portId, 0, 0, 0, 0, 0);
- return;
- }
-#endif
-
- /*Unblock Stats Get call*/
- ixOsalMutexUnlock(&ixEthAccMacState[portId].ackMIBStatsLock);
-
-}
-
-PRIVATE void
-ixEthAccMibIIStatsEndianConvert (IxEthEthObjStats *retStats)
-{
- /* endianness conversion */
-
- /* Rx stats */
- retStats->dot3StatsAlignmentErrors =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsAlignmentErrors);
- retStats->dot3StatsFCSErrors =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsFCSErrors);
- retStats->dot3StatsInternalMacReceiveErrors =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsInternalMacReceiveErrors);
- retStats->RxOverrunDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxOverrunDiscards);
- retStats->RxLearnedEntryDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxLearnedEntryDiscards);
- retStats->RxLargeFramesDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxLargeFramesDiscards);
- retStats->RxSTPBlockedDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxSTPBlockedDiscards);
- retStats->RxVLANTypeFilterDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxVLANTypeFilterDiscards);
- retStats->RxVLANIdFilterDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxVLANIdFilterDiscards);
- retStats->RxInvalidSourceDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxInvalidSourceDiscards);
- retStats->RxBlackListDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxBlackListDiscards);
- retStats->RxWhiteListDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxWhiteListDiscards);
- retStats->RxUnderflowEntryDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxUnderflowEntryDiscards);
-
- /* Tx stats */
- retStats->dot3StatsSingleCollisionFrames =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsSingleCollisionFrames);
- retStats->dot3StatsMultipleCollisionFrames =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsMultipleCollisionFrames);
- retStats->dot3StatsDeferredTransmissions =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsDeferredTransmissions);
- retStats->dot3StatsLateCollisions =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsLateCollisions);
- retStats->dot3StatsExcessiveCollsions =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsExcessiveCollsions);
- retStats->dot3StatsInternalMacTransmitErrors =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsInternalMacTransmitErrors);
- retStats->dot3StatsCarrierSenseErrors =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsCarrierSenseErrors);
- retStats->TxLargeFrameDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->TxLargeFrameDiscards);
- retStats->TxVLANIdFilterDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->TxVLANIdFilterDiscards);
-}
-
-IxEthAccStatus
-ixEthAccMibIIStatsGet (IxEthAccPortId portId,
- IxEthEthObjStats *retStats )
-{
- IxNpeMhMessage message;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- printf("EthAcc: ixEthAccMibIIStatsGet (Mac) EthAcc service is not initialized\n");
- return (IX_ETH_ACC_FAIL);
- }
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (retStats == NULL)
- {
- printf("EthAcc: ixEthAccMibIIStatsGet (Mac) NULL argument\n");
- return (IX_ETH_ACC_FAIL);
- }
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- printf("EthAcc: ixEthAccMibIIStatsGet (Mac) NPE for port %d is not available\n", portId);
-
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot get MIB II Stats.\n",(INT32)portId,0,0,0,0,0);
-
- /* Return all zero stats */
- IX_ETH_ACC_MEMSET(retStats, 0, sizeof(IxEthEthObjStats));
-
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- printf("EthAcc: ixEthAccMibIIStatsGet (Mac) port %d is not initialized\n", portId);
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- IX_OSAL_CACHE_INVALIDATE(retStats, sizeof(IxEthEthObjStats));
-
- message.data[0] = IX_ETHNPE_GETSTATS << IX_ETH_ACC_MAC_MSGID_SHL;
- message.data[1] = (UINT32) IX_OSAL_MMU_VIRT_TO_PHYS(retStats);
-
- /* Permit only one task to request MIB statistics Get operation
- at a time */
- ixOsalMutexLock(&ixEthAccMacState[portId].MIBStatsGetAccessLock, IX_OSAL_WAIT_FOREVER);
-
- if(ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId),
- message,
- IX_ETHNPE_GETSTATS,
- ixEthAccMacNpeStatsMessageCallback,
- IX_NPEMH_SEND_RETRIES_DEFAULT)
- != IX_SUCCESS)
- {
- ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetAccessLock);
-
- printf("EthAcc: (Mac) StatsGet failed to send NPE message\n");
-
- return IX_ETH_ACC_FAIL;
- }
-
- /* Wait for callback invocation indicating response to
- this request - we need this mutex in order to ensure
- that the return from this function is synchronous */
- ixOsalMutexLock(&ixEthAccMacState[portId].ackMIBStatsLock, IX_ETH_ACC_MIB_STATS_DELAY_MSECS);
-
- /* Permit other tasks to perform MIB statistics Get operation */
- ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetAccessLock);
-
- ixEthAccMibIIStatsEndianConvert (retStats);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-
-PRIVATE void
-ixEthAccMacNpeStatsResetMessageCallback (IxNpeMhNpeId npeId,
- IxNpeMhMessage msg)
-{
- IxEthAccPortId portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);
-
-#ifndef NDEBUG
- /* Prudent to at least check the port is within range */
- if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS)
- {
- IX_ETH_ACC_FATAL_LOG(
- "IXETHACC:ixEthAccMacNpeStatsResetMessageCallback: Illegal port: %u\n",
- (UINT32)portId, 0, 0, 0, 0, 0);
- return;
- }
-#endif
-
- /*Unblock Stats Get & reset call*/
- ixOsalMutexUnlock(&ixEthAccMacState[portId].ackMIBStatsResetLock);
-
-}
-
-
-
-IxEthAccStatus
-ixEthAccMibIIStatsGetClear (IxEthAccPortId portId,
- IxEthEthObjStats *retStats)
-{
- IxNpeMhMessage message;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) EthAcc service is not initialized\n");
- return (IX_ETH_ACC_FAIL);
- }
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (retStats == NULL)
- {
- printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) NULL argument\n");
- return (IX_ETH_ACC_FAIL);
- }
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) NPE for port %d is not available\n", portId);
-
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot get and clear MIB II Stats.\n", (INT32)portId, 0, 0, 0, 0, 0);
-
- /* Return all zero stats */
- IX_ETH_ACC_MEMSET(retStats, 0, sizeof(IxEthEthObjStats));
-
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) port %d is not initialized\n", portId);
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- IX_OSAL_CACHE_INVALIDATE(retStats, sizeof(IxEthEthObjStats));
-
- message.data[0] = IX_ETHNPE_RESETSTATS << IX_ETH_ACC_MAC_MSGID_SHL;
- message.data[1] = (UINT32) IX_OSAL_MMU_VIRT_TO_PHYS(retStats);
-
- /* Permit only one task to request MIB statistics Get-Reset operation at a time */
- ixOsalMutexLock(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock, IX_OSAL_WAIT_FOREVER);
-
- if(ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId),
- message,
- IX_ETHNPE_RESETSTATS,
- ixEthAccMacNpeStatsResetMessageCallback,
- IX_NPEMH_SEND_RETRIES_DEFAULT)
- != IX_SUCCESS)
- {
- ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock);
-
- printf("EthAcc: (Mac) ixEthAccMibIIStatsGetClear failed to send NPE message\n");
-
- return IX_ETH_ACC_FAIL;
- }
-
- /* Wait for callback invocation indicating response to this request */
- ixOsalMutexLock(&ixEthAccMacState[portId].ackMIBStatsResetLock, IX_ETH_ACC_MIB_STATS_DELAY_MSECS);
-
- /* permit other tasks to get and reset MIB stats*/
- ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock);
-
- ixEthAccMibIIStatsEndianConvert(retStats);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccMibIIStatsClear (IxEthAccPortId portId)
-{
- static IxEthEthObjStats retStats;
- IxEthAccStatus status;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot clear MIB II Stats.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- /* there is no reset operation without a corresponding Get */
- status = ixEthAccMibIIStatsGetClear(portId, &retStats);
-
- return status;
-}
-
-/* Initialize the ethernet MAC settings */
-IxEthAccStatus
-ixEthAccMacInit(IxEthAccPortId portId)
-{
- IX_OSAL_MBUF_POOL* portDisablePool;
- UINT8 *data;
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot initialize Mac.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if(ixEthAccMacState[portId].macInitialised == FALSE)
- {
- ixEthAccMacState[portId].fullDuplex = TRUE;
- ixEthAccMacState[portId].rxFCSAppend = TRUE;
- ixEthAccMacState[portId].txFCSAppend = TRUE;
- ixEthAccMacState[portId].txPADAppend = TRUE;
- ixEthAccMacState[portId].enabled = FALSE;
- ixEthAccMacState[portId].promiscuous = TRUE;
- ixEthAccMacState[portId].joinAll = FALSE;
- ixEthAccMacState[portId].initDone = FALSE;
- ixEthAccMacState[portId].macInitialised = TRUE;
-
- /* initialize MIB stats mutexes */
- ixOsalMutexInit(&ixEthAccMacState[portId].ackMIBStatsLock);
- ixOsalMutexLock(&ixEthAccMacState[portId].ackMIBStatsLock, IX_OSAL_WAIT_FOREVER);
-
- ixOsalMutexInit(&ixEthAccMacState[portId].ackMIBStatsResetLock);
- ixOsalMutexLock(&ixEthAccMacState[portId].ackMIBStatsResetLock, IX_OSAL_WAIT_FOREVER);
-
- ixOsalMutexInit(&ixEthAccMacState[portId].MIBStatsGetAccessLock);
-
- ixOsalMutexInit(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock);
-
- ixOsalMutexInit(&ixEthAccMacState[portId].npeLoopbackMessageLock);
-
- ixEthAccMacState[portId].portDisableRxMbufPtr = NULL;
- ixEthAccMacState[portId].portDisableTxMbufPtr = NULL;
-
- portDisablePool = IX_OSAL_MBUF_POOL_INIT(2,
- IX_ETHACC_RX_MBUF_MIN_SIZE,
- "portDisable Pool");
-
- IX_OSAL_ENSURE(portDisablePool != NULL, "Failed to initialize PortDisable pool");
-
- ixEthAccMacState[portId].portDisableRxMbufPtr = IX_OSAL_MBUF_POOL_GET(portDisablePool);
- ixEthAccMacState[portId].portDisableTxMbufPtr = IX_OSAL_MBUF_POOL_GET(portDisablePool);
-
- IX_OSAL_ENSURE(ixEthAccMacState[portId].portDisableRxMbufPtr != NULL,
- "Pool allocation failed");
- IX_OSAL_ENSURE(ixEthAccMacState[portId].portDisableTxMbufPtr != NULL,
- "Pool allocation failed");
- /* fill the payload of the Rx mbuf used in portDisable */
- IX_OSAL_MBUF_MLEN(ixEthAccMacState[portId].portDisableRxMbufPtr) = IX_ETHACC_RX_MBUF_MIN_SIZE;
-
- memset(IX_OSAL_MBUF_MDATA(ixEthAccMacState[portId].portDisableRxMbufPtr),
- 0xAA,
- IX_ETHACC_RX_MBUF_MIN_SIZE);
-
- /* fill the payload of the Tx mbuf used in portDisable (64 bytes) */
- IX_OSAL_MBUF_MLEN(ixEthAccMacState[portId].portDisableTxMbufPtr) = 64;
- IX_OSAL_MBUF_PKT_LEN(ixEthAccMacState[portId].portDisableTxMbufPtr) = 64;
-
- data = (UINT8 *) IX_OSAL_MBUF_MDATA(ixEthAccMacState[portId].portDisableTxMbufPtr);
- memset(data, 0xBB, 64);
- data[0] = 0x00; /* unicast destination MAC address */
- data[6] = 0x00; /* unicast source MAC address */
- data[12] = 0x08; /* typelength : IP frame */
- data[13] = 0x00; /* typelength : IP frame */
-
- IX_OSAL_CACHE_FLUSH(data, 64);
- }
-
- IX_OSAL_ASSERT (ixEthAccMacBase[portId] != 0);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_CORE_CNTRL,
- IX_ETH_ACC_CORE_RESET);
-
- ixOsalSleep(IX_ETH_ACC_MAC_RESET_DELAY);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_CORE_CNTRL,
- IX_ETH_ACC_CORE_MDC_EN);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_INT_CLK_THRESH,
- IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT);
-
- ixEthAccMacStateUpdate(portId);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-/* PRIVATE Functions*/
-
-PRIVATE void
-ixEthAccMacStateUpdate(IxEthAccPortId portId)
-{
- UINT32 regval;
-
- if ( ixEthAccMacState[portId].enabled == FALSE )
- {
- /* Just disable both the transmitter and reciver in the MAC. */
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval);
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval & ~IX_ETH_ACC_RX_CNTRL1_RX_EN);
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval);
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval & ~IX_ETH_ACC_TX_CNTRL1_TX_EN);
- }
-
- if(ixEthAccMacState[portId].fullDuplex)
- {
- ixEthAccPortDuplexModeSetPriv (portId, IX_ETH_ACC_FULL_DUPLEX);
- }
- else
- {
- ixEthAccPortDuplexModeSetPriv (portId, IX_ETH_ACC_HALF_DUPLEX);
- }
-
- if(ixEthAccMacState[portId].rxFCSAppend)
- {
- ixEthAccPortRxFrameAppendFCSEnablePriv (portId);
- }
- else
- {
- ixEthAccPortRxFrameAppendFCSDisablePriv (portId);
- }
-
- if(ixEthAccMacState[portId].txFCSAppend)
- {
- ixEthAccPortTxFrameAppendFCSEnablePriv (portId);
- }
- else
- {
- ixEthAccPortTxFrameAppendFCSDisablePriv (portId);
- }
-
- if(ixEthAccMacState[portId].txPADAppend)
- {
- ixEthAccPortTxFrameAppendPaddingEnablePriv (portId);
- }
- else
- {
- ixEthAccPortTxFrameAppendPaddingDisablePriv (portId);
- }
-
- if(ixEthAccMacState[portId].promiscuous)
- {
- ixEthAccPortPromiscuousModeSetPriv(portId);
- }
- else
- {
- ixEthAccPortPromiscuousModeClearPriv(portId);
- }
-
- if ( ixEthAccMacState[portId].enabled == TRUE )
- {
- /* Enable both the transmitter and reciver in the MAC. */
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval);
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval | IX_ETH_ACC_RX_CNTRL1_RX_EN);
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval);
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval | IX_ETH_ACC_TX_CNTRL1_TX_EN);
- }
-}
-
-
-PRIVATE BOOL
-ixEthAccMacEqual(IxEthAccMacAddr *macAddr1,
- IxEthAccMacAddr *macAddr2)
-{
- UINT32 i;
- for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE; i++)
- {
- if(macAddr1->macAddress[i] != macAddr2->macAddress[i])
- {
- return FALSE;
- }
- }
- return TRUE;
-}
-
-PRIVATE void
-ixEthAccMacPrint(IxEthAccMacAddr *m)
-{
- printf("%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x",
- m->macAddress[0], m->macAddress[1],
- m->macAddress[2], m->macAddress[3],
- m->macAddress[4], m->macAddress[5]);
-}
-
-/* Set the multicast address and address mask registers
- *
- * A bit in the address mask register must be set if
- * all multicast addresses always have that bit set, or if
- * all multicast addresses always have that bit cleared.
- *
- * A bit in the address register must be set if all multicast
- * addresses have that bit set, otherwise, it should be cleared
- */
-
-PRIVATE void
-ixEthAccMulticastAddressSet(IxEthAccPortId portId)
-{
- UINT32 i;
- UINT32 j;
- IxEthAccMacAddr addressMask;
- IxEthAccMacAddr address;
- IxEthAccMacAddr alwaysClearBits;
- IxEthAccMacAddr alwaysSetBits;
-
- /* calculate alwaysClearBits and alwaysSetBits:
- * alwaysClearBits is calculated by ORing all
- * multicast addresses, those bits that are always
- * clear are clear in the result
- *
- * alwaysSetBits is calculated by ANDing all
- * multicast addresses, those bits that are always set
- * are set in the result
- */
-
- if (ixEthAccMacState[portId].promiscuous == TRUE)
- {
- /* Promiscuous Mode is set, and filtering
- * allow all packets, and enable the mcast and
- * bcast detection.
- */
- memset(&addressMask.macAddress,
- 0,
- IX_IEEE803_MAC_ADDRESS_SIZE);
- memset(&address.macAddress,
- 0,
- IX_IEEE803_MAC_ADDRESS_SIZE);
- }
- else
- {
- if(ixEthAccMacState[portId].joinAll == TRUE)
- {
- /* Join all is set. The mask and address are
- * the multicast settings.
- */
- IxEthAccMacAddr macAddr = {{0x1,0x0,0x0,0x0,0x0,0x0}};
-
- memcpy(addressMask.macAddress,
- macAddr.macAddress,
- IX_IEEE803_MAC_ADDRESS_SIZE);
- memcpy(address.macAddress,
- macAddr.macAddress,
- IX_IEEE803_MAC_ADDRESS_SIZE);
- }
- else if(ixEthAccMacState[portId].mcastAddrIndex == 0)
- {
- /* No entry in the filtering database,
- * Promiscuous Mode is cleared, Broadcast filtering
- * is configured.
- */
- memset(addressMask.macAddress,
- IX_ETH_ACC_MAC_ALL_BITS_SET,
- IX_IEEE803_MAC_ADDRESS_SIZE);
- memset(address.macAddress,
- IX_ETH_ACC_MAC_ALL_BITS_SET,
- IX_IEEE803_MAC_ADDRESS_SIZE);
- }
- else
- {
- /* build a mask and an address which mix all entreis
- * from the list of multicast addresses
- */
- memset(alwaysClearBits.macAddress,
- 0,
- IX_IEEE803_MAC_ADDRESS_SIZE);
- memset(alwaysSetBits.macAddress,
- IX_ETH_ACC_MAC_ALL_BITS_SET,
- IX_IEEE803_MAC_ADDRESS_SIZE);
-
- for(i=0;i<ixEthAccMacState[portId].mcastAddrIndex;i++)
- {
- for(j=0;j<IX_IEEE803_MAC_ADDRESS_SIZE;j++)
- {
- alwaysClearBits.macAddress[j] |=
- ixEthAccMacState[portId].mcastAddrsTable[i].macAddress[j];
- alwaysSetBits.macAddress[j] &=
- ixEthAccMacState[portId].mcastAddrsTable[i].macAddress[j];
- }
- }
-
- for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
- {
- addressMask.macAddress[i] = alwaysSetBits.macAddress[i]
- | ~alwaysClearBits.macAddress[i];
- address.macAddress[i] = alwaysSetBits.macAddress[i];
- }
- }
- }
-
- /*write the new addr filtering to h/w*/
- for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
- {
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_ADDR_MASK_1+i*sizeof(UINT32),
- addressMask.macAddress[i]);
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_ADDR_1+i*sizeof(UINT32),
- address.macAddress[i]);
- }
-}
+++ /dev/null
-/**
- * @file IxEthAccMii.c
- *
- * @author Intel Corporation
- * @date
- *
- * @brief MII control functions
- *
- * Design Notes:
- *
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-#include "IxEthAcc.h"
-#include "IxEthAcc_p.h"
-#include "IxEthAccMac_p.h"
-#include "IxEthAccMii_p.h"
-
-
-PRIVATE UINT32 miiBaseAddressVirt;
-PRIVATE IxOsalMutex miiAccessLock;
-
-PUBLIC UINT32 ixEthAccMiiRetryCount = IX_ETH_ACC_MII_TIMEOUT_10TH_SECS;
-PUBLIC UINT32 ixEthAccMiiAccessTimeout = IX_ETH_ACC_MII_10TH_SEC_IN_MILLIS;
-
-/* -----------------------------------
- * private function prototypes
- */
-PRIVATE void
-ixEthAccMdioCmdWrite(UINT32 mdioCommand);
-
-PRIVATE void
-ixEthAccMdioCmdRead(UINT32 *data);
-
-PRIVATE void
-ixEthAccMdioStatusRead(UINT32 *data);
-
-
-PRIVATE void
-ixEthAccMdioCmdWrite(UINT32 mdioCommand)
-{
- REG_WRITE(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_CMD_1,
- mdioCommand & 0xff);
-
- REG_WRITE(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_CMD_2,
- (mdioCommand >> 8) & 0xff);
-
- REG_WRITE(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_CMD_3,
- (mdioCommand >> 16) & 0xff);
-
- REG_WRITE(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_CMD_4,
- (mdioCommand >> 24) & 0xff);
-}
-
-PRIVATE void
-ixEthAccMdioCmdRead(UINT32 *data)
-{
- UINT32 regval;
-
- REG_READ(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_CMD_1,
- regval);
-
- *data = regval & 0xff;
-
- REG_READ(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_CMD_2,
- regval);
-
- *data |= (regval & 0xff) << 8;
-
- REG_READ(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_CMD_3,
- regval);
-
- *data |= (regval & 0xff) << 16;
-
- REG_READ(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_CMD_4,
- regval);
-
- *data |= (regval & 0xff) << 24;
-
-}
-
-PRIVATE void
-ixEthAccMdioStatusRead(UINT32 *data)
-{
- UINT32 regval;
-
- REG_READ(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_STS_1,
- regval);
-
- *data = regval & 0xff;
-
- REG_READ(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_STS_2,
- regval);
-
- *data |= (regval & 0xff) << 8;
-
- REG_READ(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_STS_3,
- regval);
-
- *data |= (regval & 0xff) << 16;
-
- REG_READ(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_STS_4,
- regval);
-
- *data |= (regval & 0xff) << 24;
-
-}
-
-
-/********************************************************************
- * ixEthAccMiiInit
- */
-IxEthAccStatus
-ixEthAccMiiInit()
-{
- if(ixOsalMutexInit(&miiAccessLock)!= IX_SUCCESS)
- {
- return IX_ETH_ACC_FAIL;
- }
-
- miiBaseAddressVirt = (UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_0_BASE, IX_OSAL_IXP400_ETHA_MAP_SIZE);
-
- if (miiBaseAddressVirt == 0)
- {
- ixOsalLog(IX_OSAL_LOG_LVL_FATAL,
- IX_OSAL_LOG_DEV_STDOUT,
- "EthAcc: Could not map MII I/O mapped memory\n",
- 0, 0, 0, 0, 0, 0);
-
- return IX_ETH_ACC_FAIL;
- }
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-void
-ixEthAccMiiUnload(void)
-{
- IX_OSAL_MEM_UNMAP(miiBaseAddressVirt);
-
- miiBaseAddressVirt = 0;
-}
-
-PUBLIC IxEthAccStatus
-ixEthAccMiiAccessTimeoutSet(UINT32 timeout, UINT32 retryCount)
-{
- if (retryCount < 1) return IX_ETH_ACC_FAIL;
-
- ixEthAccMiiRetryCount = retryCount;
- ixEthAccMiiAccessTimeout = timeout;
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-/*********************************************************************
- * ixEthAccMiiReadRtn - read a 16 bit value from a PHY
- */
-IxEthAccStatus
-ixEthAccMiiReadRtn (UINT8 phyAddr,
- UINT8 phyReg,
- UINT16 *value)
-{
- UINT32 mdioCommand;
- UINT32 regval;
- UINT32 miiTimeout;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- if ((phyAddr >= IXP425_ETH_ACC_MII_MAX_ADDR)
- || (phyReg >= IXP425_ETH_ACC_MII_MAX_REG))
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- if (value == NULL)
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER);
- mdioCommand = phyReg << IX_ETH_ACC_MII_REG_SHL
- | phyAddr << IX_ETH_ACC_MII_ADDR_SHL;
- mdioCommand |= IX_ETH_ACC_MII_GO;
-
- ixEthAccMdioCmdWrite(mdioCommand);
-
- miiTimeout = ixEthAccMiiRetryCount;
-
- while(miiTimeout)
- {
-
- ixEthAccMdioCmdRead(®val);
-
- if((regval & IX_ETH_ACC_MII_GO) == 0x0)
- {
- break;
- }
- /* Sleep for a while */
- ixOsalSleep(ixEthAccMiiAccessTimeout);
- miiTimeout--;
- }
-
-
-
- if(miiTimeout == 0)
- {
- ixOsalMutexUnlock(&miiAccessLock);
- *value = 0xffff;
- return IX_ETH_ACC_FAIL;
- }
-
-
- ixEthAccMdioStatusRead(®val);
- if(regval & IX_ETH_ACC_MII_READ_FAIL)
- {
- ixOsalMutexUnlock(&miiAccessLock);
- *value = 0xffff;
- return IX_ETH_ACC_FAIL;
- }
-
- *value = regval & 0xffff;
- ixOsalMutexUnlock(&miiAccessLock);
- return IX_ETH_ACC_SUCCESS;
-
-}
-
-
-/*********************************************************************
- * ixEthAccMiiWriteRtn - write a 16 bit value to a PHY
- */
-IxEthAccStatus
-ixEthAccMiiWriteRtn (UINT8 phyAddr,
- UINT8 phyReg,
- UINT16 value)
-{
- UINT32 mdioCommand;
- UINT32 regval;
- UINT16 readVal;
- UINT32 miiTimeout;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- if ((phyAddr >= IXP425_ETH_ACC_MII_MAX_ADDR)
- || (phyReg >= IXP425_ETH_ACC_MII_MAX_REG))
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- /* ensure that a PHY is present at this address */
- if(ixEthAccMiiReadRtn(phyAddr,
- IX_ETH_ACC_MII_CTRL_REG,
- &readVal) != IX_ETH_ACC_SUCCESS)
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER);
- mdioCommand = phyReg << IX_ETH_ACC_MII_REG_SHL
- | phyAddr << IX_ETH_ACC_MII_ADDR_SHL ;
- mdioCommand |= IX_ETH_ACC_MII_GO | IX_ETH_ACC_MII_WRITE | value;
-
- ixEthAccMdioCmdWrite(mdioCommand);
-
- miiTimeout = ixEthAccMiiRetryCount;
-
- while(miiTimeout)
- {
-
- ixEthAccMdioCmdRead(®val);
-
- /*The "GO" bit is reset to 0 when the write completes*/
- if((regval & IX_ETH_ACC_MII_GO) == 0x0)
- {
- break;
- }
- /* Sleep for a while */
- ixOsalSleep(ixEthAccMiiAccessTimeout);
- miiTimeout--;
- }
-
- ixOsalMutexUnlock(&miiAccessLock);
- if(miiTimeout == 0)
- {
- return IX_ETH_ACC_FAIL;
- }
- return IX_ETH_ACC_SUCCESS;
-}
-
-
-/*****************************************************************
- *
- * Phy query functions
- *
- */
-IxEthAccStatus
-ixEthAccMiiStatsShow (UINT32 phyAddr)
-{
- UINT16 regval;
- printf("Regisers on PHY at address 0x%x\n", phyAddr);
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_CTRL_REG, ®val);
- printf(" Control Register : 0x%4.4x\n", regval);
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_STAT_REG, ®val);
- printf(" Status Register : 0x%4.4x\n", regval);
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_PHY_ID1_REG, ®val);
- printf(" PHY ID1 Register : 0x%4.4x\n", regval);
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_PHY_ID2_REG, ®val);
- printf(" PHY ID2 Register : 0x%4.4x\n", regval);
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_AN_ADS_REG, ®val);
- printf(" Auto Neg ADS Register : 0x%4.4x\n", regval);
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_AN_PRTN_REG, ®val);
- printf(" Auto Neg Partner Ability Register : 0x%4.4x\n", regval);
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_AN_EXP_REG, ®val);
- printf(" Auto Neg Expansion Register : 0x%4.4x\n", regval);
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_AN_NEXT_REG, ®val);
- printf(" Auto Neg Next Register : 0x%4.4x\n", regval);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-
-/*****************************************************************
- *
- * Interface query functions
- *
- */
-IxEthAccStatus
-ixEthAccMdioShow (void)
-{
- UINT32 regval;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER);
- ixEthAccMdioCmdRead(®val);
- ixOsalMutexUnlock(&miiAccessLock);
-
- printf("MDIO command register\n");
- printf(" Go bit : 0x%x\n", (regval & BIT(31)) >> 31);
- printf(" MDIO Write : 0x%x\n", (regval & BIT(26)) >> 26);
- printf(" PHY address : 0x%x\n", (regval >> 21) & 0x1f);
- printf(" Reg address : 0x%x\n", (regval >> 16) & 0x1f);
-
- ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER);
- ixEthAccMdioStatusRead(®val);
- ixOsalMutexUnlock(&miiAccessLock);
-
- printf("MDIO status register\n");
- printf(" Read OK : 0x%x\n", (regval & BIT(31)) >> 31);
- printf(" Read Data : 0x%x\n", (regval >> 16) & 0xff);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
+++ /dev/null
-/**
- * @file IxEthDBAPI.c
- *
- * @brief Implementation of the public API
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-#include "IxFeatureCtrl.h"
-
-extern HashTable dbHashtable;
-extern IxEthDBPortMap overflowUpdatePortList;
-extern BOOL ixEthDBPortUpdateRequired[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1];
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringStaticEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING);
-
- return ixEthDBTriggerAddPortUpdate(macAddr, portID, TRUE);
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringDynamicEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING);
-
- return ixEthDBTriggerAddPortUpdate(macAddr, portID, FALSE);
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringEntryDelete(IxEthDBMacAddr *macAddr)
-{
- HashNode *searchResult;
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS);
-
- if (searchResult == NULL)
- {
- return IX_ETH_DB_NO_SUCH_ADDR; /* not found */
- }
-
- ixEthDBReleaseHashNode(searchResult);
-
- /* build a remove event and place it on the event queue */
- return ixEthDBTriggerRemovePortUpdate(macAddr, ((MacDescriptor *) searchResult->data)->portID);
-}
-
-IX_ETH_DB_PUBLIC
-void ixEthDBDatabaseMaintenance()
-{
- HashIterator iterator;
- UINT32 portIndex;
- BOOL agingRequired = FALSE;
-
- /* ports who will have deleted records and therefore will need updating */
- IxEthDBPortMap triggerPorts;
-
- if (IX_FEATURE_CTRL_SWCONFIG_ENABLED !=
- ixFeatureCtrlSwConfigurationCheck (IX_FEATURECTRL_ETH_LEARNING))
- {
- return;
- }
-
- SET_EMPTY_DEPENDENCY_MAP(triggerPorts);
-
- /* check if there's at least a port that needs aging */
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- if (ixEthDBPortInfo[portIndex].agingEnabled && ixEthDBPortInfo[portIndex].enabled)
- {
- agingRequired = TRUE;
- }
- }
-
- if (agingRequired)
- {
- /* ask each NPE port to write back the database for aging inspection */
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE
- && ixEthDBPortInfo[portIndex].agingEnabled
- && ixEthDBPortInfo[portIndex].enabled)
- {
- IxNpeMhMessage message;
- IX_STATUS result;
-
- /* send EDB_GetMACAddressDatabase message */
- FILL_GETMACADDRESSDATABASE(message,
- 0 /* unused */,
- IX_OSAL_MMU_VIRT_TO_PHYS(ixEthDBPortInfo[portIndex].updateMethod.npeUpdateZone));
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portIndex), message, result);
-
- if (result == IX_SUCCESS)
- {
- /* analyze NPE copy */
- ixEthDBNPESyncScan(portIndex, ixEthDBPortInfo[portIndex].updateMethod.npeUpdateZone, FULL_ELT_BYTE_SIZE);
-
- IX_ETH_DB_SUPPORT_TRACE("DB: (API) Finished scanning NPE tree on port %d\n", portIndex);
- }
- else
- {
- ixEthDBPortInfo[portIndex].agingEnabled = FALSE;
- ixEthDBPortInfo[portIndex].updateMethod.updateEnabled = FALSE;
- ixEthDBPortInfo[portIndex].updateMethod.userControlled = TRUE;
-
- ixOsalLog(IX_OSAL_LOG_LVL_FATAL,
- IX_OSAL_LOG_DEV_STDOUT,
- "EthDB: (Maintenance) warning, disabling aging and updates for port %d (assumed dead)\n",
- portIndex, 0, 0, 0, 0, 0);
-
- ixEthDBDatabaseClear(portIndex, IX_ETH_DB_ALL_RECORD_TYPES);
- }
- }
- }
-
- /* browse database and age entries */
- BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator));
-
- while (IS_ITERATOR_VALID(&iterator))
- {
- MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data;
- UINT32 *age = NULL;
- BOOL staticEntry = TRUE;
-
- if (descriptor->type == IX_ETH_DB_FILTERING_RECORD)
- {
- age = &descriptor->recordData.filteringData.age;
- staticEntry = descriptor->recordData.filteringData.staticEntry;
- }
- else if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD)
- {
- age = &descriptor->recordData.filteringVlanData.age;
- staticEntry = descriptor->recordData.filteringVlanData.staticEntry;
- }
- else
- {
- staticEntry = TRUE;
- }
-
- if (ixEthDBPortInfo[descriptor->portID].agingEnabled && (staticEntry == FALSE))
- {
- /* manually increment the age if the port has no such capability */
- if ((ixEthDBPortDefinitions[descriptor->portID].capabilities & IX_ETH_ENTRY_AGING) == 0)
- {
- *age += (IX_ETH_DB_MAINTENANCE_TIME / 60);
- }
-
- /* age entry if it exceeded the maximum time to live */
- if (*age >= (IX_ETH_DB_LEARNING_ENTRY_AGE_TIME / 60))
- {
- /* add port to the set of update trigger ports */
- JOIN_PORT_TO_MAP(triggerPorts, descriptor->portID);
-
- /* delete entry */
- BUSY_RETRY(ixEthDBRemoveEntryAtHashIterator(&dbHashtable, &iterator));
- }
- else
- {
- /* move to the next record */
- BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator));
- }
- }
- else
- {
- /* move to the next record */
- BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator));
- }
- }
-
- /* update ports which lost records */
- ixEthDBUpdatePortLearningTrees(triggerPorts);
- }
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBDatabaseClear(IxEthDBPortId portID, IxEthDBRecordType recordType)
-{
- IxEthDBPortMap triggerPorts;
- HashIterator iterator;
-
- if (portID >= IX_ETH_DB_NUMBER_OF_PORTS && portID != IX_ETH_DB_ALL_PORTS)
- {
- return IX_ETH_DB_INVALID_PORT;
- }
-
- /* check if the user passes some extra bits */
- if ((recordType | IX_ETH_DB_ALL_RECORD_TYPES) != IX_ETH_DB_ALL_RECORD_TYPES)
- {
- return IX_ETH_DB_INVALID_ARG;
- }
-
- SET_EMPTY_DEPENDENCY_MAP(triggerPorts);
-
- /* browse database and age entries */
- BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator));
-
- while (IS_ITERATOR_VALID(&iterator))
- {
- MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data;
-
- if (((descriptor->portID == portID) || (portID == IX_ETH_DB_ALL_PORTS))
- && ((descriptor->type & recordType) != 0))
- {
- /* add to trigger if automatic updates are required */
- if (ixEthDBPortUpdateRequired[descriptor->type])
- {
- /* add port to the set of update trigger ports */
- JOIN_PORT_TO_MAP(triggerPorts, descriptor->portID);
- }
-
- /* delete entry */
- BUSY_RETRY(ixEthDBRemoveEntryAtHashIterator(&dbHashtable, &iterator));
- }
- else
- {
- /* move to the next record */
- BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator));
- }
- }
-
- /* update ports which lost records */
- ixEthDBUpdatePortLearningTrees(triggerPorts);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringPortSearch(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
- HashNode *searchResult;
- IxEthDBStatus result = IX_ETH_DB_NO_SUCH_ADDR;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING);
-
- searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS);
-
- if (searchResult == NULL)
- {
- return IX_ETH_DB_NO_SUCH_ADDR; /* not found */
- }
-
- if (((MacDescriptor *) (searchResult->data))->portID == portID)
- {
- result = IX_ETH_DB_SUCCESS; /* address and port match */
- }
-
- ixEthDBReleaseHashNode(searchResult);
-
- return result;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringDatabaseSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr)
-{
- HashNode *searchResult;
-
- IX_ETH_DB_CHECK_REFERENCE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS);
-
- if (searchResult == NULL)
- {
- return IX_ETH_DB_NO_SUCH_ADDR; /* not found */
- }
-
- /* return the port ID */
- *portID = ((MacDescriptor *) searchResult->data)->portID;
-
- ixEthDBReleaseHashNode(searchResult);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortAgingDisable(IxEthDBPortId portID)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING);
-
- ixEthDBPortInfo[portID].agingEnabled = FALSE;
-
- return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortAgingEnable(IxEthDBPortId portID)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING);
-
- ixEthDBPortInfo[portID].agingEnabled = TRUE;
-
- return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringPortUpdatingSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr)
-{
- HashNode *searchResult;
- MacDescriptor *descriptor;
-
- IX_ETH_DB_CHECK_REFERENCE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS);
-
- if (searchResult == NULL)
- {
- return IX_ETH_DB_NO_SUCH_ADDR; /* not found */
- }
-
- descriptor = (MacDescriptor *) searchResult->data;
-
- /* return the port ID */
- *portID = descriptor->portID;
-
- /* reset entry age */
- if (descriptor->type == IX_ETH_DB_FILTERING_RECORD)
- {
- descriptor->recordData.filteringData.age = 0;
- }
- else
- {
- descriptor->recordData.filteringVlanData.age = 0;
- }
-
- ixEthDBReleaseHashNode(searchResult);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortDependencyMapSet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(dependencyPortMap);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FILTERING);
-
- /* force bit at offset 255 to 0 (reserved) */
- dependencyPortMap[31] &= 0xFE;
-
- COPY_DEPENDENCY_MAP(ixEthDBPortInfo[portID].dependencyPortMap, dependencyPortMap);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortDependencyMapGet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(dependencyPortMap);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FILTERING);
-
- COPY_DEPENDENCY_MAP(dependencyPortMap, ixEthDBPortInfo[portID].dependencyPortMap);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortUpdateEnableSet(IxEthDBPortId portID, BOOL enableUpdate)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FILTERING);
-
- ixEthDBPortInfo[portID].updateMethod.updateEnabled = enableUpdate;
- ixEthDBPortInfo[portID].updateMethod.userControlled = TRUE;
-
- return IX_ETH_DB_SUCCESS;
-}
+++ /dev/null
-/**
- * @file IxEthDBAPISupport.c
- *
- * @brief Public API support functions
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include <IxEthDB.h>
-#include <IxNpeMh.h>
-#include <IxFeatureCtrl.h>
-
-#include "IxEthDB_p.h"
-#include "IxEthDBMessages_p.h"
-#include "IxEthDB_p.h"
-#include "IxEthDBLog_p.h"
-
-#ifdef IX_UNIT_TEST
-
-int dbAccessCounter = 0;
-int overflowEvent = 0;
-
-#endif
-
-/*
- * External declaration
- */
-extern HashTable dbHashtable;
-
-/*
- * Internal declaration
- */
-IX_ETH_DB_PUBLIC
-PortInfo ixEthDBPortInfo[IX_ETH_DB_NUMBER_OF_PORTS];
-
-IX_ETH_DB_PRIVATE
-struct
-{
- BOOL saved;
- IxEthDBPriorityTable priorityTable;
- IxEthDBVlanSet vlanMembership;
- IxEthDBVlanSet transmitTaggingInfo;
- IxEthDBFrameFilter frameFilter;
- IxEthDBTaggingAction taggingAction;
- IxEthDBFirewallMode firewallMode;
- BOOL stpBlocked;
- BOOL srcAddressFilterEnabled;
- UINT32 maxRxFrameSize;
- UINT32 maxTxFrameSize;
-} ixEthDBPortState[IX_ETH_DB_NUMBER_OF_PORTS];
-
-#define IX_ETH_DB_DEFAULT_FRAME_SIZE (1518)
-
-/**
- * @brief initializes a port
- *
- * @param portID ID of the port to be initialized
- *
- * Note that redundant initializations are silently
- * dealt with and do not constitute an error
- *
- * This function is fully documented in the main
- * header file, IxEthDB.h
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBPortInit(IxEthDBPortId portID)
-{
- PortInfo *portInfo;
-
- if (portID >= IX_ETH_DB_NUMBER_OF_PORTS)
- {
- return;
- }
-
- portInfo = &ixEthDBPortInfo[portID];
-
- if (ixEthDBSingleEthNpeCheck(portID) != IX_ETH_DB_SUCCESS)
- {
- WARNING_LOG("EthDB: Unavailable Eth %d: Cannot initialize EthDB Port.\n", (UINT32) portID);
-
- return;
- }
-
- if (portInfo->initialized)
- {
- /* redundant */
- return;
- }
-
- /* initialize core fields */
- portInfo->portID = portID;
- SET_DEPENDENCY_MAP(portInfo->dependencyPortMap, portID);
-
- /* default values */
- portInfo->agingEnabled = FALSE;
- portInfo->enabled = FALSE;
- portInfo->macAddressUploaded = FALSE;
- portInfo->maxRxFrameSize = IX_ETHDB_DEFAULT_FRAME_SIZE;
- portInfo->maxTxFrameSize = IX_ETHDB_DEFAULT_FRAME_SIZE;
-
- /* default update control values */
- portInfo->updateMethod.searchTree = NULL;
- portInfo->updateMethod.searchTreePendingWrite = FALSE;
- portInfo->updateMethod.treeInitialized = FALSE;
- portInfo->updateMethod.updateEnabled = FALSE;
- portInfo->updateMethod.userControlled = FALSE;
-
- /* default WiFi parameters */
- memset(portInfo->bbsid, 0, sizeof (portInfo->bbsid));
- portInfo->frameControlDurationID = 0;
-
- /* Ethernet NPE-specific initializations */
- if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
- {
- /* update handler */
- portInfo->updateMethod.updateHandler = ixEthDBNPEUpdateHandler;
- }
-
- /* initialize state save */
- ixEthDBPortState[portID].saved = FALSE;
-
- portInfo->initialized = TRUE;
-}
-
-/**
- * @brief enables a port
- *
- * @param portID ID of the port to enable
- *
- * This function is fully documented in the main
- * header file, IxEthDB.h
- *
- * @return IX_ETH_DB_SUCCESS if enabling was
- * accomplished, or a meaningful error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID)
-{
- IxEthDBPortMap triggerPorts;
- PortInfo *portInfo;
-
- IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- portInfo = &ixEthDBPortInfo[portID];
-
- if (portInfo->enabled)
- {
- /* redundant */
- return IX_ETH_DB_SUCCESS;
- }
-
- SET_DEPENDENCY_MAP(triggerPorts, portID);
-
- /* mark as enabled */
- portInfo->enabled = TRUE;
-
- /* Operation stops here when Ethernet Learning is not enabled */
- if(IX_FEATURE_CTRL_SWCONFIG_DISABLED ==
- ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING))
- {
- return IX_ETH_DB_SUCCESS;
- }
-
- if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE && !portInfo->macAddressUploaded)
- {
- IX_ETH_DB_SUPPORT_TRACE("DB: (Support) MAC address not set on port %d, enable failed\n", portID);
-
- /* must use UnicastAddressSet() before enabling an NPE port */
- return IX_ETH_DB_MAC_UNINITIALIZED;
- }
-
- if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
- {
- IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Attempting to enable the NPE callback for port %d...\n", portID);
-
- if (!portInfo->updateMethod.userControlled
- && ((portInfo->featureCapability & IX_ETH_DB_FILTERING) != 0))
- {
- portInfo->updateMethod.updateEnabled = TRUE;
- }
-
- /* if this is first time initialization then we already have
- write access to the tree and can AccessRelease directly */
- if (!portInfo->updateMethod.treeInitialized)
- {
- IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Initializing tree for port %d\n", portID);
-
- /* create an initial tree and release access into it */
- ixEthDBUpdatePortLearningTrees(triggerPorts);
-
- /* mark tree as being initialized */
- portInfo->updateMethod.treeInitialized = TRUE;
- }
- }
-
- if (ixEthDBPortState[portID].saved)
- {
- /* previous configuration data stored, restore state */
- if ((portInfo->featureCapability & IX_ETH_DB_FIREWALL) != 0)
- {
- ixEthDBFirewallModeSet(portID, ixEthDBPortState[portID].firewallMode);
- ixEthDBFirewallInvalidAddressFilterEnable(portID, ixEthDBPortState[portID].srcAddressFilterEnabled);
- }
-
-#if 0 /* test-only */
- if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0)
- {
- ixEthDBAcceptableFrameTypeSet(portID, ixEthDBPortState[portID].frameFilter);
- ixEthDBIngressVlanTaggingEnabledSet(portID, ixEthDBPortState[portID].taggingAction);
-
- ixEthDBEgressVlanTaggingEnabledSet(portID, ixEthDBPortState[portID].transmitTaggingInfo);
- ixEthDBPortVlanMembershipSet(portID, ixEthDBPortState[portID].vlanMembership);
-
- ixEthDBPriorityMappingTableSet(portID, ixEthDBPortState[portID].priorityTable);
- }
-#endif
-
- if ((portInfo->featureCapability & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0)
- {
- ixEthDBSpanningTreeBlockingStateSet(portID, ixEthDBPortState[portID].stpBlocked);
- }
-
- ixEthDBFilteringPortMaximumRxFrameSizeSet(portID, ixEthDBPortState[portID].maxRxFrameSize);
- ixEthDBFilteringPortMaximumTxFrameSizeSet(portID, ixEthDBPortState[portID].maxTxFrameSize);
-
- /* discard previous save */
- ixEthDBPortState[portID].saved = FALSE;
- }
-
- IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Enabling succeeded for port %d\n", portID);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief disables a port
- *
- * @param portID ID of the port to disable
- *
- * This function is fully documented in the
- * main header file, IxEthDB.h
- *
- * @return IX_ETH_DB_SUCCESS if disabling was
- * successful or an appropriate error message
- * otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID)
-{
- HashIterator iterator;
- IxEthDBPortMap triggerPorts; /* ports who will have deleted records and therefore will need updating */
- BOOL result;
- PortInfo *portInfo;
- IxEthDBFeature learningEnabled;
-#if 0 /* test-only */
- IxEthDBPriorityTable classZeroTable;
-#endif
-
- IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- portInfo = &ixEthDBPortInfo[portID];
-
- if (!portInfo->enabled)
- {
- /* redundant */
- return IX_ETH_DB_SUCCESS;
- }
-
- if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
- {
- /* save filtering state */
- ixEthDBPortState[portID].firewallMode = portInfo->firewallMode;
- ixEthDBPortState[portID].frameFilter = portInfo->frameFilter;
- ixEthDBPortState[portID].taggingAction = portInfo->taggingAction;
- ixEthDBPortState[portID].stpBlocked = portInfo->stpBlocked;
- ixEthDBPortState[portID].srcAddressFilterEnabled = portInfo->srcAddressFilterEnabled;
- ixEthDBPortState[portID].maxRxFrameSize = portInfo->maxRxFrameSize;
- ixEthDBPortState[portID].maxTxFrameSize = portInfo->maxTxFrameSize;
-
- memcpy(ixEthDBPortState[portID].vlanMembership, portInfo->vlanMembership, sizeof (IxEthDBVlanSet));
- memcpy(ixEthDBPortState[portID].transmitTaggingInfo, portInfo->transmitTaggingInfo, sizeof (IxEthDBVlanSet));
- memcpy(ixEthDBPortState[portID].priorityTable, portInfo->priorityTable, sizeof (IxEthDBPriorityTable));
-
- ixEthDBPortState[portID].saved = TRUE;
-
- /* now turn off all EthDB filtering features on the port */
-
-#if 0 /* test-only */
- /* VLAN & QoS */
- if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0)
- {
- ixEthDBPortVlanMembershipRangeAdd((IxEthDBPortId) portID, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID);
- ixEthDBEgressVlanRangeTaggingEnabledSet((IxEthDBPortId) portID, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID, FALSE);
- ixEthDBAcceptableFrameTypeSet((IxEthDBPortId) portID, IX_ETH_DB_ACCEPT_ALL_FRAMES);
- ixEthDBIngressVlanTaggingEnabledSet((IxEthDBPortId) portID, IX_ETH_DB_PASS_THROUGH);
-
- memset(classZeroTable, 0, sizeof (classZeroTable));
- ixEthDBPriorityMappingTableSet((IxEthDBPortId) portID, classZeroTable);
- }
-#endif
-
- /* STP */
- if ((portInfo->featureCapability & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0)
- {
- ixEthDBSpanningTreeBlockingStateSet((IxEthDBPortId) portID, FALSE);
- }
-
- /* Firewall */
- if ((portInfo->featureCapability & IX_ETH_DB_FIREWALL) != 0)
- {
- ixEthDBFirewallModeSet((IxEthDBPortId) portID, IX_ETH_DB_FIREWALL_BLACK_LIST);
- ixEthDBFirewallTableDownload((IxEthDBPortId) portID);
- ixEthDBFirewallInvalidAddressFilterEnable((IxEthDBPortId) portID, FALSE);
- }
-
- /* Frame size filter */
- ixEthDBFilteringPortMaximumFrameSizeSet((IxEthDBPortId) portID, IX_ETH_DB_DEFAULT_FRAME_SIZE);
-
- /* WiFi */
- if ((portInfo->featureCapability & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0)
- {
- ixEthDBWiFiConversionTableDownload((IxEthDBPortId) portID);
- }
-
- /* save and disable the learning feature bit */
- learningEnabled = portInfo->featureStatus & IX_ETH_DB_LEARNING;
- portInfo->featureStatus &= ~IX_ETH_DB_LEARNING;
- }
- else
- {
- /* save the learning feature bit */
- learningEnabled = portInfo->featureStatus & IX_ETH_DB_LEARNING;
- }
-
- SET_EMPTY_DEPENDENCY_MAP(triggerPorts);
-
- ixEthDBUpdateLock();
-
- /* wipe out current entries for this port */
- BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator));
-
- while (IS_ITERATOR_VALID(&iterator))
- {
- MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data;
-
- /* check if the port match. If so, remove the entry */
- if (descriptor->portID == portID
- && (descriptor->type == IX_ETH_DB_FILTERING_RECORD || descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD)
- && !descriptor->recordData.filteringData.staticEntry)
- {
- /* delete entry */
- BUSY_RETRY(ixEthDBRemoveEntryAtHashIterator(&dbHashtable, &iterator));
-
- /* add port to the set of update trigger ports */
- JOIN_PORT_TO_MAP(triggerPorts, portID);
- }
- else
- {
- /* move to the next record */
- BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator));
- }
- }
-
- if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
- {
- if (portInfo->updateMethod.searchTree != NULL)
- {
- ixEthDBFreeMacTreeNode(portInfo->updateMethod.searchTree);
- portInfo->updateMethod.searchTree = NULL;
- }
-
- ixEthDBNPEUpdateHandler(portID, IX_ETH_DB_FILTERING_RECORD);
- }
-
- /* mark as disabled */
- portInfo->enabled = FALSE;
-
- /* disable updates unless the user has specifically altered the default behavior */
- if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
- {
- if (!portInfo->updateMethod.userControlled)
- {
- portInfo->updateMethod.updateEnabled = FALSE;
- }
-
- /* make sure we re-initialize the NPE learning tree when the port is re-enabled */
- portInfo->updateMethod.treeInitialized = FALSE;
- }
-
- ixEthDBUpdateUnlock();
-
- /* restore learning feature bit */
- portInfo->featureStatus |= learningEnabled;
-
- /* if we've removed any records or lost any events make sure to force an update */
- IS_EMPTY_DEPENDENCY_MAP(result, triggerPorts);
-
- if (!result)
- {
- ixEthDBUpdatePortLearningTrees(triggerPorts);
- }
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief sends the updated maximum Tx/Rx frame lengths to the NPE
- *
- * @param portID ID of the port to update
- *
- * @return IX_ETH_DB_SUCCESS if the update completed
- * successfully or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBPortFrameLengthsUpdate(IxEthDBPortId portID)
-{
- IxNpeMhMessage message;
- PortInfo *portInfo = &ixEthDBPortInfo[portID];
- IX_STATUS result;
-
- FILL_SETMAXFRAMELENGTHS_MSG(message, portID, portInfo->maxRxFrameSize, portInfo->maxTxFrameSize);
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- return result;
-}
-
-/**
- * @brief sets the port maximum Rx frame size
- *
- * @param portID ID of the port to set the frame size on
- * @param maximumRxFrameSize maximum Rx frame size
- *
- * This function updates the internal data structures and
- * calls ixEthDBPortFrameLengthsUpdate() for NPE update.
- *
- * This function is fully documented in the main header
- * file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation was
- * successfull or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringPortMaximumRxFrameSizeSet(IxEthDBPortId portID, UINT32 maximumRxFrameSize)
-{
- IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- if (!ixEthDBPortInfo[portID].initialized)
- {
- return IX_ETH_DB_PORT_UNINITIALIZED;
- }
-
- if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
- {
- if ((maximumRxFrameSize < IX_ETHDB_MIN_NPE_FRAME_SIZE) ||
- (maximumRxFrameSize > IX_ETHDB_MAX_NPE_FRAME_SIZE))
- {
- return IX_ETH_DB_INVALID_ARG;
- }
- }
- else
- {
- return IX_ETH_DB_NO_PERMISSION;
- }
-
- /* update internal structure */
- ixEthDBPortInfo[portID].maxRxFrameSize = maximumRxFrameSize;
-
- /* update the maximum frame size in the NPE */
- return ixEthDBPortFrameLengthsUpdate(portID);
-}
-
-/**
- * @brief sets the port maximum Tx frame size
- *
- * @param portID ID of the port to set the frame size on
- * @param maximumTxFrameSize maximum Tx frame size
- *
- * This function updates the internal data structures and
- * calls ixEthDBPortFrameLengthsUpdate() for NPE update.
- *
- * This function is fully documented in the main header
- * file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation was
- * successfull or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringPortMaximumTxFrameSizeSet(IxEthDBPortId portID, UINT32 maximumTxFrameSize)
-{
- IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- if (!ixEthDBPortInfo[portID].initialized)
- {
- return IX_ETH_DB_PORT_UNINITIALIZED;
- }
-
- if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
- {
- if ((maximumTxFrameSize < IX_ETHDB_MIN_NPE_FRAME_SIZE) ||
- (maximumTxFrameSize > IX_ETHDB_MAX_NPE_FRAME_SIZE))
- {
- return IX_ETH_DB_INVALID_ARG;
- }
- }
- else
- {
- return IX_ETH_DB_NO_PERMISSION;
- }
-
- /* update internal structure */
- ixEthDBPortInfo[portID].maxTxFrameSize = maximumTxFrameSize;
-
- /* update the maximum frame size in the NPE */
- return ixEthDBPortFrameLengthsUpdate(portID);
-}
-
-/**
- * @brief sets the port maximum Tx and Rx frame sizes
- *
- * @param portID ID of the port to set the frame size on
- * @param maximumFrameSize maximum Tx and Rx frame sizes
- *
- * This function updates the internal data structures and
- * calls ixEthDBPortFrameLengthsUpdate() for NPE update.
- *
- * Note that both the maximum Tx and Rx frame size are set
- * to the same value. This function is kept for compatibility
- * reasons.
- *
- * This function is fully documented in the main header
- * file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation was
- * successfull or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringPortMaximumFrameSizeSet(IxEthDBPortId portID, UINT32 maximumFrameSize)
-{
- IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- if (!ixEthDBPortInfo[portID].initialized)
- {
- return IX_ETH_DB_PORT_UNINITIALIZED;
- }
-
- if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
- {
- if ((maximumFrameSize < IX_ETHDB_MIN_NPE_FRAME_SIZE) ||
- (maximumFrameSize > IX_ETHDB_MAX_NPE_FRAME_SIZE))
- {
- return IX_ETH_DB_INVALID_ARG;
- }
- }
- else
- {
- return IX_ETH_DB_NO_PERMISSION;
- }
-
- /* update internal structure */
- ixEthDBPortInfo[portID].maxRxFrameSize = maximumFrameSize;
- ixEthDBPortInfo[portID].maxTxFrameSize = maximumFrameSize;
-
- /* update the maximum frame size in the NPE */
- return ixEthDBPortFrameLengthsUpdate(portID);
-}
-
-/**
- * @brief sets the MAC address of an NPE port
- *
- * @param portID port ID to set the MAC address on
- * @param macAddr pointer to the 6-byte MAC address
- *
- * This function is called by the EthAcc
- * ixEthAccUnicastMacAddressSet() and should not be
- * manually invoked unless required by special circumstances.
- *
- * @return IX_ETH_DB_SUCCESS if the operation succeeded
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
- IxNpeMhMessage message;
- IxOsalMutex *ackPortAddressLock;
- IX_STATUS result;
-
- /* use this macro instead CHECK_PORT
- as the port doesn't need to be enabled */
- IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- if (!ixEthDBPortInfo[portID].initialized)
- {
- return IX_ETH_DB_PORT_UNINITIALIZED;
- }
-
- ackPortAddressLock = &ixEthDBPortInfo[portID].npeAckLock;
-
- /* Operation stops here when Ethernet Learning is not enabled */
- if(IX_FEATURE_CTRL_SWCONFIG_DISABLED ==
- ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING))
- {
- return IX_ETH_DB_SUCCESS;
- }
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- /* exit if the port is not an Ethernet NPE */
- if (ixEthDBPortDefinitions[portID].type != IX_ETH_NPE)
- {
- return IX_ETH_DB_INVALID_PORT;
- }
-
- /* populate message */
- FILL_SETPORTADDRESS_MSG(message, portID, macAddr->macAddress);
-
- IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Sending SetPortAddress on port %d...\n", portID);
-
- /* send a SetPortAddress message */
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- if (result == IX_SUCCESS)
- {
- ixEthDBPortInfo[portID].macAddressUploaded = TRUE;
- }
-
- return result;
-}
+++ /dev/null
-/**
- * @file IxEthDBDBCore.c
- *
- * @brief Database support functions
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-
-/* list of database hashtables */
-IX_ETH_DB_PUBLIC HashTable dbHashtable;
-IX_ETH_DB_PUBLIC MatchFunction matchFunctions[IX_ETH_DB_MAX_KEY_INDEX + 1];
-IX_ETH_DB_PUBLIC BOOL ixEthDBPortUpdateRequired[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1];
-IX_ETH_DB_PUBLIC UINT32 ixEthDBKeyType[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1];
-
-/* private initialization flag */
-IX_ETH_DB_PRIVATE BOOL ethDBInitializationComplete = FALSE;
-
-/**
- * @brief initializes EthDB
- *
- * This function must be called to initialize the component.
- *
- * It does the following things:
- * - checks the port definition structure
- * - scans the capabilities of the NPE images and sets the
- * capabilities of the ports accordingly
- * - initializes the memory pools internally used in EthDB
- * for storing database records and handling data
- * - registers automatic update handlers for add and remove
- * operations
- * - registers hashing match functions, depending on key sets
- * - initializes the main database hashtable
- * - allocates contiguous memory zones to be used for NPE
- * updates
- * - registers the serialize methods used to convert data
- * into NPE-readable format
- * - starts the event processor
- *
- * Note that this function is documented in the public
- * component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS or an appropriate error if the
- * component failed to initialize correctly
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBInit(void)
-{
- IxEthDBStatus result;
-
- if (ethDBInitializationComplete)
- {
- /* redundant */
- return IX_ETH_DB_SUCCESS;
- }
-
- /* trap an invalid port definition structure */
- IX_ETH_DB_PORTS_ASSERTION;
-
- /* memory management */
- ixEthDBInitMemoryPools();
-
- /* register hashing search methods */
- ixEthDBMatchMethodsRegister(matchFunctions);
-
- /* register type-based automatic port updates */
- ixEthDBUpdateTypeRegister(ixEthDBPortUpdateRequired);
-
- /* register record to key type mappings */
- ixEthDBKeyTypeRegister(ixEthDBKeyType);
-
- /* hash table */
- ixEthDBInitHash(&dbHashtable, NUM_BUCKETS, ixEthDBEntryXORHash, matchFunctions, (FreeFunction) ixEthDBFreeMacDescriptor);
-
- /* NPE update zones */
- ixEthDBNPEUpdateAreasInit();
-
- /* register record serialization methods */
- ixEthDBRecordSerializeMethodsRegister();
-
- /* start the event processor */
- result = ixEthDBEventProcessorInit();
-
- /* scan NPE features */
- if (result == IX_ETH_DB_SUCCESS)
- {
- ixEthDBFeatureCapabilityScan();
- }
-
- ethDBInitializationComplete = TRUE;
-
- return result;
-}
-
-/**
- * @brief prepares EthDB for unloading
- *
- * This function must be called before removing the
- * EthDB component from memory (e.g. doing rmmod in
- * Linux) if the component is to be re-initialized again
- * without rebooting the platform.
- *
- * All the EthDB ports must be disabled before this
- * function is to be called. Failure to disable all
- * the ports will return the IX_ETH_DB_BUSY error.
- *
- * This function will destroy mutexes, deallocate
- * memory and stop the event processor.
- *
- * Note that this function is fully documented in the
- * main component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if de-initialization
- * completed successfully or an appropriate error
- * message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBUnload(void)
-{
- IxEthDBPortId portIndex;
-
- if (!ethDBInitializationComplete)
- {
- /* redundant */
- return IX_ETH_DB_SUCCESS;
- }
-
- /* check if any ports are enabled */
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- if (ixEthDBPortInfo[portIndex].enabled)
- {
- return IX_ETH_DB_BUSY;
- }
- }
-
- /* free port resources */
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE)
- {
- ixOsalMutexDestroy(&ixEthDBPortInfo[portIndex].npeAckLock);
- }
-
- ixEthDBPortInfo[portIndex].initialized = FALSE;
- }
-
- /* shutdown event processor */
- ixEthDBStopLearningFunction();
-
- /* deallocate NPE update zones */
- ixEthDBNPEUpdateAreasUnload();
-
- ethDBInitializationComplete = FALSE;
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief adds a new entry to the Ethernet database
- *
- * @param newRecordTemplate address of the record template to use
- * @param updateTrigger port map containing the update triggers
- * resulting from this update operation
- *
- * Creates a new database entry, populates it with the data
- * copied from the given template and adds the record to the
- * database hash table.
- * It also checks whether the new record type is registered to trigger
- * automatic updates; if it is, the update trigger will contain the
- * port on which the record insertion was performed, as well as the
- * old port in case the addition was a record migration (from one port
- * to the other). The caller can use the updateTrigger to trigger
- * automatic updates on the ports changed as a result of this addition.
- *
- * @retval IX_ETH_DB_SUCCESS addition successful
- * @retval IX_ETH_DB_NOMEM insertion failed, no memory left in the mac descriptor memory pool
- * @retval IX_ETH_DB_BUSY database busy, cannot insert due to locking
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBAdd(MacDescriptor *newRecordTemplate, IxEthDBPortMap updateTrigger)
-{
- IxEthDBStatus result;
- MacDescriptor *newDescriptor;
- IxEthDBPortId originalPortID;
- HashNode *node = NULL;
-
- BUSY_RETRY(ixEthDBSearchHashEntry(&dbHashtable, ixEthDBKeyType[newRecordTemplate->type], newRecordTemplate, &node));
-
- TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER;
-
- if (node == NULL)
- {
- /* not found, create a new one */
- newDescriptor = ixEthDBAllocMacDescriptor();
-
- if (newDescriptor == NULL)
- {
- return IX_ETH_DB_NOMEM; /* no memory */
- }
-
- /* old port does not exist, avoid unnecessary updates */
- originalPortID = newRecordTemplate->portID;
- }
- else
- {
- /* a node with the same key exists, will update node */
- newDescriptor = (MacDescriptor *) node->data;
-
- /* save original port id */
- originalPortID = newDescriptor->portID;
- }
-
- /* copy/update fields into new record */
- memcpy(newDescriptor->macAddress, newRecordTemplate->macAddress, sizeof (IxEthDBMacAddr));
- memcpy(&newDescriptor->recordData, &newRecordTemplate->recordData, sizeof (IxEthDBRecordData));
-
- newDescriptor->type = newRecordTemplate->type;
- newDescriptor->portID = newRecordTemplate->portID;
- newDescriptor->user = newRecordTemplate->user;
-
- if (node == NULL)
- {
- /* new record, insert into hashtable */
- BUSY_RETRY_WITH_RESULT(ixEthDBAddHashEntry(&dbHashtable, newDescriptor), result);
-
- if (result != IX_ETH_DB_SUCCESS)
- {
- ixEthDBFreeMacDescriptor(newDescriptor);
-
- return result; /* insertion failed */
- }
- }
-
- if (node != NULL)
- {
- /* release access */
- ixEthDBReleaseHashNode(node);
- }
-
- /* trigger add/remove update if required by type */
- if (updateTrigger != NULL &&
- ixEthDBPortUpdateRequired[newRecordTemplate->type])
- {
- /* add new port to update list */
- JOIN_PORT_TO_MAP(updateTrigger, newRecordTemplate->portID);
-
- /* check if record has moved, we'll need to update the old port as well */
- if (originalPortID != newDescriptor->portID)
- {
- JOIN_PORT_TO_MAP(updateTrigger, originalPortID);
- }
- }
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief remove a record from the Ethernet database
- *
- * @param templateRecord template record used to determine
- * what record is to be removed
- * @param updateTrigger port map containing the update triggers
- * resulting from this update operation
- *
- * This function will examine the template record it receives
- * and attempts to delete a record of the same type and containing
- * the same keys as the template record. If deletion is successful
- * and the record type is registered for automatic port updates the
- * port will also be set in the updateTrigger port map, so that the
- * client can perform an update of the port.
- *
- * @retval IX_ETH_DB_SUCCESS removal was successful
- * @retval IX_ETH_DB_NO_SUCH_ADDR the record with the given MAC address was not found
- * @retval IX_ETH_DB_BUSY database busy, cannot remove due to locking
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBRemove(MacDescriptor *templateRecord, IxEthDBPortMap updateTrigger)
-{
- IxEthDBStatus result;
-
- TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER;
-
- BUSY_RETRY_WITH_RESULT(ixEthDBRemoveHashEntry(&dbHashtable, ixEthDBKeyType[templateRecord->type], templateRecord), result);
-
- if (result != IX_ETH_DB_SUCCESS)
- {
- return IX_ETH_DB_NO_SUCH_ADDR; /* not found */
- }
-
- /* trigger add/remove update if required by type */
- if (updateTrigger != NULL
- &&ixEthDBPortUpdateRequired[templateRecord->type])
- {
- /* add new port to update list */
- JOIN_PORT_TO_MAP(updateTrigger, templateRecord->portID);
- }
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief register record key types
- *
- * This function registers the appropriate key types,
- * depending on record types.
- *
- * All filtering records use the MAC address as the key.
- * WiFi and Firewall records use a compound key consisting
- * in both the MAC address and the port ID.
- *
- * @return the number of registered record types
- */
-IX_ETH_DB_PUBLIC
-UINT32 ixEthDBKeyTypeRegister(UINT32 *keyType)
-{
- /* safety */
- memset(keyType, 0, sizeof (keyType));
-
- /* register all known record types */
- keyType[IX_ETH_DB_FILTERING_RECORD] = IX_ETH_DB_MAC_KEY;
- keyType[IX_ETH_DB_FILTERING_VLAN_RECORD] = IX_ETH_DB_MAC_KEY;
- keyType[IX_ETH_DB_ALL_FILTERING_RECORDS] = IX_ETH_DB_MAC_KEY;
- keyType[IX_ETH_DB_WIFI_RECORD] = IX_ETH_DB_MAC_PORT_KEY;
- keyType[IX_ETH_DB_FIREWALL_RECORD] = IX_ETH_DB_MAC_PORT_KEY;
-
- return 5;
-}
-
-/**
- * @brief Sets a user-defined field into a database record
- *
- * Note that this function is fully documented in the main component
- * header file.
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBUserFieldSet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void *field)
-{
- HashNode *result = NULL;
-
- if (macAddr == NULL)
- {
- return IX_ETH_DB_INVALID_ARG;
- }
-
- if (recordType == IX_ETH_DB_FILTERING_RECORD)
- {
- result = ixEthDBSearch(macAddr, recordType);
- }
- else if (recordType == IX_ETH_DB_FILTERING_VLAN_RECORD)
- {
- result = ixEthDBVlanSearch(macAddr, vlanID, recordType);
- }
- else if (recordType == IX_ETH_DB_WIFI_RECORD || recordType == IX_ETH_DB_FIREWALL_RECORD)
- {
- IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
- result = ixEthDBPortSearch(macAddr, portID, recordType);
- }
- else
- {
- return IX_ETH_DB_INVALID_ARG;
- }
-
- if (result == NULL)
- {
- return IX_ETH_DB_NO_SUCH_ADDR;
- }
-
- ((MacDescriptor *) result->data)->user = field;
-
- ixEthDBReleaseHashNode(result);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief Retrieves a user-defined field from a database record
- *
- * Note that this function is fully documented in the main component
- * header file.
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBUserFieldGet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void **field)
-{
- HashNode *result = NULL;
-
- if (macAddr == NULL || field == NULL)
- {
- return IX_ETH_DB_INVALID_ARG;
- }
-
- if (recordType == IX_ETH_DB_FILTERING_RECORD)
- {
- result = ixEthDBSearch(macAddr, recordType);
- }
- else if (recordType == IX_ETH_DB_FILTERING_VLAN_RECORD)
- {
- result = ixEthDBVlanSearch(macAddr, vlanID, recordType);
- }
- else if (recordType == IX_ETH_DB_WIFI_RECORD || recordType == IX_ETH_DB_FIREWALL_RECORD)
- {
- IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
- result = ixEthDBPortSearch(macAddr, portID, recordType);
- }
- else
- {
- return IX_ETH_DB_INVALID_ARG;
- }
-
- if (result == NULL)
- {
- return IX_ETH_DB_NO_SUCH_ADDR;
- }
-
- *field = ((MacDescriptor *) result->data)->user;
-
- ixEthDBReleaseHashNode(result);
-
- return IX_ETH_DB_SUCCESS;
-}
+++ /dev/null
-/**
- * @file IxEthDBEvents.c
- *
- * @brief Implementation of the event processor component
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include <IxNpeMh.h>
-#include <IxFeatureCtrl.h>
-
-#include "IxEthDB_p.h"
-
-/* forward prototype declarations */
-IX_ETH_DB_PUBLIC void ixEthDBEventProcessorLoop(void *);
-IX_ETH_DB_PUBLIC void ixEthDBNPEEventCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg);
-IX_ETH_DB_PRIVATE void ixEthDBProcessEvent(PortEvent *local_event, IxEthDBPortMap triggerPorts);
-IX_ETH_DB_PRIVATE IxEthDBStatus ixEthDBTriggerPortUpdate(UINT32 eventType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, BOOL staticEntry);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBStartLearningFunction(void);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBStopLearningFunction(void);
-
-/* data */
-IX_ETH_DB_PRIVATE IxOsalSemaphore eventQueueSemaphore;
-IX_ETH_DB_PRIVATE PortEventQueue eventQueue;
-IX_ETH_DB_PRIVATE IxOsalMutex eventQueueLock;
-IX_ETH_DB_PRIVATE IxOsalMutex portUpdateLock;
-
-IX_ETH_DB_PRIVATE BOOL ixEthDBLearningShutdown = FALSE;
-IX_ETH_DB_PRIVATE BOOL ixEthDBEventProcessorRunning = FALSE;
-
-/* imported data */
-extern HashTable dbHashtable;
-
-/**
- * @brief initializes the event processor
- *
- * Initializes the event processor queue and processing thread.
- * Called from ixEthDBInit() DB-subcomponent master init function.
- *
- * @warning do not call directly
- *
- * @retval IX_ETH_DB_SUCCESS initialization was successful
- * @retval IX_ETH_DB_FAIL initialization failed (OSAL or mutex init failure)
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBEventProcessorInit(void)
-{
- if (ixOsalMutexInit(&portUpdateLock) != IX_SUCCESS)
- {
- return IX_ETH_DB_FAIL;
- }
-
- if (ixOsalMutexInit(&eventQueueLock) != IX_SUCCESS)
- {
- return IX_ETH_DB_FAIL;
- }
-
- if (IX_FEATURE_CTRL_SWCONFIG_ENABLED ==
- ixFeatureCtrlSwConfigurationCheck (IX_FEATURECTRL_ETH_LEARNING))
- {
-
- /* start processor loop thread */
- if (ixEthDBStartLearningFunction() != IX_ETH_DB_SUCCESS)
- {
- return IX_ETH_DB_FAIL;
- }
- }
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief initializes the event queue and the event processor
- *
- * This function is called by the component initialization
- * function, ixEthDBInit().
- *
- * @warning do not call directly
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or IX_ETH_DB_FAIL otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBStartLearningFunction(void)
-{
- IxOsalThread eventProcessorThread;
- IxOsalThreadAttr threadAttr;
-
- threadAttr.name = "EthDB event thread";
- threadAttr.stackSize = 32 * 1024; /* 32kbytes */
- threadAttr.priority = 128;
-
- /* reset event queue */
- ixOsalMutexLock(&eventQueueLock, IX_OSAL_WAIT_FOREVER);
-
- RESET_QUEUE(&eventQueue);
-
- ixOsalMutexUnlock(&eventQueueLock);
-
- /* init event queue semaphore */
- if (ixOsalSemaphoreInit(&eventQueueSemaphore, 0) != IX_SUCCESS)
- {
- return IX_ETH_DB_FAIL;
- }
-
- ixEthDBLearningShutdown = FALSE;
-
- /* create processor loop thread */
- if (ixOsalThreadCreate(&eventProcessorThread, &threadAttr, ixEthDBEventProcessorLoop, NULL) != IX_SUCCESS)
- {
- return IX_ETH_DB_FAIL;
- }
-
- /* start event processor */
- ixOsalThreadStart(&eventProcessorThread);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief stops the event processor
- *
- * Stops the event processor and frees the event queue semaphore
- * Called by the component de-initialization function, ixEthDBUnload()
- *
- * @warning do not call directly
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or IX_ETH_DB_FAIL otherwise;
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBStopLearningFunction(void)
-{
- ixEthDBLearningShutdown = TRUE;
-
- /* wake up event processing loop to actually process the shutdown event */
- ixOsalSemaphorePost(&eventQueueSemaphore);
-
- if (ixOsalSemaphoreDestroy(&eventQueueSemaphore) != IX_SUCCESS)
- {
- return IX_ETH_DB_FAIL;
- }
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief default NPE event processing callback
- *
- * @param npeID ID of the NPE that generated the event
- * @param msg NPE message (encapsulated event)
- *
- * Creates an event object on the Ethernet event processor queue
- * and signals the new event by incrementing the event queue semaphore.
- * Events are processed by @ref ixEthDBEventProcessorLoop() which runs
- * at user level.
- *
- * @see ixEthDBEventProcessorLoop()
- *
- * @warning do not call directly
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNPEEventCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg)
-{
- PortEvent *local_event;
-
- IX_ETH_DB_IRQ_EVENTS_TRACE("DB: (Events) new event received by processor callback from port %d, id 0x%X\n", IX_ETH_DB_NPE_TO_PORT_ID(npeID), NPE_MSG_ID(msg), 0, 0, 0, 0);
-
- if (CAN_ENQUEUE(&eventQueue))
- {
- TEST_FIXTURE_LOCK_EVENT_QUEUE;
-
- local_event = QUEUE_HEAD(&eventQueue);
-
- /* create event structure on queue */
- local_event->eventType = NPE_MSG_ID(msg);
- local_event->portID = IX_ETH_DB_NPE_TO_PORT_ID(npeID);
-
- /* update queue */
- PUSH_UPDATE_QUEUE(&eventQueue);
-
- TEST_FIXTURE_UNLOCK_EVENT_QUEUE;
-
- IX_ETH_DB_IRQ_EVENTS_TRACE("DB: (Events) Waking up main processor loop...\n", 0, 0, 0, 0, 0, 0);
-
- /* increment event queue semaphore */
- ixOsalSemaphorePost(&eventQueueSemaphore);
- }
- else
- {
- IX_ETH_DB_IRQ_EVENTS_TRACE("DB: (Events) Warning: could not enqueue event (overflow)\n", 0, 0, 0, 0, 0, 0);
- }
-}
-
-/**
- * @brief Ethernet event processor loop
- *
- * Extracts at most EVENT_PROCESSING_LIMIT batches of events and
- * sends them for processing to @ref ixEthDBProcessEvent().
- * Triggers port updates which normally follow learning events.
- *
- * @warning do not call directly, executes in separate thread
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBEventProcessorLoop(void *unused1)
-{
- IxEthDBPortMap triggerPorts;
- IxEthDBPortId portIndex;
-
- ixEthDBEventProcessorRunning = TRUE;
-
- IX_ETH_DB_EVENTS_TRACE("DB: (Events) Event processor loop was started\n");
-
- while (!ixEthDBLearningShutdown)
- {
- BOOL keepProcessing = TRUE;
- UINT32 processedEvents = 0;
-
- IX_ETH_DB_EVENTS_VERBOSE_TRACE("DB: (Events) Waiting for new learning event...\n");
-
- ixOsalSemaphoreWait(&eventQueueSemaphore, IX_OSAL_WAIT_FOREVER);
-
- IX_ETH_DB_EVENTS_VERBOSE_TRACE("DB: (Events) Received new event\n");
-
- if (!ixEthDBLearningShutdown)
- {
- /* port update handling */
- SET_EMPTY_DEPENDENCY_MAP(triggerPorts);
-
- while (keepProcessing)
- {
- PortEvent local_event;
- UINT32 intLockKey;
-
- /* lock queue */
- ixOsalMutexLock(&eventQueueLock, IX_OSAL_WAIT_FOREVER);
-
- /* lock NPE interrupts */
- intLockKey = ixOsalIrqLock();
-
- /* extract event */
- local_event = *(QUEUE_TAIL(&eventQueue));
-
- SHIFT_UPDATE_QUEUE(&eventQueue);
-
- ixOsalIrqUnlock(intLockKey);
-
- ixOsalMutexUnlock(&eventQueueLock);
-
- IX_ETH_DB_EVENTS_TRACE("DB: (Events) Processing event with ID 0x%X\n", local_event.eventType);
-
- ixEthDBProcessEvent(&local_event, triggerPorts);
-
- processedEvents++;
-
- if (processedEvents > EVENT_PROCESSING_LIMIT /* maximum burst reached? */
- || ixOsalSemaphoreTryWait(&eventQueueSemaphore) != IX_SUCCESS) /* or empty queue? */
- {
- keepProcessing = FALSE;
- }
- }
-
- ixEthDBUpdatePortLearningTrees(triggerPorts);
- }
- }
-
- /* turn off automatic updates */
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- ixEthDBPortInfo[portIndex].updateMethod.updateEnabled = FALSE;
- }
-
- ixEthDBEventProcessorRunning = FALSE;
-}
-
-/**
- * @brief event processor routine
- *
- * @param event event to be processed
- * @param triggerPorts port map accumulating ports to be updated
- *
- * Processes learning events by synchronizing the database with
- * newly learnt data. Called only by @ref ixEthDBEventProcessorLoop().
- *
- * @warning do not call directly
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBProcessEvent(PortEvent *local_event, IxEthDBPortMap triggerPorts)
-{
- MacDescriptor recordTemplate;
-
- switch (local_event->eventType)
- {
- case IX_ETH_DB_ADD_FILTERING_RECORD:
- /* add record */
- memset(&recordTemplate, 0, sizeof (recordTemplate));
- memcpy(recordTemplate.macAddress, local_event->macAddr.macAddress, sizeof (IxEthDBMacAddr));
-
- recordTemplate.type = IX_ETH_DB_FILTERING_RECORD;
- recordTemplate.portID = local_event->portID;
- recordTemplate.recordData.filteringData.staticEntry = local_event->staticEntry;
-
- ixEthDBAdd(&recordTemplate, triggerPorts);
-
- IX_ETH_DB_EVENTS_TRACE("DB: (Events) Added record on port %d\n", local_event->portID);
-
- break;
-
- case IX_ETH_DB_REMOVE_FILTERING_RECORD:
- /* remove record */
- memset(&recordTemplate, 0, sizeof (recordTemplate));
- memcpy(recordTemplate.macAddress, local_event->macAddr.macAddress, sizeof (IxEthDBMacAddr));
-
- recordTemplate.type = IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD;
-
- ixEthDBRemove(&recordTemplate, triggerPorts);
-
- IX_ETH_DB_EVENTS_TRACE("DB: (Events) Removed record on port %d\n", local_event->portID);
-
- break;
-
- default:
- /* can't handle/not interested in this event type */
- ERROR_LOG("DB: (Events) Event processor received an unknown event type (0x%X)\n", local_event->eventType);
-
- return;
- }
-}
-
-/**
- * @brief asynchronously adds a filtering record
- * by posting an ADD_FILTERING_RECORD event to the event queue
- *
- * @param macAddr MAC address of the new record
- * @param portID port ID of the new record
- * @param staticEntry TRUE if record is static, FALSE if dynamic
- *
- * @return IX_ETH_DB_SUCCESS if the event creation was
- * successfull or IX_ETH_DB_BUSY if the event queue is full
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBTriggerAddPortUpdate(IxEthDBMacAddr *macAddr, IxEthDBPortId portID, BOOL staticEntry)
-{
- MacDescriptor reference;
-
- TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER;
-
- /* fill search fields */
- memcpy(reference.macAddress, macAddr, sizeof (IxEthDBMacAddr));
- reference.portID = portID;
-
- /* set acceptable record types */
- reference.type = IX_ETH_DB_ALL_FILTERING_RECORDS;
-
- if (ixEthDBPeekHashEntry(&dbHashtable, IX_ETH_DB_MAC_PORT_KEY, &reference) == IX_ETH_DB_SUCCESS)
- {
- /* already have an identical record */
- return IX_ETH_DB_SUCCESS;
- }
- else
- {
- return ixEthDBTriggerPortUpdate(IX_ETH_DB_ADD_FILTERING_RECORD, macAddr, portID, staticEntry);
- }
-}
-
-/**
- * @brief asynchronously removes a filtering record
- * by posting a REMOVE_FILTERING_RECORD event to the event queue
- *
- * @param macAddr MAC address of the record to remove
- * @param portID port ID of the record to remove
- *
- * @return IX_ETH_DB_SUCCESS if the event creation was
- * successfull or IX_ETH_DB_BUSY if the event queue is full
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBTriggerRemovePortUpdate(IxEthDBMacAddr *macAddr, IxEthDBPortId portID)
-{
- if (ixEthDBPeek(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS) != IX_ETH_DB_NO_SUCH_ADDR)
- {
- return ixEthDBTriggerPortUpdate(IX_ETH_DB_REMOVE_FILTERING_RECORD, macAddr, portID, FALSE);
- }
- else
- {
- return IX_ETH_DB_NO_SUCH_ADDR;
- }
-}
-
-/**
- * @brief adds an ADD or REMOVE event to the main event queue
- *
- * @param eventType event type - IX_ETH_DB_ADD_FILTERING_RECORD
- * to add and IX_ETH_DB_REMOVE_FILTERING_RECORD to remove a
- * record.
- *
- * @return IX_ETH_DB_SUCCESS if the event was successfully
- * sent or IX_ETH_DB_BUSY if the event queue is full
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBTriggerPortUpdate(UINT32 eventType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, BOOL staticEntry)
-{
- UINT32 intLockKey;
-
- /* lock interrupts to protect queue */
- intLockKey = ixOsalIrqLock();
-
- if (CAN_ENQUEUE(&eventQueue))
- {
- PortEvent *queueEvent = QUEUE_HEAD(&eventQueue);
-
- /* update fields on the queue */
- memcpy(queueEvent->macAddr.macAddress, macAddr->macAddress, sizeof (IxEthDBMacAddr));
-
- queueEvent->eventType = eventType;
- queueEvent->portID = portID;
- queueEvent->staticEntry = staticEntry;
-
- PUSH_UPDATE_QUEUE(&eventQueue);
-
- /* imcrement event queue semaphore */
- ixOsalSemaphorePost(&eventQueueSemaphore);
-
- /* unlock interrupts */
- ixOsalIrqUnlock(intLockKey);
-
- return IX_ETH_DB_SUCCESS;
- }
- else /* event queue full */
- {
- /* unlock interrupts */
- ixOsalIrqUnlock(intLockKey);
-
- return IX_ETH_DB_BUSY;
- }
-}
-
-/**
- * @brief Locks learning tree updates and port disable
- *
- *
- * This function locks portUpdateLock single mutex. It is primarily used
- * to avoid executing 'port disable' during ELT maintenance.
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBUpdateLock(void)
-{
- ixOsalMutexLock(&portUpdateLock, IX_OSAL_WAIT_FOREVER);
-}
-
-/**
- * @brief Unlocks learning tree updates and port disable
- *
- *
- * This function unlocks a portUpdateLock mutex. It is primarily used
- * to avoid executing 'port disable' during ELT maintenance.
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBUpdateUnlock(void)
-{
- ixOsalMutexUnlock(&portUpdateLock);
-}
-
+++ /dev/null
-/**
- * @file IxEthDBFeatures.c
- *
- * @brief Implementation of the EthDB feature control API
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxNpeDl.h"
-#include "IxEthDBQoS.h"
-#include "IxEthDB_p.h"
-
-/**
- * @brief scans the capabilities of the loaded NPE images
- *
- * This function MUST be called by the ixEthDBInit() function.
- * No EthDB features (including learning and filtering) are enabled
- * before this function is called.
- *
- * @return none
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBFeatureCapabilityScan(void)
-{
- IxNpeDlImageId imageId, npeAImageId;
- IxEthDBPortId portIndex;
- PortInfo *portInfo;
- IxEthDBPriorityTable defaultPriorityTable;
- IX_STATUS result;
- UINT32 queueIndex;
- UINT32 queueStructureIndex;
- UINT32 trafficClassDefinitionIndex;
-
- /* read version of NPE A - required to set the AQM queues for B and C */
- npeAImageId.functionalityId = 0;
- ixNpeDlLoadedImageGet(IX_NPEDL_NPEID_NPEA, &npeAImageId);
-
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- IxNpeMhMessage msg;
-
- portInfo = &ixEthDBPortInfo[portIndex];
-
- /* check and bypass if NPE B or C is fused out */
- if (ixEthDBSingleEthNpeCheck(portIndex) != IX_ETH_DB_SUCCESS) continue;
-
- /* all ports are capable of LEARNING by default */
- portInfo->featureCapability |= IX_ETH_DB_LEARNING;
- portInfo->featureStatus |= IX_ETH_DB_LEARNING;
-
- if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE)
- {
-
- if (ixNpeDlLoadedImageGet(IX_ETH_DB_PORT_ID_TO_NPE(portIndex), &imageId) != IX_SUCCESS)
- {
- WARNING_LOG("DB: (FeatureScan) NpeDl did not provide the image ID for NPE port %d\n", portIndex);
- }
- else
- {
- /* initialize and empty NPE response mutex */
- ixOsalMutexInit(&portInfo->npeAckLock);
- ixOsalMutexLock(&portInfo->npeAckLock, IX_OSAL_WAIT_FOREVER);
-
- /* check NPE response to GetStatus */
- msg.data[0] = IX_ETHNPE_NPE_GETSTATUS << 24;
- msg.data[1] = 0;
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portIndex), msg, result);
- if (result != IX_SUCCESS)
- {
- WARNING_LOG("DB: (FeatureScan) warning, could not send message to the NPE\n");
- continue;
- }
-
-
- if (imageId.functionalityId == 0x00
- || imageId.functionalityId == 0x03
- || imageId.functionalityId == 0x04
- || imageId.functionalityId == 0x80)
- {
- portInfo->featureCapability |= IX_ETH_DB_FILTERING;
- portInfo->featureCapability |= IX_ETH_DB_FIREWALL;
- portInfo->featureCapability |= IX_ETH_DB_SPANNING_TREE_PROTOCOL;
- }
- else if (imageId.functionalityId == 0x01
- || imageId.functionalityId == 0x81)
- {
- portInfo->featureCapability |= IX_ETH_DB_FILTERING;
- portInfo->featureCapability |= IX_ETH_DB_FIREWALL;
- portInfo->featureCapability |= IX_ETH_DB_SPANNING_TREE_PROTOCOL;
- portInfo->featureCapability |= IX_ETH_DB_VLAN_QOS;
- }
- else if (imageId.functionalityId == 0x02
- || imageId.functionalityId == 0x82)
- {
- portInfo->featureCapability |= IX_ETH_DB_WIFI_HEADER_CONVERSION;
- portInfo->featureCapability |= IX_ETH_DB_FIREWALL;
- portInfo->featureCapability |= IX_ETH_DB_SPANNING_TREE_PROTOCOL;
- portInfo->featureCapability |= IX_ETH_DB_VLAN_QOS;
- }
-
- /* reset AQM queues */
- memset(portInfo->ixEthDBTrafficClassAQMAssignments, 0, sizeof (portInfo->ixEthDBTrafficClassAQMAssignments));
-
- /* ensure there's at least one traffic class record in the definition table, otherwise we have no default case, hence no queues */
- IX_ENSURE(sizeof (ixEthDBTrafficClassDefinitions) != 0, "DB: no traffic class definitions found, check IxEthDBQoS.h");
-
- /* find the traffic class definition index compatible with the current NPE A functionality ID */
- for (trafficClassDefinitionIndex = 0 ;
- trafficClassDefinitionIndex < sizeof (ixEthDBTrafficClassDefinitions) / sizeof (ixEthDBTrafficClassDefinitions[0]);
- trafficClassDefinitionIndex++)
- {
- if (ixEthDBTrafficClassDefinitions[trafficClassDefinitionIndex][IX_ETH_DB_NPE_A_FUNCTIONALITY_ID_INDEX] == npeAImageId.functionalityId)
- {
- /* found it */
- break;
- }
- }
-
- /* select the default case if we went over the array boundary */
- if (trafficClassDefinitionIndex == sizeof (ixEthDBTrafficClassDefinitions) / sizeof (ixEthDBTrafficClassDefinitions[0]))
- {
- trafficClassDefinitionIndex = 0; /* the first record is the default case */
- }
-
- /* select queue assignment structure based on the traffic class configuration index */
- queueStructureIndex = ixEthDBTrafficClassDefinitions[trafficClassDefinitionIndex][IX_ETH_DB_QUEUE_ASSIGNMENT_INDEX];
-
- /* only traffic class 0 is active at initialization time */
- portInfo->ixEthDBTrafficClassCount = 1;
-
- /* enable port, VLAN and Firewall feature bits to initialize QoS/VLAN/Firewall configuration */
- portInfo->featureStatus |= IX_ETH_DB_VLAN_QOS;
- portInfo->featureStatus |= IX_ETH_DB_FIREWALL;
- portInfo->enabled = TRUE;
-
-#define CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */
-#ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */
- /* set VLAN initial configuration (permissive) */
- if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0) /* QoS-enabled image */
- {
- /* QoS capable */
- portInfo->ixEthDBTrafficClassAvailable = ixEthDBTrafficClassDefinitions[trafficClassDefinitionIndex][IX_ETH_DB_TRAFFIC_CLASS_COUNT_INDEX];
-
- /* set AQM queues */
- for (queueIndex = 0 ; queueIndex < IX_IEEE802_1Q_QOS_PRIORITY_COUNT ; queueIndex++)
- {
- portInfo->ixEthDBTrafficClassAQMAssignments[queueIndex] = ixEthDBQueueAssignments[queueStructureIndex][queueIndex];
- }
-
- /* set default PVID (0) and default traffic class 0 */
- ixEthDBPortVlanTagSet(portIndex, 0);
-
- /* enable reception of all frames */
- ixEthDBAcceptableFrameTypeSet(portIndex, IX_ETH_DB_ACCEPT_ALL_FRAMES);
-
- /* clear full VLAN membership */
- ixEthDBPortVlanMembershipRangeRemove(portIndex, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID);
-
- /* clear TTI table - no VLAN tagged frames will be transmitted */
- ixEthDBEgressVlanRangeTaggingEnabledSet(portIndex, 0, 4094, FALSE);
-
- /* set membership on 0, otherwise no Tx or Rx is working */
- ixEthDBPortVlanMembershipAdd(portIndex, 0);
- }
- else /* QoS not available in this image */
-#endif /* test-only */
- {
- /* initialize traffic class availability (only class 0 is available) */
- portInfo->ixEthDBTrafficClassAvailable = 1;
-
- /* point all AQM queues to traffic class 0 */
- for (queueIndex = 0 ; queueIndex < IX_IEEE802_1Q_QOS_PRIORITY_COUNT ; queueIndex++)
- {
- portInfo->ixEthDBTrafficClassAQMAssignments[queueIndex] =
- ixEthDBQueueAssignments[queueStructureIndex][0];
- }
- }
-
-#ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */
- /* download priority mapping table and Rx queue configuration */
- memset (defaultPriorityTable, 0, sizeof (defaultPriorityTable));
- ixEthDBPriorityMappingTableSet(portIndex, defaultPriorityTable);
-#endif
-
- /* by default we turn off invalid source MAC address filtering */
- ixEthDBFirewallInvalidAddressFilterEnable(portIndex, FALSE);
-
- /* disable port, VLAN, Firewall feature bits */
- portInfo->featureStatus &= ~IX_ETH_DB_VLAN_QOS;
- portInfo->featureStatus &= ~IX_ETH_DB_FIREWALL;
- portInfo->enabled = FALSE;
-
- /* enable filtering by default if present */
- if ((portInfo->featureCapability & IX_ETH_DB_FILTERING) != 0)
- {
- portInfo->featureStatus |= IX_ETH_DB_FILTERING;
- }
- }
- }
- }
-}
-
-/**
- * @brief returns the capability of a port
- *
- * @param portID ID of the port
- * @param featureSet location to store the port capability in
- *
- * This function will save the capability set of the given port
- * into the given location. Capabilities are bit-ORed, each representing
- * a bit of the feature set.
- *
- * Note that this function is documented in the main component
- * public header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or IX_ETH_DB_INVALID_PORT if the given port is invalid
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeatureCapabilityGet(IxEthDBPortId portID, IxEthDBFeature *featureSet)
-{
- IX_ETH_DB_CHECK_PORT_INITIALIZED(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(featureSet);
-
- *featureSet = ixEthDBPortInfo[portID].featureCapability;
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief enables or disables a port capability
- *
- * @param portID ID of the port
- * @param feature feature to enable or disable
- * @param enabled TRUE to enable the selected feature or FALSE to disable it
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, BOOL enable)
-{
- PortInfo *portInfo;
- IxEthDBPriorityTable defaultPriorityTable;
- IxEthDBVlanSet vlanSet;
- IxEthDBStatus status = IX_ETH_DB_SUCCESS;
- BOOL portEnabled;
-
- IX_ETH_DB_CHECK_PORT_INITIALIZED(portID);
-
- portInfo = &ixEthDBPortInfo[portID];
- portEnabled = portInfo->enabled;
-
- /* check that only one feature is selected */
- if (!ixEthDBCheckSingleBitValue(feature))
- {
- return IX_ETH_DB_FEATURE_UNAVAILABLE;
- }
-
- /* port capable of this feature? */
- if ((portInfo->featureCapability & feature) == 0)
- {
- return IX_ETH_DB_FEATURE_UNAVAILABLE;
- }
-
- /* mutual exclusion between learning and WiFi header conversion */
- if (enable && ((feature | portInfo->featureStatus) & (IX_ETH_DB_FILTERING | IX_ETH_DB_WIFI_HEADER_CONVERSION))
- == (IX_ETH_DB_FILTERING | IX_ETH_DB_WIFI_HEADER_CONVERSION))
- {
- return IX_ETH_DB_NO_PERMISSION;
- }
-
- /* learning must be enabled before filtering */
- if (enable && (feature == IX_ETH_DB_FILTERING) && ((portInfo->featureStatus & IX_ETH_DB_LEARNING) == 0))
- {
- return IX_ETH_DB_NO_PERMISSION;
- }
-
- /* filtering must be disabled before learning */
- if (!enable && (feature == IX_ETH_DB_LEARNING) && ((portInfo->featureStatus & IX_ETH_DB_FILTERING) != 0))
- {
- return IX_ETH_DB_NO_PERMISSION;
- }
-
- /* redundant enabling or disabling */
- if ((!enable && ((portInfo->featureStatus & feature) == 0))
- || (enable && ((portInfo->featureStatus & feature) != 0)))
- {
- /* do nothing */
- return IX_ETH_DB_SUCCESS;
- }
-
- /* force port enabled */
- portInfo->enabled = TRUE;
-
- if (enable)
- {
- /* turn on enable bit */
- portInfo->featureStatus |= feature;
-
-#ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */
- /* if this is VLAN/QoS set the default priority table */
- if (feature == IX_ETH_DB_VLAN_QOS)
- {
- /* turn on VLAN/QoS (most permissive mode):
- - set default 802.1Q priority mapping table, in accordance to the
- availability of traffic classes
- - set the acceptable frame filter to accept all
- - set the Ingress tagging mode to pass-through
- - set full VLAN membership list
- - set full TTI table
- - set the default 802.1Q tag to 0 (VLAN ID 0, Pri 0, CFI 0)
- - enable TPID port extraction
- */
-
- portInfo->ixEthDBTrafficClassCount = portInfo->ixEthDBTrafficClassAvailable;
-
- /* set default 802.1Q priority mapping table - note that C indexing starts from 0, so we substract 1 here */
- memcpy (defaultPriorityTable,
- (const void *) ixEthIEEE802_1QUserPriorityToTrafficClassMapping[portInfo->ixEthDBTrafficClassCount - 1],
- sizeof (defaultPriorityTable));
-
- /* update priority mapping and AQM queue assignments */
- status = ixEthDBPriorityMappingTableSet(portID, defaultPriorityTable);
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBAcceptableFrameTypeSet(portID, IX_ETH_DB_ACCEPT_ALL_FRAMES);
- }
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBIngressVlanTaggingEnabledSet(portID, IX_ETH_DB_PASS_THROUGH);
- }
-
- /* set membership and TTI tables */
- memset (vlanSet, 0xFF, sizeof (vlanSet));
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- /* use the internal function to bypass PVID check */
- status = ixEthDBPortVlanTableSet(portID, portInfo->vlanMembership, vlanSet);
- }
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- /* use the internal function to bypass PVID check */
- status = ixEthDBPortVlanTableSet(portID, portInfo->transmitTaggingInfo, vlanSet);
- }
-
- /* reset the PVID */
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBPortVlanTagSet(portID, 0);
- }
-
- /* enable TPID port extraction */
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBVlanPortExtractionEnable(portID, TRUE);
- }
- }
- else if (feature == IX_ETH_DB_FIREWALL)
-#endif
- {
- /* firewall starts in black-list mode unless otherwise configured before *
- * note that invalid source MAC address filtering is disabled by default */
- if (portInfo->firewallMode != IX_ETH_DB_FIREWALL_BLACK_LIST
- && portInfo->firewallMode != IX_ETH_DB_FIREWALL_WHITE_LIST)
- {
- status = ixEthDBFirewallModeSet(portID, IX_ETH_DB_FIREWALL_BLACK_LIST);
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBFirewallInvalidAddressFilterEnable(portID, FALSE);
- }
- }
- }
-
- if (status != IX_ETH_DB_SUCCESS)
- {
- /* checks failed, disable */
- portInfo->featureStatus &= ~feature;
- }
- }
- else
- {
- /* turn off features */
- if (feature == IX_ETH_DB_FIREWALL)
- {
- /* turning off the firewall is equivalent to:
- - set to black-list mode
- - clear all the entries and download the new table
- - turn off the invalid source address checking
- */
-
- status = ixEthDBDatabaseClear(portID, IX_ETH_DB_FIREWALL_RECORD);
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBFirewallModeSet(portID, IX_ETH_DB_FIREWALL_BLACK_LIST);
- }
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBFirewallInvalidAddressFilterEnable(portID, FALSE);
- }
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBFirewallTableDownload(portID);
- }
- }
- else if (feature == IX_ETH_DB_WIFI_HEADER_CONVERSION)
- {
- /* turn off header conversion */
- status = ixEthDBDatabaseClear(portID, IX_ETH_DB_WIFI_RECORD);
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBWiFiConversionTableDownload(portID);
- }
- }
-#ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */
- else if (feature == IX_ETH_DB_VLAN_QOS)
- {
- /* turn off VLAN/QoS:
- - set a priority mapping table with one traffic class
- - set the acceptable frame filter to accept all
- - set the Ingress tagging mode to pass-through
- - clear the VLAN membership list
- - clear the TTI table
- - set the default 802.1Q tag to 0 (VLAN ID 0, Pri 0, CFI 0)
- - disable TPID port extraction
- */
-
- /* initialize all => traffic class 0 priority mapping table */
- memset (defaultPriorityTable, 0, sizeof (defaultPriorityTable));
- portInfo->ixEthDBTrafficClassCount = 1;
- status = ixEthDBPriorityMappingTableSet(portID, defaultPriorityTable);
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBAcceptableFrameTypeSet(portID, IX_ETH_DB_ACCEPT_ALL_FRAMES);
- }
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBIngressVlanTaggingEnabledSet(portID, IX_ETH_DB_PASS_THROUGH);
- }
-
- /* clear membership and TTI tables */
- memset (vlanSet, 0, sizeof (vlanSet));
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- /* use the internal function to bypass PVID check */
- status = ixEthDBPortVlanTableSet(portID, portInfo->vlanMembership, vlanSet);
- }
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- /* use the internal function to bypass PVID check */
- status = ixEthDBPortVlanTableSet(portID, portInfo->transmitTaggingInfo, vlanSet);
- }
-
- /* reset the PVID */
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBPortVlanTagSet(portID, 0);
- }
-
- /* disable TPID port extraction */
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBVlanPortExtractionEnable(portID, FALSE);
- }
- }
-#endif
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- /* checks passed, disable */
- portInfo->featureStatus &= ~feature;
- }
- }
-
- /* restore port enabled state */
- portInfo->enabled = portEnabled;
-
- return status;
-}
-
-/**
- * @brief returns the status of a feature
- *
- * @param portID port ID
- * @param present location to store a boolean value indicating
- * if the feature is present (TRUE) or not (FALSE)
- * @param enabled location to store a booleam value indicating
- * if the feature is present (TRUE) or not (FALSE)
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeatureStatusGet(IxEthDBPortId portID, IxEthDBFeature feature, BOOL *present, BOOL *enabled)
-{
- PortInfo *portInfo;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(present);
-
- IX_ETH_DB_CHECK_REFERENCE(enabled);
-
- portInfo = &ixEthDBPortInfo[portID];
-
- *present = (portInfo->featureCapability & feature) != 0;
- *enabled = (portInfo->featureStatus & feature) != 0;
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief returns the value of an EthDB property
- *
- * @param portID ID of the port
- * @param feature feature owning the property
- * @param property ID of the property
- * @param type location to store the property type into
- * @param value location to store the property value into
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeaturePropertyGet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, IxEthDBPropertyType *type, void *value)
-{
- IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(type);
-
- IX_ETH_DB_CHECK_REFERENCE(value);
-
- if (feature == IX_ETH_DB_VLAN_QOS)
- {
- if (property == IX_ETH_DB_QOS_TRAFFIC_CLASS_COUNT_PROPERTY)
- {
- * (UINT32 *) value = ixEthDBPortInfo[portID].ixEthDBTrafficClassCount;
- *type = IX_ETH_DB_INTEGER_PROPERTY;
-
- return IX_ETH_DB_SUCCESS;
- }
- else if (property >= IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY
- && property <= IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY)
- {
- UINT32 classDelta = property - IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY;
-
- if (classDelta >= ixEthDBPortInfo[portID].ixEthDBTrafficClassCount)
- {
- return IX_ETH_DB_FAIL;
- }
-
- * (UINT32 *) value = ixEthDBPortInfo[portID].ixEthDBTrafficClassAQMAssignments[classDelta];
- *type = IX_ETH_DB_INTEGER_PROPERTY;
-
- return IX_ETH_DB_SUCCESS;
- }
- }
-
- return IX_ETH_DB_INVALID_ARG;
-}
-
-/**
- * @brief sets the value of an EthDB property
- *
- * @param portID ID of the port
- * @param feature feature owning the property
- * @param property ID of the property
- * @param value location containing the property value
- *
- * This function implements a private property intended
- * only for EthAcc usage. Upon setting the IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE
- * property (the value is ignored), the availability of traffic classes is
- * frozen to whatever traffic class structure is currently in use.
- * This means that if VLAN_QOS has been enabled before EthAcc
- * initialization then all the defined traffic classes will be available;
- * otherwise only one traffic class (0) will be available.
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h as not accepting any parameters. The
- * current implementation is only intended for the private use of EthAcc.
- *
- * Also note that once this function is called the effect is irreversible,
- * unless EthDB is complete unloaded and re-initialized.
- *
- * @return IX_ETH_DB_INVALID_ARG (no read-write properties are
- * supported in this release)
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeaturePropertySet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, void *value)
-{
- IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
- if ((feature == IX_ETH_DB_VLAN_QOS) && (property == IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE))
- {
- ixEthDBPortInfo[portID].ixEthDBTrafficClassAvailable = ixEthDBPortInfo[portID].ixEthDBTrafficClassCount;
-
- return IX_ETH_DB_SUCCESS;
- }
-
- return IX_ETH_DB_INVALID_ARG;
-}
+++ /dev/null
-/**
- * @file IxEthDBFirewall.c
- *
- * @brief Implementation of the firewall API
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#include "IxEthDB_p.h"
-
-/**
- * @brief updates the NPE firewall operating mode and
- * firewall address table
- *
- * @param portID ID of the port
- * @param epDelta initial entry point for binary searches (NPE optimization)
- * @param address address of the firewall MAC address table
- *
- * This function will send a message to the NPE configuring the
- * firewall mode (white list or black list), invalid source
- * address filtering and downloading a new MAC address database
- * to be used for firewall matching.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or IX_ETH_DB_FAIL otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFirewallUpdate(IxEthDBPortId portID, void *address, UINT32 epDelta)
-{
- IxNpeMhMessage message;
- IX_STATUS result;
-
- UINT32 mode = 0;
- PortInfo *portInfo = &ixEthDBPortInfo[portID];
-
- mode = (portInfo->srcAddressFilterEnabled != FALSE) << 1 | (portInfo->firewallMode == IX_ETH_DB_FIREWALL_WHITE_LIST);
-
- FILL_SETFIREWALLMODE_MSG(message,
- IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID),
- epDelta,
- mode,
- IX_OSAL_MMU_VIRT_TO_PHYS(address));
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- return result;
-}
-
-/**
- * @brief configures the firewall white list/black list
- * access mode
- *
- * @param portID ID of the port
- * @param mode firewall filtering mode (IX_ETH_DB_FIREWALL_WHITE_LIST
- * or IX_ETH_DB_FIREWALL_BLACK_LIST)
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFirewallModeSet(IxEthDBPortId portID, IxEthDBFirewallMode mode)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL);
-
- if (mode != IX_ETH_DB_FIREWALL_WHITE_LIST
- && mode != IX_ETH_DB_FIREWALL_BLACK_LIST)
- {
- return IX_ETH_DB_INVALID_ARG;
- }
-
- ixEthDBPortInfo[portID].firewallMode = mode;
-
- return ixEthDBFirewallTableDownload(portID);
-}
-
-/**
- * @brief enables or disables the invalid source MAC address filter
- *
- * @param portID ID of the port
- * @param enable TRUE to enable invalid source MAC address filtering
- * or FALSE to disable it
- *
- * The invalid source MAC address filter will discard, when enabled,
- * frames whose source MAC address is a multicast or the broadcast MAC
- * address.
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFirewallInvalidAddressFilterEnable(IxEthDBPortId portID, BOOL enable)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL);
-
- ixEthDBPortInfo[portID].srcAddressFilterEnabled = enable;
-
- return ixEthDBFirewallTableDownload(portID);
-}
-
-/**
- * @brief adds a firewall record
- *
- * @param portID ID of the port
- * @param macAddr MAC address of the new record
- *
- * This function will add a new firewall record
- * on the specified port, using the specified
- * MAC address. If the record already exists this
- * function will silently return IX_ETH_DB_SUCCESS,
- * although no duplicate records are added.
- *
- * Note that this function is documented in the main
- * component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFirewallEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
- MacDescriptor recordTemplate;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL);
-
- memcpy(recordTemplate.macAddress, macAddr, sizeof (IxEthDBMacAddr));
-
- recordTemplate.type = IX_ETH_DB_FIREWALL_RECORD;
- recordTemplate.portID = portID;
-
- return ixEthDBAdd(&recordTemplate, NULL);
-}
-
-/**
- * @brief removes a firewall record
- *
- * @param portID ID of the port
- * @param macAddr MAC address of the record to remove
- *
- * This function will attempt to remove a firewall
- * record from the given port, using the specified
- * MAC address.
- *
- * Note that this function is documented in the main
- * component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully of an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFirewallEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
- MacDescriptor recordTemplate;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL);
-
- memcpy(recordTemplate.macAddress, macAddr, sizeof (IxEthDBMacAddr));
-
- recordTemplate.type = IX_ETH_DB_FIREWALL_RECORD;
- recordTemplate.portID = portID;
-
- return ixEthDBRemove(&recordTemplate, NULL);
-}
-
-/**
- * @brief downloads the firewall address table to an NPE
- *
- * @param portID ID of the port
- *
- * This function will download the firewall address table to
- * an NPE port.
- *
- * Note that this function is documented in the main
- * component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or IX_ETH_DB_FAIL otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFirewallTableDownload(IxEthDBPortId portID)
-{
- IxEthDBPortMap query;
- IxEthDBStatus result;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL);
-
- SET_DEPENDENCY_MAP(query, portID);
-
- ixEthDBUpdateLock();
-
- ixEthDBPortInfo[portID].updateMethod.searchTree = ixEthDBQuery(NULL, query, IX_ETH_DB_FIREWALL_RECORD, MAX_FW_SIZE);
-
- result = ixEthDBNPEUpdateHandler(portID, IX_ETH_DB_FIREWALL_RECORD);
-
- ixEthDBUpdateUnlock();
-
- return result;
-}
+++ /dev/null
-/**
- * @file ethHash.c
- *
- * @brief Hashtable implementation
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#include "IxEthDB_p.h"
-#include "IxEthDBLocks_p.h"
-
-/**
- * @addtogroup EthDB
- *
- * @{
- */
-
-/**
- * @brief initializes a hash table object
- *
- * @param hashTable uninitialized hash table structure
- * @param numBuckets number of buckets to use
- * @param entryHashFunction hash function used
- * to hash entire hash node data block (for adding)
- * @param matchFunctions array of match functions, indexed on type,
- * used to differentiate records with the same hash value
- * @param freeFunction function used to free node data blocks
- *
- * Initializes the given hash table object.
- *
- * @internal
- */
-void ixEthDBInitHash(HashTable *hashTable,
- UINT32 numBuckets,
- HashFunction entryHashFunction,
- MatchFunction *matchFunctions,
- FreeFunction freeFunction)
-{
- UINT32 bucketIndex;
- UINT32 hashSize = numBuckets * sizeof(HashNode *);
-
- /* entry hashing, matching and freeing methods */
- hashTable->entryHashFunction = entryHashFunction;
- hashTable->matchFunctions = matchFunctions;
- hashTable->freeFunction = freeFunction;
-
- /* buckets */
- hashTable->numBuckets = numBuckets;
-
- /* set to 0 all buckets */
- memset(hashTable->hashBuckets, 0, hashSize);
-
- /* init bucket locks - note that initially all mutexes are unlocked after MutexInit()*/
- for (bucketIndex = 0 ; bucketIndex < numBuckets ; bucketIndex++)
- {
- ixOsalFastMutexInit(&hashTable->bucketLocks[bucketIndex]);
- }
-}
-
-/**
- * @brief adds an entry to the hash table
- *
- * @param hashTable hash table to add the entry to
- * @param entry entry to add
- *
- * The entry will be hashed using the entry hashing function and added to the
- * hash table, unless a locking blockage occurs, in which case the caller
- * should retry.
- *
- * @retval IX_ETH_DB_SUCCESS if adding <i>entry</i> has succeeded
- * @retval IX_ETH_DB_NOMEM if there's no memory left in the hash node pool
- * @retval IX_ETH_DB_BUSY if there's a locking failure on the insertion path
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBAddHashEntry(HashTable *hashTable, void *entry)
-{
- UINT32 hashValue = hashTable->entryHashFunction(entry);
- UINT32 bucketIndex = hashValue % hashTable->numBuckets;
- HashNode *bucket = hashTable->hashBuckets[bucketIndex];
- HashNode *newNode;
-
- LockStack locks;
-
- INIT_STACK(&locks);
-
- /* lock bucket */
- PUSH_LOCK(&locks, &hashTable->bucketLocks[bucketIndex]);
-
- /* lock insertion element (first in chain), if any */
- if (bucket != NULL)
- {
- PUSH_LOCK(&locks, &bucket->lock);
- }
-
- /* get new node */
- newNode = ixEthDBAllocHashNode();
-
- if (newNode == NULL)
- {
- /* unlock everything */
- UNROLL_STACK(&locks);
-
- return IX_ETH_DB_NOMEM;
- }
-
- /* init lock - note that mutexes are unlocked after MutexInit */
- ixOsalFastMutexInit(&newNode->lock);
-
- /* populate new link */
- newNode->data = entry;
-
- /* add to bucket */
- newNode->next = bucket;
- hashTable->hashBuckets[bucketIndex] = newNode;
-
- /* unlock bucket and insertion point */
- UNROLL_STACK(&locks);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief removes an entry from the hashtable
- *
- * @param hashTable hash table to remove entry from
- * @param keyType type of record key used for matching
- * @param reference reference key used to identify the entry
- *
- * The reference key will be hashed using the key hashing function,
- * the entry is searched using the hashed value and then examined
- * against the reference entry using the match function. A positive
- * match will trigger the deletion of the entry.
- * Locking failures are reported and the caller should retry.
- *
- * @retval IX_ETH_DB_SUCCESS if the removal was successful
- * @retval IX_ETH_DB_NO_SUCH_ADDR if the entry was not found
- * @retval IX_ETH_DB_BUSY if a locking failure occured during the process
- *
- * @internal
- */
-IxEthDBStatus ixEthDBRemoveHashEntry(HashTable *hashTable, int keyType, void *reference)
-{
- UINT32 hashValue = hashTable->entryHashFunction(reference);
- UINT32 bucketIndex = hashValue % hashTable->numBuckets;
- HashNode *node = hashTable->hashBuckets[bucketIndex];
- HashNode *previousNode = NULL;
-
- LockStack locks;
-
- INIT_STACK(&locks);
-
- while (node != NULL)
- {
- /* try to lock node */
- PUSH_LOCK(&locks, &node->lock);
-
- if (hashTable->matchFunctions[keyType](reference, node->data))
- {
- /* found entry */
- if (node->next != NULL)
- {
- PUSH_LOCK(&locks, &node->next->lock);
- }
-
- if (previousNode == NULL)
- {
- /* node is head of chain */
- PUSH_LOCK(&locks, &hashTable->bucketLocks[bucketIndex]);
-
- hashTable->hashBuckets[bucketIndex] = node->next;
-
- POP_LOCK(&locks);
- }
- else
- {
- /* relink */
- previousNode->next = node->next;
- }
-
- UNROLL_STACK(&locks);
-
- /* free node */
- hashTable->freeFunction(node->data);
- ixEthDBFreeHashNode(node);
-
- return IX_ETH_DB_SUCCESS;
- }
- else
- {
- if (previousNode != NULL)
- {
- /* unlock previous node */
- SHIFT_STACK(&locks);
- }
-
- /* advance to next element in chain */
- previousNode = node;
- node = node->next;
- }
- }
-
- UNROLL_STACK(&locks);
-
- /* not found */
- return IX_ETH_DB_NO_SUCH_ADDR;
-}
-
-/**
- * @brief retrieves an entry from the hash table
- *
- * @param hashTable hash table to perform the search into
- * @param reference search key (a MAC address)
- * @param keyType type of record key used for matching
- * @param searchResult pointer where a reference to the located hash node
- * is placed
- *
- * Searches the entry with the same key as <i>reference</i> and places the
- * pointer to the resulting node in <i>searchResult</i>.
- * An implicit write access lock is granted after a search, which gives the
- * caller the opportunity to modify the entry.
- * Access should be released as soon as possible using @ref ixEthDBReleaseHashNode().
- *
- * @see ixEthDBReleaseHashNode()
- *
- * @retval IX_ETH_DB_SUCCESS if the search was completed successfully
- * @retval IX_ETH_DB_NO_SUCH_ADDRESS if no entry with the given key was found
- * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case
- * the caller should retry
- *
- * @warning unless the return value is <b>IX_ETH_DB_SUCCESS</b> the searchResult
- * location is NOT modified and therefore using a NULL comparison test when the
- * value was not properly initialized would be an error
- *
- * @internal
- */
-IxEthDBStatus ixEthDBSearchHashEntry(HashTable *hashTable, int keyType, void *reference, HashNode **searchResult)
-{
- UINT32 hashValue;
- HashNode *node;
-
- hashValue = hashTable->entryHashFunction(reference);
- node = hashTable->hashBuckets[hashValue % hashTable->numBuckets];
-
- while (node != NULL)
- {
- TRY_LOCK(&node->lock);
-
- if (hashTable->matchFunctions[keyType](reference, node->data))
- {
- *searchResult = node;
-
- return IX_ETH_DB_SUCCESS;
- }
- else
- {
- UNLOCK(&node->lock);
-
- node = node->next;
- }
- }
-
- /* not found */
- return IX_ETH_DB_NO_SUCH_ADDR;
-}
-
-/**
- * @brief reports the existence of an entry in the hash table
- *
- * @param hashTable hash table to perform the search into
- * @param reference search key (a MAC address)
- * @param keyType type of record key used for matching
- *
- * Searches the entry with the same key as <i>reference</i>.
- * No implicit write access lock is granted after a search, hence the
- * caller cannot access or modify the entry. The result is only temporary.
- *
- * @see ixEthDBReleaseHashNode()
- *
- * @retval IX_ETH_DB_SUCCESS if the search was completed successfully
- * @retval IX_ETH_DB_NO_SUCH_ADDRESS if no entry with the given key was found
- * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case
- * the caller should retry
- *
- * @internal
- */
-IxEthDBStatus ixEthDBPeekHashEntry(HashTable *hashTable, int keyType, void *reference)
-{
- UINT32 hashValue;
- HashNode *node;
-
- hashValue = hashTable->entryHashFunction(reference);
- node = hashTable->hashBuckets[hashValue % hashTable->numBuckets];
-
- while (node != NULL)
- {
- TRY_LOCK(&node->lock);
-
- if (hashTable->matchFunctions[keyType](reference, node->data))
- {
- UNLOCK(&node->lock);
-
- return IX_ETH_DB_SUCCESS;
- }
- else
- {
- UNLOCK(&node->lock);
-
- node = node->next;
- }
- }
-
- /* not found */
- return IX_ETH_DB_NO_SUCH_ADDR;
-}
-
-/**
- * @brief releases the write access lock
- *
- * @pre the node should have been obtained via @ref ixEthDBSearchHashEntry()
- *
- * @see ixEthDBSearchHashEntry()
- *
- * @internal
- */
-void ixEthDBReleaseHashNode(HashNode *node)
-{
- UNLOCK(&node->lock);
-}
-
-/**
- * @brief initializes a hash iterator
- *
- * @param hashTable hash table to be iterated
- * @param iterator iterator object
- *
- * If the initialization is successful the iterator will point to the
- * first hash table record (if any).
- * Testing if the iterator has not passed the end of the table should be
- * done using the IS_ITERATOR_VALID(iteratorPtr) macro.
- * An implicit write access lock is granted on the entry pointed by the iterator.
- * The access is automatically revoked when the iterator is incremented.
- * If the caller decides to terminate the iteration before the end of the table is
- * passed then the manual access release method, @ref ixEthDBReleaseHashIterator,
- * must be called.
- *
- * @see ixEthDBReleaseHashIterator()
- *
- * @retval IX_ETH_DB_SUCCESS if initialization was successful and the iterator points
- * to the first valid table node
- * @retval IX_ETH_DB_FAIL if the table is empty
- * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case the caller
- * should retry
- *
- * @warning do not use ixEthDBReleaseHashNode() on entries pointed by the iterator, as this
- * might place the database in a permanent invalid lock state
- *
- * @internal
- */
-IxEthDBStatus ixEthDBInitHashIterator(HashTable *hashTable, HashIterator *iterator)
-{
- iterator->bucketIndex = 0;
- iterator->node = NULL;
- iterator->previousNode = NULL;
-
- return ixEthDBIncrementHashIterator(hashTable, iterator);
-}
-
-/**
- * @brief releases the write access locks of the iterator nodes
- *
- * @warning use of this function is required only when the caller terminates an iteration
- * before reaching the end of the table
- *
- * @see ixEthDBInitHashIterator()
- * @see ixEthDBIncrementHashIterator()
- *
- * @param iterator iterator whose node(s) should be unlocked
- *
- * @internal
- */
-void ixEthDBReleaseHashIterator(HashIterator *iterator)
-{
- if (iterator->previousNode != NULL)
- {
- UNLOCK(&iterator->previousNode->lock);
- }
-
- if (iterator->node != NULL)
- {
- UNLOCK(&iterator->node->lock);
- }
-}
-
-/**
- * @brief incremenents an iterator so that it points to the next valid entry of the table
- * (if any)
- *
- * @param hashTable hash table to iterate
- * @param iterator iterator object
- *
- * @pre the iterator object must be initialized using @ref ixEthDBInitHashIterator()
- *
- * If the increment operation is successful the iterator will point to the
- * next hash table record (if any).
- * Testing if the iterator has not passed the end of the table should be
- * done using the IS_ITERATOR_VALID(iteratorPtr) macro.
- * An implicit write access lock is granted on the entry pointed by the iterator.
- * The access is automatically revoked when the iterator is re-incremented.
- * If the caller decides to terminate the iteration before the end of the table is
- * passed then the manual access release method, @ref ixEthDBReleaseHashIterator,
- * must be called.
- * Is is guaranteed that no other thread can remove or change the iterated entry until
- * the iterator is incremented successfully.
- *
- * @see ixEthDBReleaseHashIterator()
- *
- * @retval IX_ETH_DB_SUCCESS if the operation was successful and the iterator points
- * to the next valid table node
- * @retval IX_ETH_DB_FAIL if the iterator has passed the end of the table
- * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case the caller
- * should retry
- *
- * @warning do not use ixEthDBReleaseHashNode() on entries pointed by the iterator, as this
- * might place the database in a permanent invalid lock state
- *
- * @internal
- */
-IxEthDBStatus ixEthDBIncrementHashIterator(HashTable *hashTable, HashIterator *iterator)
-{
- /* unless iterator is just initialized... */
- if (iterator->node != NULL)
- {
- /* try next in chain */
- if (iterator->node->next != NULL)
- {
- TRY_LOCK(&iterator->node->next->lock);
-
- if (iterator->previousNode != NULL)
- {
- UNLOCK(&iterator->previousNode->lock);
- }
-
- iterator->previousNode = iterator->node;
- iterator->node = iterator->node->next;
-
- return IX_ETH_DB_SUCCESS;
- }
- else
- {
- /* last in chain, prepare for next bucket */
- iterator->bucketIndex++;
- }
- }
-
- /* try next used bucket */
- for (; iterator->bucketIndex < hashTable->numBuckets ; iterator->bucketIndex++)
- {
- HashNode **nodePtr = &(hashTable->hashBuckets[iterator->bucketIndex]);
- HashNode *node = *nodePtr;
-#if (CPU!=SIMSPARCSOLARIS) && !defined (__wince)
- if (((iterator->bucketIndex & IX_ETHDB_BUCKET_INDEX_MASK) == 0) &&
- (iterator->bucketIndex < (hashTable->numBuckets - IX_ETHDB_BUCKETPTR_AHEAD)))
- {
- /* preload next cache line (2 cache line ahead) */
- nodePtr += IX_ETHDB_BUCKETPTR_AHEAD;
- __asm__ ("pld [%0];\n": : "r" (nodePtr));
- }
-#endif
- if (node != NULL)
- {
- TRY_LOCK(&node->lock);
-
- /* unlock last one or two nodes in the previous chain */
- if (iterator->node != NULL)
- {
- UNLOCK(&iterator->node->lock);
-
- if (iterator->previousNode != NULL)
- {
- UNLOCK(&iterator->previousNode->lock);
- }
- }
-
- /* redirect iterator */
- iterator->previousNode = NULL;
- iterator->node = node;
-
- return IX_ETH_DB_SUCCESS;
- }
- }
-
- /* could not advance iterator */
- if (iterator->node != NULL)
- {
- UNLOCK(&iterator->node->lock);
-
- if (iterator->previousNode != NULL)
- {
- UNLOCK(&iterator->previousNode->lock);
- }
-
- iterator->node = NULL;
- }
-
- return IX_ETH_DB_END;
-}
-
-/**
- * @brief removes an entry pointed by an iterator
- *
- * @param hashTable iterated hash table
- * @param iterator iterator object
- *
- * Removes the entry currently pointed by the iterator and repositions the iterator
- * on the next valid entry (if any). Handles locking issues automatically and
- * implicitely grants write access lock to the new pointed entry.
- * Failures due to concurrent threads having write access locks in the same region
- * preserve the state of the database and the iterator object, leaving the caller
- * free to retry without loss of access. It is guaranteed that only the thread owning
- * the iterator can remove the object pointed by the iterator.
- *
- * @retval IX_ETH_DB_SUCCESS if removal has succeeded
- * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case the caller
- * should retry
- *
- * @internal
- */
-IxEthDBStatus ixEthDBRemoveEntryAtHashIterator(HashTable *hashTable, HashIterator *iterator)
-{
- HashIterator nextIteratorPos;
- LockStack locks;
-
- INIT_STACK(&locks);
-
- /* set initial bucket index for next position */
- nextIteratorPos.bucketIndex = iterator->bucketIndex;
-
- /* compute iterator position before removing anything and lock ahead */
- if (iterator->node->next != NULL)
- {
- PUSH_LOCK(&locks, &iterator->node->next->lock);
-
- /* reposition on the next node in the chain */
- nextIteratorPos.node = iterator->node->next;
- nextIteratorPos.previousNode = iterator->previousNode;
- }
- else
- {
- /* try next chain - don't know yet if we'll find anything */
- nextIteratorPos.node = NULL;
-
- /* if we find something it's a chain head */
- nextIteratorPos.previousNode = NULL;
-
- /* browse up in the buckets to find a non-null chain */
- while (++nextIteratorPos.bucketIndex < hashTable->numBuckets)
- {
- nextIteratorPos.node = hashTable->hashBuckets[nextIteratorPos.bucketIndex];
-
- if (nextIteratorPos.node != NULL)
- {
- /* found a non-empty chain, try to lock head */
- PUSH_LOCK(&locks, &nextIteratorPos.node->lock);
-
- break;
- }
- }
- }
-
- /* restore links over the to-be-deleted item */
- if (iterator->previousNode == NULL)
- {
- /* first in chain, lock bucket */
- PUSH_LOCK(&locks, &hashTable->bucketLocks[iterator->bucketIndex]);
-
- hashTable->hashBuckets[iterator->bucketIndex] = iterator->node->next;
-
- POP_LOCK(&locks);
- }
- else
- {
- /* relink */
- iterator->previousNode->next = iterator->node->next;
-
- /* unlock last remaining node in current chain when moving between chains */
- if (iterator->node->next == NULL)
- {
- UNLOCK(&iterator->previousNode->lock);
- }
- }
-
- /* delete entry */
- hashTable->freeFunction(iterator->node->data);
- ixEthDBFreeHashNode(iterator->node);
-
- /* reposition iterator */
- *iterator = nextIteratorPos;
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @}
- */
+++ /dev/null
-/**
- * @file IxEthDBLearning.c
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-
-/**
- * @brief hashes the mac address in a mac descriptor with a XOR function
- *
- * @param entry pointer to a mac descriptor to be hashed
- *
- * This function only extracts the mac address and employs ixEthDBKeyXORHash()
- * to do the actual hashing.
- * Used only to add a whole entry to a hash table, as opposed to searching which
- * takes only a key and uses the key hashing directly.
- *
- * @see ixEthDBKeyXORHash()
- *
- * @return the hash value
- *
- * @internal
- */
-UINT32 ixEthDBEntryXORHash(void *entry)
-{
- MacDescriptor *descriptor = (MacDescriptor *) entry;
-
- return ixEthDBKeyXORHash(descriptor->macAddress);
-}
-
-/**
- * @brief hashes a mac address
- *
- * @param key pointer to a 6 byte structure (typically an IxEthDBMacAddr pointer)
- * to be hashed
- *
- * Given a 6 bytes MAC address, the hash used is:
- *
- * hash(MAC[0:5]) = MAC[0:1] ^ MAC[2:3] ^ MAC[4:5]
- *
- * Used by the hash table to search and remove entries based
- * solely on their keys (mac addresses).
- *
- * @return the hash value
- *
- * @internal
- */
-UINT32 ixEthDBKeyXORHash(void *key)
-{
- UINT32 hashValue;
- UINT8 *value = (UINT8 *) key;
-
- hashValue = (value[5] << 8) | value[4];
- hashValue ^= (value[3] << 8) | value[2];
- hashValue ^= (value[1] << 8) | value[0];
-
- return hashValue;
-}
-
-/**
- * @brief mac descriptor match function
- *
- * @param reference mac address (typically an IxEthDBMacAddr pointer) structure
- * @param entry pointer to a mac descriptor whose key (mac address) is to be
- * matched against the reference key
- *
- * Used by the hash table to retrieve entries. Hashing entries can produce
- * collisions, i.e. descriptors with different mac addresses and the same
- * hash value, where this function is used to differentiate entries.
- *
- * @retval TRUE if the entry matches the reference key (equal addresses)
- * @retval FALSE if the entry does not match the reference key
- *
- * @internal
- */
-BOOL ixEthDBAddressMatch(void *reference, void *entry)
-{
- return (ixEthDBAddressCompare(reference, ((MacDescriptor *) entry)->macAddress) == 0);
-}
-
-/**
- * @brief compares two mac addresses
- *
- * @param mac1 first mac address to compare
- * @param mac2 second mac address to compare
- *
- * This comparison works in a similar way to strcmp, producing similar results.
- * Used to insert values keyed on mac addresses into binary search trees.
- *
- * @retval -1 if mac1 < mac2
- * @retval 0 if ma1 == mac2
- * @retval 1 if mac1 > mac2
- */
-UINT32 ixEthDBAddressCompare(UINT8 *mac1, UINT8 *mac2)
-{
- UINT32 local_index;
-
- for (local_index = 0 ; local_index < IX_IEEE803_MAC_ADDRESS_SIZE ; local_index++)
- {
- if (mac1[local_index] > mac2[local_index])
- {
- return 1;
- }
- else if (mac1[local_index] < mac2[local_index])
- {
- return -1;
- }
- }
-
- return 0;
-}
-
+++ /dev/null
-/**
- * @file IxEthDBDBMem.c
- *
- * @brief Memory handling routines for the MAC address database
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#include "IxEthDB_p.h"
-
-IX_ETH_DB_PRIVATE HashNode *nodePool = NULL;
-IX_ETH_DB_PRIVATE MacDescriptor *macPool = NULL;
-IX_ETH_DB_PRIVATE MacTreeNode *treePool = NULL;
-
-IX_ETH_DB_PRIVATE HashNode nodePoolArea[NODE_POOL_SIZE];
-IX_ETH_DB_PRIVATE MacDescriptor macPoolArea[MAC_POOL_SIZE];
-IX_ETH_DB_PRIVATE MacTreeNode treePoolArea[TREE_POOL_SIZE];
-
-IX_ETH_DB_PRIVATE IxOsalMutex nodePoolLock;
-IX_ETH_DB_PRIVATE IxOsalMutex macPoolLock;
-IX_ETH_DB_PRIVATE IxOsalMutex treePoolLock;
-
-#define LOCK_NODE_POOL { ixOsalMutexLock(&nodePoolLock, IX_OSAL_WAIT_FOREVER); }
-#define UNLOCK_NODE_POOL { ixOsalMutexUnlock(&nodePoolLock); }
-
-#define LOCK_MAC_POOL { ixOsalMutexLock(&macPoolLock, IX_OSAL_WAIT_FOREVER); }
-#define UNLOCK_MAC_POOL { ixOsalMutexUnlock(&macPoolLock); }
-
-#define LOCK_TREE_POOL { ixOsalMutexLock(&treePoolLock, IX_OSAL_WAIT_FOREVER); }
-#define UNLOCK_TREE_POOL { ixOsalMutexUnlock(&treePoolLock); }
-
-/* private function prototypes */
-IX_ETH_DB_PRIVATE MacDescriptor* ixEthDBPoolAllocMacDescriptor(void);
-IX_ETH_DB_PRIVATE void ixEthDBPoolFreeMacDescriptor(MacDescriptor *macDescriptor);
-
-/**
- * @addtogroup EthMemoryManagement
- *
- * @{
- */
-
-/**
- * @brief initializes the memory pools used by the ethernet database component
- *
- * Initializes the hash table node, mac descriptor and mac tree node pools.
- * Called at initialization time by @ref ixEthDBInit().
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBInitMemoryPools(void)
-{
- int local_index;
-
- /* HashNode pool */
- ixOsalMutexInit(&nodePoolLock);
-
- for (local_index = 0 ; local_index < NODE_POOL_SIZE ; local_index++)
- {
- HashNode *freeNode = &nodePoolArea[local_index];
-
- freeNode->nextFree = nodePool;
- nodePool = freeNode;
- }
-
- /* MacDescriptor pool */
- ixOsalMutexInit(&macPoolLock);
-
- for (local_index = 0 ; local_index < MAC_POOL_SIZE ; local_index++)
- {
- MacDescriptor *freeDescriptor = &macPoolArea[local_index];
-
- freeDescriptor->nextFree = macPool;
- macPool = freeDescriptor;
- }
-
- /* MacTreeNode pool */
- ixOsalMutexInit(&treePoolLock);
-
- for (local_index = 0 ; local_index < TREE_POOL_SIZE ; local_index++)
- {
- MacTreeNode *freeNode = &treePoolArea[local_index];
-
- freeNode->nextFree = treePool;
- treePool = freeNode;
- }
-}
-
-/**
- * @brief allocates a hash node from the pool
- *
- * Allocates a hash node and resets its value.
- *
- * @return the allocated hash node or NULL if the pool is empty
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-HashNode* ixEthDBAllocHashNode(void)
-{
- HashNode *allocatedNode = NULL;
-
- if (nodePool != NULL)
- {
- LOCK_NODE_POOL;
-
- allocatedNode = nodePool;
- nodePool = nodePool->nextFree;
-
- UNLOCK_NODE_POOL;
-
- memset(allocatedNode, 0, sizeof(HashNode));
- }
-
- return allocatedNode;
-}
-
-/**
- * @brief frees a hash node into the pool
- *
- * @param hashNode node to be freed
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBFreeHashNode(HashNode *hashNode)
-{
- if (hashNode != NULL)
- {
- LOCK_NODE_POOL;
-
- hashNode->nextFree = nodePool;
- nodePool = hashNode;
-
- UNLOCK_NODE_POOL;
- }
-}
-
-/**
- * @brief allocates a mac descriptor from the pool
- *
- * Allocates a mac descriptor and resets its value.
- * This function is not used directly, instead @ref ixEthDBAllocMacDescriptor()
- * is used, which keeps track of the pointer reference count.
- *
- * @see ixEthDBAllocMacDescriptor()
- *
- * @warning this function is not used directly by any other function
- * apart from ixEthDBAllocMacDescriptor()
- *
- * @return the allocated mac descriptor or NULL if the pool is empty
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-MacDescriptor* ixEthDBPoolAllocMacDescriptor(void)
-{
- MacDescriptor *allocatedDescriptor = NULL;
-
- if (macPool != NULL)
- {
- LOCK_MAC_POOL;
-
- allocatedDescriptor = macPool;
- macPool = macPool->nextFree;
-
- UNLOCK_MAC_POOL;
-
- memset(allocatedDescriptor, 0, sizeof(MacDescriptor));
- }
-
- return allocatedDescriptor;
-}
-
-/**
- * @brief allocates and initializes a mac descriptor smart pointer
- *
- * Uses @ref ixEthDBPoolAllocMacDescriptor() to allocate a mac descriptor
- * from the pool and initializes its reference count.
- *
- * @see ixEthDBPoolAllocMacDescriptor()
- *
- * @return the allocated mac descriptor or NULL if the pool is empty
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-MacDescriptor* ixEthDBAllocMacDescriptor(void)
-{
- MacDescriptor *allocatedDescriptor = ixEthDBPoolAllocMacDescriptor();
-
- if (allocatedDescriptor != NULL)
- {
- LOCK_MAC_POOL;
-
- allocatedDescriptor->refCount++;
-
- UNLOCK_MAC_POOL;
- }
-
- return allocatedDescriptor;
-}
-
-/**
- * @brief frees a mac descriptor back into the pool
- *
- * @param macDescriptor mac descriptor to be freed
- *
- * @warning this function is not to be called by anyone but
- * ixEthDBFreeMacDescriptor()
- *
- * @see ixEthDBFreeMacDescriptor()
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBPoolFreeMacDescriptor(MacDescriptor *macDescriptor)
-{
- LOCK_MAC_POOL;
-
- macDescriptor->nextFree = macPool;
- macPool = macDescriptor;
-
- UNLOCK_MAC_POOL;
-}
-
-/**
- * @brief frees or reduces the usage count of a mac descriptor smart pointer
- *
- * If the reference count reaches 0 (structure is no longer used anywhere)
- * then the descriptor is freed back into the pool using ixEthDBPoolFreeMacDescriptor().
- *
- * @see ixEthDBPoolFreeMacDescriptor()
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBFreeMacDescriptor(MacDescriptor *macDescriptor)
-{
- if (macDescriptor != NULL)
- {
- LOCK_MAC_POOL;
-
- if (macDescriptor->refCount > 0)
- {
- macDescriptor->refCount--;
-
- if (macDescriptor->refCount == 0)
- {
- UNLOCK_MAC_POOL;
-
- ixEthDBPoolFreeMacDescriptor(macDescriptor);
- }
- else
- {
- UNLOCK_MAC_POOL;
- }
- }
- else
- {
- UNLOCK_MAC_POOL;
- }
- }
-}
-
-/**
- * @brief clones a mac descriptor smart pointer
- *
- * @param macDescriptor mac descriptor to clone
- *
- * Increments the usage count of the smart pointer
- *
- * @returns the cloned smart pointer
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-MacDescriptor* ixEthDBCloneMacDescriptor(MacDescriptor *macDescriptor)
-{
- LOCK_MAC_POOL;
-
- if (macDescriptor->refCount == 0)
- {
- UNLOCK_MAC_POOL;
-
- return NULL;
- }
-
- macDescriptor->refCount++;
-
- UNLOCK_MAC_POOL;
-
- return macDescriptor;
-}
-
-/**
- * @brief allocates a mac tree node from the pool
- *
- * Allocates and initializes a mac tree node from the pool.
- *
- * @return the allocated mac tree node or NULL if the pool is empty
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-MacTreeNode* ixEthDBAllocMacTreeNode(void)
-{
- MacTreeNode *allocatedNode = NULL;
-
- if (treePool != NULL)
- {
- LOCK_TREE_POOL;
-
- allocatedNode = treePool;
- treePool = treePool->nextFree;
-
- UNLOCK_TREE_POOL;
-
- memset(allocatedNode, 0, sizeof(MacTreeNode));
- }
-
- return allocatedNode;
-}
-
-/**
- * @brief frees a mac tree node back into the pool
- *
- * @param macNode mac tree node to be freed
- *
- * @warning not to be used except from ixEthDBFreeMacTreeNode().
- *
- * @see ixEthDBFreeMacTreeNode()
- *
- * @internal
- */
-void ixEthDBPoolFreeMacTreeNode(MacTreeNode *macNode)
-{
- if (macNode != NULL)
- {
- LOCK_TREE_POOL;
-
- macNode->nextFree = treePool;
- treePool = macNode;
-
- UNLOCK_TREE_POOL;
- }
-}
-
-/**
- * @brief frees or reduces the usage count of a mac tree node smart pointer
- *
- * @param macNode mac tree node to free
- *
- * Reduces the usage count of the given mac node. If the usage count
- * reaches 0 the node is freed back into the pool using ixEthDBPoolFreeMacTreeNode()
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBFreeMacTreeNode(MacTreeNode *macNode)
-{
- if (macNode->descriptor != NULL)
- {
- ixEthDBFreeMacDescriptor(macNode->descriptor);
- }
-
- if (macNode->left != NULL)
- {
- ixEthDBFreeMacTreeNode(macNode->left);
- }
-
- if (macNode->right != NULL)
- {
- ixEthDBFreeMacTreeNode(macNode->right);
- }
-
- ixEthDBPoolFreeMacTreeNode(macNode);
-}
-
-/**
- * @brief clones a mac tree node
- *
- * @param macNode mac tree node to be cloned
- *
- * Increments the usage count of the node, <i>its associated descriptor
- * and <b>recursively</b> of all its child nodes</i>.
- *
- * @warning this function is recursive and clones whole trees/subtrees, use only for
- * root nodes
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-MacTreeNode* ixEthDBCloneMacTreeNode(MacTreeNode *macNode)
-{
- if (macNode != NULL)
- {
- MacTreeNode *clonedMacNode = ixEthDBAllocMacTreeNode();
-
- if (clonedMacNode != NULL)
- {
- if (macNode->right != NULL)
- {
- clonedMacNode->right = ixEthDBCloneMacTreeNode(macNode->right);
- }
-
- if (macNode->left != NULL)
- {
- clonedMacNode->left = ixEthDBCloneMacTreeNode(macNode->left);
- }
-
- if (macNode->descriptor != NULL)
- {
- clonedMacNode->descriptor = ixEthDBCloneMacDescriptor(macNode->descriptor);
- }
- }
-
- return clonedMacNode;
- }
- else
- {
- return NULL;
- }
-}
-
-#ifndef NDEBUG
-/* Debug statistical functions for memory usage */
-
-extern HashTable dbHashtable;
-int ixEthDBNumHashElements(void);
-
-int ixEthDBNumHashElements(void)
-{
- UINT32 bucketIndex;
- int numElements = 0;
- HashTable *hashTable = &dbHashtable;
-
- for (bucketIndex = 0 ; bucketIndex < hashTable->numBuckets ; bucketIndex++)
- {
- if (hashTable->hashBuckets[bucketIndex] != NULL)
- {
- HashNode *node = hashTable->hashBuckets[bucketIndex];
-
- while (node != NULL)
- {
- numElements++;
-
- node = node->next;
- }
- }
- }
-
- return numElements;
-}
-
-UINT32 ixEthDBSearchTreeUsageGet(MacTreeNode *tree)
-{
- if (tree == NULL)
- {
- return 0;
- }
- else
- {
- return 1 /* this node */ + ixEthDBSearchTreeUsageGet(tree->left) + ixEthDBSearchTreeUsageGet(tree->right);
- }
-}
-
-int ixEthDBShowMemoryStatus(void)
-{
- MacDescriptor *mac;
- MacTreeNode *tree;
- HashNode *node;
-
- int macCounter = 0;
- int treeCounter = 0;
- int nodeCounter = 0;
-
- int totalTreeUsage = 0;
- int totalDescriptorUsage = 0;
- int totalCloneDescriptorUsage = 0;
- int totalNodeUsage = 0;
-
- UINT32 portIndex;
-
- LOCK_NODE_POOL;
- LOCK_MAC_POOL;
- LOCK_TREE_POOL;
-
- mac = macPool;
- tree = treePool;
- node = nodePool;
-
- while (mac != NULL)
- {
- macCounter++;
-
- mac = mac->nextFree;
-
- if (macCounter > MAC_POOL_SIZE)
- {
- break;
- }
- }
-
- while (tree != NULL)
- {
- treeCounter++;
-
- tree = tree->nextFree;
-
- if (treeCounter > TREE_POOL_SIZE)
- {
- break;
- }
- }
-
- while (node != NULL)
- {
- nodeCounter++;
-
- node = node->nextFree;
-
- if (nodeCounter > NODE_POOL_SIZE)
- {
- break;
- }
- }
-
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- int treeUsage = ixEthDBSearchTreeUsageGet(ixEthDBPortInfo[portIndex].updateMethod.searchTree);
-
- totalTreeUsage += treeUsage;
- totalCloneDescriptorUsage += treeUsage; /* each tree node contains a descriptor */
- }
-
- totalNodeUsage = ixEthDBNumHashElements();
- totalDescriptorUsage += totalNodeUsage; /* each hash table entry contains a descriptor */
-
- UNLOCK_NODE_POOL;
- UNLOCK_MAC_POOL;
- UNLOCK_TREE_POOL;
-
- printf("Ethernet database memory usage stats:\n\n");
-
- if (macCounter <= MAC_POOL_SIZE)
- {
- printf("\tMAC descriptor pool : %d free out of %d entries (%d%%)\n", macCounter, MAC_POOL_SIZE, macCounter * 100 / MAC_POOL_SIZE);
- }
- else
- {
- printf("\tMAC descriptor pool : invalid state (ring within the pool), normally %d entries\n", MAC_POOL_SIZE);
- }
-
- if (treeCounter <= TREE_POOL_SIZE)
- {
- printf("\tTree node pool : %d free out of %d entries (%d%%)\n", treeCounter, TREE_POOL_SIZE, treeCounter * 100 / TREE_POOL_SIZE);
- }
- else
- {
- printf("\tTREE descriptor pool : invalid state (ring within the pool), normally %d entries\n", TREE_POOL_SIZE);
- }
-
- if (nodeCounter <= NODE_POOL_SIZE)
- {
- printf("\tHash node pool : %d free out of %d entries (%d%%)\n", nodeCounter, NODE_POOL_SIZE, nodeCounter * 100 / NODE_POOL_SIZE);
- }
- else
- {
- printf("\tNODE descriptor pool : invalid state (ring within the pool), normally %d entries\n", NODE_POOL_SIZE);
- }
-
- printf("\n");
- printf("\tMAC descriptor usage : %d entries, %d cloned\n", totalDescriptorUsage, totalCloneDescriptorUsage);
- printf("\tTree node usage : %d entries\n", totalTreeUsage);
- printf("\tHash node usage : %d entries\n", totalNodeUsage);
- printf("\n");
-
- /* search for duplicate nodes in the mac pool */
- {
- MacDescriptor *reference = macPool;
-
- while (reference != NULL)
- {
- MacDescriptor *comparison = reference->nextFree;
-
- while (comparison != NULL)
- {
- if (reference == comparison)
- {
- printf("Warning: reached a duplicate (%p), invalid MAC pool state\n", reference);
-
- return 1;
- }
-
- comparison = comparison->nextFree;
- }
-
- reference = reference->nextFree;
- }
- }
-
- printf("No duplicates found in the MAC pool (sanity check ok)\n");
-
- return 0;
-}
-
-#endif /* NDEBUG */
-
-/**
- * @} EthMemoryManagement
- */
+++ /dev/null
-/**
- * @file IxEthDBDBNPEAdaptor.c
- *
- * @brief Routines that read and write learning/search trees in NPE-specific format
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-#include "IxEthDBLog_p.h"
-
-/* forward prototype declarations */
-IX_ETH_DB_PUBLIC void ixEthDBELTShow(IxEthDBPortId portID);
-IX_ETH_DB_PUBLIC void ixEthDBShowNpeMsgHistory(void);
-
-/* data */
-UINT8* ixEthDBNPEUpdateArea[IX_ETH_DB_NUMBER_OF_PORTS];
-UINT32 dumpEltSize;
-
-/* private data */
-IX_ETH_DB_PRIVATE IxEthDBNoteWriteFn ixEthDBNPENodeWrite[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1];
-
-#define IX_ETH_DB_MAX_DELTA_ZONES (6) /* at most 6 EP Delta zones, according to NPE FS */
-IX_ETH_DB_PRIVATE UINT32 ixEthDBEPDeltaOffset[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1][IX_ETH_DB_MAX_DELTA_ZONES];
-IX_ETH_DB_PRIVATE UINT32 ixEthDBEPDelta[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1][IX_ETH_DB_MAX_DELTA_ZONES];
-
-/**
- * @brief allocates non-cached or contiguous NPE tree update areas for all the ports
- *
- * This function is called only once at initialization time from
- * @ref ixEthDBInit().
- *
- * @warning do not call manually
- *
- * @see ixEthDBInit()
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNPEUpdateAreasInit(void)
-{
- UINT32 portIndex;
- PortUpdateMethod *update;
-
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- update = &ixEthDBPortInfo[portIndex].updateMethod;
-
- if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE)
- {
- update->npeUpdateZone = IX_OSAL_CACHE_DMA_MALLOC(FULL_ELT_BYTE_SIZE);
- update->npeGwUpdateZone = IX_OSAL_CACHE_DMA_MALLOC(FULL_GW_BYTE_SIZE);
- update->vlanUpdateZone = IX_OSAL_CACHE_DMA_MALLOC(FULL_VLAN_BYTE_SIZE);
-
- if (update->npeUpdateZone == NULL
- || update->npeGwUpdateZone == NULL
- || update->vlanUpdateZone == NULL)
- {
- ERROR_LOG("Fatal error: IX_ACC_DRV_DMA_MALLOC() returned NULL, no NPE update zones available\n");
- }
- else
- {
- memset(update->npeUpdateZone, 0, FULL_ELT_BYTE_SIZE);
- memset(update->npeGwUpdateZone, 0, FULL_GW_BYTE_SIZE);
- memset(update->vlanUpdateZone, 0, FULL_VLAN_BYTE_SIZE);
- }
- }
- else
- {
- /* unused */
- update->npeUpdateZone = NULL;
- update->npeGwUpdateZone = NULL;
- update->vlanUpdateZone = NULL;
- }
- }
-}
-
-/**
- * @brief deallocates the NPE update areas for all the ports
- *
- * This function is called at component de-initialization time
- * by @ref ixEthDBUnload().
- *
- * @warning do not call manually
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNPEUpdateAreasUnload(void)
-{
- UINT32 portIndex;
-
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE)
- {
- IX_OSAL_CACHE_DMA_FREE(ixEthDBPortInfo[portIndex].updateMethod.npeUpdateZone);
- IX_OSAL_CACHE_DMA_FREE(ixEthDBPortInfo[portIndex].updateMethod.npeGwUpdateZone);
- IX_OSAL_CACHE_DMA_FREE(ixEthDBPortInfo[portIndex].updateMethod.vlanUpdateZone);
- }
- }
-}
-
-/**
- * @brief general-purpose NPE callback function
- *
- * @param npeID NPE ID
- * @param msg NPE message
- *
- * This function will unblock the caller by unlocking
- * the npeAckLock mutex defined for each NPE port
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNpeMsgAck(IxNpeMhNpeId npeID, IxNpeMhMessage msg)
-{
- IxEthDBPortId portID = IX_ETH_DB_NPE_TO_PORT_ID(npeID);
- PortInfo *portInfo;
-
- if (portID >= IX_ETH_DB_NUMBER_OF_PORTS)
- {
- /* invalid port */
- return;
- }
-
- if (ixEthDBPortDefinitions[portID].type != IX_ETH_NPE)
- {
- /* not an NPE */
- return;
- }
-
- portInfo = &ixEthDBPortInfo[portID];
-
- ixOsalMutexUnlock(&portInfo->npeAckLock);
-}
-
-/**
- * @brief synchronizes the database with tree
- *
- * @param portID port ID of the NPE whose tree is to be scanned
- * @param eltBaseAddress memory base address of the NPE serialized tree
- * @param eltSize size in bytes of the NPE serialized tree
- *
- * Scans the NPE learning tree and resets the age of active database records.
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNPESyncScan(IxEthDBPortId portID, void *eltBaseAddress, UINT32 eltSize)
-{
- UINT32 eltEntryOffset;
- UINT32 entryPortID;
-
- /* invalidate cache */
- IX_OSAL_CACHE_INVALIDATE(eltBaseAddress, eltSize);
-
- for (eltEntryOffset = ELT_ROOT_OFFSET ; eltEntryOffset < eltSize ; eltEntryOffset += ELT_ENTRY_SIZE)
- {
- /* (eltBaseAddress + eltEntryOffset) points to a valid NPE tree node
- *
- * the format of the node is MAC[6 bytes]:PortID[1 byte]:Reserved[6 bits]:Active[1 bit]:Valid[1 bit]
- * therefore we can just use the pointer for database searches as only the first 6 bytes are checked
- */
- void *eltNodeAddress = (void *) ((UINT32) eltBaseAddress + eltEntryOffset);
-
- /* debug */
- IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) checking node at offset %d...\n", eltEntryOffset / ELT_ENTRY_SIZE);
-
- if (IX_EDB_NPE_NODE_VALID(eltNodeAddress) != TRUE)
- {
- IX_ETH_DB_NPE_VERBOSE_TRACE("\t... node is empty\n");
- }
- else if (eltEntryOffset == ELT_ROOT_OFFSET)
- {
- IX_ETH_DB_NPE_VERBOSE_TRACE("\t... node is root\n");
- }
-
- if (IX_EDB_NPE_NODE_VALID(eltNodeAddress))
- {
- entryPortID = IX_ETH_DB_NPE_LOGICAL_ID_TO_PORT_ID(IX_EDB_NPE_NODE_PORT_ID(eltNodeAddress));
-
- /* check only active entries belonging to this port */
- if (ixEthDBPortInfo[portID].agingEnabled && IX_EDB_NPE_NODE_ACTIVE(eltNodeAddress) && (portID == entryPortID)
- && ((ixEthDBPortDefinitions[portID].capabilities & IX_ETH_ENTRY_AGING) == 0))
- {
- /* search record */
- HashNode *node = ixEthDBSearch((IxEthDBMacAddr *) eltNodeAddress, IX_ETH_DB_ALL_FILTERING_RECORDS);
-
- /* safety check, maybe user deleted record right before sync? */
- if (node != NULL)
- {
- /* found record */
- MacDescriptor *descriptor = (MacDescriptor *) node->data;
-
- IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) synced entry [%s] already in the database, updating fields\n", mac2string(eltNodeAddress));
-
- /* reset age - set to -1 so that maintenance will restore it to 0 (or more) when incrementing */
- if (!descriptor->recordData.filteringData.staticEntry)
- {
- if (descriptor->type == IX_ETH_DB_FILTERING_RECORD)
- {
- descriptor->recordData.filteringData.age = AGE_RESET;
- }
- else if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD)
- {
- descriptor->recordData.filteringVlanData.age = AGE_RESET;
- }
- }
-
- /* end transaction */
- ixEthDBReleaseHashNode(node);
- }
- }
- else
- {
- IX_ETH_DB_NPE_VERBOSE_TRACE("\t... found portID %d, we check only port %d\n", entryPortID, portID);
- }
- }
- }
-}
-
-/**
- * @brief writes a search tree in NPE format
- *
- * @param type type of records to be written into the NPE update zone
- * @param totalSize maximum size of the linearized tree
- * @param baseAddress memory base address where to write the NPE tree into
- * @param tree search tree to write in NPE format
- * @param blocks number of written 64-byte blocks
- * @param startIndex optimal binary search start index
- *
- * Serializes the given tree in NPE linear format
- *
- * @return none
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNPETreeWrite(IxEthDBRecordType type, UINT32 totalSize, void *baseAddress, MacTreeNode *tree, UINT32 *epDelta, UINT32 *blocks)
-{
- MacTreeNodeStack *stack;
- UINT32 maxOffset = 0;
- UINT32 emptyOffset;
-
- stack = ixOsalCacheDmaMalloc(sizeof (MacTreeNodeStack));
-
- if (stack == NULL)
- {
- ERROR_LOG("DB: (NPEAdaptor) failed to allocate the node stack for learning tree linearization, out of memory?\n");
- return;
- }
-
- /* zero out empty root */
- memset(baseAddress, 0, ELT_ENTRY_SIZE);
-
- NODE_STACK_INIT(stack);
-
- if (tree != NULL)
- {
- /* push tree root at offset 1 */
- NODE_STACK_PUSH(stack, tree, 1);
-
- maxOffset = 1;
- }
-
- while (NODE_STACK_NONEMPTY(stack))
- {
- MacTreeNode *node;
- UINT32 offset;
-
- NODE_STACK_POP(stack, node, offset);
-
- /* update maximum offset */
- if (offset > maxOffset)
- {
- maxOffset = offset;
- }
-
- IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) writing MAC [%s] at offset %d\n", mac2string(node->descriptor->macAddress), offset);
-
- /* add node to NPE ELT at position indicated by offset */
- if (offset < MAX_ELT_SIZE)
- {
- ixEthDBNPENodeWrite[type]((void *) (((UINT32) baseAddress) + offset * ELT_ENTRY_SIZE), node);
- }
-
- if (node->left != NULL)
- {
- NODE_STACK_PUSH(stack, node->left, LEFT_CHILD_OFFSET(offset));
- }
- else
- {
- /* ensure this entry is zeroed */
- memset((void *) ((UINT32) baseAddress + LEFT_CHILD_OFFSET(offset) * ELT_ENTRY_SIZE), 0, ELT_ENTRY_SIZE);
- }
-
- if (node->right != NULL)
- {
- NODE_STACK_PUSH(stack, node->right, RIGHT_CHILD_OFFSET(offset));
- }
- else
- {
- /* ensure this entry is zeroed */
- memset((void *) ((UINT32) baseAddress + RIGHT_CHILD_OFFSET(offset) * ELT_ENTRY_SIZE), 0, ELT_ENTRY_SIZE);
- }
- }
-
- emptyOffset = maxOffset + 1;
-
- /* zero out rest of the tree */
- IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Emptying tree from offset %d, address 0x%08X, %d bytes\n",
- emptyOffset, ((UINT32) baseAddress) + emptyOffset * ELT_ENTRY_SIZE, totalSize - (emptyOffset * ELT_ENTRY_SIZE));
-
- if (emptyOffset < MAX_ELT_SIZE - 1)
- {
- memset((void *) (((UINT32) baseAddress) + (emptyOffset * ELT_ENTRY_SIZE)), 0, totalSize - (emptyOffset * ELT_ENTRY_SIZE));
- }
-
- /* flush cache */
- IX_OSAL_CACHE_FLUSH(baseAddress, totalSize);
-
- /* debug */
- IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Ethernet learning/filtering tree XScale wrote at address 0x%08X (max %d bytes):\n\n",
- (UINT32) baseAddress, FULL_ELT_BYTE_SIZE);
-
- IX_ETH_DB_NPE_DUMP_ELT(baseAddress, FULL_ELT_BYTE_SIZE);
-
- /* compute number of 64-byte blocks */
- if (blocks != NULL)
- {
- *blocks = maxOffset != 0 ? 1 + maxOffset / 8 : 0;
-
- IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Wrote %d 64-byte blocks\n", *blocks);
- }
-
- /* compute epDelta - start index for binary search */
- if (epDelta != NULL)
- {
- UINT32 deltaIndex = 0;
-
- *epDelta = 0;
-
- for (; deltaIndex < IX_ETH_DB_MAX_DELTA_ZONES ; deltaIndex ++)
- {
- if (ixEthDBEPDeltaOffset[type][deltaIndex] >= maxOffset)
- {
- *epDelta = ixEthDBEPDelta[type][deltaIndex];
- break;
- }
- }
-
- IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Computed epDelta %d (based on maxOffset %d)\n", *epDelta, maxOffset);
- }
-
- ixOsalCacheDmaFree(stack);
-}
-
-/**
- * @brief implements a dummy node serialization function
- *
- * @param address address of where the node is to be serialized (unused)
- * @param node tree node to be serialized (unused)
- *
- * This function is registered for safety reasons and should
- * never be called. It will display an error message if this
- * function is called.
- *
- * @return none
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBNullSerialize(void *address, MacTreeNode *node)
-{
- IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Warning, the NullSerialize function was called, wrong record type?\n");
-}
-
-/**
- * @brief writes a filtering entry in NPE linear format
- *
- * @param address memory address to write node to
- * @param node node to be written
- *
- * Used by @ref ixEthDBNPETreeWrite to liniarize a search tree
- * in NPE-readable format.
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBNPELearningNodeWrite(void *address, MacTreeNode *node)
-{
- /* copy mac address */
- memcpy(address, node->descriptor->macAddress, IX_IEEE803_MAC_ADDRESS_SIZE);
-
- /* copy port ID */
- NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_PORT_ID_OFFSET) = IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(node->descriptor->portID);
-
- /* copy flags (valid and not active, as the NPE sets it to active) and clear reserved section (bits 2-7) */
- NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_FLAGS_OFFSET) = (UINT8) IX_EDB_FLAGS_INACTIVE_VALID;
-
- IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) writing ELT node 0x%08x:0x%08x\n", * (UINT32 *) address, * (((UINT32 *) (address)) + 1));
-}
-
-/**
- * @brief writes a WiFi header conversion record in
- * NPE linear format
- *
- * @param address memory address to write node to
- * @param node node to be written
- *
- * Used by @ref ixEthDBNPETreeWrite to liniarize a search tree
- * in NPE-readable format.
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBNPEWiFiNodeWrite(void *address, MacTreeNode *node)
-{
- /* copy mac address */
- memcpy(address, node->descriptor->macAddress, IX_IEEE803_MAC_ADDRESS_SIZE);
-
- /* copy index */
- NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_WIFI_INDEX_OFFSET) = node->descriptor->recordData.wifiData.gwAddressIndex;
-
- /* copy flags (type and valid) */
- NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_WIFI_FLAGS_OFFSET) = node->descriptor->recordData.wifiData.type << 1 | IX_EDB_FLAGS_VALID;
-}
-
-/**
- * @brief writes a WiFi gateway header conversion record in
- * NPE linear format
- *
- * @param address memory address to write node to
- * @param node node to be written
- *
- * Used by @ref ixEthDBNPETreeWrite to liniarize a search tree
- * in NPE-readable format.
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNPEGatewayNodeWrite(void *address, MacTreeNode *node)
-{
- /* copy mac address */
- memcpy(address, node->descriptor->recordData.wifiData.gwMacAddress, IX_IEEE803_MAC_ADDRESS_SIZE);
-
- /* set reserved field, two bytes */
- NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_FW_RESERVED_OFFSET) = 0;
- NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_FW_RESERVED_OFFSET + 1) = 0;
-}
-
-/**
- * @brief writes a firewall record in
- * NPE linear format
- *
- * @param address memory address to write node to
- * @param node node to be written
- *
- * Used by @ref ixEthDBNPETreeWrite to liniarize a search tree
- * in NPE-readable format.
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBNPEFirewallNodeWrite(void *address, MacTreeNode *node)
-{
- /* set reserved field */
- NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_FW_RESERVED_OFFSET) = 0;
-
- /* set flags */
- NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_FW_FLAGS_OFFSET) = IX_EDB_FLAGS_VALID;
-
- /* copy mac address */
- memcpy((void *) ((UINT32) address + IX_EDB_NPE_NODE_FW_ADDR_OFFSET), node->descriptor->macAddress, IX_IEEE803_MAC_ADDRESS_SIZE);
-}
-
-/**
- * @brief registers the NPE serialization methods
- *
- * This functions registers NPE serialization methods
- * for writing the following types of records in NPE
- * readable linear format:
- * - filtering records
- * - WiFi header conversion records
- * - WiFi gateway header conversion records
- * - firewall records
- *
- * Note that this function should be called by the
- * component initialization function.
- *
- * @return number of registered record types
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-UINT32 ixEthDBRecordSerializeMethodsRegister()
-{
- int i;
-
- /* safety - register a blank method for everybody first */
- for ( i = 0 ; i < IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1 ; i++)
- {
- ixEthDBNPENodeWrite[i] = ixEthDBNullSerialize;
- }
-
- /* register real methods */
- ixEthDBNPENodeWrite[IX_ETH_DB_FILTERING_RECORD] = ixEthDBNPELearningNodeWrite;
- ixEthDBNPENodeWrite[IX_ETH_DB_FILTERING_VLAN_RECORD] = ixEthDBNPELearningNodeWrite;
- ixEthDBNPENodeWrite[IX_ETH_DB_WIFI_RECORD] = ixEthDBNPEWiFiNodeWrite;
- ixEthDBNPENodeWrite[IX_ETH_DB_FIREWALL_RECORD] = ixEthDBNPEFirewallNodeWrite;
- ixEthDBNPENodeWrite[IX_ETH_DB_GATEWAY_RECORD] = ixEthDBNPEGatewayNodeWrite;
-
- /* EP Delta arrays */
- memset(ixEthDBEPDeltaOffset, 0, sizeof (ixEthDBEPDeltaOffset));
- memset(ixEthDBEPDelta, 0, sizeof (ixEthDBEPDelta));
-
- /* filtering records */
- ixEthDBEPDeltaOffset[IX_ETH_DB_FILTERING_RECORD][0] = 1;
- ixEthDBEPDelta[IX_ETH_DB_FILTERING_RECORD][0] = 0;
-
- ixEthDBEPDeltaOffset[IX_ETH_DB_FILTERING_RECORD][1] = 3;
- ixEthDBEPDelta[IX_ETH_DB_FILTERING_RECORD][1] = 7;
-
- ixEthDBEPDeltaOffset[IX_ETH_DB_FILTERING_RECORD][2] = 511;
- ixEthDBEPDelta[IX_ETH_DB_FILTERING_RECORD][2] = 14;
-
- /* wifi records */
- ixEthDBEPDeltaOffset[IX_ETH_DB_WIFI_RECORD][0] = 1;
- ixEthDBEPDelta[IX_ETH_DB_WIFI_RECORD][0] = 0;
-
- ixEthDBEPDeltaOffset[IX_ETH_DB_WIFI_RECORD][1] = 3;
- ixEthDBEPDelta[IX_ETH_DB_WIFI_RECORD][1] = 7;
-
- ixEthDBEPDeltaOffset[IX_ETH_DB_WIFI_RECORD][2] = 511;
- ixEthDBEPDelta[IX_ETH_DB_WIFI_RECORD][2] = 14;
-
- /* firewall records */
- ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][0] = 0;
- ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][0] = 0;
-
- ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][1] = 1;
- ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][1] = 5;
-
- ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][2] = 3;
- ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][2] = 13;
-
- ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][3] = 7;
- ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][3] = 21;
-
- ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][4] = 15;
- ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][4] = 29;
-
- ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][5] = 31;
- ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][5] = 37;
-
- return 5; /* 5 methods registered */
-}
-
-#ifndef IX_NDEBUG
-
-IX_ETH_DB_PUBLIC UINT32 npeMsgHistory[IX_ETH_DB_NPE_MSG_HISTORY_DEPTH][2];
-IX_ETH_DB_PUBLIC UINT32 npeMsgHistoryLen = 0;
-
-/**
- * When compiled in DEBUG mode, this function can be used to display
- * the history of messages sent to the NPEs (up to 100).
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBShowNpeMsgHistory()
-{
- UINT32 i = 0;
- UINT32 base, len;
-
- if (npeMsgHistoryLen <= IX_ETH_DB_NPE_MSG_HISTORY_DEPTH)
- {
- base = 0;
- len = npeMsgHistoryLen;
- }
- else
- {
- base = npeMsgHistoryLen % IX_ETH_DB_NPE_MSG_HISTORY_DEPTH;
- len = IX_ETH_DB_NPE_MSG_HISTORY_DEPTH;
- }
-
- printf("NPE message history [last %d messages, from least to most recent]:\n", len);
-
- for (; i < len ; i++)
- {
- UINT32 pos = (base + i) % IX_ETH_DB_NPE_MSG_HISTORY_DEPTH;
- printf("msg[%d]: 0x%08x:0x%08x\n", i, npeMsgHistory[pos][0], npeMsgHistory[pos][1]);
- }
-}
-
-IX_ETH_DB_PUBLIC
-void ixEthDBELTShow(IxEthDBPortId portID)
-{
- IxNpeMhMessage message;
- IX_STATUS result;
-
- /* send EDB_GetMACAddressDatabase message */
- FILL_GETMACADDRESSDATABASE(message,
- 0 /* reserved */,
- IX_OSAL_MMU_VIRT_TO_PHYS(ixEthDBPortInfo[portID].updateMethod.npeUpdateZone));
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- if (result == IX_SUCCESS)
- {
- /* analyze NPE copy */
- UINT32 eltEntryOffset;
- UINT32 entryPortID;
-
- UINT32 eltBaseAddress = (UINT32) ixEthDBPortInfo[portID].updateMethod.npeUpdateZone;
- UINT32 eltSize = FULL_ELT_BYTE_SIZE;
-
- /* invalidate cache */
- IX_OSAL_CACHE_INVALIDATE((void *) eltBaseAddress, eltSize);
-
- printf("Listing records in main learning tree for port %d\n", portID);
-
- for (eltEntryOffset = ELT_ROOT_OFFSET ; eltEntryOffset < eltSize ; eltEntryOffset += ELT_ENTRY_SIZE)
- {
- /* (eltBaseAddress + eltEntryOffset) points to a valid NPE tree node
- *
- * the format of the node is MAC[6 bytes]:PortID[1 byte]:Reserved[6 bits]:Active[1 bit]:Valid[1 bit]
- * therefore we can just use the pointer for database searches as only the first 6 bytes are checked
- */
- void *eltNodeAddress = (void *) ((UINT32) eltBaseAddress + eltEntryOffset);
-
- if (IX_EDB_NPE_NODE_VALID(eltNodeAddress))
- {
- HashNode *node;
-
- entryPortID = IX_ETH_DB_NPE_LOGICAL_ID_TO_PORT_ID(IX_EDB_NPE_NODE_PORT_ID(eltNodeAddress));
-
- /* search record */
- node = ixEthDBSearch((IxEthDBMacAddr *) eltNodeAddress, IX_ETH_DB_ALL_RECORD_TYPES);
-
- printf("%s - port %d - %s ", mac2string((unsigned char *) eltNodeAddress), entryPortID,
- IX_EDB_NPE_NODE_ACTIVE(eltNodeAddress) ? "active" : "inactive");
-
- /* safety check, maybe user deleted record right before sync? */
- if (node != NULL)
- {
- /* found record */
- MacDescriptor *descriptor = (MacDescriptor *) node->data;
-
- printf("- %s ",
- descriptor->type == IX_ETH_DB_FILTERING_RECORD ? "filtering" :
- descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD ? "vlan" :
- descriptor->type == IX_ETH_DB_WIFI_RECORD ? "wifi" : "other (check main DB)");
-
- if (descriptor->type == IX_ETH_DB_FILTERING_RECORD) printf("- age %d - %s ",
- descriptor->recordData.filteringData.age,
- descriptor->recordData.filteringData.staticEntry ? "static" : "dynamic");
-
- if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD) printf("- age %d - %s - tci %d ",
- descriptor->recordData.filteringVlanData.age,
- descriptor->recordData.filteringVlanData.staticEntry ? "static" : "dynamic",
- descriptor->recordData.filteringVlanData.ieee802_1qTag);
-
- /* end transaction */
- ixEthDBReleaseHashNode(node);
- }
- else
- {
- printf("- not synced");
- }
-
- printf("\n");
- }
- }
- }
- else
- {
- ixOsalLog(IX_OSAL_LOG_LVL_FATAL, IX_OSAL_LOG_DEV_STDOUT,
- "EthDB: (ShowELT) Could not complete action (communication failure)\n",
- portID, 0, 0, 0, 0, 0);
- }
-}
-
-#endif
+++ /dev/null
-/**
- * @file IxEthDBDBPortUpdate.c
- *
- * @brief Implementation of dependency and port update handling
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-
-/* forward prototype declarations */
-IX_ETH_DB_PRIVATE MacTreeNode* ixEthDBTreeInsert(MacTreeNode *searchTree, MacDescriptor *descriptor);
-IX_ETH_DB_PRIVATE void ixEthDBCreateTrees(IxEthDBPortMap updatePorts);
-IX_ETH_DB_PRIVATE MacTreeNode* ixEthDBTreeRebalance(MacTreeNode *searchTree);
-IX_ETH_DB_PRIVATE void ixEthDBRebalanceTreeToVine(MacTreeNode *root, UINT32 *size);
-IX_ETH_DB_PRIVATE void ixEthDBRebalanceVineToTree(MacTreeNode *root, UINT32 size);
-IX_ETH_DB_PRIVATE void ixEthDBRebalanceCompression(MacTreeNode *root, UINT32 count);
-IX_ETH_DB_PRIVATE UINT32 ixEthDBRebalanceLog2Floor(UINT32 x);
-
-extern HashTable dbHashtable;
-
-/**
- * @brief register types requiring automatic updates
- *
- * @param typeArray array indexed on record types, each
- * element indicating whether the record type requires an
- * automatic update (TRUE) or not (FALSE)
- *
- * Automatic updates are done for registered record types
- * upon adding, updating (that is, updating the record portID)
- * and removing records. Whenever an automatic update is triggered
- * the appropriate ports will be provided with new database
- * information.
- *
- * It is assumed that the typeArray parameter is allocated large
- * enough to hold all the user defined types. Also, the type
- * array should be initialized to FALSE as this function only
- * caters for types which do require automatic updates.
- *
- * Note that this function should be called by the component
- * initialization function.
- *
- * @return number of record types registered for automatic
- * updates
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-UINT32 ixEthDBUpdateTypeRegister(BOOL *typeArray)
-{
- typeArray[IX_ETH_DB_FILTERING_RECORD] = TRUE;
- typeArray[IX_ETH_DB_FILTERING_VLAN_RECORD] = TRUE;
-
- return 2;
-}
-
-/**
- * @brief computes dependencies and triggers port learning tree updates
- *
- * @param triggerPorts port map consisting in the ports which triggered the update
- *
- * This function browses through all the ports and determines how to waterfall the update
- * event from the trigger ports to all other ports depending on them.
- *
- * Once the list of ports to be updated is determined this function
- * calls @ref ixEthDBCreateTrees.
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBUpdatePortLearningTrees(IxEthDBPortMap triggerPorts)
-{
- IxEthDBPortMap updatePorts;
- UINT32 portIndex;
-
- ixEthDBUpdateLock();
-
- SET_EMPTY_DEPENDENCY_MAP(updatePorts);
-
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- PortInfo *port = &ixEthDBPortInfo[portIndex];
- BOOL mapsCollide;
-
- MAPS_COLLIDE(mapsCollide, triggerPorts, port->dependencyPortMap);
-
- if (mapsCollide /* do triggers influence this port? */
- && !IS_PORT_INCLUDED(portIndex, updatePorts) /* and it's not already in the update list */
- && port->updateMethod.updateEnabled) /* and we're allowed to update it */
- {
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) Adding port %d to update set\n", portIndex);
-
- JOIN_PORT_TO_MAP(updatePorts, portIndex);
- }
- else
- {
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) Didn't add port %d to update set, reasons follow:\n", portIndex);
-
- if (!mapsCollide)
- {
- IX_ETH_DB_UPDATE_TRACE("\tMaps don't collide on port %d\n", portIndex);
- }
-
- if (IS_PORT_INCLUDED(portIndex, updatePorts))
- {
- IX_ETH_DB_UPDATE_TRACE("\tPort %d is already in the update set\n", portIndex);
- }
-
- if (!port->updateMethod.updateEnabled)
- {
- IX_ETH_DB_UPDATE_TRACE("\tPort %d doesn't have updateEnabled set\n", portIndex);
- }
- }
- }
-
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) Updating port set\n");
-
- ixEthDBCreateTrees(updatePorts);
-
- ixEthDBUpdateUnlock();
-}
-
-/**
- * @brief creates learning trees and calls the port update handlers
- *
- * @param updatePorts set of ports in need of learning trees
- *
- * This function determines the optimal method of creating learning
- * trees using a minimal number of database queries, keeping in mind
- * that different ports can either use the same learning trees or they
- * can partially share them. The actual tree building routine is
- * @ref ixEthDBQuery.
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBCreateTrees(IxEthDBPortMap updatePorts)
-{
- UINT32 portIndex;
- BOOL result;
- BOOL portsLeft = TRUE;
-
- while (portsLeft)
- {
- /* get port with minimal dependency map and NULL search tree */
- UINT32 minPortIndex = MAX_PORT_SIZE;
- UINT32 minimalSize = MAX_PORT_SIZE;
-
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- UINT32 size;
- PortInfo *port = &ixEthDBPortInfo[portIndex];
-
- /* generate trees only for ports that need them */
- if (!port->updateMethod.searchTreePendingWrite && IS_PORT_INCLUDED(portIndex, updatePorts))
- {
- GET_MAP_SIZE(port->dependencyPortMap, size);
-
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) Dependency map for port %d: size %d\n",
- portIndex, size);
-
- if (size < minimalSize)
- {
- minPortIndex = portIndex;
- minimalSize = size;
- }
- }
- else
- {
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) Skipped port %d from tree diff (%s)\n", portIndex,
- port->updateMethod.searchTreePendingWrite ? "pending write access" : "ignored by query");
- }
- }
-
- /* if a port was found than minimalSize is not MAX_PORT_SIZE */
- if (minimalSize != MAX_PORT_SIZE)
- {
- /* minPortIndex is the port we seek */
- PortInfo *port = &ixEthDBPortInfo[minPortIndex];
-
- IxEthDBPortMap query;
- MacTreeNode *baseTree;
-
- /* now try to find a port with minimal map difference */
- PortInfo *minimalDiffPort = NULL;
- UINT32 minimalDiff = MAX_PORT_SIZE;
-
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) Minimal size port is %d\n", minPortIndex);
-
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- PortInfo *diffPort = &ixEthDBPortInfo[portIndex];
- BOOL mapIsSubset;
-
- IS_MAP_SUBSET(mapIsSubset, diffPort->dependencyPortMap, port->dependencyPortMap);
-
-
- if (portIndex != minPortIndex
- && diffPort->updateMethod.searchTree != NULL
- && mapIsSubset)
- {
- /* compute size and pick only minimal size difference */
- UINT32 diffPortSize;
- UINT32 sizeDifference;
-
- GET_MAP_SIZE(diffPort->dependencyPortMap, diffPortSize);
-
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) Checking port %d for differences...\n", portIndex);
-
- sizeDifference = minimalSize - diffPortSize;
-
- if (sizeDifference < minimalDiff)
- {
- minimalDiffPort = diffPort;
- minimalDiff = sizeDifference;
-
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) Minimal difference 0x%x was found on port %d\n",
- minimalDiff, portIndex);
- }
- }
- }
-
- /* check if filtering is enabled on this port */
- if ((port->featureStatus & IX_ETH_DB_FILTERING) != 0)
- {
- /* if minimalDiff is not MAX_PORT_SIZE minimalDiffPort points to the most similar port */
- if (minimalDiff != MAX_PORT_SIZE)
- {
- baseTree = ixEthDBCloneMacTreeNode(minimalDiffPort->updateMethod.searchTree);
- DIFF_MAPS(query, port->dependencyPortMap , minimalDiffPort->dependencyPortMap);
-
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) Found minimal diff, extending tree %d on query\n",
- minimalDiffPort->portID);
- }
- else /* .. otherwise no similar port was found, build tree from scratch */
- {
- baseTree = NULL;
-
- COPY_DEPENDENCY_MAP(query, port->dependencyPortMap);
-
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) No similar diff, creating tree from query\n");
- }
-
- IS_EMPTY_DEPENDENCY_MAP(result, query);
-
- if (!result) /* otherwise we don't need anything more on top of the cloned tree */
- {
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) Adding query tree to port %d\n", minPortIndex);
-
- /* build learning tree */
- port->updateMethod.searchTree = ixEthDBQuery(baseTree, query, IX_ETH_DB_ALL_FILTERING_RECORDS, MAX_ELT_SIZE);
- }
- else
- {
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) Query is empty, assuming identical nearest tree\n");
-
- port->updateMethod.searchTree = baseTree;
- }
- }
- else
- {
- /* filtering is not enabled, will download an empty tree */
- if (port->updateMethod.searchTree != NULL)
- {
- ixEthDBFreeMacTreeNode(port->updateMethod.searchTree);
- }
-
- port->updateMethod.searchTree = NULL;
- }
-
- /* mark tree as valid */
- port->updateMethod.searchTreePendingWrite = TRUE;
- }
- else
- {
- portsLeft = FALSE;
-
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) No trees to create this round\n");
- }
- }
-
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- PortInfo *updatePort = &ixEthDBPortInfo[portIndex];
-
- if (updatePort->updateMethod.searchTreePendingWrite)
- {
- IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) Starting procedure to upload new search tree (%snull) into NPE %d\n",
- updatePort->updateMethod.searchTree != NULL ? "not " : "",
- portIndex);
-
- updatePort->updateMethod.updateHandler(portIndex, IX_ETH_DB_FILTERING_RECORD);
- }
- }
-}
-
-/**
- * @brief standard NPE update handler
- *
- * @param portID id of the port to be updated
- * @param type record type to be pushed during this update
- *
- * The NPE update handler manages updating the NPE databases
- * given a certain record type.
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBNPEUpdateHandler(IxEthDBPortId portID, IxEthDBRecordType type)
-{
- UINT32 epDelta, blockCount;
- IxNpeMhMessage message;
- UINT32 treeSize = 0;
- PortInfo *port = &ixEthDBPortInfo[portID];
-
- /* size selection and type check */
- if (type == IX_ETH_DB_FILTERING_RECORD || type == IX_ETH_DB_WIFI_RECORD)
- {
- treeSize = FULL_ELT_BYTE_SIZE;
- }
- else if (type == IX_ETH_DB_FIREWALL_RECORD)
- {
- treeSize = FULL_FW_BYTE_SIZE;
- }
- else
- {
- return IX_ETH_DB_INVALID_ARG;
- }
-
- /* serialize tree into memory */
- ixEthDBNPETreeWrite(type, treeSize, port->updateMethod.npeUpdateZone, port->updateMethod.searchTree, &epDelta, &blockCount);
-
- /* free internal copy */
- if (port->updateMethod.searchTree != NULL)
- {
- ixEthDBFreeMacTreeNode(port->updateMethod.searchTree);
- }
-
- /* forget last used search tree */
- port->updateMethod.searchTree = NULL;
- port->updateMethod.searchTreePendingWrite = FALSE;
-
- /* dependending on the update type we do different things */
- if (type == IX_ETH_DB_FILTERING_RECORD || type == IX_ETH_DB_WIFI_RECORD)
- {
- IX_STATUS result;
-
- FILL_SETMACADDRESSDATABASE_MSG(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID),
- epDelta, blockCount,
- IX_OSAL_MMU_VIRT_TO_PHYS(port->updateMethod.npeUpdateZone));
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- if (result == IX_SUCCESS)
- {
- IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) Finished downloading NPE tree on port %d\n", portID);
- }
- else
- {
- ixEthDBPortInfo[portID].agingEnabled = FALSE;
- ixEthDBPortInfo[portID].updateMethod.updateEnabled = FALSE;
- ixEthDBPortInfo[portID].updateMethod.userControlled = TRUE;
-
- ERROR_LOG("EthDB: (PortUpdate) disabling aging and updates on port %d (assumed dead)\n", portID);
-
- ixEthDBDatabaseClear(portID, IX_ETH_DB_ALL_RECORD_TYPES);
-
- return IX_ETH_DB_FAIL;
- }
-
- return IX_ETH_DB_SUCCESS;
- }
- else if (type == IX_ETH_DB_FIREWALL_RECORD)
- {
- return ixEthDBFirewallUpdate(portID, port->updateMethod.npeUpdateZone, epDelta);
- }
-
- return IX_ETH_DB_INVALID_ARG;
-}
-
-/**
- * @brief queries the database for a set of records to be inserted into a given tree
- *
- * @param searchTree pointer to a tree where insertions will be performed; can be NULL
- * @param query set of ports that a database record must match to be inserted into the tree
- *
- * The query method browses through the database, extracts all the descriptors matching
- * the given query parameter and inserts them into the given learning tree.
- * Note that this is an append procedure, the given tree needs not to be empty.
- * A "descriptor matching the query" is a descriptor whose port id is in the query map.
- * If the given tree is empty (NULL) a new tree is created and returned.
- *
- * @return the tree root
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-MacTreeNode* ixEthDBQuery(MacTreeNode *searchTree, IxEthDBPortMap query, IxEthDBRecordType recordFilter, UINT32 maxEntries)
-{
- HashIterator iterator;
- UINT32 entryCount = 0;
-
- /* browse database */
- BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator));
-
- while (IS_ITERATOR_VALID(&iterator))
- {
- MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data;
-
- IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) querying [%s]:%d on port map ... ",
- mac2string(descriptor->macAddress),
- descriptor->portID);
-
- if ((descriptor->type & recordFilter) != 0
- && IS_PORT_INCLUDED(descriptor->portID, query))
- {
- MacDescriptor *descriptorClone = ixEthDBCloneMacDescriptor(descriptor);
-
- IX_ETH_DB_UPDATE_TRACE("match\n");
-
- if (descriptorClone != NULL)
- {
- /* add descriptor to tree */
- searchTree = ixEthDBTreeInsert(searchTree, descriptorClone);
-
- entryCount++;
- }
- }
- else
- {
- IX_ETH_DB_UPDATE_TRACE("no match\n");
- }
-
- if (entryCount < maxEntries)
- {
- /* advance to the next record */
- BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator));
- }
- else
- {
- /* the NPE won't accept more entries so we can stop now */
- ixEthDBReleaseHashIterator(&iterator);
-
- IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) number of elements reached maximum supported by port\n");
-
- break;
- }
- }
-
- IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) query inserted %d records in the search tree\n", entryCount);
-
- return ixEthDBTreeRebalance(searchTree);
-}
-
-/**
- * @brief inserts a mac descriptor into an tree
- *
- * @param searchTree tree where the insertion is to be performed (may be NULL)
- * @param descriptor descriptor to insert into tree
- *
- * @return the tree root
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-MacTreeNode* ixEthDBTreeInsert(MacTreeNode *searchTree, MacDescriptor *descriptor)
-{
- MacTreeNode *currentNode = searchTree;
- MacTreeNode *insertLocation = NULL;
- MacTreeNode *newNode;
- INT32 insertPosition = RIGHT;
-
- if (descriptor == NULL)
- {
- return searchTree;
- }
-
- /* create a new node */
- newNode = ixEthDBAllocMacTreeNode();
-
- if (newNode == NULL)
- {
- /* out of memory */
- ERROR_LOG("Warning: ixEthDBAllocMacTreeNode returned NULL in file %s:%d (out of memory?)\n", __FILE__, __LINE__);
-
- ixEthDBFreeMacDescriptor(descriptor);
-
- return NULL;
- }
-
- /* populate node */
- newNode->descriptor = descriptor;
-
- /* an empty initial tree is a special case */
- if (searchTree == NULL)
- {
- return newNode;
- }
-
- /* get insertion location */
- while (insertLocation == NULL)
- {
- MacTreeNode *nextNode;
-
- /* compare given key with current node key */
- insertPosition = ixEthDBAddressCompare(descriptor->macAddress, currentNode->descriptor->macAddress);
-
- /* navigate down */
- if (insertPosition == RIGHT)
- {
- nextNode = currentNode->right;
- }
- else if (insertPosition == LEFT)
- {
- nextNode = currentNode->left;
- }
- else
- {
- /* error, duplicate key */
- ERROR_LOG("Warning: trapped insertion of a duplicate MAC address in an NPE search tree\n");
-
- /* this will free the MAC descriptor as well */
- ixEthDBFreeMacTreeNode(newNode);
-
- return searchTree;
- }
-
- /* when we can no longer dive through the tree we found the insertion place */
- if (nextNode != NULL)
- {
- currentNode = nextNode;
- }
- else
- {
- insertLocation = currentNode;
- }
- }
-
- /* insert node */
- if (insertPosition == RIGHT)
- {
- insertLocation->right = newNode;
- }
- else
- {
- insertLocation->left = newNode;
- }
-
- return searchTree;
-}
-
-/**
- * @brief balance a tree
- *
- * @param searchTree tree to balance
- *
- * Converts a tree into a balanced tree and returns the root of
- * the balanced tree. The resulting tree is <i>route balanced</i>
- * not <i>perfectly balanced</i>. This makes no difference to the
- * average tree search time which is the same in both cases, O(log2(n)).
- *
- * @return root of the balanced tree or NULL if there's no memory left
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-MacTreeNode* ixEthDBTreeRebalance(MacTreeNode *searchTree)
-{
- MacTreeNode *pseudoRoot = ixEthDBAllocMacTreeNode();
- UINT32 size;
-
- if (pseudoRoot == NULL)
- {
- /* out of memory */
- return NULL;
- }
-
- pseudoRoot->right = searchTree;
-
- ixEthDBRebalanceTreeToVine(pseudoRoot, &size);
- ixEthDBRebalanceVineToTree(pseudoRoot, size);
-
- searchTree = pseudoRoot->right;
-
- /* remove pseudoRoot right branch, otherwise it will free the entire tree */
- pseudoRoot->right = NULL;
-
- ixEthDBFreeMacTreeNode(pseudoRoot);
-
- return searchTree;
-}
-
-/**
- * @brief converts a tree into a vine
- *
- * @param root root of tree to convert
- * @param size depth of vine (equal to the number of nodes in the tree)
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBRebalanceTreeToVine(MacTreeNode *root, UINT32 *size)
-{
- MacTreeNode *vineTail = root;
- MacTreeNode *remainder = vineTail->right;
- MacTreeNode *tempPtr;
-
- *size = 0;
-
- while (remainder != NULL)
- {
- if (remainder->left == NULL)
- {
- /* move tail down one */
- vineTail = remainder;
- remainder = remainder->right;
- (*size)++;
- }
- else
- {
- /* rotate around remainder */
- tempPtr = remainder->left;
- remainder->left = tempPtr->right;
- tempPtr->right = remainder;
- remainder = tempPtr;
- vineTail->right = tempPtr;
- }
- }
-}
-
-/**
- * @brief converts a vine into a balanced tree
- *
- * @param root vine to convert
- * @param size depth of vine
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBRebalanceVineToTree(MacTreeNode *root, UINT32 size)
-{
- UINT32 leafCount = size + 1 - (1 << ixEthDBRebalanceLog2Floor(size + 1));
-
- ixEthDBRebalanceCompression(root, leafCount);
-
- size = size - leafCount;
-
- while (size > 1)
- {
- ixEthDBRebalanceCompression(root, size / 2);
-
- size /= 2;
- }
-}
-
-/**
- * @brief compresses a vine/tree stage into a more balanced vine/tree
- *
- * @param root root of the tree to compress
- * @param count number of "spine" nodes
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBRebalanceCompression(MacTreeNode *root, UINT32 count)
-{
- MacTreeNode *scanner = root;
- MacTreeNode *child;
- UINT32 local_index;
-
- for (local_index = 0 ; local_index < count ; local_index++)
- {
- child = scanner->right;
- scanner->right = child->right;
- scanner = scanner->right;
- child->right = scanner->left;
- scanner->left = child;
- }
-}
-
-/**
- * @brief computes |_log2(x)_| (a.k.a. floor(log2(x)))
- *
- * @param x number to compute |_log2(x)_| for
- *
- * @return |_log2(x)_|
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-UINT32 ixEthDBRebalanceLog2Floor(UINT32 x)
-{
- UINT32 log = 0;
- UINT32 val = 1;
-
- while (val < x)
- {
- log++;
- val <<= 1;
- }
-
- return val == x ? log : log - 1;
-}
-
+++ /dev/null
-/**
- * @file IxEthDBAPI.c
- *
- * @brief Implementation of the public API
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-
-extern HashTable dbHashtable;
-IX_ETH_DB_PRIVATE void ixEthDBPortInfoShow(IxEthDBPortId portID, IxEthDBRecordType recordFilter);
-IX_ETH_DB_PRIVATE IxEthDBStatus ixEthDBHeaderShow(IxEthDBRecordType recordFilter);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBDependencyPortMapShow(IxEthDBPortId portID, IxEthDBPortMap map);
-
-/**
- * @brief displays a port dependency map
- *
- * @param portID ID of the port
- * @param map port map to display
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBDependencyPortMapShow(IxEthDBPortId portID, IxEthDBPortMap map)
-{
- UINT32 portIndex;
- BOOL mapSelf = TRUE, mapNone = TRUE, firstPort = TRUE;
-
- /* dependency port maps */
- printf("Dependency port map: ");
-
- /* browse the port map */
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- if (IS_PORT_INCLUDED(portIndex, map))
- {
- mapNone = FALSE;
-
- if (portIndex != portID)
- {
- mapSelf = FALSE;
- }
-
- printf("%s%d", firstPort ? "{" : ", ", portIndex);
-
- firstPort = FALSE;
- }
- }
-
- if (mapNone)
- {
- mapSelf = FALSE;
- }
-
- printf("%s (%s)\n", firstPort ? "" : "}", mapSelf ? "self" : mapNone ? "none" : "group");
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief displays all the filtering records belonging to a port
- *
- * @param portID ID of the port to display
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @warning deprecated, use @ref ixEthDBFilteringDatabaseShowRecords()
- * instead. Calling this function is equivalent to calling
- * ixEthDBFilteringDatabaseShowRecords(portID, IX_ETH_DB_FILTERING_RECORD)
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringDatabaseShow(IxEthDBPortId portID)
-{
- IxEthDBStatus local_result;
- HashIterator iterator;
- PortInfo *portInfo;
- UINT32 recordCount = 0;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- portInfo = &ixEthDBPortInfo[portID];
-
- /* display table header */
- printf("Ethernet database records for port ID [%d]\n", portID);
-
- ixEthDBDependencyPortMapShow(portID, portInfo->dependencyPortMap);
-
- if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
- {
- printf("NPE updates are %s\n\n", portInfo->updateMethod.updateEnabled ? "enabled" : "disabled");
- }
- else
- {
- printf("updates disabled (not an NPE)\n\n");
- }
-
- printf(" MAC address | Age | Type \n");
- printf("___________________________________\n");
-
- /* browse database */
- BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator));
-
- while (IS_ITERATOR_VALID(&iterator))
- {
- MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data;
-
- if (descriptor->portID == portID && descriptor->type == IX_ETH_DB_FILTERING_RECORD)
- {
- recordCount++;
-
- /* display entry */
- printf(" %02X:%02X:%02X:%02X:%02X:%02X | %5d | %s\n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5],
- descriptor->recordData.filteringData.age,
- descriptor->recordData.filteringData.staticEntry ? "static" : "dynamic");
- }
-
- /* move to the next record */
- BUSY_RETRY_WITH_RESULT(ixEthDBIncrementHashIterator(&dbHashtable, &iterator), local_result);
-
- /* debug */
- if (local_result == IX_ETH_DB_BUSY)
- {
- return IX_ETH_DB_FAIL;
- }
- }
-
- /* display number of records */
- printf("\nFound %d records\n", recordCount);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief displays all the filtering records belonging to all the ports
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @warning deprecated, use @ref ixEthDBFilteringDatabaseShowRecords()
- * instead. Calling this function is equivalent to calling
- * ixEthDBFilteringDatabaseShowRecords(IX_ETH_DB_ALL_PORTS, IX_ETH_DB_FILTERING_RECORD)
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBFilteringDatabaseShowAll()
-{
- IxEthDBPortId portIndex;
-
- printf("\nEthernet learning/filtering database: listing %d ports\n\n", (UINT32) IX_ETH_DB_NUMBER_OF_PORTS);
-
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- ixEthDBFilteringDatabaseShow(portIndex);
-
- if (portIndex < IX_ETH_DB_NUMBER_OF_PORTS - 1)
- {
- printf("\n");
- }
- }
-}
-
-/**
- * @brief displays one record in a format depending on the record filter
- *
- * @param descriptor pointer to the record
- * @param recordFilter format filter
- *
- * This function will display the fields in a record depending on the
- * selected record filter.
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBRecordShow(MacDescriptor *descriptor, IxEthDBRecordType recordFilter)
-{
- if (recordFilter == IX_ETH_DB_FILTERING_VLAN_RECORD
- || recordFilter == (IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD))
- {
- /* display VLAN record header - leave this commented code in place, its purpose is to align the print format with the header
- printf(" MAC address | Age | Type | VLAN ID | CFI | QoS class \n");
- printf("___________________________________________________________________\n"); */
-
- if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD)
- {
- printf("%02X:%02X:%02X:%02X:%02X:%02X | %3d | %s | %d | %d | %d\n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5],
- descriptor->recordData.filteringVlanData.age,
- descriptor->recordData.filteringVlanData.staticEntry ? "static" : "dynamic",
- IX_ETH_DB_GET_VLAN_ID(descriptor->recordData.filteringVlanData.ieee802_1qTag),
- (descriptor->recordData.filteringVlanData.ieee802_1qTag & 0x1000) >> 12,
- IX_ETH_DB_GET_QOS_PRIORITY(descriptor->recordData.filteringVlanData.ieee802_1qTag));
- }
- else if (descriptor->type == IX_ETH_DB_FILTERING_RECORD)
- {
- printf("%02X:%02X:%02X:%02X:%02X:%02X | %3d | %s | - | - | -\n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5],
- descriptor->recordData.filteringData.age,
- descriptor->recordData.filteringData.staticEntry ? "static" : "dynamic");
- }
- }
- else if (recordFilter == IX_ETH_DB_FILTERING_RECORD)
- {
- /* display filtering record header - leave this commented code in place, its purpose is to align the print format with the header
- printf(" MAC address | Age | Type \n");
- printf("_______________________________________\n"); */
-
- if (descriptor->type == IX_ETH_DB_FILTERING_RECORD)
- {
- printf("%02X:%02X:%02X:%02X:%02X:%02X | %3d | %s \n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5],
- descriptor->recordData.filteringData.age,
- descriptor->recordData.filteringData.staticEntry ? "static" : "dynamic");
- }
- }
- else if (recordFilter == IX_ETH_DB_WIFI_RECORD)
- {
- /* display WiFi record header - leave this commented code in place, its purpose is to align the print format with the header
- printf(" MAC address | GW MAC address \n");
- printf("_______________________________________\n"); */
-
- if (descriptor->type == IX_ETH_DB_WIFI_RECORD)
- {
- if (descriptor->recordData.wifiData.type == IX_ETH_DB_WIFI_AP_TO_AP)
- {
- /* gateway address present */
- printf("%02X:%02X:%02X:%02X:%02X:%02X | %02X:%02X:%02X:%02X:%02X:%02X \n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5],
- descriptor->recordData.wifiData.gwMacAddress[0],
- descriptor->recordData.wifiData.gwMacAddress[1],
- descriptor->recordData.wifiData.gwMacAddress[2],
- descriptor->recordData.wifiData.gwMacAddress[3],
- descriptor->recordData.wifiData.gwMacAddress[4],
- descriptor->recordData.wifiData.gwMacAddress[5]);
- }
- else
- {
- /* no gateway */
- printf("%02X:%02X:%02X:%02X:%02X:%02X | ----no gateway----- \n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5]);
- }
- }
- }
- else if (recordFilter == IX_ETH_DB_FIREWALL_RECORD)
- {
- /* display Firewall record header - leave this commented code in place, its purpose is to align the print format with the header
- printf(" MAC address \n");
- printf("__________________\n"); */
-
- if (descriptor->type == IX_ETH_DB_FIREWALL_RECORD)
- {
- printf("%02X:%02X:%02X:%02X:%02X:%02X \n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5]);
- }
- }
- else if (recordFilter == IX_ETH_DB_ALL_RECORD_TYPES)
- {
- /* display composite record header - leave this commented code in place, its purpose is to align the print format with the header
- printf(" MAC address | Record | Age| Type | VLAN |CFI| QoS | GW MAC address \n");
- printf("_______________________________________________________________________________\n"); */
-
- if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD)
- {
- printf("%02X:%02X:%02X:%02X:%02X:%02X | VLAN | %2d | %s | %4d | %1d | %1d | -----------------\n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5],
- descriptor->recordData.filteringVlanData.age,
- descriptor->recordData.filteringVlanData.staticEntry ? "static " : "dynamic",
- IX_ETH_DB_GET_VLAN_ID(descriptor->recordData.filteringVlanData.ieee802_1qTag),
- (descriptor->recordData.filteringVlanData.ieee802_1qTag & 0x1000) >> 12,
- IX_ETH_DB_GET_QOS_PRIORITY(descriptor->recordData.filteringVlanData.ieee802_1qTag));
- }
- else if (descriptor->type == IX_ETH_DB_FILTERING_RECORD)
- {
- printf("%02X:%02X:%02X:%02X:%02X:%02X | Filter | %2d | %s | ---- | - | --- | -----------------\n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5],
- descriptor->recordData.filteringData.age,
- descriptor->recordData.filteringData.staticEntry ? "static " : "dynamic");
- }
- else if (descriptor->type == IX_ETH_DB_WIFI_RECORD)
- {
- if (descriptor->recordData.wifiData.type == IX_ETH_DB_WIFI_AP_TO_AP)
- {
- /* gateway address present */
- printf("%02X:%02X:%02X:%02X:%02X:%02X | WiFi | -- | AP=>AP | ---- | - | --- | %02X:%02X:%02X:%02X:%02X:%02X\n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5],
- descriptor->recordData.wifiData.gwMacAddress[0],
- descriptor->recordData.wifiData.gwMacAddress[1],
- descriptor->recordData.wifiData.gwMacAddress[2],
- descriptor->recordData.wifiData.gwMacAddress[3],
- descriptor->recordData.wifiData.gwMacAddress[4],
- descriptor->recordData.wifiData.gwMacAddress[5]);
- }
- else
- {
- /* no gateway */
- printf("%02X:%02X:%02X:%02X:%02X:%02X | WiFi | -- | AP=>ST | ---- | - | --- | -- no gateway -- \n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5]);
- }
- }
- else if (descriptor->type == IX_ETH_DB_FIREWALL_RECORD)
- {
- printf("%02X:%02X:%02X:%02X:%02X:%02X | FW | -- | ------- | ---- | - | --- | -----------------\n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5]);
- }
- }
- else
- {
- printf("invalid record filter\n");
- }
-}
-
-/**
- * @brief displays the status, records and configuration information of a port
- *
- * @param portID ID of the port
- * @param recordFilter record filter to display
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBPortInfoShow(IxEthDBPortId portID, IxEthDBRecordType recordFilter)
-{
- PortInfo *portInfo = &ixEthDBPortInfo[portID];
- UINT32 recordCount = 0;
- HashIterator iterator;
- IxEthDBStatus local_result;
-
- /* display port status */
- printf("== Port ID %d ==\n", portID);
-
- /* display capabilities */
- printf("- Capabilities: ");
-
- if ((portInfo->featureCapability & IX_ETH_DB_LEARNING) != 0)
- {
- printf("Learning (%s) ", ((portInfo->featureStatus & IX_ETH_DB_LEARNING) != 0) ? "on" : "off");
- }
-
- if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0)
- {
- printf("VLAN/QoS (%s) ", ((portInfo->featureStatus & IX_ETH_DB_VLAN_QOS) != 0) ? "on" : "off");
- }
-
- if ((portInfo->featureCapability & IX_ETH_DB_FIREWALL) != 0)
- {
- printf("Firewall (%s) ", ((portInfo->featureStatus & IX_ETH_DB_FIREWALL) != 0) ? "on" : "off");
- }
-
- if ((portInfo->featureCapability & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0)
- {
- printf("WiFi (%s) ", ((portInfo->featureStatus & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0) ? "on" : "off");
- }
-
- if ((portInfo->featureCapability & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0)
- {
- printf("STP (%s) ", ((portInfo->featureStatus & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0) ? "on" : "off");
- }
-
- printf("\n");
-
- /* dependency map */
- ixEthDBDependencyPortMapShow(portID, portInfo->dependencyPortMap);
-
- /* NPE dynamic updates */
- if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
- {
- printf(" - NPE dynamic update is %s\n", portInfo->updateMethod.updateEnabled ? "enabled" : "disabled");
- }
- else
- {
- printf(" - dynamic update disabled (not an NPE)\n");
- }
-
- if ((portInfo->featureCapability & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0)
- {
- if ((portInfo->featureStatus & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0)
- {
- /* WiFi header conversion */
- if ((portInfo->frameControlDurationID
- + portInfo->bbsid[0]
- + portInfo->bbsid[1]
- + portInfo->bbsid[2]
- + portInfo->bbsid[3]
- + portInfo->bbsid[4]
- + portInfo->bbsid[5]) == 0)
- {
- printf(" - WiFi header conversion not configured\n");
- }
- else
- {
- printf(" - WiFi header conversion: BBSID [%02X:%02X:%02X:%02X:%02X:%02X], Frame Control 0x%X, Duration/ID 0x%X\n",
- portInfo->bbsid[0],
- portInfo->bbsid[1],
- portInfo->bbsid[2],
- portInfo->bbsid[3],
- portInfo->bbsid[4],
- portInfo->bbsid[5],
- portInfo->frameControlDurationID >> 16,
- portInfo->frameControlDurationID & 0xFFFF);
- }
- }
- else
- {
- printf(" - WiFi header conversion not enabled\n");
- }
- }
-
- /* Firewall */
- if ((portInfo->featureCapability & IX_ETH_DB_FIREWALL) != 0)
- {
- if ((portInfo->featureStatus & IX_ETH_DB_FIREWALL) != 0)
- {
- printf(" - Firewall is in %s-list mode\n", portInfo->firewallMode == IX_ETH_DB_FIREWALL_BLACK_LIST ? "black" : "white");
- printf(" - Invalid source MAC address filtering is %s\n", portInfo->srcAddressFilterEnabled ? "enabled" : "disabled");
- }
- else
- {
- printf(" - Firewall not enabled\n");
- }
- }
-
- /* browse database if asked to display records */
- if (recordFilter != IX_ETH_DB_NO_RECORD_TYPE)
- {
- printf("\n");
- ixEthDBHeaderShow(recordFilter);
-
- BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator));
-
- while (IS_ITERATOR_VALID(&iterator))
- {
- MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data;
-
- if (descriptor->portID == portID && (descriptor->type & recordFilter) != 0)
- {
- recordCount++;
-
- /* display entry */
- ixEthDBRecordShow(descriptor, recordFilter);
- }
-
- /* move to the next record */
- BUSY_RETRY_WITH_RESULT(ixEthDBIncrementHashIterator(&dbHashtable, &iterator), local_result);
-
- /* debug */
- if (local_result == IX_ETH_DB_BUSY)
- {
- printf("EthDB (API): Error, database browser failed (no access), giving up\n");
- }
- }
-
- printf("\nFound %d records\n\n", recordCount);
- }
-}
-
-/**
- * @brief displays a record header
- *
- * @param recordFilter record type filter
- *
- * This function displays a record header, depending on
- * the given record type filter. It is useful when used
- * in conjunction with ixEthDBRecordShow which will display
- * record fields formatted for the header, provided the same
- * record filter is used.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or IX_ETH_DB_INVALID_ARG if the recordFilter
- * parameter is invalid or not supported
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBHeaderShow(IxEthDBRecordType recordFilter)
-{
- if (recordFilter == IX_ETH_DB_FILTERING_VLAN_RECORD
- || recordFilter == (IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD))
- {
- /* display VLAN record header */
- printf(" MAC address | Age | Type | VLAN ID | CFI | QoS class \n");
- printf("___________________________________________________________________\n");
- }
- else if (recordFilter == IX_ETH_DB_FILTERING_RECORD)
- {
- /* display filtering record header */
- printf(" MAC address | Age | Type \n");
- printf("_______________________________________\n");
- }
- else if (recordFilter == IX_ETH_DB_WIFI_RECORD)
- {
- /* display WiFi record header */
- printf(" MAC address | GW MAC address \n");
- printf("_______________________________________\n");
- }
- else if (recordFilter == IX_ETH_DB_FIREWALL_RECORD)
- {
- /* display Firewall record header */
- printf(" MAC address \n");
- printf("__________________\n");
- }
- else if (recordFilter == IX_ETH_DB_ALL_RECORD_TYPES)
- {
- /* display composite record header */
- printf(" MAC address | Record | Age| Type | VLAN |CFI| QoS | GW MAC address \n");
- printf("_______________________________________________________________________________\n");
- }
- else
- {
- return IX_ETH_DB_INVALID_ARG;
- }
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief displays database information (records and port information)
- *
- * @param portID ID of the port to display (or IX_ETH_DB_ALL_PORTS for all the ports)
- * @param recordFilter record filter (use IX_ETH_DB_NO_RECORD_TYPE to display only
- * port information)
- *
- * Note that this function is documented in the main component header
- * file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully or
- * an appropriate error code otherwise
- *
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringDatabaseShowRecords(IxEthDBPortId portID, IxEthDBRecordType recordFilter)
-{
- IxEthDBPortId currentPort;
- BOOL showAllPorts = (portID == IX_ETH_DB_ALL_PORTS);
-
- IX_ETH_DB_CHECK_PORT_ALL(portID);
-
- printf("\nEthernet learning/filtering database: listing %d port(s)\n\n", showAllPorts ? (UINT32) IX_ETH_DB_NUMBER_OF_PORTS : 1);
-
- currentPort = showAllPorts ? 0 : portID;
-
- while (currentPort != IX_ETH_DB_NUMBER_OF_PORTS)
- {
- /* display port info */
- ixEthDBPortInfoShow(currentPort, recordFilter);
-
- /* next port */
- currentPort = showAllPorts ? currentPort + 1 : IX_ETH_DB_NUMBER_OF_PORTS;
- }
-
- return IX_ETH_DB_SUCCESS;
-}
-
+++ /dev/null
-/**
- * @file IxEthDBSearch.c
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-
-extern HashTable dbHashtable;
-
-/**
- * @brief matches two database records based on their MAC addresses
- *
- * @param untypedReference record to match against
- * @param untypedEntry record to match
- *
- * @return TRUE if the match is successful or FALSE otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-BOOL ixEthDBAddressRecordMatch(void *untypedReference, void *untypedEntry)
-{
- MacDescriptor *entry = (MacDescriptor *) untypedEntry;
- MacDescriptor *reference = (MacDescriptor *) untypedReference;
-
- /* check accepted record types */
- if ((entry->type & reference->type) == 0) return FALSE;
-
- return (ixEthDBAddressCompare((UINT8 *) entry->macAddress, (UINT8 *) reference->macAddress) == 0);
-}
-
-/**
- * @brief matches two database records based on their MAC addresses
- * and VLAN IDs
- *
- * @param untypedReference record to match against
- * @param untypedEntry record to match
- *
- * @return TRUE if the match is successful or FALSE otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-BOOL ixEthDBVlanRecordMatch(void *untypedReference, void *untypedEntry)
-{
- MacDescriptor *entry = (MacDescriptor *) untypedEntry;
- MacDescriptor *reference = (MacDescriptor *) untypedReference;
-
- /* check accepted record types */
- if ((entry->type & reference->type) == 0) return FALSE;
-
- return (IX_ETH_DB_GET_VLAN_ID(entry->recordData.filteringVlanData.ieee802_1qTag) ==
- IX_ETH_DB_GET_VLAN_ID(reference->recordData.filteringVlanData.ieee802_1qTag)) &&
- (ixEthDBAddressCompare(entry->macAddress, reference->macAddress) == 0);
-}
-
-/**
- * @brief matches two database records based on their MAC addresses
- * and port IDs
- *
- * @param untypedReference record to match against
- * @param untypedEntry record to match
- *
- * @return TRUE if the match is successful or FALSE otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-BOOL ixEthDBPortRecordMatch(void *untypedReference, void *untypedEntry)
-{
- MacDescriptor *entry = (MacDescriptor *) untypedEntry;
- MacDescriptor *reference = (MacDescriptor *) untypedReference;
-
- /* check accepted record types */
- if ((entry->type & reference->type) == 0) return FALSE;
-
- return (entry->portID == reference->portID) &&
- (ixEthDBAddressCompare(entry->macAddress, reference->macAddress) == 0);
-}
-
-/**
- * @brief dummy matching function, registered for safety
- *
- * @param reference record to match against (unused)
- * @param entry record to match (unused)
- *
- * This function is registered in the matching functions
- * array on invalid types. Calling it will display an
- * error message, indicating an error in the component logic.
- *
- * @return FALSE
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-BOOL ixEthDBNullMatch(void *reference, void *entry)
-{
- /* display an error message */
-
- ixOsalLog(IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, "DB: (Search) The NullMatch function was called, wrong key type?\n", 0, 0, 0, 0, 0, 0);
-
-
- return FALSE;
-}
-
-/**
- * @brief registers hash matching methods
- *
- * @param matchFunctions table of match functions to be populated
- *
- * This function registers the available record matching functions
- * by indexing them on record types into the given function array.
- *
- * Note that it is compulsory to call this in ixEthDBInit(),
- * otherwise hashtable searching and removal will not work
- *
- * @return number of registered functions
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-UINT32 ixEthDBMatchMethodsRegister(MatchFunction *matchFunctions)
-{
- UINT32 i;
-
- /* safety first */
- for ( i = 0 ; i < IX_ETH_DB_MAX_KEY_INDEX + 1 ; i++)
- {
- matchFunctions[i] = ixEthDBNullMatch;
- }
-
- /* register MAC search method */
- matchFunctions[IX_ETH_DB_MAC_KEY] = ixEthDBAddressRecordMatch;
-
- /* register MAC/PortID search method */
- matchFunctions[IX_ETH_DB_MAC_PORT_KEY] = ixEthDBPortRecordMatch;
-
- /* register MAC/VLAN ID search method */
- matchFunctions[IX_ETH_DB_MAC_VLAN_KEY] = ixEthDBVlanRecordMatch;
-
- return 3; /* three methods */
-}
-
-/**
- * @brief search a record in the Ethernet datbase
- *
- * @param macAddress MAC address to perform the search on
- * @param typeFilter type of records to consider for matching
- *
- * @warning if searching is successful an implicit write lock
- * to the search result is granted, therefore unlock the
- * entry using @ref ixEthDBReleaseHashNode() as soon as possible.
- *
- * @see ixEthDBReleaseHashNode()
- *
- * @return the search result, or NULL if a record with the given
- * MAC address was not found
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-HashNode* ixEthDBSearch(IxEthDBMacAddr *macAddress, IxEthDBRecordType typeFilter)
-{
- HashNode *searchResult = NULL;
- MacDescriptor reference;
-
- TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER;
-
- if (macAddress == NULL)
- {
- return NULL;
- }
-
- /* fill search fields */
- memcpy(reference.macAddress, macAddress, sizeof (IxEthDBMacAddr));
-
- /* set acceptable record types */
- reference.type = typeFilter;
-
- BUSY_RETRY(ixEthDBSearchHashEntry(&dbHashtable, IX_ETH_DB_MAC_KEY, &reference, &searchResult));
-
- return searchResult;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPeek(IxEthDBMacAddr *macAddress, IxEthDBRecordType typeFilter)
-{
- MacDescriptor reference;
- IxEthDBStatus result;
-
- TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER;
-
- if (macAddress == NULL)
- {
- return IX_ETH_DB_INVALID_ARG;
- }
-
- /* fill search fields */
- memcpy(reference.macAddress, macAddress, sizeof (IxEthDBMacAddr));
-
- /* set acceptable record types */
- reference.type = typeFilter;
-
- result = ixEthDBPeekHashEntry(&dbHashtable, IX_ETH_DB_MAC_KEY, &reference);
-
- return result;
-}
-
-/**
- * @brief search a record in the Ethernet datbase
- *
- * @param macAddress MAC address to perform the search on
- * @param portID port ID to perform the search on
- * @param typeFilter type of records to consider for matching
- *
- * @warning if searching is successful an implicit write lock
- * to the search result is granted, therefore unlock the
- * entry using @ref ixEthDBReleaseHashNode() as soon as possible.
- *
- * @see ixEthDBReleaseHashNode()
- *
- * @return the search result, or NULL if a record with the given
- * MAC address/port ID combination was not found
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-HashNode* ixEthDBPortSearch(IxEthDBMacAddr *macAddress, IxEthDBPortId portID, IxEthDBRecordType typeFilter)
-{
- HashNode *searchResult = NULL;
- MacDescriptor reference;
-
- if (macAddress == NULL)
- {
- return NULL;
- }
-
- /* fill search fields */
- memcpy(reference.macAddress, macAddress, sizeof (IxEthDBMacAddr));
- reference.portID = portID;
-
- /* set acceptable record types */
- reference.type = typeFilter;
-
- BUSY_RETRY(ixEthDBSearchHashEntry(&dbHashtable, IX_ETH_DB_MAC_PORT_KEY, &reference, &searchResult));
-
- return searchResult;
-}
-
-/**
- * @brief search a record in the Ethernet datbase
- *
- * @param macAddress MAC address to perform the search on
- * @param vlanID VLAN ID to perform the search on
- * @param typeFilter type of records to consider for matching
- *
- * @warning if searching is successful an implicit write lock
- * to the search result is granted, therefore unlock the
- * entry using @ref ixEthDBReleaseHashNode() as soon as possible.
- *
- * @see ixEthDBReleaseHashNode()
- *
- * @return the search result, or NULL if a record with the given
- * MAC address/VLAN ID combination was not found
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-HashNode* ixEthDBVlanSearch(IxEthDBMacAddr *macAddress, IxEthDBVlanId vlanID, IxEthDBRecordType typeFilter)
-{
- HashNode *searchResult = NULL;
- MacDescriptor reference;
-
- if (macAddress == NULL)
- {
- return NULL;
- }
-
- /* fill search fields */
- memcpy(reference.macAddress, macAddress, sizeof (IxEthDBMacAddr));
- reference.recordData.filteringVlanData.ieee802_1qTag =
- IX_ETH_DB_SET_VLAN_ID(reference.recordData.filteringVlanData.ieee802_1qTag, vlanID);
-
- /* set acceptable record types */
- reference.type = typeFilter;
-
- BUSY_RETRY(ixEthDBSearchHashEntry(&dbHashtable, IX_ETH_DB_MAC_VLAN_KEY, &reference, &searchResult));
-
- return searchResult;
-}
+++ /dev/null
-/**
- * @file IxEthDBSpanningTree.c
- *
- * @brief Implementation of the STP API
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#include "IxEthDB_p.h"
-
-/**
- * @brief sets the STP blocking state of a port
- *
- * @param portID ID of the port
- * @param blocked TRUE to block the port or FALSE to unblock it
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBSpanningTreeBlockingStateSet(IxEthDBPortId portID, BOOL blocked)
-{
- IxNpeMhMessage message;
- IX_STATUS result;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_SPANNING_TREE_PROTOCOL);
-
- ixEthDBPortInfo[portID].stpBlocked = blocked;
-
- FILL_SETBLOCKINGSTATE_MSG(message, portID, blocked);
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- return result;
-}
-
-/**
- * @brief retrieves the STP blocking state of a port
- *
- * @param portID ID of the port
- * @param blocked address to write the blocked status into
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBSpanningTreeBlockingStateGet(IxEthDBPortId portID, BOOL *blocked)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_SPANNING_TREE_PROTOCOL);
-
- IX_ETH_DB_CHECK_REFERENCE(blocked);
-
- *blocked = ixEthDBPortInfo[portID].stpBlocked;
-
- return IX_ETH_DB_SUCCESS;
-}
+++ /dev/null
-/**
- * @file ethUtil.c
- *
- * @brief Utility functions
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#include "IxFeatureCtrl.h"
-#include "IxEthDB_p.h"
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBSingleEthNpeCheck(IxEthDBPortId portID)
-{
- /* If not IXP42X A0 stepping, proceed to check for existence of coprocessors */
- if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
- (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
- || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
- {
- if ((portID == 0) &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED))
- {
- return IX_ETH_DB_FAIL;
- }
-
- if ((portID == 1) &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED))
- {
- return IX_ETH_DB_FAIL;
- }
-
- if ((portID == 2) &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA_ETH) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED))
- {
- return IX_ETH_DB_FAIL;
- }
- }
-
- return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-BOOL ixEthDBCheckSingleBitValue(UINT32 value)
-{
-#if (CPU != SIMSPARCSOLARIS) && !defined (__wince)
- UINT32 shift;
-
- /* use the count-leading-zeros XScale instruction */
- __asm__ ("clz %0, %1\n" : "=r" (shift) : "r" (value));
-
- return ((value << shift) == 0x80000000UL);
-
-#else
-
- while (value != 0)
- {
- if (value == 1) return TRUE;
- else if ((value & 1) == 1) return FALSE;
-
- value >>= 1;
- }
-
- return FALSE;
-
-#endif
-}
-
-const char *mac2string(const unsigned char *mac)
-{
- static char str[19];
-
- if (mac == NULL)
- {
- return NULL;
- }
-
- sprintf(str, "%02X:%02X:%02X:%02X:%02X:%02X", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
-
- return str;
-}
+++ /dev/null
-/**
- * @file IxEthDBVlan.c
- *
- * @brief Implementation of the VLAN API
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB.h"
-#include "IxEthDB_p.h"
-
-/* forward prototypes */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBUpdateTrafficClass(IxEthDBPortId portID, UINT32 classIndex);
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBVlanTableGet(IxEthDBPortId portID, IxEthDBVlanSet portVlanTable, IxEthDBVlanSet vlanSet);
-
-/* contants used by various functions as "action" parameter */
-#define ADD_VLAN (0x1)
-#define REMOVE_VLAN (0x2)
-
-/**
- * @brief adds or removes a VLAN from a VLAN set
- *
- * @param vlanID VLAN ID to add or remove
- * @param table VLAN set to add into or remove from
- * @param action ADD_VLAN or REMOVE_VLAN
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBLocalVlanMembershipChange(UINT32 vlanID, IxEthDBVlanSet table, UINT32 action)
-{
- UINT32 setOffset;
-
- /* add/remove VID to membership table */
- setOffset = VLAN_SET_OFFSET(vlanID); /* we need 9 bits to index the 512 byte membership array */
-
- if (action == ADD_VLAN)
- {
- table[setOffset] |= 1 << VLAN_SET_MASK(vlanID);
- }
- else if (action == REMOVE_VLAN)
- {
- table[setOffset] &= ~(1 << VLAN_SET_MASK(vlanID));
- }
-}
-
-/**
- * @brief updates a set of 8 VLANs in an NPE
- *
- * @param portID ID of the port
- * @param setOffset offset of the 8 VLANs
- *
- * This function updates the VLAN membership table
- * and Transmit Tagging Info table for 8 consecutive
- * VLAN IDs indexed by setOffset.
- *
- * For example, a setOffset of 0 indexes VLAN IDs 0
- * through 7, 1 indexes VLAN IDs 8 through 9 etc.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBVlanTableEntryUpdate(IxEthDBPortId portID, UINT32 setOffset)
-{
- PortInfo *portInfo = &ixEthDBPortInfo[portID];
- IxNpeMhMessage message;
- IX_STATUS result;
-
- FILL_SETPORTVLANTABLEENTRY_MSG(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID),
- 2 * setOffset,
- portInfo->vlanMembership[setOffset],
- portInfo->transmitTaggingInfo[setOffset]);
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- return result;
-}
-
-/**
- * @brief updates a VLAN range in an NPE
- *
- * @param portID ID of the port
- *
- * This function is similar to @ref ixEthDBVlanTableEntryUpdate
- * except that it can update more than one VLAN set (up to
- * the entire VLAN membership and TTI tables if the offset is 0
- * and length is sizeof (IxEthDBVlanSet) (512 bytes).
- *
- * Updating the NPE via this method is slower as it requires
- * a memory copy from SDRAM, hence it is recommended that the
- * ixEthDBVlanTableEntryUpdate function is used where possible.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBVlanTableRangeUpdate(IxEthDBPortId portID)
-{
- PortInfo *portInfo = &ixEthDBPortInfo[portID];
- UINT8 *vlanUpdateZone = (UINT8 *) portInfo->updateMethod.vlanUpdateZone;
- IxNpeMhMessage message;
- UINT32 setIndex;
- IX_STATUS result;
-
- /* copy membership info and transmit tagging into into exchange area */
- for (setIndex = 0 ; setIndex < sizeof (portInfo->vlanMembership) ; setIndex++)
- {
- /* membership and TTI data are interleaved */
- vlanUpdateZone[setIndex * 2] = portInfo->vlanMembership[setIndex];
- vlanUpdateZone[setIndex * 2 + 1] = portInfo->transmitTaggingInfo[setIndex];
- }
-
- IX_OSAL_CACHE_FLUSH(vlanUpdateZone, FULL_VLAN_BYTE_SIZE);
-
- /* build NPE message */
- FILL_SETPORTVLANTABLERANGE_MSG(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), 0, 0,
- IX_OSAL_MMU_VIRT_TO_PHYS(vlanUpdateZone));
-
- /* send message */
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- return result;
-}
-
-/**
- * @brief adds or removes a VLAN from a port's VLAN membership table
- * or Transmit Tagging Information table
- *
- * @param portID ID of the port
- * @param vlanID VLAN ID to add or remove
- * @param table to add or remove from
- * @param action ADD_VLAN or REMOVE_VLAN
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBPortVlanMembershipChange(IxEthDBPortId portID, IxEthDBVlanId vlanID, IxEthDBVlanSet table, UINT32 action)
-{
- /* change VLAN in local membership table */
- ixEthDBLocalVlanMembershipChange(vlanID, table, action);
-
- /* send updated entry to NPE */
- return ixEthDBVlanTableEntryUpdate(portID, VLAN_SET_OFFSET(vlanID));
-}
-
-/**
- * @brief sets the default port VLAN tag (the lower 3 bytes are the PVID)
- *
- * @param portID ID of the port
- * @param vlanTag port VLAN tag (802.1Q tag)
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanTagSet(IxEthDBPortId portID, IxEthDBVlanTag vlanTag)
-{
- IxNpeMhMessage message;
- IX_STATUS result;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_VLAN_TAG(vlanTag);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- /* add VLAN ID to local membership table */
- ixEthDBPortVlanMembershipChange(portID,
- vlanTag & IX_ETH_DB_802_1Q_VLAN_MASK,
- ixEthDBPortInfo[portID].vlanMembership,
- ADD_VLAN);
-
- /* set tag in portInfo */
- ixEthDBPortInfo[portID].vlanTag = vlanTag;
-
- /* build VLAN_SetDefaultRxVID message */
- FILL_SETDEFAULTRXVID_MSG(message,
- IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID),
- IX_IEEE802_1Q_VLAN_TPID,
- vlanTag);
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- return result;
-}
-
-/**
- * @brief retrieves the default port VLAN tag (the lower 3 bytes are the PVID)
- *
- * @param portID ID of the port
- * @param vlanTag address to write the port VLAN tag (802.1Q tag) into
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanTagGet(IxEthDBPortId portID, IxEthDBVlanTag *vlanTag)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- IX_ETH_DB_CHECK_REFERENCE(vlanTag);
-
- *vlanTag = ixEthDBPortInfo[portID].vlanTag;
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief sets the VLAN tag (the lower 3 bytes are the PVID) of a
- * database filtering record
- *
- * @param portID ID of the port
- * @param vlanTag VLAN tag (802.1Q tag)
- *
- * Important: filtering records are automatically converted to
- * IX_ETH_DB_FILTERING_VLAN record when added a VLAN tag.
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBVlanTagSet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag vlanTag)
-{
- HashNode *searchResult;
- MacDescriptor *descriptor;
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- IX_ETH_DB_CHECK_VLAN_TAG(vlanTag);
-
- searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS);
-
- if (searchResult == NULL)
- {
- return IX_ETH_DB_NO_SUCH_ADDR;
- }
-
- descriptor = (MacDescriptor *) searchResult->data;
-
- /* set record type to VLAN if not already set */
- descriptor->type = IX_ETH_DB_FILTERING_VLAN_RECORD;
-
- /* add vlan tag */
- descriptor->recordData.filteringVlanData.ieee802_1qTag = vlanTag;
-
- /* transaction completed */
- ixEthDBReleaseHashNode(searchResult);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief retrieves the VLAN tag (the lower 3 bytes are the PVID) from a
- * database VLAN filtering record
- *
- * @param portID ID of the port
- * @param vlanTag address to write the VLAN tag (802.1Q tag) into
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBVlanTagGet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag *vlanTag)
-{
- HashNode *searchResult;
- MacDescriptor *descriptor;
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- IX_ETH_DB_CHECK_REFERENCE(vlanTag);
-
- searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_FILTERING_VLAN_RECORD);
-
- if (searchResult == NULL)
- {
- return IX_ETH_DB_NO_SUCH_ADDR;
- }
-
- descriptor = (MacDescriptor *) searchResult->data;
-
- /* get vlan tag */
- *vlanTag = descriptor->recordData.filteringVlanData.ieee802_1qTag;
-
- /* transaction completed */
- ixEthDBReleaseHashNode(searchResult);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief adds a VLAN to a port's VLAN membership table
- *
- * @param portID ID of the port
- * @param vlanID VLAN ID to add
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanMembershipAdd(IxEthDBPortId portID, IxEthDBVlanId vlanID)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_VLAN_ID(vlanID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- return ixEthDBPortVlanMembershipChange(portID, vlanID, ixEthDBPortInfo[portID].vlanMembership, ADD_VLAN);
-}
-
-/**
- * @brief removes a VLAN from a port's VLAN membership table
- *
- * @param portID ID of the port
- * @param vlanID VLAN ID to remove
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanMembershipRemove(IxEthDBPortId portID, IxEthDBVlanId vlanID)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- IX_ETH_DB_CHECK_VLAN_ID(vlanID);
-
- /* for safety isolate only the VLAN ID in the tag (the lower 12 bits) */
- vlanID = vlanID & IX_ETH_DB_802_1Q_VLAN_MASK;
-
- /* check we're not asked to remove the default port VID */
- if (vlanID == IX_ETH_DB_GET_VLAN_ID(ixEthDBPortInfo[portID].vlanTag))
- {
- return IX_ETH_DB_NO_PERMISSION;
- }
-
- return ixEthDBPortVlanMembershipChange(portID, vlanID, ixEthDBPortInfo[portID].vlanMembership, REMOVE_VLAN);
-}
-
-/**
- * @brief adds or removes a VLAN range from a port's
- * VLAN membership table or TTI table
- *
- * @param portID ID of the port
- * @param vlanIDMin start of the VLAN range
- * @param vlanIDMax end of the VLAN range
- * @param table VLAN set to add or remove from
- * @param action ADD_VLAN or REMOVE_VLAN
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBPortVlanMembershipRangeChange(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax, IxEthDBVlanSet table, UINT32 action)
-{
- UINT32 setOffsetMin, setOffsetMax;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- IX_ETH_DB_CHECK_VLAN_ID(vlanIDMin);
-
- IX_ETH_DB_CHECK_VLAN_ID(vlanIDMax);
-
- /* for safety isolate only the VLAN ID in the tags (the lower 12 bits) */
- vlanIDMin = vlanIDMin & IX_ETH_DB_802_1Q_VLAN_MASK;
- vlanIDMax = vlanIDMax & IX_ETH_DB_802_1Q_VLAN_MASK;
-
- /* is this a range? */
- if (vlanIDMax < vlanIDMin)
- {
- return IX_ETH_DB_INVALID_VLAN;
- }
-
- /* check that we're not specifically asked to remove the default port VID */
- if (action == REMOVE_VLAN && vlanIDMax == vlanIDMin && IX_ETH_DB_GET_VLAN_ID(ixEthDBPortInfo[portID].vlanTag) == vlanIDMin)
- {
- return IX_ETH_DB_NO_PERMISSION;
- }
-
- /* compute set offsets */
- setOffsetMin = VLAN_SET_OFFSET(vlanIDMin);
- setOffsetMax = VLAN_SET_OFFSET(vlanIDMax);
-
- /* change VLAN range */
- for (; vlanIDMin <= vlanIDMax ; vlanIDMin++)
- {
- /* change vlan in local membership table */
- ixEthDBLocalVlanMembershipChange(vlanIDMin, table, action);
- }
-
- /* if the range is within one set (max 8 VLANs in one table byte) we can just update that entry in the NPE */
- if (setOffsetMin == setOffsetMax)
- {
- /* send updated entry to NPE */
- return ixEthDBVlanTableEntryUpdate(portID, setOffsetMin);
- }
- else
- {
- /* update a zone of the membership/transmit tag info table */
- return ixEthDBVlanTableRangeUpdate(portID);
- }
-}
-
-/**
- * @brief adds a VLAN range to a port's VLAN membership table
- *
- * @param portID ID of the port
- * @param vlanIDMin start of the VLAN range
- * @param vlanIDMax end of the VLAN range
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanMembershipRangeAdd(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- return ixEthDBPortVlanMembershipRangeChange(portID, vlanIDMin, vlanIDMax, ixEthDBPortInfo[portID].vlanMembership, ADD_VLAN);
-}
-
-/**
- * @brief removes a VLAN range from a port's VLAN membership table
- *
- * @param portID ID of the port
- * @param vlanIDMin start of the VLAN range
- * @param vlanIDMax end of the VLAN range
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanMembershipRangeRemove(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- return ixEthDBPortVlanMembershipRangeChange(portID, vlanIDMin, vlanIDMax, ixEthDBPortInfo[portID].vlanMembership, REMOVE_VLAN);
-}
-
-/**
- * @brief sets a port's VLAN membership table or TTI table and
- * updates the NPE VLAN configuration
- *
- * @param portID ID of the port
- * @param portVlanTable port VLAN table to set
- * @param vlanSet new set contents
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanTableSet(IxEthDBPortId portID, IxEthDBVlanSet portVlanTable, IxEthDBVlanSet vlanSet)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- IX_ETH_DB_CHECK_REFERENCE(vlanSet);
-
- memcpy(portVlanTable, vlanSet, sizeof (IxEthDBVlanSet));
-
- return ixEthDBVlanTableRangeUpdate(portID);
-}
-
-/**
- * @brief retireves a port's VLAN membership table or TTI table
- *
- * @param portID ID of the port
- * @param portVlanTable port VLAN table to retrieve
- * @param vlanSet address to
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBVlanTableGet(IxEthDBPortId portID, IxEthDBVlanSet portVlanTable, IxEthDBVlanSet vlanSet)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- IX_ETH_DB_CHECK_REFERENCE(vlanSet);
-
- memcpy(vlanSet, portVlanTable, sizeof (IxEthDBVlanSet));
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief sets a port's VLAN membership table
- *
- * @param portID ID of the port
- * @param vlanSet new VLAN membership table
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanMembershipSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
-{
- IxEthDBVlanId vlanID;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(vlanSet);
-
- /* set the bit corresponding to the PVID just in case */
- vlanID = IX_ETH_DB_GET_VLAN_ID(ixEthDBPortInfo[portID].vlanTag);
- vlanSet[VLAN_SET_OFFSET(vlanID)] |= 1 << VLAN_SET_MASK(vlanID);
-
- return ixEthDBPortVlanTableSet(portID, ixEthDBPortInfo[portID].vlanMembership, vlanSet);
-}
-
-/**
- * @brief retrieves a port's VLAN membership table
- *
- * @param portID ID of the port
- * @param vlanSet location to store the port's VLAN membership table
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanMembershipGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- return ixEthDBVlanTableGet(portID, ixEthDBPortInfo[portID].vlanMembership, vlanSet);
-}
-
-/**
- * @brief enables or disables Egress tagging for one VLAN ID
- *
- * @param portID ID of the port
- * @param vlanID VLAN ID to enable or disable Egress tagging on
- * @param enabled TRUE to enable and FALSE to disable tagging
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL enabled)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_VLAN_ID(vlanID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- return ixEthDBPortVlanMembershipChange(portID, vlanID, ixEthDBPortInfo[portID].transmitTaggingInfo, enabled? ADD_VLAN : REMOVE_VLAN);
-}
-
-/**
- * @brief retrieves the Egress tagging status for one VLAN ID
- *
- * @param portID ID of the port
- * @param vlanID VLAN ID to retrieve the tagging status for
- * @param enabled location to store the tagging status
- * (TRUE - tagging enabled, FALSE - tagging disabled)
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL *enabled)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- IX_ETH_DB_CHECK_REFERENCE(enabled);
-
- IX_ETH_DB_CHECK_VLAN_ID(vlanID);
-
- *enabled = ((ixEthDBPortInfo[portID].transmitTaggingInfo[VLAN_SET_OFFSET(vlanID)] & (1 << VLAN_SET_MASK(vlanID))) != 0);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief enables or disables Egress VLAN tagging for a VLAN range
- *
- * @param portID ID of the port
- * @param vlanIDMin start of VLAN range
- * @param vlanIDMax end of VLAN range
- * @param enabled TRUE to enable or FALSE to disable VLAN tagging
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBEgressVlanRangeTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax, BOOL enabled)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- return ixEthDBPortVlanMembershipRangeChange(portID, vlanIDMin, vlanIDMax, ixEthDBPortInfo[portID].transmitTaggingInfo, enabled? ADD_VLAN : REMOVE_VLAN);
-}
-
-/**
- * @brief sets the Egress VLAN tagging table (the Transmit Tagging
- * Information table)
- *
- * @param portID ID of the port
- * @param vlanSet new TTI table
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBEgressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
-{
- IxEthDBVlanId vlanID;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(vlanSet);
-
- /* set the PVID bit just in case */
- vlanID = IX_ETH_DB_GET_VLAN_ID(ixEthDBPortInfo[portID].vlanTag);
- vlanSet[VLAN_SET_OFFSET(vlanID)] |= 1 << VLAN_SET_MASK(vlanID);
-
- return ixEthDBPortVlanTableSet(portID, ixEthDBPortInfo[portID].transmitTaggingInfo, vlanSet);
-}
-
-/**
- * @brief retrieves the Egress VLAN tagging table (the Transmit
- * Tagging Information table)
- *
- * @param portID ID of the port
- * @param vlanSet location to store the port's TTI table
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBEgressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- return ixEthDBVlanTableGet(portID, ixEthDBPortInfo[portID].transmitTaggingInfo, vlanSet);
-}
-
-/**
- * @brief sends the NPE the updated frame filter and default
- * Ingress tagging
- *
- * @param portID ID of the port
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBIngressVlanModeUpdate(IxEthDBPortId portID)
-{
- PortInfo *portInfo = &ixEthDBPortInfo[portID];
- IxNpeMhMessage message;
- IX_STATUS result;
-
- FILL_SETRXTAGMODE_MSG(message, portID, portInfo->npeFrameFilter, portInfo->npeTaggingAction);
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- return result;
-}
-
-/**
- * @brief sets the default Ingress tagging behavior
- *
- * @param portID ID of the port
- * @param taggingAction default tagging behavior
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBIngressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBTaggingAction taggingAction)
-{
- PortInfo *portInfo;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- portInfo = &ixEthDBPortInfo[portID];
-
- if (taggingAction == IX_ETH_DB_PASS_THROUGH)
- {
- portInfo->npeTaggingAction = 0x00;
- }
- else if (taggingAction == IX_ETH_DB_ADD_TAG)
- {
- portInfo->npeTaggingAction = 0x02;
- }
- else if (taggingAction == IX_ETH_DB_REMOVE_TAG)
- {
- portInfo->npeTaggingAction = 0x01;
- }
- else
- {
- return IX_ETH_DB_INVALID_ARG;
- }
-
- portInfo->taggingAction = taggingAction;
-
- return ixEthDBIngressVlanModeUpdate(portID);
-}
-
-/**
- * @brief retrieves the default Ingress tagging behavior of a port
- *
- * @param portID ID of the port
- * @param taggingAction location to save the default tagging behavior
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBIngressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBTaggingAction *taggingAction)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- IX_ETH_DB_CHECK_REFERENCE(taggingAction);
-
- *taggingAction = ixEthDBPortInfo[portID].taggingAction;
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief sets the Ingress acceptable frame type filter
- *
- * @param portID ID of the port
- * @param frameFilter acceptable frame type filter
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBAcceptableFrameTypeSet(IxEthDBPortId portID, IxEthDBFrameFilter frameFilter)
-{
- PortInfo *portInfo;
- IxEthDBStatus result = IX_ETH_DB_SUCCESS;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- /* check parameter range
- the ORed value of the valid values is 0x7
- a value having extra bits is invalid */
- if ((frameFilter | 0x7) != 0x7 || frameFilter == 0)
- {
- return IX_ETH_DB_INVALID_ARG;
- }
-
- portInfo = &ixEthDBPortInfo[portID];
-
- portInfo->frameFilter = frameFilter;
- portInfo->npeFrameFilter = 0; /* allow all by default */
-
- /* if accepting priority tagged but not all VLAN tagged
- set the membership table to contain only VLAN ID 0
- hence remove vlans 1-4094 and add VLAN ID 0 */
- if (((frameFilter & IX_ETH_DB_PRIORITY_TAGGED_FRAMES) != 0)
- && ((frameFilter & IX_ETH_DB_VLAN_TAGGED_FRAMES) == 0))
- {
- result = ixEthDBPortVlanMembershipRangeChange(portID,
- 1, IX_ETH_DB_802_1Q_MAX_VLAN_ID, portInfo->vlanMembership, REMOVE_VLAN);
-
- if (result == IX_ETH_DB_SUCCESS)
- {
- ixEthDBLocalVlanMembershipChange(0, portInfo->vlanMembership, ADD_VLAN);
- result = ixEthDBVlanTableRangeUpdate(portID);
- }
- }
-
- /* untagged only? */
- if (frameFilter == IX_ETH_DB_UNTAGGED_FRAMES)
- {
- portInfo->npeFrameFilter = 0x01;
- }
-
- /* tagged only? */
- if ((frameFilter & IX_ETH_DB_UNTAGGED_FRAMES) == 0)
- {
- portInfo->npeFrameFilter = 0x02;
- }
-
- if (result == IX_ETH_DB_SUCCESS)
- {
- result = ixEthDBIngressVlanModeUpdate(portID);
- }
-
- return result;
-}
-
-/**
- * @brief retrieves the acceptable frame type filter for a port
- *
- * @param portID ID of the port
- * @param frameFilter location to store the frame filter
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBAcceptableFrameTypeGet(IxEthDBPortId portID, IxEthDBFrameFilter *frameFilter)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- IX_ETH_DB_CHECK_REFERENCE(frameFilter);
-
- *frameFilter = ixEthDBPortInfo[portID].frameFilter;
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief sends an NPE the updated configuration related
- * to one QoS priority (associated traffic class and AQM mapping)
- *
- * @param portID ID of the port
- * @param classIndex QoS priority (traffic class index)
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBUpdateTrafficClass(IxEthDBPortId portID, UINT32 classIndex)
-{
- IxNpeMhMessage message;
- IX_STATUS result;
-
- UINT32 trafficClass = ixEthDBPortInfo[portID].priorityTable[classIndex];
- UINT32 aqmQueue = ixEthDBPortInfo[portID].ixEthDBTrafficClassAQMAssignments[trafficClass];
-
- FILL_SETRXQOSENTRY(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), classIndex, trafficClass, aqmQueue);
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- return result;
-}
-
-/**
- * @brief sets the priority mapping table
- *
- * @param portID ID of the port
- * @param priorityTable new priority mapping table
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPriorityMappingTableSet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable)
-{
- UINT32 classIndex;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- IX_ETH_DB_CHECK_REFERENCE(priorityTable);
-
- for (classIndex = 0 ; classIndex < IX_IEEE802_1Q_QOS_PRIORITY_COUNT ; classIndex++)
- {
- /* check range */
- if (priorityTable[classIndex] >= ixEthDBPortInfo[portID].ixEthDBTrafficClassCount)
- {
- return IX_ETH_DB_INVALID_PRIORITY;
- }
- }
-
- /* set new traffic classes */
- for (classIndex = 0 ; classIndex < IX_IEEE802_1Q_QOS_PRIORITY_COUNT ; classIndex++)
- {
- ixEthDBPortInfo[portID].priorityTable[classIndex] = priorityTable[classIndex];
-
- if (ixEthDBUpdateTrafficClass(portID, classIndex) != IX_ETH_DB_SUCCESS)
- {
- return IX_ETH_DB_FAIL;
- }
- }
-
- return IX_ETH_DB_SUCCESS;
- }
-
-/**
- * @brief retrieves a port's priority mapping table
- *
- * @param portID ID of the port
- * @param priorityTable location to store the priority table
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPriorityMappingTableGet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- IX_ETH_DB_CHECK_REFERENCE(priorityTable);
-
- memcpy(priorityTable, ixEthDBPortInfo[portID].priorityTable, sizeof (IxEthDBPriorityTable));
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief sets one QoS priority => traffic class mapping
- *
- * @param portID ID of the port
- * @param userPriority QoS (user) priority
- * @param trafficClass associated traffic class
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPriorityMappingClassSet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority trafficClass)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- /* check ranges for userPriority and trafficClass */
- if (userPriority >= IX_IEEE802_1Q_QOS_PRIORITY_COUNT || trafficClass >= ixEthDBPortInfo[portID].ixEthDBTrafficClassCount)
- {
- return IX_ETH_DB_INVALID_PRIORITY;
- }
-
- ixEthDBPortInfo[portID].priorityTable[userPriority] = trafficClass;
-
- return ixEthDBUpdateTrafficClass(portID, userPriority);
-}
-
-/**
- * @brief retrieves one QoS priority => traffic class mapping
- *
- * @param portID ID of the port
- * @param userPriority QoS (user) priority
- * @param trafficClass location to store the associated traffic class
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPriorityMappingClassGet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority *trafficClass)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- IX_ETH_DB_CHECK_REFERENCE(trafficClass);
-
- /* check userPriority range */
- if (userPriority >= IX_IEEE802_1Q_QOS_PRIORITY_COUNT)
- {
- return IX_ETH_DB_INVALID_PRIORITY;
- }
-
- *trafficClass = ixEthDBPortInfo[portID].priorityTable[userPriority];
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief enables or disables the source port extraction
- * from the VLAN TPID field
- *
- * @param portID ID of the port
- * @param enable TRUE to enable or FALSE to disable
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBVlanPortExtractionEnable(IxEthDBPortId portID, BOOL enable)
-{
- IxNpeMhMessage message;
- IX_STATUS result;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- FILL_SETPORTIDEXTRACTIONMODE(message, portID, enable);
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- return result;
-}
+++ /dev/null
-/**
- * @file IxEthDBAPI.c
- *
- * @brief Implementation of the public API
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-
-/* forward prototypes */
-IX_ETH_DB_PUBLIC
-MacTreeNode *ixEthDBGatewaySelect(MacTreeNode *stations);
-
-/**
- * @brief sets the BBSID value for the WiFi header conversion feature
- *
- * @param portID ID of the port
- * @param bbsid pointer to the 6-byte BBSID value
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiBBSIDSet(IxEthDBPortId portID, IxEthDBMacAddr *bbsid)
-{
- IxNpeMhMessage message;
- IX_STATUS result;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION);
-
- IX_ETH_DB_CHECK_REFERENCE(bbsid);
-
- memcpy(ixEthDBPortInfo[portID].bbsid, bbsid, sizeof (IxEthDBMacAddr));
-
- FILL_SETBBSID_MSG(message, portID, bbsid);
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- return result;
-}
-
-/**
- * @brief updates the Frame Control and Duration/ID WiFi header
- * conversion parameters in an NPE
- *
- * @param portID ID of the port
- *
- * This function will send a message to the NPE updating the
- * frame conversion parameters for 802.3 => 802.11 header conversion.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or IX_ETH_DB_FAIL otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBWiFiFrameControlDurationIDUpdate(IxEthDBPortId portID)
-{
- IxNpeMhMessage message;
- IX_STATUS result;
-
- FILL_SETFRAMECONTROLDURATIONID(message, portID, ixEthDBPortInfo[portID].frameControlDurationID);
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- return result;
-}
-
-/**
- * @brief sets the Duration/ID WiFi frame header conversion parameter
- *
- * @param portID ID of the port
- * @param durationID 16-bit value containing the new Duration/ID parameter
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiDurationIDSet(IxEthDBPortId portID, UINT16 durationID)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION);
-
- ixEthDBPortInfo[portID].frameControlDurationID = (ixEthDBPortInfo[portID].frameControlDurationID & 0xFFFF0000) | durationID;
-
- return ixEthDBWiFiFrameControlDurationIDUpdate(portID);
-}
-
-/**
- * @brief sets the Frame Control WiFi frame header conversion parameter
- *
- * @param portID ID of the port
- * @param durationID 16-bit value containing the new Frame Control parameter
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiFrameControlSet(IxEthDBPortId portID, UINT16 frameControl)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION);
-
- ixEthDBPortInfo[portID].frameControlDurationID = (ixEthDBPortInfo[portID].frameControlDurationID & 0xFFFF) | (frameControl << 16);
-
- return ixEthDBWiFiFrameControlDurationIDUpdate(portID);
-}
-
-/**
- * @brief removes a WiFi header conversion record
- *
- * @param portID ID of the port
- * @param macAddr MAC address of the record to remove
- *
- * Note that this function is documented in the main
- * component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
- MacDescriptor recordTemplate;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION);
-
- memcpy(recordTemplate.macAddress, macAddr, sizeof (IxEthDBMacAddr));
-
- recordTemplate.type = IX_ETH_DB_WIFI_RECORD;
- recordTemplate.portID = portID;
-
- return ixEthDBRemove(&recordTemplate, NULL);
-}
-
-/**
- * @brief adds a WiFi header conversion record
- *
- * @param portID ID of the port
- * @param macAddr MAC address of the record to add
- * @param gatewayMacAddr address of the gateway (or
- * NULL if this is a station record)
- *
- * This function adds a record of type AP_TO_AP (gateway is not NULL)
- * or AP_TO_STA (gateway is NULL) in the main database as a
- * WiFi header conversion record.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBWiFiEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr, IxEthDBMacAddr *gatewayMacAddr)
-{
- MacDescriptor recordTemplate;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION);
-
- memcpy(recordTemplate.macAddress, macAddr, sizeof (IxEthDBMacAddr));
-
- recordTemplate.type = IX_ETH_DB_WIFI_RECORD;
- recordTemplate.portID = portID;
-
- if (gatewayMacAddr != NULL)
- {
- memcpy(recordTemplate.recordData.wifiData.gwMacAddress, gatewayMacAddr, sizeof (IxEthDBMacAddr));
-
- recordTemplate.recordData.wifiData.type = IX_ETH_DB_WIFI_AP_TO_AP;
- }
- else
- {
- memset(recordTemplate.recordData.wifiData.gwMacAddress, 0, sizeof (IxEthDBMacAddr));
-
- recordTemplate.recordData.wifiData.type = IX_ETH_DB_WIFI_AP_TO_STA;
- }
-
- return ixEthDBAdd(&recordTemplate, NULL);
-}
-
-/**
- * @brief adds a WiFi header conversion record
- *
- * @param portID ID of the port
- * @param macAddr MAC address of the record to add
- * @param gatewayMacAddr address of the gateway
- *
- * This function adds a record of type AP_TO_AP
- * in the main database as a WiFi header conversion record.
- *
- * This is simply a wrapper over @ref ixEthDBWiFiEntryAdd().
- *
- * Note that this function is documented in the main
- * component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiAccessPointEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr, IxEthDBMacAddr *gatewayMacAddr)
-{
- IX_ETH_DB_CHECK_REFERENCE(gatewayMacAddr);
-
- return ixEthDBWiFiEntryAdd(portID, macAddr, gatewayMacAddr);
-}
-
-/**
- * @brief adds a WiFi header conversion record
- *
- * @param portID ID of the port
- * @param macAddr MAC address of the record to add
- *
- * This function adds a record of type AP_TO_STA
- * in the main database as a WiFi header conversion record.
- *
- * This is simply a wrapper over @ref ixEthDBWiFiEntryAdd().
- *
- * Note that this function is documented in the main
- * component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiStationEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
- return ixEthDBWiFiEntryAdd(portID, macAddr, NULL);
-}
-
-/**
- * @brief selects a set of gateways from a tree of
- * WiFi header conversion records
- *
- * @param stations binary tree containing pointers to WiFi header
- * conversion records
- *
- * This function browses through the input binary tree, identifies
- * records of type AP_TO_AP, clones these records and appends them
- * to a vine (a single right-branch binary tree) which is returned
- * as result. A maximum of MAX_GW_SIZE entries containing gateways
- * will be cloned from the original tree.
- *
- * @return vine (linear binary tree) containing record
- * clones of AP_TO_AP type, which have a gateway field
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-MacTreeNode *ixEthDBGatewaySelect(MacTreeNode *stations)
-{
- MacTreeNodeStack *stack;
- MacTreeNode *gateways, *insertionPlace;
- UINT32 gwIndex = 1; /* skip the empty root */
-
- if (stations == NULL)
- {
- return NULL;
- }
-
- stack = ixOsalCacheDmaMalloc(sizeof (MacTreeNodeStack));
-
- if (stack == NULL)
- {
- ERROR_LOG("DB: (WiFi) failed to allocate the node stack for gateway tree linearization, out of memory?\n");
- return NULL;
- }
-
- /* initialize root node */
- gateways = insertionPlace = NULL;
-
- /* start browsing the station tree */
- NODE_STACK_INIT(stack);
-
- /* initialize stack by pushing the tree root at offset 0 */
- NODE_STACK_PUSH(stack, stations, 0);
-
- while (NODE_STACK_NONEMPTY(stack))
- {
- MacTreeNode *node;
- UINT32 offset;
-
- NODE_STACK_POP(stack, node, offset);
-
- /* we can store maximum 31 (32 total, 1 empty root) entries in the gateway tree */
- if (offset > (MAX_GW_SIZE - 1)) break;
-
- /* check if this record has a gateway address */
- if (node->descriptor != NULL && node->descriptor->recordData.wifiData.type == IX_ETH_DB_WIFI_AP_TO_AP)
- {
- /* found a record, create an insertion place */
- if (insertionPlace != NULL)
- {
- insertionPlace->right = ixEthDBAllocMacTreeNode();
- insertionPlace = insertionPlace->right;
- }
- else
- {
- gateways = ixEthDBAllocMacTreeNode();
- insertionPlace = gateways;
- }
-
- if (insertionPlace == NULL)
- {
- /* no nodes left, bail out with what we have */
- ixOsalCacheDmaFree(stack);
- return gateways;
- }
-
- /* clone the original record for the gateway tree */
- insertionPlace->descriptor = ixEthDBCloneMacDescriptor(node->descriptor);
-
- /* insert and update the offset in the original record */
- node->descriptor->recordData.wifiData.gwAddressIndex = gwIndex++;
- }
-
- /* browse the tree */
- if (node->left != NULL)
- {
- NODE_STACK_PUSH(stack, node->left, LEFT_CHILD_OFFSET(offset));
- }
-
- if (node->right != NULL)
- {
- NODE_STACK_PUSH(stack, node->right, RIGHT_CHILD_OFFSET(offset));
- }
- }
-
- ixOsalCacheDmaFree(stack);
- return gateways;
-}
-
-/**
- * @brief downloads the WiFi header conversion table to an NPE
- *
- * @param portID ID of the port
- *
- * This function prepares the WiFi header conversion tables and
- * downloads them to the specified NPE port.
- *
- * The header conversion tables consist in the main table of
- * addresses and the secondary table of gateways. AP_TO_AP records
- * from the first table contain index fields into the second table
- * for gateway selection.
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiConversionTableDownload(IxEthDBPortId portID)
-{
- IxEthDBPortMap query;
- MacTreeNode *stations = NULL, *gateways = NULL, *gateway = NULL;
- IxNpeMhMessage message;
- PortInfo *portInfo;
- IX_STATUS result;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION);
-
- portInfo = &ixEthDBPortInfo[portID];
-
- SET_DEPENDENCY_MAP(query, portID);
-
- ixEthDBUpdateLock();
-
- stations = ixEthDBQuery(NULL, query, IX_ETH_DB_WIFI_RECORD, MAX_ELT_SIZE);
- gateways = ixEthDBGatewaySelect(stations);
-
- /* clean up gw area */
- memset((void *) portInfo->updateMethod.npeGwUpdateZone, FULL_GW_BYTE_SIZE, 0);
-
- /* write all gateways */
- gateway = gateways;
-
- while (gateway != NULL)
- {
- ixEthDBNPEGatewayNodeWrite((void *) (((UINT32) portInfo->updateMethod.npeGwUpdateZone)
- + gateway->descriptor->recordData.wifiData.gwAddressIndex * ELT_ENTRY_SIZE),
- gateway);
-
- gateway = gateway->right;
- }
-
- /* free the gateway tree */
- if (gateways != NULL)
- {
- ixEthDBFreeMacTreeNode(gateways);
- }
-
- FILL_SETAPMACTABLE_MSG(message,
- IX_OSAL_MMU_VIRT_TO_PHYS(portInfo->updateMethod.npeGwUpdateZone));
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- if (result == IX_SUCCESS)
- {
- /* update the main tree (the stations tree) */
- portInfo->updateMethod.searchTree = stations;
-
- result = ixEthDBNPEUpdateHandler(portID, IX_ETH_DB_WIFI_RECORD);
- }
-
- ixEthDBUpdateUnlock();
-
- return result;
-}
+++ /dev/null
-/**
- * @file IxEthMii.c
- *
- * @author Intel Corporation
- * @date
- *
- * @brief MII control functions
- *
- * Design Notes:
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-
-#include "IxEthAcc.h"
-#include "IxEthMii_p.h"
-
-#ifdef __wince
-#include "IxOsPrintf.h"
-#endif
-
-/* Array to store the phy IDs of the discovered phys */
-PRIVATE UINT32 ixEthMiiPhyId[IXP425_ETH_ACC_MII_MAX_ADDR];
-
-/*********************************************************
- *
- * Scan for PHYs on the MII bus. This function returns
- * an array of booleans, one for each PHY address.
- * If a PHY is found at a particular address, the
- * corresponding entry in the array is set to TRUE.
- *
- */
-
-PUBLIC IX_STATUS
-ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount)
-{
- UINT32 i;
- UINT16 regval, regvalId1, regvalId2;
-
- /*Search for PHYs on the MII*/
- /*Search for existant phys on the MDIO bus*/
-
- if ((phyPresent == NULL) ||
- (maxPhyCount > IXP425_ETH_ACC_MII_MAX_ADDR))
- {
- return IX_FAIL;
- }
-
- /* fill the array */
- for(i=0;
- i<IXP425_ETH_ACC_MII_MAX_ADDR;
- i++)
- {
- phyPresent[i] = FALSE;
- }
-
- /* iterate through the PHY addresses */
- for(i=0;
- maxPhyCount > 0 && i<IXP425_ETH_ACC_MII_MAX_ADDR;
- i++)
- {
- ixEthMiiPhyId[i] = IX_ETH_MII_INVALID_PHY_ID;
- if(ixEthAccMiiReadRtn(i,
- IX_ETH_MII_CTRL_REG,
- ®val) == IX_ETH_ACC_SUCCESS)
- {
- if((regval & 0xffff) != 0xffff)
- {
- maxPhyCount--;
- /*Need to read the register twice here to flush PHY*/
- ixEthAccMiiReadRtn(i, IX_ETH_MII_PHY_ID1_REG, ®valId1);
- ixEthAccMiiReadRtn(i, IX_ETH_MII_PHY_ID1_REG, ®valId1);
- ixEthAccMiiReadRtn(i, IX_ETH_MII_PHY_ID2_REG, ®valId2);
- ixEthMiiPhyId[i] = (regvalId1 << IX_ETH_MII_REG_SHL) | regvalId2;
- if ((ixEthMiiPhyId[i] == IX_ETH_MII_KS8995_PHY_ID)
- || (ixEthMiiPhyId[i] == IX_ETH_MII_LXT971_PHY_ID)
- || (ixEthMiiPhyId[i] == IX_ETH_MII_LXT972_PHY_ID)
- || (ixEthMiiPhyId[i] == IX_ETH_MII_LXT973_PHY_ID)
- || (ixEthMiiPhyId[i] == IX_ETH_MII_LXT973A3_PHY_ID)
- || (ixEthMiiPhyId[i] == IX_ETH_MII_LXT9785_PHY_ID)
- )
- {
- /* supported phy */
- phyPresent[i] = TRUE;
- } /* end of if(ixEthMiiPhyId) */
- else
- {
- if (ixEthMiiPhyId[i] != IX_ETH_MII_INVALID_PHY_ID)
- {
- /* unsupported phy */
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
- IX_OSAL_LOG_DEV_STDOUT,
- "ixEthMiiPhyScan : unexpected Mii PHY ID %8.8x\n",
- ixEthMiiPhyId[i], 2, 3, 4, 5, 6);
- ixEthMiiPhyId[i] = IX_ETH_MII_UNKNOWN_PHY_ID;
- phyPresent[i] = TRUE;
- }
- }
- }
- }
- }
- return IX_SUCCESS;
-}
-
-/************************************************************
- *
- * Configure the PHY at the specified address
- *
- */
-PUBLIC IX_STATUS
-ixEthMiiPhyConfig(UINT32 phyAddr,
- BOOL speed100,
- BOOL fullDuplex,
- BOOL autonegotiate)
-{
- UINT16 regval=0;
-
- /* parameter check */
- if ((phyAddr < IXP425_ETH_ACC_MII_MAX_ADDR) &&
- (ixEthMiiPhyId[phyAddr] != IX_ETH_MII_INVALID_PHY_ID))
- {
- /*
- * set the control register
- */
- if(autonegotiate)
- {
- regval |= IX_ETH_MII_CR_AUTO_EN | IX_ETH_MII_CR_RESTART;
- }
- else
- {
- if(speed100)
- {
- regval |= IX_ETH_MII_CR_100;
- }
- if(fullDuplex)
- {
- regval |= IX_ETH_MII_CR_FDX;
- }
- } /* end of if-else() */
- if (ixEthAccMiiWriteRtn(phyAddr,
- IX_ETH_MII_CTRL_REG,
- regval) == IX_ETH_ACC_SUCCESS)
- {
- return IX_SUCCESS;
- }
- } /* end of if(phyAddr) */
- return IX_FAIL;
-}
-
-/******************************************************************
- *
- * Enable the PHY Loopback at the specified address
- */
-PUBLIC IX_STATUS
-ixEthMiiPhyLoopbackEnable (UINT32 phyAddr)
-{
- UINT16 regval ;
-
- if ((phyAddr < IXP425_ETH_ACC_MII_MAX_ADDR) &&
- (IX_ETH_MII_INVALID_PHY_ID != ixEthMiiPhyId[phyAddr]))
- {
- /* read/write the control register */
- if(ixEthAccMiiReadRtn (phyAddr,
- IX_ETH_MII_CTRL_REG,
- ®val)
- == IX_ETH_ACC_SUCCESS)
- {
- if(ixEthAccMiiWriteRtn (phyAddr,
- IX_ETH_MII_CTRL_REG,
- regval | IX_ETH_MII_CR_LOOPBACK)
- == IX_ETH_ACC_SUCCESS)
- {
- return IX_SUCCESS;
- }
- }
- }
- return IX_FAIL;
-}
-
-/******************************************************************
- *
- * Disable the PHY Loopback at the specified address
- */
-PUBLIC IX_STATUS
-ixEthMiiPhyLoopbackDisable (UINT32 phyAddr)
-{
- UINT16 regval ;
-
- if ((phyAddr < IXP425_ETH_ACC_MII_MAX_ADDR) &&
- (IX_ETH_MII_INVALID_PHY_ID != ixEthMiiPhyId[phyAddr]))
- {
- /* read/write the control register */
- if(ixEthAccMiiReadRtn (phyAddr,
- IX_ETH_MII_CTRL_REG,
- ®val)
- == IX_ETH_ACC_SUCCESS)
- {
- if(ixEthAccMiiWriteRtn (phyAddr,
- IX_ETH_MII_CTRL_REG,
- regval & (~IX_ETH_MII_CR_LOOPBACK))
- == IX_ETH_ACC_SUCCESS)
- {
- return IX_SUCCESS;
- }
- }
- }
- return IX_FAIL;
-}
-
-/******************************************************************
- *
- * Reset the PHY at the specified address
- */
-PUBLIC IX_STATUS
-ixEthMiiPhyReset(UINT32 phyAddr)
-{
- UINT32 timeout;
- UINT16 regval;
-
- if ((phyAddr < IXP425_ETH_ACC_MII_MAX_ADDR) &&
- (ixEthMiiPhyId[phyAddr] != IX_ETH_MII_INVALID_PHY_ID))
- {
- if ((ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT971_PHY_ID) ||
- (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT972_PHY_ID) ||
- (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT973_PHY_ID) ||
- (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT973A3_PHY_ID) ||
- (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT9785_PHY_ID)
- )
- {
- /* use the control register to reset the phy */
- ixEthAccMiiWriteRtn(phyAddr,
- IX_ETH_MII_CTRL_REG,
- IX_ETH_MII_CR_RESET);
-
- /* poll until the reset bit is cleared */
- timeout = 0;
- do
- {
- ixOsalSleep (IX_ETH_MII_RESET_POLL_MS);
-
- /* read the control register and check for timeout */
- ixEthAccMiiReadRtn(phyAddr,
- IX_ETH_MII_CTRL_REG,
- ®val);
- if ((regval & IX_ETH_MII_CR_RESET) == 0)
- {
- /* timeout bit is self-cleared */
- break;
- }
- timeout += IX_ETH_MII_RESET_POLL_MS;
- }
- while (timeout < IX_ETH_MII_RESET_DELAY_MS);
-
- /* check for timeout */
- if (timeout >= IX_ETH_MII_RESET_DELAY_MS)
- {
- ixEthAccMiiWriteRtn(phyAddr, IX_ETH_MII_CTRL_REG,
- IX_ETH_MII_CR_NORM_EN);
- return IX_FAIL;
- }
-
- return IX_SUCCESS;
- } /* end of if(ixEthMiiPhyId) */
- else if (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_KS8995_PHY_ID)
- {
- /* reset bit is reserved, just reset the control register */
- ixEthAccMiiWriteRtn(phyAddr, IX_ETH_MII_CTRL_REG,
- IX_ETH_MII_CR_NORM_EN);
- return IX_SUCCESS;
- }
- else
- {
- /* unknown PHY, set the control register reset bit,
- * wait 2 s. and clear the control register.
- */
- ixEthAccMiiWriteRtn(phyAddr, IX_ETH_MII_CTRL_REG,
- IX_ETH_MII_CR_RESET);
-
- ixOsalSleep (IX_ETH_MII_RESET_DELAY_MS);
-
- ixEthAccMiiWriteRtn(phyAddr, IX_ETH_MII_CTRL_REG,
- IX_ETH_MII_CR_NORM_EN);
- return IX_SUCCESS;
- } /* end of if-else(ixEthMiiPhyId) */
- } /* end of if(phyAddr) */
- return IX_FAIL;
-}
-
-/*****************************************************************
- *
- * Link state query functions
- */
-
-PUBLIC IX_STATUS
-ixEthMiiLinkStatus(UINT32 phyAddr,
- BOOL *linkUp,
- BOOL *speed100,
- BOOL *fullDuplex,
- BOOL *autoneg)
-{
- UINT16 ctrlRegval, statRegval, regval, regval4, regval5;
-
- /* check the parameters */
- if ((linkUp == NULL) ||
- (speed100 == NULL) ||
- (fullDuplex == NULL) ||
- (autoneg == NULL))
- {
- return IX_FAIL;
- }
-
- *linkUp = FALSE;
- *speed100 = FALSE;
- *fullDuplex = FALSE;
- *autoneg = FALSE;
-
- if ((phyAddr < IXP425_ETH_ACC_MII_MAX_ADDR) &&
- (ixEthMiiPhyId[phyAddr] != IX_ETH_MII_INVALID_PHY_ID))
- {
- if ((ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT971_PHY_ID) ||
- (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT972_PHY_ID) ||
- (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT9785_PHY_ID)
- )
- {
- /* --------------------------------------------------*/
- /* Retrieve information from PHY specific register */
- /* --------------------------------------------------*/
- if (ixEthAccMiiReadRtn(phyAddr,
- IX_ETH_MII_STAT2_REG,
- ®val) != IX_ETH_ACC_SUCCESS)
- {
- return IX_FAIL;
- }
- *linkUp = ((regval & IX_ETH_MII_SR2_LINK) != 0);
- *speed100 = ((regval & IX_ETH_MII_SR2_100) != 0);
- *fullDuplex = ((regval & IX_ETH_MII_SR2_FD) != 0);
- *autoneg = ((regval & IX_ETH_MII_SR2_AUTO) != 0);
- return IX_SUCCESS;
- } /* end of if(ixEthMiiPhyId) */
- else
- {
- /* ----------------------------------------------------*/
- /* Retrieve information from status and ctrl registers */
- /* ----------------------------------------------------*/
- if (ixEthAccMiiReadRtn(phyAddr,
- IX_ETH_MII_CTRL_REG,
- &ctrlRegval) != IX_ETH_ACC_SUCCESS)
- {
- return IX_FAIL;
- }
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_STAT_REG, &statRegval);
-
- *linkUp = ((statRegval & IX_ETH_MII_SR_LINK_STATUS) != 0);
- if (*linkUp)
- {
- *autoneg = ((ctrlRegval & IX_ETH_MII_CR_AUTO_EN) != 0) &&
- ((statRegval & IX_ETH_MII_SR_AUTO_SEL) != 0) &&
- ((statRegval & IX_ETH_MII_SR_AUTO_NEG) != 0);
-
- if (*autoneg)
- {
- /* mask the current stat values with the capabilities */
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_AN_ADS_REG, ®val4);
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_AN_PRTN_REG, ®val5);
- /* merge the flags from the 3 registers */
- regval = (statRegval & ((regval4 & regval5) << 6));
- /* initialise from status register values */
- if ((regval & IX_ETH_MII_SR_TX_FULL_DPX) != 0)
- {
- /* 100 Base X full dplx */
- *speed100 = TRUE;
- *fullDuplex = TRUE;
- return IX_SUCCESS;
- }
- if ((regval & IX_ETH_MII_SR_TX_HALF_DPX) != 0)
- {
- /* 100 Base X half dplx */
- *speed100 = TRUE;
- return IX_SUCCESS;
- }
- if ((regval & IX_ETH_MII_SR_10T_FULL_DPX) != 0)
- {
- /* 10 mb full dplx */
- *fullDuplex = TRUE;
- return IX_SUCCESS;
- }
- if ((regval & IX_ETH_MII_SR_10T_HALF_DPX) != 0)
- {
- /* 10 mb half dplx */
- return IX_SUCCESS;
- }
- } /* end of if(autoneg) */
- else
- {
- /* autonegotiate not complete, return setup parameters */
- *speed100 = ((ctrlRegval & IX_ETH_MII_CR_100) != 0);
- *fullDuplex = ((ctrlRegval & IX_ETH_MII_CR_FDX) != 0);
- }
- } /* end of if(linkUp) */
- } /* end of if-else(ixEthMiiPhyId) */
- } /* end of if(phyAddr) */
- else
- {
- return IX_FAIL;
- } /* end of if-else(phyAddr) */
- return IX_SUCCESS;
-}
-
-/*****************************************************************
- *
- * Link state display functions
- */
-
-PUBLIC IX_STATUS
-ixEthMiiPhyShow (UINT32 phyAddr)
-{
- BOOL linkUp, speed100, fullDuplex, autoneg;
- UINT16 cregval;
- UINT16 sregval;
-
-
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_STAT_REG, &sregval);
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_CTRL_REG, &cregval);
-
- /* get link information */
- if (ixEthMiiLinkStatus(phyAddr,
- &linkUp,
- &speed100,
- &fullDuplex,
- &autoneg) != IX_ETH_ACC_SUCCESS)
- {
- printf("PHY Status unknown\n");
- return IX_FAIL;
- }
-
- printf("PHY ID [phyAddr]: %8.8x\n",ixEthMiiPhyId[phyAddr]);
- printf( " Status reg: %4.4x\n",sregval);
- printf( " control reg: %4.4x\n",cregval);
- /* display link information */
- printf("PHY Status:\n");
- printf(" Link is %s\n",
- (linkUp ? "Up" : "Down"));
- if((sregval & IX_ETH_MII_SR_REMOTE_FAULT) != 0)
- {
- printf(" Remote fault detected\n");
- }
- printf(" Auto Negotiation %s\n",
- (autoneg ? "Completed" : "Not Completed"));
-
- printf("PHY Configuration:\n");
- printf(" Speed %sMb/s\n",
- (speed100 ? "100" : "10"));
- printf(" %s Duplex\n",
- (fullDuplex ? "Full" : "Half"));
- printf(" Auto Negotiation %s\n",
- (autoneg ? "Enabled" : "Disabled"));
- return IX_SUCCESS;
-}
-
+++ /dev/null
-/**
- * @file IxFeatureCtrl.c
- *
- * @author Intel Corporation
- * @date 29-Jan-2003
- *
- * @brief Feature Control Public API Implementation
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-#include "IxOsal.h"
-#include "IxVersionId.h"
-#include "IxFeatureCtrl.h"
-
-/* Macro to read from the Feature Control Register */
-#define IX_FEATURE_CTRL_READ(result) \
-do { \
-ixFeatureCtrlExpMap(); \
-(result) = IX_OSAL_READ_LONG(ixFeatureCtrlRegister); \
-} while (0)
-
-/* Macro to write to the Feature Control Register */
-#define IX_FEATURE_CTRL_WRITE(value) \
-do { \
-ixFeatureCtrlExpMap(); \
-IX_OSAL_WRITE_LONG(ixFeatureCtrlRegister, (value)); \
-} while (0)
-
-/*
- * This is the offset of the feature register relative to the base of the
- * Expansion Bus Controller MMR.
- */
-#define IX_FEATURE_CTRL_REG_OFFSET (0x00000028)
-
-
-/* Boolean to mark the fact that the EXP_CONFIG address space was mapped */
-PRIVATE BOOL ixFeatureCtrlExpCfgRegionMapped = FALSE;
-
-/* Pointer holding the virtual address of the Feature Control Register */
-PRIVATE VUINT32 *ixFeatureCtrlRegister = NULL;
-
-/* Place holder to store the software configuration */
-PRIVATE BOOL swConfiguration[IX_FEATURECTRL_SWCONFIG_MAX];
-
-/* Flag to control swConfiguration[] is initialized once */
-PRIVATE BOOL swConfigurationFlag = FALSE ;
-
-/* Array containing component mask values */
-#ifdef __ixp42X
-UINT32 componentMask[IX_FEATURECTRL_MAX_COMPONENTS] = {
- (0x1<<IX_FEATURECTRL_RCOMP),
- (0x1<<IX_FEATURECTRL_USB),
- (0x1<<IX_FEATURECTRL_HASH),
- (0x1<<IX_FEATURECTRL_AES),
- (0x1<<IX_FEATURECTRL_DES),
- (0x1<<IX_FEATURECTRL_HDLC),
- (0x1<<IX_FEATURECTRL_AAL),
- (0x1<<IX_FEATURECTRL_HSS),
- (0x1<<IX_FEATURECTRL_UTOPIA),
- (0x1<<IX_FEATURECTRL_ETH0),
- (0x1<<IX_FEATURECTRL_ETH1),
- (0x1<<IX_FEATURECTRL_NPEA),
- (0x1<<IX_FEATURECTRL_NPEB),
- (0x1<<IX_FEATURECTRL_NPEC),
- (0x1<<IX_FEATURECTRL_PCI),
- IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE,
- (0x3<<IX_FEATURECTRL_UTOPIA_PHY_LIMIT),
- (0x1<<IX_FEATURECTRL_UTOPIA_PHY_LIMIT_BIT2),
- IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE,
- IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE,
- IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE,
- IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE,
- IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE
-};
-#elif defined (__ixp46X)
-UINT32 componentMask[IX_FEATURECTRL_MAX_COMPONENTS] = {
- (0x1<<IX_FEATURECTRL_RCOMP),
- (0x1<<IX_FEATURECTRL_USB),
- (0x1<<IX_FEATURECTRL_HASH),
- (0x1<<IX_FEATURECTRL_AES),
- (0x1<<IX_FEATURECTRL_DES),
- (0x1<<IX_FEATURECTRL_HDLC),
- IX_FEATURECTRL_COMPONENT_ALWAYS_AVAILABLE, /* AAL component is always on */
- (0x1<<IX_FEATURECTRL_HSS),
- (0x1<<IX_FEATURECTRL_UTOPIA),
- (0x1<<IX_FEATURECTRL_ETH0),
- (0x1<<IX_FEATURECTRL_ETH1),
- (0x1<<IX_FEATURECTRL_NPEA),
- (0x1<<IX_FEATURECTRL_NPEB),
- (0x1<<IX_FEATURECTRL_NPEC),
- (0x1<<IX_FEATURECTRL_PCI),
- (0x1<<IX_FEATURECTRL_ECC_TIMESYNC),
- (0x3<<IX_FEATURECTRL_UTOPIA_PHY_LIMIT),
- (0x1<<IX_FEATURECTRL_UTOPIA_PHY_LIMIT_BIT2), /* NOT TO BE USED */
- (0x1<<IX_FEATURECTRL_USB_HOST_CONTROLLER),
- (0x1<<IX_FEATURECTRL_NPEA_ETH),
- (0x1<<IX_FEATURECTRL_NPEB_ETH),
- (0x1<<IX_FEATURECTRL_RSA),
- (0x3<<IX_FEATURECTRL_XSCALE_MAX_FREQ),
- (0x1<<IX_FEATURECTRL_XSCALE_MAX_FREQ_BIT2)
-};
-#endif /* __ixp42X */
-
-/**
- * Forward declaration
- */
-PRIVATE
-void ixFeatureCtrlExpMap(void);
-
-PRIVATE
-void ixFeatureCtrlSwConfigurationInit(void);
-
-/**
- * Function to map EXP_CONFIG space
- */
-PRIVATE
-void ixFeatureCtrlExpMap(void)
-{
- UINT32 expCfgBaseAddress = 0;
-
- /* If the EXP Configuration space has already been mapped then
- * return */
- if (ixFeatureCtrlExpCfgRegionMapped == TRUE)
- {
- return;
- }
-
- /* Map (get virtual address) for the EXP_CONFIG space */
- expCfgBaseAddress = (UINT32)
- (IX_OSAL_MEM_MAP(IX_OSAL_IXP400_EXP_BUS_REGS_PHYS_BASE,
- IX_OSAL_IXP400_EXP_REG_MAP_SIZE));
-
- /* Assert that the mapping operation succeeded */
- IX_OSAL_ASSERT(expCfgBaseAddress);
-
- /* Set the address of the Feature register */
- ixFeatureCtrlRegister =
- (VUINT32 *) (expCfgBaseAddress + IX_FEATURE_CTRL_REG_OFFSET);
-
- /* Mark the fact that the EXP_CONFIG space has already been mapped */
- ixFeatureCtrlExpCfgRegionMapped = TRUE;
-}
-
-/**
- * Function definition: ixFeatureCtrlSwConfigurationInit
- * This function will only initialize software configuration once.
- */
-PRIVATE void ixFeatureCtrlSwConfigurationInit(void)
-{
- UINT32 i;
- if (FALSE == swConfigurationFlag)
- {
- for (i=0; i<IX_FEATURECTRL_SWCONFIG_MAX ; i++)
- {
- /* By default, all software configuration are enabled */
- swConfiguration[i]= TRUE ;
- }
- /*Make sure this function only initializes swConfiguration[] once*/
- swConfigurationFlag = TRUE ;
- }
-}
-
-/**
- * Function definition: ixFeatureCtrlRead
- */
-IxFeatureCtrlReg
-ixFeatureCtrlRead (void)
-{
- IxFeatureCtrlReg result;
-
-#if CPU!=SIMSPARCSOLARIS
- /* Read the feature control register */
- IX_FEATURE_CTRL_READ(result);
- return result;
-#else
- /* Return an invalid value for VxWorks simulation */
- result = 0xFFFFFFFF;
- return result;
-#endif
-}
-
-/**
- * Function definition: ixFeatureCtrlWrite
- */
-void
-ixFeatureCtrlWrite (IxFeatureCtrlReg expUnitReg)
-{
-#if CPU!=SIMSPARCSOLARIS
- /* Write value to feature control register */
- IX_FEATURE_CTRL_WRITE(expUnitReg);
-#endif
-}
-
-
-/**
- * Function definition: ixFeatureCtrlHwCapabilityRead
- */
-IxFeatureCtrlReg
-ixFeatureCtrlHwCapabilityRead (void)
-{
- IxFeatureCtrlReg currentReg, hwCapability;
-
- /* Capture a copy of feature control register */
- currentReg = ixFeatureCtrlRead();
-
- /* Try to enable all hardware components.
- * Only software disable hardware can be enabled again */
- ixFeatureCtrlWrite(0);
-
- /* Read feature control register to know the hardware capability. */
- hwCapability = ixFeatureCtrlRead();
-
- /* Restore initial feature control value */
- ixFeatureCtrlWrite(currentReg);
-
- /* return Hardware Capability */
- return hwCapability;
-}
-
-
-/**
- * Function definition: ixFeatureCtrlComponentCheck
- */
-IX_STATUS
-ixFeatureCtrlComponentCheck (IxFeatureCtrlComponentType componentType)
-{
- IxFeatureCtrlReg expUnitReg;
- UINT32 mask = 0;
-
- /* Lookup mask of component */
- mask=componentMask[componentType];
-
- /* Check if mask is available or not */
- if(IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE == mask)
- {
- return IX_FEATURE_CTRL_COMPONENT_DISABLED;
- }
-
- if(IX_FEATURECTRL_COMPONENT_ALWAYS_AVAILABLE == mask)
- {
- return IX_FEATURE_CTRL_COMPONENT_ENABLED;
- }
-
- /* Read feature control register to know current hardware capability. */
- expUnitReg = ixFeatureCtrlRead();
-
- /* For example: To check for Hashing Coprocessor (bit-2)
- * expUniteg = 0x0010
- * ~expUnitReg = 0x1101
- * componentType = 0x0100
- * ~expUnitReg & componentType = 0x0100 (Not zero)
- */
-
- /*
- * Inverse the bit value because available component is 0 in value
- */
- expUnitReg = ~expUnitReg ;
-
- if (expUnitReg & mask)
- {
- return (IX_FEATURE_CTRL_COMPONENT_ENABLED);
- }
- else
- {
- return (IX_FEATURE_CTRL_COMPONENT_DISABLED);
- }
-}
-
-
-/**
- * Function definition: ixFeatureCtrlProductIdRead
- */
-IxFeatureCtrlProductId
-ixFeatureCtrlProductIdRead ()
-{
-#if CPU!=SIMSPARCSOLARIS
- IxFeatureCtrlProductId pdId = 0 ;
-
- /* Use ARM instruction to move register0 from coprocessor to ARM register */
-
-#ifndef __wince
- __asm__("mrc p15, 0, %0, cr0, cr0, 0;" : "=r"(pdId) :);
-#else
-
-#ifndef IN_KERNEL
- BOOL mode;
-#endif
- extern IxFeatureCtrlProductId AsmixFeatureCtrlProductIdRead();
-
-#ifndef IN_KERNEL
- mode = SetKMode(TRUE);
-#endif
- pdId = AsmixFeatureCtrlProductIdRead();
-#ifndef IN_KERNEL
- SetKMode(mode);
-#endif
-
-#endif
- return (pdId);
-#else
- /* Return an invalid value for VxWorks simulation */
- return 0xffffffff;
-#endif
-}
-
-/**
- * Function definition: ixFeatureCtrlDeviceRead
- */
-IxFeatureCtrlDeviceId
-ixFeatureCtrlDeviceRead ()
-{
- return ((ixFeatureCtrlProductIdRead() >> IX_FEATURE_CTRL_DEVICE_TYPE_OFFSET)
- & IX_FEATURE_CTRL_DEVICE_TYPE_MASK);
-} /* End function ixFeatureCtrlDeviceRead */
-
-
-/**
- * Function definition: ixFeatureCtrlSwConfigurationCheck
- */
-IX_STATUS
-ixFeatureCtrlSwConfigurationCheck (IxFeatureCtrlSwConfig swConfigType)
-{
- if (swConfigType >= IX_FEATURECTRL_SWCONFIG_MAX)
- {
- ixOsalLog(IX_OSAL_LOG_LVL_WARNING,
- IX_OSAL_LOG_DEV_STDOUT,
- "FeatureCtrl: Invalid software configuraiton input.\n",
- 0, 0, 0, 0, 0, 0);
-
- return IX_FEATURE_CTRL_SWCONFIG_DISABLED;
- }
-
- /* The function will only initialize once. */
- ixFeatureCtrlSwConfigurationInit();
-
- /* Check and return software configuration */
- return ((swConfiguration[(UINT32)swConfigType] == TRUE) ? IX_FEATURE_CTRL_SWCONFIG_ENABLED: IX_FEATURE_CTRL_SWCONFIG_DISABLED);
-}
-
-/**
- * Function definition: ixFeatureCtrlSwConfigurationWrite
- */
-void
-ixFeatureCtrlSwConfigurationWrite (IxFeatureCtrlSwConfig swConfigType, BOOL enabled)
-{
- if (swConfigType >= IX_FEATURECTRL_SWCONFIG_MAX)
- {
- ixOsalLog(IX_OSAL_LOG_LVL_WARNING,
- IX_OSAL_LOG_DEV_STDOUT,
- "FeatureCtrl: Invalid software configuraiton input.\n",
- 0, 0, 0, 0, 0, 0);
-
- return;
- }
-
- /* The function will only initialize once. */
- ixFeatureCtrlSwConfigurationInit();
-
- /* Write software configuration */
- swConfiguration[(UINT32)swConfigType]=enabled ;
-}
-
-/**
- * Function definition: ixFeatureCtrlIxp400SwVersionShow
- */
-void
-ixFeatureCtrlIxp400SwVersionShow (void)
-{
- printf ("\nIXP400 Software Release %s %s\n\n", IX_VERSION_ID, IX_VERSION_INTERNAL_ID);
-
-}
-
-/**
- * Function definition: ixFeatureCtrlSoftwareBuildGet
- */
-IxFeatureCtrlBuildDevice
-ixFeatureCtrlSoftwareBuildGet (void)
-{
- #ifdef __ixp42X
- return IX_FEATURE_CTRL_SW_BUILD_IXP42X;
- #else
- return IX_FEATURE_CTRL_SW_BUILD_IXP46X;
- #endif
-}
+++ /dev/null
-/**
- * @file IxNpeDl.c
- *
- * @author Intel Corporation
- * @date 08 January 2002
- *
- * @brief This file contains the implementation of the public API for the
- * IXP425 NPE Downloader component
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * Put the system defined include files required
- */
-
-/*
- * Put the user defined include files required
- */
-#include "IxNpeDl.h"
-#include "IxNpeDlImageMgr_p.h"
-#include "IxNpeDlNpeMgr_p.h"
-#include "IxNpeDlMacros_p.h"
-#include "IxFeatureCtrl.h"
-#include "IxOsal.h"
-/*
- * #defines used in this file
- */
- #define IMAGEID_MAJOR_NUMBER_DEFAULT 0
- #define IMAGEID_MINOR_NUMBER_DEFAULT 0
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-typedef struct
-{
- BOOL validImage;
- IxNpeDlImageId imageId;
-} IxNpeDlNpeState;
-
-/* module statistics counters */
-typedef struct
-{
- UINT32 attemptedDownloads;
- UINT32 successfulDownloads;
- UINT32 criticalFailDownloads;
-} IxNpeDlStats;
-
-/*
- * Variable declarations global to this file only. Externs are followed
- * by static variables.
- */
-static IxNpeDlNpeState ixNpeDlNpeState[IX_NPEDL_NPEID_MAX] =
-{
- {FALSE, {IX_NPEDL_NPEID_MAX, 0, 0, 0}},
- {FALSE, {IX_NPEDL_NPEID_MAX, 0, 0, 0}},
- {FALSE, {IX_NPEDL_NPEID_MAX, 0, 0, 0}}
-};
-
-static IxNpeDlStats ixNpeDlStats;
-
-/*
- * Software guard to prevent NPE from being started multiple times.
- */
-static BOOL ixNpeDlNpeStarted[IX_NPEDL_NPEID_MAX] ={FALSE, FALSE, FALSE} ;
-
-
-/*
- * static function prototypes.
- */
-PRIVATE IX_STATUS
-ixNpeDlNpeInitAndStartInternal (UINT32 *imageLibrary, UINT32 imageId);
-
-/*
- * Function definition: ixNpeDlImageDownload
- */
-PUBLIC IX_STATUS
-ixNpeDlImageDownload (IxNpeDlImageId *imageIdPtr,
- BOOL verify)
-{
- UINT32 imageSize;
- UINT32 *imageCodePtr = NULL;
- IX_STATUS status;
- IxNpeDlNpeId npeId = imageIdPtr->npeId;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlImageDownload\n");
-
- ixNpeDlStats.attemptedDownloads++;
-
- /* Check input parameters */
- if ((npeId >= IX_NPEDL_NPEID_MAX) || (npeId < 0))
- {
- status = IX_NPEDL_PARAM_ERR;
- IX_NPEDL_ERROR_REPORT ("ixNpeDlImageDownload - invalid parameter\n");
- }
- else
- {
- /* Ensure initialisation has been completed */
- ixNpeDlNpeMgrInit();
-
- /* If not IXP42X A0 stepping, proceed to check for existence of npe's */
- if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
- (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
- || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
- {
- if (npeId == IX_NPEDL_NPEID_NPEA)
- {
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED)
- {
- IX_NPEDL_WARNING_REPORT("Warning: the NPE A component you specified does"
- " not exist\n");
- return IX_SUCCESS;
- }
- } /* end of if(npeId) */
- else if (npeId == IX_NPEDL_NPEID_NPEB)
- {
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)==
- IX_FEATURE_CTRL_COMPONENT_DISABLED)
- {
- IX_NPEDL_WARNING_REPORT("Warning: the NPE B component you specified"
- " does not exist\n");
- return IX_SUCCESS;
- }
- } /* end of elseif(npeId) */
- else if (npeId == IX_NPEDL_NPEID_NPEC)
- {
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)==
- IX_FEATURE_CTRL_COMPONENT_DISABLED)
- {
- IX_NPEDL_WARNING_REPORT("Warning: the NPE C component you specified"
- " does not exist\n");
- return IX_SUCCESS;
- }
- } /* end of elseif(npeId) */
- } /* end of if(IX_FEATURE_CTRL_SILICON_TYPE_B0) */ /*End of Silicon Type Check*/
-
- /* stop and reset the NPE */
- if (IX_SUCCESS != ixNpeDlNpeStopAndReset (npeId))
- {
- IX_NPEDL_ERROR_REPORT ("Failed to stop and reset NPE\n");
- return IX_FAIL;
- }
-
- /* Locate image */
- status = ixNpeDlImageMgrImageLocate (imageIdPtr, &imageCodePtr,
- &imageSize);
- if (IX_SUCCESS == status)
- {
- /*
- * If download was successful, store image Id in list of
- * currently loaded images. If a critical error occured
- * during download, record that the NPE has an invalid image
- */
- status = ixNpeDlNpeMgrImageLoad (npeId, imageCodePtr,
- verify);
- if (IX_SUCCESS == status)
- {
- ixNpeDlNpeState[npeId].imageId = *imageIdPtr;
- ixNpeDlNpeState[npeId].validImage = TRUE;
- ixNpeDlStats.successfulDownloads++;
-
- status = ixNpeDlNpeExecutionStart (npeId);
- }
- else if ((status == IX_NPEDL_CRITICAL_NPE_ERR) ||
- (status == IX_NPEDL_CRITICAL_MICROCODE_ERR))
- {
- ixNpeDlNpeState[npeId].imageId = *imageIdPtr;
- ixNpeDlNpeState[npeId].validImage = FALSE;
- ixNpeDlStats.criticalFailDownloads++;
- }
- } /* end of if(IX_SUCCESS) */ /* condition: image located successfully in microcode image */
- } /* end of if-else(npeId) */ /* condition: parameter checks ok */
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlImageDownload : status = %d\n", status);
- return status;
-}
-
-/*
- * Function definition: ixNpeDlAvailableImagesCountGet
- */
-PUBLIC IX_STATUS
-ixNpeDlAvailableImagesCountGet (UINT32 *numImagesPtr)
-{
- IX_STATUS status;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlAvailableImagesCountGet\n");
-
- /* Check input parameters */
- if (numImagesPtr == NULL)
- {
- status = IX_NPEDL_PARAM_ERR;
- IX_NPEDL_ERROR_REPORT ("ixNpeDlAvailableImagesCountGet - "
- "invalid parameter\n");
- }
- else
- {
- /*
- * Use ImageMgr module to get no. of images listed in Image Library Header.
- * If NULL is passed as imageListPtr parameter to following function,
- * it will only fill number of images into numImagesPtr
- */
- status = ixNpeDlImageMgrImageListExtract (NULL, numImagesPtr);
- } /* end of if-else(numImagesPtr) */
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlAvailableImagesCountGet : "
- "status = %d\n", status);
- return status;
-}
-
-/*
- * Function definition: ixNpeDlAvailableImagesListGet
- */
-PUBLIC IX_STATUS
-ixNpeDlAvailableImagesListGet (IxNpeDlImageId *imageIdListPtr,
- UINT32 *listSizePtr)
-{
- IX_STATUS status;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlAvailableImagesListGet\n");
-
- /* Check input parameters */
- if ((imageIdListPtr == NULL) || (listSizePtr == NULL))
- {
- status = IX_NPEDL_PARAM_ERR;
- IX_NPEDL_ERROR_REPORT ("ixNpeDlAvailableImagesListGet - "
- "invalid parameter\n");
- }
- else
- {
- /* Call ImageMgr to get list of images listed in Image Library Header */
- status = ixNpeDlImageMgrImageListExtract (imageIdListPtr,
- listSizePtr);
- } /* end of if-else(imageIdListPtr) */
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlAvailableImagesListGet : status = %d\n",
- status);
- return status;
-}
-
-/*
- * Function definition: ixNpeDlLoadedImageGet
- */
-PUBLIC IX_STATUS
-ixNpeDlLoadedImageGet (IxNpeDlNpeId npeId,
- IxNpeDlImageId *imageIdPtr)
-{
- IX_STATUS status = IX_SUCCESS;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlLoadedImageGet\n");
-
- /* Check input parameters */
- if ((npeId >= IX_NPEDL_NPEID_MAX) || (npeId < 0) || (imageIdPtr == NULL))
- {
- status = IX_NPEDL_PARAM_ERR;
- IX_NPEDL_ERROR_REPORT ("ixNpeDlLoadedImageGet - invalid parameter\n");
- }
- else
- {
-
- /* If not IXP42X A0 stepping, proceed to check for existence of npe's */
- if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
- (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
- || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
- {
- if (npeId == IX_NPEDL_NPEID_NPEA &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED))
- {
- IX_NPEDL_WARNING_REPORT("Warning: the NPE A component you specified does"
- " not exist\n");
- return IX_SUCCESS;
- } /* end of if(npeId) */
-
- if (npeId == IX_NPEDL_NPEID_NPEB &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED))
- {
- IX_NPEDL_WARNING_REPORT("Warning: the NPE B component you specified does"
- " not exist\n");
- return IX_SUCCESS;
- } /* end of if(npeId) */
-
- if (npeId == IX_NPEDL_NPEID_NPEC &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED))
- {
- IX_NPEDL_WARNING_REPORT("Warning: the NPE C component you specified does"
- " not exist\n");
- return IX_SUCCESS;
- } /* end of if(npeId) */
- } /* end of if not IXP42x-A0 silicon */
-
- if (ixNpeDlNpeState[npeId].validImage)
- {
- /* use npeId to get imageId from list of currently loaded
- images */
- *imageIdPtr = ixNpeDlNpeState[npeId].imageId;
- }
- else
- {
- status = IX_FAIL;
- } /* end of if-else(ixNpeDlNpeState) */
- } /* end of if-else(npeId) */
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlLoadedImageGet : status = %d\n",
- status);
- return status;
-}
-
-/*
- * Function definition: ixNpeDlLatestImageGet
- */
-PUBLIC IX_STATUS
-ixNpeDlLatestImageGet (
- IxNpeDlNpeId npeId,
- IxNpeDlFunctionalityId functionalityId,
- IxNpeDlImageId *imageIdPtr)
-{
- IX_STATUS status;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlLatestImageGet\n");
-
- /* Check input parameters */
- if ((npeId >= IX_NPEDL_NPEID_MAX) ||
- (npeId < 0) ||
- (imageIdPtr == NULL))
- {
- status = IX_NPEDL_PARAM_ERR;
- IX_NPEDL_ERROR_REPORT ("ixNpeDlLatestImageGet - "
- "invalid parameter\n");
- } /* end of if(npeId) */
- else
- {
-
- /* If not IXP42X A0 stepping, proceed to check for existence of npe's */
- if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
- (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
- || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
- {
- if (npeId == IX_NPEDL_NPEID_NPEA &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED))
- {
- IX_NPEDL_WARNING_REPORT("Warning: the NPE A component you specified does"
- " not exist\n");
- return IX_SUCCESS;
- } /* end of if(npeId) */
-
- if (npeId == IX_NPEDL_NPEID_NPEB &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED))
- {
- IX_NPEDL_WARNING_REPORT("Warning: the NPE B component you specified does"
- " not exist\n");
- return IX_SUCCESS;
- } /* end of if(npeId) */
-
- if (npeId == IX_NPEDL_NPEID_NPEC &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED))
- {
- IX_NPEDL_WARNING_REPORT("Warning: the NPE C component you specified does"
- " not exist\n");
- return IX_SUCCESS;
- } /* end of if(npeId) */
- } /* end of if not IXP42x-A0 silicon */
-
- imageIdPtr->npeId = npeId;
- imageIdPtr->functionalityId = functionalityId;
- imageIdPtr->major = IMAGEID_MAJOR_NUMBER_DEFAULT;
- imageIdPtr->minor = IMAGEID_MINOR_NUMBER_DEFAULT;
- /* Call ImageMgr to get list of images listed in Image Library Header */
- status = ixNpeDlImageMgrLatestImageExtract(imageIdPtr);
- } /* end of if-else(npeId) */
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlLatestImageGet : status = %d\n",
- status);
-
- return status;
-}
-
-/*
- * Function definition: ixNpeDlNpeStopAndReset
- */
-PUBLIC IX_STATUS
-ixNpeDlNpeStopAndReset (IxNpeDlNpeId npeId)
-{
- IX_STATUS status = IX_SUCCESS;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlNpeStopAndReset\n");
-
- /* Ensure initialisation has been completed */
- ixNpeDlNpeMgrInit();
-
- /* If not IXP42X A0 stepping, proceed to check for existence of npe's */
- if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
- (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
- || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
- {
- /*
- * Check whether NPE is present
- */
- if (IX_NPEDL_NPEID_NPEA == npeId)
- {
- /* Check whether NPE A is present */
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA)==
- IX_FEATURE_CTRL_COMPONENT_DISABLED)
- {
- /* NPE A does not present */
- IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeStopAndReset - Warning:NPEA does not present.\n");
- return IX_SUCCESS;
- }
- } /* end of if(IX_NPEDL_NPEID_NPEA) */
- else if (IX_NPEDL_NPEID_NPEB == npeId)
- {
- /* Check whether NPE B is present */
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)==
- IX_FEATURE_CTRL_COMPONENT_DISABLED)
- {
- /* NPE B does not present */
- IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeStopAndReset - Warning:NPEB does not present.\n");
- return IX_SUCCESS;
- }
- } /* end of elseif(IX_NPEDL_NPEID_NPEB) */
- else if (IX_NPEDL_NPEID_NPEC == npeId)
- {
- /* Check whether NPE C is present */
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)==
- IX_FEATURE_CTRL_COMPONENT_DISABLED)
- {
- /* NPE C does not present */
- IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeStopAndReset - Warning:NPEC does not present.\n");
- return IX_SUCCESS;
- }
- } /* end of elseif(IX_NPEDL_NPEID_NPEC) */
- else
- {
- /* Invalid NPE ID */
- IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeStopAndReset - invalid Npe ID\n");
- status = IX_NPEDL_PARAM_ERR;
- } /* end of if-else(IX_NPEDL_NPEID_NPEC) */
- } /* end of if not IXP42x-A0 Silicon */
-
- if (status == IX_SUCCESS)
- {
- /* call NpeMgr function to stop the NPE */
- status = ixNpeDlNpeMgrNpeStop (npeId);
- if (status == IX_SUCCESS)
- {
- /* call NpeMgr function to reset the NPE */
- status = ixNpeDlNpeMgrNpeReset (npeId);
- }
- } /* end of if(status) */
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlNpeStopAndReset : status = %d\n", status);
-
- if (IX_SUCCESS == status)
- {
- /* Indicate NPE has been stopped */
- ixNpeDlNpeStarted[npeId] = FALSE ;
- }
-
- return status;
-}
-
-/*
- * Function definition: ixNpeDlNpeExecutionStart
- */
-PUBLIC IX_STATUS
-ixNpeDlNpeExecutionStart (IxNpeDlNpeId npeId)
-{
- IX_STATUS status = IX_SUCCESS;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlNpeExecutionStart\n");
-
- /* If not IXP42X A0 stepping, proceed to check for existence of npe's */
- if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
- (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
- || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
- {
- /*
- * Check whether NPE is present
- */
- if (IX_NPEDL_NPEID_NPEA == npeId)
- {
- /* Check whether NPE A is present */
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA)==
- IX_FEATURE_CTRL_COMPONENT_DISABLED)
- {
- /* NPE A does not present */
- IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStart - Warning:NPEA does not present.\n");
- return IX_SUCCESS;
- }
- } /* end of if(IX_NPEDL_NPEID_NPEA) */
- else if (IX_NPEDL_NPEID_NPEB == npeId)
- {
- /* Check whether NPE B is present */
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)==
- IX_FEATURE_CTRL_COMPONENT_DISABLED)
- {
- /* NPE B does not present */
- IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStart - Warning:NPEB does not present.\n");
- return IX_SUCCESS;
- }
- } /* end of elseif(IX_NPEDL_NPEID_NPEB) */
- else if (IX_NPEDL_NPEID_NPEC == npeId)
- {
- /* Check whether NPE C is present */
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)==
- IX_FEATURE_CTRL_COMPONENT_DISABLED)
- {
- /* NPE C does not present */
- IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStart - Warning:NPEC does not present.\n");
- return IX_SUCCESS;
- }
- } /* end of elseif(IX_NPEDL_NPEID_NPEC) */
- else
- {
- /* Invalid NPE ID */
- IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeExecutionStart - invalid Npe ID\n");
- return IX_NPEDL_PARAM_ERR;
- } /* end of if-else(IX_NPEDL_NPEID_NPEC) */
- } /* end of if not IXP42x-A0 Silicon */
-
- if (TRUE == ixNpeDlNpeStarted[npeId])
- {
- /* NPE has been started. */
- return IX_SUCCESS ;
- }
-
- /* Ensure initialisation has been completed */
- ixNpeDlNpeMgrInit();
-
- /* call NpeMgr function to start the NPE */
- status = ixNpeDlNpeMgrNpeStart (npeId);
-
- if (IX_SUCCESS == status)
- {
- /* Indicate NPE has started */
- ixNpeDlNpeStarted[npeId] = TRUE ;
- }
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlNpeExecutionStart : status = %d\n",
- status);
-
- return status;
-}
-
-/*
- * Function definition: ixNpeDlNpeExecutionStop
- */
-PUBLIC IX_STATUS
-ixNpeDlNpeExecutionStop (IxNpeDlNpeId npeId)
-{
- IX_STATUS status = IX_SUCCESS;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlNpeExecutionStop\n");
-
- /* Ensure initialisation has been completed */
- ixNpeDlNpeMgrInit();
-
- /* If not IXP42X A0 stepping, proceed to check for existence of npe's */
- if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
- (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
- || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
- {
- /*
- * Check whether NPE is present
- */
- if (IX_NPEDL_NPEID_NPEA == npeId)
- {
- /* Check whether NPE A is present */
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA)==
- IX_FEATURE_CTRL_COMPONENT_DISABLED)
- {
- /* NPE A does not present */
- IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStop - Warning:NPEA does not present.\n");
- return IX_SUCCESS;
- }
- } /* end of if(IX_NPEDL_NPEID_NPEA) */
- else if (IX_NPEDL_NPEID_NPEB == npeId)
- {
- /* Check whether NPE B is present */
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)==
- IX_FEATURE_CTRL_COMPONENT_DISABLED)
- {
- /* NPE B does not present */
- IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStop - Warning:NPEB does not present.\n");
- return IX_SUCCESS;
- }
- } /* end of elseif(IX_NPEDL_NPEID_NPEB) */
- else if (IX_NPEDL_NPEID_NPEC == npeId)
- {
- /* Check whether NPE C is present */
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)==
- IX_FEATURE_CTRL_COMPONENT_DISABLED)
- {
- /* NPE C does not present */
- IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStop - Warning:NPEC does not present.\n");
- return IX_SUCCESS;
- }
- } /* end of elseif(IX_NPEDL_NPEID_NPEC) */
- else
- {
- /* Invalid NPE ID */
- IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeExecutionStop - invalid Npe ID\n");
- status = IX_NPEDL_PARAM_ERR;
- } /* end of if-else(IX_NPEDL_NPEID_NPEC) */
- } /* end of if not IXP42X-AO Silicon */
-
- if (status == IX_SUCCESS)
- {
- /* call NpeMgr function to stop the NPE */
- status = ixNpeDlNpeMgrNpeStop (npeId);
- }
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlNpeExecutionStop : status = %d\n",
- status);
-
- if (IX_SUCCESS == status)
- {
- /* Indicate NPE has been stopped */
- ixNpeDlNpeStarted[npeId] = FALSE ;
- }
-
- return status;
-}
-
-/*
- * Function definition: ixNpeDlUnload
- */
-PUBLIC IX_STATUS
-ixNpeDlUnload (void)
-{
- IX_STATUS status;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlUnload\n");
-
- status = ixNpeDlNpeMgrUninit();
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlUnload : status = %d\n",
- status);
- return status;
-}
-
-/*
- * Function definition: ixNpeDlStatsShow
- */
-PUBLIC void
-ixNpeDlStatsShow (void)
-{
- ixOsalLog (IX_OSAL_LOG_LVL_USER,
- IX_OSAL_LOG_DEV_STDOUT,
- "\nixNpeDlStatsShow:\n"
- "\tDownloads Attempted by user: %u\n"
- "\tSuccessful Downloads: %u\n"
- "\tFailed Downloads (due to Critical Error): %u\n\n",
- ixNpeDlStats.attemptedDownloads,
- ixNpeDlStats.successfulDownloads,
- ixNpeDlStats.criticalFailDownloads,
- 0,0,0);
-
- ixNpeDlImageMgrStatsShow ();
- ixNpeDlNpeMgrStatsShow ();
-}
-
-/*
- * Function definition: ixNpeDlStatsReset
- */
-PUBLIC void
-ixNpeDlStatsReset (void)
-{
- ixNpeDlStats.attemptedDownloads = 0;
- ixNpeDlStats.successfulDownloads = 0;
- ixNpeDlStats.criticalFailDownloads = 0;
-
- ixNpeDlImageMgrStatsReset ();
- ixNpeDlNpeMgrStatsReset ();
-}
-
-/*
- * Function definition: ixNpeDlNpeInitAndStartInternal
- */
-PRIVATE IX_STATUS
-ixNpeDlNpeInitAndStartInternal (UINT32 *imageLibrary,
- UINT32 imageId)
-{
- UINT32 imageSize;
- UINT32 *imageCodePtr = NULL;
- IX_STATUS status;
- IxNpeDlNpeId npeId = IX_NPEDL_NPEID_FROM_IMAGEID_GET(imageId);
- IxFeatureCtrlDeviceId deviceId = IX_NPEDL_DEVICEID_FROM_IMAGEID_GET(imageId);
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlNpeInitAndStartInternal\n");
-
- ixNpeDlStats.attemptedDownloads++;
-
- /* Check input parameter device correctness */
- if ((deviceId >= IX_FEATURE_CTRL_DEVICE_TYPE_MAX) ||
- (deviceId < IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X))
- {
- status = IX_NPEDL_PARAM_ERR;
- IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeInitAndStartInternal - "
- "invalid parameter\n");
- } /* End valid device id checking */
-
- /* Check input parameters */
- else if ((npeId >= IX_NPEDL_NPEID_MAX) || (npeId < 0))
- {
- status = IX_NPEDL_PARAM_ERR;
- IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeInitAndStartInternal - "
- "invalid parameter\n");
- }
-
- else
- {
- /* Ensure initialisation has been completed */
- ixNpeDlNpeMgrInit();
-
- /* Checking if image being loaded is meant for device that is running.
- * Image is forward compatible. i.e Image built for IXP42X should run
- * on IXP46X but not vice versa.*/
- if (deviceId > (ixFeatureCtrlDeviceRead() & IX_FEATURE_CTRL_DEVICE_TYPE_MASK))
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeInitAndStartInternal - "
- "Device type mismatch. NPE Image not "
- "meant for device in use \n");
- return IX_NPEDL_DEVICE_ERR;
- }/* if statement - matching image device and current device */
-
- /* If not IXP42X A0 stepping, proceed to check for existence of npe's */
- if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
- (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
- || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
- {
- if (npeId == IX_NPEDL_NPEID_NPEA)
- {
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED)
- {
- IX_NPEDL_WARNING_REPORT("Warning: the NPE A component you specified does"
- " not exist\n");
- return IX_SUCCESS;
- }
- } /* end of if(npeId) */
- else if (npeId == IX_NPEDL_NPEID_NPEB)
- {
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)==
- IX_FEATURE_CTRL_COMPONENT_DISABLED)
- {
- IX_NPEDL_WARNING_REPORT("Warning: the NPE B component you specified"
- " does not exist\n");
- return IX_SUCCESS;
- }
- } /* end of elseif(npeId) */
- else if (npeId == IX_NPEDL_NPEID_NPEC)
- {
- if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)==
- IX_FEATURE_CTRL_COMPONENT_DISABLED)
- {
- IX_NPEDL_WARNING_REPORT("Warning: the NPE C component you specified"
- " does not exist\n");
- return IX_SUCCESS;
- }
- } /* end of elseif(npeId) */
- } /* end of if not IXP42X-A0 Silicon */
-
- /* stop and reset the NPE */
- status = ixNpeDlNpeStopAndReset (npeId);
- if (IX_SUCCESS != status)
- {
- IX_NPEDL_ERROR_REPORT ("Failed to stop and reset NPE\n");
- return status;
- }
-
- /* Locate image */
- status = ixNpeDlImageMgrImageFind (imageLibrary, imageId,
- &imageCodePtr, &imageSize);
- if (IX_SUCCESS == status)
- {
- /*
- * If download was successful, store image Id in list of
- * currently loaded images. If a critical error occured
- * during download, record that the NPE has an invalid image
- */
- status = ixNpeDlNpeMgrImageLoad (npeId, imageCodePtr, TRUE);
- if (IX_SUCCESS == status)
- {
- ixNpeDlNpeState[npeId].validImage = TRUE;
- ixNpeDlStats.successfulDownloads++;
-
- status = ixNpeDlNpeExecutionStart (npeId);
- }
- else if ((status == IX_NPEDL_CRITICAL_NPE_ERR) ||
- (status == IX_NPEDL_CRITICAL_MICROCODE_ERR))
- {
- ixNpeDlNpeState[npeId].validImage = FALSE;
- ixNpeDlStats.criticalFailDownloads++;
- }
-
- /* NOTE - The following section of code is here to support
- * a deprecated function ixNpeDlLoadedImageGet(). When that
- * function is removed from the API, this code should be revised.
- */
- ixNpeDlNpeState[npeId].imageId.npeId = npeId;
- ixNpeDlNpeState[npeId].imageId.functionalityId =
- IX_NPEDL_FUNCTIONID_FROM_IMAGEID_GET(imageId);
- ixNpeDlNpeState[npeId].imageId.major =
- IX_NPEDL_MAJOR_FROM_IMAGEID_GET(imageId);
- ixNpeDlNpeState[npeId].imageId.minor =
- IX_NPEDL_MINOR_FROM_IMAGEID_GET(imageId);
- } /* end of if(IX_SUCCESS) */ /* condition: image located successfully in microcode image */
- } /* end of if-else(npeId-deviceId) */ /* condition: parameter checks ok */
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlNpeInitAndStartInternal : "
- "status = %d\n", status);
- return status;
-}
-
-/*
- * Function definition: ixNpeDlCustomImageNpeInitAndStart
- */
-PUBLIC IX_STATUS
-ixNpeDlCustomImageNpeInitAndStart (UINT32 *imageLibrary,
- UINT32 imageId)
-{
- IX_STATUS status;
-
- if (imageLibrary == NULL)
- {
- status = IX_NPEDL_PARAM_ERR;
- IX_NPEDL_ERROR_REPORT ("ixNpeDlCustomImageNpeInitAndStart "
- "- invalid parameter\n");
- }
- else
- {
- status = ixNpeDlNpeInitAndStartInternal (imageLibrary, imageId);
- } /* end of if-else(imageLibrary) */
-
- return status;
-}
-
-/*
- * Function definition: ixNpeDlNpeInitAndStart
- */
-PUBLIC IX_STATUS
-ixNpeDlNpeInitAndStart (UINT32 imageId)
-{
- return ixNpeDlNpeInitAndStartInternal (NULL, imageId);
-}
-
-/*
- * Function definition: ixNpeDlLoadedImageFunctionalityGet
- */
-PUBLIC IX_STATUS
-ixNpeDlLoadedImageFunctionalityGet (IxNpeDlNpeId npeId,
- UINT8 *functionalityId)
-{
- /* Check input parameters */
- if ((npeId >= IX_NPEDL_NPEID_MAX) || (npeId < 0))
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlLoadedImageFunctionalityGet "
- "- invalid parameter\n");
- return IX_NPEDL_PARAM_ERR;
- }
- if (functionalityId == NULL)
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlLoadedImageFunctionalityGet "
- "- invalid parameter\n");
- return IX_NPEDL_PARAM_ERR;
- }
-
- if (ixNpeDlNpeState[npeId].validImage)
- {
- *functionalityId = ixNpeDlNpeState[npeId].imageId.functionalityId;
- return IX_SUCCESS;
- }
- else
- {
- return IX_FAIL;
- }
-}
+++ /dev/null
-/**
- * @file IxNpeDlImageMgr.c
- *
- * @author Intel Corporation
- * @date 09 January 2002
- *
- * @brief This file contains the implementation of the private API for the
- * IXP425 NPE Downloader ImageMgr module
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-
-/*
- * Put the system defined include files required.
- */
-#include "IxOsal.h"
-
-/*
- * Put the user defined include files required.
- */
-#include "IxNpeDlImageMgr_p.h"
-#include "IxNpeDlMacros_p.h"
-
-/*
- * define the flag which toggles the firmare inclusion
- */
-#define IX_NPE_MICROCODE_FIRMWARE_INCLUDED 1
-#include "IxNpeMicrocode.h"
-
-/*
- * Indicates the start of an NPE Image, in new NPE Image Library format.
- * 2 consecutive occurances indicates the end of the NPE Image Library
- */
-#define NPE_IMAGE_MARKER 0xfeedf00d
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/*
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * TO BE DEPRECATED IN A FUTURE RELEASE
- */
-typedef struct
-{
- UINT32 size;
- UINT32 offset;
- UINT32 id;
-} IxNpeDlImageMgrImageEntry;
-
-/*
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * TO BE DEPRECATED IN A FUTURE RELEASE
- */
-typedef union
-{
- IxNpeDlImageMgrImageEntry image;
- UINT32 eohMarker;
-} IxNpeDlImageMgrHeaderEntry;
-
-/*
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * TO BE DEPRECATED IN A FUTURE RELEASE
- */
-typedef struct
-{
- UINT32 signature;
- /* 1st entry in the header (there may be more than one) */
- IxNpeDlImageMgrHeaderEntry entry[1];
-} IxNpeDlImageMgrImageLibraryHeader;
-
-
-/*
- * NPE Image Header definition, used in new NPE Image Library format
- */
-typedef struct
-{
- UINT32 marker;
- UINT32 id;
- UINT32 size;
-} IxNpeDlImageMgrImageHeader;
-
-/* module statistics counters */
-typedef struct
-{
- UINT32 invalidSignature;
- UINT32 imageIdListOverflow;
- UINT32 imageIdNotFound;
-} IxNpeDlImageMgrStats;
-
-
-/*
- * Variable declarations global to this file only. Externs are followed by
- * static variables.
- */
-static IxNpeDlImageMgrStats ixNpeDlImageMgrStats;
-
-static UINT32* getIxNpeMicroCodeImageLibrary(void)
-{
- char *s;
-
- if ((s = getenv("npe_ucode")) != NULL)
- return (UINT32*) simple_strtoul(s, NULL, 16);
- else
- return NULL;
-}
-
-/*
- * static function prototypes.
- */
-PRIVATE BOOL
-ixNpeDlImageMgrSignatureCheck (UINT32 *microCodeImageLibrary);
-
-PRIVATE void
-ixNpeDlImageMgrImageIdFormat (UINT32 rawImageId, IxNpeDlImageId *imageId);
-
-PRIVATE BOOL
-ixNpeDlImageMgrImageIdCompare (IxNpeDlImageId *imageIdA,
- IxNpeDlImageId *imageIdB);
-
-PRIVATE BOOL
-ixNpeDlImageMgrNpeFunctionIdCompare (IxNpeDlImageId *imageIdA,
- IxNpeDlImageId *imageIdB);
-
-#if 0
-PRIVATE IX_STATUS
-ixNpeDlImageMgrImageFind_legacy (UINT32 *imageLibrary,
- UINT32 imageId,
- UINT32 **imagePtr,
- UINT32 *imageSize);
-
-/*
- * Function definition: ixNpeDlImageMgrMicrocodeImageLibraryOverride
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-IX_STATUS
-ixNpeDlImageMgrMicrocodeImageLibraryOverride (
- UINT32 *clientImageLibrary)
-{
- IX_STATUS status = IX_SUCCESS;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlImageMgrMicrocodeImageLibraryOverride\n");
-
- if (ixNpeDlImageMgrSignatureCheck (clientImageLibrary))
- {
- IxNpeMicroCodeImageLibrary = clientImageLibrary;
- }
- else
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrMicrocodeImageLibraryOverride: "
- "Client-supplied image has invalid signature\n");
- status = IX_FAIL;
- }
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlImageMgrMicrocodeImageLibraryOverride: status = %d\n",
- status);
- return status;
-}
-#endif
-
-/*
- * Function definition: ixNpeDlImageMgrImageListExtract
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-IX_STATUS
-ixNpeDlImageMgrImageListExtract (
- IxNpeDlImageId *imageListPtr,
- UINT32 *numImages)
-{
- UINT32 rawImageId;
- IxNpeDlImageId formattedImageId;
- IX_STATUS status = IX_SUCCESS;
- UINT32 imageCount = 0;
- IxNpeDlImageMgrImageLibraryHeader *header;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlImageMgrImageListExtract\n");
-
- header = (IxNpeDlImageMgrImageLibraryHeader *) getIxNpeMicroCodeImageLibrary();
-
- if (ixNpeDlImageMgrSignatureCheck (getIxNpeMicroCodeImageLibrary()))
- {
- /* for each image entry in the image header ... */
- while (header->entry[imageCount].eohMarker !=
- IX_NPEDL_IMAGEMGR_END_OF_HEADER)
- {
- /*
- * if the image list container from calling function has capacity,
- * add the image id to the list
- */
- if ((imageListPtr != NULL) && (imageCount < *numImages))
- {
- rawImageId = header->entry[imageCount].image.id;
- ixNpeDlImageMgrImageIdFormat (rawImageId, &formattedImageId);
- imageListPtr[imageCount] = formattedImageId;
- }
- /* imageCount reflects no. of image entries in image library header */
- imageCount++;
- }
-
- /*
- * if image list container from calling function was too small to
- * contain all image ids in the header, set return status to FAIL
- */
- if ((imageListPtr != NULL) && (imageCount > *numImages))
- {
- status = IX_FAIL;
- IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageListExtract: "
- "number of Ids found exceeds list capacity\n");
- ixNpeDlImageMgrStats.imageIdListOverflow++;
- }
- /* return number of image ids found in image library header */
- *numImages = imageCount;
- }
- else
- {
- status = IX_FAIL;
- IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageListExtract: "
- "invalid signature in image\n");
- }
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlImageMgrImageListExtract: status = %d\n",
- status);
- return status;
-}
-
-
-/*
- * Function definition: ixNpeDlImageMgrImageLocate
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-IX_STATUS
-ixNpeDlImageMgrImageLocate (
- IxNpeDlImageId *imageId,
- UINT32 **imagePtr,
- UINT32 *imageSize)
-{
- UINT32 imageOffset;
- UINT32 rawImageId;
- IxNpeDlImageId formattedImageId;
- /* used to index image entries in image library header */
- UINT32 imageCount = 0;
- IX_STATUS status = IX_FAIL;
- IxNpeDlImageMgrImageLibraryHeader *header;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlImageMgrImageLocate\n");
-
- header = (IxNpeDlImageMgrImageLibraryHeader *) getIxNpeMicroCodeImageLibrary();
-
- if (ixNpeDlImageMgrSignatureCheck (getIxNpeMicroCodeImageLibrary()))
- {
- /* for each image entry in the image library header ... */
- while (header->entry[imageCount].eohMarker !=
- IX_NPEDL_IMAGEMGR_END_OF_HEADER)
- {
- rawImageId = header->entry[imageCount].image.id;
- ixNpeDlImageMgrImageIdFormat (rawImageId, &formattedImageId);
- /* if a match for imageId is found in the image library header... */
- if (ixNpeDlImageMgrImageIdCompare (imageId, &formattedImageId))
- {
- /*
- * get pointer to the image in the image library using offset from
- * 1st word in image library
- */
- UINT32 *tmp=getIxNpeMicroCodeImageLibrary();
- imageOffset = header->entry[imageCount].image.offset;
- *imagePtr = &tmp[imageOffset];
- /* get the image size */
- *imageSize = header->entry[imageCount].image.size;
- status = IX_SUCCESS;
- break;
- }
- imageCount++;
- }
- if (status != IX_SUCCESS)
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageLocate: "
- "imageId not found in image library header\n");
- ixNpeDlImageMgrStats.imageIdNotFound++;
- }
- }
- else
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageLocate: "
- "invalid signature in image library\n");
- }
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlImageMgrImageLocate: status = %d\n", status);
- return status;
-}
-
-/*
- * Function definition: ixNpeDlImageMgrLatestImageExtract
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-IX_STATUS
-ixNpeDlImageMgrLatestImageExtract (IxNpeDlImageId *imageId)
-{
- UINT32 imageCount = 0;
- UINT32 rawImageId;
- IxNpeDlImageId formattedImageId;
- IX_STATUS status = IX_FAIL;
- IxNpeDlImageMgrImageLibraryHeader *header;
-
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlImageMgrLatestImageExtract\n");
-
- header = (IxNpeDlImageMgrImageLibraryHeader *) getIxNpeMicroCodeImageLibrary();
-
- if (ixNpeDlImageMgrSignatureCheck (getIxNpeMicroCodeImageLibrary()))
- {
- /* for each image entry in the image library header ... */
- while (header->entry[imageCount].eohMarker !=
- IX_NPEDL_IMAGEMGR_END_OF_HEADER)
- {
- rawImageId = header->entry[imageCount].image.id;
- ixNpeDlImageMgrImageIdFormat (rawImageId, &formattedImageId);
- /*
- * if a match for the npe Id and functionality Id of the imageId is
- * found in the image library header...
- */
- if(ixNpeDlImageMgrNpeFunctionIdCompare(imageId, &formattedImageId))
- {
- if(imageId->major <= formattedImageId.major)
- {
- if(imageId->minor < formattedImageId.minor)
- {
- imageId->minor = formattedImageId.minor;
- }
- imageId->major = formattedImageId.major;
- }
- status = IX_SUCCESS;
- }
- imageCount++;
- }
- if (status != IX_SUCCESS)
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrLatestImageExtract: "
- "imageId not found in image library header\n");
- ixNpeDlImageMgrStats.imageIdNotFound++;
- }
- }
- else
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrLatestImageGet: "
- "invalid signature in image library\n");
- }
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlImageMgrLatestImageGet: status = %d\n", status);
- return status;
-}
-
-/*
- * Function definition: ixNpeDlImageMgrSignatureCheck
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-PRIVATE BOOL
-ixNpeDlImageMgrSignatureCheck (UINT32 *microCodeImageLibrary)
-{
- IxNpeDlImageMgrImageLibraryHeader *header =
- (IxNpeDlImageMgrImageLibraryHeader *) microCodeImageLibrary;
- BOOL result = TRUE;
-
- if (!header || header->signature != IX_NPEDL_IMAGEMGR_SIGNATURE)
- {
- result = FALSE;
- ixNpeDlImageMgrStats.invalidSignature++;
- }
-
- return result;
-}
-
-
-/*
- * Function definition: ixNpeDlImageMgrImageIdFormat
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-PRIVATE void
-ixNpeDlImageMgrImageIdFormat (
- UINT32 rawImageId,
- IxNpeDlImageId *imageId)
-{
- imageId->npeId = (rawImageId >>
- IX_NPEDL_IMAGEID_NPEID_OFFSET) &
- IX_NPEDL_NPEIMAGE_FIELD_MASK;
- imageId->functionalityId = (rawImageId >>
- IX_NPEDL_IMAGEID_FUNCTIONID_OFFSET) &
- IX_NPEDL_NPEIMAGE_FIELD_MASK;
- imageId->major = (rawImageId >>
- IX_NPEDL_IMAGEID_MAJOR_OFFSET) &
- IX_NPEDL_NPEIMAGE_FIELD_MASK;
- imageId->minor = (rawImageId >>
- IX_NPEDL_IMAGEID_MINOR_OFFSET) &
- IX_NPEDL_NPEIMAGE_FIELD_MASK;
-
-}
-
-
-/*
- * Function definition: ixNpeDlImageMgrImageIdCompare
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-PRIVATE BOOL
-ixNpeDlImageMgrImageIdCompare (
- IxNpeDlImageId *imageIdA,
- IxNpeDlImageId *imageIdB)
-{
- if ((imageIdA->npeId == imageIdB->npeId) &&
- (imageIdA->functionalityId == imageIdB->functionalityId) &&
- (imageIdA->major == imageIdB->major) &&
- (imageIdA->minor == imageIdB->minor))
- {
- return TRUE;
- }
- else
- {
- return FALSE;
- }
-}
-
-/*
- * Function definition: ixNpeDlImageMgrNpeFunctionIdCompare
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-PRIVATE BOOL
-ixNpeDlImageMgrNpeFunctionIdCompare (
- IxNpeDlImageId *imageIdA,
- IxNpeDlImageId *imageIdB)
-{
- if ((imageIdA->npeId == imageIdB->npeId) &&
- (imageIdA->functionalityId == imageIdB->functionalityId))
- {
- return TRUE;
- }
- else
- {
- return FALSE;
- }
-}
-
-
-/*
- * Function definition: ixNpeDlImageMgrStatsShow
- */
-void
-ixNpeDlImageMgrStatsShow (void)
-{
- ixOsalLog (IX_OSAL_LOG_LVL_USER,
- IX_OSAL_LOG_DEV_STDOUT,
- "\nixNpeDlImageMgrStatsShow:\n"
- "\tInvalid Image Signatures: %u\n"
- "\tImage Id List capacity too small: %u\n"
- "\tImage Id not found: %u\n\n",
- ixNpeDlImageMgrStats.invalidSignature,
- ixNpeDlImageMgrStats.imageIdListOverflow,
- ixNpeDlImageMgrStats.imageIdNotFound,
- 0,0,0);
-}
-
-
-/*
- * Function definition: ixNpeDlImageMgrStatsReset
- */
-void
-ixNpeDlImageMgrStatsReset (void)
-{
- ixNpeDlImageMgrStats.invalidSignature = 0;
- ixNpeDlImageMgrStats.imageIdListOverflow = 0;
- ixNpeDlImageMgrStats.imageIdNotFound = 0;
-}
-
-
-#if 0
-/*
- * Function definition: ixNpeDlImageMgrImageFind_legacy
- *
- * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT
- * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE
- */
-PRIVATE IX_STATUS
-ixNpeDlImageMgrImageFind_legacy (
- UINT32 *imageLibrary,
- UINT32 imageId,
- UINT32 **imagePtr,
- UINT32 *imageSize)
-{
- UINT32 imageOffset;
- /* used to index image entries in image library header */
- UINT32 imageCount = 0;
- IX_STATUS status = IX_FAIL;
- IxNpeDlImageMgrImageLibraryHeader *header;
- BOOL imageFound = FALSE;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlImageMgrImageFind\n");
-
-
- /* If user didn't specify a library to use, use the default
- * one from IxNpeMicrocode.h
- */
- if (imageLibrary == NULL)
- {
- imageLibrary = IxNpeMicroCodeImageLibrary;
- }
-
- if (ixNpeDlImageMgrSignatureCheck (imageLibrary))
- {
- header = (IxNpeDlImageMgrImageLibraryHeader *) imageLibrary;
-
- /* for each image entry in the image library header ... */
- while ((header->entry[imageCount].eohMarker !=
- IX_NPEDL_IMAGEMGR_END_OF_HEADER) && !(imageFound))
- {
- /* if a match for imageId is found in the image library header... */
- if (imageId == header->entry[imageCount].image.id)
- {
- /*
- * get pointer to the image in the image library using offset from
- * 1st word in image library
- */
- imageOffset = header->entry[imageCount].image.offset;
- *imagePtr = &imageLibrary[imageOffset];
- /* get the image size */
- *imageSize = header->entry[imageCount].image.size;
- status = IX_SUCCESS;
- imageFound = TRUE;
- }
- imageCount++;
- }
- if (status != IX_SUCCESS)
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageFind: "
- "imageId not found in image library header\n");
- ixNpeDlImageMgrStats.imageIdNotFound++;
- }
- }
- else
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageFind: "
- "invalid signature in image library\n");
- }
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlImageMgrImageFind: status = %d\n", status);
- return status;
-}
-#endif
-
-/*
- * Function definition: ixNpeDlImageMgrImageFind
- */
-IX_STATUS
-ixNpeDlImageMgrImageFind (
- UINT32 *imageLibrary,
- UINT32 imageId,
- UINT32 **imagePtr,
- UINT32 *imageSize)
-{
- IxNpeDlImageMgrImageHeader *image;
- UINT32 offset = 0;
-
- /* If user didn't specify a library to use, use the default
- * one from IxNpeMicrocode.h
- */
- if (imageLibrary == NULL)
- {
-#ifdef IX_NPEDL_READ_MICROCODE_FROM_FILE
- if (ixNpeMicrocode_binaryArray == NULL)
- {
- printk (KERN_ERR "ixp400.o: ERROR, no Microcode found in memory\n");
- return IX_FAIL;
- }
- else
- {
- imageLibrary = ixNpeMicrocode_binaryArray;
- }
-#else
- imageLibrary = getIxNpeMicroCodeImageLibrary();
- if (imageLibrary == NULL)
- {
- printf ("npe: ERROR, no Microcode found in memory\n");
- return IX_FAIL;
- }
-#endif /* IX_NPEDL_READ_MICROCODE_FROM_FILE */
- }
-
-#if 0
- /* For backward's compatibility with previous image format */
- if (ixNpeDlImageMgrSignatureCheck(imageLibrary))
- {
- return ixNpeDlImageMgrImageFind_legacy(imageLibrary,
- imageId,
- imagePtr,
- imageSize);
- }
-#endif
-
- while (*(imageLibrary+offset) == NPE_IMAGE_MARKER)
- {
- image = (IxNpeDlImageMgrImageHeader *)(imageLibrary+offset);
- offset += sizeof(IxNpeDlImageMgrImageHeader)/sizeof(UINT32);
-
- if (image->id == imageId)
- {
- *imagePtr = imageLibrary + offset;
- *imageSize = image->size;
- return IX_SUCCESS;
- }
- /* 2 consecutive NPE_IMAGE_MARKER's indicates end of library */
- else if (image->id == NPE_IMAGE_MARKER)
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageFind: "
- "imageId not found in image library header\n");
- ixNpeDlImageMgrStats.imageIdNotFound++;
- /* reached end of library, image not found */
- return IX_FAIL;
- }
- offset += image->size;
- }
-
- /* If we get here, our image library may be corrupted */
- IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageFind: "
- "image library format may be invalid or corrupted\n");
- return IX_FAIL;
-}
-
+++ /dev/null
-/**
- * @file IxNpeDlNpeMgr.c
- *
- * @author Intel Corporation
- * @date 09 January 2002
- *
- * @brief This file contains the implementation of the private API for the
- * IXP425 NPE Downloader NpeMgr module
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-
-/*
- * Put the user defined include files required.
- */
-
-
-/*
- * Put the user defined include files required.
- */
-#include "IxOsal.h"
-#include "IxNpeDl.h"
-#include "IxNpeDlNpeMgr_p.h"
-#include "IxNpeDlNpeMgrUtils_p.h"
-#include "IxNpeDlNpeMgrEcRegisters_p.h"
-#include "IxNpeDlMacros_p.h"
-#include "IxFeatureCtrl.h"
-
-/*
- * #defines and macros used in this file.
- */
-#define IX_NPEDL_BYTES_PER_WORD 4
-
-/* used to read download map from version in microcode image */
-#define IX_NPEDL_BLOCK_TYPE_INSTRUCTION 0x00000000
-#define IX_NPEDL_BLOCK_TYPE_DATA 0x00000001
-#define IX_NPEDL_BLOCK_TYPE_STATE 0x00000002
-#define IX_NPEDL_END_OF_DOWNLOAD_MAP 0x0000000F
-
-/*
- * masks used to extract address info from State information context
- * register addresses as read from microcode image
- */
-#define IX_NPEDL_MASK_STATE_ADDR_CTXT_REG 0x0000000F
-#define IX_NPEDL_MASK_STATE_ADDR_CTXT_NUM 0x000000F0
-
-/* LSB offset of Context Number field in State-Info Context Address */
-#define IX_NPEDL_OFFSET_STATE_ADDR_CTXT_NUM 4
-
-/* size (in words) of single State Information entry (ctxt reg address|data) */
-#define IX_NPEDL_STATE_INFO_ENTRY_SIZE 2
-
-
- #define IX_NPEDL_RESET_NPE_PARITY 0x0800
- #define IX_NPEDL_PARITY_BIT_MASK 0x3F00FFFF
- #define IX_NPEDL_CONFIG_CTRL_REG_MASK 0x3F3FFFFF
-
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-typedef struct
-{
- UINT32 type;
- UINT32 offset;
-} IxNpeDlNpeMgrDownloadMapBlockEntry;
-
-typedef union
-{
- IxNpeDlNpeMgrDownloadMapBlockEntry block;
- UINT32 eodmMarker;
-} IxNpeDlNpeMgrDownloadMapEntry;
-
-typedef struct
-{
- /* 1st entry in the download map (there may be more than one) */
- IxNpeDlNpeMgrDownloadMapEntry entry[1];
-} IxNpeDlNpeMgrDownloadMap;
-
-
-/* used to access an instruction or data block in a microcode image */
-typedef struct
-{
- UINT32 npeMemAddress;
- UINT32 size;
- UINT32 data[1];
-} IxNpeDlNpeMgrCodeBlock;
-
-/* used to access each Context Reg entry state-information block */
-typedef struct
-{
- UINT32 addressInfo;
- UINT32 value;
-} IxNpeDlNpeMgrStateInfoCtxtRegEntry;
-
-/* used to access a state-information block in a microcode image */
-typedef struct
-{
- UINT32 size;
- IxNpeDlNpeMgrStateInfoCtxtRegEntry ctxtRegEntry[1];
-} IxNpeDlNpeMgrStateInfoBlock;
-
-/* used to store some useful NPE information for easy access */
-typedef struct
-{
- UINT32 baseAddress;
- UINT32 insMemSize;
- UINT32 dataMemSize;
-} IxNpeDlNpeInfo;
-
-/* used to distinguish instruction and data memory operations */
-typedef enum
-{
- IX_NPEDL_MEM_TYPE_INSTRUCTION = 0,
- IX_NPEDL_MEM_TYPE_DATA
-} IxNpeDlNpeMemType;
-
-/* used to hold a reset value for a particular ECS register */
-typedef struct
-{
- UINT32 regAddr;
- UINT32 regResetVal;
-} IxNpeDlEcsRegResetValue;
-
-/* prototype of function to write either Instruction or Data memory */
-typedef IX_STATUS (*IxNpeDlNpeMgrMemWrite) (UINT32 npeBaseAddress,
- UINT32 npeMemAddress,
- UINT32 npeMemData,
- BOOL verify);
-
-/* module statistics counters */
-typedef struct
-{
- UINT32 instructionBlocksLoaded;
- UINT32 dataBlocksLoaded;
- UINT32 stateInfoBlocksLoaded;
- UINT32 criticalNpeErrors;
- UINT32 criticalMicrocodeErrors;
- UINT32 npeStarts;
- UINT32 npeStops;
- UINT32 npeResets;
-} IxNpeDlNpeMgrStats;
-
-
-/*
- * Variable declarations global to this file only. Externs are followed by
- * static variables.
- */
-static IxNpeDlNpeInfo ixNpeDlNpeInfo[] =
-{
- {
- 0,
- IX_NPEDL_INS_MEMSIZE_WORDS_NPEA,
- IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA
- },
- {
- 0,
- IX_NPEDL_INS_MEMSIZE_WORDS_NPEB,
- IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB
- },
- {
- 0,
- IX_NPEDL_INS_MEMSIZE_WORDS_NPEC,
- IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC
- }
-};
-
-/* contains Reset values for Context Store Registers */
-static UINT32 ixNpeDlCtxtRegResetValues[] =
-{
- IX_NPEDL_CTXT_REG_RESET_STEVT,
- IX_NPEDL_CTXT_REG_RESET_STARTPC,
- IX_NPEDL_CTXT_REG_RESET_REGMAP,
- IX_NPEDL_CTXT_REG_RESET_CINDEX,
-};
-
-/* contains Reset values for Context Store Registers */
-static IxNpeDlEcsRegResetValue ixNpeDlEcsRegResetValues[] =
-{
- {IX_NPEDL_ECS_BG_CTXT_REG_0, IX_NPEDL_ECS_BG_CTXT_REG_0_RESET},
- {IX_NPEDL_ECS_BG_CTXT_REG_1, IX_NPEDL_ECS_BG_CTXT_REG_1_RESET},
- {IX_NPEDL_ECS_BG_CTXT_REG_2, IX_NPEDL_ECS_BG_CTXT_REG_2_RESET},
- {IX_NPEDL_ECS_PRI_1_CTXT_REG_0, IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET},
- {IX_NPEDL_ECS_PRI_1_CTXT_REG_1, IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET},
- {IX_NPEDL_ECS_PRI_1_CTXT_REG_2, IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET},
- {IX_NPEDL_ECS_PRI_2_CTXT_REG_0, IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET},
- {IX_NPEDL_ECS_PRI_2_CTXT_REG_1, IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET},
- {IX_NPEDL_ECS_PRI_2_CTXT_REG_2, IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET},
- {IX_NPEDL_ECS_DBG_CTXT_REG_0, IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET},
- {IX_NPEDL_ECS_DBG_CTXT_REG_1, IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET},
- {IX_NPEDL_ECS_DBG_CTXT_REG_2, IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET},
- {IX_NPEDL_ECS_INSTRUCT_REG, IX_NPEDL_ECS_INSTRUCT_REG_RESET}
-};
-
-static IxNpeDlNpeMgrStats ixNpeDlNpeMgrStats;
-
-/* Set when NPE register memory has been mapped */
-static BOOL ixNpeDlMemInitialised = FALSE;
-
-
-/*
- * static function prototypes.
- */
-PRIVATE IX_STATUS
-ixNpeDlNpeMgrMemLoad (IxNpeDlNpeId npeId, UINT32 npeBaseAddress,
- IxNpeDlNpeMgrCodeBlock *codeBlockPtr,
- BOOL verify, IxNpeDlNpeMemType npeMemType);
-PRIVATE IX_STATUS
-ixNpeDlNpeMgrStateInfoLoad (UINT32 npeBaseAddress,
- IxNpeDlNpeMgrStateInfoBlock *codeBlockPtr,
- BOOL verify);
-PRIVATE BOOL
-ixNpeDlNpeMgrBitsSetCheck (UINT32 npeBaseAddress, UINT32 regOffset,
- UINT32 expectedBitsSet);
-
-PRIVATE UINT32
-ixNpeDlNpeMgrBaseAddressGet (IxNpeDlNpeId npeId);
-
-/*
- * Function definition: ixNpeDlNpeMgrBaseAddressGet
- */
-PRIVATE UINT32
-ixNpeDlNpeMgrBaseAddressGet (IxNpeDlNpeId npeId)
-{
- IX_OSAL_ASSERT (ixNpeDlMemInitialised);
- return ixNpeDlNpeInfo[npeId].baseAddress;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrInit
- */
-void
-ixNpeDlNpeMgrInit (void)
-{
- /* Only map the memory once */
- if (!ixNpeDlMemInitialised)
- {
- UINT32 virtAddr;
-
- /* map the register memory for NPE-A */
- virtAddr = (UINT32) IX_OSAL_MEM_MAP (IX_NPEDL_NPEBASEADDRESS_NPEA,
- IX_OSAL_IXP400_NPEA_MAP_SIZE);
- IX_OSAL_ASSERT(virtAddr);
- ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEA].baseAddress = virtAddr;
-
- /* map the register memory for NPE-B */
- virtAddr = (UINT32) IX_OSAL_MEM_MAP (IX_NPEDL_NPEBASEADDRESS_NPEB,
- IX_OSAL_IXP400_NPEB_MAP_SIZE);
- IX_OSAL_ASSERT(virtAddr);
- ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress = virtAddr;
-
- /* map the register memory for NPE-C */
- virtAddr = (UINT32) IX_OSAL_MEM_MAP (IX_NPEDL_NPEBASEADDRESS_NPEC,
- IX_OSAL_IXP400_NPEC_MAP_SIZE);
- IX_OSAL_ASSERT(virtAddr);
- ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress = virtAddr;
-
- ixNpeDlMemInitialised = TRUE;
- }
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrUninit
- */
-IX_STATUS
-ixNpeDlNpeMgrUninit (void)
-{
- if (!ixNpeDlMemInitialised)
- {
- return IX_FAIL;
- }
-
- IX_OSAL_MEM_UNMAP (ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEA].baseAddress);
- IX_OSAL_MEM_UNMAP (ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress);
- IX_OSAL_MEM_UNMAP (ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress);
-
- ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEA].baseAddress = 0;
- ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress = 0;
- ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress = 0;
-
- ixNpeDlMemInitialised = FALSE;
-
- return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeDlNpeMgrImageLoad
- */
-IX_STATUS
-ixNpeDlNpeMgrImageLoad (
- IxNpeDlNpeId npeId,
- UINT32 *imageCodePtr,
- BOOL verify)
-{
- UINT32 npeBaseAddress;
- IxNpeDlNpeMgrDownloadMap *downloadMap;
- UINT32 *blockPtr;
- UINT32 mapIndex = 0;
- IX_STATUS status = IX_SUCCESS;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlNpeMgrImageLoad\n");
-
- /* get base memory address of NPE from npeId */
- npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId);
-
- /* check execution status of NPE to verify NPE Stop was successful */
- if (!ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL,
- IX_NPEDL_EXCTL_STATUS_STOP))
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrImageDownload - "
- "NPE was not stopped before download\n");
- status = IX_FAIL;
- }
- else
- {
- /*
- * Read Download Map, checking each block type and calling
- * appropriate function to perform download
- */
- downloadMap = (IxNpeDlNpeMgrDownloadMap *) imageCodePtr;
- while ((downloadMap->entry[mapIndex].eodmMarker !=
- IX_NPEDL_END_OF_DOWNLOAD_MAP)
- && (status == IX_SUCCESS))
- {
- /* calculate pointer to block to be downloaded */
- blockPtr = imageCodePtr +
- downloadMap->entry[mapIndex].block.offset;
-
- switch (downloadMap->entry[mapIndex].block.type)
- {
- case IX_NPEDL_BLOCK_TYPE_INSTRUCTION:
- status = ixNpeDlNpeMgrMemLoad (npeId, npeBaseAddress,
- (IxNpeDlNpeMgrCodeBlock *)blockPtr,
- verify,
- IX_NPEDL_MEM_TYPE_INSTRUCTION);
- break;
- case IX_NPEDL_BLOCK_TYPE_DATA:
- status = ixNpeDlNpeMgrMemLoad (npeId, npeBaseAddress,
- (IxNpeDlNpeMgrCodeBlock *)blockPtr,
- verify, IX_NPEDL_MEM_TYPE_DATA);
- break;
- case IX_NPEDL_BLOCK_TYPE_STATE:
- status = ixNpeDlNpeMgrStateInfoLoad (npeBaseAddress,
- (IxNpeDlNpeMgrStateInfoBlock *) blockPtr,
- verify);
- break;
- default:
- IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrImageLoad: "
- "unknown block type in download map\n");
- status = IX_NPEDL_CRITICAL_MICROCODE_ERR;
- ixNpeDlNpeMgrStats.criticalMicrocodeErrors++;
- break;
- }
- mapIndex++;
- }/* loop: for each entry in download map, while status == SUCCESS */
- }/* condition: NPE stopped before attempting download */
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlNpeMgrImageLoad : status = %d\n",
- status);
- return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrMemLoad
- */
-PRIVATE IX_STATUS
-ixNpeDlNpeMgrMemLoad (
- IxNpeDlNpeId npeId,
- UINT32 npeBaseAddress,
- IxNpeDlNpeMgrCodeBlock *blockPtr,
- BOOL verify,
- IxNpeDlNpeMemType npeMemType)
-{
- UINT32 npeMemAddress;
- UINT32 blockSize;
- UINT32 memSize = 0;
- IxNpeDlNpeMgrMemWrite memWriteFunc = NULL;
- UINT32 localIndex = 0;
- IX_STATUS status = IX_SUCCESS;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlNpeMgrMemLoad\n");
-
- /*
- * select NPE EXCTL reg read/write commands depending on memory
- * type (instruction/data) to be accessed
- */
- if (npeMemType == IX_NPEDL_MEM_TYPE_INSTRUCTION)
- {
- memSize = ixNpeDlNpeInfo[npeId].insMemSize;
- memWriteFunc = (IxNpeDlNpeMgrMemWrite) ixNpeDlNpeMgrInsMemWrite;
- }
- else if (npeMemType == IX_NPEDL_MEM_TYPE_DATA)
- {
- memSize = ixNpeDlNpeInfo[npeId].dataMemSize;
- memWriteFunc = (IxNpeDlNpeMgrMemWrite) ixNpeDlNpeMgrDataMemWrite;
- }
-
- /*
- * NPE memory is loaded contiguously from each block, so only address
- * of 1st word in block is needed
- */
- npeMemAddress = blockPtr->npeMemAddress;
- /* number of words of instruction/data microcode in block to download */
- blockSize = blockPtr->size;
- if ((npeMemAddress + blockSize) > memSize)
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrMemLoad: "
- "Block size too big for NPE memory\n");
- status = IX_NPEDL_CRITICAL_MICROCODE_ERR;
- ixNpeDlNpeMgrStats.criticalMicrocodeErrors++;
- }
- else
- {
- for (localIndex = 0; localIndex < blockSize; localIndex++)
- {
- status = memWriteFunc (npeBaseAddress, npeMemAddress,
- blockPtr->data[localIndex], verify);
-
- if (status != IX_SUCCESS)
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrMemLoad: "
- "write to NPE memory failed\n");
- status = IX_NPEDL_CRITICAL_NPE_ERR;
- ixNpeDlNpeMgrStats.criticalNpeErrors++;
- break; /* abort download */
- }
- /* increment target (word)address in NPE memory */
- npeMemAddress++;
- }
- }/* condition: block size will fit in NPE memory */
-
- if (status == IX_SUCCESS)
- {
- if (npeMemType == IX_NPEDL_MEM_TYPE_INSTRUCTION)
- {
- ixNpeDlNpeMgrStats.instructionBlocksLoaded++;
- }
- else if (npeMemType == IX_NPEDL_MEM_TYPE_DATA)
- {
- ixNpeDlNpeMgrStats.dataBlocksLoaded++;
- }
- }
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlNpeMgrMemLoad : status = %d\n", status);
- return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrStateInfoLoad
- */
-PRIVATE IX_STATUS
-ixNpeDlNpeMgrStateInfoLoad (
- UINT32 npeBaseAddress,
- IxNpeDlNpeMgrStateInfoBlock *blockPtr,
- BOOL verify)
-{
- UINT32 blockSize;
- UINT32 ctxtRegAddrInfo;
- UINT32 ctxtRegVal;
- IxNpeDlCtxtRegNum ctxtReg; /* identifies Context Store reg (0-3) */
- UINT32 ctxtNum; /* identifies Context number (0-16) */
- UINT32 i;
- IX_STATUS status = IX_SUCCESS;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlNpeMgrStateInfoLoad\n");
-
- /* block size contains number of words of state-info in block */
- blockSize = blockPtr->size;
-
- ixNpeDlNpeMgrDebugInstructionPreExec (npeBaseAddress);
-
- /* for each state-info context register entry in block */
- for (i = 0; i < (blockSize/IX_NPEDL_STATE_INFO_ENTRY_SIZE); i++)
- {
- /* each state-info entry is 2 words (address, value) in length */
- ctxtRegAddrInfo = (blockPtr->ctxtRegEntry[i]).addressInfo;
- ctxtRegVal = (blockPtr->ctxtRegEntry[i]).value;
-
- ctxtReg = (ctxtRegAddrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_REG);
- ctxtNum = (ctxtRegAddrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_NUM) >>
- IX_NPEDL_OFFSET_STATE_ADDR_CTXT_NUM;
-
- /* error-check Context Register No. and Context Number values */
- /* NOTE that there is no STEVT register for Context 0 */
- if ((ctxtReg < 0) ||
- (ctxtReg >= IX_NPEDL_CTXT_REG_MAX) ||
- (ctxtNum > IX_NPEDL_CTXT_NUM_MAX) ||
- ((ctxtNum == 0) && (ctxtReg == IX_NPEDL_CTXT_REG_STEVT)))
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrStateInfoLoad: "
- "invalid Context Register Address\n");
- status = IX_NPEDL_CRITICAL_MICROCODE_ERR;
- ixNpeDlNpeMgrStats.criticalMicrocodeErrors++;
- break; /* abort download */
- }
-
- status = ixNpeDlNpeMgrCtxtRegWrite (npeBaseAddress, ctxtNum, ctxtReg,
- ctxtRegVal, verify);
- if (status != IX_SUCCESS)
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrStateInfoLoad: "
- "write of state-info to NPE failed\n");
- status = IX_NPEDL_CRITICAL_NPE_ERR;
- ixNpeDlNpeMgrStats.criticalNpeErrors++;
- break; /* abort download */
- }
- }/* loop: for each context reg entry in State Info block */
-
- ixNpeDlNpeMgrDebugInstructionPostExec (npeBaseAddress);
-
- if (status == IX_SUCCESS)
- {
- ixNpeDlNpeMgrStats.stateInfoBlocksLoaded++;
- }
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlNpeMgrStateInfoLoad : status = %d\n",
- status);
- return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrNpeReset
- */
-IX_STATUS
-ixNpeDlNpeMgrNpeReset (
- IxNpeDlNpeId npeId)
-{
- UINT32 npeBaseAddress;
- IxNpeDlCtxtRegNum ctxtReg; /* identifies Context Store reg (0-3) */
- UINT32 ctxtNum; /* identifies Context number (0-16) */
- UINT32 regAddr;
- UINT32 regVal;
- UINT32 localIndex;
- UINT32 indexMax;
- IX_STATUS status = IX_SUCCESS;
- IxFeatureCtrlReg unitFuseReg;
- UINT32 ixNpeConfigCtrlRegVal;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlNpeMgrNpeReset\n");
-
- /* get base memory address of NPE from npeId */
- npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId);
-
- /* pre-store the NPE Config Control Register Value */
- IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_CTL, &ixNpeConfigCtrlRegVal);
-
- ixNpeConfigCtrlRegVal |= 0x3F000000;
-
- /* disable the parity interrupt */
- IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_CTL, (ixNpeConfigCtrlRegVal & IX_NPEDL_PARITY_BIT_MASK));
-
- ixNpeDlNpeMgrDebugInstructionPreExec (npeBaseAddress);
-
- /*
- * clear the FIFOs
- */
- while (ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress,
- IX_NPEDL_REG_OFFSET_WFIFO,
- IX_NPEDL_MASK_WFIFO_VALID))
- {
- /* read from the Watch-point FIFO until empty */
- IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WFIFO,
- ®Val);
- }
-
- while (ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress,
- IX_NPEDL_REG_OFFSET_STAT,
- IX_NPEDL_MASK_STAT_OFNE))
- {
- /* read from the outFIFO until empty */
- IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_FIFO,
- ®Val);
- }
-
- while (ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress,
- IX_NPEDL_REG_OFFSET_STAT,
- IX_NPEDL_MASK_STAT_IFNE))
- {
- /*
- * step execution of the NPE intruction to read inFIFO using
- * the Debug Executing Context stack
- */
- status = ixNpeDlNpeMgrDebugInstructionExec (npeBaseAddress,
- IX_NPEDL_INSTR_RD_FIFO, 0, 0);
-
- if (IX_SUCCESS != status)
- {
- return status;
- }
-
- }
-
- /*
- * Reset the mailbox reg
- */
- /* ...from XScale side */
- IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_MBST,
- IX_NPEDL_REG_RESET_MBST);
- /* ...from NPE side */
- status = ixNpeDlNpeMgrDebugInstructionExec (npeBaseAddress,
- IX_NPEDL_INSTR_RESET_MBOX, 0, 0);
-
- if (IX_SUCCESS != status)
- {
- return status;
- }
-
- /*
- * Reset the physical registers in the NPE register file:
- * Note: no need to save/restore REGMAP for Context 0 here
- * since all Context Store regs are reset in subsequent code
- */
- for (regAddr = 0;
- (regAddr < IX_NPEDL_TOTAL_NUM_PHYS_REG) && (status != IX_FAIL);
- regAddr++)
- {
- /* for each physical register in the NPE reg file, write 0 : */
- status = ixNpeDlNpeMgrPhysicalRegWrite (npeBaseAddress, regAddr,
- 0, TRUE);
- if (status != IX_SUCCESS)
- {
- return status; /* abort reset */
- }
- }
-
-
- /*
- * Reset the context store:
- */
- for (ctxtNum = IX_NPEDL_CTXT_NUM_MIN;
- ctxtNum <= IX_NPEDL_CTXT_NUM_MAX; ctxtNum++)
- {
- /* set each context's Context Store registers to reset values: */
- for (ctxtReg = 0; ctxtReg < IX_NPEDL_CTXT_REG_MAX; ctxtReg++)
- {
- /* NOTE that there is no STEVT register for Context 0 */
- if (!((ctxtNum == 0) && (ctxtReg == IX_NPEDL_CTXT_REG_STEVT)))
- {
- regVal = ixNpeDlCtxtRegResetValues[ctxtReg];
- status = ixNpeDlNpeMgrCtxtRegWrite (npeBaseAddress, ctxtNum,
- ctxtReg, regVal, TRUE);
- if (status != IX_SUCCESS)
- {
- return status; /* abort reset */
- }
- }
- }
- }
-
- ixNpeDlNpeMgrDebugInstructionPostExec (npeBaseAddress);
-
- /* write Reset values to Execution Context Stack registers */
- indexMax = sizeof (ixNpeDlEcsRegResetValues) /
- sizeof (IxNpeDlEcsRegResetValue);
- for (localIndex = 0; localIndex < indexMax; localIndex++)
- {
- regAddr = ixNpeDlEcsRegResetValues[localIndex].regAddr;
- regVal = ixNpeDlEcsRegResetValues[localIndex].regResetVal;
- ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, regAddr, regVal);
- }
-
- /* clear the profile counter */
- ixNpeDlNpeMgrCommandIssue (npeBaseAddress,
- IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT);
-
- /* clear registers EXCT, AP0, AP1, AP2 and AP3 */
- for (regAddr = IX_NPEDL_REG_OFFSET_EXCT;
- regAddr <= IX_NPEDL_REG_OFFSET_AP3;
- regAddr += IX_NPEDL_BYTES_PER_WORD)
- {
- IX_NPEDL_REG_WRITE (npeBaseAddress, regAddr, 0);
- }
-
- /* Reset the Watch-count register */
- IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC, 0);
-
- /*
- * WR IXA00055043 - Remove IMEM Parity Introduced by NPE Reset Operation
- */
-
- /*
- * Call the feature control API to fused out and reset the NPE and its
- * coprocessor - to reset internal states and remove parity error
- */
- unitFuseReg = ixFeatureCtrlRead ();
- unitFuseReg |= (IX_NPEDL_RESET_NPE_PARITY << npeId);
- ixFeatureCtrlWrite (unitFuseReg);
-
- /* call the feature control API to un-fused and un-reset the NPE & COP */
- unitFuseReg &= (~(IX_NPEDL_RESET_NPE_PARITY << npeId));
- ixFeatureCtrlWrite (unitFuseReg);
-
- /*
- * Call NpeMgr function to stop the NPE again after the Feature Control
- * has unfused and Un-Reset the NPE and its associated Coprocessors
- */
- status = ixNpeDlNpeMgrNpeStop (npeId);
-
- /* restore NPE configuration bus Control Register - Parity Settings */
- IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_CTL,
- (ixNpeConfigCtrlRegVal & IX_NPEDL_CONFIG_CTRL_REG_MASK));
-
- ixNpeDlNpeMgrStats.npeResets++;
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlNpeMgrNpeReset : status = %d\n", status);
- return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrNpeStart
- */
-IX_STATUS
-ixNpeDlNpeMgrNpeStart (
- IxNpeDlNpeId npeId)
-{
- UINT32 npeBaseAddress;
- UINT32 ecsRegVal;
- BOOL npeRunning;
- IX_STATUS status = IX_SUCCESS;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlNpeMgrNpeStart\n");
-
- /* get base memory address of NPE from npeId */
- npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId);
-
- /*
- * ensure only Background Context Stack Level is Active by turning off
- * the Active bit in each of the other Executing Context Stack levels
- */
- ecsRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
- IX_NPEDL_ECS_PRI_1_CTXT_REG_0);
- ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE;
- ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_PRI_1_CTXT_REG_0,
- ecsRegVal);
-
- ecsRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
- IX_NPEDL_ECS_PRI_2_CTXT_REG_0);
- ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE;
- ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_PRI_2_CTXT_REG_0,
- ecsRegVal);
-
- ecsRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
- IX_NPEDL_ECS_DBG_CTXT_REG_0);
- ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE;
- ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_0,
- ecsRegVal);
-
- /* clear the pipeline */
- ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE);
-
- /* start NPE execution by issuing command through EXCTL register on NPE */
- ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_START);
-
- /*
- * check execution status of NPE to verify NPE Start operation was
- * successful
- */
- npeRunning = ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress,
- IX_NPEDL_REG_OFFSET_EXCTL,
- IX_NPEDL_EXCTL_STATUS_RUN);
- if (npeRunning)
- {
- ixNpeDlNpeMgrStats.npeStarts++;
- }
- else
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrNpeStart: "
- "failed to start NPE execution\n");
- status = IX_FAIL;
- }
-
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlNpeMgrNpeStart : status = %d\n", status);
- return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrNpeStop
- */
-IX_STATUS
-ixNpeDlNpeMgrNpeStop (
- IxNpeDlNpeId npeId)
-{
- UINT32 npeBaseAddress;
- IX_STATUS status = IX_SUCCESS;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlNpeMgrNpeStop\n");
-
- /* get base memory address of NPE from npeId */
- npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId);
-
- /* stop NPE execution by issuing command through EXCTL register on NPE */
- ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_STOP);
-
- /* verify that NPE Stop was successful */
- if (! ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL,
- IX_NPEDL_EXCTL_STATUS_STOP))
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrNpeStop: "
- "failed to stop NPE execution\n");
- status = IX_FAIL;
- }
-
- ixNpeDlNpeMgrStats.npeStops++;
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlNpeMgrNpeStop : status = %d\n", status);
- return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrBitsSetCheck
- */
-PRIVATE BOOL
-ixNpeDlNpeMgrBitsSetCheck (
- UINT32 npeBaseAddress,
- UINT32 regOffset,
- UINT32 expectedBitsSet)
-{
- UINT32 regVal;
- IX_NPEDL_REG_READ (npeBaseAddress, regOffset, ®Val);
-
- return expectedBitsSet == (expectedBitsSet & regVal);
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrStatsShow
- */
-void
-ixNpeDlNpeMgrStatsShow (void)
-{
- ixOsalLog (IX_OSAL_LOG_LVL_USER,
- IX_OSAL_LOG_DEV_STDOUT,
- "\nixNpeDlNpeMgrStatsShow:\n"
- "\tInstruction Blocks loaded: %u\n"
- "\tData Blocks loaded: %u\n"
- "\tState Information Blocks loaded: %u\n"
- "\tCritical NPE errors: %u\n"
- "\tCritical Microcode errors: %u\n",
- ixNpeDlNpeMgrStats.instructionBlocksLoaded,
- ixNpeDlNpeMgrStats.dataBlocksLoaded,
- ixNpeDlNpeMgrStats.stateInfoBlocksLoaded,
- ixNpeDlNpeMgrStats.criticalNpeErrors,
- ixNpeDlNpeMgrStats.criticalMicrocodeErrors,
- 0);
-
- ixOsalLog (IX_OSAL_LOG_LVL_USER,
- IX_OSAL_LOG_DEV_STDOUT,
- "\tSuccessful NPE Starts: %u\n"
- "\tSuccessful NPE Stops: %u\n"
- "\tSuccessful NPE Resets: %u\n\n",
- ixNpeDlNpeMgrStats.npeStarts,
- ixNpeDlNpeMgrStats.npeStops,
- ixNpeDlNpeMgrStats.npeResets,
- 0,0,0);
-
- ixNpeDlNpeMgrUtilsStatsShow ();
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrStatsReset
- */
-void
-ixNpeDlNpeMgrStatsReset (void)
-{
- ixNpeDlNpeMgrStats.instructionBlocksLoaded = 0;
- ixNpeDlNpeMgrStats.dataBlocksLoaded = 0;
- ixNpeDlNpeMgrStats.stateInfoBlocksLoaded = 0;
- ixNpeDlNpeMgrStats.criticalNpeErrors = 0;
- ixNpeDlNpeMgrStats.criticalMicrocodeErrors = 0;
- ixNpeDlNpeMgrStats.npeStarts = 0;
- ixNpeDlNpeMgrStats.npeStops = 0;
- ixNpeDlNpeMgrStats.npeResets = 0;
-
- ixNpeDlNpeMgrUtilsStatsReset ();
-}
+++ /dev/null
-/**
- * @file IxNpeDlNpeMgrUtils.c
- *
- * @author Intel Corporation
- * @date 18 February 2002
- *
- * @brief This file contains the implementation of the private API for the
- * IXP425 NPE Downloader NpeMgr Utils module
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-
-/*
- * Put the system defined include files required.
- */
-#define IX_NPE_DL_MAX_NUM_OF_RETRIES 1000000 /**< Maximum number of
- * retries before
- * timeout
- */
-
-/*
- * Put the user defined include files required.
- */
-#include "IxOsal.h"
-#include "IxNpeDl.h"
-#include "IxNpeDlNpeMgrUtils_p.h"
-#include "IxNpeDlNpeMgrEcRegisters_p.h"
-#include "IxNpeDlMacros_p.h"
-
-/*
- * #defines and macros used in this file.
- */
-
-/* used to bit-mask a number of bytes */
-#define IX_NPEDL_MASK_LOWER_BYTE_OF_WORD 0x000000FF
-#define IX_NPEDL_MASK_LOWER_SHORT_OF_WORD 0x0000FFFF
-#define IX_NPEDL_MASK_FULL_WORD 0xFFFFFFFF
-
-#define IX_NPEDL_BYTES_PER_WORD 4
-#define IX_NPEDL_BYTES_PER_SHORT 2
-
-#define IX_NPEDL_REG_SIZE_BYTE 8
-#define IX_NPEDL_REG_SIZE_SHORT 16
-#define IX_NPEDL_REG_SIZE_WORD 32
-
-/*
- * Introduce extra read cycles after issuing read command to NPE
- * so that we read the register after the NPE has updated it
- * This is to overcome race condition between XScale and NPE
- */
-#define IX_NPEDL_DELAY_READ_CYCLES 2
-/*
- * To mask top three MSBs of 32bit word to download into NPE IMEM
- */
-#define IX_NPEDL_MASK_UNUSED_IMEM_BITS 0x1FFFFFFF;
-
-
-/*
- * typedefs
- */
-typedef struct
-{
- UINT32 regAddress;
- UINT32 regSize;
-} IxNpeDlCtxtRegAccessInfo;
-
-/* module statistics counters */
-typedef struct
-{
- UINT32 insMemWrites;
- UINT32 insMemWriteFails;
- UINT32 dataMemWrites;
- UINT32 dataMemWriteFails;
- UINT32 ecsRegWrites;
- UINT32 ecsRegReads;
- UINT32 dbgInstructionExecs;
- UINT32 contextRegWrites;
- UINT32 physicalRegWrites;
- UINT32 nextPcWrites;
-} IxNpeDlNpeMgrUtilsStats;
-
-
-/*
- * Variable declarations global to this file only. Externs are followed by
- * static variables.
- */
-
-/*
- * contains useful address and function pointers to read/write Context Regs,
- * eliminating some switch or if-else statements in places
- */
-static IxNpeDlCtxtRegAccessInfo ixNpeDlCtxtRegAccInfo[IX_NPEDL_CTXT_REG_MAX] =
-{
- {
- IX_NPEDL_CTXT_REG_ADDR_STEVT,
- IX_NPEDL_REG_SIZE_BYTE
- },
- {
- IX_NPEDL_CTXT_REG_ADDR_STARTPC,
- IX_NPEDL_REG_SIZE_SHORT
- },
- {
- IX_NPEDL_CTXT_REG_ADDR_REGMAP,
- IX_NPEDL_REG_SIZE_SHORT
- },
- {
- IX_NPEDL_CTXT_REG_ADDR_CINDEX,
- IX_NPEDL_REG_SIZE_BYTE
- }
-};
-
-static UINT32 ixNpeDlSavedExecCount = 0;
-static UINT32 ixNpeDlSavedEcsDbgCtxtReg2 = 0;
-
-static IxNpeDlNpeMgrUtilsStats ixNpeDlNpeMgrUtilsStats;
-
-
-/*
- * static function prototypes.
- */
-PRIVATE __inline__ void
-ixNpeDlNpeMgrWriteCommandIssue (UINT32 npeBaseAddress, UINT32 cmd,
- UINT32 addr, UINT32 data);
-
-PRIVATE __inline__ UINT32
-ixNpeDlNpeMgrReadCommandIssue (UINT32 npeBaseAddress, UINT32 cmd, UINT32 addr);
-
-PRIVATE IX_STATUS
-ixNpeDlNpeMgrLogicalRegRead (UINT32 npeBaseAddress, UINT32 regAddr,
- UINT32 regSize, UINT32 ctxtNum, UINT32 *regVal);
-
-PRIVATE IX_STATUS
-ixNpeDlNpeMgrLogicalRegWrite (UINT32 npeBaseAddress, UINT32 regAddr,
- UINT32 regVal, UINT32 regSize,
- UINT32 ctxtNum, BOOL verify);
-
-/*
- * Function definition: ixNpeDlNpeMgrWriteCommandIssue
- */
-PRIVATE __inline__ void
-ixNpeDlNpeMgrWriteCommandIssue (
- UINT32 npeBaseAddress,
- UINT32 cmd,
- UINT32 addr,
- UINT32 data)
-{
- IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, data);
- IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXAD, addr);
- IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, cmd);
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrReadCommandIssue
- */
-PRIVATE __inline__ UINT32
-ixNpeDlNpeMgrReadCommandIssue (
- UINT32 npeBaseAddress,
- UINT32 cmd,
- UINT32 addr)
-{
- UINT32 data = 0;
- int i;
-
- IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXAD, addr);
- IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, cmd);
- for (i = 0; i <= IX_NPEDL_DELAY_READ_CYCLES; i++)
- {
- IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, &data);
- }
-
- return data;
-}
-
-/*
- * Function definition: ixNpeDlNpeMgrInsMemWrite
- */
-IX_STATUS
-ixNpeDlNpeMgrInsMemWrite (
- UINT32 npeBaseAddress,
- UINT32 insMemAddress,
- UINT32 insMemData,
- BOOL verify)
-{
- UINT32 insMemDataRtn;
-
- ixNpeDlNpeMgrWriteCommandIssue (npeBaseAddress,
- IX_NPEDL_EXCTL_CMD_WR_INS_MEM,
- insMemAddress, insMemData);
- if (verify)
- {
- /* write invalid data to this reg, so we can see if we're reading
- the EXDATA register too early */
- IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA,
- ~insMemData);
-
- /*Disabled since top 3 MSB are not used for Azusa hardware Refer WR:IXA00053900*/
- insMemData&=IX_NPEDL_MASK_UNUSED_IMEM_BITS;
-
- insMemDataRtn=ixNpeDlNpeMgrReadCommandIssue (npeBaseAddress,
- IX_NPEDL_EXCTL_CMD_RD_INS_MEM,
- insMemAddress);
-
- insMemDataRtn&=IX_NPEDL_MASK_UNUSED_IMEM_BITS;
-
- if (insMemData != insMemDataRtn)
- {
- ixNpeDlNpeMgrUtilsStats.insMemWriteFails++;
- return IX_FAIL;
- }
- }
-
- ixNpeDlNpeMgrUtilsStats.insMemWrites++;
- return IX_SUCCESS;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrDataMemWrite
- */
-IX_STATUS
-ixNpeDlNpeMgrDataMemWrite (
- UINT32 npeBaseAddress,
- UINT32 dataMemAddress,
- UINT32 dataMemData,
- BOOL verify)
-{
- ixNpeDlNpeMgrWriteCommandIssue (npeBaseAddress,
- IX_NPEDL_EXCTL_CMD_WR_DATA_MEM,
- dataMemAddress, dataMemData);
- if (verify)
- {
- /* write invalid data to this reg, so we can see if we're reading
- the EXDATA register too early */
- IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, ~dataMemData);
-
- if (dataMemData !=
- ixNpeDlNpeMgrReadCommandIssue (npeBaseAddress,
- IX_NPEDL_EXCTL_CMD_RD_DATA_MEM,
- dataMemAddress))
- {
- ixNpeDlNpeMgrUtilsStats.dataMemWriteFails++;
- return IX_FAIL;
- }
- }
-
- ixNpeDlNpeMgrUtilsStats.dataMemWrites++;
- return IX_SUCCESS;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrExecAccRegWrite
- */
-void
-ixNpeDlNpeMgrExecAccRegWrite (
- UINT32 npeBaseAddress,
- UINT32 regAddress,
- UINT32 regData)
-{
- ixNpeDlNpeMgrWriteCommandIssue (npeBaseAddress,
- IX_NPEDL_EXCTL_CMD_WR_ECS_REG,
- regAddress, regData);
- ixNpeDlNpeMgrUtilsStats.ecsRegWrites++;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrExecAccRegRead
- */
-UINT32
-ixNpeDlNpeMgrExecAccRegRead (
- UINT32 npeBaseAddress,
- UINT32 regAddress)
-{
- ixNpeDlNpeMgrUtilsStats.ecsRegReads++;
- return ixNpeDlNpeMgrReadCommandIssue (npeBaseAddress,
- IX_NPEDL_EXCTL_CMD_RD_ECS_REG,
- regAddress);
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrCommandIssue
- */
-void
-ixNpeDlNpeMgrCommandIssue (
- UINT32 npeBaseAddress,
- UINT32 command)
-{
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlNpeMgrCommandIssue\n");
-
- IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, command);
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlNpeMgrCommandIssue\n");
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrDebugInstructionPreExec
- */
-void
-ixNpeDlNpeMgrDebugInstructionPreExec(
- UINT32 npeBaseAddress)
-{
- /* turn off the halt bit by clearing Execution Count register. */
- /* save reg contents 1st and restore later */
- IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCT,
- &ixNpeDlSavedExecCount);
- IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCT, 0);
-
- /* ensure that IF and IE are on (temporarily), so that we don't end up
- * stepping forever */
- ixNpeDlSavedEcsDbgCtxtReg2 = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
- IX_NPEDL_ECS_DBG_CTXT_REG_2);
-
- ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_2,
- (ixNpeDlSavedEcsDbgCtxtReg2 |
- IX_NPEDL_MASK_ECS_DBG_REG_2_IF |
- IX_NPEDL_MASK_ECS_DBG_REG_2_IE));
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrDebugInstructionExec
- */
-IX_STATUS
-ixNpeDlNpeMgrDebugInstructionExec(
- UINT32 npeBaseAddress,
- UINT32 npeInstruction,
- UINT32 ctxtNum,
- UINT32 ldur)
-{
- UINT32 ecsDbgRegVal;
- UINT32 oldWatchcount, newWatchcount;
- UINT32 retriesCount = 0;
- IX_STATUS status = IX_SUCCESS;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlNpeMgrDebugInstructionExec\n");
-
- /* set the Active bit, and the LDUR, in the debug level */
- ecsDbgRegVal = IX_NPEDL_MASK_ECS_REG_0_ACTIVE |
- (ldur << IX_NPEDL_OFFSET_ECS_REG_0_LDUR);
-
- ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_0,
- ecsDbgRegVal);
-
- /*
- * set CCTXT at ECS DEBUG L3 to specify in which context to execute the
- * instruction, and set SELCTXT at ECS DEBUG Level to specify which context
- * store to access.
- * Debug ECS Level Reg 1 has form 0x000n000n, where n = context number
- */
- ecsDbgRegVal = (ctxtNum << IX_NPEDL_OFFSET_ECS_REG_1_CCTXT) |
- (ctxtNum << IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT);
-
- ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_1,
- ecsDbgRegVal);
-
- /* clear the pipeline */
- ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE);
-
- /* load NPE instruction into the instruction register */
- ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_INSTRUCT_REG,
- npeInstruction);
-
- /* we need this value later to wait for completion of NPE execution step */
- IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC, &oldWatchcount);
-
- /* issue a Step One command via the Execution Control register */
- ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_STEP);
-
- /* Watch Count register increments when NPE completes an instruction */
- IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC,
- &newWatchcount);
-
- /*
- * force the XScale to wait until the NPE has finished execution step
- * NOTE that this delay will be very small, just long enough to allow a
- * single NPE instruction to complete execution; if instruction execution
- * is not completed before timeout retries, exit the while loop
- */
- while ((IX_NPE_DL_MAX_NUM_OF_RETRIES > retriesCount)
- && (newWatchcount == oldWatchcount))
- {
- /* Watch Count register increments when NPE completes an instruction */
- IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC,
- &newWatchcount);
-
- retriesCount++;
- }
-
- if (IX_NPE_DL_MAX_NUM_OF_RETRIES > retriesCount)
- {
- ixNpeDlNpeMgrUtilsStats.dbgInstructionExecs++;
- }
- else
- {
- /* Return timeout status as the instruction has not been executed
- * after maximum retries */
- status = IX_NPEDL_CRITICAL_NPE_ERR;
- }
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlNpeMgrDebugInstructionExec\n");
-
- return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrDebugInstructionPostExec
- */
-void
-ixNpeDlNpeMgrDebugInstructionPostExec(
- UINT32 npeBaseAddress)
-{
- /* clear active bit in debug level */
- ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_0,
- 0);
-
- /* clear the pipeline */
- ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE);
-
- /* restore Execution Count register contents. */
- IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCT,
- ixNpeDlSavedExecCount);
-
- /* restore IF and IE bits to original values */
- ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_2,
- ixNpeDlSavedEcsDbgCtxtReg2);
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrLogicalRegRead
- */
-PRIVATE IX_STATUS
-ixNpeDlNpeMgrLogicalRegRead (
- UINT32 npeBaseAddress,
- UINT32 regAddr,
- UINT32 regSize,
- UINT32 ctxtNum,
- UINT32 *regVal)
-{
- IX_STATUS status = IX_SUCCESS;
- UINT32 npeInstruction = 0;
- UINT32 mask = 0;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlNpeMgrLogicalRegRead\n");
-
- switch (regSize)
- {
- case IX_NPEDL_REG_SIZE_BYTE:
- npeInstruction = IX_NPEDL_INSTR_RD_REG_BYTE;
- mask = IX_NPEDL_MASK_LOWER_BYTE_OF_WORD; break;
- case IX_NPEDL_REG_SIZE_SHORT:
- npeInstruction = IX_NPEDL_INSTR_RD_REG_SHORT;
- mask = IX_NPEDL_MASK_LOWER_SHORT_OF_WORD; break;
- case IX_NPEDL_REG_SIZE_WORD:
- npeInstruction = IX_NPEDL_INSTR_RD_REG_WORD;
- mask = IX_NPEDL_MASK_FULL_WORD; break;
- }
-
- /* make regAddr be the SRC and DEST operands (e.g. movX d0, d0) */
- npeInstruction |= (regAddr << IX_NPEDL_OFFSET_INSTR_SRC) |
- (regAddr << IX_NPEDL_OFFSET_INSTR_DEST);
-
- /* step execution of NPE intruction using Debug Executing Context stack */
- status = ixNpeDlNpeMgrDebugInstructionExec (npeBaseAddress, npeInstruction,
- ctxtNum, IX_NPEDL_RD_INSTR_LDUR);
-
- if (IX_SUCCESS != status)
- {
- return status;
- }
-
- /* read value of register from Execution Data register */
- IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, regVal);
-
- /* align value from left to right */
- *regVal = (*regVal >> (IX_NPEDL_REG_SIZE_WORD - regSize)) & mask;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlNpeMgrLogicalRegRead\n");
-
- return IX_SUCCESS;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrLogicalRegWrite
- */
-PRIVATE IX_STATUS
-ixNpeDlNpeMgrLogicalRegWrite (
- UINT32 npeBaseAddress,
- UINT32 regAddr,
- UINT32 regVal,
- UINT32 regSize,
- UINT32 ctxtNum,
- BOOL verify)
-{
- UINT32 npeInstruction = 0;
- UINT32 mask = 0;
- IX_STATUS status = IX_SUCCESS;
- UINT32 retRegVal;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlNpeMgrLogicalRegWrite\n");
-
- if (regSize == IX_NPEDL_REG_SIZE_WORD)
- {
- /* NPE register addressing is left-to-right: e.g. |d0|d1|d2|d3| */
- /* Write upper half-word (short) to |d0|d1| */
- status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, regAddr,
- regVal >> IX_NPEDL_REG_SIZE_SHORT,
- IX_NPEDL_REG_SIZE_SHORT,
- ctxtNum, verify);
-
- if (IX_SUCCESS != status)
- {
- return status;
- }
-
- /* Write lower half-word (short) to |d2|d3| */
- status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress,
- regAddr + IX_NPEDL_BYTES_PER_SHORT,
- regVal & IX_NPEDL_MASK_LOWER_SHORT_OF_WORD,
- IX_NPEDL_REG_SIZE_SHORT,
- ctxtNum, verify);
-
- if (IX_SUCCESS != status)
- {
- return status;
- }
- }
- else
- {
- switch (regSize)
- {
- case IX_NPEDL_REG_SIZE_BYTE:
- npeInstruction = IX_NPEDL_INSTR_WR_REG_BYTE;
- mask = IX_NPEDL_MASK_LOWER_BYTE_OF_WORD; break;
- case IX_NPEDL_REG_SIZE_SHORT:
- npeInstruction = IX_NPEDL_INSTR_WR_REG_SHORT;
- mask = IX_NPEDL_MASK_LOWER_SHORT_OF_WORD; break;
- }
- /* mask out any redundant bits, so verify will work later */
- regVal &= mask;
-
- /* fill dest operand field of instruction with destination reg addr */
- npeInstruction |= (regAddr << IX_NPEDL_OFFSET_INSTR_DEST);
-
- /* fill src operand field of instruction with least-sig 5 bits of val*/
- npeInstruction |= ((regVal & IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA) <<
- IX_NPEDL_OFFSET_INSTR_SRC);
-
- /* fill coprocessor field of instruction with most-sig 11 bits of val*/
- npeInstruction |= ((regVal & IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA) <<
- IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA);
-
- /* step execution of NPE intruction using Debug ECS */
- status = ixNpeDlNpeMgrDebugInstructionExec(npeBaseAddress, npeInstruction,
- ctxtNum, IX_NPEDL_WR_INSTR_LDUR);
-
- if (IX_SUCCESS != status)
- {
- return status;
- }
- }/* condition: if reg to be written is 8-bit or 16-bit (not 32-bit) */
-
- if (verify)
- {
- status = ixNpeDlNpeMgrLogicalRegRead (npeBaseAddress, regAddr,
- regSize, ctxtNum, &retRegVal);
-
- if (IX_SUCCESS == status)
- {
- if (regVal != retRegVal)
- {
- status = IX_FAIL;
- }
- }
- }
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlNpeMgrLogicalRegWrite : status = %d\n",
- status);
-
- return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrPhysicalRegWrite
- */
-IX_STATUS
-ixNpeDlNpeMgrPhysicalRegWrite (
- UINT32 npeBaseAddress,
- UINT32 regAddr,
- UINT32 regValue,
- BOOL verify)
-{
- IX_STATUS status;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlNpeMgrPhysicalRegWrite\n");
-
-/*
- * There are 32 physical registers used in an NPE. These are
- * treated as 16 pairs of 32-bit registers. To write one of the pair,
- * write the pair number (0-16) to the REGMAP for Context 0. Then write
- * the value to register 0 or 4 in the regfile, depending on which
- * register of the pair is to be written
- */
-
- /*
- * set REGMAP for context 0 to (regAddr >> 1) to choose which pair (0-16)
- * of physical registers to write
- */
- status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress,
- IX_NPEDL_CTXT_REG_ADDR_REGMAP,
- (regAddr >>
- IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP),
- IX_NPEDL_REG_SIZE_SHORT, 0, verify);
- if (status == IX_SUCCESS)
- {
- /* regAddr = 0 or 4 */
- regAddr = (regAddr & IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR) *
- IX_NPEDL_BYTES_PER_WORD;
-
- status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, regAddr, regValue,
- IX_NPEDL_REG_SIZE_WORD, 0, verify);
- }
-
- if (status != IX_SUCCESS)
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrPhysicalRegWrite: "
- "error writing to physical register\n");
- }
-
- ixNpeDlNpeMgrUtilsStats.physicalRegWrites++;
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlNpeMgrPhysicalRegWrite : status = %d\n",
- status);
- return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrCtxtRegWrite
- */
-IX_STATUS
-ixNpeDlNpeMgrCtxtRegWrite (
- UINT32 npeBaseAddress,
- UINT32 ctxtNum,
- IxNpeDlCtxtRegNum ctxtReg,
- UINT32 ctxtRegVal,
- BOOL verify)
-{
- UINT32 tempRegVal;
- UINT32 ctxtRegAddr;
- UINT32 ctxtRegSize;
- IX_STATUS status = IX_SUCCESS;
-
- IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
- "Entering ixNpeDlNpeMgrCtxtRegWrite\n");
-
- /*
- * Context 0 has no STARTPC. Instead, this value is used to set
- * NextPC for Background ECS, to set where NPE starts executing code
- */
- if ((ctxtNum == 0) && (ctxtReg == IX_NPEDL_CTXT_REG_STARTPC))
- {
- /* read BG_CTXT_REG_0, update NEXTPC bits, and write back to reg */
- tempRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
- IX_NPEDL_ECS_BG_CTXT_REG_0);
- tempRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_NEXTPC;
- tempRegVal |= (ctxtRegVal << IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC) &
- IX_NPEDL_MASK_ECS_REG_0_NEXTPC;
-
- ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress,
- IX_NPEDL_ECS_BG_CTXT_REG_0, tempRegVal);
-
- ixNpeDlNpeMgrUtilsStats.nextPcWrites++;
- }
- else
- {
- ctxtRegAddr = ixNpeDlCtxtRegAccInfo[ctxtReg].regAddress;
- ctxtRegSize = ixNpeDlCtxtRegAccInfo[ctxtReg].regSize;
- status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, ctxtRegAddr,
- ctxtRegVal, ctxtRegSize,
- ctxtNum, verify);
- if (status != IX_SUCCESS)
- {
- IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrCtxtRegWrite: "
- "error writing to context store register\n");
- }
-
- ixNpeDlNpeMgrUtilsStats.contextRegWrites++;
- }
-
- IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
- "Exiting ixNpeDlNpeMgrCtxtRegWrite : status = %d\n",
- status);
-
- return status;
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrUtilsStatsShow
- */
-void
-ixNpeDlNpeMgrUtilsStatsShow (void)
-{
- ixOsalLog (IX_OSAL_LOG_LVL_USER,
- IX_OSAL_LOG_DEV_STDOUT,
- "\nixNpeDlNpeMgrUtilsStatsShow:\n"
- "\tInstruction Memory writes: %u\n"
- "\tInstruction Memory writes failed: %u\n"
- "\tData Memory writes: %u\n"
- "\tData Memory writes failed: %u\n",
- ixNpeDlNpeMgrUtilsStats.insMemWrites,
- ixNpeDlNpeMgrUtilsStats.insMemWriteFails,
- ixNpeDlNpeMgrUtilsStats.dataMemWrites,
- ixNpeDlNpeMgrUtilsStats.dataMemWriteFails,
- 0,0);
-
- ixOsalLog (IX_OSAL_LOG_LVL_USER,
- IX_OSAL_LOG_DEV_STDOUT,
- "\tExecuting Context Stack Register writes: %u\n"
- "\tExecuting Context Stack Register reads: %u\n"
- "\tPhysical Register writes: %u\n"
- "\tContext Store Register writes: %u\n"
- "\tExecution Backgound Context NextPC writes: %u\n"
- "\tDebug Instructions Executed: %u\n\n",
- ixNpeDlNpeMgrUtilsStats.ecsRegWrites,
- ixNpeDlNpeMgrUtilsStats.ecsRegReads,
- ixNpeDlNpeMgrUtilsStats.physicalRegWrites,
- ixNpeDlNpeMgrUtilsStats.contextRegWrites,
- ixNpeDlNpeMgrUtilsStats.nextPcWrites,
- ixNpeDlNpeMgrUtilsStats.dbgInstructionExecs);
-}
-
-
-/*
- * Function definition: ixNpeDlNpeMgrUtilsStatsReset
- */
-void
-ixNpeDlNpeMgrUtilsStatsReset (void)
-{
- ixNpeDlNpeMgrUtilsStats.insMemWrites = 0;
- ixNpeDlNpeMgrUtilsStats.insMemWriteFails = 0;
- ixNpeDlNpeMgrUtilsStats.dataMemWrites = 0;
- ixNpeDlNpeMgrUtilsStats.dataMemWriteFails = 0;
- ixNpeDlNpeMgrUtilsStats.ecsRegWrites = 0;
- ixNpeDlNpeMgrUtilsStats.ecsRegReads = 0;
- ixNpeDlNpeMgrUtilsStats.physicalRegWrites = 0;
- ixNpeDlNpeMgrUtilsStats.contextRegWrites = 0;
- ixNpeDlNpeMgrUtilsStats.nextPcWrites = 0;
- ixNpeDlNpeMgrUtilsStats.dbgInstructionExecs = 0;
-}
+++ /dev/null
-/**
- * @file IxNpeMh.c
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the implementation of the public API for the
- * IXP425 NPE Message Handler component.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * Put the system defined include files required.
- */
-
-/*
- * Put the user defined include files required.
- */
-
-#include "IxOsal.h"
-#include "IxNpeMhMacros_p.h"
-
-#include "IxNpeMh.h"
-
-#include "IxNpeMhConfig_p.h"
-#include "IxNpeMhReceive_p.h"
-#include "IxNpeMhSend_p.h"
-#include "IxNpeMhSolicitedCbMgr_p.h"
-#include "IxNpeMhUnsolicitedCbMgr_p.h"
-
-/*
- * #defines and macros used in this file.
- */
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/*
- * Variable declarations global to this file only. Externs are followed by
- * static variables.
- */
-
-PRIVATE BOOL ixNpeMhInitialized = FALSE;
-
-/*
- * Extern function prototypes.
- */
-
-/*
- * Static function prototypes.
- */
-
-/*
- * Function definition: ixNpeMhInitialize
- */
-
-PUBLIC IX_STATUS ixNpeMhInitialize (
- IxNpeMhNpeInterrupts npeInterrupts)
-{
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhInitialize\n");
-
- /* check the npeInterrupts parameter */
- if ((npeInterrupts != IX_NPEMH_NPEINTERRUPTS_NO) &&
- (npeInterrupts != IX_NPEMH_NPEINTERRUPTS_YES))
- {
- IX_NPEMH_ERROR_REPORT ("Illegal npeInterrupts parameter value\n");
- return IX_FAIL;
- }
-
- /* parameters are ok ... */
-
- /* initialize the Receive module */
- ixNpeMhReceiveInitialize ();
-
- /* initialize the Solicited Callback Manager module */
- ixNpeMhSolicitedCbMgrInitialize ();
-
- /* initialize the Unsolicited Callback Manager module */
- ixNpeMhUnsolicitedCbMgrInitialize ();
-
- /* initialize the Configuration module
- *
- * NOTE: This module was originally configured before the
- * others, but the sequence was changed so that interrupts
- * would only be enabled after the handler functions were
- * set up. The above modules need to be initialised to
- * handle the NPE interrupts. See SCR #2231.
- */
- ixNpeMhConfigInitialize (npeInterrupts);
-
- ixNpeMhInitialized = TRUE;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhInitialize\n");
-
- return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeMhUnload
- */
-
-PUBLIC IX_STATUS ixNpeMhUnload (void)
-{
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhUnload\n");
-
- if (!ixNpeMhInitialized)
- {
- return IX_FAIL;
- }
-
- /* Uninitialize the Configuration module */
- ixNpeMhConfigUninit ();
-
- ixNpeMhInitialized = FALSE;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhUnload\n");
-
- return IX_SUCCESS;
-}
-
-
-/*
- * Function definition: ixNpeMhUnsolicitedCallbackRegister
- */
-
-PUBLIC IX_STATUS ixNpeMhUnsolicitedCallbackRegister (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId messageId,
- IxNpeMhCallback unsolicitedCallback)
-{
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhUnsolicitedCallbackRegister\n");
-
- /* check that we are initialized */
- if (!ixNpeMhInitialized)
- {
- IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n");
- return IX_FAIL;
- }
-
- /* check the npeId parameter */
- if (!ixNpeMhConfigNpeIdIsValid (npeId))
- {
- IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n");
- return IX_FAIL;
- }
-
- /* check the messageId parameter */
- if ((messageId < IX_NPEMH_MIN_MESSAGE_ID)
- || (messageId > IX_NPEMH_MAX_MESSAGE_ID))
- {
- IX_NPEMH_ERROR_REPORT ("Message ID is out of range\n");
- return IX_FAIL;
- }
-
- /* the unsolicitedCallback parameter is allowed to be NULL */
-
- /* parameters are ok ... */
-
- /* get the lock to prevent other clients from entering */
- ixNpeMhConfigLockGet (npeId);
-
- /* save the unsolicited callback for the message ID */
- ixNpeMhUnsolicitedCbMgrCallbackSave (
- npeId, messageId, unsolicitedCallback);
-
- /* release the lock to allow other clients back in */
- ixNpeMhConfigLockRelease (npeId);
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhUnsolicitedCallbackRegister\n");
-
- return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeMhUnsolicitedCallbackForRangeRegister
- */
-
-PUBLIC IX_STATUS ixNpeMhUnsolicitedCallbackForRangeRegister (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId minMessageId,
- IxNpeMhMessageId maxMessageId,
- IxNpeMhCallback unsolicitedCallback)
-{
- IxNpeMhMessageId messageId;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhUnsolicitedCallbackForRangeRegister\n");
-
- /* check that we are initialized */
- if (!ixNpeMhInitialized)
- {
- IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n");
- return IX_FAIL;
- }
-
- /* check the npeId parameter */
- if (!ixNpeMhConfigNpeIdIsValid (npeId))
- {
- IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n");
- return IX_FAIL;
- }
-
- /* check the minMessageId parameter */
- if ((minMessageId < IX_NPEMH_MIN_MESSAGE_ID)
- || (minMessageId > IX_NPEMH_MAX_MESSAGE_ID))
- {
- IX_NPEMH_ERROR_REPORT ("Min message ID is out of range\n");
- return IX_FAIL;
- }
-
- /* check the maxMessageId parameter */
- if ((maxMessageId < IX_NPEMH_MIN_MESSAGE_ID)
- || (maxMessageId > IX_NPEMH_MAX_MESSAGE_ID))
- {
- IX_NPEMH_ERROR_REPORT ("Max message ID is out of range\n");
- return IX_FAIL;
- }
-
- /* check the semantics of the message range parameters */
- if (minMessageId > maxMessageId)
- {
- IX_NPEMH_ERROR_REPORT ("Min message ID greater than max message "
- "ID\n");
- return IX_FAIL;
- }
-
- /* the unsolicitedCallback parameter is allowed to be NULL */
-
- /* parameters are ok ... */
-
- /* get the lock to prevent other clients from entering */
- ixNpeMhConfigLockGet (npeId);
-
- /* for each message ID in the range ... */
- for (messageId = minMessageId; messageId <= maxMessageId; messageId++)
- {
- /* save the unsolicited callback for the message ID */
- ixNpeMhUnsolicitedCbMgrCallbackSave (
- npeId, messageId, unsolicitedCallback);
- }
-
- /* release the lock to allow other clients back in */
- ixNpeMhConfigLockRelease (npeId);
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhUnsolicitedCallbackForRangeRegister\n");
-
- return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeMhMessageSend
- */
-
-PUBLIC IX_STATUS ixNpeMhMessageSend (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage message,
- UINT32 maxSendRetries)
-{
- IX_STATUS status = IX_SUCCESS;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhMessageSend\n");
-
- /* check that we are initialized */
- if (!ixNpeMhInitialized)
- {
- IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n");
- return IX_FAIL;
- }
-
- /* check the npeId parameter */
- if (!ixNpeMhConfigNpeIdIsValid (npeId))
- {
- IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n");
- return IX_FAIL;
- }
-
- /* parameters are ok ... */
-
- /* get the lock to prevent other clients from entering */
- ixNpeMhConfigLockGet (npeId);
-
- /* send the message */
- status = ixNpeMhSendMessageSend (npeId, message, maxSendRetries);
- if (status != IX_SUCCESS)
- {
- IX_NPEMH_ERROR_REPORT ("Failed to send message\n");
- }
-
- /* release the lock to allow other clients back in */
- ixNpeMhConfigLockRelease (npeId);
-
- IX_NPEMH_TRACE1 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhMessageSend"
- " : status = %d\n", status);
-
- return status;
-}
-
-/*
- * Function definition: ixNpeMhMessageWithResponseSend
- */
-
-PUBLIC IX_STATUS ixNpeMhMessageWithResponseSend (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage message,
- IxNpeMhMessageId solicitedMessageId,
- IxNpeMhCallback solicitedCallback,
- UINT32 maxSendRetries)
-{
- IX_STATUS status = IX_SUCCESS;
- IxNpeMhCallback unsolicitedCallback = NULL;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhMessageWithResponseSend\n");
-
- /* check that we are initialized */
- if (!ixNpeMhInitialized)
- {
- IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n");
- return IX_FAIL;
- }
-
- /* the solicitecCallback parameter is allowed to be NULL. this */
- /* signifies the client is not interested in the response message */
-
- /* check the npeId parameter */
- if (!ixNpeMhConfigNpeIdIsValid (npeId))
- {
- IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n");
- return IX_FAIL;
- }
-
- /* check the solicitedMessageId parameter */
- if ((solicitedMessageId < IX_NPEMH_MIN_MESSAGE_ID)
- || (solicitedMessageId > IX_NPEMH_MAX_MESSAGE_ID))
- {
- IX_NPEMH_ERROR_REPORT ("Solicited message ID is out of range\n");
- return IX_FAIL;
- }
-
- /* check the solicitedMessageId parameter. if an unsolicited */
- /* callback has been registered for the specified message ID then */
- /* report an error and return failure */
- ixNpeMhUnsolicitedCbMgrCallbackRetrieve (
- npeId, solicitedMessageId, &unsolicitedCallback);
- if (unsolicitedCallback != NULL)
- {
- IX_NPEMH_ERROR_REPORT ("Solicited message ID conflicts with "
- "unsolicited message ID\n");
- return IX_FAIL;
- }
-
- /* parameters are ok ... */
-
- /* get the lock to prevent other clients from entering */
- ixNpeMhConfigLockGet (npeId);
-
- /* send the message */
- status = ixNpeMhSendMessageWithResponseSend (
- npeId, message, solicitedMessageId, solicitedCallback,
- maxSendRetries);
- if (status != IX_SUCCESS)
- {
- IX_NPEMH_ERROR_REPORT ("Failed to send message\n");
- }
-
- /* release the lock to allow other clients back in */
- ixNpeMhConfigLockRelease (npeId);
-
- IX_NPEMH_TRACE1 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhMessageWithResponseSend"
- " : status = %d\n", status);
-
- return status;
-}
-
-/*
- * Function definition: ixNpeMhMessagesReceive
- */
-
-PUBLIC IX_STATUS ixNpeMhMessagesReceive (
- IxNpeMhNpeId npeId)
-{
- IX_STATUS status = IX_SUCCESS;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhMessagesReceive\n");
-
- /* check that we are initialized */
- if (!ixNpeMhInitialized)
- {
- IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n");
- return IX_FAIL;
- }
-
- /* check the npeId parameter */
- if (!ixNpeMhConfigNpeIdIsValid (npeId))
- {
- IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n");
- return IX_FAIL;
- }
-
- /* parameters are ok ... */
-
- /* get the lock to prevent other clients from entering */
- ixNpeMhConfigLockGet (npeId);
-
- /* receive messages from the NPE */
- status = ixNpeMhReceiveMessagesReceive (npeId);
-
- if (status != IX_SUCCESS)
- {
- IX_NPEMH_ERROR_REPORT ("Failed to receive message\n");
- }
-
- /* release the lock to allow other clients back in */
- ixNpeMhConfigLockRelease (npeId);
-
- IX_NPEMH_TRACE1 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhMessagesReceive"
- " : status = %d\n", status);
-
- return status;
-}
-
-/*
- * Function definition: ixNpeMhShow
- */
-
-PUBLIC IX_STATUS ixNpeMhShow (
- IxNpeMhNpeId npeId)
-{
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhShow\n");
-
- /* check that we are initialized */
- if (!ixNpeMhInitialized)
- {
- IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n");
- return IX_FAIL;
- }
-
- /* check the npeId parameter */
- if (!ixNpeMhConfigNpeIdIsValid (npeId))
- {
- IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n");
- return IX_FAIL;
- }
-
- /* parameters are ok ... */
-
- /* note we don't get the lock here as printing the statistics */
- /* to a console may take some time and we don't want to impact */
- /* system performance. this means that the statistics displayed */
- /* may be in a state of flux and make not represent a consistent */
- /* snapshot. */
-
- /* display a header */
- ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT,
- "Current state of NPE ID %d:\n\n", npeId, 0, 0, 0, 0, 0);
-
- /* show the current state of each module */
-
- /* show the current state of the Configuration module */
- ixNpeMhConfigShow (npeId);
-
- /* show the current state of the Receive module */
- ixNpeMhReceiveShow (npeId);
-
- /* show the current state of the Send module */
- ixNpeMhSendShow (npeId);
-
- /* show the current state of the Solicited Callback Manager module */
- ixNpeMhSolicitedCbMgrShow (npeId);
-
- /* show the current state of the Unsolicited Callback Manager module */
- ixNpeMhUnsolicitedCbMgrShow (npeId);
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhShow\n");
-
- return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeMhShowReset
- */
-
-PUBLIC IX_STATUS ixNpeMhShowReset (
- IxNpeMhNpeId npeId)
-{
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhShowReset\n");
-
- /* check that we are initialized */
- if (!ixNpeMhInitialized)
- {
- IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n");
- return IX_FAIL;
- }
-
- /* check the npeId parameter */
- if (!ixNpeMhConfigNpeIdIsValid (npeId))
- {
- IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n");
- return IX_FAIL;
- }
-
- /* parameters are ok ... */
-
- /* note we don't get the lock here as resetting the statistics */
- /* shouldn't impact system performance. */
-
- /* reset the current state of each module */
-
- /* reset the current state of the Configuration module */
- ixNpeMhConfigShowReset (npeId);
-
- /* reset the current state of the Receive module */
- ixNpeMhReceiveShowReset (npeId);
-
- /* reset the current state of the Send module */
- ixNpeMhSendShowReset (npeId);
-
- /* reset the current state of the Solicited Callback Manager module */
- ixNpeMhSolicitedCbMgrShowReset (npeId);
-
- /* reset the current state of the Unsolicited Callback Manager module */
- ixNpeMhUnsolicitedCbMgrShowReset (npeId);
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhShowReset\n");
-
- return IX_SUCCESS;
-}
+++ /dev/null
-/**
- * @file IxNpeMhConfig.c
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the implementation of the private API for the
- * Configuration module.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * Put the system defined include files required.
- */
-
-
-/*
- * Put the user defined include files required.
- */
-
-#include "IxOsal.h"
-
-#include "IxNpeMhMacros_p.h"
-
-#include "IxNpeMhConfig_p.h"
-
-/*
- * #defines and macros used in this file.
- */
-#define IX_NPE_MH_MAX_NUM_OF_RETRIES 1000000 /**< Maximum number of
- * retries before
- * timeout
- */
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/**
- * @struct IxNpeMhConfigStats
- *
- * @brief This structure is used to maintain statistics for the
- * Configuration module.
- */
-
-typedef struct
-{
- UINT32 outFifoReads; /**< outFifo reads */
- UINT32 inFifoWrites; /**< inFifo writes */
- UINT32 maxInFifoFullRetries; /**< max retries if inFIFO full */
- UINT32 maxOutFifoEmptyRetries; /**< max retries if outFIFO empty */
-} IxNpeMhConfigStats;
-
-/*
- * Variable declarations global to this file only. Externs are followed by
- * static variables.
- */
-
-IxNpeMhConfigNpeInfo ixNpeMhConfigNpeInfo[IX_NPEMH_NUM_NPES] =
-{
- {
- 0,
- IX_NPEMH_NPEA_INT,
- 0,
- 0,
- 0,
- 0,
- 0,
- NULL,
- FALSE
- },
- {
- 0,
- IX_NPEMH_NPEB_INT,
- 0,
- 0,
- 0,
- 0,
- 0,
- NULL,
- FALSE
- },
- {
- 0,
- IX_NPEMH_NPEC_INT,
- 0,
- 0,
- 0,
- 0,
- 0,
- NULL,
- FALSE
- }
-};
-
-PRIVATE IxNpeMhConfigStats ixNpeMhConfigStats[IX_NPEMH_NUM_NPES];
-
-/*
- * Extern function prototypes.
- */
-
-/*
- * Static function prototypes.
- */
-PRIVATE
-void ixNpeMhConfigIsr (void *parameter);
-
-/*
- * Function definition: ixNpeMhConfigIsr
- */
-
-PRIVATE
-void ixNpeMhConfigIsr (void *parameter)
-{
- IxNpeMhNpeId npeId = (IxNpeMhNpeId)parameter;
- UINT32 ofint;
- volatile UINT32 *statusReg =
- (UINT32 *)ixNpeMhConfigNpeInfo[npeId].statusRegister;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhConfigIsr\n");
-
- /* get the OFINT (OutFifo interrupt) bit of the status register */
- IX_NPEMH_REGISTER_READ_BITS (statusReg, &ofint, IX_NPEMH_NPE_STAT_OFINT);
-
- /* if the OFINT status bit is set */
- if (ofint)
- {
- /* if there is an ISR registered for this NPE */
- if (ixNpeMhConfigNpeInfo[npeId].isr != NULL)
- {
- /* invoke the ISR routine */
- ixNpeMhConfigNpeInfo[npeId].isr (npeId);
- }
- else
- {
- /* if we don't service the interrupt the NPE will continue */
- /* to trigger the interrupt indefinitely */
- IX_NPEMH_ERROR_REPORT ("No ISR registered to service "
- "interrupt\n");
- }
- }
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhConfigIsr\n");
-}
-
-/*
- * Function definition: ixNpeMhConfigInitialize
- */
-
-void ixNpeMhConfigInitialize (
- IxNpeMhNpeInterrupts npeInterrupts)
-{
- IxNpeMhNpeId npeId;
- UINT32 virtualAddr[IX_NPEMH_NUM_NPES];
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhConfigInitialize\n");
-
- /* Request a mapping for the NPE-A config register address space */
- virtualAddr[IX_NPEMH_NPEID_NPEA] =
- (UINT32) IX_OSAL_MEM_MAP (IX_NPEMH_NPEA_BASE,
- IX_OSAL_IXP400_NPEA_MAP_SIZE);
- IX_OSAL_ASSERT (virtualAddr[IX_NPEMH_NPEID_NPEA]);
-
- /* Request a mapping for the NPE-B config register address space */
- virtualAddr[IX_NPEMH_NPEID_NPEB] =
- (UINT32) IX_OSAL_MEM_MAP (IX_NPEMH_NPEB_BASE,
- IX_OSAL_IXP400_NPEB_MAP_SIZE);
- IX_OSAL_ASSERT (virtualAddr[IX_NPEMH_NPEID_NPEB]);
-
- /* Request a mapping for the NPE-C config register address space */
- virtualAddr[IX_NPEMH_NPEID_NPEC] =
- (UINT32) IX_OSAL_MEM_MAP (IX_NPEMH_NPEC_BASE,
- IX_OSAL_IXP400_NPEC_MAP_SIZE);
- IX_OSAL_ASSERT (virtualAddr[IX_NPEMH_NPEID_NPEC]);
-
- /* for each NPE ... */
- for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++)
- {
- /* declare a convenience pointer */
- IxNpeMhConfigNpeInfo *npeInfo = &ixNpeMhConfigNpeInfo[npeId];
-
- /* store the virtual addresses of the NPE registers for later use */
- npeInfo->virtualRegisterBase = virtualAddr[npeId];
- npeInfo->statusRegister = virtualAddr[npeId] + IX_NPEMH_NPESTAT_OFFSET;
- npeInfo->controlRegister = virtualAddr[npeId] + IX_NPEMH_NPECTL_OFFSET;
- npeInfo->inFifoRegister = virtualAddr[npeId] + IX_NPEMH_NPEFIFO_OFFSET;
- npeInfo->outFifoRegister = virtualAddr[npeId] + IX_NPEMH_NPEFIFO_OFFSET;
-
- /* for test purposes - to verify the register addresses */
- IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d status register = "
- "0x%08X\n", npeId, npeInfo->statusRegister);
- IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d control register = "
- "0x%08X\n", npeId, npeInfo->controlRegister);
- IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d inFifo register = "
- "0x%08X\n", npeId, npeInfo->inFifoRegister);
- IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d outFifo register = "
- "0x%08X\n", npeId, npeInfo->outFifoRegister);
-
- /* connect our ISR to the NPE interrupt */
- (void) ixOsalIrqBind (
- npeInfo->interruptId, ixNpeMhConfigIsr, (void *)npeId);
-
- /* initialise a mutex for this NPE */
- (void) ixOsalMutexInit (&npeInfo->mutex);
-
- /* if we should service the NPE's "outFIFO not empty" interrupt */
- if (npeInterrupts == IX_NPEMH_NPEINTERRUPTS_YES)
- {
- /* enable the NPE's "outFIFO not empty" interrupt */
- ixNpeMhConfigNpeInterruptEnable (npeId);
- }
- else
- {
- /* disable the NPE's "outFIFO not empty" interrupt */
- ixNpeMhConfigNpeInterruptDisable (npeId);
- }
- }
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhConfigInitialize\n");
-}
-
-/*
- * Function definition: ixNpeMhConfigUninit
- */
-
-void ixNpeMhConfigUninit (void)
-{
- IxNpeMhNpeId npeId;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhConfigUninit\n");
-
- /* for each NPE ... */
- for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++)
- {
- /* declare a convenience pointer */
- IxNpeMhConfigNpeInfo *npeInfo = &ixNpeMhConfigNpeInfo[npeId];
-
- /* disconnect ISR */
- ixOsalIrqUnbind(npeInfo->interruptId);
-
- /* destroy mutex associated with this NPE */
- ixOsalMutexDestroy(&npeInfo->mutex);
-
- IX_OSAL_MEM_UNMAP (npeInfo->virtualRegisterBase);
-
- npeInfo->virtualRegisterBase = 0;
- npeInfo->statusRegister = 0;
- npeInfo->controlRegister = 0;
- npeInfo->inFifoRegister = 0;
- npeInfo->outFifoRegister = 0;
- }
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhConfigUninit\n");
-}
-
-/*
- * Function definition: ixNpeMhConfigIsrRegister
- */
-
-void ixNpeMhConfigIsrRegister (
- IxNpeMhNpeId npeId,
- IxNpeMhConfigIsr isr)
-{
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhConfigIsrRegister\n");
-
- /* check if there is already an ISR registered for this NPE */
- if (ixNpeMhConfigNpeInfo[npeId].isr != NULL)
- {
- IX_NPEMH_TRACE0 (IX_NPEMH_DEBUG, "Over-writing registered NPE ISR\n");
- }
-
- /* save the ISR routine with the NPE info */
- ixNpeMhConfigNpeInfo[npeId].isr = isr;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhConfigIsrRegister\n");
-}
-
-/*
- * Function definition: ixNpeMhConfigNpeInterruptEnable
- */
-
-BOOL ixNpeMhConfigNpeInterruptEnable (
- IxNpeMhNpeId npeId)
-{
- UINT32 ofe;
- volatile UINT32 *controlReg =
- (UINT32 *)ixNpeMhConfigNpeInfo[npeId].controlRegister;
-
- /* get the OFE (OutFifoEnable) bit of the control register */
- IX_NPEMH_REGISTER_READ_BITS (controlReg, &ofe, IX_NPEMH_NPE_CTL_OFE);
-
- /* if the interrupt is disabled then we must enable it */
- if (!ofe)
- {
- /* set the OFE (OutFifoEnable) bit of the control register */
- /* we must set the OFEWE (OutFifoEnableWriteEnable) at the same */
- /* time for the write to have effect */
- IX_NPEMH_REGISTER_WRITE_BITS (controlReg,
- (IX_NPEMH_NPE_CTL_OFE |
- IX_NPEMH_NPE_CTL_OFEWE),
- (IX_NPEMH_NPE_CTL_OFE |
- IX_NPEMH_NPE_CTL_OFEWE));
- }
-
- /* return the previous state of the interrupt */
- return (ofe != 0);
-}
-
-/*
- * Function definition: ixNpeMhConfigNpeInterruptDisable
- */
-
-BOOL ixNpeMhConfigNpeInterruptDisable (
- IxNpeMhNpeId npeId)
-{
- UINT32 ofe;
- volatile UINT32 *controlReg =
- (UINT32 *)ixNpeMhConfigNpeInfo[npeId].controlRegister;
-
- /* get the OFE (OutFifoEnable) bit of the control register */
- IX_NPEMH_REGISTER_READ_BITS (controlReg, &ofe, IX_NPEMH_NPE_CTL_OFE);
-
- /* if the interrupt is enabled then we must disable it */
- if (ofe)
- {
- /* unset the OFE (OutFifoEnable) bit of the control register */
- /* we must set the OFEWE (OutFifoEnableWriteEnable) at the same */
- /* time for the write to have effect */
- IX_NPEMH_REGISTER_WRITE_BITS (controlReg,
- (0 |
- IX_NPEMH_NPE_CTL_OFEWE),
- (IX_NPEMH_NPE_CTL_OFE |
- IX_NPEMH_NPE_CTL_OFEWE));
- }
-
- /* return the previous state of the interrupt */
- return (ofe != 0);
-}
-
-/*
- * Function definition: ixNpeMhConfigMessageIdGet
- */
-
-IxNpeMhMessageId ixNpeMhConfigMessageIdGet (
- IxNpeMhMessage message)
-{
- /* return the most-significant byte of the first word of the */
- /* message */
- return ((IxNpeMhMessageId) ((message.data[0] >> 24) & 0xFF));
-}
-
-/*
- * Function definition: ixNpeMhConfigNpeIdIsValid
- */
-
-BOOL ixNpeMhConfigNpeIdIsValid (
- IxNpeMhNpeId npeId)
-{
- /* check that the npeId parameter is within the range of valid IDs */
- return (npeId >= 0 && npeId < IX_NPEMH_NUM_NPES);
-}
-
-/*
- * Function definition: ixNpeMhConfigLockGet
- */
-
-void ixNpeMhConfigLockGet (
- IxNpeMhNpeId npeId)
-{
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhConfigLockGet\n");
-
- /* lock the mutex for this NPE */
- (void) ixOsalMutexLock (&ixNpeMhConfigNpeInfo[npeId].mutex,
- IX_OSAL_WAIT_FOREVER);
-
- /* disable the NPE's "outFIFO not empty" interrupt */
- ixNpeMhConfigNpeInfo[npeId].oldInterruptState =
- ixNpeMhConfigNpeInterruptDisable (npeId);
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhConfigLockGet\n");
-}
-
-/*
- * Function definition: ixNpeMhConfigLockRelease
- */
-
-void ixNpeMhConfigLockRelease (
- IxNpeMhNpeId npeId)
-{
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhConfigLockRelease\n");
-
- /* if the interrupt was previously enabled */
- if (ixNpeMhConfigNpeInfo[npeId].oldInterruptState)
- {
- /* enable the NPE's "outFIFO not empty" interrupt */
- ixNpeMhConfigNpeInfo[npeId].oldInterruptState =
- ixNpeMhConfigNpeInterruptEnable (npeId);
- }
-
- /* unlock the mutex for this NPE */
- (void) ixOsalMutexUnlock (&ixNpeMhConfigNpeInfo[npeId].mutex);
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhConfigLockRelease\n");
-}
-
-/*
- * Function definition: ixNpeMhConfigInFifoWrite
- */
-
-IX_STATUS ixNpeMhConfigInFifoWrite (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage message)
-{
- volatile UINT32 *npeInFifo =
- (UINT32 *)ixNpeMhConfigNpeInfo[npeId].inFifoRegister;
- UINT32 retriesCount = 0;
-
- /* write the first word of the message to the NPE's inFIFO */
- IX_NPEMH_REGISTER_WRITE (npeInFifo, message.data[0]);
-
- /* need to wait for room to write second word - see SCR #493,
- poll for maximum number of retries, if exceed maximum
- retries, exit from while loop */
- while ((IX_NPE_MH_MAX_NUM_OF_RETRIES > retriesCount)
- && ixNpeMhConfigInFifoIsFull (npeId))
- {
- retriesCount++;
- }
-
- /* Return TIMEOUT status to caller, indicate that NPE Hang / Halt */
- if (IX_NPE_MH_MAX_NUM_OF_RETRIES == retriesCount)
- {
- return IX_NPEMH_CRITICAL_NPE_ERR;
- }
-
- /* write the second word of the message to the NPE's inFIFO */
- IX_NPEMH_REGISTER_WRITE (npeInFifo, message.data[1]);
-
- /* record in the stats the maximum number of retries needed */
- if (ixNpeMhConfigStats[npeId].maxInFifoFullRetries < retriesCount)
- {
- ixNpeMhConfigStats[npeId].maxInFifoFullRetries = retriesCount;
- }
-
- /* update statistical info */
- ixNpeMhConfigStats[npeId].inFifoWrites++;
-
- return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeMhConfigOutFifoRead
- */
-
-IX_STATUS ixNpeMhConfigOutFifoRead (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage *message)
-{
- volatile UINT32 *npeOutFifo =
- (UINT32 *)ixNpeMhConfigNpeInfo[npeId].outFifoRegister;
- UINT32 retriesCount = 0;
-
- /* read the first word of the message from the NPE's outFIFO */
- IX_NPEMH_REGISTER_READ (npeOutFifo, &message->data[0]);
-
- /* need to wait for NPE to write second word - see SCR #493
- poll for maximum number of retries, if exceed maximum
- retries, exit from while loop */
- while ((IX_NPE_MH_MAX_NUM_OF_RETRIES > retriesCount)
- && ixNpeMhConfigOutFifoIsEmpty (npeId))
- {
- retriesCount++;
- }
-
- /* Return TIMEOUT status to caller, indicate that NPE Hang / Halt */
- if (IX_NPE_MH_MAX_NUM_OF_RETRIES == retriesCount)
- {
- return IX_NPEMH_CRITICAL_NPE_ERR;
- }
-
- /* read the second word of the message from the NPE's outFIFO */
- IX_NPEMH_REGISTER_READ (npeOutFifo, &message->data[1]);
-
- /* record in the stats the maximum number of retries needed */
- if (ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries < retriesCount)
- {
- ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries = retriesCount;
- }
-
- /* update statistical info */
- ixNpeMhConfigStats[npeId].outFifoReads++;
-
- return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeMhConfigShow
- */
-
-void ixNpeMhConfigShow (
- IxNpeMhNpeId npeId)
-{
- /* show the message fifo read counter */
- IX_NPEMH_SHOW ("Message FIFO reads",
- ixNpeMhConfigStats[npeId].outFifoReads);
-
- /* show the message fifo write counter */
- IX_NPEMH_SHOW ("Message FIFO writes",
- ixNpeMhConfigStats[npeId].inFifoWrites);
-
- /* show the max retries performed when inFIFO full */
- IX_NPEMH_SHOW ("Max inFIFO Full retries",
- ixNpeMhConfigStats[npeId].maxInFifoFullRetries);
-
- /* show the max retries performed when outFIFO empty */
- IX_NPEMH_SHOW ("Max outFIFO Empty retries",
- ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries);
-
- /* show the current status of the inFifo */
- ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT,
- "InFifo is %s and %s\n",
- (ixNpeMhConfigInFifoIsEmpty (npeId) ?
- (int) "EMPTY" : (int) "NOT EMPTY"),
- (ixNpeMhConfigInFifoIsFull (npeId) ?
- (int) "FULL" : (int) "NOT FULL"),
- 0, 0, 0, 0);
-
- /* show the current status of the outFifo */
- ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT,
- "OutFifo is %s and %s\n",
- (ixNpeMhConfigOutFifoIsEmpty (npeId) ?
- (int) "EMPTY" : (int) "NOT EMPTY"),
- (ixNpeMhConfigOutFifoIsFull (npeId) ?
- (int) "FULL" : (int) "NOT FULL"),
- 0, 0, 0, 0);
-}
-
-/*
- * Function definition: ixNpeMhConfigShowReset
- */
-
-void ixNpeMhConfigShowReset (
- IxNpeMhNpeId npeId)
-{
- /* reset the message fifo read counter */
- ixNpeMhConfigStats[npeId].outFifoReads = 0;
-
- /* reset the message fifo write counter */
- ixNpeMhConfigStats[npeId].inFifoWrites = 0;
-
- /* reset the max inFIFO Full retries counter */
- ixNpeMhConfigStats[npeId].maxInFifoFullRetries = 0;
-
- /* reset the max outFIFO empty retries counter */
- ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries = 0;
-}
-
-
+++ /dev/null
-/**
- * @file IxNpeMhReceive.c
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the implementation of the private API for the
- * Receive module.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * Put the system defined include files required.
- */
-
-
-/*
- * Put the user defined include files required.
- */
-#include "IxOsal.h"
-#include "IxNpeMhMacros_p.h"
-#include "IxNpeMhConfig_p.h"
-#include "IxNpeMhReceive_p.h"
-#include "IxNpeMhSolicitedCbMgr_p.h"
-#include "IxNpeMhUnsolicitedCbMgr_p.h"
-
-/*
- * #defines and macros used in this file.
- */
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/**
- * @struct IxNpeMhReceiveStats
- *
- * @brief This structure is used to maintain statistics for the Receive
- * module.
- */
-
-typedef struct
-{
- UINT32 isrs; /**< receive ISR invocations */
- UINT32 receives; /**< receive messages invocations */
- UINT32 messages; /**< messages received */
- UINT32 solicited; /**< solicited messages received */
- UINT32 unsolicited; /**< unsolicited messages received */
- UINT32 callbacks; /**< callbacks invoked */
-} IxNpeMhReceiveStats;
-
-/*
- * Variable declarations global to this file only. Externs are followed by
- * static variables.
- */
-
-PRIVATE IxNpeMhReceiveStats ixNpeMhReceiveStats[IX_NPEMH_NUM_NPES];
-
-/*
- * Extern function prototypes.
- */
-
-/*
- * Static function prototypes.
- */
-PRIVATE
-void ixNpeMhReceiveIsr (int npeId);
-
-PRIVATE
-void ixNpeMhReceiveIsr (int npeId)
-{
- int lockKey;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhReceiveIsr\n");
-
- lockKey = ixOsalIrqLock ();
-
- /* invoke the message receive routine to get messages from the NPE */
- ixNpeMhReceiveMessagesReceive (npeId);
-
- /* update statistical info */
- ixNpeMhReceiveStats[npeId].isrs++;
-
- ixOsalIrqUnlock (lockKey);
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhReceiveIsr\n");
-}
-
-/*
- * Function definition: ixNpeMhReceiveInitialize
- */
-
-void ixNpeMhReceiveInitialize (void)
-{
- IxNpeMhNpeId npeId = 0;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhReceiveInitialize\n");
-
- /* for each NPE ... */
- for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++)
- {
- /* register our internal ISR for the NPE to handle "outFIFO not */
- /* empty" interrupts */
- ixNpeMhConfigIsrRegister (npeId, ixNpeMhReceiveIsr);
- }
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhReceiveInitialize\n");
-}
-
-/*
- * Function definition: ixNpeMhReceiveMessagesReceive
- */
-
-IX_STATUS ixNpeMhReceiveMessagesReceive (
- IxNpeMhNpeId npeId)
-{
- IxNpeMhMessage message = { { 0, 0 } };
- IxNpeMhMessageId messageId = 0;
- IxNpeMhCallback callback = NULL;
- IX_STATUS status;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhReceiveMessagesReceive\n");
-
- /* update statistical info */
- ixNpeMhReceiveStats[npeId].receives++;
-
- /* while the NPE has messages in its outFIFO */
- while (!ixNpeMhConfigOutFifoIsEmpty (npeId))
- {
- /* read a message from the NPE's outFIFO */
- status = ixNpeMhConfigOutFifoRead (npeId, &message);
-
- if (IX_SUCCESS != status)
- {
- return status;
- }
-
- /* get the ID of the message */
- messageId = ixNpeMhConfigMessageIdGet (message);
-
- IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG,
- "Received message from NPE %d with ID 0x%02X\n",
- npeId, messageId);
-
- /* update statistical info */
- ixNpeMhReceiveStats[npeId].messages++;
-
- /* try to find a matching unsolicited callback for this message. */
-
- /* we assume the message is unsolicited. only if there is no */
- /* unsolicited callback for this message type do we assume the */
- /* message is solicited. it is much faster to check for an */
- /* unsolicited callback, so doing this check first should result */
- /* in better performance. */
-
- ixNpeMhUnsolicitedCbMgrCallbackRetrieve (
- npeId, messageId, &callback);
-
- if (callback != NULL)
- {
- IX_NPEMH_TRACE0 (IX_NPEMH_DEBUG,
- "Found matching unsolicited callback\n");
-
- /* update statistical info */
- ixNpeMhReceiveStats[npeId].unsolicited++;
- }
-
- /* if no unsolicited callback was found try to find a matching */
- /* solicited callback for this message */
- if (callback == NULL)
- {
- ixNpeMhSolicitedCbMgrCallbackRetrieve (
- npeId, messageId, &callback);
-
- if (callback != NULL)
- {
- IX_NPEMH_TRACE0 (IX_NPEMH_DEBUG,
- "Found matching solicited callback\n");
-
- /* update statistical info */
- ixNpeMhReceiveStats[npeId].solicited++;
- }
- }
-
- /* if a callback (either unsolicited or solicited) was found */
- if (callback != NULL)
- {
- /* invoke the callback to pass the message back to the client */
- callback (npeId, message);
-
- /* update statistical info */
- ixNpeMhReceiveStats[npeId].callbacks++;
- }
- else /* no callback (neither unsolicited nor solicited) was found */
- {
- IX_NPEMH_TRACE2 (IX_NPEMH_WARNING,
- "No matching callback for NPE %d"
- " and ID 0x%02X, discarding message\n",
- npeId, messageId);
-
- /* the message will be discarded. this is normal behaviour */
- /* if the client passes a NULL solicited callback when */
- /* sending a message. this indicates that the client is not */
- /* interested in receiving the response. alternatively a */
- /* NULL callback here may signify an unsolicited message */
- /* with no appropriate registered callback. */
- }
- }
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhReceiveMessagesReceive\n");
-
- return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeMhReceiveShow
- */
-
-void ixNpeMhReceiveShow (
- IxNpeMhNpeId npeId)
-{
- /* show the ISR invocation counter */
- IX_NPEMH_SHOW ("Receive ISR invocations",
- ixNpeMhReceiveStats[npeId].isrs);
-
- /* show the receive message invocation counter */
- IX_NPEMH_SHOW ("Receive messages invocations",
- ixNpeMhReceiveStats[npeId].receives);
-
- /* show the message received counter */
- IX_NPEMH_SHOW ("Messages received",
- ixNpeMhReceiveStats[npeId].messages);
-
- /* show the solicited message counter */
- IX_NPEMH_SHOW ("Solicited messages received",
- ixNpeMhReceiveStats[npeId].solicited);
-
- /* show the unsolicited message counter */
- IX_NPEMH_SHOW ("Unsolicited messages received",
- ixNpeMhReceiveStats[npeId].unsolicited);
-
- /* show the callback invoked counter */
- IX_NPEMH_SHOW ("Callbacks invoked",
- ixNpeMhReceiveStats[npeId].callbacks);
-
- /* show the message discarded counter */
- IX_NPEMH_SHOW ("Received messages discarded",
- (ixNpeMhReceiveStats[npeId].messages -
- ixNpeMhReceiveStats[npeId].callbacks));
-}
-
-/*
- * Function definition: ixNpeMhReceiveShowReset
- */
-
-void ixNpeMhReceiveShowReset (
- IxNpeMhNpeId npeId)
-{
- /* reset the ISR invocation counter */
- ixNpeMhReceiveStats[npeId].isrs = 0;
-
- /* reset the receive message invocation counter */
- ixNpeMhReceiveStats[npeId].receives = 0;
-
- /* reset the message received counter */
- ixNpeMhReceiveStats[npeId].messages = 0;
-
- /* reset the solicited message counter */
- ixNpeMhReceiveStats[npeId].solicited = 0;
-
- /* reset the unsolicited message counter */
- ixNpeMhReceiveStats[npeId].unsolicited = 0;
-
- /* reset the callback invoked counter */
- ixNpeMhReceiveStats[npeId].callbacks = 0;
-}
+++ /dev/null
-/**
- * @file IxNpeMhSend.c
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the implementation of the private API for the
- * Send module.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * Put the system defined include files required.
- */
-
-
-/*
- * Put the user defined include files required.
- */
-
-#include "IxNpeMhMacros_p.h"
-
-#include "IxNpeMhConfig_p.h"
-#include "IxNpeMhSend_p.h"
-#include "IxNpeMhSolicitedCbMgr_p.h"
-
-/*
- * #defines and macros used in this file.
- */
-
-/**
- * @def IX_NPEMH_INFIFO_RETRY_DELAY_US
- *
- * @brief Amount of time (uSecs) to delay between retries
- * while inFIFO is Full when attempting to send a message
- */
-#define IX_NPEMH_INFIFO_RETRY_DELAY_US (1)
-
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/**
- * @struct IxNpeMhSendStats
- *
- * @brief This structure is used to maintain statistics for the Send
- * module.
- */
-
-typedef struct
-{
- UINT32 sends; /**< send invocations */
- UINT32 sendWithResponses; /**< send with response invocations */
- UINT32 queueFulls; /**< fifo queue full occurrences */
- UINT32 queueFullRetries; /**< fifo queue full retry occurrences */
- UINT32 maxQueueFullRetries; /**< max fifo queue full retries */
- UINT32 callbackFulls; /**< callback list full occurrences */
-} IxNpeMhSendStats;
-
-/*
- * Variable declarations global to this file only. Externs are followed by
- * static variables.
- */
-
-PRIVATE IxNpeMhSendStats ixNpeMhSendStats[IX_NPEMH_NUM_NPES];
-
-/*
- * Extern function prototypes.
- */
-
-/*
- * Static function prototypes.
- */
-PRIVATE
-BOOL ixNpeMhSendInFifoIsFull(
- IxNpeMhNpeId npeId,
- UINT32 maxSendRetries);
-
-/*
- * Function definition: ixNpeMhSendInFifoIsFull
- */
-
-PRIVATE
-BOOL ixNpeMhSendInFifoIsFull(
- IxNpeMhNpeId npeId,
- UINT32 maxSendRetries)
-{
- BOOL isFull = FALSE;
- UINT32 numRetries = 0;
-
- /* check the NPE's inFIFO */
- isFull = ixNpeMhConfigInFifoIsFull (npeId);
-
- /* we retry a few times, just to give the NPE a chance to read from */
- /* the FIFO if the FIFO is currently full */
- while (isFull && (numRetries++ < maxSendRetries))
- {
- if (numRetries >= IX_NPEMH_SEND_RETRIES_DEFAULT)
- {
- /* Delay here for as short a time as possible (1 us). */
- /* Adding a delay here should ensure we are not hogging */
- /* the AHB bus while we are retrying */
- ixOsalBusySleep (IX_NPEMH_INFIFO_RETRY_DELAY_US);
- }
-
- /* re-check the NPE's inFIFO */
- isFull = ixNpeMhConfigInFifoIsFull (npeId);
-
- /* update statistical info */
- ixNpeMhSendStats[npeId].queueFullRetries++;
- }
-
- /* record the highest number of retries that occurred */
- if (ixNpeMhSendStats[npeId].maxQueueFullRetries < numRetries)
- {
- ixNpeMhSendStats[npeId].maxQueueFullRetries = numRetries;
- }
-
- if (isFull)
- {
- /* update statistical info */
- ixNpeMhSendStats[npeId].queueFulls++;
- }
-
- return isFull;
-}
-
-/*
- * Function definition: ixNpeMhSendMessageSend
- */
-
-IX_STATUS ixNpeMhSendMessageSend (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage message,
- UINT32 maxSendRetries)
-{
- IX_STATUS status;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhSendMessageSend\n");
-
- /* update statistical info */
- ixNpeMhSendStats[npeId].sends++;
-
- /* check if the NPE's inFIFO is full - if so return an error */
- if (ixNpeMhSendInFifoIsFull (npeId, maxSendRetries))
- {
- IX_NPEMH_TRACE0 (IX_NPEMH_WARNING, "NPE's inFIFO is full\n");
- return IX_FAIL;
- }
-
- /* write the message to the NPE's inFIFO */
- status = ixNpeMhConfigInFifoWrite (npeId, message);
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhSendMessageSend\n");
-
- return status;
-}
-
-/*
- * Function definition: ixNpeMhSendMessageWithResponseSend
- */
-
-IX_STATUS ixNpeMhSendMessageWithResponseSend (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage message,
- IxNpeMhMessageId solicitedMessageId,
- IxNpeMhCallback solicitedCallback,
- UINT32 maxSendRetries)
-{
- IX_STATUS status = IX_SUCCESS;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhSendMessageWithResponseSend\n");
-
- /* update statistical info */
- ixNpeMhSendStats[npeId].sendWithResponses++;
-
- /* sr: this sleep will call the receive routine (no interrupts used!!!) */
- ixOsalSleep (IX_NPEMH_INFIFO_RETRY_DELAY_US);
-
- /* check if the NPE's inFIFO is full - if so return an error */
- if (ixNpeMhSendInFifoIsFull (npeId, maxSendRetries))
- {
- IX_NPEMH_TRACE0 (IX_NPEMH_WARNING, "NPE's inFIFO is full\n");
- return IX_FAIL;
- }
-
- /* save the solicited callback */
- status = ixNpeMhSolicitedCbMgrCallbackSave (
- npeId, solicitedMessageId, solicitedCallback);
- if (status != IX_SUCCESS)
- {
- IX_NPEMH_ERROR_REPORT ("Failed to save solicited callback\n");
-
- /* update statistical info */
- ixNpeMhSendStats[npeId].callbackFulls++;
-
- return status;
- }
-
- /* write the message to the NPE's inFIFO */
- status = ixNpeMhConfigInFifoWrite (npeId, message);
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhSendMessageWithResponseSend\n");
-
- return status;
-}
-
-/*
- * Function definition: ixNpeMhSendShow
- */
-
-void ixNpeMhSendShow (
- IxNpeMhNpeId npeId)
-{
- /* show the message send invocation counter */
- IX_NPEMH_SHOW ("Send invocations",
- ixNpeMhSendStats[npeId].sends);
-
- /* show the message send with response invocation counter */
- IX_NPEMH_SHOW ("Send with response invocations",
- ixNpeMhSendStats[npeId].sendWithResponses);
-
- /* show the fifo queue full occurrence counter */
- IX_NPEMH_SHOW ("Fifo queue full occurrences",
- ixNpeMhSendStats[npeId].queueFulls);
-
- /* show the fifo queue full retry occurrence counter */
- IX_NPEMH_SHOW ("Fifo queue full retry occurrences",
- ixNpeMhSendStats[npeId].queueFullRetries);
-
- /* show the fifo queue full maximum retries counter */
- IX_NPEMH_SHOW ("Maximum fifo queue full retries",
- ixNpeMhSendStats[npeId].maxQueueFullRetries);
-
- /* show the callback list full occurrence counter */
- IX_NPEMH_SHOW ("Solicited callback list full occurrences",
- ixNpeMhSendStats[npeId].callbackFulls);
-}
-
-/*
- * Function definition: ixNpeMhSendShowReset
- */
-
-void ixNpeMhSendShowReset (
- IxNpeMhNpeId npeId)
-{
- /* reset the message send invocation counter */
- ixNpeMhSendStats[npeId].sends = 0;
-
- /* reset the message send with response invocation counter */
- ixNpeMhSendStats[npeId].sendWithResponses = 0;
-
- /* reset the fifo queue full occurrence counter */
- ixNpeMhSendStats[npeId].queueFulls = 0;
-
- /* reset the fifo queue full retry occurrence counter */
- ixNpeMhSendStats[npeId].queueFullRetries = 0;
-
- /* reset the max fifo queue full retries counter */
- ixNpeMhSendStats[npeId].maxQueueFullRetries = 0;
-
- /* reset the callback list full occurrence counter */
- ixNpeMhSendStats[npeId].callbackFulls = 0;
-}
+++ /dev/null
-/**
- * @file IxNpeMhSolicitedCbMgr.c
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the implementation of the private API for the
- * Solicited Callback Manager module.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-#ifndef IXNPEMHCONFIG_P_H
-# define IXNPEMHSOLICITEDCBMGR_C
-#else
-# error "Error, IxNpeMhConfig_p.h should not be included before this definition."
-#endif
-
-/*
- * Put the system defined include files required.
- */
-
-
-/*
- * Put the user defined include files required.
- */
-
-#include "IxOsal.h"
-
-#include "IxNpeMhMacros_p.h"
-#include "IxNpeMhSolicitedCbMgr_p.h"
-#include "IxNpeMhConfig_p.h"
-/*
- * #defines and macros used in this file.
- */
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/**
- * @struct IxNpeMhSolicitedCallbackListEntry
- *
- * @brief This structure is used to store the information associated with
- * an entry in the callback list. This consists of the ID of the send
- * message (which indicates the ID of the corresponding response message)
- * and the callback function pointer itself.
- *
- */
-
-typedef struct IxNpeMhSolicitedCallbackListEntry
-{
- /** message ID */
- IxNpeMhMessageId messageId;
-
- /** callback function pointer */
- IxNpeMhCallback callback;
-
- /** pointer to next entry in the list */
- struct IxNpeMhSolicitedCallbackListEntry *next;
-} IxNpeMhSolicitedCallbackListEntry;
-
-/**
- * @struct IxNpeMhSolicitedCallbackList
- *
- * @brief This structure is used to maintain the list of response
- * callbacks. The number of entries in this list will be variable, and
- * they will be stored in a linked list fashion for ease of addition and
- * removal. The entries themselves are statically allocated, and are
- * organised into a "free" list and a "callback" list. Adding an entry
- * means taking an entry from the "free" list and adding it to the
- * "callback" list. Removing an entry means removing it from the
- * "callback" list and returning it to the "free" list.
- */
-
-typedef struct
-{
- /** pointer to the head of the free list */
- IxNpeMhSolicitedCallbackListEntry *freeHead;
-
- /** pointer to the head of the callback list */
- IxNpeMhSolicitedCallbackListEntry *callbackHead;
-
- /** pointer to the tail of the callback list */
- IxNpeMhSolicitedCallbackListEntry *callbackTail;
-
- /** array of entries - the first entry is used as a dummy entry to */
- /* avoid the scenario of having an empty list, hence '+ 1' */
- IxNpeMhSolicitedCallbackListEntry entries[IX_NPEMH_MAX_CALLBACKS + 1];
-} IxNpeMhSolicitedCallbackList;
-
-/**
- * @struct IxNpeMhSolicitedCbMgrStats
- *
- * @brief This structure is used to maintain statistics for the Solicited
- * Callback Manager module.
- */
-
-typedef struct
-{
- UINT32 saves; /**< callback list saves */
- UINT32 retrieves; /**< callback list retrieves */
-} IxNpeMhSolicitedCbMgrStats;
-
-/*
- * Variable declarations global to this file only. Externs are followed by
- * static variables.
- */
-
-PRIVATE IxNpeMhSolicitedCallbackList
-ixNpeMhSolicitedCbMgrCallbackLists[IX_NPEMH_NUM_NPES];
-
-PRIVATE IxNpeMhSolicitedCbMgrStats
-ixNpeMhSolicitedCbMgrStats[IX_NPEMH_NUM_NPES];
-
-/*
- * Extern function prototypes.
- */
-
-/*
- * Static function prototypes.
- */
-
-/*
- * Function definition: ixNpeMhSolicitedCbMgrInitialize
- */
-
-void ixNpeMhSolicitedCbMgrInitialize (void)
-{
- IxNpeMhNpeId npeId;
- UINT32 localIndex;
- IxNpeMhSolicitedCallbackList *list = NULL;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhSolicitedCbMgrInitialize\n");
-
- /* for each NPE ... */
- for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++)
- {
- /* initialise a pointer to the list for convenience */
- list = &ixNpeMhSolicitedCbMgrCallbackLists[npeId];
-
- /* for each entry in the list, after the dummy entry ... */
- for (localIndex = 1; localIndex <= IX_NPEMH_MAX_CALLBACKS; localIndex++)
- {
- /* initialise the entry */
- list->entries[localIndex].messageId = 0x00;
- list->entries[localIndex].callback = NULL;
-
- /* if this entry is before the last entry */
- if (localIndex < IX_NPEMH_MAX_CALLBACKS)
- {
- /* chain this entry to the following entry */
- list->entries[localIndex].next = &(list->entries[localIndex + 1]);
- }
- else /* this entry is the last entry */
- {
- /* the last entry isn't chained to anything */
- list->entries[localIndex].next = NULL;
- }
- }
-
- /* set the free list pointer to point to the first real entry */
- /* (all real entries begin chained together on the free list) */
- list->freeHead = &(list->entries[1]);
-
- /* set the callback list pointers to point to the dummy entry */
- /* (the callback list is initially empty) */
- list->callbackHead = &(list->entries[0]);
- list->callbackTail = &(list->entries[0]);
- }
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhSolicitedCbMgrInitialize\n");
-}
-
-/*
- * Function definition: ixNpeMhSolicitedCbMgrCallbackSave
- */
-
-IX_STATUS ixNpeMhSolicitedCbMgrCallbackSave (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId solicitedMessageId,
- IxNpeMhCallback solicitedCallback)
-{
- IxNpeMhSolicitedCallbackList *list = NULL;
- IxNpeMhSolicitedCallbackListEntry *callbackEntry = NULL;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhSolicitedCbMgrCallbackSave\n");
-
- /* initialise a pointer to the list for convenience */
- list = &ixNpeMhSolicitedCbMgrCallbackLists[npeId];
-
- /* check to see if there are any entries in the free list */
- if (list->freeHead == NULL)
- {
- IX_NPEMH_ERROR_REPORT ("Solicited callback list is full\n");
- return IX_FAIL;
- }
-
- /* there is an entry in the free list we can use */
-
- /* update statistical info */
- ixNpeMhSolicitedCbMgrStats[npeId].saves++;
-
- /* remove a callback entry from the start of the free list */
- callbackEntry = list->freeHead;
- list->freeHead = callbackEntry->next;
-
- /* fill in the callback entry with the new data */
- callbackEntry->messageId = solicitedMessageId;
- callbackEntry->callback = solicitedCallback;
-
- /* the new callback entry will be added to the tail of the callback */
- /* list, so it isn't chained to anything */
- callbackEntry->next = NULL;
-
- /* chain new callback entry to the last entry of the callback list */
- list->callbackTail->next = callbackEntry;
- list->callbackTail = callbackEntry;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhSolicitedCbMgrCallbackSave\n");
-
- return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixNpeMhSolicitedCbMgrCallbackRetrieve
- */
-
-void ixNpeMhSolicitedCbMgrCallbackRetrieve (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId solicitedMessageId,
- IxNpeMhCallback *solicitedCallback)
-{
- IxNpeMhSolicitedCallbackList *list = NULL;
- IxNpeMhSolicitedCallbackListEntry *callbackEntry = NULL;
- IxNpeMhSolicitedCallbackListEntry *previousEntry = NULL;
-
- /* initialise a pointer to the list for convenience */
- list = &ixNpeMhSolicitedCbMgrCallbackLists[npeId];
-
- /* initialise the callback entry to the first entry of the callback */
- /* list - we must skip over the dummy entry, which is the previous */
- callbackEntry = list->callbackHead->next;
- previousEntry = list->callbackHead;
-
- /* traverse the callback list looking for an entry with a matching */
- /* message ID. note we also save the previous entry's pointer to */
- /* allow us to unchain the matching entry from the callback list */
- while ((callbackEntry != NULL) &&
- (callbackEntry->messageId != solicitedMessageId))
- {
- previousEntry = callbackEntry;
- callbackEntry = callbackEntry->next;
- }
-
- /* if we didn't find a matching callback entry */
- if (callbackEntry == NULL)
- {
- /* return a NULL callback in the outgoing parameter */
- *solicitedCallback = NULL;
- }
- else /* we found a matching callback entry */
- {
- /* update statistical info */
- ixNpeMhSolicitedCbMgrStats[npeId].retrieves++;
-
- /* return the callback in the outgoing parameter */
- *solicitedCallback = callbackEntry->callback;
-
- /* unchain callback entry by chaining previous entry to next */
- previousEntry->next = callbackEntry->next;
-
- /* if the callback entry is at the tail of the list */
- if (list->callbackTail == callbackEntry)
- {
- /* update the tail of the callback list */
- list->callbackTail = previousEntry;
- }
-
- /* re-initialise the callback entry */
- callbackEntry->messageId = 0x00;
- callbackEntry->callback = NULL;
-
- /* add the callback entry to the start of the free list */
- callbackEntry->next = list->freeHead;
- list->freeHead = callbackEntry;
- }
-}
-
-/*
- * Function definition: ixNpeMhSolicitedCbMgrShow
- */
-
-void ixNpeMhSolicitedCbMgrShow (
- IxNpeMhNpeId npeId)
-{
- /* show the solicited callback list save counter */
- IX_NPEMH_SHOW ("Solicited callback list saves",
- ixNpeMhSolicitedCbMgrStats[npeId].saves);
-
- /* show the solicited callback list retrieve counter */
- IX_NPEMH_SHOW ("Solicited callback list retrieves",
- ixNpeMhSolicitedCbMgrStats[npeId].retrieves);
-}
-
-/*
- * Function definition: ixNpeMhSolicitedCbMgrShowReset
- */
-
-void ixNpeMhSolicitedCbMgrShowReset (
- IxNpeMhNpeId npeId)
-{
- /* reset the solicited callback list save counter */
- ixNpeMhSolicitedCbMgrStats[npeId].saves = 0;
-
- /* reset the solicited callback list retrieve counter */
- ixNpeMhSolicitedCbMgrStats[npeId].retrieves = 0;
-}
+++ /dev/null
-/**
- * @file IxNpeMhUnsolicitedCbMgr.c
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the implementation of the private API for
- * the Unsolicited Callback Manager module.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * Put the system defined include files required.
- */
-
-
-/*
- * Put the user defined include files required.
- */
-#include "IxOsal.h"
-
-#include "IxNpeMhMacros_p.h"
-
-#include "IxNpeMhUnsolicitedCbMgr_p.h"
-
-
-/*
- * #defines and macros used in this file.
- */
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/**
- * @struct IxNpeMhUnsolicitedCallbackTable
- *
- * @brief This structure is used to maintain the list of registered
- * callbacks. One entry exists for each message ID, and a NULL entry will
- * signify that no callback has been registered for that ID.
- */
-
-typedef struct
-{
- /** array of entries */
- IxNpeMhCallback entries[IX_NPEMH_MAX_MESSAGE_ID + 1];
-} IxNpeMhUnsolicitedCallbackTable;
-
-/**
- * @struct IxNpeMhUnsolicitedCbMgrStats
- *
- * @brief This structure is used to maintain statistics for the Unsolicited
- * Callback Manager module.
- */
-
-typedef struct
-{
- UINT32 saves; /**< callback table saves */
- UINT32 overwrites; /**< callback table overwrites */
-} IxNpeMhUnsolicitedCbMgrStats;
-
-/*
- * Variable declarations global to this file only. Externs are followed by
- * static variables.
- */
-
-PRIVATE IxNpeMhUnsolicitedCallbackTable
-ixNpeMhUnsolicitedCallbackTables[IX_NPEMH_NUM_NPES];
-
-PRIVATE IxNpeMhUnsolicitedCbMgrStats
-ixNpeMhUnsolicitedCbMgrStats[IX_NPEMH_NUM_NPES];
-
-/*
- * Extern function prototypes.
- */
-
-/*
- * Static function prototypes.
- */
-
-/*
- * Function definition: ixNpeMhUnsolicitedCbMgrInitialize
- */
-
-void ixNpeMhUnsolicitedCbMgrInitialize (void)
-{
- IxNpeMhNpeId npeId = 0;
- IxNpeMhUnsolicitedCallbackTable *table = NULL;
- IxNpeMhMessageId messageId = 0;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhUnsolicitedCbMgrInitialize\n");
-
- /* for each NPE ... */
- for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++)
- {
- /* initialise a pointer to the table for convenience */
- table = &ixNpeMhUnsolicitedCallbackTables[npeId];
-
- /* for each message ID ... */
- for (messageId = IX_NPEMH_MIN_MESSAGE_ID;
- messageId <= IX_NPEMH_MAX_MESSAGE_ID; messageId++)
- {
- /* initialise the callback for this message ID to NULL */
- table->entries[messageId] = NULL;
- }
- }
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhUnsolicitedCbMgrInitialize\n");
-}
-
-/*
- * Function definition: ixNpeMhUnsolicitedCbMgrCallbackSave
- */
-
-void ixNpeMhUnsolicitedCbMgrCallbackSave (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId unsolicitedMessageId,
- IxNpeMhCallback unsolicitedCallback)
-{
- IxNpeMhUnsolicitedCallbackTable *table = NULL;
-
- /* initialise a pointer to the table for convenience */
- table = &ixNpeMhUnsolicitedCallbackTables[npeId];
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
- "ixNpeMhUnsolicitedCbMgrCallbackSave\n");
-
- /* update statistical info */
- ixNpeMhUnsolicitedCbMgrStats[npeId].saves++;
-
- /* check if there is a callback already registered for this NPE and */
- /* message ID */
- if (table->entries[unsolicitedMessageId] != NULL)
- {
- /* if we are overwriting an existing callback */
- if (unsolicitedCallback != NULL)
- {
- IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "Unsolicited callback "
- "overwriting existing callback for NPE ID %d "
- "message ID 0x%02X\n", npeId, unsolicitedMessageId);
- }
- else /* if we are clearing an existing callback */
- {
- IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NULL unsolicited callback "
- "clearing existing callback for NPE ID %d "
- "message ID 0x%02X\n", npeId, unsolicitedMessageId);
- }
-
- /* update statistical info */
- ixNpeMhUnsolicitedCbMgrStats[npeId].overwrites++;
- }
-
- /* save the callback into the table */
- table->entries[unsolicitedMessageId] = unsolicitedCallback;
-
- IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
- "ixNpeMhUnsolicitedCbMgrCallbackSave\n");
-}
-
-/*
- * Function definition: ixNpeMhUnsolicitedCbMgrCallbackRetrieve
- */
-
-void ixNpeMhUnsolicitedCbMgrCallbackRetrieve (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId unsolicitedMessageId,
- IxNpeMhCallback *unsolicitedCallback)
-{
- IxNpeMhUnsolicitedCallbackTable *table = NULL;
-
- /* initialise a pointer to the table for convenience */
- table = &ixNpeMhUnsolicitedCallbackTables[npeId];
-
- /* retrieve the callback from the table */
- *unsolicitedCallback = table->entries[unsolicitedMessageId];
-}
-
-/*
- * Function definition: ixNpeMhUnsolicitedCbMgrShow
- */
-
-void ixNpeMhUnsolicitedCbMgrShow (
- IxNpeMhNpeId npeId)
-{
- /* show the unsolicited callback table save counter */
- IX_NPEMH_SHOW ("Unsolicited callback table saves",
- ixNpeMhUnsolicitedCbMgrStats[npeId].saves);
-
- /* show the unsolicited callback table overwrite counter */
- IX_NPEMH_SHOW ("Unsolicited callback table overwrites",
- ixNpeMhUnsolicitedCbMgrStats[npeId].overwrites);
-}
-
-/*
- * Function definition: ixNpeMhUnsolicitedCbMgrShowReset
- */
-
-void ixNpeMhUnsolicitedCbMgrShowReset (
- IxNpeMhNpeId npeId)
-{
- /* reset the unsolicited callback table save counter */
- ixNpeMhUnsolicitedCbMgrStats[npeId].saves = 0;
-
- /* reset the unsolicited callback table overwrite counter */
- ixNpeMhUnsolicitedCbMgrStats[npeId].overwrites = 0;
-}
+++ /dev/null
-/**
- * @file IxOsalBufferMgt.c
- *
- * @brief Default buffer pool management and buffer management
- * Implementation.
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-/*
- * OS may choose to use default bufferMgt by defining
- * IX_OSAL_USE_DEFAULT_BUFFER_MGT in IxOsalOsBufferMgt.h
- */
-
-#include "IxOsal.h"
-
-#define IX_OSAL_BUFFER_FREE_PROTECTION /* Define this to enable Illegal MBuf Freed Protection*/
-
-/*
- * The implementation is only used when the following
- * is defined.
- */
-#ifdef IX_OSAL_USE_DEFAULT_BUFFER_MGT
-
-
-#define IX_OSAL_MBUF_SYS_SIGNATURE (0x8BADF00D)
-#define IX_OSAL_MBUF_SYS_SIGNATURE_MASK (0xEFFFFFFF)
-#define IX_OSAL_MBUF_USED_FLAG (0x10000000)
-#define IX_OSAL_MBUF_SYS_SIGNATURE_INIT(bufPtr) IX_OSAL_MBUF_SIGNATURE (bufPtr) = (UINT32)IX_OSAL_MBUF_SYS_SIGNATURE
-
-/*
-* This implementation is protect, the buffer pool management's ixOsalMBufFree
-* against an invalid MBUF pointer argument that already has been freed earlier
-* or in other words resides in the free pool of MBUFs. This added feature,
-* checks the MBUF "USED" FLAG. The Flag tells if the MBUF is still not freed
-* back to the Buffer Pool.
-* Disable this feature for performance reasons by undef
-* IX_OSAL_BUFFER_FREE_PROTECTION macro.
-*/
-#ifdef IX_OSAL_BUFFER_FREE_PROTECTION /*IX_OSAL_BUFFER_FREE_PROTECTION With Buffer Free protection*/
-
-#define IX_OSAL_MBUF_GET_SYS_SIGNATURE(bufPtr) (IX_OSAL_MBUF_SIGNATURE (bufPtr)&(IX_OSAL_MBUF_SYS_SIGNATURE_MASK) )
-#define IX_OSAL_MBUF_SET_SYS_SIGNATURE(bufPtr) do { \
- IX_OSAL_MBUF_SIGNATURE (bufPtr)&(~IX_OSAL_MBUF_SYS_SIGNATURE_MASK);\
- IX_OSAL_MBUF_SIGNATURE (bufPtr)|=IX_OSAL_MBUF_SYS_SIGNATURE; \
- }while(0)
-
-#define IX_OSAL_MBUF_SET_USED_FLAG(bufPtr) IX_OSAL_MBUF_SIGNATURE (bufPtr)|=IX_OSAL_MBUF_USED_FLAG
-#define IX_OSAL_MBUF_CLEAR_USED_FLAG(bufPtr) IX_OSAL_MBUF_SIGNATURE (bufPtr)&=~IX_OSAL_MBUF_USED_FLAG
-#define IX_OSAL_MBUF_ISSET_USED_FLAG(bufPtr) (IX_OSAL_MBUF_SIGNATURE (bufPtr)&IX_OSAL_MBUF_USED_FLAG)
-
-#else
-
-#define IX_OSAL_MBUF_GET_SYS_SIGNATURE(bufPtr) IX_OSAL_MBUF_SIGNATURE (bufPtr)
-#define IX_OSAL_MBUF_SET_SYS_SIGNATURE(bufPtr) IX_OSAL_MBUF_SIGNATURE (bufPtr) = IX_OSAL_MBUF_SYS_SIGNATURE
-
-#endif /*IX_OSAL_BUFFER_FREE_PROTECTION With Buffer Free protection*/
-/*
- * Variable declarations global to this file only. Externs are followed by
- * static variables.
- */
-
-/*
- * A unit of 32, used to provide bit-shift for pool
- * management. Needs some work if users want more than 32 pools.
- */
-#define IX_OSAL_BUFF_FREE_BITS 32
-
-PRIVATE UINT32 ixOsalBuffFreePools[IX_OSAL_MBUF_MAX_POOLS /
- IX_OSAL_BUFF_FREE_BITS];
-
-PUBLIC IX_OSAL_MBUF_POOL ixOsalBuffPools[IX_OSAL_MBUF_MAX_POOLS];
-
-static int ixOsalBuffPoolsInUse = 0;
-
-#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY
-PRIVATE IX_OSAL_MBUF *
-ixOsalBuffPoolMbufInit (UINT32 mbufSizeAligned,
- UINT32 dataSizeAligned,
- IX_OSAL_MBUF_POOL *poolPtr);
-#endif
-
-PRIVATE IX_OSAL_MBUF_POOL * ixOsalPoolAlloc (void);
-
-/*
- * Function definition: ixOsalPoolAlloc
- */
-
-/****************************/
-
-PRIVATE IX_OSAL_MBUF_POOL *
-ixOsalPoolAlloc (void)
-{
- register unsigned int i = 0;
-
- /*
- * Scan for the first free buffer. Free buffers are indicated by 0
- * on the corrsponding bit in ixOsalBuffFreePools.
- */
- if (ixOsalBuffPoolsInUse >= IX_OSAL_MBUF_MAX_POOLS)
- {
- /*
- * Fail to grab a ptr this time
- */
- return NULL;
- }
-
- while (ixOsalBuffFreePools[i / IX_OSAL_BUFF_FREE_BITS] &
- (1 << (i % IX_OSAL_BUFF_FREE_BITS)))
- i++;
- /*
- * Free buffer found. Mark it as busy and initialize.
- */
- ixOsalBuffFreePools[i / IX_OSAL_BUFF_FREE_BITS] |=
- (1 << (i % IX_OSAL_BUFF_FREE_BITS));
-
- memset (&ixOsalBuffPools[i], 0, sizeof (IX_OSAL_MBUF_POOL));
-
- ixOsalBuffPools[i].poolIdx = i;
- ixOsalBuffPoolsInUse++;
-
- return &ixOsalBuffPools[i];
-}
-
-
-#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY
-PRIVATE IX_OSAL_MBUF *
-ixOsalBuffPoolMbufInit (UINT32 mbufSizeAligned,
- UINT32 dataSizeAligned,
- IX_OSAL_MBUF_POOL *poolPtr)
-{
- UINT8 *dataPtr;
- IX_OSAL_MBUF *realMbufPtr;
- /* Allocate cache-aligned memory for mbuf header */
- realMbufPtr = (IX_OSAL_MBUF *) IX_OSAL_CACHE_DMA_MALLOC (mbufSizeAligned);
- IX_OSAL_ASSERT (realMbufPtr != NULL);
- memset (realMbufPtr, 0, mbufSizeAligned);
-
- /* Allocate cache-aligned memory for mbuf data */
- dataPtr = (UINT8 *) IX_OSAL_CACHE_DMA_MALLOC (dataSizeAligned);
- IX_OSAL_ASSERT (dataPtr != NULL);
- memset (dataPtr, 0, dataSizeAligned);
-
- /* Fill in mbuf header fields */
- IX_OSAL_MBUF_MDATA (realMbufPtr) = dataPtr;
- IX_OSAL_MBUF_ALLOCATED_BUFF_DATA (realMbufPtr) = (UINT32)dataPtr;
-
- IX_OSAL_MBUF_MLEN (realMbufPtr) = dataSizeAligned;
- IX_OSAL_MBUF_ALLOCATED_BUFF_LEN (realMbufPtr) = dataSizeAligned;
-
- IX_OSAL_MBUF_NET_POOL (realMbufPtr) = (IX_OSAL_MBUF_POOL *) poolPtr;
-
- IX_OSAL_MBUF_SYS_SIGNATURE_INIT(realMbufPtr);
-
- /* update some statistical information */
- poolPtr->mbufMemSize += mbufSizeAligned;
- poolPtr->dataMemSize += dataSizeAligned;
-
- return realMbufPtr;
-}
-#endif /* #ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY */
-
-/*
- * Function definition: ixOsalBuffPoolInit
- */
-
-PUBLIC IX_OSAL_MBUF_POOL *
-ixOsalPoolInit (UINT32 count, UINT32 size, const char *name)
-{
-
- /* These variables are only used if UX_OSAL_BUFFER_ALLOC_SEPERATELY
- * is defined .
- */
-#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY
- UINT32 i, mbufSizeAligned, dataSizeAligned;
- IX_OSAL_MBUF *currentMbufPtr = NULL;
-#else
- void *poolBufPtr;
- void *poolDataPtr;
- int mbufMemSize;
- int dataMemSize;
-#endif
-
- IX_OSAL_MBUF_POOL *poolPtr = NULL;
-
- if (count <= 0)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
- IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalPoolInit(): " "count = 0 \n", 0, 0, 0, 0, 0, 0);
- return NULL;
- }
-
- if (name == NULL)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
- IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalPoolInit(): " "NULL name \n", 0, 0, 0, 0, 0, 0);
- return NULL;
- }
-
- if (strlen (name) > IX_OSAL_MBUF_POOL_NAME_LEN)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
- IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalPoolInit(): "
- "ERROR - name length should be no greater than %d \n",
- IX_OSAL_MBUF_POOL_NAME_LEN, 0, 0, 0, 0, 0);
- return NULL;
- }
-
-/* OS can choose whether to allocate all buffers all together (if it
- * can handle a huge single alloc request), or to allocate buffers
- * separately by the defining IX_OSAL_BUFFER_ALLOC_SEPARATELY.
- */
-#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY
- /* Get a pool Ptr */
- poolPtr = ixOsalPoolAlloc ();
-
- if (poolPtr == NULL)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
- IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalPoolInit(): " "Fail to Get PoolPtr \n", 0, 0, 0, 0, 0, 0);
- return NULL;
- }
-
- mbufSizeAligned = IX_OSAL_MBUF_POOL_SIZE_ALIGN (sizeof (IX_OSAL_MBUF));
- dataSizeAligned = IX_OSAL_MBUF_POOL_SIZE_ALIGN(size);
-
- poolPtr->nextFreeBuf = NULL;
- poolPtr->mbufMemPtr = NULL;
- poolPtr->dataMemPtr = NULL;
- poolPtr->bufDataSize = dataSizeAligned;
- poolPtr->totalBufsInPool = count;
- poolPtr->poolAllocType = IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC;
- strcpy (poolPtr->name, name);
-
-
- for (i = 0; i < count; i++)
- {
- /* create an mbuf */
- currentMbufPtr = ixOsalBuffPoolMbufInit (mbufSizeAligned,
- dataSizeAligned,
- poolPtr);
-
-#ifdef IX_OSAL_BUFFER_FREE_PROTECTION
-/* Set the Buffer USED Flag. If not, ixOsalMBufFree will fail.
- ixOsalMbufFree used here is in a special case whereby, it's
- used to add MBUF to the Pool. By specification, ixOsalMbufFree
- deallocates an allocated MBUF from Pool.
-*/
- IX_OSAL_MBUF_SET_USED_FLAG(currentMbufPtr);
-#endif
- /* Add it to the pool */
- ixOsalMbufFree (currentMbufPtr);
-
- /* flush the pool information to RAM */
- IX_OSAL_CACHE_FLUSH (currentMbufPtr, mbufSizeAligned);
- }
-
- /*
- * update the number of free buffers in the pool
- */
- poolPtr->freeBufsInPool = count;
-
-#else
-/* Otherwise allocate buffers in a continuous block fashion */
- poolBufPtr = IX_OSAL_MBUF_POOL_MBUF_AREA_ALLOC (count, mbufMemSize);
- IX_OSAL_ASSERT (poolBufPtr != NULL);
- poolDataPtr =
- IX_OSAL_MBUF_POOL_DATA_AREA_ALLOC (count, size, dataMemSize);
- IX_OSAL_ASSERT (poolDataPtr != NULL);
-
- poolPtr = ixOsalNoAllocPoolInit (poolBufPtr, poolDataPtr,
- count, size, name);
- if (poolPtr == NULL)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
- IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalPoolInit(): " "Fail to get pool ptr \n", 0, 0, 0, 0, 0, 0);
- return NULL;
- }
-
- poolPtr->poolAllocType = IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC;
-
-#endif /* IX_OSAL_BUFFER_ALLOC_SEPARATELY */
- return poolPtr;
-}
-
-PUBLIC IX_OSAL_MBUF_POOL *
-ixOsalNoAllocPoolInit (void *poolBufPtr,
- void *poolDataPtr, UINT32 count, UINT32 size, const char *name)
-{
- UINT32 i, mbufSizeAligned, sizeAligned;
- IX_OSAL_MBUF *currentMbufPtr = NULL;
- IX_OSAL_MBUF *nextMbufPtr = NULL;
- IX_OSAL_MBUF_POOL *poolPtr = NULL;
-
- /*
- * check parameters
- */
- if (poolBufPtr == NULL)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
- IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalNoAllocPoolInit(): "
- "ERROR - NULL poolBufPtr \n", 0, 0, 0, 0, 0, 0);
- return NULL;
- }
-
- if (count <= 0)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
- IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalNoAllocPoolInit(): "
- "ERROR - count must > 0 \n", 0, 0, 0, 0, 0, 0);
- return NULL;
- }
-
- if (name == NULL)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
- IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalNoAllocPoolInit(): "
- "ERROR - NULL name ptr \n", 0, 0, 0, 0, 0, 0);
- return NULL;
- }
-
- if (strlen (name) > IX_OSAL_MBUF_POOL_NAME_LEN)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
- IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalNoAllocPoolInit(): "
- "ERROR - name length should be no greater than %d \n",
- IX_OSAL_MBUF_POOL_NAME_LEN, 0, 0, 0, 0, 0);
- return NULL;
- }
-
- poolPtr = ixOsalPoolAlloc ();
-
- if (poolPtr == NULL)
- {
- return NULL;
- }
-
- /*
- * Adjust sizes to ensure alignment on cache line boundaries
- */
- mbufSizeAligned =
- IX_OSAL_MBUF_POOL_SIZE_ALIGN (sizeof (IX_OSAL_MBUF));
- /*
- * clear the mbuf memory area
- */
- memset (poolBufPtr, 0, mbufSizeAligned * count);
-
- if (poolDataPtr != NULL)
- {
- /*
- * Adjust sizes to ensure alignment on cache line boundaries
- */
- sizeAligned = IX_OSAL_MBUF_POOL_SIZE_ALIGN (size);
- /*
- * clear the data memory area
- */
- memset (poolDataPtr, 0, sizeAligned * count);
- }
- else
- {
- sizeAligned = 0;
- }
-
- /*
- * initialise pool fields
- */
- strcpy ((poolPtr)->name, name);
-
- poolPtr->dataMemPtr = poolDataPtr;
- poolPtr->mbufMemPtr = poolBufPtr;
- poolPtr->bufDataSize = sizeAligned;
- poolPtr->totalBufsInPool = count;
- poolPtr->mbufMemSize = mbufSizeAligned * count;
- poolPtr->dataMemSize = sizeAligned * count;
-
- currentMbufPtr = (IX_OSAL_MBUF *) poolBufPtr;
-
- poolPtr->nextFreeBuf = currentMbufPtr;
-
- for (i = 0; i < count; i++)
- {
- if (i < (count - 1))
- {
- nextMbufPtr =
- (IX_OSAL_MBUF *) ((unsigned) currentMbufPtr +
- mbufSizeAligned);
- }
- else
- { /* last mbuf in chain */
- nextMbufPtr = NULL;
- }
- IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (currentMbufPtr) = nextMbufPtr;
- IX_OSAL_MBUF_NET_POOL (currentMbufPtr) = poolPtr;
-
- IX_OSAL_MBUF_SYS_SIGNATURE_INIT(currentMbufPtr);
-
- if (poolDataPtr != NULL)
- {
- IX_OSAL_MBUF_MDATA (currentMbufPtr) = poolDataPtr;
- IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(currentMbufPtr) = (UINT32) poolDataPtr;
-
- IX_OSAL_MBUF_MLEN (currentMbufPtr) = sizeAligned;
- IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(currentMbufPtr) = sizeAligned;
-
- poolDataPtr = (void *) ((unsigned) poolDataPtr + sizeAligned);
- }
-
- currentMbufPtr = nextMbufPtr;
- }
-
- /*
- * update the number of free buffers in the pool
- */
- poolPtr->freeBufsInPool = count;
-
- poolPtr->poolAllocType = IX_OSAL_MBUF_POOL_TYPE_USER_ALLOC;
-
- return poolPtr;
-}
-
-/*
- * Get a mbuf ptr from the pool
- */
-PUBLIC IX_OSAL_MBUF *
-ixOsalMbufAlloc (IX_OSAL_MBUF_POOL * poolPtr)
-{
- int lock;
- IX_OSAL_MBUF *newBufPtr = NULL;
-
- /*
- * check parameters
- */
- if (poolPtr == NULL)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
- IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalMbufAlloc(): "
- "ERROR - Invalid Parameter\n", 0, 0, 0, 0, 0, 0);
- return NULL;
- }
-
- lock = ixOsalIrqLock ();
-
- newBufPtr = poolPtr->nextFreeBuf;
- if (newBufPtr)
- {
- poolPtr->nextFreeBuf =
- IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (newBufPtr);
- IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (newBufPtr) = NULL;
-
- /*
- * update the number of free buffers in the pool
- */
- poolPtr->freeBufsInPool--;
- }
- else
- {
- /* Return NULL to indicate to caller that request is denied. */
- ixOsalIrqUnlock (lock);
-
- return NULL;
- }
-
-#ifdef IX_OSAL_BUFFER_FREE_PROTECTION
- /* Set Buffer Used Flag to indicate state.*/
- IX_OSAL_MBUF_SET_USED_FLAG(newBufPtr);
-#endif
-
- ixOsalIrqUnlock (lock);
-
- return newBufPtr;
-}
-
-PUBLIC IX_OSAL_MBUF *
-ixOsalMbufFree (IX_OSAL_MBUF * bufPtr)
-{
- int lock;
- IX_OSAL_MBUF_POOL *poolPtr;
-
- IX_OSAL_MBUF *nextBufPtr = NULL;
-
- /*
- * check parameters
- */
- if (bufPtr == NULL)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
- IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalMbufFree(): "
- "ERROR - Invalid Parameter\n", 0, 0, 0, 0, 0, 0);
- return NULL;
- }
-
-
-
- lock = ixOsalIrqLock ();
-
-#ifdef IX_OSAL_BUFFER_FREE_PROTECTION
-
- /* Prevention for Buffer freed more than once*/
- if(!IX_OSAL_MBUF_ISSET_USED_FLAG(bufPtr))
- {
- return NULL;
- }
- IX_OSAL_MBUF_CLEAR_USED_FLAG(bufPtr);
-#endif
-
- poolPtr = IX_OSAL_MBUF_NET_POOL (bufPtr);
-
- /*
- * check the mbuf wrapper signature (if mbuf wrapper was used)
- */
- if (poolPtr->poolAllocType == IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC)
- {
- IX_OSAL_ENSURE ( (IX_OSAL_MBUF_GET_SYS_SIGNATURE(bufPtr) == IX_OSAL_MBUF_SYS_SIGNATURE),
- "ixOsalBuffPoolBufFree: ERROR - Invalid mbuf signature.");
- }
-
- nextBufPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (bufPtr);
-
- IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (bufPtr) = poolPtr->nextFreeBuf;
- poolPtr->nextFreeBuf = bufPtr;
-
- /*
- * update the number of free buffers in the pool
- */
- poolPtr->freeBufsInPool++;
-
- ixOsalIrqUnlock (lock);
-
- return nextBufPtr;
-}
-
-PUBLIC void
-ixOsalMbufChainFree (IX_OSAL_MBUF * bufPtr)
-{
- while ((bufPtr = ixOsalMbufFree (bufPtr)));
-}
-
-/*
- * Function definition: ixOsalBuffPoolShow
- */
-PUBLIC void
-ixOsalMbufPoolShow (IX_OSAL_MBUF_POOL * poolPtr)
-{
- IX_OSAL_MBUF *nextBufPtr;
- int count = 0;
- int lock;
-
- /*
- * check parameters
- */
- if (poolPtr == NULL)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
- IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalBuffPoolShow(): "
- "ERROR - Invalid Parameter", 0, 0, 0, 0, 0, 0);
- /*
- * return IX_FAIL;
- */
- return;
- }
-
- lock = ixOsalIrqLock ();
- count = poolPtr->freeBufsInPool;
- nextBufPtr = poolPtr->nextFreeBuf;
- ixOsalIrqUnlock (lock);
-
- ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE,
- IX_OSAL_LOG_DEV_STDOUT, "=== POOL INFORMATION ===\n", 0, 0, 0,
- 0, 0, 0);
- ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
- "Pool Name: %s\n",
- (unsigned int) poolPtr->name, 0, 0, 0, 0, 0);
- ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
- "Pool Allocation Type: %d\n",
- (unsigned int) poolPtr->poolAllocType, 0, 0, 0, 0, 0);
- ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
- "Pool Mbuf Mem Usage (bytes): %d\n",
- (unsigned int) poolPtr->mbufMemSize, 0, 0, 0, 0, 0);
- ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
- "Pool Data Mem Usage (bytes): %d\n",
- (unsigned int) poolPtr->dataMemSize, 0, 0, 0, 0, 0);
- ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
- "Mbuf Data Capacity (bytes): %d\n",
- (unsigned int) poolPtr->bufDataSize, 0, 0, 0, 0, 0);
- ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
- "Total Mbufs in Pool: %d\n",
- (unsigned int) poolPtr->totalBufsInPool, 0, 0, 0, 0, 0);
- ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
- "Available Mbufs: %d\n", (unsigned int) count, 0,
- 0, 0, 0, 0);
- ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
- "Next Available Mbuf: %p\n", (unsigned int) nextBufPtr,
- 0, 0, 0, 0, 0);
-
- if (poolPtr->poolAllocType == IX_OSAL_MBUF_POOL_TYPE_USER_ALLOC)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE,
- IX_OSAL_LOG_DEV_STDOUT,
- "Mbuf Mem Area Start address: %p\n",
- (unsigned int) poolPtr->mbufMemPtr, 0, 0, 0, 0, 0);
- ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT,
- "Data Mem Area Start address: %p\n",
- (unsigned int) poolPtr->dataMemPtr, 0, 0, 0, 0, 0);
- }
-}
-
-PUBLIC void
-ixOsalMbufDataPtrReset (IX_OSAL_MBUF * bufPtr)
-{
- IX_OSAL_MBUF_POOL *poolPtr;
- UINT8 *poolDataPtr;
-
- if (bufPtr == NULL)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalBuffPoolBufDataPtrReset"
- ": ERROR - Invalid Parameter\n", 0, 0, 0, 0, 0, 0);
- return;
- }
-
- poolPtr = (IX_OSAL_MBUF_POOL *) IX_OSAL_MBUF_NET_POOL (bufPtr);
- poolDataPtr = poolPtr->dataMemPtr;
-
- if (poolPtr->poolAllocType == IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC)
- {
- if (IX_OSAL_MBUF_GET_SYS_SIGNATURE(bufPtr) != IX_OSAL_MBUF_SYS_SIGNATURE)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalBuffPoolBufDataPtrReset"
- ": invalid mbuf, cannot reset mData pointer\n", 0, 0,
- 0, 0, 0, 0);
- return;
- }
- IX_OSAL_MBUF_MDATA (bufPtr) = (UINT8*)IX_OSAL_MBUF_ALLOCATED_BUFF_DATA (bufPtr);
- }
- else
- {
- if (poolDataPtr)
- {
- unsigned int bufSize = poolPtr->bufDataSize;
- unsigned int bufDataAddr =
- (unsigned int) IX_OSAL_MBUF_MDATA (bufPtr);
- unsigned int poolDataAddr = (unsigned int) poolDataPtr;
-
- /*
- * the pointer is still pointing somewhere in the mbuf payload.
- * This operation moves the pointer to the beginning of the
- * mbuf payload
- */
- bufDataAddr = ((bufDataAddr - poolDataAddr) / bufSize) * bufSize;
- IX_OSAL_MBUF_MDATA (bufPtr) = &poolDataPtr[bufDataAddr];
- }
- else
- {
- ixOsalLog (IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalBuffPoolBufDataPtrReset"
- ": cannot be used if user supplied NULL pointer for pool data area "
- "when pool was created\n", 0, 0, 0, 0, 0, 0);
- return;
- }
- }
-
-}
-
-/*
- * Function definition: ixOsalBuffPoolUninit
- */
-PUBLIC IX_STATUS
-ixOsalBuffPoolUninit (IX_OSAL_MBUF_POOL * pool)
-{
- if (!pool)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalBuffPoolUninit: NULL ptr \n", 0, 0, 0, 0, 0, 0);
- return IX_FAIL;
- }
-
- if (pool->freeBufsInPool != pool->totalBufsInPool)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalBuffPoolUninit: need to return all ptrs to the pool first! \n",
- 0, 0, 0, 0, 0, 0);
- return IX_FAIL;
- }
-
- if (pool->poolAllocType == IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC)
- {
-#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY
- UINT32 i;
- IX_OSAL_MBUF* pBuf;
-
- pBuf = pool->nextFreeBuf;
- /* Freed the Buffer one by one till all the Memory is freed*/
- for (i= pool->freeBufsInPool; i >0 && pBuf!=NULL ;i--){
- IX_OSAL_MBUF* pBufTemp;
- pBufTemp = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(pBuf);
- /* Freed MBUF Data Memory area*/
- IX_OSAL_CACHE_DMA_FREE( (void *) (IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(pBuf)) );
- /* Freed MBUF Struct Memory area*/
- IX_OSAL_CACHE_DMA_FREE(pBuf);
- pBuf = pBufTemp;
- }
-
-#else
- IX_OSAL_CACHE_DMA_FREE (pool->mbufMemPtr);
- IX_OSAL_CACHE_DMA_FREE (pool->dataMemPtr);
-#endif
- }
-
- ixOsalBuffFreePools[pool->poolIdx / IX_OSAL_BUFF_FREE_BITS] &=
- ~(1 << (pool->poolIdx % IX_OSAL_BUFF_FREE_BITS));
- ixOsalBuffPoolsInUse--;
- return IX_SUCCESS;
-}
-
-/*
- * Function definition: ixOsalBuffPoolDataAreaSizeGet
- */
-PUBLIC UINT32
-ixOsalBuffPoolDataAreaSizeGet (int count, int size)
-{
- UINT32 memorySize;
- memorySize = count * IX_OSAL_MBUF_POOL_SIZE_ALIGN (size);
- return memorySize;
-}
-
-/*
- * Function definition: ixOsalBuffPoolMbufAreaSizeGet
- */
-PUBLIC UINT32
-ixOsalBuffPoolMbufAreaSizeGet (int count)
-{
- UINT32 memorySize;
- memorySize =
- count * IX_OSAL_MBUF_POOL_SIZE_ALIGN (sizeof (IX_OSAL_MBUF));
- return memorySize;
-}
-
-/*
- * Function definition: ixOsalBuffPoolFreeCountGet
- */
-PUBLIC UINT32 ixOsalBuffPoolFreeCountGet(IX_OSAL_MBUF_POOL * poolPtr)
-
-{
-
- return poolPtr->freeBufsInPool;
-
-}
-
-#endif /* IX_OSAL_USE_DEFAULT_BUFFER_MGT */
+++ /dev/null
-/**
- * @file IxOsalIoMem.c
- *
- * @brief OS-independent IO/Mem implementation
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-/* Access to the global mem map is only allowed in this file */
-#define IxOsalIoMem_C
-
-#include "IxOsal.h"
-
-#define SEARCH_PHYSICAL_ADDRESS (1)
-#define SEARCH_VIRTUAL_ADDRESS (2)
-
-/*
- * Searches for map using one of the following criteria:
- *
- * - enough room to include a zone starting with the physical "requestedAddress" of size "size" (for mapping)
- * - includes the virtual "requestedAddress" in its virtual address space (already mapped, for unmapping)
- * - correct coherency
- *
- * Returns a pointer to the map or NULL if a suitable map is not found.
- */
-PRIVATE IxOsalMemoryMap *
-ixOsalMemMapFind (UINT32 requestedAddress,
- UINT32 size, UINT32 searchCriteria, UINT32 requestedEndianType)
-{
- UINT32 mapIndex;
-
- UINT32 numMapElements =
- sizeof (ixOsalGlobalMemoryMap) / sizeof (IxOsalMemoryMap);
-
- for (mapIndex = 0; mapIndex < numMapElements; mapIndex++)
- {
- IxOsalMemoryMap *map = &ixOsalGlobalMemoryMap[mapIndex];
-
- if (searchCriteria == SEARCH_PHYSICAL_ADDRESS
- && requestedAddress >= map->physicalAddress
- && (requestedAddress + size) <= (map->physicalAddress + map->size)
- && (map->mapEndianType & requestedEndianType) != 0)
- {
- return map;
- }
- else if (searchCriteria == SEARCH_VIRTUAL_ADDRESS
- && requestedAddress >= map->virtualAddress
- && requestedAddress <= (map->virtualAddress + map->size)
- && (map->mapEndianType & requestedEndianType) != 0)
- {
- return map;
- }
- else if (searchCriteria == SEARCH_PHYSICAL_ADDRESS)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3,
- IX_OSAL_LOG_DEV_STDOUT,
- "Osal: Checking [phys addr 0x%x:size 0x%x:endianType %d]\n",
- map->physicalAddress, map->size, map->mapEndianType, 0, 0, 0);
- }
- }
-
- /*
- * not found
- */
- return NULL;
-}
-
-/*
- * This function maps an I/O mapped physical memory zone of the given size
- * into a virtual memory zone accessible by the caller and returns a cookie -
- * the start address of the virtual memory zone.
- * IX_OSAL_MMAP_PHYS_TO_VIRT should NOT therefore be used on the returned
- * virtual address.
- * The memory zone is to be unmapped using ixOsalMemUnmap once the caller has
- * finished using this zone (e.g. on driver unload) using the cookie as
- * parameter.
- * The IX_OSAL_READ/WRITE_LONG/SHORT macros should be used to read and write
- * the mapped memory, adding the necessary offsets to the address cookie.
- *
- * Note: this function is not to be used directly. Use IX_OSAL_MEM_MAP
- * instead.
- */
-PUBLIC void *
-ixOsalIoMemMap (UINT32 requestedAddress,
- UINT32 size, IxOsalMapEndianessType requestedEndianType)
-{
- IxOsalMemoryMap *map;
-
- ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3,
- IX_OSAL_LOG_DEV_STDOUT,
- "OSAL: Mapping [addr 0x%x:size 0x%x:endianType %d]\n",
- requestedAddress, size, requestedEndianType, 0, 0, 0);
-
- if (requestedEndianType == IX_OSAL_LE)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
- IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalIoMemMap: Please specify component coherency mode to use MEM functions \n",
- 0, 0, 0, 0, 0, 0);
- return (NULL);
- }
- map = ixOsalMemMapFind (requestedAddress,
- size, SEARCH_PHYSICAL_ADDRESS, requestedEndianType);
- if (map != NULL)
- {
- UINT32 offset = requestedAddress - map->physicalAddress;
-
- ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3,
- IX_OSAL_LOG_DEV_STDOUT, "OSAL: Found map [", 0, 0, 0, 0, 0, 0);
- ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3,
- IX_OSAL_LOG_DEV_STDOUT, map->name, 0, 0, 0, 0, 0, 0);
- ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3,
- IX_OSAL_LOG_DEV_STDOUT,
- ":addr 0x%x: virt 0x%x:size 0x%x:ref %d:endianType %d]\n",
- map->physicalAddress, map->virtualAddress,
- map->size, map->refCount, map->mapEndianType, 0);
-
- if (map->type == IX_OSAL_DYNAMIC_MAP && map->virtualAddress == 0)
- {
- if (map->mapFunction != NULL)
- {
- map->mapFunction (map);
-
- if (map->virtualAddress == 0)
- {
- /*
- * failed
- */
- ixOsalLog (IX_OSAL_LOG_LVL_FATAL,
- IX_OSAL_LOG_DEV_STDERR,
- "OSAL: Remap failed - [addr 0x%x:size 0x%x:endianType %d]\n",
- requestedAddress, size, requestedEndianType, 0, 0, 0);
- return NULL;
- }
- }
- else
- {
- /*
- * error, no map function for a dynamic map
- */
- ixOsalLog (IX_OSAL_LOG_LVL_FATAL,
- IX_OSAL_LOG_DEV_STDERR,
- "OSAL: No map function for a dynamic map - "
- "[addr 0x%x:size 0x%x:endianType %d]\n",
- requestedAddress, size, requestedEndianType, 0, 0, 0);
-
- return NULL;
- }
- }
-
- /*
- * increment reference count
- */
- map->refCount++;
-
- return (void *) (map->virtualAddress + offset);
- }
-
- /*
- * requested address is not described in the global memory map
- */
- ixOsalLog (IX_OSAL_LOG_LVL_FATAL,
- IX_OSAL_LOG_DEV_STDERR,
- "OSAL: No mapping found - [addr 0x%x:size 0x%x:endianType %d]\n",
- requestedAddress, size, requestedEndianType, 0, 0, 0);
- return NULL;
-}
-
-/*
- * This function unmaps a previously mapped I/O memory zone using
- * the cookie obtained in the mapping operation. The memory zone in question
- * becomes unavailable to the caller once unmapped and the cookie should be
- * discarded.
- *
- * This function cannot fail if the given parameter is correct and does not
- * return a value.
- *
- * Note: this function is not to be used directly. Use IX_OSAL_MEM_UNMAP
- * instead.
- */
-PUBLIC void
-ixOsalIoMemUnmap (UINT32 requestedAddress, UINT32 endianType)
-{
- IxOsalMemoryMap *map;
-
- if (endianType == IX_OSAL_LE)
- {
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR,
- IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalIoMemUnmap: Please specify component coherency mode to use MEM functions \n",
- 0, 0, 0, 0, 0, 0);
- return;
- }
-
- if (requestedAddress == 0)
- {
- /*
- * invalid virtual address
- */
- return;
- }
-
- map =
- ixOsalMemMapFind (requestedAddress, 0, SEARCH_VIRTUAL_ADDRESS,
- endianType);
-
- if (map != NULL)
- {
- if (map->refCount > 0)
- {
- /*
- * decrement reference count
- */
- map->refCount--;
-
- if (map->refCount == 0)
- {
- /*
- * no longer used, deallocate
- */
- if (map->type == IX_OSAL_DYNAMIC_MAP
- && map->unmapFunction != NULL)
- {
- map->unmapFunction (map);
- }
- }
- }
- }
- else
- {
- ixOsalLog (IX_OSAL_LOG_LVL_WARNING,
- IX_OSAL_LOG_DEV_STDERR,
- "OSAL: ixOsServMemUnmap didn't find the requested map "
- "[virt addr 0x%x: endianType %d], ignoring call\n",
- requestedAddress, endianType, 0, 0, 0, 0);
- }
-}
-
-/*
- * This function Converts a virtual address into a physical
- * address, including the dynamically mapped memory.
- *
- * Parameters virtAddr - virtual address to convert
- * Return value: corresponding physical address, or NULL
- * if there is no physical address addressable
- * by the given virtual address
- * OS: VxWorks, Linux, WinCE, QNX, eCos
- * Reentrant: Yes
- * IRQ safe: Yes
- */
-PUBLIC UINT32
-ixOsalIoMemVirtToPhys (UINT32 virtualAddress, UINT32 requestedCoherency)
-{
- IxOsalMemoryMap *map =
- ixOsalMemMapFind (virtualAddress, 0, SEARCH_VIRTUAL_ADDRESS,
- requestedCoherency);
-
- if (map != NULL)
- {
- return map->physicalAddress + virtualAddress - map->virtualAddress;
- }
- else
- {
- return (UINT32) IX_OSAL_MMU_VIRT_TO_PHYS (virtualAddress);
- }
-}
-
-/*
- * This function Converts a virtual address into a physical
- * address, including the dynamically mapped memory.
- *
- * Parameters virtAddr - virtual address to convert
- * Return value: corresponding physical address, or NULL
- * if there is no physical address addressable
- * by the given virtual address
- * OS: VxWorks, Linux, WinCE, QNX, eCos
- * Reentrant: Yes
- * IRQ safe: Yes
- */
-PUBLIC UINT32
-ixOsalIoMemPhysToVirt (UINT32 physicalAddress, UINT32 requestedCoherency)
-{
- IxOsalMemoryMap *map =
- ixOsalMemMapFind (physicalAddress, 0, SEARCH_PHYSICAL_ADDRESS,
- requestedCoherency);
-
- if (map != NULL)
- {
- return map->virtualAddress + physicalAddress - map->physicalAddress;
- }
- else
- {
- return (UINT32) IX_OSAL_MMU_PHYS_TO_VIRT (physicalAddress);
- }
-}
+++ /dev/null
-/**
- * @file IxOsalOsCacheMMU.c (linux)
- *
- * @brief Cache MemAlloc and MemFree.
- *
- *
- * @par
- * IXP400 SW Release version 1.5
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-
-#include <malloc.h>
-
-/*
- * Allocate on a cache line boundary (null pointers are
- * not affected by this operation). This operation is NOT cache safe.
- */
-void *
-ixOsalCacheDmaMalloc (UINT32 n)
-{
- return malloc(n);
-}
-
-/*
- *
- */
-void
-ixOsalCacheDmaFree (void *ptr)
-{
- free(ptr);
-}
+++ /dev/null
-/**
- * @file IxOsalOsMsgQ.c (eCos)
- *
- * @brief OS-specific Message Queue implementation.
- *
- *
- * @par
- * IXP400 SW Release version 1.5
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-
-/*******************************
- * Public functions
- *******************************/
-PUBLIC IX_STATUS
-ixOsalMessageQueueCreate (IxOsalMessageQueue * queue,
- UINT32 msgCount, UINT32 msgLen)
-{
- diag_printf("%s called\n", __FUNCTION__);
- return IX_FAIL;
-}
-
-PUBLIC IX_STATUS
-ixOsalMessageQueueDelete (IxOsalMessageQueue * queue)
-{
- diag_printf("%s called\n", __FUNCTION__);
- return IX_FAIL;
-}
-
-PUBLIC IX_STATUS
-ixOsalMessageQueueSend (IxOsalMessageQueue * queue, UINT8 * message)
-{
- diag_printf("%s called\n", __FUNCTION__);
- return IX_FAIL;
-}
-
-PUBLIC IX_STATUS
-ixOsalMessageQueueReceive (IxOsalMessageQueue * queue, UINT8 * message)
-{
- diag_printf("%s called\n", __FUNCTION__);
- return IX_FAIL;
-}
-
+++ /dev/null
-/**
- * @file IxOsalOsSemaphore.c (eCos)
- *
- * @brief Implementation for semaphore and mutex.
- *
- *
- * @par
- * IXP400 SW Release version 1.5
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-#include "IxNpeMhReceive_p.h"
-
-/* Define a large number */
-#define IX_OSAL_MAX_LONG (0x7FFFFFFF)
-
-/* Max timeout in MS, used to guard against possible overflow */
-#define IX_OSAL_MAX_TIMEOUT_MS (IX_OSAL_MAX_LONG/HZ)
-
-
-PUBLIC IX_STATUS
-ixOsalSemaphoreInit (IxOsalSemaphore * sid, UINT32 start_value)
-{
- diag_printf("%s called\n", __FUNCTION__);
- return IX_SUCCESS;
-}
-
-/**
- * DESCRIPTION: If the semaphore is 'empty', the calling thread is blocked.
- * If the semaphore is 'full', it is taken and control is returned
- * to the caller. If the time indicated in 'timeout' is reached,
- * the thread will unblock and return an error indication. If the
- * timeout is set to 'IX_OSAL_WAIT_NONE', the thread will never block;
- * if it is set to 'IX_OSAL_WAIT_FOREVER', the thread will block until
- * the semaphore is available.
- *
- *
- */
-
-
-PUBLIC IX_STATUS
-ixOsalSemaphoreWait (IxOsalOsSemaphore * sid, INT32 timeout)
-{
- diag_printf("%s called\n", __FUNCTION__);
- return IX_SUCCESS;
-}
-
-/*
- * Attempt to get semaphore, return immediately,
- * no error info because users expect some failures
- * when using this API.
- */
-PUBLIC IX_STATUS
-ixOsalSemaphoreTryWait (IxOsalSemaphore * sid)
-{
- diag_printf("%s called\n", __FUNCTION__);
- return IX_FAIL;
-}
-
-/**
- *
- * DESCRIPTION: This function causes the next available thread in the pend queue
- * to be unblocked. If no thread is pending on this semaphore, the
- * semaphore becomes 'full'.
- */
-PUBLIC IX_STATUS
-ixOsalSemaphorePost (IxOsalSemaphore * sid)
-{
- diag_printf("%s called\n", __FUNCTION__);
- return IX_SUCCESS;
-}
-
-PUBLIC IX_STATUS
-ixOsalSemaphoreGetValue (IxOsalSemaphore * sid, UINT32 * value)
-{
- diag_printf("%s called\n", __FUNCTION__);
- return IX_FAIL;
-}
-
-PUBLIC IX_STATUS
-ixOsalSemaphoreDestroy (IxOsalSemaphore * sid)
-{
- diag_printf("%s called\n", __FUNCTION__);
- return IX_FAIL;
-}
-
-/****************************
- * Mutex
- ****************************/
-
-static void drv_mutex_init(IxOsalMutex *mutex)
-{
- *mutex = 0;
-}
-
-static void drv_mutex_destroy(IxOsalMutex *mutex)
-{
- *mutex = -1;
-}
-
-static int drv_mutex_trylock(IxOsalMutex *mutex)
-{
- int result = TRUE;
-
- if (*mutex == 1)
- result = FALSE;
-
- return result;
-}
-
-static void drv_mutex_unlock(IxOsalMutex *mutex)
-{
- if (*mutex == 1)
- printf("Trying to unlock unlocked mutex!");
-
- *mutex = 0;
-}
-
-PUBLIC IX_STATUS
-ixOsalMutexInit (IxOsalMutex * mutex)
-{
- drv_mutex_init(mutex);
- return IX_SUCCESS;
-}
-
-PUBLIC IX_STATUS
-ixOsalMutexLock (IxOsalMutex * mutex, INT32 timeout)
-{
- int tries;
-
- if (timeout == IX_OSAL_WAIT_NONE) {
- if (drv_mutex_trylock(mutex))
- return IX_SUCCESS;
- else
- return IX_FAIL;
- }
-
- tries = (timeout * 1000) / 50;
- while (1) {
- if (drv_mutex_trylock(mutex))
- return IX_SUCCESS;
- if (timeout != IX_OSAL_WAIT_FOREVER && tries-- <= 0)
- break;
- udelay(50);
- }
- return IX_FAIL;
-}
-
-PUBLIC IX_STATUS
-ixOsalMutexUnlock (IxOsalMutex * mutex)
-{
- drv_mutex_unlock(mutex);
- return IX_SUCCESS;
-}
-
-/*
- * Attempt to get mutex, return immediately,
- * no error info because users expect some failures
- * when using this API.
- */
-PUBLIC IX_STATUS
-ixOsalMutexTryLock (IxOsalMutex * mutex)
-{
- if (drv_mutex_trylock(mutex))
- return IX_SUCCESS;
- return IX_FAIL;
-}
-
-PUBLIC IX_STATUS
-ixOsalMutexDestroy (IxOsalMutex * mutex)
-{
- drv_mutex_destroy(mutex);
- return IX_SUCCESS;
-}
-
-PUBLIC IX_STATUS
-ixOsalFastMutexInit (IxOsalFastMutex * mutex)
-{
- return ixOsalMutexInit(mutex);
-}
-
-PUBLIC IX_STATUS ixOsalFastMutexTryLock(IxOsalFastMutex *mutex)
-{
- return ixOsalMutexTryLock(mutex);
-}
-
-
-PUBLIC IX_STATUS
-ixOsalFastMutexUnlock (IxOsalFastMutex * mutex)
-{
- return ixOsalMutexUnlock(mutex);
-}
-
-PUBLIC IX_STATUS
-ixOsalFastMutexDestroy (IxOsalFastMutex * mutex)
-{
- return ixOsalMutexDestroy(mutex);
-}
+++ /dev/null
-/**
- * @file IxOsalOsServices.c (linux)
- *
- * @brief Implementation for Irq, Mem, sleep.
- *
- *
- * @par
- * IXP400 SW Release version 1.5
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include <config.h>
-#include <common.h>
-#include "IxOsal.h"
-#include <IxEthAcc.h>
-#include <IxEthDB.h>
-#include <IxNpeDl.h>
-#include <IxQMgr.h>
-#include <IxNpeMh.h>
-
-static char *traceHeaders[] = {
- "",
- "[fatal] ",
- "[error] ",
- "[warning] ",
- "[message] ",
- "[debug1] ",
- "[debug2] ",
- "[debug3] ",
- "[all]"
-};
-
-/* by default trace all but debug message */
-PRIVATE int ixOsalCurrLogLevel = IX_OSAL_LOG_LVL_MESSAGE;
-
-/**************************************
- * Irq services
- *************************************/
-
-PUBLIC IX_STATUS
-ixOsalIrqBind (UINT32 vector, IxOsalVoidFnVoidPtr routine, void *parameter)
-{
- return IX_FAIL;
-}
-
-PUBLIC IX_STATUS
-ixOsalIrqUnbind (UINT32 vector)
-{
- return IX_FAIL;
-}
-
-PUBLIC UINT32
-ixOsalIrqLock ()
-{
- return 0;
-}
-
-/* Enable interrupts and task scheduling,
- * input parameter: irqEnable status returned
- * by ixOsalIrqLock().
- */
-PUBLIC void
-ixOsalIrqUnlock (UINT32 lockKey)
-{
-}
-
-PUBLIC UINT32
-ixOsalIrqLevelSet (UINT32 level)
-{
- return IX_FAIL;
-}
-
-PUBLIC void
-ixOsalIrqEnable (UINT32 irqLevel)
-{
-}
-
-PUBLIC void
-ixOsalIrqDisable (UINT32 irqLevel)
-{
-}
-
-/*********************
- * Log function
- *********************/
-
-INT32
-ixOsalLog (IxOsalLogLevel level,
- IxOsalLogDevice device,
- char *format, int arg1, int arg2, int arg3, int arg4, int arg5, int arg6)
-{
- /*
- * Return -1 for custom display devices
- */
- if ((device != IX_OSAL_LOG_DEV_STDOUT)
- && (device != IX_OSAL_LOG_DEV_STDERR))
- {
- debug("ixOsalLog: only IX_OSAL_LOG_DEV_STDOUT and IX_OSAL_LOG_DEV_STDERR are supported \n");
- return (IX_OSAL_LOG_ERROR);
- }
-
- if (level <= ixOsalCurrLogLevel && level != IX_OSAL_LOG_LVL_NONE)
- {
-#if 0 /* sr: U-Boots printf or debug doesn't return a length */
- int headerByteCount = (level == IX_OSAL_LOG_LVL_USER) ? 0 : diag_printf(traceHeaders[level - 1]);
-
- return headerByteCount + diag_printf (format, arg1, arg2, arg3, arg4, arg5, arg6);
-#else
- int headerByteCount = (level == IX_OSAL_LOG_LVL_USER) ? 0 : strlen(traceHeaders[level - 1]);
-
- return headerByteCount + strlen(format);
-#endif
- }
- else
- {
- /*
- * Return error
- */
- return (IX_OSAL_LOG_ERROR);
- }
-}
-
-PUBLIC UINT32
-ixOsalLogLevelSet (UINT32 level)
-{
- UINT32 oldLevel;
-
- /*
- * Check value first
- */
- if ((level < IX_OSAL_LOG_LVL_NONE) || (level > IX_OSAL_LOG_LVL_ALL))
- {
- ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE,
- IX_OSAL_LOG_DEV_STDOUT,
- "ixOsalLogLevelSet: Log Level is between %d and%d \n",
- IX_OSAL_LOG_LVL_NONE, IX_OSAL_LOG_LVL_ALL, 0, 0, 0, 0);
- return IX_OSAL_LOG_LVL_NONE;
- }
- oldLevel = ixOsalCurrLogLevel;
-
- ixOsalCurrLogLevel = level;
-
- return oldLevel;
-}
-
-/**************************************
- * Task services
- *************************************/
-
-PUBLIC void
-ixOsalBusySleep (UINT32 microseconds)
-{
- udelay(microseconds);
-}
-
-PUBLIC void
-ixOsalSleep (UINT32 milliseconds)
-{
- if (milliseconds != 0) {
-#if 1
- /*
- * sr: We poll while we wait because interrupts are off in U-Boot
- * and CSR expects messages, etc to be dispatched while sleeping.
- */
- int i;
- IxQMgrDispatcherFuncPtr qDispatcherFunc;
-
- ixQMgrDispatcherLoopGet(&qDispatcherFunc);
-
- while (milliseconds--) {
- for (i = 1; i <= 2; i++)
- ixNpeMhMessagesReceive(i);
- (*qDispatcherFunc)(IX_QMGR_QUELOW_GROUP);
-
- udelay(1000);
- }
-#endif
- }
-}
-
-/**************************************
- * Memory functions
- *************************************/
-
-void *
-ixOsalMemAlloc (UINT32 size)
-{
- return (void *)0;
-}
-
-void
-ixOsalMemFree (void *ptr)
-{
-}
-
-/*
- * Copy count bytes from src to dest ,
- * returns pointer to the dest mem zone.
- */
-void *
-ixOsalMemCopy (void *dest, void *src, UINT32 count)
-{
- IX_OSAL_ASSERT (dest != NULL);
- IX_OSAL_ASSERT (src != NULL);
- return (memcpy (dest, src, count));
-}
-
-/*
- * Fills a memory zone with a given constant byte,
- * returns pointer to the memory zone.
- */
-void *
-ixOsalMemSet (void *ptr, UINT8 filler, UINT32 count)
-{
- IX_OSAL_ASSERT (ptr != NULL);
- return (memset (ptr, filler, count));
-}
+++ /dev/null
-/**
- * @file IxOsalOsThread.c (eCos)
- *
- * @brief OS-specific thread implementation.
- *
- *
- * @par
- * IXP400 SW Release version 1.5
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-
-/* Thread attribute is ignored */
-PUBLIC IX_STATUS
-ixOsalThreadCreate (IxOsalThread * ptrTid,
- IxOsalThreadAttr * threadAttr, IxOsalVoidFnVoidPtr entryPoint, void *arg)
-{
- return IX_SUCCESS;
-}
-
-/*
- * Start thread after given its thread handle
- */
-PUBLIC IX_STATUS
-ixOsalThreadStart (IxOsalThread * tId)
-{
- /* Thread already started upon creation */
- return IX_SUCCESS;
-}
-
-/*
- * In Linux threadKill does not actually destroy the thread,
- * it will stop the signal handling.
- */
-PUBLIC IX_STATUS
-ixOsalThreadKill (IxOsalThread * tid)
-{
- return IX_SUCCESS;
-}
-
-PUBLIC void
-ixOsalThreadExit (void)
-{
-}
-
-PUBLIC IX_STATUS
-ixOsalThreadPrioritySet (IxOsalOsThread * tid, UINT32 priority)
-{
- return IX_SUCCESS;
-}
-
-PUBLIC IX_STATUS
-ixOsalThreadSuspend (IxOsalThread * tId)
-{
- return IX_SUCCESS;
-
-}
-
-PUBLIC IX_STATUS
-ixOsalThreadResume (IxOsalThread * tId)
-{
- return IX_SUCCESS;
-}
+++ /dev/null
-/*
- * @file: IxQMgrAqmIf.c
- *
- * @author Intel Corporation
- * @date 30-Oct-2001
- *
- * @brief This component provides a set of functions for
- * perfoming I/O on the AQM hardware.
- *
- * Design Notes:
- * These functions are intended to be as fast as possible
- * and as a result perform NO PARAMETER CHECKING.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * Inlines are compiled as function when this is defined.
- * N.B. Must be placed before #include of "IxQMgrAqmIf_p.h
- */
-#ifndef IXQMGRAQMIF_P_H
-# define IXQMGRAQMIF_C
-#else
-# error
-#endif
-
-/*
- * User defined include files.
- */
-#include "IxOsal.h"
-#include "IxQMgr.h"
-#include "IxQMgrAqmIf_p.h"
-#include "IxQMgrLog_p.h"
-
-
-/*
- * #defines and macros used in this file.
- */
-
-/* These defines are the bit offsets of the various fields of
- * the queue configuration register
- */
-#define IX_QMGR_Q_CONFIG_WRPTR_OFFSET 0x00
-#define IX_QMGR_Q_CONFIG_RDPTR_OFFSET 0x07
-#define IX_QMGR_Q_CONFIG_BADDR_OFFSET 0x0E
-#define IX_QMGR_Q_CONFIG_ESIZE_OFFSET 0x16
-#define IX_QMGR_Q_CONFIG_BSIZE_OFFSET 0x18
-#define IX_QMGR_Q_CONFIG_NE_OFFSET 0x1A
-#define IX_QMGR_Q_CONFIG_NF_OFFSET 0x1D
-
-#define IX_QMGR_BASE_ADDR_16_WORD_ALIGN 0x40
-#define IX_QMGR_BASE_ADDR_16_WORD_SHIFT 0x6
-
-#define IX_QMGR_NE_NF_CLEAR_MASK 0x03FFFFFF
-#define IX_QMGR_NE_MASK 0x7
-#define IX_QMGR_NF_MASK 0x7
-#define IX_QMGR_SIZE_MASK 0x3
-#define IX_QMGR_ENTRY_SIZE_MASK 0x3
-#define IX_QMGR_BADDR_MASK 0x003FC000
-#define IX_QMGR_RDPTR_MASK 0x7F
-#define IX_QMGR_WRPTR_MASK 0x7F
-#define IX_QMGR_RDWRPTR_MASK 0x00003FFF
-
-#define IX_QMGR_AQM_ADDRESS_SPACE_SIZE_IN_WORDS 0x1000
-
-/* Base address of AQM SRAM */
-#define IX_QMGR_AQM_SRAM_BASE_ADDRESS_OFFSET \
-((IX_QMGR_QUECONFIG_BASE_OFFSET) + (IX_QMGR_QUECONFIG_SIZE))
-
-/* Min buffer size used for generating buffer size in QUECONFIG */
-#define IX_QMGR_MIN_BUFFER_SIZE 16
-
-/* Reset values of QMgr hardware registers */
-#define IX_QMGR_QUELOWSTAT_RESET_VALUE 0x33333333
-#define IX_QMGR_QUEUOSTAT_RESET_VALUE 0x00000000
-#define IX_QMGR_QUEUPPSTAT0_RESET_VALUE 0xFFFFFFFF
-#define IX_QMGR_QUEUPPSTAT1_RESET_VALUE 0x00000000
-#define IX_QMGR_INT0SRCSELREG_RESET_VALUE 0x00000000
-#define IX_QMGR_QUEIEREG_RESET_VALUE 0x00000000
-#define IX_QMGR_QINTREG_RESET_VALUE 0xFFFFFFFF
-#define IX_QMGR_QUECONFIG_RESET_VALUE 0x00000000
-
-#define IX_QMGR_PHYSICAL_AQM_BASE_ADDRESS IX_OSAL_IXP400_QMGR_PHYS_BASE
-
-#define IX_QMGR_QUELOWSTAT_BITS_PER_Q (BITS_PER_WORD/IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD)
-
-#define IX_QMGR_QUELOWSTAT_QID_MASK 0x7
-#define IX_QMGR_Q_CONFIG_ADDR_GET(qId)\
- (((qId) * IX_QMGR_NUM_BYTES_PER_WORD) +\
- IX_QMGR_QUECONFIG_BASE_OFFSET)
-
-#define IX_QMGR_ENTRY1_OFFSET 0
-#define IX_QMGR_ENTRY2_OFFSET 1
-#define IX_QMGR_ENTRY4_OFFSET 3
-
-/*
- * Variable declarations global to this file. Externs are followed by
- * statics.
- */
-UINT32 aqmBaseAddress = 0;
-/* Store addresses and bit-masks for certain queue access and status registers.
- * This is to facilitate inlining of QRead, QWrite and QStatusGet functions
- * in IxQMgr,h
- */
-extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
-UINT32 * ixQMgrAqmIfQueAccRegAddr[IX_QMGR_MAX_NUM_QUEUES];
-UINT32 ixQMgrAqmIfQueLowStatRegAddr[IX_QMGR_MIN_QUEUPP_QID];
-UINT32 ixQMgrAqmIfQueLowStatBitsOffset[IX_QMGR_MIN_QUEUPP_QID];
-UINT32 ixQMgrAqmIfQueLowStatBitsMask;
-UINT32 ixQMgrAqmIfQueUppStat0RegAddr;
-UINT32 ixQMgrAqmIfQueUppStat1RegAddr;
-UINT32 ixQMgrAqmIfQueUppStat0BitMask[IX_QMGR_MIN_QUEUPP_QID];
-UINT32 ixQMgrAqmIfQueUppStat1BitMask[IX_QMGR_MIN_QUEUPP_QID];
-
-/*
- * Fast mutexes, one for each queue, used to protect peek & poke functions
- */
-IxOsalFastMutex ixQMgrAqmIfPeekPokeFastMutex[IX_QMGR_MAX_NUM_QUEUES];
-
-/*
- * Function prototypes
- */
-PRIVATE unsigned
-watermarkToAqmWatermark (IxQMgrWMLevel watermark );
-
-PRIVATE unsigned
-entrySizeToAqmEntrySize (IxQMgrQEntrySizeInWords entrySize);
-
-PRIVATE unsigned
-bufferSizeToAqmBufferSize (unsigned bufferSizeInWords);
-
-PRIVATE void
-ixQMgrAqmIfRegistersReset (void);
-
-PRIVATE void
-ixQMgrAqmIfEntryAddressGet (unsigned int entryIndex,
- UINT32 configRegWord,
- unsigned int qEntrySizeInwords,
- unsigned int qSizeInWords,
- UINT32 **address);
-/*
- * Function definitions
- */
-void
-ixQMgrAqmIfInit (void)
-{
- UINT32 aqmVirtualAddr;
- int i;
-
- /* The value of aqmBaseAddress depends on the logical address
- * assigned by the MMU.
- */
- aqmVirtualAddr =
- (UINT32) IX_OSAL_MEM_MAP(IX_QMGR_PHYSICAL_AQM_BASE_ADDRESS,
- IX_OSAL_IXP400_QMGR_MAP_SIZE);
- IX_OSAL_ASSERT (aqmVirtualAddr);
-
- ixQMgrAqmIfBaseAddressSet (aqmVirtualAddr);
-
- ixQMgrAqmIfRegistersReset ();
-
- for (i = 0; i< IX_QMGR_MAX_NUM_QUEUES; i++)
- {
- ixOsalFastMutexInit(&ixQMgrAqmIfPeekPokeFastMutex[i]);
-
- /********************************************************************
- * Register addresses and bit masks are calculated and stored here to
- * facilitate inlining of QRead, QWrite and QStatusGet functions in
- * IxQMgr.h.
- * These calculations are normally performed dynamically in inlined
- * functions in IxQMgrAqmIf_p.h, and their semantics are reused here.
- */
-
- /* AQM Queue access reg addresses, per queue */
- ixQMgrAqmIfQueAccRegAddr[i] =
- (UINT32 *)(aqmBaseAddress + IX_QMGR_Q_ACCESS_ADDR_GET(i));
- ixQMgrQInlinedReadWriteInfo[i].qAccRegAddr =
- (volatile UINT32 *)(aqmBaseAddress + IX_QMGR_Q_ACCESS_ADDR_GET(i));
-
-
- ixQMgrQInlinedReadWriteInfo[i].qConfigRegAddr =
- (volatile UINT32 *)(aqmBaseAddress + IX_QMGR_Q_CONFIG_ADDR_GET(i));
-
- /* AQM Queue lower-group (0-31), only */
- if (i < IX_QMGR_MIN_QUEUPP_QID)
- {
- /* AQM Q underflow/overflow status register addresses, per queue */
- ixQMgrQInlinedReadWriteInfo[i].qUOStatRegAddr =
- (volatile UINT32 *)(aqmBaseAddress +
- IX_QMGR_QUEUOSTAT0_OFFSET +
- ((i / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD) *
- IX_QMGR_NUM_BYTES_PER_WORD));
-
- /* AQM Q underflow status bit masks for status register per queue */
- ixQMgrQInlinedReadWriteInfo[i].qUflowStatBitMask =
- (IX_QMGR_UNDERFLOW_BIT_OFFSET + 1) <<
- ((i & (IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD - 1)) *
- (BITS_PER_WORD / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD));
-
- /* AQM Q overflow status bit masks for status register, per queue */
- ixQMgrQInlinedReadWriteInfo[i].qOflowStatBitMask =
- (IX_QMGR_OVERFLOW_BIT_OFFSET + 1) <<
- ((i & (IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD - 1)) *
- (BITS_PER_WORD / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD));
-
- /* AQM Q lower-group (0-31) status register addresses, per queue */
- ixQMgrAqmIfQueLowStatRegAddr[i] = aqmBaseAddress +
- IX_QMGR_QUELOWSTAT0_OFFSET +
- ((i / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD) *
- IX_QMGR_NUM_BYTES_PER_WORD);
-
- /* AQM Q lower-group (0-31) status register bit offset */
- ixQMgrAqmIfQueLowStatBitsOffset[i] =
- (i & (IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD - 1)) *
- (BITS_PER_WORD / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD);
- }
- else /* AQM Q upper-group (32-63), only */
- {
- /* AQM Q upper-group (32-63) Nearly Empty status reg bit masks */
- ixQMgrAqmIfQueUppStat0BitMask[i - IX_QMGR_MIN_QUEUPP_QID] =
- (1 << (i - IX_QMGR_MIN_QUEUPP_QID));
-
- /* AQM Q upper-group (32-63) Full status register bit masks */
- ixQMgrAqmIfQueUppStat1BitMask[i - IX_QMGR_MIN_QUEUPP_QID] =
- (1 << (i - IX_QMGR_MIN_QUEUPP_QID));
- }
- }
-
- /* AQM Q lower-group (0-31) status register bit mask */
- ixQMgrAqmIfQueLowStatBitsMask = (1 <<
- (BITS_PER_WORD /
- IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD)) - 1;
-
- /* AQM Q upper-group (32-63) Nearly Empty status register address */
- ixQMgrAqmIfQueUppStat0RegAddr = aqmBaseAddress + IX_QMGR_QUEUPPSTAT0_OFFSET;
-
- /* AQM Q upper-group (32-63) Full status register address */
- ixQMgrAqmIfQueUppStat1RegAddr = aqmBaseAddress + IX_QMGR_QUEUPPSTAT1_OFFSET;
-}
-
-/*
- * Uninitialise the AqmIf module by unmapping memory, etc
- */
-void
-ixQMgrAqmIfUninit (void)
-{
- UINT32 virtAddr;
-
- ixQMgrAqmIfBaseAddressGet (&virtAddr);
- IX_OSAL_MEM_UNMAP (virtAddr);
- ixQMgrAqmIfBaseAddressSet (0);
-}
-
-/*
- * Set the the logical base address of AQM
- */
-void
-ixQMgrAqmIfBaseAddressSet (UINT32 address)
-{
- aqmBaseAddress = address;
-}
-
-/*
- * Get the logical base address of AQM
- */
-void
-ixQMgrAqmIfBaseAddressGet (UINT32 *address)
-{
- *address = aqmBaseAddress;
-}
-
-/*
- * Get the logical base address of AQM SRAM
- */
-void
-ixQMgrAqmIfSramBaseAddressGet (UINT32 *address)
-{
- *address = aqmBaseAddress +
- IX_QMGR_AQM_SRAM_BASE_ADDRESS_OFFSET;
-}
-
-/*
- * This function will write the status bits of a queue
- * specified by qId.
- */
-void
-ixQMgrAqmIfQRegisterBitsWrite (IxQMgrQId qId,
- UINT32 registerBaseAddrOffset,
- unsigned queuesPerRegWord,
- UINT32 value)
-{
- volatile UINT32 *registerAddress;
- UINT32 registerWord;
- UINT32 statusBitsMask;
- UINT32 bitsPerQueue;
-
- bitsPerQueue = BITS_PER_WORD / queuesPerRegWord;
-
- /*
- * Calculate the registerAddress
- * multiple queues split accross registers
- */
- registerAddress = (UINT32*)(aqmBaseAddress +
- registerBaseAddrOffset +
- ((qId / queuesPerRegWord) *
- IX_QMGR_NUM_BYTES_PER_WORD));
-
- /* Read the current data */
- ixQMgrAqmIfWordRead (registerAddress, ®isterWord);
-
-
- if( (registerBaseAddrOffset == IX_QMGR_INT0SRCSELREG0_OFFSET) &&
- (qId == IX_QMGR_QUEUE_0) )
- {
- statusBitsMask = 0x7 ;
-
- /* Queue 0 at INT0SRCSELREG should not corrupt the value bit-3 */
- value &= 0x7 ;
- }
- else
- {
- /* Calculate the mask for the status bits for this queue. */
- statusBitsMask = ((1 << bitsPerQueue) - 1);
- statusBitsMask <<= ((qId & (queuesPerRegWord - 1)) * bitsPerQueue);
-
- /* Mask out bits in value that would overwrite other q data */
- value <<= ((qId & (queuesPerRegWord - 1)) * bitsPerQueue);
- value &= statusBitsMask;
- }
-
- /* Mask out bits to write to */
- registerWord &= ~statusBitsMask;
-
-
- /* Set the write bits */
- registerWord |= value;
-
- /*
- * Write the data
- */
- ixQMgrAqmIfWordWrite (registerAddress, registerWord);
-}
-
-/*
- * This function generates the parameters that can be used to
- * check if a Qs status matches the specified source select.
- * It calculates which status word to check (statusWordOffset),
- * the value to check the status against (checkValue) and the
- * mask (mask) to mask out all but the bits to check in the status word.
- */
-void
-ixQMgrAqmIfQStatusCheckValsCalc (IxQMgrQId qId,
- IxQMgrSourceId srcSel,
- unsigned int *statusWordOffset,
- UINT32 *checkValue,
- UINT32 *mask)
-{
- UINT32 shiftVal;
-
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- switch (srcSel)
- {
- case IX_QMGR_Q_SOURCE_ID_E:
- *checkValue = IX_QMGR_Q_STATUS_E_BIT_MASK;
- *mask = IX_QMGR_Q_STATUS_E_BIT_MASK;
- break;
- case IX_QMGR_Q_SOURCE_ID_NE:
- *checkValue = IX_QMGR_Q_STATUS_NE_BIT_MASK;
- *mask = IX_QMGR_Q_STATUS_NE_BIT_MASK;
- break;
- case IX_QMGR_Q_SOURCE_ID_NF:
- *checkValue = IX_QMGR_Q_STATUS_NF_BIT_MASK;
- *mask = IX_QMGR_Q_STATUS_NF_BIT_MASK;
- break;
- case IX_QMGR_Q_SOURCE_ID_F:
- *checkValue = IX_QMGR_Q_STATUS_F_BIT_MASK;
- *mask = IX_QMGR_Q_STATUS_F_BIT_MASK;
- break;
- case IX_QMGR_Q_SOURCE_ID_NOT_E:
- *checkValue = 0;
- *mask = IX_QMGR_Q_STATUS_E_BIT_MASK;
- break;
- case IX_QMGR_Q_SOURCE_ID_NOT_NE:
- *checkValue = 0;
- *mask = IX_QMGR_Q_STATUS_NE_BIT_MASK;
- break;
- case IX_QMGR_Q_SOURCE_ID_NOT_NF:
- *checkValue = 0;
- *mask = IX_QMGR_Q_STATUS_NF_BIT_MASK;
- break;
- case IX_QMGR_Q_SOURCE_ID_NOT_F:
- *checkValue = 0;
- *mask = IX_QMGR_Q_STATUS_F_BIT_MASK;
- break;
- default:
- /* Should never hit */
- IX_OSAL_ASSERT(0);
- break;
- }
-
- /* One nibble of status per queue so need to shift the
- * check value and mask out to the correct position.
- */
- shiftVal = (qId % IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD) *
- IX_QMGR_QUELOWSTAT_BITS_PER_Q;
-
- /* Calculate the which status word to check from the qId,
- * 8 Qs status per word
- */
- *statusWordOffset = qId / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD;
-
- *checkValue <<= shiftVal;
- *mask <<= shiftVal;
- }
- else
- {
- /* One status word */
- *statusWordOffset = 0;
- /* Single bits per queue and int source bit hardwired NE,
- * Qs start at 32.
- */
- *mask = 1 << (qId - IX_QMGR_MIN_QUEUPP_QID);
- *checkValue = *mask;
- }
-}
-
-void
-ixQMgrAqmIfQInterruptEnable (IxQMgrQId qId)
-{
- volatile UINT32 *registerAddress;
- UINT32 registerWord;
- UINT32 actualBitOffset;
-
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- registerAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_QUEIEREG0_OFFSET);
- }
- else
- {
- registerAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_QUEIEREG1_OFFSET);
- }
-
- actualBitOffset = 1 << (qId % IX_QMGR_MIN_QUEUPP_QID);
-
- ixQMgrAqmIfWordRead (registerAddress, ®isterWord);
- ixQMgrAqmIfWordWrite (registerAddress, (registerWord | actualBitOffset));
-}
-
-void
-ixQMgrAqmIfQInterruptDisable (IxQMgrQId qId)
-{
- volatile UINT32 *registerAddress;
- UINT32 registerWord;
- UINT32 actualBitOffset;
-
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- registerAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_QUEIEREG0_OFFSET);
- }
- else
- {
- registerAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_QUEIEREG1_OFFSET);
- }
-
- actualBitOffset = 1 << (qId % IX_QMGR_MIN_QUEUPP_QID);
-
- ixQMgrAqmIfWordRead (registerAddress, ®isterWord);
- ixQMgrAqmIfWordWrite (registerAddress, registerWord & (~actualBitOffset));
-}
-
-void
-ixQMgrAqmIfQueCfgWrite (IxQMgrQId qId,
- IxQMgrQSizeInWords qSizeInWords,
- IxQMgrQEntrySizeInWords entrySizeInWords,
- UINT32 freeSRAMAddress)
-{
- volatile UINT32 *cfgAddress = NULL;
- UINT32 qCfg = 0;
- UINT32 baseAddress = 0;
- unsigned aqmEntrySize = 0;
- unsigned aqmBufferSize = 0;
-
- /* Build config register */
- aqmEntrySize = entrySizeToAqmEntrySize (entrySizeInWords);
- qCfg |= (aqmEntrySize&IX_QMGR_ENTRY_SIZE_MASK) <<
- IX_QMGR_Q_CONFIG_ESIZE_OFFSET;
-
- aqmBufferSize = bufferSizeToAqmBufferSize (qSizeInWords);
- qCfg |= (aqmBufferSize&IX_QMGR_SIZE_MASK) << IX_QMGR_Q_CONFIG_BSIZE_OFFSET;
-
- /* baseAddress, calculated relative to aqmBaseAddress and start address */
- baseAddress = freeSRAMAddress -
- (aqmBaseAddress + IX_QMGR_QUECONFIG_BASE_OFFSET);
-
- /* Verify base address aligned to a 16 word boundary */
- if ((baseAddress % IX_QMGR_BASE_ADDR_16_WORD_ALIGN) != 0)
- {
- IX_QMGR_LOG_ERROR0("ixQMgrAqmIfQueCfgWrite () address is not on 16 word boundary\n");
- }
- /* Now convert it to a 16 word pointer as required by QUECONFIG register */
- baseAddress >>= IX_QMGR_BASE_ADDR_16_WORD_SHIFT;
-
-
- qCfg |= (baseAddress << IX_QMGR_Q_CONFIG_BADDR_OFFSET);
-
-
- cfgAddress = (UINT32*)(aqmBaseAddress +
- IX_QMGR_Q_CONFIG_ADDR_GET(qId));
-
-
- /* NOTE: High and Low watermarks are set to zero */
- ixQMgrAqmIfWordWrite (cfgAddress, qCfg);
-}
-
-void
-ixQMgrAqmIfQueCfgRead (IxQMgrQId qId,
- unsigned int numEntries,
- UINT32 *baseAddress,
- unsigned int *ne,
- unsigned int *nf,
- UINT32 *readPtr,
- UINT32 *writePtr)
-{
- UINT32 qcfg;
- UINT32 *cfgAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_Q_CONFIG_ADDR_GET(qId));
- unsigned int qEntrySizeInwords;
- unsigned int qSizeInWords;
- UINT32 *readPtr_ = NULL;
-
- /* Read the queue configuration register */
- ixQMgrAqmIfWordRead (cfgAddress, &qcfg);
-
- /* Extract the base address */
- *baseAddress = (UINT32)((qcfg & IX_QMGR_BADDR_MASK) >>
- (IX_QMGR_Q_CONFIG_BADDR_OFFSET));
-
- /* Base address is a 16 word pointer from the start of AQM SRAM.
- * Convert to absolute word address.
- */
- *baseAddress <<= IX_QMGR_BASE_ADDR_16_WORD_SHIFT;
- *baseAddress += (UINT32)IX_QMGR_QUECONFIG_BASE_OFFSET;
-
- /*
- * Extract the watermarks. 0->0 entries, 1->1 entries, 2->2 entries, 3->4 entries......
- * If ne > 0 ==> neInEntries = 2^(ne - 1)
- * If ne == 0 ==> neInEntries = 0
- * The same applies.
- */
- *ne = ((qcfg) >> (IX_QMGR_Q_CONFIG_NE_OFFSET)) & IX_QMGR_NE_MASK;
- *nf = ((qcfg) >> (IX_QMGR_Q_CONFIG_NF_OFFSET)) & IX_QMGR_NF_MASK;
-
- if (0 != *ne)
- {
- *ne = 1 << (*ne - 1);
- }
- if (0 != *nf)
- {
- *nf = 1 << (*nf - 1);
- }
-
- /* Get the queue entry size in words */
- qEntrySizeInwords = ixQMgrQEntrySizeInWordsGet (qId);
-
- /* Get the queue size in words */
- qSizeInWords = ixQMgrQSizeInWordsGet (qId);
-
- ixQMgrAqmIfEntryAddressGet (0/* Entry 0. i.e the readPtr*/,
- qcfg,
- qEntrySizeInwords,
- qSizeInWords,
- &readPtr_);
- *readPtr = (UINT32)readPtr_;
- *readPtr -= (UINT32)aqmBaseAddress;/* Offset, not absolute address */
-
- *writePtr = (qcfg >> IX_QMGR_Q_CONFIG_WRPTR_OFFSET) & IX_QMGR_WRPTR_MASK;
- *writePtr = *baseAddress + (*writePtr * (IX_QMGR_NUM_BYTES_PER_WORD));
- return;
-}
-
-unsigned
-ixQMgrAqmIfLog2 (unsigned number)
-{
- unsigned count = 0;
-
- /*
- * N.B. this function will return 0
- * for ixQMgrAqmIfLog2 (0)
- */
- while (number/2)
- {
- number /=2;
- count++;
- }
-
- return count;
-}
-
-void ixQMgrAqmIfIntSrcSelReg0Bit3Set (void)
-{
-
- volatile UINT32 *registerAddress;
- UINT32 registerWord;
-
- /*
- * Calculate the registerAddress
- * multiple queues split accross registers
- */
- registerAddress = (UINT32*)(aqmBaseAddress +
- IX_QMGR_INT0SRCSELREG0_OFFSET);
-
- /* Read the current data */
- ixQMgrAqmIfWordRead (registerAddress, ®isterWord);
-
- /* Set the write bits */
- registerWord |= (1<<IX_QMGR_INT0SRCSELREG0_BIT3) ;
-
- /*
- * Write the data
- */
- ixQMgrAqmIfWordWrite (registerAddress, registerWord);
-}
-
-
-void
-ixQMgrAqmIfIntSrcSelWrite (IxQMgrQId qId,
- IxQMgrSourceId sourceId)
-{
- ixQMgrAqmIfQRegisterBitsWrite (qId,
- IX_QMGR_INT0SRCSELREG0_OFFSET,
- IX_QMGR_INTSRC_NUM_QUE_PER_WORD,
- sourceId);
-}
-
-
-
-void
-ixQMgrAqmIfWatermarkSet (IxQMgrQId qId,
- unsigned ne,
- unsigned nf)
-{
- volatile UINT32 *address = 0;
- UINT32 value = 0;
- unsigned aqmNeWatermark = 0;
- unsigned aqmNfWatermark = 0;
-
- address = (UINT32*)(aqmBaseAddress +
- IX_QMGR_Q_CONFIG_ADDR_GET(qId));
-
- aqmNeWatermark = watermarkToAqmWatermark (ne);
- aqmNfWatermark = watermarkToAqmWatermark (nf);
-
- /* Read the current watermarks */
- ixQMgrAqmIfWordRead (address, &value);
-
- /* Clear out the old watermarks */
- value &= IX_QMGR_NE_NF_CLEAR_MASK;
-
- /* Generate the value to write */
- value |= (aqmNeWatermark << IX_QMGR_Q_CONFIG_NE_OFFSET) |
- (aqmNfWatermark << IX_QMGR_Q_CONFIG_NF_OFFSET);
-
- ixQMgrAqmIfWordWrite (address, value);
-
-}
-
-PRIVATE void
-ixQMgrAqmIfEntryAddressGet (unsigned int entryIndex,
- UINT32 configRegWord,
- unsigned int qEntrySizeInwords,
- unsigned int qSizeInWords,
- UINT32 **address)
-{
- UINT32 readPtr;
- UINT32 baseAddress;
- UINT32 *topOfAqmSram;
-
- topOfAqmSram = ((UINT32 *)aqmBaseAddress + IX_QMGR_AQM_ADDRESS_SPACE_SIZE_IN_WORDS);
-
- /* Extract the base address */
- baseAddress = (UINT32)((configRegWord & IX_QMGR_BADDR_MASK) >>
- (IX_QMGR_Q_CONFIG_BADDR_OFFSET));
-
- /* Base address is a 16 word pointer from the start of AQM SRAM.
- * Convert to absolute word address.
- */
- baseAddress <<= IX_QMGR_BASE_ADDR_16_WORD_SHIFT;
- baseAddress += ((UINT32)aqmBaseAddress + (UINT32)IX_QMGR_QUECONFIG_BASE_OFFSET);
-
- /* Extract the read pointer. Read pointer is a word pointer */
- readPtr = (UINT32)((configRegWord >>
- IX_QMGR_Q_CONFIG_RDPTR_OFFSET)&IX_QMGR_RDPTR_MASK);
-
- /* Read/Write pointers(word pointers) are offsets from the queue buffer space base address.
- * Calculate the absolute read pointer address. NOTE: Queues are circular buffers.
- */
- readPtr = (readPtr + (entryIndex * qEntrySizeInwords)) & (qSizeInWords - 1); /* Mask by queue size */
- *address = (UINT32 *)(baseAddress + (readPtr * (IX_QMGR_NUM_BYTES_PER_WORD)));
-
- switch (qEntrySizeInwords)
- {
- case IX_QMGR_Q_ENTRY_SIZE1:
- IX_OSAL_ASSERT((*address + IX_QMGR_ENTRY1_OFFSET) < topOfAqmSram);
- break;
- case IX_QMGR_Q_ENTRY_SIZE2:
- IX_OSAL_ASSERT((*address + IX_QMGR_ENTRY2_OFFSET) < topOfAqmSram);
- break;
- case IX_QMGR_Q_ENTRY_SIZE4:
- IX_OSAL_ASSERT((*address + IX_QMGR_ENTRY4_OFFSET) < topOfAqmSram);
- break;
- default:
- IX_QMGR_LOG_ERROR0("Invalid Q Entry size passed to ixQMgrAqmIfEntryAddressGet");
- break;
- }
-
-}
-
-IX_STATUS
-ixQMgrAqmIfQPeek (IxQMgrQId qId,
- unsigned int entryIndex,
- unsigned int *entry)
-{
- UINT32 *cfgRegAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_Q_CONFIG_ADDR_GET(qId));
- UINT32 *entryAddress = NULL;
- UINT32 configRegWordOnEntry;
- UINT32 configRegWordOnExit;
- unsigned int qEntrySizeInwords;
- unsigned int qSizeInWords;
-
- /* Get the queue entry size in words */
- qEntrySizeInwords = ixQMgrQEntrySizeInWordsGet (qId);
-
- /* Get the queue size in words */
- qSizeInWords = ixQMgrQSizeInWordsGet (qId);
-
- /* Read the config register */
- ixQMgrAqmIfWordRead (cfgRegAddress, &configRegWordOnEntry);
-
- /* Get the entry address */
- ixQMgrAqmIfEntryAddressGet (entryIndex,
- configRegWordOnEntry,
- qEntrySizeInwords,
- qSizeInWords,
- &entryAddress);
-
- /* Get the lock or return busy */
- if (IX_SUCCESS != ixOsalFastMutexTryLock(&ixQMgrAqmIfPeekPokeFastMutex[qId]))
- {
- return IX_FAIL;
- }
-
- while(qEntrySizeInwords--)
- {
- ixQMgrAqmIfWordRead (entryAddress++, entry++);
- }
-
- /* Release the lock */
- ixOsalFastMutexUnlock(&ixQMgrAqmIfPeekPokeFastMutex[qId]);
-
- /* Read the config register */
- ixQMgrAqmIfWordRead (cfgRegAddress, &configRegWordOnExit);
-
- /* Check that the read and write pointers have not changed */
- if (configRegWordOnEntry != configRegWordOnExit)
- {
- return IX_FAIL;
- }
-
- return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrAqmIfQPoke (IxQMgrQId qId,
- unsigned entryIndex,
- unsigned int *entry)
-{
- UINT32 *cfgRegAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_Q_CONFIG_ADDR_GET(qId));
- UINT32 *entryAddress = NULL;
- UINT32 configRegWordOnEntry;
- UINT32 configRegWordOnExit;
- unsigned int qEntrySizeInwords;
- unsigned int qSizeInWords;
-
- /* Get the queue entry size in words */
- qEntrySizeInwords = ixQMgrQEntrySizeInWordsGet (qId);
-
- /* Get the queue size in words */
- qSizeInWords = ixQMgrQSizeInWordsGet (qId);
-
- /* Read the config register */
- ixQMgrAqmIfWordRead (cfgRegAddress, &configRegWordOnEntry);
-
- /* Get the entry address */
- ixQMgrAqmIfEntryAddressGet (entryIndex,
- configRegWordOnEntry,
- qEntrySizeInwords,
- qSizeInWords,
- &entryAddress);
-
- /* Get the lock or return busy */
- if (IX_SUCCESS != ixOsalFastMutexTryLock(&ixQMgrAqmIfPeekPokeFastMutex[qId]))
- {
- return IX_FAIL;
- }
-
- /* Else read the entry directly from SRAM. This will not move the read pointer */
- while(qEntrySizeInwords--)
- {
- ixQMgrAqmIfWordWrite (entryAddress++, *entry++);
- }
-
- /* Release the lock */
- ixOsalFastMutexUnlock(&ixQMgrAqmIfPeekPokeFastMutex[qId]);
-
- /* Read the config register */
- ixQMgrAqmIfWordRead (cfgRegAddress, &configRegWordOnExit);
-
- /* Check that the read and write pointers have not changed */
- if (configRegWordOnEntry != configRegWordOnExit)
- {
- return IX_FAIL;
- }
-
- return IX_SUCCESS;
-}
-
-PRIVATE unsigned
-watermarkToAqmWatermark (IxQMgrWMLevel watermark )
-{
- unsigned aqmWatermark = 0;
-
- /*
- * Watermarks 0("000"),1("001"),2("010"),4("011"),
- * 8("100"),16("101"),32("110"),64("111")
- */
- aqmWatermark = ixQMgrAqmIfLog2 (watermark * 2);
-
- return aqmWatermark;
-}
-
-PRIVATE unsigned
-entrySizeToAqmEntrySize (IxQMgrQEntrySizeInWords entrySize)
-{
- /* entrySize 1("00"),2("01"),4("10") */
- return (ixQMgrAqmIfLog2 (entrySize));
-}
-
-PRIVATE unsigned
-bufferSizeToAqmBufferSize (unsigned bufferSizeInWords)
-{
- /* bufferSize 16("00"),32("01),64("10"),128("11") */
- return (ixQMgrAqmIfLog2 (bufferSizeInWords / IX_QMGR_MIN_BUFFER_SIZE));
-}
-
-/*
- * Reset AQM registers to default values.
- */
-PRIVATE void
-ixQMgrAqmIfRegistersReset (void)
-{
- volatile UINT32 *qConfigWordAddress = NULL;
- unsigned int i;
-
- /*
- * Need to initialize AQM hardware registers to an initial
- * value as init may have been called as a result of a soft
- * reset. i.e. soft reset does not reset hardware registers.
- */
-
- /* Reset queues 0..31 status registers 0..3 */
- ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUELOWSTAT0_OFFSET),
- IX_QMGR_QUELOWSTAT_RESET_VALUE);
- ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUELOWSTAT1_OFFSET),
- IX_QMGR_QUELOWSTAT_RESET_VALUE);
- ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUELOWSTAT2_OFFSET),
- IX_QMGR_QUELOWSTAT_RESET_VALUE);
- ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUELOWSTAT3_OFFSET),
- IX_QMGR_QUELOWSTAT_RESET_VALUE);
-
- /* Reset underflow/overflow status registers 0..1 */
- ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEUOSTAT0_OFFSET),
- IX_QMGR_QUEUOSTAT_RESET_VALUE);
- ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEUOSTAT1_OFFSET),
- IX_QMGR_QUEUOSTAT_RESET_VALUE);
-
- /* Reset queues 32..63 nearly empty status registers */
- ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEUPPSTAT0_OFFSET),
- IX_QMGR_QUEUPPSTAT0_RESET_VALUE);
-
- /* Reset queues 32..63 full status registers */
- ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEUPPSTAT1_OFFSET),
- IX_QMGR_QUEUPPSTAT1_RESET_VALUE);
-
- /* Reset int0 status flag source select registers 0..3 */
- ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_INT0SRCSELREG0_OFFSET),
- IX_QMGR_INT0SRCSELREG_RESET_VALUE);
- ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_INT0SRCSELREG1_OFFSET),
- IX_QMGR_INT0SRCSELREG_RESET_VALUE);
- ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_INT0SRCSELREG2_OFFSET),
- IX_QMGR_INT0SRCSELREG_RESET_VALUE);
- ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_INT0SRCSELREG3_OFFSET),
- IX_QMGR_INT0SRCSELREG_RESET_VALUE);
-
- /* Reset queue interrupt enable register 0..1 */
- ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEIEREG0_OFFSET),
- IX_QMGR_QUEIEREG_RESET_VALUE);
- ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEIEREG1_OFFSET),
- IX_QMGR_QUEIEREG_RESET_VALUE);
-
- /* Reset queue interrupt register 0..1 */
- ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QINTREG0_OFFSET),
- IX_QMGR_QINTREG_RESET_VALUE);
- ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QINTREG1_OFFSET),
- IX_QMGR_QINTREG_RESET_VALUE);
-
- /* Reset queue configuration words 0..63 */
- qConfigWordAddress = (UINT32 *)(aqmBaseAddress + IX_QMGR_QUECONFIG_BASE_OFFSET);
- for (i = 0; i < (IX_QMGR_QUECONFIG_SIZE / sizeof(UINT32)); i++)
- {
- ixQMgrAqmIfWordWrite(qConfigWordAddress,
- IX_QMGR_QUECONFIG_RESET_VALUE);
- /* Next word */
- qConfigWordAddress++;
- }
-}
-
+++ /dev/null
-/**
- * @file IxQMgrDispatcher.c
- *
- * @author Intel Corporation
- * @date 20-Dec-2001
- *
- * @brief This file contains the implementation of the Dispatcher sub component
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * User defined include files.
- */
-#include "IxQMgr.h"
-#include "IxQMgrAqmIf_p.h"
-#include "IxQMgrQCfg_p.h"
-#include "IxQMgrDispatcher_p.h"
-#include "IxQMgrLog_p.h"
-#include "IxQMgrDefines_p.h"
-#include "IxFeatureCtrl.h"
-#include "IxOsal.h"
-
-
-
-/*
- * #defines and macros used in this file.
- */
-
-
-/*
- * This constant is used to indicate the number of priority levels supported
- */
-#define IX_QMGR_NUM_PRIORITY_LEVELS 3
-
-/*
- * This constant is used to set the size of the array of status words
- */
-#define MAX_Q_STATUS_WORDS 4
-
-/*
- * This macro is used to check if a given priority is valid
- */
-#define IX_QMGR_DISPATCHER_PRIORITY_CHECK(priority) \
-(((priority) >= IX_QMGR_Q_PRIORITY_0) && ((priority) <= IX_QMGR_Q_PRIORITY_2))
-
-/*
- * This macto is used to check that a given interrupt source is valid
- */
-#define IX_QMGR_DISPATCHER_SOURCE_ID_CHECK(srcSel) \
-(((srcSel) >= IX_QMGR_Q_SOURCE_ID_E) && ((srcSel) <= IX_QMGR_Q_SOURCE_ID_NOT_F))
-
-/*
- * Number of times a dummy callback is called before logging a trace
- * message
- */
-#define LOG_THROTTLE_COUNT 1000000
-
-/* Priority tables limits */
-#define IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX (0)
-#define IX_QMGR_MID_LOW_QUE_PRIORITY_TABLE_INDEX (16)
-#define IX_QMGR_MAX_LOW_QUE_PRIORITY_TABLE_INDEX (31)
-#define IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX (32)
-#define IX_QMGR_MID_UPP_QUE_PRIORITY_TABLE_INDEX (48)
-#define IX_QMGR_MAX_UPP_QUE_PRIORITY_TABLE_INDEX (63)
-
-/*
- * This macro is used to check if a given callback type is valid
- */
-#define IX_QMGR_DISPATCHER_CALLBACK_TYPE_CHECK(type) \
- (((type) >= IX_QMGR_TYPE_REALTIME_OTHER) && \
- ((type) <= IX_QMGR_TYPE_REALTIME_SPORADIC))
-
-/*
- * define max index in lower queue to use in loops
- */
-#define IX_QMGR_MAX_LOW_QUE_TABLE_INDEX (31)
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/*
- * Information on a queue needed by the Dispatcher
- */
-typedef struct
-{
- IxQMgrCallback callback; /* Notification callback */
- IxQMgrCallbackId callbackId; /* Notification callback identifier */
- unsigned dummyCallbackCount; /* Number of times runs of dummy callback */
- IxQMgrPriority priority; /* Dispatch priority */
- unsigned int statusWordOffset; /* Offset to the status word to check */
- UINT32 statusMask; /* Status mask */
- UINT32 statusCheckValue; /* Status check value */
- UINT32 intRegCheckMask; /* Interrupt register check mask */
-} IxQMgrQInfo;
-
-/*
- * Variable declarations global to this file. Externs are followed by
- * statics.
- */
-
-/*
- * Flag to keep record of what dispatcher set in featureCtrl when ixQMgrInit()
- * is called. This is needed because it is possible that a client might
- * change whether the live lock prevention dispatcher is used between
- * calls to ixQMgrInit() and ixQMgrDispatcherLoopGet().
- */
-PRIVATE IX_STATUS ixQMgrOrigB0Dispatcher = IX_FEATURE_CTRL_COMPONENT_ENABLED;
-
-/*
- * keep record of Q types - not in IxQMgrQInfo for performance as
- * it is only used with ixQMgrDispatcherLoopRunB0LLP()
- */
-PRIVATE IxQMgrType ixQMgrQTypes[IX_QMGR_MAX_NUM_QUEUES];
-
-/*
- * This array contains a list of queue identifiers ordered by priority. The table
- * is split logically between queue identifiers 0-31 and 32-63.
- */
-static IxQMgrQId priorityTable[IX_QMGR_MAX_NUM_QUEUES];
-
-/*
- * This flag indicates to the dispatcher that the priority table needs to be rebuilt.
- */
-static BOOL rebuildTable = FALSE;
-
-/* Dispatcher statistics */
-static IxQMgrDispatcherStats dispatcherStats;
-
-/* Table of queue information */
-static IxQMgrQInfo dispatchQInfo[IX_QMGR_MAX_NUM_QUEUES];
-
-/* Masks use to identify the first queues in the priority tables
-* when comparing with the interrupt register
-*/
-static unsigned int lowPriorityTableFirstHalfMask;
-static unsigned int uppPriorityTableFirstHalfMask;
-
-/*
- * Static function prototypes
- */
-
-/*
- * This function is the default callback for all queues
- */
-PRIVATE void
-dummyCallback (IxQMgrQId qId,
- IxQMgrCallbackId cbId);
-
-PRIVATE void
-ixQMgrDispatcherReBuildPriorityTable (void);
-
-/*
- * Function definitions.
- */
-void
-ixQMgrDispatcherInit (void)
-{
- int i;
- IxFeatureCtrlProductId productId = 0;
- IxFeatureCtrlDeviceId deviceId = 0;
- BOOL stickyIntSilicon = TRUE;
-
- /* Set default priorities */
- for (i=0; i< IX_QMGR_MAX_NUM_QUEUES; i++)
- {
- dispatchQInfo[i].callback = dummyCallback;
- dispatchQInfo[i].callbackId = 0;
- dispatchQInfo[i].dummyCallbackCount = 0;
- dispatchQInfo[i].priority = IX_QMGR_Q_PRIORITY_2;
- dispatchQInfo[i].statusWordOffset = 0;
- dispatchQInfo[i].statusCheckValue = 0;
- dispatchQInfo[i].statusMask = 0;
- /*
- * There are two interrupt registers, 32 bits each. One for the lower
- * queues(0-31) and one for the upper queues(32-63). Therefore need to
- * mod by 32 i.e the min upper queue identifier.
- */
- dispatchQInfo[i].intRegCheckMask = (1<<(i%(IX_QMGR_MIN_QUEUPP_QID)));
-
- /*
- * Set the Q types - will only be used with livelock
- */
- ixQMgrQTypes[i] = IX_QMGR_TYPE_REALTIME_OTHER;
-
- /* Reset queue statistics */
- dispatcherStats.queueStats[i].callbackCnt = 0;
- dispatcherStats.queueStats[i].priorityChangeCnt = 0;
- dispatcherStats.queueStats[i].intNoCallbackCnt = 0;
- dispatcherStats.queueStats[i].intLostCallbackCnt = 0;
- dispatcherStats.queueStats[i].notificationEnabled = FALSE;
- dispatcherStats.queueStats[i].srcSel = 0;
-
- }
-
- /* Priority table. Order the table from queue 0 to 63 */
- ixQMgrDispatcherReBuildPriorityTable();
-
- /* Reset statistics */
- dispatcherStats.loopRunCnt = 0;
-
- /* Get the device ID for the underlying silicon */
- deviceId = ixFeatureCtrlDeviceRead();
-
- /* Get the product ID for the underlying silicon */
- productId = ixFeatureCtrlProductIdRead();
-
- /*
- * Check featureCtrl to see if Livelock prevention is required
- */
- ixQMgrOrigB0Dispatcher = ixFeatureCtrlSwConfigurationCheck(
- IX_FEATURECTRL_ORIGB0_DISPATCHER);
-
- /*
- * Check if the silicon supports the sticky interrupt feature.
- * IF (IXP42X AND A0) -> No sticky interrupt feature supported
- */
- if ((IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X ==
- (IX_FEATURE_CTRL_DEVICE_TYPE_MASK & deviceId)) &&
- (IX_FEATURE_CTRL_SILICON_TYPE_A0 ==
- (IX_FEATURE_CTRL_SILICON_STEPPING_MASK & productId)))
- {
- stickyIntSilicon = FALSE;
- }
-
- /*
- * IF user wants livelock prev option AND silicon supports sticky interrupt
- * feature -> enable the sticky interrupt bit
- */
- if ((IX_FEATURE_CTRL_SWCONFIG_DISABLED == ixQMgrOrigB0Dispatcher) &&
- stickyIntSilicon)
- {
- ixQMgrStickyInterruptRegEnable();
- }
-}
-
-IX_STATUS
-ixQMgrDispatcherPrioritySet (IxQMgrQId qId,
- IxQMgrPriority priority)
-{
- int ixQMgrLockKey;
-
- if (!ixQMgrQIsConfigured(qId))
- {
- return IX_QMGR_Q_NOT_CONFIGURED;
- }
-
- if (!IX_QMGR_DISPATCHER_PRIORITY_CHECK(priority))
- {
- return IX_QMGR_Q_INVALID_PRIORITY;
- }
-
- ixQMgrLockKey = ixOsalIrqLock();
-
- /* Change priority */
- dispatchQInfo[qId].priority = priority;
- /* Set flag */
- rebuildTable = TRUE;
-
- ixOsalIrqUnlock(ixQMgrLockKey);
-
-#ifndef NDEBUG
- /* Update statistics */
- dispatcherStats.queueStats[qId].priorityChangeCnt++;
-#endif
-
- return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrNotificationCallbackSet (IxQMgrQId qId,
- IxQMgrCallback callback,
- IxQMgrCallbackId callbackId)
-{
- if (!ixQMgrQIsConfigured(qId))
- {
- return IX_QMGR_Q_NOT_CONFIGURED;
- }
-
- if (NULL == callback)
- {
- /* Reset to dummy callback */
- dispatchQInfo[qId].callback = dummyCallback;
- dispatchQInfo[qId].dummyCallbackCount = 0;
- dispatchQInfo[qId].callbackId = 0;
- }
- else
- {
- dispatchQInfo[qId].callback = callback;
- dispatchQInfo[qId].callbackId = callbackId;
- }
-
- return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrNotificationEnable (IxQMgrQId qId,
- IxQMgrSourceId srcSel)
-{
- IxQMgrQStatus qStatusOnEntry;/* The queue status on entry/exit */
- IxQMgrQStatus qStatusOnExit; /* to this function */
- int ixQMgrLockKey;
-
-#ifndef NDEBUG
- if (!ixQMgrQIsConfigured (qId))
- {
- return IX_QMGR_Q_NOT_CONFIGURED;
- }
-
- if ((qId < IX_QMGR_MIN_QUEUPP_QID) &&
- !IX_QMGR_DISPATCHER_SOURCE_ID_CHECK(srcSel))
- {
- /* QId 0-31 source id invalid */
- return IX_QMGR_INVALID_INT_SOURCE_ID;
- }
-
- if ((IX_QMGR_Q_SOURCE_ID_NE != srcSel) &&
- (qId >= IX_QMGR_MIN_QUEUPP_QID))
- {
- /*
- * For queues 32-63 the interrupt source is fixed to the Nearly
- * Empty status flag and therefore should have a srcSel of NE.
- */
- return IX_QMGR_INVALID_INT_SOURCE_ID;
- }
-#endif
-
-#ifndef NDEBUG
- dispatcherStats.queueStats[qId].notificationEnabled = TRUE;
- dispatcherStats.queueStats[qId].srcSel = srcSel;
-#endif
-
- /* Get the current queue status */
- ixQMgrAqmIfQueStatRead (qId, &qStatusOnEntry);
-
- /*
- * Enabling interrupts results in Read-Modify-Write
- * so need critical section
- */
-
- ixQMgrLockKey = ixOsalIrqLock();
-
- /* Calculate the checkMask and checkValue for this q */
- ixQMgrAqmIfQStatusCheckValsCalc (qId,
- srcSel,
- &dispatchQInfo[qId].statusWordOffset,
- &dispatchQInfo[qId].statusCheckValue,
- &dispatchQInfo[qId].statusMask);
-
-
- /* Set the interupt source is this queue is in the range 0-31 */
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- ixQMgrAqmIfIntSrcSelWrite (qId, srcSel);
- }
-
- /* Enable the interrupt */
- ixQMgrAqmIfQInterruptEnable (qId);
-
- ixOsalIrqUnlock(ixQMgrLockKey);
-
- /* Get the current queue status */
- ixQMgrAqmIfQueStatRead (qId, &qStatusOnExit);
-
- /* If the status has changed return a warning */
- if (qStatusOnEntry != qStatusOnExit)
- {
- return IX_QMGR_WARNING;
- }
-
- return IX_SUCCESS;
-}
-
-
-IX_STATUS
-ixQMgrNotificationDisable (IxQMgrQId qId)
-{
- int ixQMgrLockKey;
-
-#ifndef NDEBUG
- /* Validate parameters */
- if (!ixQMgrQIsConfigured (qId))
- {
- return IX_QMGR_Q_NOT_CONFIGURED;
- }
-#endif
-
- /*
- * Enabling interrupts results in Read-Modify-Write
- * so need critical section
- */
-#ifndef NDEBUG
- dispatcherStats.queueStats[qId].notificationEnabled = FALSE;
-#endif
-
- ixQMgrLockKey = ixOsalIrqLock();
-
- ixQMgrAqmIfQInterruptDisable (qId);
-
- ixOsalIrqUnlock(ixQMgrLockKey);
-
- return IX_SUCCESS;
-}
-
-void
-ixQMgrStickyInterruptRegEnable(void)
-{
- /* Use Aqm If function to set Interrupt Register0 Bit-3 */
- ixQMgrAqmIfIntSrcSelReg0Bit3Set ();
-}
-
-#if !defined __XSCALE__ || defined __linux
-
-/* Count the number of leading zero bits in a word,
- * and return the same value than the CLZ instruction.
- *
- * word (in) return value (out)
- * 0x80000000 0
- * 0x40000000 1
- * ,,, ,,,
- * 0x00000002 30
- * 0x00000001 31
- * 0x00000000 32
- *
- * The C version of this function is used as a replacement
- * for system not providing the equivalent of the CLZ
- * assembly language instruction.
- *
- * Note that this version is big-endian
- */
-unsigned int
-ixQMgrCountLeadingZeros(UINT32 word)
-{
- unsigned int leadingZerosCount = 0;
-
- if (word == 0)
- {
- return 32;
- }
- /* search the first bit set by testing the MSB and shifting the input word */
- while ((word & 0x80000000) == 0)
- {
- word <<= 1;
- leadingZerosCount++;
- }
- return leadingZerosCount;
-}
-#endif /* not __XSCALE__ or __linux */
-
-void
-ixQMgrDispatcherLoopGet (IxQMgrDispatcherFuncPtr *qDispatcherFuncPtr)
-{
- IxFeatureCtrlProductId productId = 0;
- IxFeatureCtrlDeviceId deviceId = 0;
-
- /* Get the device ID for the underlying silicon */
- deviceId = ixFeatureCtrlDeviceRead();
-
- /* Get the product ID for the underlying silicon */
- productId = ixFeatureCtrlProductIdRead ();
-
- /* IF (IXP42X AND A0 silicon) -> use ixQMgrDispatcherLoopRunA0 */
- if ((IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X ==
- (IX_FEATURE_CTRL_DEVICE_TYPE_MASK & deviceId)) &&
- (IX_FEATURE_CTRL_SILICON_TYPE_A0 ==
- (IX_FEATURE_CTRL_SILICON_STEPPING_MASK & productId)))
- {
- /*For IXP42X A0 silicon */
- *qDispatcherFuncPtr = &ixQMgrDispatcherLoopRunA0 ;
- }
- else /*For IXP42X B0 or IXP46X silicon*/
- {
- if (IX_FEATURE_CTRL_SWCONFIG_ENABLED == ixQMgrOrigB0Dispatcher)
- {
- /* Default for IXP42X B0 and IXP46X silicon */
- *qDispatcherFuncPtr = &ixQMgrDispatcherLoopRunB0;
- }
- else
- {
- /* FeatureCtrl indicated that livelock dispatcher be used */
- *qDispatcherFuncPtr = &ixQMgrDispatcherLoopRunB0LLP;
- }
- }
-}
-
-void
-ixQMgrDispatcherLoopRunA0 (IxQMgrDispatchGroup group)
-{
- UINT32 intRegVal; /* Interrupt reg val */
- UINT32 intRegValAfterWrite; /* Interrupt reg val after writing back */
- UINT32 intRegCheckMask; /* Mask for checking interrupt bits */
- UINT32 qStatusWordsB4Write[MAX_Q_STATUS_WORDS]; /* Status b4 interrupt write */
- UINT32 qStatusWordsAfterWrite[MAX_Q_STATUS_WORDS]; /* Status after interrupt write */
- IxQMgrQInfo *currDispatchQInfo;
- BOOL statusChangeFlag;
-
- int priorityTableIndex;/* Priority table index */
- int qIndex; /* Current queue being processed */
- int endIndex; /* Index of last queue to process */
-
-#ifndef NDEBUG
- IX_OSAL_ASSERT((group == IX_QMGR_QUEUPP_GROUP) ||
- (group == IX_QMGR_QUELOW_GROUP));
-#endif
-
- /* Read Q status registers before interrupt status read/write */
- ixQMgrAqmIfQStatusRegsRead (group, qStatusWordsB4Write);
-
- /* Read the interrupt register */
- ixQMgrAqmIfQInterruptRegRead (group, &intRegVal);
-
- /* No bit set : nothing to process (the reaminder of the algorithm is
- * based on the fact that the interrupt register value contains at
- * least one bit set
- */
- if (intRegVal == 0)
- {
-#ifndef NDEBUG
- /* Update statistics */
- dispatcherStats.loopRunCnt++;
-#endif
-
- /* Rebuild the priority table if needed */
- if (rebuildTable)
- {
- ixQMgrDispatcherReBuildPriorityTable ();
- }
-
- return;
- }
-
- /* Write it back to clear the interrupt */
- ixQMgrAqmIfQInterruptRegWrite (group, intRegVal);
-
- /* Read Q status registers after interrupt status read/write */
- ixQMgrAqmIfQStatusRegsRead (group, qStatusWordsAfterWrite);
-
- /* get the first queue Id from the interrupt register value */
- qIndex = (BITS_PER_WORD - 1) - ixQMgrCountLeadingZeros(intRegVal);
-
- /* check if any change occured during hw register modifications */
- if (IX_QMGR_QUELOW_GROUP == group)
- {
- statusChangeFlag =
- (qStatusWordsB4Write[0] != qStatusWordsAfterWrite[0]) ||
- (qStatusWordsB4Write[1] != qStatusWordsAfterWrite[1]) ||
- (qStatusWordsB4Write[2] != qStatusWordsAfterWrite[2]) ||
- (qStatusWordsB4Write[3] != qStatusWordsAfterWrite[3]);
- }
- else
- {
- statusChangeFlag =
- (qStatusWordsB4Write[0] != qStatusWordsAfterWrite[0]);
- /* Set the queue range based on the queue group to proccess */
- qIndex += IX_QMGR_MIN_QUEUPP_QID;
- }
-
- if (statusChangeFlag == FALSE)
- {
- /* check if the interrupt register contains
- * only 1 bit set (happy day scenario)
- */
- currDispatchQInfo = &dispatchQInfo[qIndex];
- if (intRegVal == currDispatchQInfo->intRegCheckMask)
- {
- /* only 1 queue event triggered a notification *
- * Call the callback function for this queue
- */
- currDispatchQInfo->callback (qIndex,
- currDispatchQInfo->callbackId);
-#ifndef NDEBUG
- /* Update statistics */
- dispatcherStats.queueStats[qIndex].callbackCnt++;
-#endif
- }
- else
- {
- /* the event is triggered by more than 1 queue,
- * the queue search will be starting from the beginning
- * or the middle of the priority table
- *
- * the serach will end when all the bits of the interrupt
- * register are cleared. There is no need to maintain
- * a seperate value and test it at each iteration.
- */
- if (IX_QMGR_QUELOW_GROUP == group)
- {
- /* check if any bit related to queues in the first
- * half of the priority table is set
- */
- if (intRegVal & lowPriorityTableFirstHalfMask)
- {
- priorityTableIndex = IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX;
- }
- else
- {
- priorityTableIndex = IX_QMGR_MID_LOW_QUE_PRIORITY_TABLE_INDEX;
- }
- }
- else
- {
- /* check if any bit related to queues in the first
- * half of the priority table is set
- */
- if (intRegVal & uppPriorityTableFirstHalfMask)
- {
- priorityTableIndex = IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX;
- }
- else
- {
- priorityTableIndex = IX_QMGR_MID_UPP_QUE_PRIORITY_TABLE_INDEX;
- }
- }
-
- /* iterate following the priority table until all the bits
- * of the interrupt register are cleared.
- */
- do
- {
- qIndex = priorityTable[priorityTableIndex++];
- currDispatchQInfo = &dispatchQInfo[qIndex];
- intRegCheckMask = currDispatchQInfo->intRegCheckMask;
-
- /* If this queue caused this interrupt to be raised */
- if (intRegVal & intRegCheckMask)
- {
- /* Call the callback function for this queue */
- currDispatchQInfo->callback (qIndex,
- currDispatchQInfo->callbackId);
-#ifndef NDEBUG
- /* Update statistics */
- dispatcherStats.queueStats[qIndex].callbackCnt++;
-#endif
-
- /* Clear the interrupt register bit */
- intRegVal &= ~intRegCheckMask;
- }
- }
- while(intRegVal);
- }
- }
- else
- {
- /* A change in queue status occured during the hw interrupt
- * register update. To maintain the interrupt consistency, it
- * is necessary to iterate through all queues of the queue group.
- */
-
- /* Read interrupt status again */
- ixQMgrAqmIfQInterruptRegRead (group, &intRegValAfterWrite);
-
- if (IX_QMGR_QUELOW_GROUP == group)
- {
- priorityTableIndex = IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX;
- endIndex = IX_QMGR_MAX_LOW_QUE_PRIORITY_TABLE_INDEX;
- }
- else
- {
- priorityTableIndex = IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX;
- endIndex = IX_QMGR_MAX_UPP_QUE_PRIORITY_TABLE_INDEX;
- }
-
- for ( ; priorityTableIndex<=endIndex; priorityTableIndex++)
- {
- qIndex = priorityTable[priorityTableIndex];
- currDispatchQInfo = &dispatchQInfo[qIndex];
- intRegCheckMask = currDispatchQInfo->intRegCheckMask;
-
- /* If this queue caused this interrupt to be raised */
- if (intRegVal & intRegCheckMask)
- {
- /* Call the callback function for this queue */
- currDispatchQInfo->callback (qIndex,
- currDispatchQInfo->callbackId);
-#ifndef NDEBUG
- /* Update statistics */
- dispatcherStats.queueStats[qIndex].callbackCnt++;
-#endif
-
- } /* if (intRegVal .. */
-
- /*
- * If interrupt bit is set in intRegValAfterWrite don't
- * proceed as this will be caught in next interrupt
- */
- else if ((intRegValAfterWrite & intRegCheckMask) == 0)
- {
- /* Check if an interrupt was lost for this Q */
- if (ixQMgrAqmIfQStatusCheck(qStatusWordsB4Write,
- qStatusWordsAfterWrite,
- currDispatchQInfo->statusWordOffset,
- currDispatchQInfo->statusCheckValue,
- currDispatchQInfo->statusMask))
- {
- /* Call the callback function for this queue */
- currDispatchQInfo->callback (qIndex,
- dispatchQInfo[qIndex].callbackId);
-#ifndef NDEBUG
- /* Update statistics */
- dispatcherStats.queueStats[qIndex].callbackCnt++;
- dispatcherStats.queueStats[qIndex].intLostCallbackCnt++;
-#endif
- } /* if ixQMgrAqmIfQStatusCheck(.. */
- } /* else if ((intRegValAfterWrite ... */
- } /* for (priorityTableIndex=0 ... */
- }
-
- /* Rebuild the priority table if needed */
- if (rebuildTable)
- {
- ixQMgrDispatcherReBuildPriorityTable ();
- }
-
-#ifndef NDEBUG
- /* Update statistics */
- dispatcherStats.loopRunCnt++;
-#endif
-}
-
-
-
-void
-ixQMgrDispatcherLoopRunB0 (IxQMgrDispatchGroup group)
-{
- UINT32 intRegVal; /* Interrupt reg val */
- UINT32 intRegCheckMask; /* Mask for checking interrupt bits */
- IxQMgrQInfo *currDispatchQInfo;
-
-
- int priorityTableIndex; /* Priority table index */
- int qIndex; /* Current queue being processed */
-
-#ifndef NDEBUG
- IX_OSAL_ASSERT((group == IX_QMGR_QUEUPP_GROUP) ||
- (group == IX_QMGR_QUELOW_GROUP));
- IX_OSAL_ASSERT((group == IX_QMGR_QUEUPP_GROUP) ||
- (group == IX_QMGR_QUELOW_GROUP));
-#endif
-
- /* Read the interrupt register */
- ixQMgrAqmIfQInterruptRegRead (group, &intRegVal);
-
-
- /* No queue has interrupt register set */
- if (intRegVal != 0)
- {
-
- /* Write it back to clear the interrupt */
- ixQMgrAqmIfQInterruptRegWrite (group, intRegVal);
-
- /* get the first queue Id from the interrupt register value */
- qIndex = (BITS_PER_WORD - 1) - ixQMgrCountLeadingZeros(intRegVal);
-
- if (IX_QMGR_QUEUPP_GROUP == group)
- {
- /* Set the queue range based on the queue group to proccess */
- qIndex += IX_QMGR_MIN_QUEUPP_QID;
- }
-
- /* check if the interrupt register contains
- * only 1 bit set
- * For example:
- * intRegVal = 0x0010
- * currDispatchQInfo->intRegCheckMask = 0x0010
- * intRegVal == currDispatchQInfo->intRegCheckMask is TRUE.
- */
- currDispatchQInfo = &dispatchQInfo[qIndex];
- if (intRegVal == currDispatchQInfo->intRegCheckMask)
- {
- /* only 1 queue event triggered a notification *
- * Call the callback function for this queue
- */
- currDispatchQInfo->callback (qIndex,
- currDispatchQInfo->callbackId);
-#ifndef NDEBUG
- /* Update statistics */
- dispatcherStats.queueStats[qIndex].callbackCnt++;
-#endif
- }
- else
- {
- /* the event is triggered by more than 1 queue,
- * the queue search will be starting from the beginning
- * or the middle of the priority table
- *
- * the serach will end when all the bits of the interrupt
- * register are cleared. There is no need to maintain
- * a seperate value and test it at each iteration.
- */
- if (IX_QMGR_QUELOW_GROUP == group)
- {
- /* check if any bit related to queues in the first
- * half of the priority table is set
- */
- if (intRegVal & lowPriorityTableFirstHalfMask)
- {
- priorityTableIndex = IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX;
- }
- else
- {
- priorityTableIndex = IX_QMGR_MID_LOW_QUE_PRIORITY_TABLE_INDEX;
- }
- }
- else
- {
- /* check if any bit related to queues in the first
- * half of the priority table is set
- */
- if (intRegVal & uppPriorityTableFirstHalfMask)
- {
- priorityTableIndex = IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX;
- }
- else
- {
- priorityTableIndex = IX_QMGR_MID_UPP_QUE_PRIORITY_TABLE_INDEX;
- }
- }
-
- /* iterate following the priority table until all the bits
- * of the interrupt register are cleared.
- */
- do
- {
- qIndex = priorityTable[priorityTableIndex++];
- currDispatchQInfo = &dispatchQInfo[qIndex];
- intRegCheckMask = currDispatchQInfo->intRegCheckMask;
-
- /* If this queue caused this interrupt to be raised */
- if (intRegVal & intRegCheckMask)
- {
- /* Call the callback function for this queue */
- currDispatchQInfo->callback (qIndex,
- currDispatchQInfo->callbackId);
-#ifndef NDEBUG
- /* Update statistics */
- dispatcherStats.queueStats[qIndex].callbackCnt++;
-#endif
-
- /* Clear the interrupt register bit */
- intRegVal &= ~intRegCheckMask;
- }
- }
- while(intRegVal);
- } /*End of intRegVal == currDispatchQInfo->intRegCheckMask */
- } /* End of intRegVal != 0 */
-
-#ifndef NDEBUG
- /* Update statistics */
- dispatcherStats.loopRunCnt++;
-#endif
-
- /* Rebuild the priority table if needed */
- if (rebuildTable)
- {
- ixQMgrDispatcherReBuildPriorityTable ();
- }
-}
-
-void
-ixQMgrDispatcherLoopRunB0LLP (IxQMgrDispatchGroup group)
-{
- UINT32 intRegVal =0; /* Interrupt reg val */
- UINT32 intRegCheckMask; /* Mask for checking interrupt bits */
- IxQMgrQInfo *currDispatchQInfo;
-
- int priorityTableIndex; /* Priority table index */
- int qIndex; /* Current queue being processed */
-
- UINT32 intRegValCopy = 0;
- UINT32 intEnableRegVal = 0;
- UINT8 i = 0;
-
-#ifndef NDEBUG
- IX_OSAL_ASSERT((group == IX_QMGR_QUEUPP_GROUP) ||
- (group == IX_QMGR_QUELOW_GROUP));
-#endif
-
- /* Read the interrupt register */
- ixQMgrAqmIfQInterruptRegRead (group, &intRegVal);
-
- /*
- * mask any interrupts that are not enabled
- */
- ixQMgrAqmIfQInterruptEnableRegRead (group, &intEnableRegVal);
- intRegVal &= intEnableRegVal;
-
- /* No queue has interrupt register set */
- if (intRegVal != 0)
- {
- if (IX_QMGR_QUELOW_GROUP == group)
- {
- /*
- * As the sticky bit is set, the interrupt register will
- * not clear if write back at this point because the condition
- * has not been cleared. Take a copy and write back later after
- * the condition has been cleared
- */
- intRegValCopy = intRegVal;
- }
- else
- {
- /* no sticky for upper Q's, so write back now */
- ixQMgrAqmIfQInterruptRegWrite (group, intRegVal);
- }
-
- /* get the first queue Id from the interrupt register value */
- qIndex = (BITS_PER_WORD - 1) - ixQMgrCountLeadingZeros(intRegVal);
-
- if (IX_QMGR_QUEUPP_GROUP == group)
- {
- /* Set the queue range based on the queue group to proccess */
- qIndex += IX_QMGR_MIN_QUEUPP_QID;
- }
-
- /* check if the interrupt register contains
- * only 1 bit set
- * For example:
- * intRegVal = 0x0010
- * currDispatchQInfo->intRegCheckMask = 0x0010
- * intRegVal == currDispatchQInfo->intRegCheckMask is TRUE.
- */
- currDispatchQInfo = &dispatchQInfo[qIndex];
- if (intRegVal == currDispatchQInfo->intRegCheckMask)
- {
-
- /*
- * check if Q type periodic - only lower queues can
- * have there type set to periodic
- */
- if (IX_QMGR_TYPE_REALTIME_PERIODIC == ixQMgrQTypes[qIndex])
- {
- /*
- * Disable the notifications on any sporadics
- */
- for (i=0; i <= IX_QMGR_MAX_LOW_QUE_TABLE_INDEX; i++)
- {
- if (IX_QMGR_TYPE_REALTIME_SPORADIC == ixQMgrQTypes[i])
- {
- ixQMgrNotificationDisable(i);
-#ifndef NDEBUG
- /* Update statistics */
- dispatcherStats.queueStats[i].disableCount++;
-#endif
- }
- }
- }
-
- currDispatchQInfo->callback (qIndex,
- currDispatchQInfo->callbackId);
-#ifndef NDEBUG
- /* Update statistics */
- dispatcherStats.queueStats[qIndex].callbackCnt++;
-#endif
- }
- else
- {
- /* the event is triggered by more than 1 queue,
- * the queue search will be starting from the beginning
- * or the middle of the priority table
- *
- * the serach will end when all the bits of the interrupt
- * register are cleared. There is no need to maintain
- * a seperate value and test it at each iteration.
- */
- if (IX_QMGR_QUELOW_GROUP == group)
- {
- /* check if any bit related to queues in the first
- * half of the priority table is set
- */
- if (intRegVal & lowPriorityTableFirstHalfMask)
- {
- priorityTableIndex =
- IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX;
- }
- else
- {
- priorityTableIndex =
- IX_QMGR_MID_LOW_QUE_PRIORITY_TABLE_INDEX;
- }
- }
- else
- {
- /* check if any bit related to queues in the first
- * half of the priority table is set
- */
- if (intRegVal & uppPriorityTableFirstHalfMask)
- {
- priorityTableIndex =
- IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX;
- }
- else
- {
- priorityTableIndex =
- IX_QMGR_MID_UPP_QUE_PRIORITY_TABLE_INDEX;
- }
- }
-
- /* iterate following the priority table until all the bits
- * of the interrupt register are cleared.
- */
- do
- {
- qIndex = priorityTable[priorityTableIndex++];
- currDispatchQInfo = &dispatchQInfo[qIndex];
- intRegCheckMask = currDispatchQInfo->intRegCheckMask;
-
- /* If this queue caused this interrupt to be raised */
- if (intRegVal & intRegCheckMask)
- {
- /*
- * check if Q type periodic - only lower queues can
- * have there type set to periodic. There can only be one
- * periodic queue, so the sporadics are only disabled once.
- */
- if (IX_QMGR_TYPE_REALTIME_PERIODIC == ixQMgrQTypes[qIndex])
- {
- /*
- * Disable the notifications on any sporadics
- */
- for (i=0; i <= IX_QMGR_MAX_LOW_QUE_TABLE_INDEX; i++)
- {
- if (IX_QMGR_TYPE_REALTIME_SPORADIC ==
- ixQMgrQTypes[i])
- {
- ixQMgrNotificationDisable(i);
- /*
- * remove from intRegVal as we don't want
- * to service any sporadics now
- */
- intRegVal &= ~dispatchQInfo[i].intRegCheckMask;
-#ifndef NDEBUG
- /* Update statistics */
- dispatcherStats.queueStats[i].disableCount++;
-#endif
- }
- }
- }
-
- currDispatchQInfo->callback (qIndex,
- currDispatchQInfo->callbackId);
-#ifndef NDEBUG
- /* Update statistics */
- dispatcherStats.queueStats[qIndex].callbackCnt++;
-#endif
- /* Clear the interrupt register bit */
- intRegVal &= ~intRegCheckMask;
- }
- }
- while(intRegVal);
- } /*End of intRegVal == currDispatchQInfo->intRegCheckMask */
- } /* End of intRegVal != 0 */
-
-#ifndef NDEBUG
- /* Update statistics */
- dispatcherStats.loopRunCnt++;
-#endif
-
- if ((intRegValCopy != 0) && (IX_QMGR_QUELOW_GROUP == group))
- {
- /*
- * lower groups (therefore sticky) AND at least one enabled interrupt
- * Write back to clear the interrupt
- */
- ixQMgrAqmIfQInterruptRegWrite (IX_QMGR_QUELOW_GROUP, intRegValCopy);
- }
-
- /* Rebuild the priority table if needed */
- if (rebuildTable)
- {
- ixQMgrDispatcherReBuildPriorityTable ();
- }
-}
-
-PRIVATE void
-ixQMgrDispatcherReBuildPriorityTable (void)
-{
- UINT32 qIndex;
- UINT32 priority;
- int lowQuePriorityTableIndex = IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX;
- int uppQuePriorityTableIndex = IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX;
-
- /* Reset the rebuild flag */
- rebuildTable = FALSE;
-
- /* initialize the mak used to identify the queues in the first half
- * of the priority table
- */
- lowPriorityTableFirstHalfMask = 0;
- uppPriorityTableFirstHalfMask = 0;
-
- /* For each priority level */
- for(priority=0; priority<IX_QMGR_NUM_PRIORITY_LEVELS; priority++)
- {
- /* Foreach low queue in this priority */
- for(qIndex=0; qIndex<IX_QMGR_MIN_QUEUPP_QID; qIndex++)
- {
- if (dispatchQInfo[qIndex].priority == priority)
- {
- /* build the priority table bitmask which match the
- * queues of the first half of the priority table
- */
- if (lowQuePriorityTableIndex < IX_QMGR_MID_LOW_QUE_PRIORITY_TABLE_INDEX)
- {
- lowPriorityTableFirstHalfMask |= dispatchQInfo[qIndex].intRegCheckMask;
- }
- /* build the priority table */
- priorityTable[lowQuePriorityTableIndex++] = qIndex;
- }
- }
- /* Foreach upp queue */
- for(qIndex=IX_QMGR_MIN_QUEUPP_QID; qIndex<=IX_QMGR_MAX_QID; qIndex++)
- {
- if (dispatchQInfo[qIndex].priority == priority)
- {
- /* build the priority table bitmask which match the
- * queues of the first half of the priority table
- */
- if (uppQuePriorityTableIndex < IX_QMGR_MID_UPP_QUE_PRIORITY_TABLE_INDEX)
- {
- uppPriorityTableFirstHalfMask |= dispatchQInfo[qIndex].intRegCheckMask;
- }
- /* build the priority table */
- priorityTable[uppQuePriorityTableIndex++] = qIndex;
- }
- }
- }
-}
-
-IxQMgrDispatcherStats*
-ixQMgrDispatcherStatsGet (void)
-{
- return &dispatcherStats;
-}
-
-PRIVATE void
-dummyCallback (IxQMgrQId qId,
- IxQMgrCallbackId cbId)
-{
- /* Throttle the trace message */
- if ((dispatchQInfo[qId].dummyCallbackCount % LOG_THROTTLE_COUNT) == 0)
- {
- IX_QMGR_LOG_WARNING2("--> dummyCallback: qId (%d), callbackId (%d)\n",qId,cbId);
- }
- dispatchQInfo[qId].dummyCallbackCount++;
-
-#ifndef NDEBUG
- /* Update statistcs */
- dispatcherStats.queueStats[qId].intNoCallbackCnt++;
-#endif
-}
-void
-ixQMgrLLPShow (int resetStats)
-{
-#ifndef NDEBUG
- UINT8 i = 0;
- IxQMgrQInfo *q;
- UINT32 intEnableRegVal = 0;
-
- printf ("Livelock statistics are printed on the fly.\n");
- printf ("qId Type EnableCnt DisableCnt IntEnableState Callbacks\n");
- printf ("=== ======== ========= ========== ============== =========\n");
-
- for (i=0; i<= IX_QMGR_MAX_LOW_QUE_TABLE_INDEX; i++)
- {
- q = &dispatchQInfo[i];
-
- if (ixQMgrQTypes[i] != IX_QMGR_TYPE_REALTIME_OTHER)
- {
- printf (" %2d ", i);
-
- if (ixQMgrQTypes[i] == IX_QMGR_TYPE_REALTIME_SPORADIC)
- {
- printf ("Sporadic");
- }
- else
- {
- printf ("Periodic");
- }
-
-
- ixQMgrAqmIfQInterruptEnableRegRead (IX_QMGR_QUELOW_GROUP,
- &intEnableRegVal);
-
-
- intEnableRegVal &= dispatchQInfo[i].intRegCheckMask;
- intEnableRegVal = intEnableRegVal >> i;
-
- printf (" %10d %10d %10d %10d\n",
- dispatcherStats.queueStats[i].enableCount,
- dispatcherStats.queueStats[i].disableCount,
- intEnableRegVal,
- dispatcherStats.queueStats[i].callbackCnt);
-
- if (resetStats)
- {
- dispatcherStats.queueStats[i].enableCount =
- dispatcherStats.queueStats[i].disableCount =
- dispatcherStats.queueStats[i].callbackCnt = 0;
- }
- }
- }
-#else
- IX_QMGR_LOG0("Livelock Prevention statistics are only collected in debug mode\n");
-#endif
-}
-
-void
-ixQMgrPeriodicDone (void)
-{
- UINT32 i = 0;
- UINT32 ixQMgrLockKey = 0;
-
- /*
- * for the lower queues
- */
- for (i=0; i <= IX_QMGR_MAX_LOW_QUE_TABLE_INDEX; i++)
- {
- /*
- * check for sporadics
- */
- if (IX_QMGR_TYPE_REALTIME_SPORADIC == ixQMgrQTypes[i])
- {
- /*
- * enable any sporadics
- */
- ixQMgrLockKey = ixOsalIrqLock();
- ixQMgrAqmIfQInterruptEnable(i);
- ixOsalIrqUnlock(ixQMgrLockKey);
-#ifndef NDEBUG
- /*
- * Update statistics
- */
- dispatcherStats.queueStats[i].enableCount++;
- dispatcherStats.queueStats[i].notificationEnabled = TRUE;
-#endif
- }
- }
-}
-IX_STATUS
-ixQMgrCallbackTypeSet (IxQMgrQId qId,
- IxQMgrType type)
-{
- UINT32 ixQMgrLockKey = 0;
- IxQMgrType ixQMgrOldType =0;
-
-#ifndef NDEBUG
- if (!ixQMgrQIsConfigured(qId))
- {
- return IX_QMGR_Q_NOT_CONFIGURED;
- }
- if (qId >= IX_QMGR_MIN_QUEUPP_QID)
- {
- return IX_QMGR_PARAMETER_ERROR;
- }
- if(!IX_QMGR_DISPATCHER_CALLBACK_TYPE_CHECK(type))
- {
- return IX_QMGR_PARAMETER_ERROR;
- }
-#endif
-
- ixQMgrOldType = ixQMgrQTypes[qId];
- ixQMgrQTypes[qId] = type;
-
- /*
- * check if Q has been changed from type SPORADIC
- */
- if (IX_QMGR_TYPE_REALTIME_SPORADIC == ixQMgrOldType)
- {
- /*
- * previously Q was a SPORADIC, this means that LLP
- * might have had it disabled. enable it now.
- */
- ixQMgrLockKey = ixOsalIrqLock();
- ixQMgrAqmIfQInterruptEnable(qId);
- ixOsalIrqUnlock(ixQMgrLockKey);
-
-#ifndef NDEBUG
- /*
- * Update statistics
- */
- dispatcherStats.queueStats[qId].enableCount++;
-#endif
- }
-
- return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrCallbackTypeGet (IxQMgrQId qId,
- IxQMgrType *type)
-{
-#ifndef NDEBUG
- if (!ixQMgrQIsConfigured(qId))
- {
- return IX_QMGR_Q_NOT_CONFIGURED;
- }
- if (qId >= IX_QMGR_MIN_QUEUPP_QID)
- {
- return IX_QMGR_PARAMETER_ERROR;
- }
- if(type == NULL)
- {
- return IX_QMGR_PARAMETER_ERROR;
- }
-#endif
-
- *type = ixQMgrQTypes[qId];
- return IX_SUCCESS;
-}
+++ /dev/null
-/**
- * @file IxQMgrInit.c
- *
- * @author Intel Corporation
- * @date 30-Oct-2001
- *
- * @brief: Provided initialization of the QMgr component and its subcomponents.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * System defined include files.
- */
-
-/*
- * User defined include files.
- */
-#include "IxOsal.h"
-#include "IxQMgr.h"
-#include "IxQMgrQCfg_p.h"
-#include "IxQMgrDispatcher_p.h"
-#include "IxQMgrLog_p.h"
-#include "IxQMgrQAccess_p.h"
-#include "IxQMgrDefines_p.h"
-#include "IxQMgrAqmIf_p.h"
-
-/*
- * Set to true if initialized
- * N.B. global so integration/unit tests can reinitialize
- */
-BOOL qMgrIsInitialized = FALSE;
-
-/*
- * Function definitions.
- */
-IX_STATUS
-ixQMgrInit (void)
-{
- if (qMgrIsInitialized)
- {
- IX_QMGR_LOG0("ixQMgrInit: IxQMgr already initialised\n");
- return IX_FAIL;
- }
-
- /* Initialise the QCfg component */
- ixQMgrQCfgInit ();
-
- /* Initialise the Dispatcher component */
- ixQMgrDispatcherInit ();
-
- /* Initialise the Access component */
- ixQMgrQAccessInit ();
-
- /* Initialization complete */
- qMgrIsInitialized = TRUE;
-
- return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrUnload (void)
-{
- if (!qMgrIsInitialized)
- {
- return IX_FAIL;
- }
-
- /* Uninitialise the QCfg component */
- ixQMgrQCfgUninit ();
-
- /* Uninitialization complete */
- qMgrIsInitialized = FALSE;
-
- return IX_SUCCESS;
-}
-
-void
-ixQMgrShow (void)
-{
- IxQMgrQCfgStats *qCfgStats = NULL;
- IxQMgrDispatcherStats *dispatcherStats = NULL;
- int i;
- UINT32 lowIntRegRead, upIntRegRead;
-
- qCfgStats = ixQMgrQCfgStatsGet ();
- dispatcherStats = ixQMgrDispatcherStatsGet ();
- ixQMgrAqmIfQInterruptRegRead (IX_QMGR_QUELOW_GROUP, &lowIntRegRead);
- ixQMgrAqmIfQInterruptRegRead (IX_QMGR_QUEUPP_GROUP, &upIntRegRead);
- printf("Generic Stats........\n");
- printf("=====================\n");
- printf("Loop Run Count..........%u\n",dispatcherStats->loopRunCnt);
- printf("Watermark set count.....%d\n", qCfgStats->wmSetCnt);
- printf("===========================================\n");
- printf("On the fly Interrupt Register Stats........\n");
- printf("===========================================\n");
- printf("Lower Interrupt Register............0x%08x\n",lowIntRegRead);
- printf("Upper Interrupt Register............0x%08x\n",upIntRegRead);
- printf("==============================================\n");
- printf("Queue Specific Stats........\n");
- printf("============================\n");
-
- for (i=0; i<IX_QMGR_MAX_NUM_QUEUES; i++)
- {
- if (ixQMgrQIsConfigured(i))
- {
- ixQMgrQShow(i);
- }
- }
-
- printf("============================\n");
-}
-
-IX_STATUS
-ixQMgrQShow (IxQMgrQId qId)
-{
- IxQMgrQCfgStats *qCfgStats = NULL;
- IxQMgrDispatcherStats *dispatcherStats = NULL;
-
- if (!ixQMgrQIsConfigured(qId))
- {
- return IX_QMGR_Q_NOT_CONFIGURED;
- }
-
- dispatcherStats = ixQMgrDispatcherStatsGet ();
- qCfgStats = ixQMgrQCfgQStatsGet (qId);
-
- printf("QId %d\n", qId);
- printf("======\n");
- printf(" IxQMgrQCfg Stats\n");
- printf(" Name..................... \"%s\"\n", qCfgStats->qStats[qId].qName);
- printf(" Size in words............ %u\n", qCfgStats->qStats[qId].qSizeInWords);
- printf(" Entry size in words...... %u\n", qCfgStats->qStats[qId].qEntrySizeInWords);
- printf(" Nearly empty watermark... %u\n", qCfgStats->qStats[qId].ne);
- printf(" Nearly full watermark.... %u\n", qCfgStats->qStats[qId].nf);
- printf(" Number of full entries... %u\n", qCfgStats->qStats[qId].numEntries);
- printf(" Sram base address........ 0x%X\n", qCfgStats->qStats[qId].baseAddress);
- printf(" Read pointer............. 0x%X\n", qCfgStats->qStats[qId].readPtr);
- printf(" Write pointer............ 0x%X\n", qCfgStats->qStats[qId].writePtr);
-
-#ifndef NDEBUG
- if (dispatcherStats->queueStats[qId].notificationEnabled)
- {
- char *localEvent = "none ????";
- switch (dispatcherStats->queueStats[qId].srcSel)
- {
- case IX_QMGR_Q_SOURCE_ID_E:
- localEvent = "Empty";
- break;
- case IX_QMGR_Q_SOURCE_ID_NE:
- localEvent = "Nearly Empty";
- break;
- case IX_QMGR_Q_SOURCE_ID_NF:
- localEvent = "Nearly Full";
- break;
- case IX_QMGR_Q_SOURCE_ID_F:
- localEvent = "Full";
- break;
- case IX_QMGR_Q_SOURCE_ID_NOT_E:
- localEvent = "Not Empty";
- break;
- case IX_QMGR_Q_SOURCE_ID_NOT_NE:
- localEvent = "Not Nearly Empty";
- break;
- case IX_QMGR_Q_SOURCE_ID_NOT_NF:
- localEvent = "Not Nearly Full";
- break;
- case IX_QMGR_Q_SOURCE_ID_NOT_F:
- localEvent = "Not Full";
- break;
- default :
- break;
- }
- printf(" Notifications localEvent...... %s\n", localEvent);
- }
- else
- {
- printf(" Notifications............ not enabled\n");
- }
- printf(" IxQMgrDispatcher Stats\n");
- printf(" Callback count................%d\n",
- dispatcherStats->queueStats[qId].callbackCnt);
- printf(" Priority change count.........%d\n",
- dispatcherStats->queueStats[qId].priorityChangeCnt);
- printf(" Interrupt no callback count...%d\n",
- dispatcherStats->queueStats[qId].intNoCallbackCnt);
- printf(" Interrupt lost callback count...%d\n",
- dispatcherStats->queueStats[qId].intLostCallbackCnt);
-#endif
-
- return IX_SUCCESS;
-}
-
-
-
-
+++ /dev/null
-/**
- * @file IxQMgrQAccess.c
- *
- * @author Intel Corporation
- * @date 30-Oct-2001
- *
- * @brief This file contains functions for putting entries on a queue and
- * removing entries from a queue.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * Inlines are compiled as function when this is defined.
- * N.B. Must be placed before #include of "IxQMgr.h"
- */
-#ifndef IXQMGR_H
-# define IXQMGRQACCESS_C
-#else
-# error
-#endif
-
-/*
- * System defined include files.
- */
-
-/*
- * User defined include files.
- */
-#include "IxQMgr.h"
-#include "IxQMgrAqmIf_p.h"
-#include "IxQMgrQAccess_p.h"
-#include "IxQMgrQCfg_p.h"
-#include "IxQMgrDefines_p.h"
-
-/*
- * Global variables and extern definitions
- */
-extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
-
-/*
- * Function definitions.
- */
-void
-ixQMgrQAccessInit (void)
-{
-}
-
-IX_STATUS
-ixQMgrQReadWithChecks (IxQMgrQId qId,
- UINT32 *entry)
-{
- IxQMgrQEntrySizeInWords entrySizeInWords;
- IxQMgrQInlinedReadWriteInfo *infoPtr;
-
- if (NULL == entry)
- {
- return IX_QMGR_PARAMETER_ERROR;
- }
-
- /* Check QId */
- if (!ixQMgrQIsConfigured(qId))
- {
- return IX_QMGR_Q_NOT_CONFIGURED;
- }
-
- /* Get the q entry size in words */
- entrySizeInWords = ixQMgrQEntrySizeInWordsGet (qId);
-
- ixQMgrAqmIfQPop (qId, entrySizeInWords, entry);
-
- /* reset the current read count if the counter wrapped around
- * (unsigned arithmetic)
- */
- infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
- if (infoPtr->qReadCount-- > infoPtr->qSizeInEntries)
- {
- infoPtr->qReadCount = 0;
- }
-
- /* Check if underflow occurred on the read */
- if (ixQMgrAqmIfUnderflowCheck (qId))
- {
- return IX_QMGR_Q_UNDERFLOW;
- }
-
- return IX_SUCCESS;
-}
-
-/* this function reads the remaining of the q entry
- * for queues configured with many words.
- * (the first word of the entry is already read
- * in the inlined function and the entry pointer already
- * incremented
- */
-IX_STATUS
-ixQMgrQReadMWordsMinus1 (IxQMgrQId qId,
- UINT32 *entry)
-{
- IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
- UINT32 entrySize = infoPtr->qEntrySizeInWords;
- volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
-
- while (--entrySize)
- {
- /* read the entry and accumulate the result */
- *(++entry) = IX_OSAL_READ_LONG(++qAccRegAddr);
- }
- /* underflow is available for lower queues only */
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- /* get the queue status */
- UINT32 status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr);
-
- /* check the underflow status */
- if (status & infoPtr->qUflowStatBitMask)
- {
- /* the queue is empty
- * clear the underflow status bit if it was set
- */
- IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr,
- status & ~infoPtr->qUflowStatBitMask);
- return IX_QMGR_Q_UNDERFLOW;
- }
- }
- return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrQWriteWithChecks (IxQMgrQId qId,
- UINT32 *entry)
-{
- IxQMgrQEntrySizeInWords entrySizeInWords;
- IxQMgrQInlinedReadWriteInfo *infoPtr;
-
- if (NULL == entry)
- {
- return IX_QMGR_PARAMETER_ERROR;
- }
-
- /* Check QId */
- if (!ixQMgrQIsConfigured(qId))
- {
- return IX_QMGR_Q_NOT_CONFIGURED;
- }
-
- /* Get the q entry size in words */
- entrySizeInWords = ixQMgrQEntrySizeInWordsGet (qId);
-
- ixQMgrAqmIfQPush (qId, entrySizeInWords, entry);
-
- /* reset the current read count if the counter wrapped around
- * (unsigned arithmetic)
- */
- infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
- if (infoPtr->qWriteCount++ >= infoPtr->qSizeInEntries)
- {
- infoPtr->qWriteCount = infoPtr->qSizeInEntries;
- }
-
- /* Check if overflow occurred on the write*/
- if (ixQMgrAqmIfOverflowCheck (qId))
- {
- return IX_QMGR_Q_OVERFLOW;
- }
-
- return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrQPeek (IxQMgrQId qId,
- unsigned int entryIndex,
- UINT32 *entry)
-{
- unsigned int numEntries;
-
-#ifndef NDEBUG
- if ((NULL == entry) || (entryIndex >= IX_QMGR_Q_SIZE_INVALID))
- {
- return IX_QMGR_PARAMETER_ERROR;
- }
-
- if (!ixQMgrQIsConfigured(qId))
- {
- return IX_QMGR_Q_NOT_CONFIGURED;
- }
-#endif
-
- if (IX_SUCCESS != ixQMgrQNumEntriesGet (qId, &numEntries))
- {
- return IX_FAIL;
- }
-
- if (entryIndex >= numEntries) /* entryIndex starts at 0 */
- {
- return IX_QMGR_ENTRY_INDEX_OUT_OF_BOUNDS;
- }
-
- return ixQMgrAqmIfQPeek (qId, entryIndex, entry);
-}
-
-IX_STATUS
-ixQMgrQPoke (IxQMgrQId qId,
- unsigned entryIndex,
- UINT32 *entry)
-{
- unsigned int numEntries;
-
-#ifndef NDEBUG
- if ((NULL == entry) || (entryIndex > 128))
- {
- return IX_QMGR_PARAMETER_ERROR;
- }
-
- if (!ixQMgrQIsConfigured(qId))
- {
- return IX_QMGR_Q_NOT_CONFIGURED;
- }
-#endif
-
- if (IX_SUCCESS != ixQMgrQNumEntriesGet (qId, &numEntries))
- {
- return IX_FAIL;
- }
-
- if (numEntries < (entryIndex + 1)) /* entryIndex starts at 0 */
- {
- return IX_QMGR_ENTRY_INDEX_OUT_OF_BOUNDS;
- }
-
- return ixQMgrAqmIfQPoke (qId, entryIndex, entry);
-}
-
-IX_STATUS
-ixQMgrQStatusGetWithChecks (IxQMgrQId qId,
- IxQMgrQStatus *qStatus)
-{
- if (NULL == qStatus)
- {
- return IX_QMGR_PARAMETER_ERROR;
- }
-
- if (!ixQMgrQIsConfigured (qId))
- {
- return IX_QMGR_Q_NOT_CONFIGURED;
- }
-
- ixQMgrAqmIfQueStatRead (qId, qStatus);
-
- return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrQNumEntriesGet (IxQMgrQId qId,
- unsigned *numEntriesPtr)
-{
- UINT32 qPtrs;
- UINT32 qStatus;
- unsigned numEntries;
- IxQMgrQInlinedReadWriteInfo *infoPtr;
-
-
-#ifndef NDEBUG
- if (NULL == numEntriesPtr)
- {
- return IX_QMGR_PARAMETER_ERROR;
- }
-
- /* Check QId */
- if (!ixQMgrQIsConfigured(qId))
- {
- return IX_QMGR_Q_NOT_CONFIGURED;
- }
-#endif
-
- /* get fast access data */
- infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
-
- /* get snapshot */
- qPtrs = IX_OSAL_READ_LONG(infoPtr->qConfigRegAddr);
-
- /* Mod subtraction of pointers to get number of words in Q. */
- numEntries = (qPtrs - (qPtrs >> 7)) & 0x7f;
-
- if (numEntries == 0)
- {
- /*
- * Could mean either full or empty queue
- * so look at status
- */
- ixQMgrAqmIfQueStatRead (qId, &qStatus);
-
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- if (qStatus & IX_QMGR_Q_STATUS_E_BIT_MASK)
- {
- /* Empty */
- *numEntriesPtr = 0;
- }
- else if (qStatus & IX_QMGR_Q_STATUS_F_BIT_MASK)
- {
- /* Full */
- *numEntriesPtr = infoPtr->qSizeInEntries;
- }
- else
- {
- /*
- * Queue status and read/write pointers are volatile.
- * The queue state has changed since we took the
- * snapshot of the read and write pointers.
- * Client can retry if they wish
- */
- *numEntriesPtr = 0;
- return IX_QMGR_WARNING;
- }
- }
- else /* It is an upper queue which does not have an empty status bit maintained */
- {
- if (qStatus & IX_QMGR_Q_STATUS_F_BIT_MASK)
- {
- /* The queue is Full at the time of snapshot. */
- *numEntriesPtr = infoPtr->qSizeInEntries;
- }
- else
- {
- /* The queue is either empty, either moving,
- * Client can retry if they wish
- */
- *numEntriesPtr = 0;
- return IX_QMGR_WARNING;
- }
- }
- }
- else
- {
- *numEntriesPtr = (numEntries / infoPtr->qEntrySizeInWords) & (infoPtr->qSizeInEntries - 1);
- }
-
- return IX_SUCCESS;
-}
-
-#if defined(__wince) && defined(NO_INLINE_APIS)
-
-PUBLIC IX_STATUS
-ixQMgrQRead (IxQMgrQId qId,
- UINT32 *entryPtr)
-{
- extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
- IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
- UINT32 entry, entrySize;
-
- /* get a new entry */
- entrySize = infoPtr->qEntrySizeInWords;
- entry = IX_OSAL_READ_LONG(infoPtr->qAccRegAddr);
-
- if (entrySize != IX_QMGR_Q_ENTRY_SIZE1)
- {
- *entryPtr = entry;
- /* process the remaining part of the entry */
- return ixQMgrQReadMWordsMinus1(qId, entryPtr);
- }
-
- /* underflow is available for lower queues only */
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- /* the counter of queue entries is decremented. In happy
- * day scenario there are many entries in the queue
- * and the counter does not reach zero.
- */
- if (infoPtr->qReadCount-- == 0)
- {
- /* There is maybe no entry in the queue
- * qReadCount is now negative, but will be corrected before
- * the function returns.
- */
- UINT32 qPtrs; /* queue internal pointers */
-
- /* when a queue is empty, the hw guarantees to return
- * a null value. If the value is not null, the queue is
- * not empty.
- */
- if (entry == 0)
- {
- /* get the queue status */
- UINT32 status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr);
-
- /* check the underflow status */
- if (status & infoPtr->qUflowStatBitMask)
- {
- /* the queue is empty
- * clear the underflow status bit if it was set
- */
- IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr,
- status & ~infoPtr->qUflowStatBitMask);
- *entryPtr = 0;
- infoPtr->qReadCount = 0;
- return IX_QMGR_Q_UNDERFLOW;
- }
- }
- /* store the result */
- *entryPtr = entry;
-
- /* No underflow occured : someone is filling the queue
- * or the queue contains null entries.
- * The current counter needs to be
- * updated from the current number of entries in the queue
- */
-
- /* get snapshot of queue pointers */
- qPtrs = IX_OSAL_READ_LONG(infoPtr->qConfigRegAddr);
-
- /* Mod subtraction of pointers to get number of words in Q. */
- qPtrs = (qPtrs - (qPtrs >> 7)) & 0x7f;
-
- if (qPtrs == 0)
- {
- /* no entry in the queue */
- infoPtr->qReadCount = 0;
- }
- else
- {
- /* convert the number of words inside the queue
- * to a number of entries
- */
- infoPtr->qReadCount = qPtrs & (infoPtr->qSizeInEntries - 1);
- }
- return IX_SUCCESS;
- }
- }
- *entryPtr = entry;
- return IX_SUCCESS;
-}
-
-PUBLIC IX_STATUS
-ixQMgrQBurstRead (IxQMgrQId qId,
- UINT32 numEntries,
- UINT32 *entries)
-{
- extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
- IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
- UINT32 nullCheckEntry;
-
- if (infoPtr->qEntrySizeInWords == IX_QMGR_Q_ENTRY_SIZE1)
- {
- volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
-
- /* the code is optimized to take care of data dependencies:
- * Durig a read, there are a few cycles needed to get the
- * read complete. During these cycles, it is poossible to
- * do some CPU, e.g. increment pointers and decrement
- * counters.
- */
-
- /* fetch a queue entry */
- nullCheckEntry = IX_OSAL_READ_LONG(infoPtr->qAccRegAddr);
-
- /* iterate the specified number of queue entries */
- while (--numEntries)
- {
- /* check the result of the previous read */
- if (nullCheckEntry == 0)
- {
- /* if we read a NULL entry, stop. We have underflowed */
- break;
- }
- else
- {
- /* write the entry */
- *entries = nullCheckEntry;
- /* fetch next entry */
- nullCheckEntry = IX_OSAL_READ_LONG(qAccRegAddr);
- /* increment the write address */
- entries++;
- }
- }
- /* write the pre-fetched entry */
- *entries = nullCheckEntry;
- }
- else
- {
- IxQMgrQEntrySizeInWords entrySizeInWords = infoPtr->qEntrySizeInWords;
- /* read the specified number of queue entries */
- nullCheckEntry = 0;
- while (numEntries--)
- {
- int i;
-
- for (i = 0; i < entrySizeInWords; i++)
- {
- *entries = IX_OSAL_READ_LONG(infoPtr->qAccRegAddr + i);
- nullCheckEntry |= *entries++;
- }
-
- /* if we read a NULL entry, stop. We have underflowed */
- if (nullCheckEntry == 0)
- {
- break;
- }
- nullCheckEntry = 0;
- }
- }
-
- /* reset the current read count : next access to the read function
- * will force a underflow status check
- */
- infoPtr->qWriteCount = 0;
-
- /* Check if underflow occurred on the read */
- if (nullCheckEntry == 0 && qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- /* get the queue status */
- UINT32 status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr);
-
- if (status & infoPtr->qUflowStatBitMask)
- {
- /* clear the underflow status bit if it was set */
- IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr,
- status & ~infoPtr->qUflowStatBitMask);
- return IX_QMGR_Q_UNDERFLOW;
- }
- }
-
- return IX_SUCCESS;
-}
-
-PUBLIC IX_STATUS
-ixQMgrQWrite (IxQMgrQId qId,
- UINT32 *entry)
-{
- extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
- IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
- UINT32 entrySize;
-
- /* write the entry */
- IX_OSAL_WRITE_LONG(infoPtr->qAccRegAddr, *entry);
- entrySize = infoPtr->qEntrySizeInWords;
-
- if (entrySize != IX_QMGR_Q_ENTRY_SIZE1)
- {
- /* process the remaining part of the entry */
- volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
- while (--entrySize)
- {
- ++entry;
- IX_OSAL_WRITE_LONG(++qAccRegAddr, *entry);
- }
- entrySize = infoPtr->qEntrySizeInWords;
- }
-
- /* overflow is available for lower queues only */
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- UINT32 qSize = infoPtr->qSizeInEntries;
- /* increment the current number of entries in the queue
- * and check for overflow
- */
- if (infoPtr->qWriteCount++ == qSize)
- {
- /* the queue may have overflow */
- UINT32 qPtrs; /* queue internal pointers */
-
- /* get the queue status */
- UINT32 status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr);
-
- /* read the status twice because the status may
- * not be immediately ready after the write operation
- */
- if ((status & infoPtr->qOflowStatBitMask) ||
- ((status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr))
- & infoPtr->qOflowStatBitMask))
- {
- /* the queue is full, clear the overflow status
- * bit if it was set
- */
- IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr,
- status & ~infoPtr->qOflowStatBitMask);
- infoPtr->qWriteCount = infoPtr->qSizeInEntries;
- return IX_QMGR_Q_OVERFLOW;
- }
- /* No overflow occured : someone is draining the queue
- * and the current counter needs to be
- * updated from the current number of entries in the queue
- */
-
- /* get q pointer snapshot */
- qPtrs = IX_OSAL_READ_LONG(infoPtr->qConfigRegAddr);
-
- /* Mod subtraction of pointers to get number of words in Q. */
- qPtrs = (qPtrs - (qPtrs >> 7)) & 0x7f;
-
- if (qPtrs == 0)
- {
- /* the queue may be full at the time of the
- * snapshot. Next access will check
- * the overflow status again.
- */
- infoPtr->qWriteCount = qSize;
- }
- else
- {
- /* convert the number of words to a number of entries */
- if (entrySize == IX_QMGR_Q_ENTRY_SIZE1)
- {
- infoPtr->qWriteCount = qPtrs & (qSize - 1);
- }
- else
- {
- infoPtr->qWriteCount = (qPtrs / entrySize) & (qSize - 1);
- }
- }
- }
- }
- return IX_SUCCESS;
-}
-
-PUBLIC IX_STATUS
-ixQMgrQBurstWrite (IxQMgrQId qId,
- unsigned numEntries,
- UINT32 *entries)
-{
- extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
- IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
- UINT32 status;
-
- /* update the current write count */
- infoPtr->qWriteCount += numEntries;
-
- if (infoPtr->qEntrySizeInWords == IX_QMGR_Q_ENTRY_SIZE1)
- {
- volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
- while (numEntries--)
- {
- IX_OSAL_WRITE_LONG(qAccRegAddr, *entries);
- entries++;
- }
- }
- else
- {
- IxQMgrQEntrySizeInWords entrySizeInWords = infoPtr->qEntrySizeInWords;
- int i;
-
- /* write each queue entry */
- while (numEntries--)
- {
- /* write the queueEntrySize number of words for each entry */
- for (i = 0; i < entrySizeInWords; i++)
- {
- IX_OSAL_WRITE_LONG((infoPtr->qAccRegAddr + i), *entries);
- entries++;
- }
- }
- }
-
- /* check if the write count overflows */
- if (infoPtr->qWriteCount > infoPtr->qSizeInEntries)
- {
- /* reset the current write count */
- infoPtr->qWriteCount = infoPtr->qSizeInEntries;
- }
-
- /* Check if overflow occurred on the write operation */
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- /* get the queue status */
- status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr);
-
- /* read the status twice because the status may
- * not be ready at the time of the write
- */
- if ((status & infoPtr->qOflowStatBitMask) ||
- ((status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr))
- & infoPtr->qOflowStatBitMask))
- {
- /* clear the underflow status bit if it was set */
- IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr,
- status & ~infoPtr->qOflowStatBitMask);
- return IX_QMGR_Q_OVERFLOW;
- }
- }
-
- return IX_SUCCESS;
-}
-
-PUBLIC IX_STATUS
-ixQMgrQStatusGet (IxQMgrQId qId,
- IxQMgrQStatus *qStatus)
-{
- /* read the status of a queue in the range 0-31 */
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- extern UINT32 ixQMgrAqmIfQueLowStatRegAddr[];
- extern UINT32 ixQMgrAqmIfQueLowStatBitsOffset[];
- extern UINT32 ixQMgrAqmIfQueLowStatBitsMask;
- extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
- IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
- volatile UINT32 *lowStatRegAddr = (UINT32*)ixQMgrAqmIfQueLowStatRegAddr[qId];
- volatile UINT32 *qUOStatRegAddr = infoPtr->qUOStatRegAddr;
-
- UINT32 lowStatBitsOffset = ixQMgrAqmIfQueLowStatBitsOffset[qId];
- UINT32 lowStatBitsMask = ixQMgrAqmIfQueLowStatBitsMask;
- UINT32 underflowBitMask = infoPtr->qUflowStatBitMask;
- UINT32 overflowBitMask = infoPtr->qOflowStatBitMask;
-
- /* read the status register for this queue */
- *qStatus = IX_OSAL_READ_LONG(lowStatRegAddr);
- /* mask out the status bits relevant only to this queue */
- *qStatus = (*qStatus >> lowStatBitsOffset) & lowStatBitsMask;
-
- /* Check if the queue has overflowed */
- if (IX_OSAL_READ_LONG(qUOStatRegAddr) & overflowBitMask)
- {
- /* clear the overflow status bit if it was set */
- IX_OSAL_WRITE_LONG(qUOStatRegAddr,
- (IX_OSAL_READ_LONG(qUOStatRegAddr) &
- ~overflowBitMask));
- *qStatus |= IX_QMGR_Q_STATUS_OF_BIT_MASK;
- }
-
- /* Check if the queue has underflowed */
- if (IX_OSAL_READ_LONG(qUOStatRegAddr) & underflowBitMask)
- {
- /* clear the underflow status bit if it was set */
- IX_OSAL_WRITE_LONG(qUOStatRegAddr,
- (IX_OSAL_READ_LONG(qUOStatRegAddr) &
- ~underflowBitMask));
- *qStatus |= IX_QMGR_Q_STATUS_UF_BIT_MASK;
- }
- }
- else /* read status of a queue in the range 32-63 */
- {
- extern UINT32 ixQMgrAqmIfQueUppStat0RegAddr;
- extern UINT32 ixQMgrAqmIfQueUppStat1RegAddr;
- extern UINT32 ixQMgrAqmIfQueUppStat0BitMask[];
- extern UINT32 ixQMgrAqmIfQueUppStat1BitMask[];
-
- volatile UINT32 *qNearEmptyStatRegAddr = (UINT32*)ixQMgrAqmIfQueUppStat0RegAddr;
- volatile UINT32 *qFullStatRegAddr = (UINT32*)ixQMgrAqmIfQueUppStat1RegAddr;
- int maskIndex = qId - IX_QMGR_MIN_QUEUPP_QID;
- UINT32 qNearEmptyStatBitMask = ixQMgrAqmIfQueUppStat0BitMask[maskIndex];
- UINT32 qFullStatBitMask = ixQMgrAqmIfQueUppStat1BitMask[maskIndex];
-
- /* Reset the status bits */
- *qStatus = 0;
-
- /* Check if the queue is nearly empty */
- if (IX_OSAL_READ_LONG(qNearEmptyStatRegAddr) & qNearEmptyStatBitMask)
- {
- *qStatus |= IX_QMGR_Q_STATUS_NE_BIT_MASK;
- }
-
- /* Check if the queue is full */
- if (IX_OSAL_READ_LONG(qFullStatRegAddr) & qFullStatBitMask)
- {
- *qStatus |= IX_QMGR_Q_STATUS_F_BIT_MASK;
- }
- }
- return IX_SUCCESS;
-}
-#endif /* def NO_INLINE_APIS */
+++ /dev/null
-/**
- * @file QMgrQCfg.c
- *
- * @author Intel Corporation
- * @date 30-Oct-2001
- *
- * @brief This modules provides an interface for setting up the static
- * configuration of AQM queues.This file contains the following
- * functions:
- *
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-/*
- * System defined include files.
- */
-
-/*
- * User defined include files.
- */
-#include "IxOsal.h"
-#include "IxQMgr.h"
-#include "IxQMgrAqmIf_p.h"
-#include "IxQMgrQCfg_p.h"
-#include "IxQMgrDefines_p.h"
-
-/*
- * #defines and macros used in this file.
- */
-
-#define IX_QMGR_MIN_ENTRY_SIZE_IN_WORDS 16
-
-/* Total size of SRAM */
-#define IX_QMGR_AQM_SRAM_SIZE_IN_BYTES 0x4000
-
-/*
- * Check that qId is a valid queue identifier. This is provided to
- * make the code easier to read.
- */
-#define IX_QMGR_QID_IS_VALID(qId) \
-(((qId) >= (IX_QMGR_MIN_QID)) && ((qId) <= (IX_QMGR_MAX_QID)))
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/*
- * This struct describes an AQM queue.
- * N.b. bufferSizeInWords and qEntrySizeInWords are stored in the queue
- * as these are requested by Access in the data path. sizeInEntries is
- * not required by the data path so it can be calculated dynamically.
- *
- */
-typedef struct
-{
- char qName[IX_QMGR_MAX_QNAME_LEN+1]; /* Textual description of a queue*/
- IxQMgrQSizeInWords qSizeInWords; /* The number of words in the queue */
- IxQMgrQEntrySizeInWords qEntrySizeInWords; /* Number of words per queue entry*/
- BOOL isConfigured; /* This flag is TRUE if the queue has
- * been configured
- */
-} IxQMgrCfgQ;
-
-/*
- * Variable declarations global to this file. Externs are followed by
- * statics.
- */
-
-extern UINT32 * ixQMgrAqmIfQueAccRegAddr[];
-
-/* Store data required to inline read and write access
- */
-IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[IX_QMGR_MAX_NUM_QUEUES];
-
-static IxQMgrCfgQ cfgQueueInfo[IX_QMGR_MAX_NUM_QUEUES];
-
-/* This pointer holds the starting address of AQM SRAM not used by
- * the AQM queues.
- */
-static UINT32 freeSramAddress=0;
-
-/* 4 words of zeroed memory for inline access */
-static UINT32 zeroedPlaceHolder[4] = { 0, 0, 0, 0 };
-
-static BOOL cfgInitialized = FALSE;
-
-static IxOsalMutex ixQMgrQCfgMutex;
-
-/*
- * Statistics
- */
-static IxQMgrQCfgStats stats;
-
-/*
- * Function declarations
- */
-PRIVATE BOOL
-watermarkLevelIsOk (IxQMgrQId qId, IxQMgrWMLevel level);
-
-PRIVATE BOOL
-qSizeInWordsIsOk (IxQMgrQSizeInWords qSize);
-
-PRIVATE BOOL
-qEntrySizeInWordsIsOk (IxQMgrQEntrySizeInWords entrySize);
-
-/*
- * Function definitions.
- */
-void
-ixQMgrQCfgInit (void)
-{
- int loopIndex;
-
- for (loopIndex=0; loopIndex < IX_QMGR_MAX_NUM_QUEUES;loopIndex++)
- {
- /* info for code inlining */
- ixQMgrAqmIfQueAccRegAddr[loopIndex] = zeroedPlaceHolder;
-
- /* info for code inlining */
- ixQMgrQInlinedReadWriteInfo[loopIndex].qReadCount = 0;
- ixQMgrQInlinedReadWriteInfo[loopIndex].qWriteCount = 0;
- ixQMgrQInlinedReadWriteInfo[loopIndex].qAccRegAddr = zeroedPlaceHolder;
- ixQMgrQInlinedReadWriteInfo[loopIndex].qUOStatRegAddr = zeroedPlaceHolder;
- ixQMgrQInlinedReadWriteInfo[loopIndex].qUflowStatBitMask = 0;
- ixQMgrQInlinedReadWriteInfo[loopIndex].qOflowStatBitMask = 0;
- ixQMgrQInlinedReadWriteInfo[loopIndex].qEntrySizeInWords = 0;
- ixQMgrQInlinedReadWriteInfo[loopIndex].qSizeInEntries = 0;
- ixQMgrQInlinedReadWriteInfo[loopIndex].qConfigRegAddr = zeroedPlaceHolder;
- }
-
- /* Initialise the AqmIf component */
- ixQMgrAqmIfInit ();
-
- /* Reset all queues to have queue name = NULL, entry size = 0 and
- * isConfigured = false
- */
- for (loopIndex=0; loopIndex < IX_QMGR_MAX_NUM_QUEUES;loopIndex++)
- {
- strcpy (cfgQueueInfo[loopIndex].qName, "");
- cfgQueueInfo[loopIndex].qSizeInWords = 0;
- cfgQueueInfo[loopIndex].qEntrySizeInWords = 0;
- cfgQueueInfo[loopIndex].isConfigured = FALSE;
-
- /* Statistics */
- stats.qStats[loopIndex].isConfigured = FALSE;
- stats.qStats[loopIndex].qName = cfgQueueInfo[loopIndex].qName;
- }
-
- /* Statistics */
- stats.wmSetCnt = 0;
-
- ixQMgrAqmIfSramBaseAddressGet (&freeSramAddress);
-
- ixOsalMutexInit(&ixQMgrQCfgMutex);
-
- cfgInitialized = TRUE;
-}
-
-void
-ixQMgrQCfgUninit (void)
-{
- cfgInitialized = FALSE;
-
- /* Uninitialise the AqmIf component */
- ixQMgrAqmIfUninit ();
-}
-
-IX_STATUS
-ixQMgrQConfig (char *qName,
- IxQMgrQId qId,
- IxQMgrQSizeInWords qSizeInWords,
- IxQMgrQEntrySizeInWords qEntrySizeInWords)
-{
- UINT32 aqmLocalBaseAddress;
-
- if (!cfgInitialized)
- {
- return IX_FAIL;
- }
-
- if (!IX_QMGR_QID_IS_VALID(qId))
- {
- return IX_QMGR_INVALID_Q_ID;
- }
-
- else if (NULL == qName)
- {
- return IX_QMGR_PARAMETER_ERROR;
- }
-
- else if (strlen (qName) > IX_QMGR_MAX_QNAME_LEN)
- {
- return IX_QMGR_PARAMETER_ERROR;
- }
-
- else if (!qSizeInWordsIsOk (qSizeInWords))
- {
- return IX_QMGR_INVALID_QSIZE;
- }
-
- else if (!qEntrySizeInWordsIsOk (qEntrySizeInWords))
- {
- return IX_QMGR_INVALID_Q_ENTRY_SIZE;
- }
-
- else if (cfgQueueInfo[qId].isConfigured)
- {
- return IX_QMGR_Q_ALREADY_CONFIGURED;
- }
-
- ixOsalMutexLock(&ixQMgrQCfgMutex, IX_OSAL_WAIT_FOREVER);
-
- /* Write the config register */
- ixQMgrAqmIfQueCfgWrite (qId,
- qSizeInWords,
- qEntrySizeInWords,
- freeSramAddress);
-
-
- strcpy (cfgQueueInfo[qId].qName, qName);
- cfgQueueInfo[qId].qSizeInWords = qSizeInWords;
- cfgQueueInfo[qId].qEntrySizeInWords = qEntrySizeInWords;
-
- /* store pre-computed information in the same cache line
- * to facilitate inlining of QRead and QWrite functions
- * in IxQMgr.h
- */
- ixQMgrQInlinedReadWriteInfo[qId].qReadCount = 0;
- ixQMgrQInlinedReadWriteInfo[qId].qWriteCount = 0;
- ixQMgrQInlinedReadWriteInfo[qId].qEntrySizeInWords = qEntrySizeInWords;
- ixQMgrQInlinedReadWriteInfo[qId].qSizeInEntries =
- (UINT32)qSizeInWords / (UINT32)qEntrySizeInWords;
-
- /* Calculate the new freeSramAddress from the size of the queue
- * currently being configured.
- */
- freeSramAddress += (qSizeInWords * IX_QMGR_NUM_BYTES_PER_WORD);
-
- /* Get the virtual SRAM address */
- ixQMgrAqmIfBaseAddressGet (&aqmLocalBaseAddress);
-
- IX_OSAL_ASSERT((freeSramAddress - (aqmLocalBaseAddress + (IX_QMGR_QUEBUFFER_SPACE_OFFSET))) <=
- IX_QMGR_QUE_BUFFER_SPACE_SIZE);
-
- /* The queue is now configured */
- cfgQueueInfo[qId].isConfigured = TRUE;
-
- ixOsalMutexUnlock(&ixQMgrQCfgMutex);
-
-#ifndef NDEBUG
- /* Update statistics */
- stats.qStats[qId].isConfigured = TRUE;
- stats.qStats[qId].qName = cfgQueueInfo[qId].qName;
-#endif
- return IX_SUCCESS;
-}
-
-IxQMgrQSizeInWords
-ixQMgrQSizeInWordsGet (IxQMgrQId qId)
-{
- /* No parameter checking as this is used on the data path */
- return (cfgQueueInfo[qId].qSizeInWords);
-}
-
-IX_STATUS
-ixQMgrQSizeInEntriesGet (IxQMgrQId qId,
- unsigned *qSizeInEntries)
-{
- if (!ixQMgrQIsConfigured(qId))
- {
- return IX_QMGR_Q_NOT_CONFIGURED;
- }
-
- if(NULL == qSizeInEntries)
- {
- return IX_QMGR_PARAMETER_ERROR;
- }
-
- *qSizeInEntries = (UINT32)(cfgQueueInfo[qId].qSizeInWords) /
- (UINT32)cfgQueueInfo[qId].qEntrySizeInWords;
-
- return IX_SUCCESS;
-}
-
-IxQMgrQEntrySizeInWords
-ixQMgrQEntrySizeInWordsGet (IxQMgrQId qId)
-{
- /* No parameter checking as this is used on the data path */
- return (cfgQueueInfo[qId].qEntrySizeInWords);
-}
-
-IX_STATUS
-ixQMgrWatermarkSet (IxQMgrQId qId,
- IxQMgrWMLevel ne,
- IxQMgrWMLevel nf)
-{
- IxQMgrQStatus qStatusOnEntry;/* The queue status on entry/exit */
- IxQMgrQStatus qStatusOnExit; /* to this function */
-
- if (!ixQMgrQIsConfigured(qId))
- {
- return IX_QMGR_Q_NOT_CONFIGURED;
- }
-
- if (!watermarkLevelIsOk (qId, ne))
- {
- return IX_QMGR_INVALID_Q_WM;
- }
-
- if (!watermarkLevelIsOk (qId, nf))
- {
- return IX_QMGR_INVALID_Q_WM;
- }
-
- /* Get the current queue status */
- ixQMgrAqmIfQueStatRead (qId, &qStatusOnEntry);
-
-#ifndef NDEBUG
- /* Update statistics */
- stats.wmSetCnt++;
-#endif
-
- ixQMgrAqmIfWatermarkSet (qId,
- ne,
- nf);
-
- /* Get the current queue status */
- ixQMgrAqmIfQueStatRead (qId, &qStatusOnExit);
-
- /* If the status has changed return a warning */
- if (qStatusOnEntry != qStatusOnExit)
- {
- return IX_QMGR_WARNING;
- }
-
- return IX_SUCCESS;
-}
-
-IX_STATUS
-ixQMgrAvailableSramAddressGet (UINT32 *address,
- unsigned *sizeOfFreeRam)
-{
- UINT32 aqmLocalBaseAddress;
-
- if ((NULL == address)||(NULL == sizeOfFreeRam))
- {
- return IX_QMGR_PARAMETER_ERROR;
- }
- if (!cfgInitialized)
- {
- return IX_FAIL;
- }
-
- *address = freeSramAddress;
-
- /* Get the virtual SRAM address */
- ixQMgrAqmIfBaseAddressGet (&aqmLocalBaseAddress);
-
- /*
- * Calculate the size in bytes of free sram
- * i.e. current free SRAM virtual pointer from
- * (base + total size)
- */
- *sizeOfFreeRam =
- (aqmLocalBaseAddress +
- IX_QMGR_AQM_SRAM_SIZE_IN_BYTES) -
- freeSramAddress;
-
- if (0 == *sizeOfFreeRam)
- {
- return IX_QMGR_NO_AVAILABLE_SRAM;
- }
-
- return IX_SUCCESS;
-}
-
-BOOL
-ixQMgrQIsConfigured (IxQMgrQId qId)
-{
- if (!IX_QMGR_QID_IS_VALID(qId))
- {
- return FALSE;
- }
-
- return cfgQueueInfo[qId].isConfigured;
-}
-
-IxQMgrQCfgStats*
-ixQMgrQCfgStatsGet (void)
-{
- return &stats;
-}
-
-IxQMgrQCfgStats*
-ixQMgrQCfgQStatsGet (IxQMgrQId qId)
-{
- unsigned int ne;
- unsigned int nf;
- UINT32 baseAddress;
- UINT32 readPtr;
- UINT32 writePtr;
-
- stats.qStats[qId].qSizeInWords = cfgQueueInfo[qId].qSizeInWords;
- stats.qStats[qId].qEntrySizeInWords = cfgQueueInfo[qId].qEntrySizeInWords;
-
- if (IX_SUCCESS != ixQMgrQNumEntriesGet (qId, &stats.qStats[qId].numEntries))
- {
- if (IX_QMGR_WARNING != ixQMgrQNumEntriesGet (qId, &stats.qStats[qId].numEntries))
- {
- IX_QMGR_LOG_WARNING1("Failed to get the number of entries in queue.... %d\n", qId);
- }
- }
-
- ixQMgrAqmIfQueCfgRead (qId,
- stats.qStats[qId].numEntries,
- &baseAddress,
- &ne,
- &nf,
- &readPtr,
- &writePtr);
-
- stats.qStats[qId].baseAddress = baseAddress;
- stats.qStats[qId].ne = ne;
- stats.qStats[qId].nf = nf;
- stats.qStats[qId].readPtr = readPtr;
- stats.qStats[qId].writePtr = writePtr;
-
- return &stats;
-}
-
-/*
- * Static function definitions
- */
-
-PRIVATE BOOL
-watermarkLevelIsOk (IxQMgrQId qId, IxQMgrWMLevel level)
-{
- unsigned qSizeInEntries;
-
- switch (level)
- {
- case IX_QMGR_Q_WM_LEVEL0:
- case IX_QMGR_Q_WM_LEVEL1:
- case IX_QMGR_Q_WM_LEVEL2:
- case IX_QMGR_Q_WM_LEVEL4:
- case IX_QMGR_Q_WM_LEVEL8:
- case IX_QMGR_Q_WM_LEVEL16:
- case IX_QMGR_Q_WM_LEVEL32:
- case IX_QMGR_Q_WM_LEVEL64:
- break;
- default:
- return FALSE;
- }
-
- /* Check watermark is not bigger than the qSizeInEntries */
- ixQMgrQSizeInEntriesGet(qId, &qSizeInEntries);
-
- if ((unsigned)level > qSizeInEntries)
- {
- return FALSE;
- }
-
- return TRUE;
-}
-
-PRIVATE BOOL
-qSizeInWordsIsOk (IxQMgrQSizeInWords qSize)
-{
- BOOL status;
-
- switch (qSize)
- {
- case IX_QMGR_Q_SIZE16:
- case IX_QMGR_Q_SIZE32:
- case IX_QMGR_Q_SIZE64:
- case IX_QMGR_Q_SIZE128:
- status = TRUE;
- break;
- default:
- status = FALSE;
- break;
- }
-
- return status;
-}
-
-PRIVATE BOOL
-qEntrySizeInWordsIsOk (IxQMgrQEntrySizeInWords entrySize)
-{
- BOOL status;
-
- switch (entrySize)
- {
- case IX_QMGR_Q_ENTRY_SIZE1:
- case IX_QMGR_Q_ENTRY_SIZE2:
- case IX_QMGR_Q_ENTRY_SIZE4:
- status = TRUE;
- break;
- default:
- status = FALSE;
- break;
- }
-
- return status;
-}
+++ /dev/null
-/**
- * @file IxAssert.h
- *
- * @date 21-MAR-2002 (replaced by OSAL)
- *
- * @brief This file contains assert and ensure macros used by the IXP400 software
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxAssert IXP400 Assertion Macros (IxAssert) API
- *
- * @brief Assertion support
- *
- * @{
- */
-
-#ifndef IXASSERT_H
-
-#ifndef __doxygen_HIDE
-#define IXASSERT_H
-#endif /* __doxygen_HIDE */
-
-#include "IxOsalBackward.h"
-
-#endif /* IXASSERT_H */
-
-/**
- * @} addtogroup IxAssert
- */
-
-
-
+++ /dev/null
-/**
- * @file IxAtmSch.h
- *
- * @date 23-NOV-2001
- *
- * @brief Header file for the IXP400 ATM Traffic Shaper
- *
- * This component demonstrates an ATM Traffic Shaper implementation. It
- * will perform shaping on upto 12 ports and total of 44 VCs accross all ports,
- * 32 are intended for AAL0/5 and 12 for OAM (1 per port).
- * The supported traffic types are;1 rt-VBR VC where PCR = SCR.
- * (Effectively CBR) and Up-to 44 VBR VCs.
- *
- * This component models the ATM ports and VCs and is capable of producing
- * a schedule of ATM cells per port which can be supplied to IxAtmdAcc
- * for execution on the data path.
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- *
- * @sa IxAtmm.h
- *
- */
-
-/**
- * @defgroup IxAtmSch IXP400 ATM Transmit Scheduler (IxAtmSch) API
- *
- * @brief IXP400 ATM scheduler component Public API
- *
- * @{
- */
-
-#ifndef IXATMSCH_H
-#define IXATMSCH_H
-
-#include "IxOsalTypes.h"
-#include "IxAtmTypes.h"
-
-/*
- * #defines and macros used in this file.
- */
-
-/* Return codes */
-
-/**
- * @ingroup IxAtmSch
- *
- * @def IX_ATMSCH_RET_NOT_ADMITTED
- * @brief Indicates that CAC function has rejected VC registration due
- * to insufficient line capacity.
-*/
-#define IX_ATMSCH_RET_NOT_ADMITTED 2
-
-/**
- * @ingroup IxAtmSch
- *
- * @def IX_ATMSCH_RET_QUEUE_FULL
- * @brief Indicates that the VC queue is full, no more demand can be
- * queued at this time.
- */
-#define IX_ATMSCH_RET_QUEUE_FULL 3
-
-/**
- * @ingroup IxAtmSch
- *
- * @def IX_ATMSCH_RET_QUEUE_EMPTY
- * @brief Indicates that all VC queues on this port are empty and
- * therefore there are no cells to be scheduled at this time.
- */
-#define IX_ATMSCH_RET_QUEUE_EMPTY 4
-
-/*
- * Function declarations
- */
-
-/**
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchInit(void)
- *
- * @brief This function is used to initialize the ixAtmSch component. It
- * should be called before any other IxAtmSch API function.
- *
- * @param None
- *
- * @return
- * - <b>IX_SUCCESS :</b> indicates that
- * -# The ATM scheduler component has been successfully initialized.
- * -# The scheduler is ready to accept Port modelling requests.
- * - <b>IX_FAIL :</b> Some internal error has prevented the scheduler component
- * from initialising.
- */
-PUBLIC IX_STATUS
-ixAtmSchInit(void);
-
-/**
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchPortModelInitialize( IxAtmLogicalPort port,
- unsigned int portRate,
- unsigned int minCellsToSchedule)
- *
- * @brief This function shall be called first to initialize an ATM port before
- * any other ixAtmSch API calls may be made for that port.
- *
- * @param port @ref IxAtmLogicalPort [in] - The specific port to initialize. Valid
- * values range from 0 to IX_UTOPIA_MAX_PORTS - 1, representing a
- * maximum of IX_UTOPIA_MAX_PORTS possible ports.
- *
- * @param portRate unsigned int [in] - Value indicating the upstream capacity
- * of the indicated port. The value should be supplied in
- * units of ATM (53 bytes) cells per second.
- * A port rate of 800Kbits/s is the equivalent
- * of 1886 cells per second
- *
- * @param minCellsToSchedule unsigned int [in] - This parameter specifies the minimum
- * number of cells which the scheduler will put in a schedule
- * table for this port. This value sets the worst case CDVT for VCs
- * on this port i.e. CDVT = 1*minCellsToSchedule/portRate.
- * @return
- * - <b>IX_SUCCESS :</b> indicates that
- * -# The ATM scheduler has been successfully initialized.
- * -# The requested port model has been established.
- * -# The scheduler is ready to accept VC modelling requests
- * on the ATM port.
- * - <b>IX_FAIL :</b> indicates the requested port could not be
- * initialized. */
-PUBLIC IX_STATUS
-ixAtmSchPortModelInitialize( IxAtmLogicalPort port,
- unsigned int portRate,
- unsigned int minCellsToSchedule);
-
-/**
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchPortRateModify( IxAtmLogicalPort port,
- unsigned int portRate)
- *
- * @brief This function is called to modify the portRate on a
- * previously initialized port, typically in the event that
- * the line condition of the port changes.
- *
- * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port which is to be
- * modified.
- *
- * @param portRate unsigned int [in] - Value indicating the new upstream
- * capacity for this port in cells/second.
- * A port rate of 800Kbits/s is the equivalent
- * of 1886 cells per second
- *
- * @return
- * - <b>IX_SUCCESS :</b> The port rate has been successfully modified.<br>
- * - <b>IX_FAIL :</b> The port rate could not be modified, either
- * because the input data was invalid, or the new port rate is
- * insufficient to support established ATM VC contracts on this
- * port.
- *
- * @warning The IxAtmSch component will validate the supplied port
- * rate is sufficient to support all established VC
- * contracts on the port. If the new port rate is
- * insufficient to support all established contracts then
- * the request to modify the port rate will be rejected.
- * In this event, the user is expected to remove
- * established contracts using the ixAtmSchVcModelRemove
- * interface and then retry this interface.
- *
- * @sa ixAtmSchVcModelRemove() */
-PUBLIC IX_STATUS
-ixAtmSchPortRateModify( IxAtmLogicalPort port,
- unsigned int portRate);
-
-
-/**
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchVcModelSetup( IxAtmLogicalPort port,
- IxAtmTrafficDescriptor *trafficDesc,
- IxAtmSchedulerVcId *vcId)
- *
- * @brief A client calls this interface to set up an upstream
- * (transmitting) virtual connection model (VC) on the
- * specified ATM port. This function also provides the
- * virtual * connection admission control (CAC) service to the
- * client.
- *
- * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the upstream
- * VC is to be established.
- *
- * @param *trafficDesc @ref IxAtmTrafficDescriptor [in] - Pointer to a structure
- * describing the requested traffic contract of the VC to be
- * established. This structure contains the typical ATM
- * traffic descriptor values (e.g. PCR, SCR, MBS, CDVT, etc.)
- * defined by the ATM standard.
- *
- * @param *vcId @ref IxAtmSchedulerVcId [out] - This value will be filled with the
- * port-unique identifier for this virtual connection. A
- * valid identification is a non-negative number.
- *
- * @return
- * - <b>IX_SUCCESS :</b> The VC has been successfully established on
- * this port. The client may begin to submit demand on this VC.
- * - <b>IX_ATMSCH_RET_NOT_ADMITTED :</b> The VC cannot be established
- * on this port because there is insufficient upstream capacity
- * available to support the requested traffic contract descriptor
- * - <b>IX_FAIL :</b>Input data are invalid. VC has not been
- * established.
- */
-PUBLIC IX_STATUS
-ixAtmSchVcModelSetup( IxAtmLogicalPort port,
- IxAtmTrafficDescriptor *trafficDesc,
- IxAtmSchedulerVcId *vcId);
-
-/**
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchVcConnIdSet( IxAtmLogicalPort port,
- IxAtmSchedulerVcId vcId,
- IxAtmConnId vcUserConnId)
- *
- * @brief A client calls this interface to set the vcUserConnId for a VC on
- * the specified ATM port. This vcUserConnId will default to
- * IX_ATM_IDLE_CELLS_CONNID if this function is not called for a VC.
- * Hence if the client does not call this function for a VC then only idle
- * cells will be scheduled for this VC.
- *
- * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the upstream
- * VC is has been established.
- *
- * @param vcId @ref IxAtmSchedulerVcId [in] - This is the unique identifier for this virtual
- * connection. A valid identification is a non-negative number and is
- * all ports.
- *
- * @param vcUserConnId @ref IxAtmConnId [in] - The connId is used to refer to a VC in schedule
- * table entries. It is treated as the Id by which the scheduler client
- * knows the VC. It is used in any communicatations from the Scheduler
- * to the scheduler user e.g. schedule table entries.
- *
- * @return
- * - <b>IX_SUCCESS :</b> The id has successfully been set.
- * - <b>IX_FAIL :</b>Input data are invalid. connId id is not established.
- */
-PUBLIC IX_STATUS
-ixAtmSchVcConnIdSet( IxAtmLogicalPort port,
- IxAtmSchedulerVcId vcId,
- IxAtmConnId vcUserConnId);
-
-/**
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchVcModelRemove( IxAtmLogicalPort port,
- IxAtmSchedulerVcId vcId)
- *
- * @brief Interface called by the client to remove a previously
- * established VC on a particular port.
- *
- * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be
- * removed is established.
- *
- * @param vcId @ref IxAtmSchedulerVcId [in] - Identifies the VC to be removed. This is the
- * value returned by the @ref ixAtmSchVcModelSetup call which
- * established the relevant VC.
- *
- * @return
- * - <b>IX_SUCCESS :</b> The VC has been successfully removed from
- * this port. It is no longer modelled on this port.
- * - <b>IX_FAIL :</b>Input data are invalid. The VC is still being modeled
- * by the traffic shaper.
- *
- * @sa ixAtmSchVcModelSetup()
- */
-PUBLIC IX_STATUS
-ixAtmSchVcModelRemove( IxAtmLogicalPort port,
- IxAtmSchedulerVcId vcId);
-
-/**
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchVcQueueUpdate( IxAtmLogicalPort port,
- IxAtmSchedulerVcId vcId,
- unsigned int numberOfCells)
- *
- * @brief The client calls this function to notify IxAtmSch that the
- * user of a VC has submitted cells for transmission.
- *
- * This information is stored, aggregated from a number of calls to
- * ixAtmSchVcQueueUpdate and eventually used in the call to
- * ixAtmSchTableUpdate.
- *
- * Normally IxAtmSch will update the VC queue by adding the number of
- * cells to the current queue length. However, if IxAtmSch
- * determines that the user has over-submitted for the VC and
- * exceeded its transmission quota the queue request can be rejected.
- * The user should resubmit the request later when the queue has been
- * depleted.
- *
- * This implementation of ixAtmSchVcQueueUpdate uses no operating
- * system or external facilities, either directly or indirectly.
- * This allows clients to call this function form within an interrupt handler.
- *
- * This interface is structurally compatible with the
- * IxAtmdAccSchQueueUpdate callback type definition required for
- * IXP400 ATM scheduler interoperability.
- *
- * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be
- * updated is established.
- *
- * @param vcId @ref IxAtmSchedulerVcId [in] - Identifies the VC to be updated. This is the
- * value returned by the @ref ixAtmSchVcModelSetup call which
- * established the relevant VC.
- *
- * @param numberOfCells unsigned int [in] - Indicates how many ATM cells should
- * be added to the queue for this VC.
- *
- * @return
- * - <b>IX_SUCCESS :</b> The VC queue has been successfully updated.
- * - <b>IX_ATMSCH_RET_QUEUE_FULL :</b> The VC queue has reached a
- * preset limit. This indicates the client has over-submitted
- * and exceeded its transmission quota. The request is
- * rejected. The VC queue is not updated. The VC user is
- * advised to resubmit the request later.
- * - <b>IX_FAIL :</b> The input are invalid. No VC queue is updated.
- *
- * @warning IxAtmSch assumes that the calling software ensures that
- * calls to ixAtmSchVcQueueUpdate, ixAtmSchVcQueueClear and
- * ixAtmSchTableUpdate are both self and mutually exclusive
- * for the same port.
- *
- * @sa ixAtmSchVcQueueUpdate(), ixAtmSchVcQueueClear(), ixAtmSchTableUpdate(). */
-PUBLIC IX_STATUS
-ixAtmSchVcQueueUpdate( IxAtmLogicalPort port,
- IxAtmSchedulerVcId vcId,
- unsigned int numberOfCells);
-
-/**
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchVcQueueClear( IxAtmLogicalPort port,
- IxAtmSchedulerVcId vcId)
- *
- * @brief The client calls this function to remove all currently
- * queued cells from a registered VC. The pending cell count
- * for the specified VC is reset to zero.
- *
- * This interface is structurally compatible with the
- * IxAtmdAccSchQueueClear callback type definition required for
- * IXP400 ATM scheduler interoperability.
- *
- * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be
- * cleared is established.
- *
- * @param vcId @ref IxAtmSchedulerVcId [in] - Identifies the VC to be cleared. This is the
- * value returned by the @ref ixAtmSchVcModelSetup call which
- * established the relevant VC.
- *
- * @return
- * - <b>IX_SUCCESS :</b> The VC queue has been successfully cleared.
- * - <b>IX_FAIL :</b> The input are invalid. No VC queue is modified.
- *
- * @warning IxAtmSch assumes that the calling software ensures that
- * calls to ixAtmSchVcQueueUpdate, ixAtmSchVcQueueClear and
- * ixAtmSchTableUpdate are both self and mutually exclusive
- * for the same port.
- *
- * @sa ixAtmSchVcQueueUpdate(), ixAtmSchVcQueueClear(), ixAtmSchTableUpdate(). */
-PUBLIC IX_STATUS
-ixAtmSchVcQueueClear( IxAtmLogicalPort port,
- IxAtmSchedulerVcId vcId);
-
-/**
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchTableUpdate( IxAtmLogicalPort port,
- unsigned int maxCells,
- IxAtmScheduleTable **rettable)
- *
- * @brief The client calls this function to request an update of the
- * schedule table for a particular ATM port.
- *
- * This is called when the client decides it needs a new sequence of
- * cells to send (probably because the transmit queue is near to
- * empty for this ATM port). The scheduler will use its stored
- * information on the cells submitted for transmit (i.e. data
- * supplied via @ref ixAtmSchVcQueueUpdate function) with the traffic
- * descriptor information of all established VCs on the ATM port to
- * decide the sequence of cells to be sent and fill the schedule
- * table for a period of time into the future.
- *
- * IxAtmSch will guarantee a minimum of minCellsToSchedule if there
- * is at least one cell ready to send. If there are no cells then
- * IX_ATMSCH_RET_QUEUE_EMPTY is returned.
- *
- * This implementation of ixAtmSchTableUpdate uses no operating
- * system or external facilities, either directly or indirectly.
- * This allows clients to call this function form within an FIQ
- * interrupt handler.
- *
- * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port for which requested
- * schedule table is to be generated.
- *
- * @param maxCells unsigned [in] - Specifies the maximum number of cells
- * that must be scheduled in the supplied table during any
- * call to the interface.
- *
- * @param **table @ref IxAtmScheduleTable [out] - A pointer to an area of
- * storage is returned which contains the generated
- * schedule table. The client should not modify the
- * contents of this table.
- *
- * @return
- * - <b>IX_SUCCESS :</b> The schedule table has been published.
- * Currently there is at least one VC queue that is nonempty.
- * - <b>IX_ATMSCH_RET_QUEUE_EMPTY :</b> Currently all VC queues on
- * this port are empty. The schedule table returned is set to
- * NULL. The client is not expected to invoke this function
- * again until more cells have been submitted on this port
- * through the @ref ixAtmSchVcQueueUpdate function.
- * - <b>IX_FAIL :</b> The input are invalid. No action is taken.
- *
- * @warning IxAtmSch assumes that the calling software ensures that
- * calls to ixAtmSchVcQueueUpdate, ixAtmSchVcQueueClear and
- * ixAtmSchTableUpdate are both self and mutually exclusive
- * for the same port.
- *
- * @warning Subsequent calls to this function for the same port will
- * overwrite the contents of previously supplied schedule
- * tables. The client must be completely finished with the
- * previously supplied schedule table before calling this
- * function again for the same port.
- *
- * @sa ixAtmSchVcQueueUpdate(), ixAtmSchVcQueueClear(), ixAtmSchTableUpdate(). */
-PUBLIC IX_STATUS
-ixAtmSchTableUpdate( IxAtmLogicalPort port,
- unsigned int maxCells,
- IxAtmScheduleTable **rettable);
-
-/**
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchShow(void)
- *
- * @brief Utility function which will print statistics on the current
- * and accumulated state of VCs and traffic in the ATM
- * scheduler component. Output is sent to the default output
- * device.
- *
- * @param none
- * @return none
- */
-PUBLIC void
-ixAtmSchShow(void);
-
-/**
- * @ingroup IxAtmSch
- *
- * @fn ixAtmSchStatsClear(void)
- *
- * @brief Utility function which will reset all counter statistics in
- * the ATM scheduler to zero.
- *
- * @param none
- * @return none
- */
-PUBLIC void
-ixAtmSchStatsClear(void);
-
-#endif
-/* IXATMSCH_H */
-
-/** @} */
+++ /dev/null
-/**
- * @file IxAtmTypes.h
- *
- * @date 24-MAR-2002
- *
- * @brief This file contains Atm types common to a number of Atm components.
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-/* ------------------------------------------------------
- Doxygen group definitions
- ------------------------------------------------------ */
-/**
- * @defgroup IxAtmTypes IXP400 ATM Types (IxAtmTypes)
- *
- * @brief The common set of types used in many Atm components
- *
- * @{ */
-
-#ifndef IXATMTYPES_H
-#define IXATMTYPES_H
-
-#include "IxNpeA.h"
-
-/**
- * @enum IxAtmLogicalPort
- *
- * @brief Logical Port Definitions :
- *
- * Only 1 port is available in SPHY configuration
- * 12 ports are enabled in MPHY configuration
- *
- */
-typedef enum
-{
- IX_UTOPIA_PORT_0 = 0, /**< Port 0 */
-#ifdef IX_NPE_MPHYMULTIPORT
- IX_UTOPIA_PORT_1, /**< Port 1 */
- IX_UTOPIA_PORT_2, /**< Port 2 */
- IX_UTOPIA_PORT_3, /**< Port 3 */
- IX_UTOPIA_PORT_4, /**< Port 4 */
- IX_UTOPIA_PORT_5, /**< Port 5 */
- IX_UTOPIA_PORT_6, /**< Port 6 */
- IX_UTOPIA_PORT_7, /**< Port 7 */
- IX_UTOPIA_PORT_8, /**< Port 8 */
- IX_UTOPIA_PORT_9, /**< Port 9 */
- IX_UTOPIA_PORT_10, /**< Port 10 */
- IX_UTOPIA_PORT_11, /**< Port 11 */
-#endif /* IX_NPE_MPHY */
- IX_UTOPIA_MAX_PORTS /**< Not a port - just a definition for the
- * maximum possible ports
- */
-} IxAtmLogicalPort;
-
-/**
- * @def IX_ATM_CELL_PAYLOAD_SIZE
- * @brief Size of a ATM cell payload
- */
-#define IX_ATM_CELL_PAYLOAD_SIZE (48)
-
-/**
- * @def IX_ATM_CELL_SIZE
- * @brief Size of a ATM cell, including header
- */
-#define IX_ATM_CELL_SIZE (53)
-
-/**
- * @def IX_ATM_CELL_SIZE_NO_HEC
- * @brief Size of a ATM cell, excluding HEC byte
- */
-#define IX_ATM_CELL_SIZE_NO_HEC (IX_ATM_CELL_SIZE - 1)
-
-/**
- * @def IX_ATM_OAM_CELL_SIZE_NO_HEC
- * @brief Size of a OAM cell, excluding HEC byte
- */
-#define IX_ATM_OAM_CELL_SIZE_NO_HEC IX_ATM_CELL_SIZE_NO_HEC
-
-/**
- * @def IX_ATM_AAL0_48_CELL_PAYLOAD_SIZE
- * @brief Size of a AAL0 48 Cell payload
- */
-#define IX_ATM_AAL0_48_CELL_PAYLOAD_SIZE IX_ATM_CELL_PAYLOAD_SIZE
-
-/**
- * @def IX_ATM_AAL5_CELL_PAYLOAD_SIZE
- * @brief Size of a AAL5 Cell payload
- */
-#define IX_ATM_AAL5_CELL_PAYLOAD_SIZE IX_ATM_CELL_PAYLOAD_SIZE
-
-/**
- * @def IX_ATM_AAL0_52_CELL_SIZE_NO_HEC
- * @brief Size of a AAL0 52 Cell, excluding HEC byte
- */
-#define IX_ATM_AAL0_52_CELL_SIZE_NO_HEC IX_ATM_CELL_SIZE_NO_HEC
-
-
-/**
- * @def IX_ATM_MAX_VPI
- * @brief Maximum value of an ATM VPI
- */
-#define IX_ATM_MAX_VPI 255
-
-/**
- * @def IX_ATM_MAX_VCI
- * @brief Maximum value of an ATM VCI
- */
-#define IX_ATM_MAX_VCI 65535
-
- /**
- * @def IX_ATM_MAX_NUM_AAL_VCS
- * @brief Maximum number of active AAL5/AAL0 VCs in the system
- */
-#define IX_ATM_MAX_NUM_AAL_VCS 32
-
-/**
- * @def IX_ATM_MAX_NUM_VC
- * @brief Maximum number of active AAL5/AAL0 VCs in the system
- * The use of this macro is depreciated, it is retained for
- * backward compatiblity. For current software release
- * and beyond the define IX_ATM_MAX_NUM_AAL_VC should be used.
- */
-#define IX_ATM_MAX_NUM_VC IX_ATM_MAX_NUM_AAL_VCS
-
-
-
-/**
- * @def IX_ATM_MAX_NUM_OAM_TX_VCS
- * @brief Maximum number of active OAM Tx VCs in the system,
- * 1 OAM VC per port
- */
-#define IX_ATM_MAX_NUM_OAM_TX_VCS IX_UTOPIA_MAX_PORTS
-
-/**
- * @def IX_ATM_MAX_NUM_OAM_RX_VCS
- * @brief Maximum number of active OAM Rx VCs in the system,
- * 1 OAM VC shared accross all ports
- */
-#define IX_ATM_MAX_NUM_OAM_RX_VCS 1
-
-/**
- * @def IX_ATM_MAX_NUM_AAL_OAM_TX_VCS
- * @brief Maximum number of active AAL5/AAL0/OAM Tx VCs in the system
- */
-#define IX_ATM_MAX_NUM_AAL_OAM_TX_VCS (IX_ATM_MAX_NUM_AAL_VCS + IX_ATM_MAX_NUM_OAM_TX_VCS)
-
-/**
- * @def IX_ATM_MAX_NUM_AAL_OAM_RX_VCS
- * @brief Maximum number of active AAL5/AAL0/OAM Rx VCs in the system
- */
-#define IX_ATM_MAX_NUM_AAL_OAM_RX_VCS (IX_ATM_MAX_NUM_AAL_VCS + IX_ATM_MAX_NUM_OAM_RX_VCS)
-
-/**
- * @def IX_ATM_IDLE_CELLS_CONNID
- * @brief VC Id used to indicate idle cells in the returned schedule table.
- */
-#define IX_ATM_IDLE_CELLS_CONNID 0
-
-
-/**
- * @def IX_ATM_CELL_HEADER_VCI_GET
- * @brief get the VCI field from a cell header
- */
-#define IX_ATM_CELL_HEADER_VCI_GET(cellHeader) \
- (((cellHeader) >> 4) & IX_OAM_VCI_BITS_MASK);
-
-/**
- * @def IX_ATM_CELL_HEADER_VPI_GET
- * @brief get the VPI field from a cell header
- */
-#define IX_ATM_CELL_HEADER_VPI_GET(cellHeader) \
- (((cellHeader) >> 20) & IX_OAM_VPI_BITS_MASK);
-
-/**
- * @def IX_ATM_CELL_HEADER_PTI_GET
- * @brief get the PTI field from a cell header
- */
-#define IX_ATM_CELL_HEADER_PTI_GET(cellHeader) \
- ((cellHeader) >> 1) & IX_OAM_PTI_BITS_MASK;
-
-/**
- * @typedef IxAtmCellHeader
- *
- * @brief ATM Cell Header, does not contain 4 byte HEC, added by NPE-A
- */
-typedef unsigned int IxAtmCellHeader;
-
-
-/**
- * @enum IxAtmServiceCategory
- *
- * @brief Enumerated type representing available ATM service categories.
- * For more informatoin on these categories, see "Traffic Management
- * Specification" v4.1, published by the ATM Forum -
- * http://www.atmforum.com
- */
-typedef enum
-{
- IX_ATM_CBR, /**< Constant Bit Rate */
- IX_ATM_RTVBR, /**< Real Time Variable Bit Rate */
- IX_ATM_VBR, /**< Variable Bit Rate */
- IX_ATM_UBR, /**< Unspecified Bit Rate */
- IX_ATM_ABR /**< Available Bit Rate (not supported) */
-
-} IxAtmServiceCategory;
-
-/**
- *
- * @enum IxAtmRxQueueId
- *
- * @brief Rx Queue Type for RX traffic
- *
- * IxAtmRxQueueId defines the queues involved for receiving data.
- *
- * There are two queues to facilitate prioritisation handling
- * and processing the 2 queues with different algorithms and
- * constraints
- *
- * e.g. : one queue can carry voice (or time-critical traffic), the
- * other queue can carry non-voice traffic
- *
- */
-typedef enum
-{
- IX_ATM_RX_A = 0, /**< RX queue A */
- IX_ATM_RX_B, /**< RX queue B */
- IX_ATM_MAX_RX_STREAMS /**< Maximum number of RX streams */
-} IxAtmRxQueueId;
-
-/**
- * @brief Structure describing an ATM traffic contract for a Virtual
- * Connection (VC).
- *
- * Structure is used to specify the requested traffic contract for a
- * VC to the IxAtmSch component using the @ref ixAtmSchVcModelSetup
- * interface.
- *
- * These parameters are defined by the ATM forum working group
- * (http://www.atmforum.com).
- *
- * @note Typical values for a voice channel 64 Kbit/s
- * - atmService @a IX_ATM_RTVBR
- * - pcr 400 (include IP overhead, and AAL5 trailer)
- * - cdvt 5000000 (5 ms)
- * - scr = pcr
- *
- * @note Typical values for a data channel 800 Kbit/s
- * - atmService @a IX_ATM_UBR
- * - pcr 1962 (include IP overhead, and AAL5 trailer)
- * - cdvt 5000000 (5 ms)
- *
- */
-typedef struct
-{
- IxAtmServiceCategory atmService; /**< ATM service category */
- unsigned pcr; /**< Peak Cell Rate - cells per second */
- unsigned cdvt; /**< Cell Delay Variation Tolerance - in nanoseconds */
- unsigned scr; /**< Sustained Cell Rate - cells per second */
- unsigned mbs; /**< Max Burst Size - cells */
- unsigned mcr; /**< Minimum Cell Rate - cells per second */
- unsigned mfs; /**< Max Frame Size - cells */
-} IxAtmTrafficDescriptor;
-
-/**
- * @typedef IxAtmConnId
- *
- * @brief ATM VC data connection identifier.
- *
- * This is is generated by IxAtmdAcc when a successful connection is
- * made on a VC. The is the ID by which IxAtmdAcc knows an active
- * VC and should be used in IxAtmdAcc API calls to reference a
- * specific VC.
- */
-typedef unsigned int IxAtmConnId;
-
-/**
- * @typedef IxAtmSchedulerVcId
- *
- * @brief ATM VC scheduling connection identifier.
- *
- * This id is generated and used by ATM Tx controller, generally
- * the traffic shaper (e.g. IxAtmSch). The IxAtmdAcc component
- * will request one of these Ids whenever a data connection on
- * a Tx VC is requested. This ID will be used in callbacks to
- * the ATM Transmission Ctrl s/w (e.g. IxAtmm) to reference a
- * particular VC.
- */
-typedef int IxAtmSchedulerVcId;
-
-/**
- * @typedef IxAtmNpeRxVcId
- *
- * @brief ATM Rx VC identifier used by the ATM Npe.
- *
- * This Id is generated by IxAtmdAcc when a successful data connection
- * is made on a rx VC.
- */
-typedef unsigned int IxAtmNpeRxVcId;
-
-/**
- * @brief ATM Schedule Table entry
- *
- * This IxAtmScheduleTableEntry is used by an ATM scheduler to inform
- * IxAtmdAcc about the data to transmit (in term of cells per VC)
- *
- * This structure defines
- * @li the number of cells to be transmitted (numberOfCells)
- * @li the VC connection to be used for transmission (connId).
- *
- * @note - When the connection Id value is IX_ATM_IDLE_CELLS_CONNID, the
- * corresponding number of idle cells will be transmitted to the hardware.
- *
- */
-typedef struct
-{
- IxAtmConnId connId; /**< connection Id
- *
- * Identifier of VC from which cells are to be transmitted.
- * When this valus is IX_ATM_IDLE_CELLS_CONNID, this indicates
- * that the system should transmit the specified number
- * of idle cells. Unknown connIds result in the transmission
- * idle cells.
- */
- unsigned int numberOfCells; /**< number of cells to transmit
- *
- * The number of contiguous cells to schedule from this VC
- * at this point. The valid range is from 1 to
- * @a IX_ATM_SCHEDULETABLE_MAXCELLS_PER_ENTRY. This
- * number can swap over mbufs and pdus. OverSchduling results
- * in the transmission of idle cells.
- */
-} IxAtmScheduleTableEntry;
-
-/**
- * @brief This structure defines a schedule table which gives details
- * on which data (from which VCs) should be transmitted for a
- * forthcoming period of time for a particular port and the
- * order in which that data should be transmitted.
- *
- * The schedule table consists of a series of entries each of which
- * will schedule one or more cells from a particular registered VC.
- * The total number of cells scheduled and the total number of
- * entries in the table are also indicated.
- *
- */
-typedef struct
-{
- unsigned tableSize; /**< Number of entries
- *
- * Indicates the total number of
- * entries in the table.
- */
- unsigned totalCellSlots; /**< Number of cells
- *
- * Indicates the total number of ATM
- * cells which are scheduled by all the
- * entries in the table.
- */
- IxAtmScheduleTableEntry *table; /**< Pointer to schedule entries
- *
- * Pointer to an array
- * containing tableSize entries
- */
-} IxAtmScheduleTable;
-
-#endif /* IXATMTYPES_H */
-
-/**
- * @} defgroup IxAtmTypes
- */
-
-
+++ /dev/null
-
-/**
- * @file IxAtmdAcc.h
- *
- * @date 07-Nov-2001
- *
- * @brief IxAtmdAcc Public API
- *
- * This file contains the public API of IxAtmdAcc, related to the
- * data functions of the component
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-/* ------------------------------------------------------
- Doxygen group definitions
- ------------------------------------------------------ */
-
-/**
- *
- * @defgroup IxAtmdAccAPI IXP400 ATM Driver Access (IxAtmdAcc) API
- *
- * @brief The public API for the IXP400 Atm Driver Data component
- *
- * IxAtmdAcc is the low level interface by which AAL0/AAL5 and
- * OAM data gets transmitted to,and received from the Utopia bus.
- *
- * For AAL0/AAL5 services transmit and receive connections may
- * be established independantly for unique combinations of
- * port,VPI,and VCI.
- *
- * Two AAL0 services supporting 48 or 52 byte cell data are provided.
- * Submitted AAL0 PDUs must be a multiple of the cell data size (48/52).
- * AAL0_52 is a raw cell service the client must format
- * the PDU with an ATM cell header (excluding HEC) at the start of
- * each cell, note that AtmdAcc does not validate the cell headers in
- * a submitted PDU.
- *
- * OAM cells cannot be received over the AAL0 service but instead
- * are received over a dedicated OAM service.
- *
- * For the OAM service an "OAM Tx channel" may be enabled for a port
- * by establishing a single dedicated OAM Tx connection on that port.
- * A single "OAM Rx channel" for all ports may be enabled by
- * establishing a dedicated OAM Rx connection.
- *
- * The OAM service allows buffers containing 52 byte OAM F4/F5 cells
- * to be transmitted and received over the dedicated OAM channels.
- * HEC is appended/removed, and CRC-10 performed by the NPE. The OAM
- * service offered by AtmdAcc is a raw cell transport service.
- * It is assumed that ITU I.610 procedures that make use of this
- * service are implemented above AtmdAcc.
- *
- * Note that the dedicated OAM connections are established on
- * reserved VPI,VCI, and (in the case of Rx) port values defined below.
- * These values are used purely to descriminate the dedicated OAM channels
- * and do not identify a particular OAM F4/F5 flow. F4/F5 flows may be
- * realised for particluar VPI/VCIs by manipulating the VPI,VCI
- * fields of the ATM cell headers of cells in the buffers passed
- * to AtmdAcc. Note that AtmdAcc does not validate the cell headers
- * in a submitted OAM PDU.
- *
- *
- *
- * This part is related to the User datapath processing
- *
- * @{
- */
-
-#ifndef IXATMDACC_H
-#define IXATMDACC_H
-
-#include "IxAtmTypes.h"
-
-/* ------------------------------------------------------
- AtmdAcc Data Types definition
- ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_WARNING
- *
- * @brief Warning return code
- *
- * This constant is used to tell IxAtmDAcc user about a special case.
- *
- */
-#define IX_ATMDACC_WARNING 2
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_BUSY
- *
- * @brief Busy return code
- *
- * This constant is used to tell IxAtmDAcc user that the request
- * is correct, but cannot be processed because the IxAtmAcc resources
- * are already used. The user has to retry its request later
- *
- */
-#define IX_ATMDACC_BUSY 3
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_RESOURCES_STILL_ALLOCATED
- *
- * @brief Disconnect return code
- *
- * This constant is used to tell IxAtmDAcc user that the disconnect
- * functions are not complete because the resources used by the driver
- * are not yet released. The user has to retry the disconnect call
- * later.
- *
- */
-#define IX_ATMDACC_RESOURCES_STILL_ALLOCATED 4
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_DEFAULT_REPLENISH_COUNT
- *
- * @brief Default resources usage for RxVcFree replenish mechanism
- *
- * This constant is used to tell IxAtmDAcc to allocate and use
- * the minimum of resources for rx free replenish.
- *
- * @sa ixAtmdAccRxVcConnect
- */
-#define IX_ATMDACC_DEFAULT_REPLENISH_COUNT 0
-
-
-/**
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_OAM_TX_VPI
- *
- * @brief The reserved value used for the dedicated OAM
- * Tx connection. This "well known" value is used by atmdAcc and
- * its clients to dsicriminate the OAM channel, and should be chosen so
- * that it does not coencide with the VPI value used in an AAL0/AAL5 connection.
- * Any attempt to connect a service type other than OAM on this VPI will fail.
- *
- *
- */
-#define IX_ATMDACC_OAM_TX_VPI 0
-
-/**
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_OAM_TX_VCI
- *
- * @brief The reserved value used for the dedicated OAM
- * Tx connection. This "well known" value is used by atmdAcc and
- * its clients to dsicriminate the OAM channel, and should be chosen so
- * that it does not coencide with the VCI value used in an AAL0/AAL5 connection.
- * Any attempt to connect a service type other than OAM on this VCI will fail.
- */
-#define IX_ATMDACC_OAM_TX_VCI 0
-
-
- /**
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_OAM_RX_PORT
- *
- * @brief The reserved dummy PORT used for all dedicated OAM
- * Rx connections. Note that this is not a real port but must
- * have a value that lies within the valid range of port values.
- */
-#define IX_ATMDACC_OAM_RX_PORT IX_UTOPIA_PORT_0
-
- /**
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_OAM_RX_VPI
- *
- * @brief The reserved value value used for the dedicated OAM
- * Rx connection. This value should be chosen so that it does not
- * coencide with the VPI value used in an AAL0/AAL5 connection.
- * Any attempt to connect a service type other than OAM on this VPI will fail.
- */
-#define IX_ATMDACC_OAM_RX_VPI 0
-
-/**
- * @ingroup IxAtmdAccAPI
- *
- * @def IX_ATMDACC_OAM_RX_VCI
- *
- * @brief The reserved value value used for the dedicated OAM
- * Rx connection. This value should be chosen so that it does not
- * coencide with the VCI value used in an AAL0/AAL5 connection.
- * Any attempt to connect a service type other than OAM on this VCI will fail.
- */
-#define IX_ATMDACC_OAM_RX_VCI 0
-
-
-/**
- * @enum IxAtmdAccPduStatus
- *
- * @ingroup IxAtmdAccAPI
- *
- * @brief IxAtmdAcc Pdu status :
- *
- * IxAtmdAccPduStatus is used during a RX operation to indicate
- * the status of the received PDU
- *
- */
-
-typedef enum
-{
- IX_ATMDACC_AAL0_VALID = 0, /**< aal0 pdu */
- IX_ATMDACC_OAM_VALID, /**< OAM pdu */
- IX_ATMDACC_AAL2_VALID, /**< aal2 pdu @b reserved for future use */
- IX_ATMDACC_AAL5_VALID, /**< aal5 pdu complete and trailer is valid */
- IX_ATMDACC_AAL5_PARTIAL, /**< aal5 pdu not complete, trailer is missing */
- IX_ATMDACC_AAL5_CRC_ERROR, /**< aal5 pdu not complete, crc error/length error */
- IX_ATMDACC_MBUF_RETURN /**< empty buffer returned to the user */
-} IxAtmdAccPduStatus;
-
-
-/**
- *
- * @enum IxAtmdAccAalType
- *
- * @ingroup IxAtmdAccAPI
- *
- * @brief IxAtmdAcc AAL Service Type :
- *
- * IxAtmdAccAalType defines the type of traffic to run on this VC
- *
- */
-typedef enum
-{
- IX_ATMDACC_AAL5, /**< ITU-T AAL5 */
- IX_ATMDACC_AAL2, /**< ITU-T AAL2 @b reserved for future use */
- IX_ATMDACC_AAL0_48, /**< AAL0 48 byte payloads (cell header is added by NPE)*/
- IX_ATMDACC_AAL0_52, /**< AAL0 52 byte cell data (HEC is added by NPE) */
- IX_ATMDACC_OAM, /**< OAM cell transport service (HEC is added by NPE)*/
- IX_ATMDACC_MAX_SERVICE_TYPE /**< not a service, used for parameter validation */
-} IxAtmdAccAalType;
-
-/**
- *
- * @enum IxAtmdAccClpStatus
- *
- * @ingroup IxAtmdAccAPI
- *
- * @brief IxAtmdAcc CLP indication
- *
- * IxAtmdAccClpStatus defines the CLP status of the current PDU
- *
- */
-typedef enum
-{
- IX_ATMDACC_CLP_NOT_SET = 0, /**< CLP indication is not set */
- IX_ATMDACC_CLP_SET = 1 /**< CLP indication is set */
-} IxAtmdAccClpStatus;
-
-/**
- * @typedef IxAtmdAccUserId
- *
- * @ingroup IxAtmdAccAPI
- *
- * @brief User-supplied Id
- *
- * IxAtmdAccUserId is passed through callbacks and allows the
- * IxAtmdAcc user to identify the source of a call back. The range of
- * this user-owned Id is [0...2^32-1)].
- *
- * The user provides this own Ids on a per-channel basis as a parameter
- * in a call to @a ixAtmdAccRxVcConnect() or @a ixAtmdAccRxVcConnect()
- *
- * @sa ixAtmdAccRxVcConnect
- * @sa ixAtmdAccTxVcConnect
- *
- */
-typedef unsigned int IxAtmdAccUserId;
-
-/* ------------------------------------------------------
- Part of the IxAtmdAcc interface related to RX traffic
- ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @brief Rx callback prototype
- *
- * IxAtmdAccRxVcRxCallback is the prototype of the Rx callback user
- * function called once per PDU to pass a receive Pdu to a user on a
- * partilcular connection. The callback is likely to push the mbufs
- * to a protocol layer, and recycle the mbufs for a further use.
- *
- * @note -This function is called ONLY in the context of
- * the @a ixAtmdAccRxDispatch() function
- *
- * @sa ixAtmdAccRxDispatch
- * @sa ixAtmdAccRxVcConnect
- *
- * @param port @ref IxAtmLogicalPort [in] - the port on which this PDU was received
- * a logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- * @param userId @ref IxAtmdAccUserId [in] - user Id provided in the call
- * to @a ixAtmdAccRxVcConnect()
- * @param status @ref IxAtmdAccPduStatus [in] - an indication about the PDU validity.
- * In the case of AAL0 the only possibile value is
- * AAL0_VALID, in this case the client may optionally determine
- * that an rx timeout occured by checking if the mbuf is
- * compleletly or only partially filled, the later case
- * indicating a timeout.
- * In the case of OAM the only possible value is OAM valid.
- * The status is set to @a IX_ATMDACC_MBUF_RETURN when
- * the mbuf is released during a disconnect process.
- * @param clp @ref IxAtmdAccClpStatus [in] - clp indication for this PDU.
- * For AAL5/AAL0_48 this information
- * is set if the clp bit of any rx cell is set
- * For AAL0-52/OAM the client may inspect the CLP in individual
- * cell headers in the PDU, and this parameter is set to 0.
- * @param *mbufPtr @ref IX_OSAL_MBUF [in] - depending on the servive type a pointer to
- * an mbuf (AAL5/AAL0/OAM) or mbuf chain (AAL5 only),
- * that comprises the complete PDU data.
- *
- * This parameter is guaranteed not to be a null pointer.
- *
- */
-typedef void (*IxAtmdAccRxVcRxCallback) (IxAtmLogicalPort port,
- IxAtmdAccUserId userId,
- IxAtmdAccPduStatus status,
- IxAtmdAccClpStatus clp,
- IX_OSAL_MBUF * mbufPtr);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @brief Callback prototype for free buffer level is low.
- *
- * IxAtmdAccRxVcFreeLowCallback is the prototype of the user function
- * which get called on a per-VC basis, when more mbufs are needed to
- * continue the ATM data reception. This function is likely to supply
- * more available mbufs by one or many calls to the replenish function
- * @a ixAtmdAccRxVcFreeReplenish()
- *
- * This function is called when the number of available buffers for
- * reception is going under the threshold level as defined
- * in @a ixAtmdAccRxVcFreeLowCallbackRegister()
- *
- * This function is called inside an Qmgr dispatch context. No system
- * resource or interrupt-unsafe feature should be used inside this
- * callback.
- *
- * @sa ixAtmdAccRxVcFreeLowCallbackRegister
- * @sa IxAtmdAccRxVcFreeLowCallback
- * @sa ixAtmdAccRxVcFreeReplenish
- * @sa ixAtmdAccRxVcFreeEntriesQuery
- * @sa ixAtmdAccRxVcConnect
- *
- * @param userId @ref IxAtmdAccUserId [in] - user Id provided in the call
- * to @a ixAtmdAccRxVcConnect()
- *
- * @return None
- *
- */
-typedef void (*IxAtmdAccRxVcFreeLowCallback) (IxAtmdAccUserId userId);
-
-/* ------------------------------------------------------
- Part of the IxAtmdAcc interface related to TX traffic
- ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @brief Buffer callback prototype.
- *
- * This function is called to relinguish ownership of a transmitted
- * buffer chain to the user.
- *
- * @note -In the case of a chained mbuf the AmtdAcc component can
- * chain many user buffers together and pass ownership to the user in
- * one function call.
- *
- * @param userId @ref IxAtmdAccUserId [in] - user If provided at registration of this
- * callback.
- * @param mbufPtr @ref IX_OSAL_MBUF [in] - a pointer to mbufs or chain of mbufs and is
- * guaranteed not to be a null pointer.
- *
- */
-typedef void (*IxAtmdAccTxVcBufferReturnCallback) (IxAtmdAccUserId userId,
- IX_OSAL_MBUF * mbufPtr);
-
-/* ------------------------------------------------------
- Part of the IxAtmdAcc interface related to Initialisation
- ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccInit (void)
- *
- * @brief Initialise the IxAtmdAcc Component
- *
- * This function initialise the IxAtmdAcc component. This function shall
- * be called before any other function of the API. Its role is to
- * initialise all internal resources of the IxAtmdAcc component.
- *
- * The ixQmgr component needs to be initialized prior the use of
- * @a ixAtmdAccInit()
- *
- * @param none
- *
- * Failing to initilialize the IxAtmdAcc API before any use of it will
- * result in a failed status.
- * If the specified component is not present, a success status will still be
- * returned, however, a warning indicating the NPE to download to is not
- * present will be issued.
- *
- * @return @li IX_SUCCESS initialisation is complete (in case of component not
- * being present, a warning is clearly indicated)
- * @return @li IX_FAIL unable to process this request either
- * because this IxAtmdAcc is already initialised
- * or some unspecified error has occrred.
- */
-PUBLIC IX_STATUS ixAtmdAccInit (void);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccShow (void)
- *
- * @brief Show IxAtmdAcc configuration on a per port basis
- *
- * @param none
- *
- * @return none
- *
- * @note - Display use printf() and are redirected to stdout
- */
-PUBLIC void
-ixAtmdAccShow (void);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccStatsShow (void)
- *
- * @brief Show all IxAtmdAcc stats
- *
- * @param none
- *
- * @return none
- *
- * @note - Stats display use printf() and are redirected to stdout
- */
-PUBLIC void
-ixAtmdAccStatsShow (void);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccStatsReset (void)
- *
- * @brief Reset all IxAtmdAcc stats
- *
- * @param none
- *
- * @return none
- *
- */
-PUBLIC void
-ixAtmdAccStatsReset (void);
-
-/* ------------------------------------------------------
- Part of the IxAtmdAcc interface related to RX traffic
- ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccRxVcConnect (IxAtmLogicalPort port,
- unsigned int vpi,
- unsigned int vci,
- IxAtmdAccAalType aalServiceType,
- IxAtmRxQueueId rxQueueId,
- IxAtmdAccUserId userCallbackId,
- IxAtmdAccRxVcRxCallback rxCallback,
- unsigned int minimumReplenishCount,
- IxAtmConnId * connIdPtr,
- IxAtmNpeRxVcId * npeVcIdPtr )
- *
- * @brief Connect to a Aal Pdu receive service for a particular
- * port/vpi/vci, and service type.
- *
- * This function allows a user to connect to an Aal5/Aal0/OAM Pdu receive service
- * for a particular port/vpi/vci. It registers the callback and allocates
- * internal resources and a Connection Id to be used in further API calls
- * related to this VCC.
- *
- * The function will setup VC receive service on the specified rx queue.
- *
- * This function is blocking and makes use internal locks, and hence
- * should not be called from an interrupt context.
- *
- * On return from @a ixAtmdAccRxVcConnect() with a failure status, the
- * connection Id parameter is unspecified. Its value cannot be used.
- * A connId is the reference by which IxAtmdAcc refers to a
- * connected VC. This identifier is the result of a succesful call
- * to a connect function. This identifier is invalid after a
- * sucessful call to a disconnect function.
- *
- * Calling this function for the same combination of Vpi, Vci and more
- * than once without calling @a ixAtmdAccRxVcTryDisconnect() will result in a
- * failure status.
- *
- * If this function returns success the user should supply receive
- * buffers by calling @a ixAtmdAccRxVcFreeReplenish() and then call
- * @a ixAtmdAccRxVcEnable() to begin receiving pdus.
- *
- * There is a choice of two receive Qs on which the VC pdus could be
- * receive. The user must associate the VC with one of these. Essentially
- * having two qs allows more flexible system configuration such as have
- * high prioriy traffic on one q (e.g. voice) and low priority traffic on
- * the other (e.g. data). The high priority Q could be serviced in
- * preference to the low priority Q. One queue may be configured to be
- * serviced as soon as there is traffic, the other queue may be configured
- * to be serviced by a polling mechanism running at idle time.
- *
- * Two AAL0 services supporting 48 or 52 byte cell data are provided.
- * Received AAL0 PDUs will be be a multiple of the cell data size (48/52).
- * AAL0_52 is a raw cell service and includes an ATM cell header
- * (excluding HEC) at the start of each cell.
- *
- * A single "OAM Rx channel" for all ports may be enabled by
- * establishing a dedicated OAM Rx connection.
- *
- * The OAM service allows buffers containing 52 byte OAM F4/F5 cells
- * to be transmitted and received over the dedicated OAM channels.
- * HEC is appended/removed, and CRC-10 performed by the NPE. The OAM
- * service offered by AtmdAcc is a raw cell transport service.
- * It is assumed that ITU I.610 procedures that make use of this
- * service are implemented above AtmdAcc.
- *
- * Note that the dedicated OAM connections are established on
- * reserved VPI,VCI, and (in the case of Rx) port values.
- * These values are used purely to descriminate the dedicated OAM channels
- * and do not identify a particular OAM F4/F5 flow. F4/F5 flows may be
- * realised for particluar VPI/VCIs by manipulating the VPI,VCI
- * fields of the ATM cell headers of cells in the buffers passed
- * to AtmdAcc.
- *
- * Calling this function prior to enable the port will fail.
- *
- * @sa ixAtmdAccRxDispatch
- * @sa ixAtmdAccRxVcEnable
- * @sa ixAtmdAccRxVcDisable
- * @sa ixAtmdAccRxVcTryDisconnect
- * @sa ixAtmdAccPortEnable
- *
- * @param port @ref IxAtmLogicalPort [in] - VC identification : logical PHY port
- * [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- * @param vpi unsigned int [in] - VC identification : ATM Vpi [0..255] or IX_ATMDACC_OAM_VPI
- * @param vci unsigned int [in] - VC identification : ATM Vci [0..65535] or IX_ATMDACC_OAM_VCI
- * @param aalServiceType @ref IxAtmdAccAalType [in] - type of service: AAL5, AAL0_48, AAL0_52, or OAM
- * @param rxQueueId @ref IxAtmRxQueueId [in] - this identifieds which of two Qs the VC
- * should use.when icoming traffic is processed
- * @param userCallbackId @ref IxAtmdAccUserId [in] - user Id used later as a parameter to
- * the supplied rxCallback.
- * @param rxCallback [in] @ref IxAtmdAccRxVxRxCallback - function called when mbufs are received.
- * This parameter cannot be a null pointer.
- * @param bufferFreeCallback [in] - function to be called to return
- * ownership of buffers to IxAtmdAcc user.
- * @param minimumReplenishCount unsigned int [in] - For AAL5/AAL0 the number of free mbufs
- * to be used with this channel. Use a high number when the expected traffic
- * rate on this channel is high, or when the user's mbufs are small, or when
- * the RxVcFreeLow Notification has to be invoked less often. When this
- * value is IX_ATMDACC_DEFAULT_REPLENISH_COUNT, the minimum of
- * resources will be used. Depending on traffic rate, pdu
- * size and mbuf size, rxfree queue size, polling/interrupt rate, this value may
- * require to be replaced by a different value in the range 1-128
- * For OAM the rxFree queue size is fixed by atmdAcc and this parameter is ignored.
- * @param connIdPtr @ref IxAtmConnId [out] - pointer to a connection Id
- * This parameter cannot be a null pointer.
- * @param npeVcIdPtr @ref IxAtmNpeRxVcId [out] - pointer to an npe Vc Id
- * This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS successful call to IxAtmdAccRxVcConnect
- * @return @li IX_ATMDACC_BUSY cannot process this request :
- * no VC is available
- * @return @li IX_FAIL
- * parameter error,
- * VC already in use,
- * attempt to connect AAL service on reserved OAM VPI/VCI,
- * attempt to connect OAM service on VPI/VCI other than the reserved OAM VPI/VCI,
- * port is not initialised,
- * or some other error occurs during processing.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxVcConnect (IxAtmLogicalPort port,
- unsigned int vpi,
- unsigned int vci,
- IxAtmdAccAalType aalServiceType,
- IxAtmRxQueueId rxQueueId,
- IxAtmdAccUserId userCallbackId,
- IxAtmdAccRxVcRxCallback rxCallback,
- unsigned int minimumReplenishCount,
- IxAtmConnId * connIdPtr,
- IxAtmNpeRxVcId * npeVcIdPtr );
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccRxVcFreeReplenish (IxAtmConnId connId,
- IX_OSAL_MBUF * mbufPtr)
- *
- * @brief Provide free mbufs for data reception on a connection.
- *
- * This function provides mbufs for data reception by the hardware. This
- * function needs to be called by the user on a regular basis to ensure
- * no packet loss. Providing free buffers is a connection-based feature;
- * each connection can have different requirements in terms of buffer size
- * number of buffers, recycling rate. This function could be invoked from
- * within the context of a @a IxAtmdAccRxVcFreeLowCallback() callback
- * for a particular VC
- *
- * Mbufs provided through this function call can be chained. They will be
- * unchained internally. A call to this function with chained mbufs or
- * multiple calls with unchained mbufs are equivalent, but calls with
- * unchained mbufs are more efficients.
- *
- * Mbufs provided to this interface need to be able to hold at least one
- * full cell payload (48/52 bytes, depending on service type).
- * Chained buffers with a size less than the size supported by the hardware
- * will be returned through the rx callback provided during the connect step.
- *
- * Failing to invoke this function prior to enabling the RX traffic
- * can result in packet loss.
- *
- * This function is not reentrant for the same connId.
- *
- * This function does not use system resources and can be
- * invoked from an interrupt context.
- *
- * @note - Over replenish is detected, and extra mbufs are returned through
- * the rx callback provided during the connect step.
- *
- * @note - Mbuf provided to the replenish function should have a length greater or
- * equal to 48/52 bytes according to service type.
- *
- * @note - The memory cache of mMbuf payload should be invalidated prior to Mbuf
- * submission. Flushing the Mbuf headers is handled by IxAtmdAcc.
- *
- * @note - When a chained mbuf is provided, this function process the mbufs
- * up to the hardware limit and invokes the user-supplied callback
- * to release extra buffers.
- *
- * @sa ixAtmdAccRxVcFreeLowCallbackRegister
- * @sa IxAtmdAccRxVcFreeLowCallback
- * @sa ixAtmdAccRxVcConnect
- *
- * @param connId @ref IxAtmConnId [in] - connection Id as returned from a succesfull call to
- * @a IxAtmdAccRxVcConnect()
- * @param mbufPtr @ref IX_OSAL_MBUF [in] - pointer to a mbuf structure to be used for data
- * reception. The mbuf pointed to by this parameter can be chained
- * to an other mbuf.
- *
- * @return @li IX_SUCCESS successful call to @a ixAtmdAccRxVcFreeReplenish()
- * and the mbuf is now ready to use for incoming traffic.
- * @return @li IX_ATMDACC_BUSY cannot process this request because
- * the max number of outstanding free buffers has been reached
- * or the internal resources have exhausted for this VC.
- * The user is responsible for retrying this request later.
- * @return @li IX_FAIL cannot process this request because of parameter
- * errors or some unspecified internal error has occurred.
- *
- * @note - It is not always guaranteed the replenish step to be as fast as the
- * hardware is consuming Rx Free mbufs. There is nothing in IxAtmdAcc to
- * guarantee that replenish reaches the rxFree threshold level. If the
- * threshold level is not reached, the next rxFree low notification for
- * this channel will not be triggered.
- * The preferred ways to replenish can be as follows (depending on
- * applications and implementations) :
- * @li Replenish in a rxFree low notification until the function
- * ixAtmdAccRxVcFreeReplenish() returns IX_ATMDACC_BUSY
- * @li Query the queue level using @sa ixAtmdAccRxVcFreeEntriesQuery, then
- * , replenish using @a ixAtmdAccRxVcFreeReplenish(), then query the queue
- * level again, and replenish if the threshold is still not reached.
- * @li Trigger replenish from an other event source and use rxFree starvation
- * to throttle the Rx traffic.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxVcFreeReplenish (IxAtmConnId connId,
- IX_OSAL_MBUF * mbufPtr);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccRxVcFreeLowCallbackRegister (IxAtmConnId connId,
- unsigned int numberOfMbufs,
- IxAtmdAccRxVcFreeLowCallback callback)
- *
- * @brief Configure the RX Free threshold value and register a callback
- * to handle threshold notifications.
- *
- * The function ixAtmdAccRxVcFreeLowCallbackRegister sets the threshold value for
- * a particular RX VC. When the number of buffers reaches this threshold
- * the callback is invoked.
- *
- * This function should be called once per VC before RX traffic is
- * enabled.This function will fail if the curent level of the free buffers
- * is equal or less than the threshold value.
- *
- * @sa ixAtmdAccRxVcFreeLowCallbackRegister
- * @sa IxAtmdAccRxVcFreeLowCallback
- * @sa ixAtmdAccRxVcFreeReplenish
- * @sa ixAtmdAccRxVcFreeEntriesQuery
- * @sa ixAtmdAccRxVcConnect
- *
- * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call
- * to @a IxAtmdAccRxVcConnect()
- * @param numberOfMbufs unsigned int [in] - threshold number of buffers. This number
- * has to be a power of 2, one of the values 0,1,2,4,8,16,32....
- * The maximum value cannot be more than half of the rxFree queue
- * size (which can be retrieved using @a ixAtmdAccRxVcFreeEntriesQuery()
- * before any use of the @a ixAtmdAccRxVcFreeReplenish() function)
- * @param callback @ref IxAtmdAccRxVcFreeLowCallback [in] - function telling the user that the number of
- * free buffers has reduced to the threshold value.
- *
- * @return @li IX_SUCCESS Threshold set successfully.
- * @return @li IX_FAIL parameter error or the current number of free buffers
- * is less than or equal to the threshold supplied or some
- * unspecified error has occrred.
- *
- * @note - the callback will be called when the threshold level will drop from
- * exactly (numberOfMbufs + 1) to (numberOfMbufs).
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxVcFreeLowCallbackRegister (IxAtmConnId connId,
- unsigned int numberOfMbufs,
- IxAtmdAccRxVcFreeLowCallback callback);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccRxVcFreeEntriesQuery (IxAtmConnId connId,
- unsigned int *numberOfMbufsPtr)
- *
- * @brief Get the number of rx mbufs the system can accept to replenish the
- * the rx reception mechanism on a particular channel
- *
- * The ixAtmdAccRxVcFreeEntriesQuery function is used to retrieve the current
- * number of available mbuf entries for reception, on a per-VC basis. This
- * function can be used to know the number of mbufs which can be provided
- * using @a ixAtmdAccRxVcFreeReplenish().
- *
- * This function can be used from a timer context, or can be associated
- * with a threshold event, or can be used inside an active polling
- * mechanism which is under user control.
- *
- * This function is reentrant and does not use system resources and can
- * be invoked from an interrupt context.
- *
- * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call
- * to @a IxAtmdAccRxVcConnect()
- * @param numberOfMbufsPtr unsigned int [out] - Pointer to the number of available entries.
- * . This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS the current number of mbufs not yet used for incoming traffic
- * @return @li IX_FAIL invalid parameter
- *
- * @sa ixAtmdAccRxVcFreeReplenish
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxVcFreeEntriesQuery (IxAtmConnId connId,
- unsigned int *numberOfMbufsPtr);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccRxVcEnable (IxAtmConnId connId)
- *
- * @brief Start the RX service on a VC.
- *
- * This functions kicks-off the traffic reception for a particular VC.
- * Once invoked, incoming PDUs will be made available by the hardware
- * and are eventually directed to the @a IxAtmdAccRxVcRxCallback() callback
- * registered for the connection.
- *
- * If the traffic is already running, this function returns IX_SUCCESS.
- * This function can be invoked many times.
- *
- * IxAtmdAccRxVcFreeLowCallback event will occur only after
- * @a ixAtmdAccRxVcEnable() function is invoked.
- *
- * Before using this function, the @a ixAtmdAccRxVcFreeReplenish() function
- * has to be used to replenish the RX Free queue. If not, incoming traffic
- * may be discarded.and in the case of interrupt driven reception the
- * @a IxAtmdAccRxVcFreeLowCallback() callback may be invoked as a side effect
- * during a replenish action.
- *
- * This function is not reentrant and should not be used inside an
- * interrupt context.
- *
- * For an VC connection this function can be called after a call to
- * @a ixAtmdAccRxVcDisable() and should not be called after
- * @a ixAtmdAccRxVcTryDisconnect()
- *
- * @sa ixAtmdAccRxVcDisable
- * @sa ixAtmdAccRxVcConnect
- * @sa ixAtmdAccRxVcFreeReplenish
- *
- * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call
- * to @a IxAtmdAccRxVcConnect()
- *
- * @return @li IX_SUCCESS successful call to ixAtmdAccRxVcEnable
- * @return @li IX_ATMDACC_WARNING the channel is already enabled
- * @return @li IX_FAIL invalid parameters or some unspecified internal
- * error occured.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxVcEnable (IxAtmConnId connId);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccRxVcDisable (IxAtmConnId connId)
- *
- * @brief Stop the RX service on a VC.
- *
- * This functions stops the traffic reception for a particular VC connection.
- *
- * Once invoked, incoming Pdus are discarded by the hardware. Any Pdus
- * pending will be freed to the user
- *
- * Hence once this function returns no more receive callbacks will be
- * called for that VC. However, buffer free callbacks will be invoked
- * until such time as all buffers supplied by the user have been freed
- * back to the user
- *
- * Calling this function doe not invalidate the connId.
- * @a ixAtmdAccRxVcEnable() can be invoked to enable Pdu reception again.
- *
- * If the traffic is already stopped, this function returns IX_SUCCESS.
- *
- * This function is not reentrant and should not be used inside an
- * interrupt context.
- *
- * @sa ixAtmdAccRxVcConnect
- * @sa ixAtmdAccRxVcEnable
- * @sa ixAtmdAccRxVcDisable
- *
- * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call to @a
- * IxAtmdAccRxVcConnect()
- *
- * @return @li IX_SUCCESS successful call to @a ixAtmdAccRxVcDisable().
- * @return @li IX_ATMDACC_WARNING the channel is already disabled
- * @return @li IX_FAIL invalid parameters or some unspecified internal error occured
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxVcDisable (IxAtmConnId connId);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccRxVcTryDisconnect (IxAtmConnId connId)
- *
- * @brief Disconnect a VC from the RX service.
- *
- * This function deregisters the VC and guarantees that all resources
- * associated with this VC are free. After its execution, the connection
- * Id is not available.
- *
- * This function will fail until such time as all resources allocated to
- * the VC connection have been freed. The user is responsible to delay and
- * call again this function many times until a success status is returned.
- *
- * This function needs internal locks and should not be called from an
- * interrupt context
- *
- * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call to
- * @a IxAtmdAccRxVcConnect()
- *
- * @return @li IX_SUCCESS successful call to ixAtmdAccRxVcDisable
- * @return @li IX_ATMDACC_RESOURCES_STILL_ALLOCATED not all resources
- * associated with the connection have been freed.
- * @return @li IX_FAIL cannot process this request because of a parameter
- * error
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxVcTryDisconnect (IxAtmConnId connId);
-
-/* ------------------------------------------------------
- Part of the IxAtmdAcc interface related to TX traffic
- ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccTxVcConnect (IxAtmLogicalPort port,
- unsigned int vpi,
- unsigned int vci,
- IxAtmdAccAalType aalServiceType,
- IxAtmdAccUserId userId,
- IxAtmdAccTxVcBufferReturnCallback bufferFreeCallback,
- IxAtmConnId * connIdPtr)
- *
- * @brief Connect to a Aal Pdu transmit service for a particular
- * port/vpi/vci and service type.
- *
- * This function allows a user to connect to an Aal5/Aal0/OAM Pdu transmit service
- * for a particular port/vpi/vci. It registers the callback and allocates
- * internal resources and a Connection Id to be used in further API calls
- * related to this VC.
- *
- * The function will setup VC transmit service on the specified on the
- * specified port. A connId is the reference by which IxAtmdAcc refers to a
- * connected VC. This identifier is the result of a succesful call
- * to a connect function. This identifier is invalid after a
- * sucessful call to a disconnect function.
- *
- * This function needs internal locks, and hence should not be called
- * from an interrupt context.
- *
- * On return from @a ixAtmdAccTxVcConnect() with a failure status, the
- * connection Id parameter is unspecified. Its value cannot be used.
- *
- * Calling this function for the same combination of port, Vpi, Vci and
- * more than once without calling @a ixAtmdAccTxVcTryDisconnect() will result
- * in a failure status.
- *
- * Two AAL0 services supporting 48 or 52 byte cell data are provided.
- * Submitted AAL0 PDUs must be a multiple of the cell data size (48/52).
- * AAL0_52 is a raw cell service the client must format
- * the PDU with an ATM cell header (excluding HEC) at the start of
- * each cell, note that AtmdAcc does not validate the cell headers in
- * a submitted PDU.
- *
- * For the OAM service an "OAM Tx channel" may be enabled for a port
- * by establishing a single dedicated OAM Tx connection on that port.
- *
- * The OAM service allows buffers containing 52 byte OAM F4/F5 cells
- * to be transmitted and received over the dedicated OAM channels.
- * HEC is appended/removed, and CRC-10 performed by the NPE. The OAM
- * service offered by AtmdAcc is a raw cell transport service.
- * It is assumed that ITU I.610 procedures that make use of this
- * service are implemented above AtmdAcc.
- *
- * Note that the dedicated OAM connections are established on
- * reserved VPI,VCI, and (in the case of Rx) port values.
- * These values are used purely to descriminate the dedicated OAM channels
- * and do not identify a particular OAM F4/F5 flow. F4/F5 flows may be
- * realised for particluar VPI/VCIs by manipulating the VPI,VCI
- * fields of the ATM cell headers of cells in the buffers passed
- * to AtmdAcc.
- *
- * Calling this function before enabling the port will fail.
- *
- * @sa ixAtmdAccTxVcTryDisconnect
- * @sa ixAtmdAccPortTxScheduledModeEnable
- * @sa ixAtmdAccPortEnable
- *
- * @param port @ref IxAtmLogicalPort [in] - VC identification : logical PHY port
- * [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- * @param vpi unsigned int [in] - VC identification : ATM Vpi [0..255] or IX_ATMDACC_OAM_VPI
- * @param vci unsigned int [in] - VC identification : ATM Vci [0..65535] or IX_ATMDACC_OAM_VCI
- * @param aalServiceType @ref IxAtmdAccAalType [in] - type of service AAL5, AAL0_48, AAL0_52, or OAM
- * @param userId @ref IxAtmdAccUserId [in] - user id to be used later during callbacks related
- * to this channel
- * @param bufferFreeCallback @ref IxAtmdAccTxVcBufferReturnCallback [in] - function called when mbufs
- * transmission is complete. This parameter cannot be a null
- * pointer.
- * @param connIdPtr @ref IxAtmConnId [out] - Pointer to a connection Id.
- * This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS successful call to @a IxAtmdAccRxVcConnect().
- * @return @li IX_ATMDACC_BUSY cannot process this request
- * because no VC is available
- * @return @li IX_FAIL
- * parameter error,
- * VC already in use,
- * attempt to connect AAL service on reserved OAM VPI/VCI,
- * attempt to connect OAM service on VPI/VCI other than the reserved OAM VPI/VCI,
- * port is not initialised,
- * or some other error occurs during processing.
- *
- * @note - Unscheduled mode is not supported in ixp425 1.0. Therefore, the
- * function @a ixAtmdAccPortTxScheduledModeEnable() need to be called
- * for this port before any establishing a Tx Connection
- */
-PUBLIC IX_STATUS ixAtmdAccTxVcConnect (IxAtmLogicalPort port,
- unsigned int vpi,
- unsigned int vci,
- IxAtmdAccAalType aalServiceType,
- IxAtmdAccUserId userId,
- IxAtmdAccTxVcBufferReturnCallback bufferFreeCallback,
- IxAtmConnId * connIdPtr);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccTxVcPduSubmit (IxAtmConnId connId,
- IX_OSAL_MBUF * mbufPtr,
- IxAtmdAccClpStatus clp,
- unsigned int numberOfCells)
- *
- * @brief Submit a Pdu for transmission on connection.
- *
- * A data user calls this function to submit an mbufs containing a Pdu
- * to be transmitted. The buffer supplied can be chained and the Pdu it
- * contains must be complete.
- *
- * The transmission behavior of this call depends on the operational mode
- * of the port on which the connection is made.
- *
- * In unscheduled mode the mbuf will be submitted to the hardware
- * immediately if sufficent resource is available. Otherwise the function
- * will return failure.
- *
- * In scheduled mode the buffer is queued internally in IxAtmdAcc. The cell
- * demand is made known to the traffic shaping entity. Cells from the
- * buffers are MUXed onto the port some time later as dictated by the
- * traffic shaping entity. The traffic shaping entity does this by sending
- * transmit schedules to IxAtmdAcc via @a ixAtmdAccPortTxProcess() function call.
- *
- * Note that the dedicated OAM channel is scheduled just like any
- * other channel. This means that any OAM traffic relating to an
- * active AAL0/AAL5 connection will be scheduled independantly of the
- * AAL0/AAL5 traffic for that connection.
- *
- * When transmission is complete, the TX Done mechanism will give the
- * owmnership of these buffers back to the customer. The tx done mechanism
- * must be in operation before transmission is attempted.
- *
- * For AAL0/OAM submitted AAL0 PDUs must be a multiple of the cell data
- * size (48/52). AAL0_52 and OAM are raw cell services, and the client
- * must format the PDU with an ATM cell header (excluding HEC) at the
- * start of each cell, note that AtmdAcc does not validate the cell headers in
- * a submitted PDU.
- *
- *
- * @sa IxAtmdAccTxVcBufferReturnCallback
- * @sa ixAtmdAccTxDoneDispatch
- *
- * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call to
- * @a ixAtmdAccTxVcConnect()
- * @param mbufPtr @ref IX_OSAL_MBUF [in] - pointer to a chained structure of mbufs to transmit.
- * This parameter cannot be a null pointer.
- * @param clp @ref IxAtmdAccClpStatus [in] - clp indication for this PDU. All cells of this pdu
- * will be sent with the clp bit set
- * @param numberOfCells unsigned int [in] - number of cells in the PDU.
- *
- * @return @li IX_SUCCESS successful call to @a ixAtmdAccTxVcPduSubmit()
- * The pdu pointed by the mbufPtr parameter will be
- * transmitted
- * @return @li IX_ATMDACC_BUSY unable to process this request because
- * internal resources are all used. The caller is responsible
- * for retrying this request later.
- * @return @li IX_FAIL unable to process this request because of error
- * in the parameters (wrong connId supplied,
- * or wrong mbuf pointer supplied), the total length of all buffers
- * in the chain should be a multiple of the cell size
- * ( 48/52 depending on the service type ),
- * or unspecified error during processing
- *
- * @note - This function in not re-entrant for the same VC (e.g. : two
- * thread cannot send PDUs for the same VC). But two threads can
- * safely call this function with a different connection Id
- *
- * @note - In unscheduled mode, this function is not re-entrant on a per
- * port basis. The size of pdus is limited to 8Kb.
- *
- * @note - 0-length mbufs should be removed from the chain before submission.
- * The total length of the pdu (sdu + padding +trailer) has to be
- * updated in the header of the first mbuf of a chain of mbufs.
- *
- * @note - Aal5 trailer information (UUI, CPI, SDU length) has to be supplied
- * before submission.
- *
- * @note - The payload memory cache should be flushed, if needed, prior to
- * transmission. Mbuf headers are flushed by IxAtmdAcc
- *
- * @note - This function does not use system resources and can be used
- * inside an interrupt context
- */
-PUBLIC IX_STATUS ixAtmdAccTxVcPduSubmit (IxAtmConnId connId,
- IX_OSAL_MBUF * mbufPtr,
- IxAtmdAccClpStatus clp,
- unsigned int numberOfCells);
-
-/**
- *
- * @ingroup IxAtmdAccAPI
- *
- * @fn ixAtmdAccTxVcTryDisconnect (IxAtmConnId connId)
- *
- * @brief Disconnect from a Aal Pdu transmit service for a particular
- * port/vpi/vci.
- *
- * This function deregisters the VC and guarantees that all resources
- * associated with this VC are free. After its execution, the connection
- * Id is not available.
- *
- * This function will fail until such time as all resources allocated to
- * the VC connection have been freed. The user is responsible to delay
- * and call again this function many times until a success status is
- * returned.
- *
- * After its execution, the connection Id is not available.
- *
- * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call to
- * @a ixAtmdAccTxVcConnect()
- *
- * @return @li IX_SUCCESS successful call to @a ixAtmdAccTxVcTryDisconnect()
- * @return @li IX_ATMDACC_RESOURCES_STILL_ALLOCATED not all resources
- * associated with the connection have been freed. This condition will
- * disappear after Tx and TxDone is complete for this channel.
- * @return @li IX_FAIL unable to process this request because of errors
- * in the parameters (wrong connId supplied)
- *
- * @note - This function needs internal locks and should not be called
- * from an interrupt context
- *
- * @note - If the @a IX_ATMDACC_RESOURCES_STILL_ALLOCATED error does not
- * clear after a while, this may be linked to a previous problem
- * of cell overscheduling. Diabling the port and retry a disconnect
- * will free the resources associated with this channel.
- *
- * @sa ixAtmdAccPortTxProcess
- *
- */
-PUBLIC IX_STATUS ixAtmdAccTxVcTryDisconnect (IxAtmConnId connId);
-
-#endif /* IXATMDACC_H */
-
-/**
- * @} defgroup IxAtmdAccAPI
- */
-
-
+++ /dev/null
-
-/**
- * @file IxAtmdAccCtrl.h
- *
- * @date 20-Mar-2002
- *
- * @brief IxAtmdAcc Public API
- *
- * This file contains the public API of IxAtmdAcc, related to the
- * control functions of the component.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-/* ------------------------------------------------------
- Doxygen group definitions
- ------------------------------------------------------ */
-
-/**
- *
- * @defgroup IxAtmdAccCtrlAPI IXP400 ATM Driver Access (IxAtmdAcc) Control API
- *
- * @brief The public API for the IXP400 Atm Driver Control component
- *
- * IxAtmdAcc is the low level interface by which AAL PDU get transmitted
- * to,and received from the Utopia bus
- *
- * This part is related to the Control configuration
- *
- * @{
- */
-
-#ifndef IXATMDACCCTRL_H
-#define IXATMDACCCTRL_H
-
-#include "IxAtmdAcc.h"
-
-/* ------------------------------------------------------
- AtmdAccCtrl Data Types definition
- ------------------------------------------------------ */
-
-/**
-*
-* @ingroup IxAtmdAccCtrlAPI
-*
-* @def IX_ATMDACC_PORT_DISABLE_IN_PROGRESS
-*
-* @brief Port enable return code
-*
-* This constant is used to tell IxAtmDAcc user that the port disable
-* functions are not complete. The user can call ixAtmdAccPortDisableComplete()
-* to find out when the disable has finished. The port enable can then proceed.
-*
-*/
-#define IX_ATMDACC_PORT_DISABLE_IN_PROGRESS 5
-
-/**
-*
-* @ingroup IxAtmdAccCtrlAPI
-*
-* @def IX_ATMDACC_ALLPDUS
-*
-* @brief All PDUs
-*
-* This constant is used to tell IxAtmDAcc to process all PDUs from
-* the RX queue or the TX Done
-*
-* @sa IxAtmdAccRxDispatcher
-* @sa IxAtmdAccTxDoneDispatcher
-*
-*/
-#define IX_ATMDACC_ALLPDUS 0xffffffff
-
-/* ------------------------------------------------------
- Part of the IxAtmdAcc interface related to RX traffic
- ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @brief Callback prototype for notification of available PDUs for
- * an Rx Q.
- *
- * This a protoype for a function which is called when there is at
- * least one Pdu available for processing on a particular Rx Q.
- *
- * This function should call @a ixAtmdAccRxDispatch() with
- * the aprropriate number of parameters to read and process the Rx Q.
- *
- * @sa ixAtmdAccRxDispatch
- * @sa ixAtmdAccRxVcConnect
- * @sa ixAtmdAccRxDispatcherRegister
- *
- * @param rxQueueId @ref IxAtmRxQueueId [in] indicates which RX queue to has Pdus to process.
- * @param numberOfPdusToProcess unsigned int [in] indicates the minimum number of
- * PDUs available to process all PDUs from the queue.
- * @param reservedPtr unsigned int* [out] pointer to a int location which can
- * be written to, but does not retain written values. This is
- * provided to make this prototype compatible
- * with @a ixAtmdAccRxDispatch()
- *
- * @return @li int - ignored.
- *
- */
-typedef IX_STATUS (*IxAtmdAccRxDispatcher) (IxAtmRxQueueId rxQueueId,
- unsigned int numberOfPdusToProcess,
- unsigned int *reservedPtr);
-
-/* ------------------------------------------------------
- Part of the IxAtmdAcc interface related to TX traffic
- ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @brief Callback prototype for transmitted mbuf when threshold level is
- * crossed.
- *
- * IxAtmdAccTxDoneDispatcher is the prototype of the user function
- * which get called when pdus are completely transmitted. This function
- * is likely to call the @a ixAtmdAccTxDoneDispatch() function.
- *
- * This function is called when the number of available pdus for
- * reception is crossing the threshold level as defined
- * in @a ixAtmdAccTxDoneDispatcherRegister()
- *
- * This function is called inside an Qmgr dispatch context. No system
- * resource or interrupt-unsafe feature should be used inside this
- * callback.
- *
- * Transmitted buffers recycling implementation is a sytem-wide mechanism
- * and needs to be set before any traffic is started. If this threshold
- * mechanism is not used, the user is responsible for polling the
- * transmitted buffers with @a ixAtmdAccTxDoneDispatch()
- * and @a ixAtmdAccTxDoneLevelQuery() functions.
- *
- * @sa ixAtmdAccTxDoneDispatcherRegister
- * @sa ixAtmdAccTxDoneDispatch
- * @sa ixAtmdAccTxDoneLevelQuery
- *
- * @param numberOfPdusToProcess unsigned int [in] - The current number of pdus currently
- * available for recycling
- * @param *reservedPtr unsigned int [out] - pointer to a int location which can be
- * written to but does not retain written values. This is provided
- * to make this prototype compatible
- * with @a ixAtmdAccTxDoneDispatch()
- *
- * @return @li IX_SUCCESS This is provided to make
- * this prototype compatible with @a ixAtmdAccTxDoneDispatch()
- * @return @li IX_FAIL invalid parameters or some unspecified internal
- * error occured. This is provided to make
- * this prototype compatible with @a ixAtmdAccTxDoneDispatch()
- *
- */
-typedef IX_STATUS (*IxAtmdAccTxDoneDispatcher) (unsigned int numberOfPdusToProcess,
- unsigned int *reservedPtr);
-
-/**
-*
-* @ingroup IxAtmdAccCtrlAPI
-*
-* @brief Notification that the threshold number of scheduled cells
-* remains in a port's transmit Q.
-*
-* The is the prototype for of the user notification function which
-* gets called on a per-port basis, when the number of remaining
-* scheduled cells to be transmitted decreases to the threshold level.
-* The number of cells passed as a parameter can be used for scheduling
-* purposes as the maximum number of cells that can be passed in a
-* schedule table to the @a ixAtmdAccPortTxProcess() function.
-*
-* @sa ixAtmdAccPortTxCallbackRegister
-* @sa ixAtmdAccPortTxProcess
-* @sa ixAtmdAccPortTxFreeEntriesQuery
-*
-* @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
-* @param numberOfAvailableCells unsigned int [in] - number of available
-* cell entries.for the port
-*
-* @note - This functions shall not use system resources when used
-* inside an interrupt context.
-*
-*/
-typedef void (*IxAtmdAccPortTxLowCallback) (IxAtmLogicalPort port,
- unsigned int numberOfAvailableCells);
-
-/**
-*
-* @ingroup IxAtmdAccCtrlAPI
-*
-* @brief Prototype to submit cells for transmission
-*
-* IxAtmdAccTxVcDemandUpdateCallback is the prototype of the callback
-* function used by AtmD to notify an ATM Scheduler that the user of
-* a VC has submitted cells for transmission.
-*
-* @sa IxAtmdAccTxVcDemandUpdateCallback
-* @sa IxAtmdAccTxVcDemandClearCallback
-* @sa IxAtmdAccTxSchVcIdGetCallback
-* @sa ixAtmdAccPortTxScheduledModeEnable
-*
-* @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be updated
-* is established
-* @param vcId int [in] - Identifies the VC to be updated. This is the value
-* returned by the @a IxAtmdAccTxSchVcIdGetCallback() call .
-* @param numberOfCells unsigned int [in] - Indicates how many ATM cells should be added
-* to the queue for this VC.
-*
-* @return @li IX_SUCCESS the function is registering the cell demand for
-* this VC.
-* @return @li IX_FAIL the function cannot register cell for this VC : the
-* scheduler maybe overloaded or misconfigured
-*
-*/
-typedef IX_STATUS (*IxAtmdAccTxVcDemandUpdateCallback) (IxAtmLogicalPort port,
- int vcId,
- unsigned int numberOfCells);
-
-/**
-*
-* @ingroup IxAtmdAccCtrlAPI
-*
-* @brief prototype to remove all currently queued cells from a
-* registered VC
-*
-* IxAtmdAccTxVcDemandClearCallback is the prototype of the function
-* to remove all currently queued cells from a registered VC. The
-* pending cell count for the specified VC is reset to zero. After the
-* use of this callback, the scheduler shall not schedule more cells
-* for this VC.
-*
-* This callback function is called during a VC disconnection
-* @a ixAtmdAccTxVcTryDisconnect()
-*
-* @sa IxAtmdAccTxVcDemandUpdateCallback
-* @sa IxAtmdAccTxVcDemandClearCallback
-* @sa IxAtmdAccTxSchVcIdGetCallback
-* @sa ixAtmdAccPortTxScheduledModeEnable
-* @sa ixAtmdAccTxVcTryDisconnect
-*
-* @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be cleared
-* is established
-* @param vcId int [in] - Identifies the VC to be cleared. This is the value
-* returned by the @a IxAtmdAccTxSchVcIdGetCallback() call .
-*
-* @return none
-*
-*/
-typedef void (*IxAtmdAccTxVcDemandClearCallback) (IxAtmLogicalPort port,
- int vcId);
-
-/**
-*
-* @ingroup IxAtmdAccCtrlAPI
-*
-* @brief prototype to get a scheduler vc id
-*
-* IxAtmdAccTxSchVcIdGetCallback is the prototype of the function to get
-* a scheduler vcId
-*
-* @sa IxAtmdAccTxVcDemandUpdateCallback
-* @sa IxAtmdAccTxVcDemandClearCallback
-* @sa IxAtmdAccTxSchVcIdGetCallback
-* @sa ixAtmdAccPortTxScheduledModeEnable
-*
-* @param port @ref IxAtmLogicalPort [in] - Specifies the ATM logical port on which the VC is
-* established
-* @param vpi unsigned int [in] - For AAL0/AAL5 specifies the ATM vpi on which the
-* VC is established.
-* For OAM specifies the dedicated "OAM Tx channel" VPI.
-* @param vci unsigned int [in] - For AAL0/AAL5 specifies the ATM vci on which the
-* VC is established.
-* For OAM specifies the dedicated "OAM Tx channel" VCI.
-* @param connId @ref IxAtmConnId [in] - specifies the IxAtmdAcc connection Id already
-* associated with this VC
-* @param vcId int* [out] - pointer to a vcId
-*
-* @return @li IX_SUCCESS the function is returning a Scheduler vcId for this
-* VC
-* @return @li IX_FAIL the function cannot process scheduling for this VC.
-* the contents of vcId is unspecified
-*
-*/
-typedef IX_STATUS (*IxAtmdAccTxSchVcIdGetCallback) (IxAtmLogicalPort port,
- unsigned int vpi,
- unsigned int vci,
- IxAtmConnId connId,
- int *vcId);
-
-/* ------------------------------------------------------
- Part of the IxAtmdAcc interface related to RX traffic
- ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccRxDispatcherRegister (
- IxAtmRxQueueId queueId,
- IxAtmdAccRxDispatcher callback)
- *
- * @brief Register a notification callback to be invoked when there is
- * at least one entry on a particular Rx queue.
- *
- * This function registers a callback to be invoked when there is at
- * least one entry in a particular queue. The registered callback is
- * called every time when the hardware adds one or more pdus to the
- * specified Rx queue.
- *
- * This function cannot be used when a Rx Vc using this queue is
- * already existing.
- *
- * @note -The callback function can be the API function
- * @a ixAtmdAccRxDispatch() : every time the threhold level
- * of the queue is reached, the ixAtmdAccRxDispatch() is
- * invoked to remove all entries from the queue.
- *
- * @sa ixAtmdAccRxDispatch
- * @sa IxAtmdAccRxDispatcher
- *
- * @param queueId @ref IxAtmRxQueueId [in] RX queue identification
- * @param callback @ref IxAtmdAccRxDispatcher [in] function triggering the delivery of incoming
- * traffic. This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS Successful call to @a ixAtmdAccRxDispatcherRegister()
- * @return @li IX_FAIL error in the parameters, or there is an
- * already active RX VC for this queue or some unspecified
- * internal error occurred.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxDispatcherRegister (
- IxAtmRxQueueId queueId,
- IxAtmdAccRxDispatcher callback);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccRxDispatch (IxAtmRxQueueId rxQueueId,
- unsigned int numberOfPdusToProcess,
- unsigned int *numberOfPdusProcessedPtr)
- *
- *
- * @brief Control function which executes Rx processing for a particular
- * Rx stream.
- *
- * The @a IxAtmdAccRxDispatch() function is used to process received Pdus
- * available from one of the two incoming RX streams. When this function
- * is invoked, the incoming traffic (up to the number of PDUs passed as
- * a parameter) will be transferred to the IxAtmdAcc users through the
- * callback @a IxAtmdAccRxVcRxCallback(), as registered during the
- * @a ixAtmdAccRxVcConnect() call.
- *
- * The user receive callbacks will be executed in the context of this
- * function.
- *
- * Failing to use this function on a regular basis when there is traffic
- * will block incoming traffic and can result in Pdus being dropped by
- * the hardware.
- *
- * This should be used to control when received pdus are handed off from
- * the hardware to Aal users from a particluar stream. The function can
- * be used from a timer context, or can be registered as a callback in
- * response to an rx stream threshold event, or can be used inside an
- * active polling mechanism which is under user control.
- *
- * @note - The signature of this function is directly compatible with the
- * callback prototype which can be register with @a ixAtmdAccRxDispatcherRegister().
- *
- * @sa ixAtmdAccRxDispatcherRegister
- * @sa IxAtmdAccRxVcRxCallback
- * @sa ixAtmdAccRxVcFreeEntriesQuery
- *
- * @param rxQueueId @ref IxAtmRxQueueId [in] - indicates which RX queue to process.
- * @param numberOfPdusToProcess unsigned int [in] - indicates the maxiumum number of PDU to
- * remove from the RX queue. A value of IX_ATMDACC_ALLPDUS indicates
- * to process all PDUs from the queue. This includes at least the PDUs
- * in the queue when the fuction is invoked. Because of real-time
- * constraints, there is no guarantee thatthe queue will be empty
- * when the function exits. If this parameter is greater than the
- * number of entries of the queues, the function will succeed
- * and the parameter numberOfPdusProcessedPtr will reflect the exact
- * number of PDUs processed.
- * @param *numberOfPdusProcessedPtr unsigned int [out] - indicates the actual number of PDU
- * processed during this call. This parameter cannot be a null
- * pointer.
- *
- * @return @li IX_SUCCESS the number of PDUs as indicated in
- * numberOfPdusProcessedPtr are removed from the RX queue and the VC callback
- * are called.
- * @return @li IX_FAIL invalid parameters or some unspecified internal
- * error occured.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxDispatch (IxAtmRxQueueId rxQueueId,
- unsigned int numberOfPdusToProcess,
- unsigned int *numberOfPdusProcessedPtr);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccRxLevelQuery (IxAtmRxQueueId rxQueueId,
- unsigned int *numberOfPdusPtr)
- *
- * @brief Query the number of entries in a particular RX queue.
- *
- * This function is used to retrieve the number of pdus received by
- * the hardware and ready for distribution to users.
- *
- * @param rxQueueId @ref IxAtmRxQueueId [in] - indicates which of two RX queues to query.
- * @param numberOfPdusPtr unsigned int* [out] - Pointer to store the number of available
- * PDUs in the RX queue. This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS the value in numberOfPdusPtr specifies the
- * number of incoming pdus waiting in this queue
- * @return @li IX_FAIL an error occurs during processing.
- * The value in numberOfPdusPtr is unspecified.
- *
- * @note - This function is reentrant, doesn't use system resources
- * and can be used from an interrupt context.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxLevelQuery (IxAtmRxQueueId rxQueueId,
- unsigned int *numberOfPdusPtr);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccRxQueueSizeQuery (IxAtmRxQueueId rxQueueId,
- unsigned int *numberOfPdusPtr)
- *
- * @brief Query the size of a particular RX queue.
- *
- * This function is used to retrieve the number of pdus the system is
- * able to queue when reception is complete.
- *
- * @param rxQueueId @ref IxAtmRxQueueId [in] - indicates which of two RX queues to query.
- * @param numberOfPdusPtr unsigned int* [out] - Pointer to store the number of pdus
- * the system is able to queue in the RX queue. This parameter
- * cannot be a null pointer.
- *
- * @return @li IX_SUCCESS the value in numberOfPdusPtr specifies the
- * number of pdus the system is able to queue.
- * @return @li IX_FAIL an error occurs during processing.
- * The value in numberOfPdusPtr is unspecified.
- *
- * @note - This function is reentrant, doesn't use system resources
- * and can be used from an interrupt context.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccRxQueueSizeQuery (IxAtmRxQueueId rxQueueId,
- unsigned int *numberOfPdusPtr);
-
-/* ------------------------------------------------------
- Part of the IxAtmdAcc interface related to TX traffic
- ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccPortTxFreeEntriesQuery (IxAtmLogicalPort port,
- unsigned int *numberOfCellsPtr)
- *
- * @brief Get the number of available cells the system can accept for
- * transmission.
- *
- * The function is used to retrieve the number of cells that can be
- * queued for transmission to the hardware.
- *
- * This number is based on the worst schedule table where one cell
- * is stored in one schedule table entry, depending on the pdus size
- * and mbuf size and fragmentation.
- *
- * This function doesn't use system resources and can be used from a
- * timer context, or can be associated with a threshold event, or can
- * be used inside an active polling mechanism
- *
- * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- * @param numberOfCellsPtr unsigned int* [out] - number of available cells.
- * This parameter cannot be a null pointer.
- *
- * @sa ixAtmdAccPortTxProcess
- *
- * @return @li IX_SUCCESS numberOfCellsPtr contains the number of cells that can be scheduled
- * for this port.
- * @return @li IX_FAIL error in the parameters, or some processing error
- * occured.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccPortTxFreeEntriesQuery (IxAtmLogicalPort port,
- unsigned int *numberOfCellsPtr);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccPortTxCallbackRegister (IxAtmLogicalPort port,
- unsigned int numberOfCells,
- IxAtmdAccPortTxLowCallback callback)
- *
- * @brief Configure the Tx port threshold value and register a callback to handle
- * threshold notifications.
- *
- * This function sets the threshold in cells
- *
- * @sa ixAtmdAccPortTxCallbackRegister
- * @sa ixAtmdAccPortTxProcess
- * @sa ixAtmdAccPortTxFreeEntriesQuery
- *
- * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- * @param numberOfCells unsigned int [in] - threshold value which triggers the callback
- * invocation, This number has to be one of the
- * values 0,1,2,4,8,16,32 ....
- * The maximum value cannot be more than half of the txVc queue
- * size (which can be retrieved using @a ixAtmdAccPortTxFreeEntriesQuery()
- * before any Tx traffic is sent for this port)
- * @param callback @ref IxAtmdAccPortTxLowCallback [in] - callback function to invoke when the threshold
- * level is reached.
- * This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS Successful call to @a ixAtmdAccPortTxCallbackRegister()
- * @return @li IX_FAIL error in the parameters, Tx channel already set for this port
- * threshold level is not correct or within the range regarding the
- * queue size:or unspecified error during processing:
- *
- * @note - This callback function get called when the threshold level drops from
- * (numberOfCells+1) cells to (numberOfCells) cells
- *
- * @note - This function should be called during system initialisation,
- * outside an interrupt context
- *
- */
-PUBLIC IX_STATUS ixAtmdAccPortTxCallbackRegister (IxAtmLogicalPort port,
- unsigned int numberOfCells,
- IxAtmdAccPortTxLowCallback callback);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccPortTxScheduledModeEnable (IxAtmLogicalPort port,
- IxAtmdAccTxVcDemandUpdateCallback vcDemandUpdateCallback,
- IxAtmdAccTxVcDemandClearCallback vcDemandClearCallback,
- IxAtmdAccTxSchVcIdGetCallback vcIdGetCallback)
- *
- * @brief Put the port into Scheduled Mode
- *
- * This function puts the specified port into scheduled mode of
- * transmission which means an external s/w entity controls the
- * transmission of cells on this port. This faciltates traffic shaping on
- * the port.
- *
- * Any buffers submitted on a VC for this port will be queued in IxAtmdAcc.
- * The transmission of these buffers to and by the hardware will be driven
- * by a transmit schedule submitted regulary in calls to
- * @a ixAtmdAccPortTxProcess() by traffic shaping entity.
- *
- * The transmit schedule is expected to be dynamic in nature based on
- * the demand in cells for each VC on the port. Hence the callback
- * parameters provided to this function allow IxAtmdAcc to inform the
- * shaping entity of demand changes for each VC on the port.
- *
- * By default a port is in Unscheduled Mode so if this function is not
- * called, transmission of data is done without sheduling rules, on a
- * first-come, first-out basis.
- *
- * Once a port is put in scheduled mode it cannot be reverted to
- * un-scheduled mode. Note that unscheduled mode is not supported
- * in ixp425 1.0
- *
- * @note - This function should be called before any VCs have be
- * connected on a port. Otherwise this function call will return failure.
- *
- * @note - This function uses internal locks and should not be called from
- * an interrupt context
- *
- * @sa IxAtmdAccTxVcDemandUpdateCallback
- * @sa IxAtmdAccTxVcDemandClearCallback
- * @sa IxAtmdAccTxSchVcIdGetCallback
- * @sa ixAtmdAccPortTxProcess
- *
- * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- * @param vcDemandUpdateCallback @ref IxAtmdAccTxVcDemandUpdateCallback [in] - callback function used to update
- * the number of outstanding cells for transmission. This parameter
- * cannot be a null pointer.
- * @param vcDemandClearCallback @ref IxAtmdAccTxVcDemandClearCallback [in] - callback function used to remove all
- * clear the number of outstanding cells for a VC. This parameter
- * cannot be a null pointer.
- * @param vcIdGetCallback @ref IxAtmdAccTxSchVcIdGetCallback [in] - callback function used to exchange vc
- * Identifiers between IxAtmdAcc and the entity supplying the
- * transmit schedule. This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS scheduler registration is complete and the port
- * is now in scheduled mode.
- * @return @li IX_FAIL failed (wrong parameters, or traffic is already
- * enabled on this port, possibly without ATM shaping)
- *
- */
-PUBLIC IX_STATUS ixAtmdAccPortTxScheduledModeEnable (IxAtmLogicalPort port,
- IxAtmdAccTxVcDemandUpdateCallback vcDemandUpdateCallback,
- IxAtmdAccTxVcDemandClearCallback vcDemandClearCallback,
- IxAtmdAccTxSchVcIdGetCallback vcIdGetCallback);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccPortTxProcess (IxAtmLogicalPort port,
- IxAtmScheduleTable* scheduleTablePtr)
- *
- * @brief Transmit queue cells to the H/W based on the supplied schedule
- * table.
- *
- * This function @a ixAtmdAccPortTxProcess() process the schedule
- * table provided as a parameter to the function. As a result cells are
- * sent to the underlaying hardware for transmission.
- *
- * The schedule table is executed in its entirety or not at all. So the
- * onus is on the caller not to submit a table containing more cells than
- * can be transmitted at that point. The maximum numbers that can be
- * transmitted is guaranteed to be the number of cells as returned by the
- * function @a ixAtmdAccPortTxFreeEntriesQuery().
- *
- * When the scheduler is invoked on a threshold level, IxAtmdAcc gives the
- * minimum number of cells (to ensure the callback will fire again later)
- * and the maximum number of cells that @a ixAtmdAccPortTxProcess()
- * will be able to process (assuming the ATM scheduler is able
- * to produce the worst-case schedule table, i.e. one entry per cell).
- *
- * When invoked ouside a threshold level, the overall number of cells of
- * the schedule table should be less than the number of cells returned
- * by the @a ixAtmdAccPortTxFreeEntriesQuery() function.
- *
- * After invoking the @a ixAtmdAccPortTxProcess() function, it is the
- * user choice to query again the queue level with the function
- * @a ixAtmdAccPortTxFreeEntriesQuery() and, depending on a new cell
- * number, submit an other schedule table.
- *
- * IxAtmdAcc will check that the number of cells in the schedule table
- * is compatible with the current transmit level. If the
- *
- * Obsolete or invalid connection Id will be silently discarded.
- *
- * This function is not reentrant for the same port.
- *
- * This functions doesn't use system resources and can be used inside an
- * interrupt context.
- *
- * This function is used as a response to the hardware requesting more
- * cells to transmit.
- *
- * @sa ixAtmdAccPortTxScheduledModeEnable
- * @sa ixAtmdAccPortTxFreeEntriesQuery
- * @sa ixAtmdAccPortTxCallbackRegister
- * @sa ixAtmdAccPortEnable
- *
- * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- * @param scheduleTablePtr @ref IxAtmScheduleTable* [in] - pointer to a scheduler update table. The
- * content of this table is not modified by this function. This
- * parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS the schedule table process is complete
- * and cells are transmitted to the hardware
- * @return @li IX_ATMDACC_WARNING : Traffic will be dropped: the schedule table exceed
- * the hardware capacity If this error is ignored, further traffic
- * and schedule will work correctly.
- * Overscheduling does not occur when the schedule table does
- * not contain more entries that the number of free entries returned
- * by @a ixAtmdAccPortTxFreeEntriesQuery().
- * However, Disconnect attempts just after this error will fail permanently
- * with the error code @a IX_ATMDACC_RESOURCES_STILL_ALLOCATED, and it is
- * necessary to disable the port to make @a ixAtmdAccTxVcTryDisconnect()
- * successful.
- * @return @li IX_FAIL a wrong parameter is supplied, or the format of
- * the schedule table is invalid, or the port is not Enabled, or
- * an internal severe error occured. No cells is transmitted to the hardware
- *
- * @note - If the failure is linked to an overschedule of data cells
- * the result is an inconsistency in the output traffic (one or many
- * cells may be missing and the traffic contract is not respected).
- *
- */
-PUBLIC IX_STATUS ixAtmdAccPortTxProcess (IxAtmLogicalPort port,
- IxAtmScheduleTable* scheduleTablePtr);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccTxDoneDispatch (unsigned int numberOfPdusToProcess,
- unsigned int *numberOfPdusProcessedPtr)
- *
- * @brief Process a number of pending transmit done pdus from the hardware.
- *
- * As a by-product of Atm transmit operation buffers which transmission
- * is complete need to be recycled to users. This function is invoked
- * to service the oustanding list of transmitted buffers and pass them
- * to VC users.
- *
- * Users are handed back pdus by invoking the free callback registered
- * during the @a ixAtmdAccTxVcConnect() call.
- *
- * There is a single Tx done stream servicing all active Atm Tx ports
- * which can contain a maximum of 64 entries. If this stream fills port
- * transmission will stop so this function must be call sufficently
- * frequently to ensure no disruption to the transmit operation.
- *
- * This function can be used from a timer context, or can be associated
- * with a TxDone level threshold event (see @a ixAtmdAccTxDoneDispatcherRegister() ),
- * or can be used inside an active polling mechanism under user control.
- *
- * For ease of use the signature of this function is compatible with the
- * TxDone threshold event callback prototype.
- *
- * This functions can be used inside an interrupt context.
- *
- * @sa ixAtmdAccTxDoneDispatcherRegister
- * @sa IxAtmdAccTxVcBufferReturnCallback
- * @sa ixAtmdAccTxDoneLevelQuery
- *
- * @param numberOfPdusToProcess unsigned int [in] - maxiumum number of pdus to remove
- * from the TX Done queue
- * @param *numberOfPdusProcessedPtr unsigned int [out] - number of pdus removed from
- * the TX Done queue. This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS the number of pdus as indicated in
- * numberOfPdusToProcess are removed from the TX Done hardware
- * and passed to the user through the Tx Done callback registered
- * during a call to @a ixAtmdAccTxVcConnect()
- * @return @li IX_FAIL invalid parameters or numberOfPdusProcessedPtr is
- * a null pointer or some unspecified internal error occured.
- *
- */
-PUBLIC IX_STATUS
-ixAtmdAccTxDoneDispatch (unsigned int numberOfPdusToProcess,
- unsigned int *numberOfPdusProcessedPtr);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccTxDoneLevelQuery (unsigned int *numberOfPdusPtr)
- *
- * @brief Query the current number of transmit pdus ready for
- * recycling.
- *
- * This function is used to get the number of transmitted pdus which
- * the hardware is ready to hand back to user.
- *
- * This function can be used from a timer context, or can be associated
- * with a threshold event, on can be used inside an active polling
- * mechanism
- *
- * @sa ixAtmdAccTxDoneDispatch
- *
- * @param *numberOfPdusPtr unsigned int [out] - Pointer to the number of pdus transmitted
- * at the time of this function call, and ready for recycling
- * This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS numberOfPdusPtr contains the number of pdus
- * ready for recycling at the time of this function call
- *
- * @return @li IX_FAIL wrong parameter (null pointer as parameter).or
- * unspecified rocessing error occurs..The value in numberOfPdusPtr
- * is unspecified.
- *
- */
-PUBLIC IX_STATUS
-ixAtmdAccTxDoneLevelQuery (unsigned int *numberOfPdusPtr);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccTxDoneQueueSizeQuery (unsigned int *numberOfPdusPtr)
- *
- * @brief Query the TxDone queue size.
- *
- * This function is used to get the number of pdus which
- * the hardware is able to store after transmission is complete
- *
- * The returned value can be used to set a threshold and enable
- * a callback to be notified when the number of pdus is going over
- * the threshold.
- *
- * @sa ixAtmdAccTxDoneDispatcherRegister
- *
- * @param *numberOfPdusPtr unsigned int [out] - Pointer to the number of pdus the system
- * is able to queue after transmission
- *
- * @return @li IX_SUCCESS numberOfPdusPtr contains the the number of
- * pdus the system is able to queue after transmission
- * @return @li IX_FAIL wrong parameter (null pointer as parameter).or
- * unspecified rocessing error occurs..The value in numberOfPdusPtr
- * is unspecified.
- *
- * @note - This function is reentrant, doesn't use system resources
- * and can be used from an interrupt context.
- */
-PUBLIC IX_STATUS
-ixAtmdAccTxDoneQueueSizeQuery (unsigned int *numberOfPdusPtr);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccTxDoneDispatcherRegister (unsigned int numberOfPdus,
- IxAtmdAccTxDoneDispatcher notificationCallback)
- *
- * @brief Configure the Tx Done stream threshold value and register a
- * callback to handle threshold notifications.
- *
- * This function sets the threshold level in term of number of pdus at
- * which the supplied notification function should be called.
- *
- * The higher the threshold value is, the less events will be necessary
- * to process transmitted buffers.
- *
- * Transmitted buffers recycling implementation is a sytem-wide mechanism
- * and needs to be set prior any traffic is started. If this threshold
- * mechanism is not used, the user is responsible for polling the
- * transmitted buffers thanks to @a ixAtmdAccTxDoneDispatch() and
- * @a ixAtmdAccTxDoneLevelQuery() functions.
- *
- * This function should be called during system initialisation outside
- * an interrupt context
- *
- * @sa ixAtmdAccTxDoneDispatcherRegister
- * @sa ixAtmdAccTxDoneDispatch
- * @sa ixAtmdAccTxDoneLevelQuery
- *
- * @param numberOfPdus unsigned int [in] - The number of TxDone pdus which triggers the
- * callback invocation This number has to be a power of 2, one of the
- * values 0,1,2,4,8,16,32 ...
- * The maximum value cannot be more than half of the txDone queue
- * size (which can be retrieved using @a ixAtmdAccTxDoneQueueSizeQuery())
- * @param notificationCallback @ref IxAtmdAccTxDoneDispatcher [in] - The function to invoke. (This
- * parameter can be @a ixAtmdAccTxDoneDispatch()).This
- * parameter ust not be a null pointer.
- *
- * @return @li IX_SUCCESS Successful call to ixAtmdAccTxDoneDispatcherRegister
- * @return @li IX_FAIL error in the parameters:
- *
- * @note - The notificationCallback will be called exactly when the threshold level
- * will increase from (numberOfPdus) to (numberOfPdus+1)
- *
- * @note - If there is no Tx traffic, there is no guarantee that TxDone Pdus will
- * be released to the user (when txDone level is permanently under the threshold
- * level. One of the preffered way to return resources to the user is to use
- * a mix of txDone notifications, used together with a slow
- * rate timer and an exclusion mechanism protecting from re-entrancy
- *
- * @note - The TxDone threshold will only hand back buffers when the threshold level is
- * crossed. Setting this threshold to a great number reduce the interrupt rate
- * and the cpu load, but also increase the number of outstanding mbufs and has
- * a system wide impact when these mbufs are needed by other components.
- *
- */
-PUBLIC IX_STATUS ixAtmdAccTxDoneDispatcherRegister (unsigned int numberOfPdus,
- IxAtmdAccTxDoneDispatcher notificationCallback);
-
-/* ------------------------------------------------------
- Part of the IxAtmdAcc interface related to Utopia config
- ------------------------------------------------------ */
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @defgroup IxAtmdAccUtopiaCtrlAPI IXP400 ATM Driver Access (IxAtmdAcc) Utopia Control API
- *
- * @brief The public API for the IXP400 Atm Driver Control component
- *
- * IxAtmdAcc is the low level interface by which AAL PDU get
- * transmitted to,and received from the Utopia bus
- *
- * This part is related to the UTOPIA configuration.
- *
- * @{
- */
-
-/**
- *
- * @brief Utopia configuration
- *
- * This structure is used to set the Utopia parameters
- * @li contains the values of Utopia registers, to be set during initialisation
- * @li contains debug commands for NPE, to be used during development steps
- *
- * @note - the exact description of all parameters is done in the Utopia reference
- * documents.
- *
- */
-typedef struct
-{
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtTxConfig_
- * @brief Utopia Tx Config Register
- */
- struct UtTxConfig_
- {
-
- unsigned int reserved_1:1; /**< [31] These bits are always 0.*/
- unsigned int txInterface:1; /**< [30] Utopia Transmit Interface. The following encoding
- * is used to set the Utopia Transmit interface as ATM master
- * or PHY slave:
- * @li 1 - PHY
- * @li 0 - ATM
- */
- unsigned int txMode:1; /**< [29] Utopia Transmit Mode. The following encoding is used
- * to set the Utopia Transmit mode to SPHY or MPHY:
- * @li 1 - SPHY
- * @li 0 - MPHY
- */
- unsigned int txOctet:1; /**< [28] Utopia Transmit cell transfer protocol. Used to set
- * the Utopia cell transfer protocol to Octet-level handshaking.
- * Note this is only applicable in SPHY mode.
- * @li 1 - Octet-handshaking enabled
- * @li 0 - Cell-handshaking enabled
- */
- unsigned int txParity:1; /**< [27] Utopia Transmit parity enabled when set. TxEvenParity
- * defines the parity format odd/even.
- * @li 1 - Enable Parity generation.
- * @li 0 - ut_op_prty held low.
- */
- unsigned int txEvenParity:1; /**< [26] Utopia Transmit Parity Mode
- * @li 1 - Even Parity Generated.
- * @li 0 - Odd Parity Generated.
- */
- unsigned int txHEC:1; /**< [25] Header Error Check Insertion Mode. Specifies if the transmit
- * cell header check byte is calculated and inserted when set.
- * @li 1 - Generate HEC.
- * @li 0 - Disable HEC generation.
- */
- unsigned int txCOSET:1; /**< [24] If enabled the HEC is Exclusive-ORÆed with the value 0x55 before
- * being presented on the Utopia bus.
- * @li 1 - Enable HEC ExOR with value 0x55
- * @li 0 - Use generated HEC value.
- */
-
- unsigned int reserved_2:1; /**< [23] These bits are always 0
- */
- unsigned int txCellSize:7; /**< [22:16] Transmit expected cell size. Configures the cell size
- * for the transmit module: Values between 52-64 are valid.
- */
- unsigned int reserved_3:3; /**< [15:13] These bits are always 0 */
- unsigned int txAddrRange:5; /**< [12:8] When configured as an ATM master in MPHY mode this
- * register specifies the upper limit of the PHY polling logical
- * range. The number of active PHYs are TxAddrRange + 1.
- */
- unsigned int reserved_4:3; /**< [7:5] These bits are always 0 */
- unsigned int txPHYAddr:5; /**< [4:0] When configured as a slave in an MPHY system this register
- * specifies the physical address of the PHY.
- */
- }
-
- utTxConfig; /**< Tx config Utopia register */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtTxStatsConfig_
- * @brief Utopia Tx stats Register
- */
- struct UtTxStatsConfig_
- {
-
- unsigned int vpi:12; /**< [31:20] ATM VPI [11:0] OR GFC [3:0] and VPI [7:0]
- @li Note: if VCStatsTxGFC is set to 0 the GFC field is ignored in test. */
-
- unsigned int vci:16; /**< [19:4] ATM VCI [15:0] or PHY Address[4] */
-
- unsigned int pti:3; /**< [3:1] ATM PTI [2:0] or PHY Address[3:1]
- @li Note: if VCStatsTxPTI is set to 0 the PTI field is ignored in test.
- @li Note: if VCStatsTxEnb is set to 0 only the transmit PHY port
- address as defined by this register is used for ATM statistics [4:0]. */
-
- unsigned int clp:1; /**< [0] ATM CLP or PHY Address [0]
- @li Note: if VCStatsTxCLP is set to 0 the CLP field is ignored in test.
- @li Note: if VCStatsTxEnb is set to 0 only the transmit PHY port
- address as defined by this register is used for ATM statistics [4:0]. */
- }
-
- utTxStatsConfig; /**< Tx stats config Utopia register */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtTxDefineIdle_
- * @brief Utopia Tx idle cells Register
- */
- struct UtTxDefineIdle_
- {
-
- unsigned int vpi:12; /**< [31:20] ATM VPI [11:0] OR GFC [3:0] and VPI [7:0]
- @li Note: if VCIdleTxGFC is set to 0 the GFC field is ignored in test. */
-
- unsigned int vci:16; /**< [19:4] ATM VCI [15:0] */
-
- unsigned int pti:3; /**< [3:1] ATM PTI PTI [2:0]
- @li Note: if VCIdleTxPTI is set to 0 the PTI field is ignored in test.*/
-
- unsigned int clp:1; /**< [0] ATM CLP [0]
- @li Note: if VCIdleTxCLP is set to 0 the CLP field is ignored in test.*/
- }
-
- utTxDefineIdle; /**< Tx idle cell config Utopia register */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtTxEnableFields_
- * @brief Utopia Tx ienable fields Register
- */
- struct UtTxEnableFields_
- {
-
- unsigned int defineTxIdleGFC:1; /**< [31] This register is used to include or exclude the GFC
- field of the ATM header when testing for Idle cells.
- @li 1 - GFC field is valid.
- @li 0 - GFC field ignored.*/
-
- unsigned int defineTxIdlePTI:1; /**< [30] This register is used to include or exclude the PTI
- field of the ATM header when testing for Idle cells.
- @li 1 - PTI field is valid
- @li 0 - PTI field ignored.*/
-
- unsigned int defineTxIdleCLP:1; /**< [29] This register is used to include or
- exclude the CLP field of the ATM header when testing for Idle cells.
- @li 1 - CLP field is valid.
- @li 0 - CLP field ignored. */
-
- unsigned int phyStatsTxEnb:1; /**< [28] This register is used to enable or disable ATM
- statistics gathering based on the specified PHY address as defined
- in TxStatsConfig register.
- @li 1 - Enable statistics for specified transmit PHY address.
- @li 0 - Disable statistics for specified transmit PHY address. */
-
- unsigned int vcStatsTxEnb:1; /**< [27] This register is used to change the ATM
- statistics-gathering mode from the specified logical PHY address
- to a specific VPI/VCI address.
- @li 1 - Enable statistics for specified VPI/VCI address.
- @li 0 - Disable statistics for specified VPI/VCI address */
-
- unsigned int vcStatsTxGFC:1; /**< [26] This register is used to include or exclude the GFC
- field of the ATM header when ATM VPI/VCI statistics are enabled.
- GFC is only available at the UNI and uses the first 4-bits of
- the VPI field.
- @li 1 - GFC field is valid
- @li 0 - GFC field ignored.*/
-
- unsigned int vcStatsTxPTI:1; /**< [25] This register is used to include or exclude the PTI
- field of the ATM header when ATM VPI/VCI statistics are enabled.
- @li 1 - PTI field is valid
- @li 0 - PTI field ignored.*/
-
- unsigned int vcStatsTxCLP:1; /**< [24] This register is used to include or exclude the CLP
- field of the ATM header when ATM VPI/VCI statistics are enabled.
- @li 1 - CLP field is valid
- @li 0 - CLP field ignored. */
-
- unsigned int reserved_1:3; /**< [23-21] These bits are always 0 */
-
- unsigned int txPollStsInt:1; /**< [20] Enable the assertion of the ucp_tx_poll_sts condition
- where there is a change in polling status.
- @li 1 - ucp_tx_poll_sts asserted whenever there is a change in status
- @li 0 - ucp_tx_poll_sts asserted if ANY transmit PHY is available
- */
- unsigned int txCellOvrInt:1; /**< [19] Enable TxCellCount overflow CBI Transmit Status condition
- assertion.
- @li 1 - If TxCellCountOvr is set assert the Transmit Status Condition.
- @li 0 - No CBI Transmit Status condition assertion */
-
- unsigned int txIdleCellOvrInt:1; /**< [18] Enable TxIdleCellCount overflow Transmit Status Condition
- @li 1 - If TxIdleCellCountOvr is set assert the Transmit Status Condition
- @li 0 - No CBI Transmit Status condition assertion..*/
-
- unsigned int enbIdleCellCnt:1; /**< [17] Enable Transmit Idle Cell Count.
- @li 1 - Enable count of Idle cells transmitted.
- @li 0 - No count is maintained. */
-
- unsigned int enbTxCellCnt:1; /**< [16] Enable Transmit Valid Cell Count of non-idle/non-error cells
- @li 1 - Enable count of valid cells transmitted- non-idle/non-error
- @li 0 - No count is maintained.*/
-
- unsigned int reserved_2:16; /**< [15:0] These bits are always 0 */
- } utTxEnableFields; /**< Tx enable Utopia register */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtTxTransTable0_
- * @brief Utopia Tx translation table Register
- */
- struct UtTxTransTable0_
- {
-
- unsigned int phy0:5; /**< [31-27] Tx Mapping value of logical phy 0 */
-
- unsigned int phy1:5; /**< [26-22] Tx Mapping value of logical phy 1 */
-
- unsigned int phy2:5; /**< [21-17] Tx Mapping value of logical phy 2 */
-
- unsigned int reserved_1:1; /**< [16] These bits are always 0.*/
-
- unsigned int phy3:5; /**< [15-11] Tx Mapping value of logical phy 3 */
-
- unsigned int phy4:5; /**< [10-6] Tx Mapping value of logical phy 4 */
-
- unsigned int phy5:5; /**< [5-1] Tx Mapping value of logical phy 5 */
-
- unsigned int reserved_2:1; /**< [0] These bits are always 0 */
- } utTxTransTable0; /**< Tx translation table */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtTxTransTable1_
- * @brief Utopia Tx translation table Register
- */
- struct UtTxTransTable1_
- {
-
- unsigned int phy6:5; /**< [31-27] Tx Mapping value of logical phy 6 */
-
- unsigned int phy7:5; /**< [26-22] Tx Mapping value of logical phy 7 */
-
- unsigned int phy8:5; /**< [21-17] Tx Mapping value of logical phy 8 */
-
- unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */
-
- unsigned int phy9:5; /**< [15-11] Tx Mapping value of logical phy 3 */
-
- unsigned int phy10:5; /**< [10-6] Tx Mapping value of logical phy 4 */
-
- unsigned int phy11:5; /**< [5-1] Tx Mapping value of logical phy 5 */
-
- unsigned int reserved_2:1; /**< [0] These bits are always 0 */
- } utTxTransTable1; /**< Tx translation table */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtTxTransTable2_
- * @brief Utopia Tx translation table Register
- */
- struct UtTxTransTable2_
- {
-
- unsigned int phy12:5; /**< [31-27] Tx Mapping value of logical phy 6 */
-
- unsigned int phy13:5; /**< [26-22] Tx Mapping value of logical phy 7 */
-
- unsigned int phy14:5; /**< [21-17] Tx Mapping value of logical phy 8 */
-
- unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */
-
- unsigned int phy15:5; /**< [15-11] Tx Mapping value of logical phy 3 */
-
- unsigned int phy16:5; /**< [10-6] Tx Mapping value of logical phy 4 */
-
- unsigned int phy17:5; /**< [5-1] Tx Mapping value of logical phy 5 */
-
- unsigned int reserved_2:1; /**< [0] These bits are always 0 */
- } utTxTransTable2; /**< Tx translation table */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtTxTransTable3_
- * @brief Utopia Tx translation table Register
- */
- struct UtTxTransTable3_
- {
-
- unsigned int phy18:5; /**< [31-27] Tx Mapping value of logical phy 6 */
-
- unsigned int phy19:5; /**< [26-22] Tx Mapping value of logical phy 7 */
-
- unsigned int phy20:5; /**< [21-17] Tx Mapping value of logical phy 8 */
-
- unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */
-
- unsigned int phy21:5; /**< [15-11] Tx Mapping value of logical phy 3 */
-
- unsigned int phy22:5; /**< [10-6] Tx Mapping value of logical phy 4 */
-
- unsigned int phy23:5; /**< [5-1] Tx Mapping value of logical phy 5 */
-
- unsigned int reserved_2:1; /**< [0] These bits are always 0 */
- } utTxTransTable3; /**< Tx translation table */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtTxTransTable4_
- * @brief Utopia Tx translation table Register
- */
- struct UtTxTransTable4_
- {
-
- unsigned int phy24:5; /**< [31-27] Tx Mapping value of logical phy 6 */
-
- unsigned int phy25:5; /**< [26-22] Tx Mapping value of logical phy 7 */
-
- unsigned int phy26:5; /**< [21-17] Tx Mapping value of logical phy 8 */
-
- unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */
-
- unsigned int phy27:5; /**< [15-11] Tx Mapping value of logical phy 3 */
-
- unsigned int phy28:5; /**< [10-6] Tx Mapping value of logical phy 4 */
-
- unsigned int phy29:5; /**< [5-1] Tx Mapping value of logical phy 5 */
-
- unsigned int reserved_2:1; /**< [0] These bits are always 0 */
- } utTxTransTable4; /**< Tx translation table */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtTxTransTable5_
- * @brief Utopia Tx translation table Register
- */
- struct UtTxTransTable5_
- {
-
- unsigned int phy30:5; /**< [31-27] Tx Mapping value of logical phy 6 */
-
- unsigned int reserved_1:27; /**< [26-0] These bits are always 0 */
-
- } utTxTransTable5; /**< Tx translation table */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtRxConfig_
- * @brief Utopia Rx config Register
- */
- struct UtRxConfig_
- {
-
- unsigned int rxInterface:1; /**< [31] Utopia Receive Interface. The following encoding is used
- to set the Utopia Receive interface as ATM master or PHY slave:
- @li 1 - PHY
- @li 0 - ATM */
-
- unsigned int rxMode:1; /**< [30] Utopia Receive Mode. The following encoding is used to set
- the Utopia Receive mode to SPHY or MPHY:
- @li 1 - SPHY
- @li 0 - MPHY */
-
- unsigned int rxOctet:1; /**< [29] Utopia Receive cell transfer protocol. Used to set the Utopia
- cell transfer protocol to Octet-level handshaking. Note this is only
- applicable in SPHY mode.
- @li 1 - Octet-handshaking enabled
- @li 0 - Cell-handshaking enabled */
-
- unsigned int rxParity:1; /**< [28] Utopia Receive Parity Checking enable.
- @li 1 - Parity checking enabled
- @li 0 - Parity checking disabled */
-
- unsigned int rxEvenParity:1;/**< [27] Utopia Receive Parity Mode
- @li 1 - Check for Even Parity
- @li 0 - Check for Odd Parity.*/
-
- unsigned int rxHEC:1; /**< [26] RxHEC Header Error Check Mode. Enables/disables cell header
- error checking on the received cell header.
- @li 1 - HEC checking enabled
- @li 0 - HEC checking disabled */
-
- unsigned int rxCOSET:1; /**< [25] If enabled the HEC is Exclusive-ORÆed with the value 0x55
- before being tested with the received HEC.
- @li 1 - Enable HEC ExOR with value 0x55.
- @li 0 - Use generated HEC value.*/
-
- unsigned int rxHECpass:1; /**< [24] Specifies if the incoming cell HEC byte should be transferred
- after optional processing to the NPE2 Coprocessor Bus Interface or
- if it should be discarded.
- @li 1 - HEC maintained 53-byte/UDC cell sent to NPE2.
- @li 0 - HEC discarded 52-byte/UDC cell sent to NPE2 coprocessor.*/
-
- unsigned int reserved_1:1; /**< [23] These bits are always 0 */
-
- unsigned int rxCellSize:7; /**< [22:16] Receive cell size. Configures the receive cell size.
- Values between 52-64 are valid */
-
- unsigned int rxHashEnbGFC:1; /**< [15] Specifies if the VPI field [11:8]/GFC field should be
- included in the Hash data input or if the bits should be padded
- with 1Æb0.
- @li 1 - VPI [11:8]/GFC field valid and used in Hash residue calculation.
- @li 0 - VPI [11:8]/GFC field padded with 1Æb0 */
-
- unsigned int rxPreHash:1; /**< [14] Enable Pre-hash value generation. Specifies if the
- incoming cell data should be pre-hashed to allow VPI/VCI header look-up
- in a hash table.
- @li 1 - Pre-hashing enabled
- @li 0 - Pre-hashing disabled */
-
- unsigned int reserved_2:1; /**< [13] These bits are always 0 */
-
- unsigned int rxAddrRange:5; /**< [12:8] In ATM master, MPHY mode,
- * this register specifies the upper
- * limit of the PHY polling logical range. The number of active PHYs are
- * RxAddrRange + 1.
- */
- unsigned int reserved_3:3; /**< [7-5] These bits are always 0 .*/
- unsigned int rxPHYAddr:5; /**< [4:0] When configured as a slave in an MPHY system this register
- * specifies the physical address of the PHY.
- */
- } utRxConfig; /**< Rx config Utopia register */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtRxStatsConfig_
- * @brief Utopia Rx stats config Register
- */
- struct UtRxStatsConfig_
- {
-
- unsigned int vpi:12; /**< [31:20] ATM VPI VPI [11:0] OR GFC [3:0] and VPI [7:0]
- @li Note: if VCStatsRxGFC is set to 0 the GFC field is ignored in test. */
-
- unsigned int vci:16; /**< [19:4] VCI [15:0] or PHY Address [4] */
-
- unsigned int pti:3; /**< [3:1] PTI [2:0] or or PHY Address [3:1]
- @li Note: if VCStatsRxPTI is set to 0 the PTI field is ignored in test.
- @li Note: if VCStatsRxEnb is set to 0 only the PHY port address is used
- for statistics gathering.. */
-
- unsigned int clp:1; /**< [0] CLP [0] or PHY Address [0]
- @li Note: if VCStatsRxCLP is set to 0 the CLP field is ignored in test.
- @li Note: if VCStatsRxEnb is set to 0 only the PHY port address is used
- for statistics gathering.. */
- } utRxStatsConfig; /**< Rx stats config Utopia register */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtRxDefineIdle_
- * @brief Utopia Rx idle cells config Register
- */
- struct UtRxDefineIdle_
- {
-
- unsigned int vpi:12; /**< [31:20] ATM VPI [11:0] OR GFC [3:0] and VPI [7:0]
- @li Note: if VCIdleRxGFC is set to 0 the GFC field is ignored in test. */
-
- unsigned int vci:16; /**< [19:4] ATM VCI [15:0] */
-
- unsigned int pti:3; /**< [3:1] ATM PTI PTI [2:0]
- @li Note: if VCIdleRxPTI is set to 0 the PTI field is ignored in test.*/
-
- unsigned int clp:1; /**< [0] ATM CLP [0]
- @li Note: if VCIdleRxCLP is set to 0 the CLP field is ignored in test.*/
- } utRxDefineIdle; /**< Rx idle cell config Utopia register */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtRxEnableFields_
- * @brief Utopia Rx enable Register
- */
- struct UtRxEnableFields_
- {
-
- unsigned int defineRxIdleGFC:1;/**< [31] This register is used to include or exclude the GFC
- field of the ATM header when testing for Idle cells.
- @li 1 - GFC field is valid.
- @li 0 - GFC field ignored.*/
-
- unsigned int defineRxIdlePTI:1;/**< [30] This register is used to include or exclude the PTI
- field of the ATM header when testing for Idle cells.
- @li 1 - PTI field is valid.
- @li 0 - PTI field ignored.*/
-
- unsigned int defineRxIdleCLP:1;/**< [29] This register is used to include or exclude the CLP
- field of the ATM header when testing for Idle cells.
- @li 1 - CLP field is valid.
- @li 0 - CLP field ignored.*/
-
- unsigned int phyStatsRxEnb:1;/**< [28] This register is used to enable or disable ATM statistics
- gathering based on the specified PHY address as defined in RxStatsConfig
- register.
- @li 1 - Enable statistics for specified receive PHY address.
- @li 0 - Disable statistics for specified receive PHY address.*/
-
- unsigned int vcStatsRxEnb:1;/**< [27] This register is used to enable or disable ATM statistics
- gathering based on a specific VPI/VCI address.
- @li 1 - Enable statistics for specified VPI/VCI address.
- @li 0 - Disable statistics for specified VPI/VCI address.*/
-
- unsigned int vcStatsRxGFC:1;/**< [26] This register is used to include or exclude the GFC field
- of the ATM header when ATM VPI/VCI statistics are enabled. GFC is only
- available at the UNI and uses the first 4-bits of the VPI field.
- @li 1 - GFC field is valid.
- @li 0 - GFC field ignored. */
-
- unsigned int vcStatsRxPTI:1;/**< [25] This register is used to include or exclude the PTI field
- of the ATM header when ATM VPI/VCI statistics are enabled.
- @li 1 - PTI field is valid.
- @li 0 - PTI field ignored.*/
-
- unsigned int vcStatsRxCLP:1;/**< [24] This register is used to include or exclude the CLP field
- of the ATM header when ATM VPI/VCI statistics are enabled.
- @li 1 - CLP field is valid.
- @li 0 - CLP field ignored. */
-
- unsigned int discardHecErr:1;/**< [23] Discard cells with an invalid HEC.
- @li 1 - Discard cells with HEC errors
- @li 0 - Cells with HEC errors are passed */
-
- unsigned int discardParErr:1;/**< [22] Discard cells containing parity errors.
- @li 1 - Discard cells with parity errors
- @li 0 - Cells with parity errors are passed */
-
- unsigned int discardIdle:1; /**< [21] Discard Idle Cells based on DefineIdle register values
- @li 1 - Discard IDLE cells
- @li 0 - IDLE cells passed */
-
- unsigned int enbHecErrCnt:1;/**< [20] Enable Receive HEC Error Count.
- @li 1 - Enable count of received cells containing HEC errors
- @li 0 - No count is maintained. */
-
- unsigned int enbParErrCnt:1;/**< [19] Enable Parity Error Count
- @li 1 - Enable count of received cells containing Parity errors
- @li 0 - No count is maintained. */
-
- unsigned int enbIdleCellCnt:1;/**< [18] Enable Receive Idle Cell Count.
- @li 1 - Enable count of Idle cells received.
- @li 0 - No count is maintained.*/
-
- unsigned int enbSizeErrCnt:1;/**< [17] Enable Receive Size Error Count.
- @li 1 - Enable count of received cells of incorrect size
- @li 0 - No count is maintained. */
-
- unsigned int enbRxCellCnt:1;/**< [16] Enable Receive Valid Cell Count of non-idle/non-error cells.
- @li 1 - Enable count of valid cells received - non-idle/non-error
- @li 0 - No count is maintained. */
-
- unsigned int reserved_1:3; /**< [15:13] These bits are always 0 */
-
- unsigned int rxCellOvrInt:1; /**< [12] Enable CBI Utopia Receive Status Condition if the RxCellCount
- register overflows.
- @li 1 - CBI Receive Status asserted.
- @li 0 - No CBI Receive Status asserted.*/
-
- unsigned int invalidHecOvrInt:1; /**< [11] Enable CBI Receive Status Condition if the InvalidHecCount
- register overflows.
- @li 1 - CBI Receive Condition asserted.
- @li 0 - No CBI Receive Condition asserted */
-
- unsigned int invalidParOvrInt:1; /**< [10] Enable CBI Receive Status Condition if the InvalidParCount
- register overflows
- @li 1 - CBI Receive Condition asserted.
- @li 0 - No CBI Receive Condition asserted */
-
- unsigned int invalidSizeOvrInt:1; /**< [9] Enable CBI Receive Status Condition if the InvalidSizeCount
- register overflows.
- @li 1 - CBI Receive Status Condition asserted.
- @li¸0 - No CBI Receive Status asserted */
-
- unsigned int rxIdleOvrInt:1; /**< [8] Enable CBI Receive Status Condition if the RxIdleCount overflows.
- @li 1 - CBI Receive Condition asserted.
- @li 0 - No CBI Receive Condition asserted */
-
- unsigned int reserved_2:3; /**< [7:5] These bits are always 0 */
-
- unsigned int rxAddrMask:5; /**< [4:0] This register is used as a mask to allow the user to increase
- the PHY receive address range. The register should be programmed with
- the address-range limit, i.e. if set to 0x3 the address range increases
- to a maximum of 4 addresses. */
- } utRxEnableFields; /**< Rx enable Utopia register */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtRxTransTable0_
- * @brief Utopia Rx translation table Register
- */
- struct UtRxTransTable0_
- {
-
- unsigned int phy0:5; /**< [31-27] Rx Mapping value of logical phy 0 */
-
- unsigned int phy1:5; /**< [26-22] Rx Mapping value of logical phy 1 */
-
- unsigned int phy2:5; /**< [21-17] Rx Mapping value of logical phy 2 */
-
- unsigned int reserved_1:1; /**< [16] These bits are always 0 */
-
- unsigned int phy3:5; /**< [15-11] Rx Mapping value of logical phy 3 */
-
- unsigned int phy4:5; /**< [10-6] Rx Mapping value of logical phy 4 */
-
- unsigned int phy5:5; /**< [5-1] Rx Mapping value of logical phy 5 */
-
- unsigned int reserved_2:1; /**< [0] These bits are always 0 */
- }
-
- utRxTransTable0; /**< Rx translation table */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtRxTransTable1_
- * @brief Utopia Rx translation table Register
- */
- struct UtRxTransTable1_
- {
-
- unsigned int phy6:5; /**< [31-27] Rx Mapping value of logical phy 6 */
-
- unsigned int phy7:5; /**< [26-22] Rx Mapping value of logical phy 7 */
-
- unsigned int phy8:5; /**< [21-17] Rx Mapping value of logical phy 8 */
-
- unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */
-
- unsigned int phy9:5; /**< [15-11] Rx Mapping value of logical phy 3 */
-
- unsigned int phy10:5; /**< [10-6] Rx Mapping value of logical phy 4 */
-
- unsigned int phy11:5; /**< [5-1] Rx Mapping value of logical phy 5 */
-
- unsigned int reserved_2:1; /**< [0] These bits are always 0 */
- }
-
- utRxTransTable1; /**< Rx translation table */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtRxTransTable2_
- * @brief Utopia Rx translation table Register
- */
- struct UtRxTransTable2_
- {
-
- unsigned int phy12:5; /**< [31-27] Rx Mapping value of logical phy 6 */
-
- unsigned int phy13:5; /**< [26-22] Rx Mapping value of logical phy 7 */
-
- unsigned int phy14:5; /**< [21-17] Rx Mapping value of logical phy 8 */
-
- unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */
-
- unsigned int phy15:5; /**< [15-11] Rx Mapping value of logical phy 3 */
-
- unsigned int phy16:5; /**< [10-6] Rx Mapping value of logical phy 4 */
-
- unsigned int phy17:5; /**< [5-1] Rx Mapping value of logical phy 5 */
-
- unsigned int reserved_2:1; /**< [0] These bits are always 0 */
- } utRxTransTable2; /**< Rx translation table */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtRxTransTable3_
- * @brief Utopia Rx translation table Register
- */
- struct UtRxTransTable3_
- {
-
- unsigned int phy18:5; /**< [31-27] Rx Mapping value of logical phy 6 */
-
- unsigned int phy19:5; /**< [26-22] Rx Mapping value of logical phy 7 */
-
- unsigned int phy20:5; /**< [21-17] Rx Mapping value of logical phy 8 */
-
- unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */
-
- unsigned int phy21:5; /**< [15-11] Rx Mapping value of logical phy 3 */
-
- unsigned int phy22:5; /**< [10-6] Rx Mapping value of logical phy 4 */
-
- unsigned int phy23:5; /**< [5-1] Rx Mapping value of logical phy 5 */
-
- unsigned int reserved_2:1; /**< [0] These bits are always 0 */
- } utRxTransTable3; /**< Rx translation table */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtRxTransTable4_
- * @brief Utopia Rx translation table Register
- */
- struct UtRxTransTable4_
- {
-
- unsigned int phy24:5; /**< [31-27] Rx Mapping value of logical phy 6 */
-
- unsigned int phy25:5; /**< [26-22] Rx Mapping value of logical phy 7 */
-
- unsigned int phy26:5; /**< [21-17] Rx Mapping value of logical phy 8 */
-
- unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */
-
- unsigned int phy27:5; /**< [15-11] Rx Mapping value of logical phy 3 */
-
- unsigned int phy28:5; /**< [10-6] Rx Mapping value of logical phy 4 */
-
- unsigned int phy29:5; /**< [5-1] Rx Mapping value of logical phy 5 */
-
- unsigned int reserved_2:1; /**< [0] These bits are always 0 */
- } utRxTransTable4; /**< Rx translation table */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtRxTransTable5_
- * @brief Utopia Rx translation table Register
- */
- struct UtRxTransTable5_
- {
-
- unsigned int phy30:5; /**< [31-27] Rx Mapping value of logical phy 6 */
-
- unsigned int reserved_1:27; /**< [26-0] These bits are always 0 */
-
- } utRxTransTable5; /**< Rx translation table */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtSysConfig_
- * @brief NPE setup Register
- */
- struct UtSysConfig_
- {
-
- unsigned int reserved_1:2; /**< [31-30] These bits are always 0 */
- unsigned int txEnbFSM:1; /**< [29] Enables the operation ofthe Utopia Transmit FSM
- * @li 1 - FSM enabled
- * @li 0 - FSM inactive
- */
- unsigned int rxEnbFSM:1; /**< [28] Enables the operation ofthe Utopia Revieve FSM
- * @li 1 - FSM enabled
- * @li 0 - FSM inactive
- */
- unsigned int disablePins:1; /**< [27] Disable Utopia interface I/O pins forcing the signals to an
- * inactive state. Note that this bit is set on reset and must be
- * de-asserted
- * @li 0 - Normal data transfer
- * @li 1 - Utopia interface pins are forced inactive
- */
- unsigned int tstLoop:1; /**< [26] Test Loop Back Enable.
- * @li Note: For loop back to function RxMode and Tx Mode must both be set
- * to single PHY mode.
- * @li 0 - Loop back
- * @li 1 - Normal operating mode
- */
-
- unsigned int txReset:1; /**< [25] Resets the Utopia Coprocessor transmit module to a known state.
- * @li Note: All transmit configuration and status registers will be reset
- * to their reset values.
- * @li 0 - Normal operating mode¸
- * @li 1 - Reset transmit modules
- */
-
- unsigned int rxReset:1; /**< [24] Resets the Utopia Coprocessor receive module to a known state.
- * @li Note: All receive configuration and status registers will be reset
- * to their reset values.
- * @li 0 - Normal operating mode
- * @li 1 - Reset receive modules
- */
-
- unsigned int reserved_2:24; /**< [23-0] These bits are always 0 */
- } utSysConfig; /**< NPE debug config */
-
-}
-IxAtmdAccUtopiaConfig;
-
-/**
-*
-* @brief Utopia status
-*
-* This structure is used to set/get the Utopia status parameters
-* @li contains debug cell counters, to be accessed during a read operation
-*
-* @note - the exact description of all parameters is done in the Utopia reference
-* documents.
-*
-*/
-typedef struct
-{
-
- unsigned int utTxCellCount; /**< count of cells transmitted */
-
- unsigned int utTxIdleCellCount; /**< count of idle cells transmitted */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtTxCellConditionStatus_
- * @brief Utopia Tx Status Register
- */
- struct UtTxCellConditionStatus_
- {
-
- unsigned int reserved_1:2; /**< [31:30] These bits are always 0 */
- unsigned int txFIFO2Underflow:1; /**< [29] This bit is set if 64-byte
- * Transmit FIFO2 indicates a FIFO underflow
- * error condition.
- */
- unsigned int txFIFO1Underflow:1; /**< [28] This bit is set if
- * 64-byte Transmit FIFO1 indicates a FIFO
- * underflow error condition.
- */
- unsigned int txFIFO2Overflow:1; /**< [27] This bit is set if 64-byte
- * Transmit FIFO2 indicates a FIFO overflow
- * error condition.
- */
- unsigned int txFIFO1Overflow:1; /**< [26] This bit is set if 64-byte
- * Transmit FIFO1 indicates a FIFO overflow
- * error condition.
- */
- unsigned int txIdleCellCountOvr:1; /**< [25] This bit is set if the
- * TxIdleCellCount register overflows.
- */
- unsigned int txCellCountOvr:1; /**< [24] This bit is set if the
- * TxCellCount register overflows
- */
- unsigned int reserved_2:24; /**< [23:0] These bits are always 0 */
- } utTxCellConditionStatus; /**< Tx cells condition status */
-
- unsigned int utRxCellCount; /**< count of cell received */
- unsigned int utRxIdleCellCount; /**< count of idle cell received */
- unsigned int utRxInvalidHECount; /**< count of invalid cell
- * received because of HEC errors
- */
- unsigned int utRxInvalidParCount; /**< count of invalid cell received
- * because of parity errors
- */
- unsigned int utRxInvalidSizeCount; /**< count of invalid cell
- * received because of cell
- * size errors
- */
-
- /**
- * @ingroup IxAtmdAccUtopiaCtrlAPI
- * @struct UtRxCellConditionStatus_
- * @brief Utopia Rx Status Register
- */
- struct UtRxCellConditionStatus_
- {
-
- unsigned int reserved_1:3; /**< [31:29] These bits are always 0.*/
- unsigned int rxCellCountOvr:1; /**< [28] This bit is set if the RxCellCount register overflows. */
- unsigned int invalidHecCountOvr:1; /**< [27] This bit is set if the InvalidHecCount register overflows.*/
- unsigned int invalidParCountOvr:1; /**< [26] This bit is set if the InvalidParCount register overflows.*/
- unsigned int invalidSizeCountOvr:1; /**< [25] This bit is set if the InvalidSizeCount register overflows.*/
- unsigned int rxIdleCountOvr:1; /**< [24] This bit is set if the RxIdleCount register overflows.*/
- unsigned int reserved_2:4; /**< [23:20] These bits are always 0 */
- unsigned int rxFIFO2Underflow:1; /**< [19] This bit is set if 64-byte Receive FIFO2
- * indicates a FIFO underflow error condition.
- */
- unsigned int rxFIFO1Underflow:1; /**< [18] This bit is set if 64-byte Receive
- * FIFO1 indicates a FIFO underflow error condition
- . */
- unsigned int rxFIFO2Overflow:1; /**< [17] This bit is set if 64-byte Receive FIFO2
- * indicates a FIFO overflow error condition.
- */
- unsigned int rxFIFO1Overflow:1; /**< [16] This bit is set if 64-byte Receive FIFO1
- * indicates a FIFO overflow error condition.
- */
- unsigned int reserved_3:16; /**< [15:0] These bits are always 0. */
- } utRxCellConditionStatus; /**< Rx cells condition status */
-
-} IxAtmdAccUtopiaStatus;
-
-/**
- * @} defgroup IxAtmdAccUtopiaCtrlAPI
- */
-
- /**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccUtopiaConfigSet (const IxAtmdAccUtopiaConfig *
- ixAtmdAccUtopiaConfigPtr)
- *
- * @brief Send the configuration structure to the Utopia interface
- *
- * This function downloads the @a IxAtmdAccUtopiaConfig structure to
- * the Utopia and has the following effects
- * @li setup the Utopia interface
- * @li initialise the NPE
- * @li reset the Utopia cell counters and status registers to known values
- *
- * This action has to be done once at initialisation. A lock is preventing
- * the concurrent use of @a ixAtmdAccUtopiaStatusGet() and
- * @A ixAtmdAccUtopiaConfigSet()
- *
- * @param *ixAtmdAccNPEConfigPtr @ref IxAtmdAccUtopiaConfig [in] - pointer to a structure to download to
- * Utopia. This parameter cannot be a null pointer.
- *
- * @return @li IX_SUCCESS successful download
- * @return @li IX_FAIL error in the parameters, or configuration is not
- * complete or failed
- *
- * @sa ixAtmdAccUtopiaStatusGet
- *
- */
-PUBLIC IX_STATUS ixAtmdAccUtopiaConfigSet (const IxAtmdAccUtopiaConfig *
- ixAtmdAccUtopiaConfigPtr);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccUtopiaStatusGet (IxAtmdAccUtopiaStatus *
- ixAtmdAccUtopiaStatus)
- *
- * @brief Get the Utopia interface configuration.
- *
- * This function reads the Utopia registers and the Cell counts
- * and fills the @a IxAtmdAccUtopiaStatus structure
- *
- * A lock is preventing the concurrent
- * use of @a ixAtmdAccUtopiaStatusGet() and @A ixAtmdAccUtopiaConfigSet()
- *
- * @param ixAtmdAccUtopiaStatus @ref IxAtmdAccUtopiaStatus [out] - pointer to structure to be updated from internal
- * hardware counters. This parameter cannot be a NULL pointer.
- *
- * @return @li IX_SUCCESS successful read
- * @return @li IX_FAIL error in the parameters null pointer, or
- * configuration read is not complete or failed
- *
- * @sa ixAtmdAccUtopiaConfigSet
- *
- */
-PUBLIC IX_STATUS ixAtmdAccUtopiaStatusGet (IxAtmdAccUtopiaStatus *
- ixAtmdAccUtopiaStatus);
-
-/**
- *
- * @ingroup IxAtmdAcc
- *
- * @fn ixAtmdAccPortEnable (IxAtmLogicalPort port)
- *
- * @brief enable a PHY logical port
- *
- * This function enables the transmission over one port. It should be
- * called before accessing any resource from this port and before the
- * establishment of a VC.
- *
- * When a port is enabled, the cell transmission to the Utopia interface
- * is started. If there is no traffic already running, idle cells are
- * sent over the interface.
- *
- * This function can be called multiple times.
- *
- * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- *
- * @return @li IX_SUCCESS enable is complete
- * @return @li IX_ATMDACC_WARNING port already enabled
- * @return @li IX_FAIL enable failed, wrong parameter, or cannot
- * initialise this port (the port is maybe already in use,
- * or there is a hardware issue)
- *
- * @note - This function needs internal locks and should not be
- * called from an interrupt context
- *
- * @sa ixAtmdAccPortDisable
- *
- */
-PUBLIC IX_STATUS ixAtmdAccPortEnable (IxAtmLogicalPort port);
-
-/**
- *
- * @ingroup IxAtmdAccCtrlAPI
- *
- * @fn ixAtmdAccPortDisable (IxAtmLogicalPort port)
- *
- * @brief disable a PHY logical port
- *
- * This function disable the transmission over one port.
- *
- * When a port is disabled, the cell transmission to the Utopia interface
- * is stopped.
- *
- * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
- *
- * @return @li IX_SUCCESS disable is complete
- * @return @li IX_ATMDACC_WARNING port already disabled
- * @return @li IX_FAIL disable failed, wrong parameter .
- *
- * @note - This function needs internal locks and should not be called
- * from an interrupt context
- *
- * @note - The response from hardware is done through the txDone mechanism
- * to ensure the synchrnisation with tx resources. Therefore, the
- * txDone mechanism needs to be serviced to make a PortDisable complete.
- *
- * @sa ixAtmdAccPortEnable
- * @sa ixAtmdAccPortDisableComplete
- * @sa ixAtmdAccTxDoneDispatch
- *
- */
-PUBLIC IX_STATUS ixAtmdAccPortDisable (IxAtmLogicalPort port);
-
-/**
-*
-* @ingroup IxAtmdAccCtrlAPI
-*
-* @fn ixAtmdAccPortDisableComplete (IxAtmLogicalPort port)
-*
-* @brief disable a PHY logical port
-*
-* This function indicates if the port disable for a port has completed. This
-* function will return TRUE if the port has never been enabled.
-*
-* @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
-*
-* @return @li TRUE disable is complete
-* @return @li FALSE disable failed, wrong parameter .
-*
-* @note - This function needs internal locks and should not be called
-* from an interrupt context
-*
-* @sa ixAtmdAccPortEnable
-* @sa ixAtmdAccPortDisable
-*
-*/
-PUBLIC BOOL ixAtmdAccPortDisableComplete (IxAtmLogicalPort port);
-
-#endif /* IXATMDACCCTRL_H */
-
-/**
- * @} defgroup IxAtmdAccCtrlAPI
- */
-
-
+++ /dev/null
-/**
- * @file IxAtmm.h
- *
- * @date 3-DEC-2001
- *
- * @brief Header file for the IXP400 ATM Manager component (IxAtmm)
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-
-/**
- * @defgroup IxAtmm IXP400 ATM Manager (IxAtmm) API
- *
- * @brief IXP400 ATM Manager component Public API
- *
- * @{
- */
-
-#ifndef IXATMM_H
-#define IXATMM_H
-
-/*
- * Put the user defined include files required
- */
-#include "IxAtmSch.h"
-#include "IxOsalTypes.h"
-
-/*
- * #defines and macros used in this file.
- */
-
-/**
- * @def IX_ATMM_RET_ALREADY_INITIALIZED
- *
- * @brief Component has already been initialized
- */
-#define IX_ATMM_RET_ALREADY_INITIALIZED 2
-
-/**
- * @def IX_ATMM_RET_INVALID_PORT
- *
- * @brief Specified port does not exist or is out of range */
-#define IX_ATMM_RET_INVALID_PORT 3
-
-/**
- * @def IX_ATMM_RET_INVALID_VC_DESCRIPTOR
- *
- * @brief The VC description does not adhere to ATM standards */
-#define IX_ATMM_RET_INVALID_VC_DESCRIPTOR 4
-
-/**
- * @def IX_ATMM_RET_VC_CONFLICT
- *
- * @brief The VPI/VCI values supplied are either reserved, or they
- * conflict with a previously registered VC on this port */
-#define IX_ATMM_RET_VC_CONFLICT 5
-
-/**
- * @def IX_ATMM_RET_PORT_CAPACITY_IS_FULL
- *
- * @brief The virtual connection cannot be established on the port
- * because the remaining port capacity is not sufficient to
- * support it */
-#define IX_ATMM_RET_PORT_CAPACITY_IS_FULL 6
-
-/**
- * @def IX_ATMM_RET_NO_SUCH_VC
- *
- * @brief No registered VC, as described by the supplied VCI/VPI or
- * VC identifier values, exists on this port */
-#define IX_ATMM_RET_NO_SUCH_VC 7
-
-/**
- * @def IX_ATMM_RET_INVALID_VC_ID
- *
- * @brief The specified VC identifier is out of range. */
-#define IX_ATMM_RET_INVALID_VC_ID 8
-
-/**
- * @def IX_ATMM_RET_INVALID_PARAM_PTR
- *
- * @brief A pointer parameter was NULL. */
-#define IX_ATMM_RET_INVALID_PARAM_PTR 9
-
-/**
- * @def IX_ATMM_UTOPIA_SPHY_ADDR
- *
- * @brief The phy address when in SPHY mode */
-#define IX_ATMM_UTOPIA_SPHY_ADDR 31
-
-/**
- * @def IX_ATMM_THREAD_PRI_HIGH
- *
- * @brief The value of high priority thread */
-#define IX_ATMM_THREAD_PRI_HIGH 90
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/** @brief Definition for use in the @ref IxAtmmVc structure.
- * Indicates the direction of a VC */
-typedef enum
-{
- IX_ATMM_VC_DIRECTION_TX=0, /**< Atmm Vc direction transmit*/
- IX_ATMM_VC_DIRECTION_RX, /**< Atmm Vc direction receive*/
- IX_ATMM_VC_DIRECTION_INVALID /**< Atmm Vc direction invalid*/
-} IxAtmmVcDirection;
-
-/** @brief Definition for use with @ref IxAtmmVcChangeCallback
- * callback. Indicates that the event type represented by the
- * callback for this VC. */
-typedef enum
-{
- IX_ATMM_VC_CHANGE_EVENT_REGISTER=0, /**< Atmm Vc event register*/
- IX_ATMM_VC_CHANGE_EVENT_DEREGISTER, /**< Atmm Vc event de-register*/
- IX_ATMM_VC_CHANGE_EVENT_INVALID /**< Atmm Vc event invalid*/
-} IxAtmmVcChangeEvent;
-
-/** @brief Definitions for use with @ref ixAtmmUTOPIAInit interface to
- * indicate that UTOPIA loopback should be enabled or disabled
- * on initialisation. */
-typedef enum
-{
- IX_ATMM_UTOPIA_LOOPBACK_DISABLED=0, /**< Atmm Utopia loopback mode disabled*/
- IX_ATMM_UTOPIA_LOOPBACK_ENABLED, /**< Atmm Utopia loopback mode enabled*/
- IX_ATMM_UTOPIA_LOOPBACK_INVALID /**< Atmm Utopia loopback mode invalid*/
-} IxAtmmUtopiaLoopbackMode;
-
-/** @brief This structure describes the required attributes of a
- * virtual connection.
-*/
-typedef struct {
- unsigned vpi; /**< VPI value of this virtual connection */
- unsigned vci; /**< VCI value of this virtual connection. */
- IxAtmmVcDirection direction; /**< VC direction */
-
- /** Traffic descriptor of this virtual connection. This structure
- * is defined by the @ref IxAtmSch component. */
- IxAtmTrafficDescriptor trafficDesc;
-} IxAtmmVc;
-
-
-/** @brief Definitions for use with @ref ixAtmmUtopiaInit interface to
- * indicate that UTOPIA multi-phy/single-phy mode is used.
- */
-typedef enum
-{
- IX_ATMM_MPHY_MODE = 0, /**< Atmm phy mode mphy*/
- IX_ATMM_SPHY_MODE, /**< Atmm phy mode sphy*/
- IX_ATMM_PHY_MODE_INVALID /**< Atmm phy mode invalid*/
-} IxAtmmPhyMode;
-
-
-/** @brief Structure contains port-specific information required to
- * initialize IxAtmm, and specifically, the IXP400 UTOPIA
- * Level-2 device. */
-typedef struct {
- unsigned reserved_1:11; /**< [31:21] Should be zero */
- unsigned UtopiaTxPhyAddr:5; /**< [20:16] Address of the
- * transmit (Tx) PHY for this
- * port on the 5-bit UTOPIA
- * Level-2 address bus */
- unsigned reserved_2:11; /**< [15:5] Should be zero */
- unsigned UtopiaRxPhyAddr:5; /**< [4:0] Address of the receive
- * (Rx) PHY for this port on the
- * 5-bit UTOPIA Level-2
- * address bus */
-} IxAtmmPortCfg;
-
-/** @brief Callback type used with @ref ixAtmmVcChangeCallbackRegister interface
- * Defines a callback type which will be used to notify registered
- * users of registration/deregistration events on a particular port
- *
- * @param eventType @ref IxAtmmVcChangeEvent [in] - Event indicating
- * whether the VC supplied has been added or
- * removed
- *
- * @param port @ref IxAtmLogicalPort [in] - Specifies the port on which the event has
- * occurred
- *
- * @param vcChanged @ref IxAtmmVc* [in] - Pointer to a structure which gives
- * details of the VC which has been added
- * or removed on the port
- */
-typedef void (*IxAtmmVcChangeCallback) (IxAtmmVcChangeEvent eventType,
- IxAtmLogicalPort port,
- const IxAtmmVc* vcChanged);
-
-/*
- * Variable declarations global to this file only. Externs are followed by
- * static variables.
- */
-
-/*
- * Extern function prototypes
- */
-
-/*
- * Function declarations
- */
-
-
-/**
- * @ingroup IxAtmm
- *
- * @fn ixAtmmInit (void)
- *
- * @brief Interface to initialize the IxAtmm software component. Can
- * be called once only.
- *
- * Must be called before any other IxAtmm API is called.
- *
- * @param "none"
- *
- * @return @li IX_SUCCESS : IxAtmm has been successfully initialized.
- * Calls to other IxAtmm interfaces may now be performed.
- * @return @li IX_FAIL : IxAtmm has already been initialized.
- */
-PUBLIC IX_STATUS
-ixAtmmInit (void);
-
-/**
- * @ingroup IxAtmm
- *
- * @fn ixAtmmUtopiaInit (unsigned numPorts,
- IxAtmmPhyMode phyMode,
- IxAtmmPortCfg portCfgs[],
- IxAtmmUtopiaLoopbackMode loopbackMode)
- *
- * @brief Interface to initialize the UTOPIA Level-2 ATM coprocessor
- * for the specified number of physical ports. The function
- * must be called before the ixAtmmPortInitialize interface
- * can operate successfully.
- *
- * @param numPorts unsigned [in] - Indicates the total number of logical
- * ports that are active on the device. Up to 12 ports are
- * supported.
- *
- * @param phyMode @ref IxAtmmPhyMode [in] - Put the Utopia coprocessor in SPHY
- * or MPHY mode.
- *
- * @param portCfgs[] @ref IxAtmmPortCfg [in] - Pointer to an array of elements
- * detailing the UTOPIA specific port characteristics. The
- * length of the array must be equal to the number of ports
- * activated. ATM ports are referred to by the relevant
- * offset in this array in all subsequent IxAtmm interface
- * calls.
- *
- * @param loopbackMode @ref IxAtmmUtopiaLoopbackMode [in] - Value must be one of
- * @ref IX_ATMM_UTOPIA_LOOPBACK_ENABLED or @ref
- * IX_ATMM_UTOPIA_LOOPBACK_DISABLED indicating whether
- * loopback should be enabled on the device. Loopback can
- * only be supported on a single PHY, therefore the numPorts
- * parameter must be 1 if loopback is enabled.
- *
- * @return @li IX_SUCCESS : Indicates that the UTOPIA device has been
- * successfully initialized for the supplied ports.
- * @return @li IX_ATMM_RET_ALREADY_INITIALIZED : The UTOPIA device has
- * already been initialized.
- * @return @li IX_FAIL : The supplied parameters are invalid or have been
- * rejected by the UTOPIA-NPE device.
- *
- * @warning
- * This interface may only be called once.
- * Port identifiers are assumed to range from 0 to (numPorts - 1) in all
- * instances.
- * In all subsequent calls to interfaces supplied by IxAtmm, the specified
- * port value is expected to represent the offset in the portCfgs array
- * specified in this interface. i.e. The first port in this array will
- * subsequently be represented as port 0, the second port as port 1,
- * and so on.*/
-PUBLIC IX_STATUS
-ixAtmmUtopiaInit (unsigned numPorts,
- IxAtmmPhyMode phyMode,
- IxAtmmPortCfg portCfgs[],
- IxAtmmUtopiaLoopbackMode loopbackMode);
-
-
-/**
- * @ingroup IxAtmm
- *
- * @fn ixAtmmPortInitialize (IxAtmLogicalPort port,
- unsigned txPortRate,
- unsigned rxPortRate)
- *
- * @brief The interface is called following @ref ixAtmmUtopiaInit ()
- * and before calls to any other IxAtmm interface. It serves
- * to activate the registered ATM port with IxAtmm.
- *
- * The transmit and receive port rates are specified in bits per
- * second. This translates to ATM cells per second according to the
- * following formula: CellsPerSecond = portRate / (53*8) The
- * IXP400 device supports only 53 byte cells. The client shall make
- * sure that the off-chip physical layer device has already been
- * initialized.
- *
- * IxAtmm will configure IxAtmdAcc and IxAtmSch to enable scheduling
- * on the port.
- *
- * This interface must be called once for each active port in the
- * system. The first time the interface is invoked, it will configure
- * the mechanism by which the handling of transmit, transmit-done and
- * receive are driven with the IxAtmdAcc component.
- *
- * This function is reentrant.
- *
- * @note The minimum tx rate that will be accepted is 424 bit/s which equates
- * to 1 cell (53 bytes) per second.
- *
- * @param port @ref IxAtmLogicalPort [in] - Identifies the port which is to be
- * initialized.
- *
- * @param txPortRate unsigned [in] - Value specifies the
- * transmit port rate for this port in
- * bits/second. This value is used by the ATM Scheduler
- * component is evaluating VC access requests for the port.
- *
- * @param rxPortRate unsigned [in] - Value specifies the
- * receive port rate for this port in bits/second.
- *
- * @return @li IX_SUCCESS : The specificed ATM port has been successfully
- * initialized. IxAtmm is ready to accept VC registrations on
- * this port.
- *
- * @return @li IX_ATMM_RET_ALREADY_INITIALIZED : ixAtmmPortInitialize has
- * already been called successfully on this port. The current
- * call is rejected.
- *
- * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the
- * input is not valid. The request is rejected.
- *
- * @return @li IX_FAIL : IxAtmm could not initialize the port because the
- * inputs are not understood.
- *
- * @sa ixAtmmPortEnable, ixAtmmPortDisable
- *
- */
-PUBLIC IX_STATUS
-ixAtmmPortInitialize (IxAtmLogicalPort port,
- unsigned txPortRate,
- unsigned rxPortRate);
-
-/**
- * @ingroup IxAtmm
- *
- * @fn ixAtmmPortModify (IxAtmLogicalPort port,
- unsigned txPortRate,
- unsigned rxPortRate)
- *
- * @brief A client may call this interface to change the existing
- * port rate (expressed in bits/second) on an established ATM
- * port.
- *
- * @param port @ref IxAtmLogicalPort [in] - Identifies the port which is to be
- * initialized.
- *
- * @param txPortRate unsigned [in] - Value specifies the``
- * transmit port rate for this port in
- * bits/second. This value is used by the ATM Scheduler
- * component is evaluating VC access requests for the port.
- *
- * @param rxPortRate unsigned [in] - Value specifies the
- * receive port rate for this port in
- * bits/second.
- *
- * @return @li IX_SUCCESS : The indicated ATM port rates have been
- * successfully modified.
- *
- * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the
- * input is not valid. The request is rejected.
- *
- * @return @li IX_FAIL : IxAtmm could not update the port because the
- * inputs are not understood, or the interface was called before
- * the port was initialized. */
-PUBLIC IX_STATUS
-ixAtmmPortModify (IxAtmLogicalPort port,
- unsigned txPortRate,
- unsigned rxPortRate);
-
-/**
- * @ingroup IxAtmm
- *
- * @fn ixAtmmPortQuery (IxAtmLogicalPort port,
- unsigned *txPortRate,
- unsigned *rxPortRate);
-
- *
- * @brief The client may call this interface to request details on
- * currently registered transmit and receive rates for an ATM
- * port.
- *
- * @param port @ref IxAtmLogicalPort [in] - Value identifies the port from which the
- * rate details are requested.
- *
- * @param *txPortRate unsigned [out] - Pointer to a value
- * which will be filled with the value of the transmit port
- * rate specified in bits/second.
- *
- * @param *rxPortRate unsigned [out] - Pointer to a value
- * which will be filled with the value of the receive port
- * rate specified in bits/second.
- *
- * @return @li IX_SUCCESS : The information requested on the specified
- * port has been successfully supplied in the output.
- *
- * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the
- * input is not valid. The request is rejected.
- *
- * @return @li IX_ATMM_RET_INVALID_PARAM_PTR : A pointer parameter was
- * NULL.
- *
- * @return @li IX_FAIL : IxAtmm could not update the port because the
- * inputs are not understood, or the interface was called before
- * the port was initialized. */
-PUBLIC IX_STATUS
-ixAtmmPortQuery (IxAtmLogicalPort port,
- unsigned *txPortRate,
- unsigned *rxPortRate);
-
-/**
- * @ingroup IxAtmm
- *
- * @fn ixAtmmPortEnable(IxAtmLogicalPort port)
- *
- * @brief The client call this interface to enable transmit for an ATM
- * port. At initialisation, all the ports are disabled.
- *
- * @param port @ref IxAtmLogicalPort [in] - Value identifies the port
- *
- * @return @li IX_SUCCESS : Transmission over this port is started.
- *
- * @return @li IX_FAIL : The port parameter is not valid, or the
- * port is already enabled
- *
- * @note - When a port is disabled, Rx and Tx VC Connect requests will fail
- *
- * @note - This function uses system resources and should not be used
- * inside an interrupt context.
- *
- * @sa ixAtmmPortDisable */
-PUBLIC IX_STATUS
-ixAtmmPortEnable(IxAtmLogicalPort port);
-
-/**
- * @ingroup IxAtmm
- *
- * @fn ixAtmmPortDisable(IxAtmLogicalPort port)
- *
- * @brief The client call this interface to disable transmit for an ATM
- * port. At initialisation, all the ports are disabled.
- *
- * @param port @ref IxAtmLogicalPort [in] - Value identifies the port
- *
- * @return @li IX_SUCCESS : Transmission over this port is stopped.
- *
- * @return @li IX_FAIL : The port parameter is not valid, or the
- * port is already disabled
- *
- * @note - When a port is disabled, Rx and Tx VC Connect requests will fail
- *
- * @note - This function call does not stop RX traffic. It is supposed
- * that this function is invoked when a serious problem
- * is detected (e.g. physical layer broken). Then, the RX traffic
- * is not passing.
- *
- * @note - This function is blocking until the hw acknowledge that the
- * transmission is stopped.
- *
- * @note - This function uses system resources and should not be used
- * inside an interrupt context.
- *
- * @sa ixAtmmPortEnable */
-PUBLIC IX_STATUS
-ixAtmmPortDisable(IxAtmLogicalPort port);
-
-/**
- * @ingroup IxAtmm
- *
- * @fn ixAtmmVcRegister (IxAtmLogicalPort port,
- IxAtmmVc *vcToAdd,
- IxAtmSchedulerVcId *vcId)
- *
- * @brief This interface is used to register an ATM Virtual
- * Connection on the specified ATM port.
- *
- * Each call to this interface registers a unidirectional virtual
- * connection with the parameters specified. If a bi-directional VC
- * is needed, the function should be called twice (once for each
- * direction, Tx & Rx) where the VPI and VCI and port parameters in
- * each call are identical.
- *
- * With the addition of each new VC to a port, a series of
- * callback functions are invoked by the IxAtmm component to notify
- * possible external components of the change. The callback functions
- * are registered using the @ref ixAtmmVcChangeCallbackRegister interface.
- *
- * The IxAtmSch component is notified of the registration of transmit
- * VCs.
- *
- * @param port @ref IxAtmLogicalPort [in] - Identifies port on which the specified VC is
- * to be registered.
- *
- * @param *vcToAdd @ref IxAtmmVc [in] - Pointer to an @ref IxAtmmVc structure
- * containing a description of the VC to be registered. The
- * client shall fill the vpi, vci and direction and relevant
- * trafficDesc members of this structure before calling this
- * function.
- *
- * @param *vcId @ref IxAtmSchedulerVcId [out] - Pointer to an integer value which is filled
- * with the per-port unique identifier value for this VC.
- * This identifier will be required when a request is
- * made to deregister or change this VC. VC identifiers
- * for transmit VCs will have a value between 0-43,
- * i.e. 32 data Tx VCs + 12 OAM Tx Port VCs.
- * Receive VCs will have a value between 44-66,
- * i.e. 32 data Rx VCs + 1 OAM Rx VC.
- *
- * @return @li IX_SUCCESS : The VC has been successfully registered on
- * this port. The VC is ready for a client to configure IxAtmdAcc
- * for receive and transmit operations on the VC.
- * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the
- * input is not valid or has not been initialized. The request
- * is rejected.
- * @return @li IX_ATMM_RET_INVALID_VC_DESCRIPTOR : The descriptor
- * pointed to by vcToAdd is invalid. The registration request
- * is rejected.
- * @return @li IX_ATMM_RET_VC_CONFLICT : The VC requested conflicts with
- * reserved VPI and/or VCI values or with another VC already activated
- * on this port.
- * @return @li IX_ATMM_RET_PORT_CAPACITY_IS_FULL : The VC cannot be
- * registered in the port becuase the port capacity is
- * insufficient to support the requested ATM traffic contract.
- * The registration request is rejected.
- * @return @li IX_ATMM_RET_INVALID_PARAM_PTR : A pointer parameter was
- * NULL.
- *
- * @warning IxAtmm has no capability of signaling or negotiating a virtual
- * connection. Negotiation of the admission of the VC to the network
- * is beyond the scope of this function. This is assumed to be
- * performed by the calling client, if appropriate,
- * before or after this function is called.
- */
-PUBLIC IX_STATUS
-ixAtmmVcRegister (IxAtmLogicalPort port,
- IxAtmmVc *vcToAdd,
- IxAtmSchedulerVcId *vcId);
-
-/**
- * @ingroup IxAtmm
- *
- * @fn ixAtmmVcDeregister (IxAtmLogicalPort port, IxAtmSchedulerVcId vcId)
- *
- * @brief Function called by a client to deregister a VC from the
- * system.
- *
- * With the removal of each new VC from a port, a series of
- * registered callback functions are invoked by the IxAtmm component
- * to notify possible external components of the change. The callback
- * functions are registered using the @ref ixAtmmVcChangeCallbackRegister.
- *
- * The IxAtmSch component is notified of the removal of transmit VCs.
- *
- * @param port @ref IxAtmLogicalPort [in] - Identifies port on which the VC to be
- * removed is currently registered.
- *
- * @param vcId @ref IxAtmSchedulerVcId [in] - VC identifier value of the VC to
- * be deregistered. This value was supplied to the client when
- the VC was originally registered. This value can also be
- queried from the IxAtmm component through the @ref ixAtmmVcQuery
- * interface.
- *
- * @return @li IX_SUCCESS : The specified VC has been successfully
- * removed from this port.
- * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the
- * input is not valid or has not been initialized. The request
- * is rejected.
- * @return @li IX_FAIL : There is no registered VC associated with the
- * supplied identifier registered on this port. */
-PUBLIC IX_STATUS
-ixAtmmVcDeregister (IxAtmLogicalPort port, IxAtmSchedulerVcId vcId);
-
-/**
- * @ingroup IxAtmm
- *
- * @fn ixAtmmVcQuery (IxAtmLogicalPort port,
- unsigned vpi,
- unsigned vci,
- IxAtmmVcDirection direction,
- IxAtmSchedulerVcId *vcId,
- IxAtmmVc *vcDesc)
- *
- * @brief This interface supplies information about an active VC on a
- * particular port when supplied with the VPI, VCI and
- * direction of that VC.
- *
- * @param port @ref IxAtmLogicalPort [in] - Identifies port on which the VC to be
- * queried is currently registered.
- *
- * @param vpi unsigned [in] - ATM VPI value of the requested VC.
- *
- * @param vci unsigned [in] - ATM VCI value of the requested VC.
- *
- * @param direction @ref IxAtmmVcDirection [in] - One of @ref
- * IX_ATMM_VC_DIRECTION_TX or @ref IX_ATMM_VC_DIRECTION_RX
- * indicating the direction (Tx or Rx) of the requested VC.
- *
- * @param *vcId @ref IxAtmSchedulerVcId [out] - Pointer to an integer value which will be
- * filled with the VC identifier value for the requested
- * VC (as returned by @ref ixAtmmVcRegister), if it
- * exists on this port.
- *
- * @param *vcDesc @ref IxAtmmVc [out] - Pointer to an @ref IxAtmmVc structure
- * which will be filled with the specific details of the
- * requested VC, if it exists on this port.
- *
- * @return @li IX_SUCCESS : The specified VC has been found on this port
- * and the requested details have been returned.
- * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the
- * input is not valid or has not been initialized. The request
- * is rejected.
- * @return @li IX_ATMM_RET_NO_SUCH_VC : No VC exists on the specified
- * port which matches the search criteria (VPI, VCI, direction)
- * given. No data is returned.
- * @return @li IX_ATMM_RET_INVALID_PARAM_PTR : A pointer parameter was
- * NULL.
- *
- */
-PUBLIC IX_STATUS
-ixAtmmVcQuery (IxAtmLogicalPort port,
- unsigned vpi,
- unsigned vci,
- IxAtmmVcDirection direction,
- IxAtmSchedulerVcId *vcId,
- IxAtmmVc *vcDesc);
-
-
-/**
- * @ingroup IxAtmm
- *
- * @fn ixAtmmVcIdQuery (IxAtmLogicalPort port, IxAtmSchedulerVcId vcId, IxAtmmVc *vcDesc)
- *
- * @brief This interface supplies information about an active VC on a
- * particular port when supplied with a vcId for that VC.
- *
- * @param port @ref IxAtmLogicalPort [in] - Identifies port on which the VC to be
- * queried is currently registered.
- *
- * @param vcId @ref IxAtmSchedulerVcId [in] - Value returned by @ref ixAtmmVcRegister which
- * uniquely identifies the requested VC on this port.
- *
- * @param *vcDesc @ref IxAtmmVc [out] - Pointer to an @ref IxAtmmVc structure
- * which will be filled with the specific details of the
- * requested VC, if it exists on this port.
- *
- * @return @li IX_SUCCESS : The specified VC has been found on this port
- * and the requested details have been returned.
- * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the
- * input is not valid or has not been initialized. The request
- * is rejected.
- * @return @li IX_ATMM_RET_NO_SUCH_VC : No VC exists on the specified
- * port which matches the supplied identifier. No data is
- * returned.
- * @return @li IX_ATMM_RET_INVALID_PARAM_PTR : A pointer parameter was
- * NULL.
- */
-PUBLIC IX_STATUS
-ixAtmmVcIdQuery (IxAtmLogicalPort port, IxAtmSchedulerVcId vcId, IxAtmmVc *vcDesc);
-
-/**
- * @ingroup IxAtmm
- *
- * @fn ixAtmmVcChangeCallbackRegister (IxAtmmVcChangeCallback callback)
- *
- * @brief This interface is invoked to supply a function to IxAtmm
- * which will be called to notify the client if a new VC is
- * registered with IxAtmm or an existing VC is removed.
- *
- * The callback, when invoked, will run within the context of the call
- * to @ref ixAtmmVcRegister or @ref ixAtmmVcDeregister which caused
- * the change of state.
- *
- * A maximum of 32 calbacks may be registered in with IxAtmm.
- *
- * @param callback @ref IxAtmmVcChangeCallback [in] - Callback which complies
- * with the @ref IxAtmmVcChangeCallback definition. This
- * function will be invoked by IxAtmm with the appropiate
- * parameters for the relevant VC when any VC has been
- * registered or deregistered with IxAtmm.
- *
- * @return @li IX_SUCCESS : The specified callback has been registered
- * successfully with IxAtmm and will be invoked when appropriate.
- * @return @li IX_FAIL : Either the supplied callback is invalid, or
- * IxAtmm has already registered 32 and connot accommodate
- * any further registrations of this type. The request is
- * rejected.
- *
- * @warning The client must not call either the @ref
- * ixAtmmVcRegister or @ref ixAtmmVcDeregister interfaces
- * from within the supplied callback function. */
-PUBLIC IX_STATUS ixAtmmVcChangeCallbackRegister (IxAtmmVcChangeCallback callback);
-
-
-/**
- * @ingroup IxAtmm
- *
- * @fn ixAtmmVcChangeCallbackDeregister (IxAtmmVcChangeCallback callback)
- *
- * @brief This interface is invoked to deregister a previously supplied
- * callback function.
- *
- * @param callback @ref IxAtmmVcChangeCallback [in] - Callback which complies
- * with the @ref IxAtmmVcChangeCallback definition. This
- * function will removed from the table of callbacks.
- *
- * @return @li IX_SUCCESS : The specified callback has been deregistered
- * successfully from IxAtmm.
- * @return @li IX_FAIL : Either the supplied callback is invalid, or
- * is not currently registered with IxAtmm.
- */
-PUBLIC IX_STATUS
-ixAtmmVcChangeCallbackDeregister (IxAtmmVcChangeCallback callback);
-
-/**
- * @ingroup IxAtmm
- *
- * @fn ixAtmmUtopiaStatusShow (void)
- *
- * @brief Display utopia status counters
- *
- * @param "none"
- *
- * @return @li IX_SUCCESS : Show function was successful
- * @return @li IX_FAIL : Internal failure
- */
-PUBLIC IX_STATUS
-ixAtmmUtopiaStatusShow (void);
-
-/**
- * @ingroup IxAtmm
- *
- * @fn ixAtmmUtopiaCfgShow (void)
- *
- * @brief Display utopia information(config registers and status registers)
- *
- * @param "none"
- *
- * @return @li IX_SUCCESS : Show function was successful
- * @return @li IX_FAIL : Internal failure
- */
-PUBLIC IX_STATUS
-ixAtmmUtopiaCfgShow (void);
-
-#endif
-/* IXATMM_H */
-
-/** @} */
+++ /dev/null
-/**
- * @file IxDmaAcc.h
- *
- * @date 15 October 2002
- *
- * @brief API of the IXP400 DMA Access Driver Component (IxDma)
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-/*---------------------------------------------------------------------
- Doxygen group definitions
- ---------------------------------------------------------------------*/
-
-#ifndef IXDMAACC_H
-#define IXDMAACC_H
-
-#include "IxOsal.h"
-#include "IxNpeDl.h"
-/**
- * @defgroup IxDmaTypes IXP400 DMA Types (IxDmaTypes)
- * @brief The common set of types used in the DMA component
- * @{
- */
-
-/**
- * @ingroup IxDmaTypes
- * @enum IxDmaReturnStatus
- * @brief Dma return status definitions
- */
-typedef enum
-{
- IX_DMA_SUCCESS = IX_SUCCESS, /**< DMA Transfer Success */
- IX_DMA_FAIL = IX_FAIL, /**< DMA Transfer Fail */
- IX_DMA_INVALID_TRANSFER_WIDTH, /**< Invalid transfer width */
- IX_DMA_INVALID_TRANSFER_LENGTH, /**< Invalid transfer length */
- IX_DMA_INVALID_TRANSFER_MODE, /**< Invalid transfer mode */
- IX_DMA_INVALID_ADDRESS_MODE, /**< Invalid address mode */
- IX_DMA_REQUEST_FIFO_FULL /**< DMA request queue is full */
-} IxDmaReturnStatus;
-
-/**
- * @ingroup IxDmaTypes
- * @enum IxDmaTransferMode
- * @brief Dma transfer mode definitions
- * @note Copy and byte swap, and copy and reverse modes only support multiples of word data length.
- */
-typedef enum
-{
- IX_DMA_COPY_CLEAR = 0, /**< copy and clear source*/
- IX_DMA_COPY, /**< copy */
- IX_DMA_COPY_BYTE_SWAP, /**< copy and byte swap (endian) */
- IX_DMA_COPY_REVERSE, /**< copy and reverse */
- IX_DMA_TRANSFER_MODE_INVALID /**< Invalid transfer mode */
-} IxDmaTransferMode;
-
-/**
- * @ingroup IxDmaTypes
- * @enum IxDmaAddressingMode
- * @brief Dma addressing mode definitions
- * @note Fixed source address to fixed destination address addressing mode is not supported.
- */
-typedef enum
-{
- IX_DMA_INC_SRC_INC_DST = 0, /**< Incremental source address to incremental destination address */
- IX_DMA_INC_SRC_FIX_DST, /**< Incremental source address to incremental destination address */
- IX_DMA_FIX_SRC_INC_DST, /**< Incremental source address to incremental destination address */
- IX_DMA_FIX_SRC_FIX_DST, /**< Incremental source address to incremental destination address */
- IX_DMA_ADDRESSING_MODE_INVALID /**< Invalid Addressing Mode */
-} IxDmaAddressingMode;
-
-/**
- * @ingroup IxDmaTypes
- * @enum IxDmaTransferWidth
- * @brief Dma transfer width definitions
- * @Note Fixed addresses (either source or destination) do not support burst transfer width.
- */
-typedef enum
-{
- IX_DMA_32_SRC_32_DST = 0, /**< 32-bit src to 32-bit dst */
- IX_DMA_32_SRC_16_DST, /**< 32-bit src to 16-bit dst */
- IX_DMA_32_SRC_8_DST, /**< 32-bit src to 8-bit dst */
- IX_DMA_16_SRC_32_DST, /**< 16-bit src to 32-bit dst */
- IX_DMA_16_SRC_16_DST, /**< 16-bit src to 16-bit dst */
- IX_DMA_16_SRC_8_DST, /**< 16-bit src to 8-bit dst */
- IX_DMA_8_SRC_32_DST, /**< 8-bit src to 32-bit dst */
- IX_DMA_8_SRC_16_DST, /**< 8-bit src to 16-bit dst */
- IX_DMA_8_SRC_8_DST, /**< 8-bit src to 8-bit dst */
- IX_DMA_8_SRC_BURST_DST, /**< 8-bit src to burst dst - Not supported for fixed destination address */
- IX_DMA_16_SRC_BURST_DST, /**< 16-bit src to burst dst - Not supported for fixed destination address */
- IX_DMA_32_SRC_BURST_DST, /**< 32-bit src to burst dst - Not supported for fixed destination address */
- IX_DMA_BURST_SRC_8_DST, /**< burst src to 8-bit dst - Not supported for fixed source address */
- IX_DMA_BURST_SRC_16_DST, /**< burst src to 16-bit dst - Not supported for fixed source address */
- IX_DMA_BURST_SRC_32_DST, /**< burst src to 32-bit dst - Not supported for fixed source address*/
- IX_DMA_BURST_SRC_BURST_DST, /**< burst src to burst dst - Not supported for fixed source and destination address
-*/
- IX_DMA_TRANSFER_WIDTH_INVALID /**< Invalid transfer width */
-} IxDmaTransferWidth;
-
-/**
- * @ingroup IxDmaTypes
- * @enum IxDmaNpeId
- * @brief NpeId numbers to identify NPE A, B or C
- */
-typedef enum
-{
- IX_DMA_NPEID_NPEA = 0, /**< Identifies NPE A */
- IX_DMA_NPEID_NPEB, /**< Identifies NPE B */
- IX_DMA_NPEID_NPEC, /**< Identifies NPE C */
- IX_DMA_NPEID_MAX /**< Total Number of NPEs */
-} IxDmaNpeId;
-/* @} */
-/**
- * @defgroup IxDmaAcc IXP400 DMA Access Driver (IxDmaAcc) API
- *
- * @brief The public API for the IXP400 IxDmaAcc component
- *
- * @{
- */
-
-/**
- * @ingroup IxDmaAcc
- * @brief DMA Request Id type
- */
-typedef UINT32 IxDmaAccRequestId;
-
-/**
- * @ingroup IxDmaAcc
- * @def IX_DMA_REQUEST_FULL
- * @brief DMA request queue is full
- * This constant is a return value used to tell the user that the IxDmaAcc
- * queue is full.
- *
- */
-#define IX_DMA_REQUEST_FULL 16
-
-/**
- * @ingroup IxDmaAcc
- * @brief DMA completion notification
- * This function is called to notify a client that the DMA has been completed
- * @param status @ref IxDmaReturnStatus [out] - reporting to client
- *
- */
-typedef void (*IxDmaAccDmaCompleteCallback) (IxDmaReturnStatus status);
-
-/**
- * @ingroup IxDmaAcc
- *
- * @fn ixDmaAccInit(IxNpeDlNpeId npeId)
- *
- * @brief Initialise the DMA Access component
- * This function will initialise the DMA Access component internals
- * @param npeId @ref IxNpeDlNpeId [in] - NPE to use for Dma Transfer
- * @return @li IX_SUCCESS succesfully initialised the component
- * @return @li IX_FAIL Initialisation failed for some unspecified
- * internal reason.
- */
-PUBLIC IX_STATUS
-ixDmaAccInit(IxNpeDlNpeId npeId);
-
-/**
- * @ingroup IxDmaAcc
- *
- * @fn ixDmaAccDmaTransfer(
- IxDmaAccDmaCompleteCallback callback,
- UINT32 SourceAddr,
- UINT32 DestinationAddr,
- UINT16 TransferLength,
- IxDmaTransferMode TransferMode,
- IxDmaAddressingMode AddressingMode,
- IxDmaTransferWidth TransferWidth)
- *
- * @brief Perform DMA transfer
- * This function will perform DMA transfer between devices within the
- * IXP400 memory map.
- * @note The following are restrictions for IxDmaAccDmaTransfer:
- * @li The function is non re-entrant.
- * @li The function assumes host devices are operating in big-endian mode.
- * @li Fixed address does not suport burst transfer width
- * @li Fixed source address to fixed destinatiom address mode is not suported
- * @li The incrementing source address for expansion bus will not support a burst transfer width and copy and clear mode
- *
- * @param callback @ref IxDmaAccDmaCompleteCallback [in] - function pointer to be stored and called when the DMA transfer is completed. This cannot be NULL.
- * @param SourceAddr UINT32 [in] - Starting address of DMA source. Must be a valid IXP400 memory map address.
- * @param DestinationAddr UINT32 [in] - Starting address of DMA destination. Must be a valid IXP400 memory map address.
- * @param TransferLength UINT16 [in] - The size of DMA data transfer. The range must be from 1-64Kbyte
- * @param TransferMode @ref IxDmaTransferMode [in] - The DMA transfer mode
- * @param AddressingMode @ref IxDmaAddressingMode [in] - The DMA addressing mode
- * @param TransferWidth @ref IxDmaTransferWidth [in] - The DMA transfer width
- *
- * @return @li IX_DMA_SUCCESS Notification that the DMA request is succesful
- * @return @li IX_DMA_FAIL IxDmaAcc not yet initialised or some internal error has occured
- * @return @li IX_DMA_INVALID_TRANSFER_WIDTH Transfer width is nit valid
- * @return @li IX_DMA_INVALID_TRANSFER_LENGTH Transfer length outside of valid range
- * @return @li IX_DMA_INVALID_TRANSFER_MODE Transfer Mode not valid
- * @return @li IX_DMA_REQUEST_FIFO_FULL IxDmaAcc request queue is full
- */
-PUBLIC IxDmaReturnStatus
-ixDmaAccDmaTransfer(
- IxDmaAccDmaCompleteCallback callback,
- UINT32 SourceAddr,
- UINT32 DestinationAddr,
- UINT16 TransferLength,
- IxDmaTransferMode TransferMode,
- IxDmaAddressingMode AddressingMode,
- IxDmaTransferWidth TransferWidth);
-/**
- * @ingroup IxDmaAcc
- *
- * @fn ixDmaAccShow(void)
- *
- * @brief Display some component information for debug purposes
- * Show some internal operation information relating to the DMA service.
- * At a minimum the following will show.
- * - the number of the DMA pend (in queue)
- * @param None
- * @return @li None
- */
-PUBLIC IX_STATUS
-ixDmaAccShow(void);
-
-#endif /* IXDMAACC_H */
-
+++ /dev/null
-/** @file IxEthAcc.h
- *
- * @brief this file contains the public API of @ref IxEthAcc component
- *
- * Design notes:
- * The IX_OSAL_MBUF address is to be specified on bits [31-5] and must
- * be cache aligned (bits[4-0] cleared)
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- *
- */
-
-#ifndef IxEthAcc_H
-#define IxEthAcc_H
-
-#include <IxOsBuffMgt.h>
-#include <IxTypes.h>
-
-/**
- * @defgroup IxEthAcc IXP400 Ethernet Access (IxEthAcc) API
- *
- * @brief ethAcc is a library that does provides access to the internal IXP400 10/100Bt Ethernet MACs.
- *
- *@{
- */
-
-/**
- * @ingroup IxEthAcc
- * @brief Definition of the Ethernet Access status
- */
-typedef enum /* IxEthAccStatus */
-{
- IX_ETH_ACC_SUCCESS = IX_SUCCESS, /**< return success*/
- IX_ETH_ACC_FAIL = IX_FAIL, /**< return fail*/
- IX_ETH_ACC_INVALID_PORT, /**< return invalid port*/
- IX_ETH_ACC_PORT_UNINITIALIZED, /**< return uninitialized*/
- IX_ETH_ACC_MAC_UNINITIALIZED, /**< return MAC uninitialized*/
- IX_ETH_ACC_INVALID_ARG, /**< return invalid arg*/
- IX_ETH_TX_Q_FULL, /**< return tx queue is full*/
- IX_ETH_ACC_NO_SUCH_ADDR /**< return no such address*/
-} IxEthAccStatus;
-
-/**
- * @ingroup IxEthAcc
- * @enum IxEthAccPortId
- * @brief Definition of the IXP400 Mac Ethernet device.
- */
-typedef enum
-{
- IX_ETH_PORT_1 = 0, /**< Ethernet Port 1 */
- IX_ETH_PORT_2 = 1 /**< Ethernet port 2 */
- ,IX_ETH_PORT_3 = 2 /**< Ethernet port 3 */
-} IxEthAccPortId;
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETH_ACC_NUMBER_OF_PORTS
- *
- * @brief Definition of the number of ports
- *
- */
-#ifdef __ixp46X
-#define IX_ETH_ACC_NUMBER_OF_PORTS (3)
-#else
-#define IX_ETH_ACC_NUMBER_OF_PORTS (2)
-#endif
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_IEEE803_MAC_ADDRESS_SIZE
- *
- * @brief Definition of the size of the MAC address
- *
- */
-#define IX_IEEE803_MAC_ADDRESS_SIZE (6)
-
-
-/**
- *
- * @brief Definition of the IEEE 802.3 Ethernet MAC address structure.
- *
- * The data should be packed with bytes xx:xx:xx:xx:xx:xx
- * @note
- * The data must be packed in network byte order.
- */
-typedef struct
-{
- UINT8 macAddress[IX_IEEE803_MAC_ADDRESS_SIZE]; /**< MAC address */
-} IxEthAccMacAddr;
-
-/**
- * @ingroup IxEthAcc
- * @def IX_ETH_ACC_NUM_TX_PRIORITIES
- * @brief Definition of the number of transmit priorities
- *
- */
-#define IX_ETH_ACC_NUM_TX_PRIORITIES (8)
-
-/**
- * @ingroup IxEthAcc
- * @enum IxEthAccTxPriority
- * @brief Definition of the relative priority used to transmit a frame
- *
- */
-typedef enum
-{
- IX_ETH_ACC_TX_PRIORITY_0 = 0, /**<Lowest Priority submission */
- IX_ETH_ACC_TX_PRIORITY_1 = 1, /**<submission prority of 1 (0 is lowest)*/
- IX_ETH_ACC_TX_PRIORITY_2 = 2, /**<submission prority of 2 (0 is lowest)*/
- IX_ETH_ACC_TX_PRIORITY_3 = 3, /**<submission prority of 3 (0 is lowest)*/
- IX_ETH_ACC_TX_PRIORITY_4 = 4, /**<submission prority of 4 (0 is lowest)*/
- IX_ETH_ACC_TX_PRIORITY_5 = 5, /**<submission prority of 5 (0 is lowest)*/
- IX_ETH_ACC_TX_PRIORITY_6 = 6, /**<submission prority of 6 (0 is lowest)*/
- IX_ETH_ACC_TX_PRIORITY_7 = 7, /**<Highest priority submission */
-
- IX_ETH_ACC_TX_DEFAULT_PRIORITY = IX_ETH_ACC_TX_PRIORITY_0 /**< By default send all
- packets with lowest priority */
-} IxEthAccTxPriority;
-
-/**
- * @ingroup IxEthAcc
- * @enum IxEthAccRxFrameType
- * @brief Identify the type of a frame.
- *
- * @sa IX_ETHACC_NE_FLAGS
- * @sa IX_ETHACC_NE_LINKMASK
- */
-typedef enum
-{
- IX_ETHACC_RX_LLCTYPE = 0x00, /**< 802.3 - 8802, with LLC/SNAP */
- IX_ETHACC_RX_ETHTYPE = 0x10, /**< 802.3 (Ethernet) without LLC/SNAP */
- IX_ETHACC_RX_STATYPE = 0x20, /**< 802.11, AP <=> STA */
- IX_ETHACC_RX_APTYPE = 0x30 /**< 802.11, AP <=> AP */
-} IxEthAccRxFrameType;
-
-/**
- * @ingroup IxEthAcc
- * @enum IxEthAccDuplexMode
- * @brief Definition to provision the duplex mode of the MAC.
- *
- */
-typedef enum
-{
- IX_ETH_ACC_FULL_DUPLEX, /**< Full duplex operation of the MAC */
- IX_ETH_ACC_HALF_DUPLEX /**< Half duplex operation of the MAC */
-} IxEthAccDuplexMode;
-
-
-/**
- * @ingroup IxEthAcc
- * @struct IxEthAccNe
- * @brief Definition of service-specific informations.
- *
- * This structure defines the Ethernet service-specific informations
- * and enable QoS and VLAN features.
- */
-typedef struct
-{
- UINT32 ixReserved_next; /**< reserved for chaining */
- UINT32 ixReserved_lengths; /**< reserved for buffer lengths */
- UINT32 ixReserved_data; /**< reserved for buffer pointer */
- UINT8 ixDestinationPortId; /**< Destination portId for this packet, if known by NPE */
- UINT8 ixSourcePortId; /**< Source portId for this packet */
- UINT16 ixFlags; /**< BitField of option for this frame */
- UINT8 ixQoS; /**< QoS class of the frame */
- UINT8 ixReserved; /**< reserved */
- UINT16 ixVlanTCI; /**< Vlan TCI */
- UINT8 ixDestMac[IX_IEEE803_MAC_ADDRESS_SIZE]; /**< Destination MAC address */
- UINT8 ixSourceMac[IX_IEEE803_MAC_ADDRESS_SIZE]; /**< Source MAC address */
-} IxEthAccNe;
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_PORT_UNKNOWN
- *
- * @brief Contents of the field @a IX_ETHACC_NE_DESTPORTID when no
- * destination port can be found by the NPE for this frame.
- *
- */
-#define IX_ETHACC_NE_PORT_UNKNOWN (0xff)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_DESTMAC
- *
- * @brief The location of the destination MAC address in the Mbuf header.
- *
- */
-#define IX_ETHACC_NE_DESTMAC(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixDestMac
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_SOURCEMAC
- *
- * @brief The location of the source MAC address in the Mbuf header.
- *
- */
-#define IX_ETHACC_NE_SOURCEMAC(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixSourceMac
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_VLANTCI
- *
- * @brief The VLAN Tag Control Information associated with this frame
- *
- * The VLAN Tag Control Information associated with this frame. On Rx
- * path, this field is extracted from the packet header.
- * On Tx path, the value of this field is inserted in the frame when
- * the port is configured to insert or replace vlan tags in the
- * egress frames.
- *
- * @sa IX_ETHACC_NE_FLAGS
- */
-#define IX_ETHACC_NE_VLANTCI(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixVlanTCI
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_SOURCEPORTID
- *
- * @brief The port where this frame came from.
- *
- * The port where this frame came from. This field is set on receive
- * with the port information. This field is ignored on Transmit path.
- */
-#define IX_ETHACC_NE_SOURCEPORTID(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixSourcePortId
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_DESTPORTID
- *
- * @brief The destination port where this frame should be sent.
- *
- * The destination port where this frame should be sent.
- *
- * @li In the transmit direction, this field contains the destination port
- * and is ignored unless @a IX_ETHACC_NE_FLAG_DST is set.
- *
- * @li In the receive direction, this field contains the port where the
- * destination MAC addresses has been learned. If the destination
- * MAC address is unknown, then this value is set to the reserved value
- * @a IX_ETHACC_NE_PORT_UNKNOWN
- *
- */
-#define IX_ETHACC_NE_DESTPORTID(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixDestinationPortId
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_QOS
- *
- * @brief QualityOfService class (QoS) for this received frame.
- *
- */
-#define IX_ETHACC_NE_QOS(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixQoS
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_FLAGS
- *
- * @brief Bit Mask of the different flags associated with a frame
- *
- * The flags are the bit-oring combination
- * of the following different fields :
- *
- * @li IP flag (Rx @a IX_ETHACC_NE_IPMASK)
- * @li Spanning Tree flag (Rx @a IX_ETHACC_NE_STMASK)
- * @li Link layer type (Rx and Tx @a IX_ETHACC_NE_LINKMASK)
- * @li VLAN Tagged Frame (Rx @a IX_ETHACC_NE_VLANMASK)
- * @li New source MAC address (Rx @a IX_ETHACC_NE_NEWSRCMASK)
- * @li Multicast flag (Rx @a IX_ETHACC_NE_MCASTMASK)
- * @li Broadcast flag (Rx @a IX_ETHACC_NE_BCASTMASK)
- * @li Destination port flag (Tx @a IX_ETHACC_NE_PORTMASK)
- * @li Tag/Untag Tx frame (Tx @a IX_ETHACC_NE_TAGMODEMASK)
- * @li Overwrite destination port (Tx @a IX_ETHACC_NE_PORTOVERMASK)
- * @li Filtered frame (Rx @a IX_ETHACC_NE_STMASK)
- * @li VLAN Enabled (Rx and Tx @a IX_ETHACC_NE_VLANENABLEMASK)
- */
-#define IX_ETHACC_NE_FLAGS(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixFlags
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_BCASTMASK
- *
- * @brief This mask defines if a received frame is a broadcast frame.
- *
- * This mask defines if a received frame is a broadcast frame.
- * The BCAST flag is set when the destination MAC address of
- * a frame is broadcast.
- *
- * @sa IX_ETHACC_NE_FLAGS
- *
- */
-#define IX_ETHACC_NE_BCASTMASK (0x1)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_MCASTMASK
- *
- * @brief This mask defines if a received frame is a multicast frame.
- *
- * This mask defines if a received frame is a multicast frame.
- * The MCAST flag is set when the destination MAC address of
- * a frame is multicast.
- *
- * @sa IX_ETHACC_NE_FLAGS
- *
- */
-#define IX_ETHACC_NE_MCASTMASK (0x1 << 1)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_IPMASK
- *
- * @brief This mask defines if a received frame is a IP frame.
- *
- * This mask applies to @a IX_ETHACC_NE_FLAGS and defines if a received
- * frame is a IP frame. The IP flag is set on Rx direction, depending on
- * the frame contents. The flag is set when the length/type field of a
- * received frame is 0x8000.
- *
- * @sa IX_ETHACC_NE_FLAGS
- *
- */
-#define IX_ETHACC_NE_IPMASK (0x1 << 2)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_VLANMASK
- *
- * @brief This mask defines if a received frame is VLAN tagged.
- *
- * This mask defines if a received frame is VLAN tagged.
- * When set, the Rx frame is VLAN-tagged and the tag value
- * is available thru @a IX_ETHACC_NE_VLANID.
- * Note that when sending frames which are already tagged
- * this flag should be set, to avoid inserting another VLAN tag.
- *
- * @sa IX_ETHACC_NE_FLAGS
- * @sa IX_ETHACC_NE_VLANID
- *
- */
-#define IX_ETHACC_NE_VLANMASK (0x1 << 3)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_LINKMASK
- *
- * @brief This mask is the link layer protocol indicator
- *
- * This mask applies to @a IX_ETHACC_NE_FLAGS.
- * It reflects the state of a frame as it exits an NPE on the Rx path
- * or enters an NPE on the Tx path. Its values are as follows:
- * @li 0x00 - IEEE802.3 - 8802 (Rx) / IEEE802.3 - 8802 (Tx)
- * @li 0x01 - IEEE802.3 - Ethernet (Rx) / IEEE802.3 - Ethernet (Tx)
- * @li 0x02 - IEEE802.11 AP -> STA (Rx) / IEEE802.11 STA -> AP (Tx)
- * @li 0x03 - IEEE802.11 AP -> AP (Rx) / IEEE802.11 AP->AP (Tx)
- *
- * @sa IX_ETHACC_NE_FLAGS
- *
- */
-#define IX_ETHACC_NE_LINKMASK (0x3 << 4)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_STMASK
- *
- * @brief This mask defines if a received frame is a Spanning Tree frame.
- *
- * This mask applies to @a IX_ETHACC_NE_FLAGS.
- * On rx direction, it defines if a received if frame is a Spanning Tree frame.
- * Setting this fkag on transmit direction overrides the port settings
- * regarding the VLAN options and
- *
- * @sa IX_ETHACC_NE_FLAGS
- *
- */
-#define IX_ETHACC_NE_STMASK (0x1 << 6)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_FILTERMASK
- *
- * @brief This bit indicates whether a frame has been filtered by the Rx service.
- *
- * This mask applies to @a IX_ETHACC_NE_FLAGS.
- * Certain frames, which should normally be fully filtered by the NPE to due
- * the destination MAC address being on the same segment as the Rx port are
- * still forwarded to the XScale (although the payload is invalid) in order
- * to learn the MAC address of the transmitting station, if this is unknown.
- * Normally EthAcc will filter and recycle these framess internally and no
- * frames with the FILTER bit set will be received by the client.
- *
- * @sa IX_ETHACC_NE_FLAGS
- *
- */
-#define IX_ETHACC_NE_FILTERMASK (0x1 << 7)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_PORTMASK
- *
- * @brief This mask defines the rule to transmit a frame
- *
- * This mask defines the rule to transmit a frame. When set, a frame
- * is transmitted to the destination port as set by the macro
- * @a IX_ETHACC_NE_DESTPORTID. If not set, the destination port
- * is searched using the destination MAC address.
- *
- * @note This flag is meaningful only for multiport Network Engines.
- *
- * @sa IX_ETHACC_NE_FLAGS
- * @sa IX_ETHACC_NE_DESTPORTID
- *
- */
-#define IX_ETHACC_NE_PORTOVERMASK (0x1 << 8)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_TAGMODEMASK
- *
- * @brief This mask defines the tagging rules to apply to a transmit frame.
- *
- * This mask defines the tagging rules to apply to a transmit frame
- * regardless of the default setting for a port. When used together
- * with @a IX_ETHACC_NE_TAGOVERMASK and when set, the
- * frame will be tagged prior to transmission. When not set,
- * the frame will be untagged prior to transmission. This is accomplished
- * irrespective of the Egress tagging rules, constituting a per-frame override.
- *
- * @sa IX_ETHACC_NE_FLAGS
- * @sa IX_ETHACC_NE_TAGOVERMASK
- *
- */
-#define IX_ETHACC_NE_TAGMODEMASK (0x1 << 9)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_TAGOVERMASK
- *
- * @brief This mask defines the rule to transmit a frame
- *
- * This mask defines the rule to transmit a frame. When set, the
- * default transmit rules of a port are overriden.
- * When not set, the default rules as set by @ref IxEthDB should apply.
- *
- * @sa IX_ETHACC_NE_FLAGS
- * @sa IX_ETHACC_NE_TAGMODEMASK
- *
- */
-#define IX_ETHACC_NE_TAGOVERMASK (0x1 << 10)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_VLANENABLEMASK
- *
- * @brief This mask defines if a frame is a VLAN frame or not
- *
- * When set, frames undergo normal VLAN processing on the Tx path
- * (membership filtering, tagging, tag removal etc). If this flag is
- * not set, the frame is considered to be a regular non-VLAN frame
- * and no VLAN processing will be performed.
- *
- * Note that VLAN-enabled NPE images will always set this flag in all
- * Rx frames, and images which are not VLAN enabled will clear this
- * flag for all received frames.
- *
- * @sa IX_ETHACC_NE_FLAGS
- *
- */
-#define IX_ETHACC_NE_VLANENABLEMASK (0x1 << 14)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IX_ETHACC_NE_NEWSRCMASK
- *
- * @brief This mask defines if a received frame has been learned.
- *
- * This mask defines if the source MAC address of a frame is
- * already known. If the bit is set, the source MAC address was
- * unknown to the NPE at the time the frame was received.
- *
- * @sa IX_ETHACC_NE_FLAGS
- *
- */
-#define IX_ETHACC_NE_NEWSRCMASK (0x1 << 15)
-
-/**
- * @ingroup IxEthAcc
- *
- * @brief This defines the recommanded minimum size of MBUF's submitted
- * to the frame receive service.
- *
- */
-#define IX_ETHACC_RX_MBUF_MIN_SIZE (2048)
-
-/**
- * @ingroup IxEthAcc
- *
- * @brief This defines the highest MII address of any attached PHYs
- *
- * The maximum number for PHY address is 31, add on for range checking.
- *
- */
-#define IXP425_ETH_ACC_MII_MAX_ADDR 32
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccInit(void)
- *
- * @brief Initializes the IXP400 Ethernet Access Service.
- *
- * @li Reentrant - no
- * @li ISR Callable - no
- *
- * This should be called once per module initialization.
- * @pre
- * The NPE must first be downloaded with the required microcode which supports all
- * required features.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : Service has failed to initialize.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccInit(void);
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccUnload(void)
- *
- * @brief Unload the Ethernet Access Service.
- *
- * @li Reentrant - no
- * @li ISR Callable - no
- *
- * @return void
- *
- * <hr>
- */
-PUBLIC void ixEthAccUnload(void);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortInit( IxEthAccPortId portId)
- *
- * @brief Initializes an NPE/Ethernet MAC Port.
- *
- * The NPE/Ethernet port initialisation includes the following steps
- * @li Initialize the NPE/Ethernet MAC hardware.
- * @li Verify NPE downloaded and operational.
- * @li The NPE shall be available for usage once this API returns.
- * @li Verify that the Ethernet port is present before initializing
- *
- * @li Reentrant - no
- * @li ISR Callable - no
- *
- * This should be called once per mac device.
- * The NPE/MAC shall be in disabled state after init.
- *
- * @pre
- * The component must be initialized via @a ixEthAccInit
- * The NPE must first be downloaded with the required microcode which supports all
- * required features.
- *
- * Dependant on Services: (Must be initialized before using this service may be initialized)
- * ixNPEmh - NPE Message handling service.
- * ixQmgr - Queue Manager component.
- *
- * @param portId @ref IxEthAccPortId [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS: if the ethernet port is not present, a warning is issued.
- * @li @a IX_ETH_ACC_FAIL : The NPE processor has failed to initialize.
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccPortInit(IxEthAccPortId portId);
-
-
-/*************************************************************************
-
- ##### ## ##### ## ##### ## ##### # #
- # # # # # # # # # # # # # #
- # # # # # # # # # # # # ######
- # # ###### # ###### ##### ###### # # #
- # # # # # # # # # # # # #
- ##### # # # # # # # # # # #
-
-*************************************************************************/
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortTxFrameSubmit(
- IxEthAccPortId portId,
- IX_OSAL_MBUF *buffer,
- IxEthAccTxPriority priority)
- *
- * @brief This function shall be used to submit MBUFs buffers for transmission on a particular MAC device.
- *
- * When the frame is transmitted, the buffer shall be returned thru the
- * callback @a IxEthAccPortTxDoneCallback.
- *
- * In case of over-submitting, the order of the frames on the
- * network may be modified.
- *
- * Buffers shall be not queued for transmission if the port is disabled.
- * The port can be enabled using @a ixEthAccPortEnable
- *
- *
- * @li Reentrant - yes
- * @li ISR Callable - yes
- *
- *
- * @pre
- * @a ixEthAccPortTxDoneCallbackRegister must be called to register a function to allow this service to
- * return the buffer to the calling service.
- *
- * @note
- * If the buffer submit fails for any reason the user has retained ownership of the buffer.
- *
- * @param portId @ref IxEthAccPortId [in] - MAC port ID to transmit Ethernet frame on.
- * @param buffer @ref IX_OSAL_MBUF [in] - pointer to an MBUF formatted buffer. Chained buffers are supported for transmission.
- * Chained packets are not supported and the field IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR is ignored.
- * @param priority @ref IxEthAccTxPriority [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : Failed to queue frame for transmission.
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-
-PUBLIC IxEthAccStatus ixEthAccPortTxFrameSubmit(
- IxEthAccPortId portId,
- IX_OSAL_MBUF *buffer,
- IxEthAccTxPriority priority);
-
-/**
- * @ingroup IxEthAcc
- *
- * @brief Function prototype for Ethernet Tx Buffer Done callback. Registered
- * via @a ixEthAccTxBufferDoneCallbackRegister
- *
- * This function is called once the previously submitted buffer is no longer required by this service.
- * It may be returned upon successful transmission of the frame or during the shutdown of
- * the port prior to the transmission of a queued frame.
- * The calling of this registered function is not a guarantee of successful transmission of the buffer.
- *
- *
- * @li Reentrant - yes , The user provided function should be reentrant.
- * @li ISR Callable - yes , The user provided function must be callable from an ISR.
- *
- *
- * <b>Calling Context </b>:
- * @par
- * This callback is called in the context of the queue manager dispatch loop @a ixQmgrgrDispatcherLoopRun
- * within the @ref IxQMgrAPI component. The calling context may be from interrupt or high priority thread.
- * The decision is system specific.
- *
- * @param callbackTag UINT32 [in] - This tag is that provided when the callback was registered for a particular MAC
- * via @a ixEthAccPortTxDoneCallbackRegister. It allows the same callback to be used for multiple MACs.
- * @param mbuf @ref IX_OSAL_MBUF [in] - Pointer to the Tx mbuf descriptor.
- *
- * @return void
- *
- * @note
- * The field IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR is modified by the access layer and reset to NULL.
- *
- * <hr>
- */
-typedef void (*IxEthAccPortTxDoneCallback) ( UINT32 callbackTag, IX_OSAL_MBUF *buffer );
-
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortTxDoneCallbackRegister( IxEthAccPortId portId,
- IxEthAccPortTxDoneCallback txCallbackFn,
- UINT32 callbackTag)
- *
- * @brief Register a callback function to allow
- * the transmitted buffers to return to the user.
- *
- * This function registers the transmit buffer done function callback for a particular port.
- *
- * The registered callback function is called once the previously submitted buffer is no longer required by this service.
- * It may be returned upon successful transmission of the frame or shutdown of port prior to submission.
- * The calling of this registered function is not a guarantee of successful transmission of the buffer.
- *
- * If called several times the latest callback shall be registered for a particular port.
- *
- * @li Reentrant - yes
- * @li ISR Callable - yes
- *
- * @pre
- * The port must be initialized via @a ixEthAccPortInit
- *
- *
- * @param portId @ref IxEthAccPortId [in] - Register callback for a particular MAC device.
- * @param txCallbackFn @ref IxEthAccPortTxDoneCallback [in] - Function to be called to return transmit buffers to the user.
- * @param callbackTag UINT32 [in] - This tag shall be provided to the callback function.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- * @li @a IX_ETH_ACC_INVALID_ARG : An argument other than portId is invalid.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortTxDoneCallbackRegister(IxEthAccPortId portId,
- IxEthAccPortTxDoneCallback txCallbackFn,
- UINT32 callbackTag);
-
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @brief Function prototype for Ethernet Frame Rx callback. Registered via @a ixEthAccPortRxCallbackRegister
- *
- * It is the responsibility of the user function to free any MBUF's which it receives.
- *
- * @li Reentrant - yes , The user provided function should be reentrant.
- * @li ISR Callable - yes , The user provided function must be callable from an ISR.
- * @par
- *
- * This function dispatches frames to the user level
- * via the provided function. The invocation shall be made for each
- * frame dequeued from the Ethernet QM queue. The user is required to free any MBUF's
- * supplied via this callback. In addition the registered callback must free up MBUF's
- * from the receive free queue when the port is disabled
- *
- * If called several times the latest callback shall be registered for a particular port.
- *
- * <b>Calling Context </b>:
- * @par
- * This callback is called in the context of the queue manager dispatch loop @a ixQmgrgrDispatcherLoopRun
- * within the @ref IxQMgrAPI component. The calling context may be from interrupt or high priority thread.
- * The decision is system specific.
- *
- *
- * @param callbackTag UINT32 [in] - This tag is that provided when the callback was registered for a particular MAC
- * via @a ixEthAccPortRxCallbackRegister. It allows the same callback to be used for multiple MACs.
- * @param mbuf @ref IX_OSAL_MBUF [in] - Pointer to the Rx mbuf header. Mbufs may be chained if
- * the frame length is greater than the supplied mbuf length.
- * @param reserved [in] - deprecated parameter The information is passed
- * thru the IxEthAccNe header destination port ID field
- * (@sa IX_ETHACC_NE_DESTPORTID). For backward
- * compatibility,the value is equal to IX_ETH_DB_UNKNOWN_PORT (0xff).
- *
- * @return void
- *
- * @note
- * Buffers may not be filled up to the length supplied in
- * @a ixEthAccPortRxFreeReplenish(). The firmware fills
- * them to the previous 64 bytes boundary. The user has to be aware
- * that the length of the received mbufs may be smaller than the length
- * of the supplied mbufs.
- * The mbuf header contains the following modified field
- * @li @a IX_OSAL_MBUF_PKT_LEN is set in the header of the first mbuf and indicates
- * the total frame size
- * @li @a IX_OSAL_MBUF_MLEN is set each mbuf header and indicates the payload length
- * @li @a IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR contains a pointer to the next
- * mbuf, or NULL at the end of a chain.
- * @li @a IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR is modified. Its value is reset to NULL
- * @li @a IX_OSAL_MBUF_FLAGS contains the bit 4 set for a broadcast packet and the bit 5
- * set for a multicast packet. Other bits are unmodified.
- *
- * <hr>
- */
-typedef void (*IxEthAccPortRxCallback) (UINT32 callbackTag, IX_OSAL_MBUF *buffer, UINT32 reserved);
-
-/**
- * @ingroup IxEthAcc
- *
- * @brief Function prototype for Ethernet Frame Rx callback. Registered via @a ixEthAccPortMultiBufferRxCallbackRegister
- *
- * It is the responsibility of the user function to free any MBUF's which it receives.
- *
- * @li Reentrant - yes , The user provided function should be reentrant.
- * @li ISR Callable - yes , The user provided function must be callable from an ISR.
- * @par
- *
- * This function dispatches many frames to the user level
- * via the provided function. The invocation shall be made for multiple frames
- * dequeued from the Ethernet QM queue. The user is required to free any MBUF's
- * supplied via this callback. In addition the registered callback must free up MBUF's
- * from the receive free queue when the port is disabled
- *
- * If called several times the latest callback shall be registered for a particular port.
- *
- * <b>Calling Context </b>:
- * @par
- * This callback is called in the context of the queue manager dispatch loop @a ixQmgrDispatcherLoopRun
- * within the @ref IxQMgrAPI component. The calling context may be from interrupt or high priority thread.
- * The decision is system specific.
- *
- *
- * @param callbackTag - This tag is that provided when the callback was registered for a particular MAC
- * via @a ixEthAccPortMultiBufferRxCallbackRegister. It allows the same callback to be used for multiple MACs.
- * @param mbuf - Pointer to an array of Rx mbuf headers. Mbufs
- * may be chained if
- * the frame length is greater than the supplied mbuf length.
- * The end of the array contains a zeroed entry (NULL pointer).
- *
- * @return void
- *
- * @note The mbufs passed to this callback have the same structure than the
- * buffers passed to @a IxEthAccPortRxCallback interfac.
- *
- * @note The usage of this callback is exclusive with the usage of
- * @a ixEthAccPortRxCallbackRegister and @a IxEthAccPortRxCallback
- *
- * @sa ixEthAccPortMultiBufferRxCallbackRegister
- * @sa IxEthAccPortMultiBufferRxCallback
- * @sa ixEthAccPortRxCallbackRegister
- * @sa IxEthAccPortRxCallback
- * <hr>
- */
-
-typedef void (*IxEthAccPortMultiBufferRxCallback) (UINT32 callbackTag, IX_OSAL_MBUF **buffer);
-
-
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortRxCallbackRegister( IxEthAccPortId portId, IxEthAccPortRxCallback rxCallbackFn, UINT32 callbackTag)
- *
- * @brief Register a callback function to allow
- * the reception of frames.
- *
- * The registered callback function is called once a frame is received by this service.
- *
- * If called several times the latest callback shall be registered for a particular port.
- *
- *
- * @li Reentrant - yes
- * @li ISR Callable - yes
- *
- *
- * @param portId @ref IxEthAccPortId [in] - Register callback for a particular MAC device.
- * @param rxCallbackFn @ref IxEthAccPortRxCallback [in] - Function to be called when Ethernet frames are availble.
- * @param callbackTag UINT32 [in] - This tag shall be provided to the callback function.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- * @li @a IX_ETH_ACC_INVALID_ARG : An argument other than portId is invalid.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortRxCallbackRegister(IxEthAccPortId portId,
- IxEthAccPortRxCallback rxCallbackFn,
- UINT32 callbackTag);
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortMultiBufferRxCallbackRegister( IxEthAccPortId portId, IxEthAccPortMultiBufferRxCallback rxCallbackFn, UINT32 callbackTag)
- *
- * @brief Register a callback function to allow
- * the reception of frames.
- *
- * The registered callback function is called once a frame is
- * received by this service. If many frames are already received,
- * the function is called once.
- *
- * If called several times the latest callback shall be registered for a particular port.
- *
- * @li Reentrant - yes
- * @li ISR Callable - yes
- *
- *
- * @param portId - Register callback for a particular MAC device.
- * @param rxCallbackFn - @a IxEthAccMultiBufferRxCallbackFn - Function to be called when Ethernet frames are availble.
- * @param callbackTag - This tag shall be provided to the callback function.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- * @li @a IX_ETH_ACC_INVALID_ARG : An argument other than portId is invalid.
- *
- * @sa ixEthAccPortMultiBufferRxCallbackRegister
- * @sa IxEthAccPortMultiBufferRxCallback
- * @sa ixEthAccPortRxCallbackRegister
- * @sa IxEthAccPortRxCallback
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortMultiBufferRxCallbackRegister(IxEthAccPortId portId,
- IxEthAccPortMultiBufferRxCallback rxCallbackFn,
- UINT32 callbackTag);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortRxFreeReplenish( IxEthAccPortId portId, IX_OSAL_MBUF *buffer)
- *
- * @brief This function provides buffers for the Ethernet receive path.
- *
- * This component does not have a buffer management mechanisms built in. All Rx buffers must be supplied to it
- * via this interface.
- *
- * @li Reentrant - yes
- * @li ISR Callable - yes
- *
- * @param portId @ref IxEthAccPortId [in] - Provide buffers only to specific Rx MAC.
- * @param buffer @ref IX_OSAL_MBUF [in] - Provide an MBUF to the Ethernet receive mechanism.
- * Buffers size smaller than IX_ETHACC_RX_MBUF_MIN_SIZE may result in poor
- * performances and excessive buffer chaining. Buffers
- * larger than this size may be suitable for jumbo frames.
- * Chained packets are not supported and the field IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR must be NULL.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : Buffer has was not able to queue the
- * buffer in the receive service.
- * @li @a IX_ETH_ACC_FAIL : Buffer size is less than IX_ETHACC_RX_MBUF_MIN_SIZE
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * @note
- * If the buffer replenish operation fails it is the responsibility
- * of the user to free the buffer.
- *
- * @note
- * Sufficient buffers must be supplied to the component to maintain
- * receive throughput and avoid rx buffer underflow conditions.
- * To meet this goal, It is expected that the user preload the
- * component with a sufficent number of buffers prior to enabling the
- * NPE Ethernet receive path. The recommended minimum number of
- * buffers is 8.
- *
- * @note
- * For maximum performances, the mbuf size should be greater
- * than the maximum frame size (Ethernet header, payload and FCS) + 64.
- * Supplying smaller mbufs to the service results in mbuf
- * chaining and degraded performances. The recommended size
- * is @a IX_ETHACC_RX_MBUF_MIN_SIZE, which is
- * enough to take care of 802.3 frames and "baby jumbo" frames without
- * chaining, and "jumbo" frame within chaining.
- *
- * @note
- * Buffers may not be filled up to their length. The firware fills
- * them up to the previous 64 bytes boundary. The user has to be aware
- * that the length of the received mbufs may be smaller than the length
- * of the supplied mbufs.
- *
- * @warning This function checks the parameters if the NDEBUG
- * flag is not defined. Turning on the argument checking (disabled by
- * default) results in a lower EthAcc performance as this function
- * is part of the data path.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortRxFreeReplenish( IxEthAccPortId portId, IX_OSAL_MBUF *buffer);
-
-
-
-/***************************************************************
-
- #### #### # # ##### ##### #### #
- # # # # ## # # # # # # #
- # # # # # # # # # # # #
- # # # # # # # ##### # # #
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- #### #### # # # # # #### ######
-
-
- ##### # ## # # ######
- # # # # # ## # #
- # # # # # # # # #####
- ##### # ###### # # # #
- # # # # # ## #
- # ###### # # # # ######
-
-***************************************************************/
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortEnable(IxEthAccPortId portId)
- *
- * @brief This enables an Ethernet port for both Tx and Rx.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @pre The port must first be initialized via @a ixEthAccPortInit and the MAC address
- * must be set using @a ixEthAccUnicastMacAddressSet before enabling it
- * The rx and Tx Done callbacks registration via @a
- * ixEthAccPortTxDoneCallbackRegister amd @a ixEthAccPortRxCallbackRegister
- * has to be done before enabling the traffic.
- *
- * @param portId @ref IxEthAccPortId [in] - Port id to act upon.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is not initialized
- * @li @a IX_ETH_ACC_MAC_UNINITIALIZED : port MAC address is not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccPortEnable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortDisable(IxEthAccPortId portId)
- *
- * @brief This disables an Ethernet port for both Tx and Rx.
- *
- * Free MBufs are returned to the user via the registered callback when the port is disabled
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @pre The port must be enabled with @a ixEthAccPortEnable, otherwise this
- * function has no effect
- *
- * @param portId @ref IxEthAccPortId [in] - Port id to act upon.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is not initialized
- * @li @a IX_ETH_ACC_MAC_UNINITIALIZED : port MAC address is not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccPortDisable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortEnabledQuery(IxEthAccPortId portId, BOOL *enabled)
- *
- * @brief Get the enabled state of a port.
- *
- * @li Reentrant - yes
- * @li ISR Callable - yes
- *
- * @pre The port must first be initialized via @a ixEthAccPortInit
- *
- * @param portId @ref IxEthAccPortId [in] - Port id to act upon.
- * @param enabled BOOL [out] - location to store the state of the port
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortEnabledQuery(IxEthAccPortId portId, BOOL *enabled);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortPromiscuousModeClear(IxEthAccPortId portId)
- *
- * @brief Put the Ethernet MAC device in non-promiscuous mode.
- *
- * In non-promiscuous mode the MAC filters all frames other than
- * destination MAC address which matches the following criteria:
- * @li Unicast address provisioned via @a ixEthAccUnicastMacAddressSet
- * @li All broadcast frames.
- * @li Multicast addresses provisioned via @a ixEthAccMulticastAddressJoin
- *
- * Other functions modify the MAC filtering
- *
- * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast
- * frames are forwarded to the application
- * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the
- * effects of @a ixEthAccPortMulticastAddressJoinAll()
- * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new
- * filtering address
- * @li @a ixEthAccPortMulticastAddressJoin() - provision a new
- * filtering address
- * @li @a ixEthAccPortPromiscuousModeSet() - all frames are
- * forwarded to the application regardless of the multicast
- * address provisioned
- * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded
- * to the application following the multicast address provisioned
- *
- * In all cases, unicast and broadcast addresses are forwarded to
- * the application.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @sa ixEthAccPortPromiscuousModeSet
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeClear(IxEthAccPortId portId);
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortPromiscuousModeSet(IxEthAccPortId portId)
- *
- * @brief Put the MAC device in promiscuous mode.
- *
- * If the device is in promiscuous mode then all all received frames shall be forwared
- * to the NPE for processing.
- *
- * Other functions modify the MAC filtering
- *
- * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast
- * frames are forwarded to the application
- * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the
- * effects of @a ixEthAccPortMulticastAddressJoinAll()
- * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new
- * filtering address
- * @li @a ixEthAccPortMulticastAddressJoin() - provision a new
- * filtering address
- * @li @a ixEthAccPortPromiscuousModeSet() - all frames are
- * forwarded to the application regardless of the multicast
- * address provisioned
- * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded
- * to the application following the multicast address provisioned
- *
- * In all cases, unicast and broadcast addresses are forwarded to
- * the application.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @sa ixEthAccPortPromiscuousModeClear
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeSet(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortUnicastMacAddressSet( IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr)
- *
- * @brief Configure unicast MAC address for a particular port
- *
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- * @param *macAddr @ref IxEthAccMacAddr [in] - Ethernet Mac address.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccPortUnicastMacAddressSet(IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortUnicastMacAddressGet( IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr)
- *
- * @brief Get unicast MAC address for a particular MAC port
- *
- * @pre
- * The MAC address must first be set via @a ixEthAccMacPromiscuousModeSet
- * If the MAC address has not been set, the function returns a
- * IX_ETH_ACC_MAC_UNINITIALIZED status
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- * @param *macAddr @ref IxEthAccMacAddr [out] - Ethernet MAC address.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_MAC_UNINITIALIZED : port MAC address is not initialized.
- * @li @a IX_ETH_ACC_FAIL : macAddr is invalid.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortUnicastMacAddressGet(IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr);
-
-
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortMulticastAddressJoin( IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr)
- *
- * @brief Add a multicast address to the MAC address table.
- *
- * @note
- * Due to the operation of the Ethernet MAC multicast filtering mechanism, frames which do not
- * have a multicast destination address which were provisioned via this API may be forwarded
- * to the NPE's. This is a result of the hardware comparison algorithm used in the destination mac address logic
- * within the Ethernet MAC.
- *
- * See Also: IXP425 hardware development manual.
- *
- * Other functions modify the MAC filtering
- *
- * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast
- * frames are forwarded to the application
- * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the
- * effects of @a ixEthAccPortMulticastAddressJoinAll()
- * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new
- * filtering address
- * @li @a ixEthAccPortMulticastAddressJoin() - provision a new
- * filtering address
- * @li @a ixEthAccPortPromiscuousModeSet() - all frames are
- * forwarded to the application regardless of the multicast
- * address provisioned
- * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded
- * to the application following the multicast address provisioned
- *
- * In all cases, unicast and broadcast addresses are forwarded to
- * the application.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- * @param *macAddr @ref IxEthAccMacAddr [in] - Ethernet Mac address.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : Error writing to the MAC registers
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressJoin(IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortMulticastAddressJoinAll( IxEthAccPortId portId)
- *
- * @brief Filter all frames with multicast dest.
- *
- * This function clears the MAC address table, and then sets
- * the MAC to forward ALL multicast frames to the NPE.
- * Specifically, it forwards all frames whose destination address
- * has the LSB of the highest byte set (01:00:00:00:00:00). This
- * bit is commonly referred to as the "multicast bit".
- * Broadcast frames will still be forwarded.
- *
- * Other functions modify the MAC filtering
- *
- * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast
- * frames are forwarded to the application
- * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the
- * effects of @a ixEthAccPortMulticastAddressJoinAll()
- * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new
- * filtering address
- * @li @a ixEthAccPortMulticastAddressJoin() - provision a new
- * filtering address
- * @li @a ixEthAccPortPromiscuousModeSet() - all frames are
- * forwarded to the application regardless of the multicast
- * address provisioned
- * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded
- * to the application following the multicast address provisioned
- *
- * In all cases, unicast and broadcast addresses are forwarded to
- * the application.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressJoinAll(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortMulticastAddressLeave( IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr)
- *
- * @brief Remove a multicast address from the MAC address table.
- *
- * Other functions modify the MAC filtering
- *
- * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast
- * frames are forwarded to the application
- * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the
- * effects of @a ixEthAccPortMulticastAddressJoinAll()
- * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new
- * filtering address
- * @li @a ixEthAccPortMulticastAddressJoin() - provision a new
- * filtering address
- * @li @a ixEthAccPortPromiscuousModeSet() - all frames are
- * forwarded to the application regardless of the multicast
- * address provisioned
- * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded
- * to the application following the multicast address provisioned
- *
- * In all cases, unicast and broadcast addresses are forwarded to
- * the application.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- * @param *macAddr @ref IxEthAccMacAddr [in] - Ethernet Mac address.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_NO_SUCH_ADDR : Failed if MAC address was not in the table.
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressLeave(IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortMulticastAddressLeaveAll( IxEthAccPortId portId)
- *
- * @brief This function unconfigures the multicast filtering settings
- *
- * This function first clears the MAC address table, and then sets
- * the MAC as configured by the promiscuous mode current settings.
- *
- * Other functions modify the MAC filtering
- *
- * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast
- * frames are forwarded to the application
- * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the
- * effects of @a ixEthAccPortMulticastAddressJoinAll()
- * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new
- * filtering address
- * @li @a ixEthAccPortMulticastAddressJoin() - provision a new
- * filtering address
- * @li @a ixEthAccPortPromiscuousModeSet() - all frames are
- * forwarded to the application regardless of the multicast
- * address provisioned
- * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded
- * to the application following the multicast address provisioned
- *
- * In all cases, unicast and broadcast addresses are forwarded to
- * the application.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressLeaveAll(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortUnicastAddressShow(IxEthAccPortId portId)
- *
- * @brief Displays unicast MAC address
- *
- * Displays unicast address which is configured using
- * @a ixEthAccUnicastMacAddressSet. This function also displays the MAC filter used
- * to filter multicast frames.
- *
- * Other functions modify the MAC filtering
- *
- * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast
- * frames are forwarded to the application
- * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the
- * effects of @a ixEthAccPortMulticastAddressJoinAll()
- * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new
- * filtering address
- * @li @a ixEthAccPortMulticastAddressJoin() - provision a new
- * filtering address
- * @li @a ixEthAccPortPromiscuousModeSet() - all frames are
- * forwarded to the application regardless of the multicast
- * address provisioned
- * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded
- * to the application following the multicast address provisioned
- *
- * In all cases, unicast and broadcast addresses are forwarded to
- * the application.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- *
- * @return void
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccPortUnicastAddressShow(IxEthAccPortId portId);
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortMulticastAddressShow( IxEthAccPortId portId)
- *
- * @brief Displays multicast MAC address
- *
- * Displays multicast address which have been configured using @a ixEthAccMulticastAddressJoin
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in] - Ethernet port id.
- *
- * @return void
- *
- * <hr>
- */
-PUBLIC void ixEthAccPortMulticastAddressShow( IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortDuplexModeSet( IxEthAccPortId portId, IxEthAccDuplexMode mode )
- *
- * @brief Set the duplex mode for the MAC.
- *
- * Configure the IXP400 MAC to either full or half duplex.
- *
- * @note
- * The configuration should match that provisioned on the PHY.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in]
- * @param mode @ref IxEthAccDuplexMode [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortDuplexModeSet(IxEthAccPortId portId,IxEthAccDuplexMode mode);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortDuplexModeGet( IxEthAccPortId portId, IxEthAccDuplexMode *mode )
- *
- * @brief Get the duplex mode for the MAC.
- *
- * return the duplex configuration of the IXP400 MAC.
- *
- * @note
- * The configuration should match that provisioned on the PHY.
- * See @a ixEthAccDuplexModeSet
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in]
- * @param *mode @ref IxEthAccDuplexMode [out]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- *
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortDuplexModeGet(IxEthAccPortId portId,IxEthAccDuplexMode *mode );
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortTxFrameAppendPaddingEnable( IxEthAccPortId portId)
- *
- * @brief Enable padding bytes to be appended to runt frames submitted to
- * this port
- *
- * Enable up to 60 null-bytes padding bytes to be appended to runt frames
- * submitted to this port. This is the default behavior of the access
- * component.
- *
- * @warning Do not change this behaviour while the port is enabled.
- *
- * @note When Tx padding is enabled, Tx FCS generation is turned on
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @sa ixEthAccPortTxFrameAppendFCSDusable
- *
- * @param portId @ref IxEthAccPortId [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendPaddingEnable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortTxFrameAppendPaddingDisable( IxEthAccPortId portId)
- *
- * @brief Disable padding bytes to be appended to runt frames submitted to
- * this port
- *
- * Disable padding bytes to be appended to runt frames
- * submitted to this port. This is not the default behavior of the access
- * component.
- *
- * @warning Do not change this behaviour while the port is enabled.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendPaddingDisable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortTxFrameAppendFCSEnable( IxEthAccPortId portId)
- *
- * @brief Enable the appending of Ethernet FCS to all frames submitted to this port
- *
- * When enabled, the FCS is added to the submitted frames. This is the default
- * behavior of the access component.
- * Do not change this behaviour while the port is enabled.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendFCSEnable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortTxFrameAppendFCSDisable( IxEthAccPortId portId)
- *
- * @brief Disable the appending of Ethernet FCS to all frames submitted to this port.
- *
- * When disabled, the Ethernet FCS is not added to the submitted frames.
- * This is not the default
- * behavior of the access component.
- *
- * @note Since the FCS is not appended to the frame it is expected that the frame submitted to the
- * component includes a valid FCS at the end of the data, although this will not be validated.
- *
- * The component shall forward the frame to the Ethernet MAC WITHOUT modification.
- *
- * Do not change this behaviour while the port is enabled.
- *
- * @note Tx FCS append is not disabled while Tx padding is enabled.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @sa ixEthAccPortTxFrameAppendPaddingEnable
- *
- * @param portId @ref IxEthAccPortId [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendFCSDisable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortRxFrameAppendFCSEnable( IxEthAccPortId portId)
- *
- * @brief Forward frames with FCS included in the receive buffer.
- *
- * The FCS is not striped from the receive buffer.
- * The received frame length includes the FCS size (4 bytes). ie.
- * A minimum sized ethernet frame shall have a length of 64bytes.
- *
- * Frame FCS validity checks are still carried out on all received frames.
- *
- * This is not the default
- * behavior of the access component.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortRxFrameAppendFCSEnable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccPortRxFrameAppendFCSDisable( IxEthAccPortId portId)
- *
- * @brief Do not forward the FCS portion of the received Ethernet frame to the user.
- * The FCS is striped from the receive buffer.
- * The received frame length does not include the FCS size (4 bytes).
- * Frame FCS validity checks are still carried out on all received frames.
- *
- * This is the default behavior of the component.
- * Do not change this behaviour while the port is enabled.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortRxFrameAppendFCSDisable(IxEthAccPortId portId);
-
-
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @enum IxEthAccSchedulerDiscipline
- *
- * @brief Definition for the port scheduling discipline
- *
- * Select the port scheduling discipline on receive and transmit path
- * @li FIFO : No Priority : In this configuration all frames are processed
- * in the access component in the strict order in which
- * the component received them.
- * @li FIFO : Priority : This shall be a very simple priority mechanism.
- * Higher prior-ity frames shall be forwarded
- * before lower priority frames. There shall be no
- * fairness mechanisms applied across different
- * priorities. Higher priority frames could starve
- * lower priority frames indefinitely.
- */
-typedef enum
-{
- FIFO_NO_PRIORITY, /**<frames submitted with no priority*/
- FIFO_PRIORITY /**<higher prority frames submitted before lower priority*/
-}IxEthAccSchedulerDiscipline;
-
-/**
- * @ingroup IxEthAcc
- *
- * @def IxEthAccTxSchedulerDiscipline
- *
- * @brief Deprecated definition for the port transmit scheduling discipline
- */
-#define IxEthAccTxSchedulerDiscipline IxEthAccSchedulerDiscipline
-
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccTxSchedulingDisciplineSet( IxEthAccPortId portId, IxEthAccSchedulerDiscipline sched)
- *
- * @brief Set the port scheduling to one of @a IxEthAccSchedulerDiscipline
- *
- * The default behavior of the component is @a FIFO_NO_PRIORITY.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- *
- * @param portId @ref IxEthAccPortId [in]
- * @param sched @ref IxEthAccSchedulerDiscipline [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : Set appropriate discipline.
- * @li @a IX_ETH_ACC_FAIL : Invalid/unsupported discipline.
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccTxSchedulingDisciplineSet(IxEthAccPortId portId,
- IxEthAccSchedulerDiscipline sched);
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccRxSchedulingDisciplineSet(IxEthAccSchedulerDiscipline sched)
- *
- * @brief Set the Rx scheduling to one of @a IxEthAccSchedulerDiscipline
- *
- * The default behavior of the component is @a FIFO_NO_PRIORITY.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- * @param sched : @a IxEthAccSchedulerDiscipline
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : Set appropriate discipline.
- * @li @a IX_ETH_ACC_FAIL : Invalid/unsupported discipline.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccRxSchedulingDisciplineSet(IxEthAccSchedulerDiscipline sched);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn IxEthAccStatus ixEthAccNpeLoopbackEnable(IxEthAccPortId portId)
- *
- * @brief Enable NPE loopback
- *
- * When this loopback mode is enabled all the transmitted frames are
- * received on the same port, without payload.
- *
- * This function is recommended for power-up diagnostic checks and
- * should never be used under normal Ethernet traffic operations.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- * @param portId : ID of the port
- *
- * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is
- * guaranteed to restore correct Ethernet Tx/Rx operation.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : NPE loopback mode enabled
- * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortNpeLoopbackEnable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn IxEthAccStatus ixEthAccPortNpeLoopbackDisable(IxEthAccPortId portId)
- *
- * @brief Disable NPE loopback
- *
- * This function is used to disable the NPE loopback if previously
- * enabled using ixEthAccNpeLoopbackEnable.
- *
- * This function is recommended for power-up diagnostic checks and
- * should never be used under normal Ethernet traffic operations.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is
- * guaranteed to restore correct Ethernet Tx/Rx operation.
- *
- * @param portId : ID of the port
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : NPE loopback successfully disabled
- * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortNpeLoopbackDisable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn IxEthAccStatus ixEthAccPortTxEnable(IxEthAccPortId portId)
- *
- * @brief Enable Tx on the port
- *
- * This function is the complement of ixEthAccPortTxDisable and should
- * be used only after Tx was disabled. A MAC core reset is required before
- * this function is called (see @a ixEthAccPortMacReset).
- *
- * This function is the recommended usage scenario for emergency security
- * shutdown and hardware failure recovery and should never be used for throttling
- * traffic.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is
- * guaranteed to restore correct Ethernet Tx/Rx operation.
- *
- * @param portId : ID of the port
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : Tx successfully enabled
- * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortTxEnable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn IxEthAccStatus ixEthAccPortTxDisable(IxEthAccPortId portId)
- *
- * @brief Disable Tx on the port
- *
- * This function can be used to disable Tx in the MAC core.
- * Tx can be re-enabled, although this is not guaranteed, by performing
- * a MAC core reset (@a ixEthAccPortMacReset) and calling ixEthAccPortTxEnable.
- * Note that using this function is not recommended, except for shutting
- * down Tx for emergency reasons. For proper port shutdown and re-enabling
- * see ixEthAccPortEnable and ixEthAccPortDisable.
- *
- * This function is the recommended usage scenario for emergency security
- * shutdown and hardware failure recovery and should never be used for throttling
- * traffic.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is
- * guaranteed to restore correct Ethernet Tx/Rx operation.
- *
- * @pre
- *
- * @param portId : ID of the port
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : Tx successfully disabled
- * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortTxDisable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn IxEthAccStatus ixEthAccPortRxEnable(IxEthAccPortId portId)
- *
- * @brief Enable Rx on the port
- *
- * This function is the complement of ixEthAccPortRxDisable and should
- * be used only after Rx was disabled.
- *
- * This function is the recommended usage scenario for emergency security
- * shutdown and hardware failure recovery and should never be used for throttling
- * traffic.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is
- * guaranteed to restore correct Ethernet Tx/Rx operation.
- *
- * @pre
- *
- * @param portId : ID of the port
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : Rx successfully enabled
- * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortRxEnable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn IxEthAccStatus ixEthAccPortRxDisable(IxEthAccPortId portId)
- *
- * @brief Disable Rx on the port
- *
- * This function can be used to disable Rx in the MAC core.
- * Rx can be re-enabled, although this is not guaranteed, by performing
- * a MAC core reset (@a ixEthAccPortMacReset) and calling ixEthAccPortRxEnable.
- * Note that using this function is not recommended, except for shutting
- * down Rx for emergency reasons. For proper port shutdown and re-enabling
- * see ixEthAccPortEnable and ixEthAccPortDisable.
- *
- * This function is the recommended usage scenario for emergency security
- * shutdown and hardware failure recovery and should never be used for throttling
- * traffic.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is
- * guaranteed to restore correct Ethernet Tx/Rx operation.
- *
- * @param portId : ID of the port
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : Rx successfully disabled
- * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortRxDisable(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn IxEthAccStatus ixEthAccPortMacReset(IxEthAccPortId portId)
- *
- * @brief Reset MAC core on the port
- *
- * This function will perform a MAC core reset (NPE Ethernet coprocessor).
- * This function is inherently unsafe and the NPE recovery is not guaranteed
- * after this function is called. The proper manner of performing port disable
- * and enable (which will reset the MAC as well) is ixEthAccPortEnable/ixEthAccPortDisable.
- *
- * This function is the recommended usage scenario for hardware failure recovery
- * and should never be used for throttling traffic.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is
- * guaranteed to restore correct Ethernet Tx/Rx operation.
- *
- * @param portId : ID of the port
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS : MAC core reset
- * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccPortMacReset(IxEthAccPortId portId);
-
-/*********************************************************************************
- #### ##### ## ##### # #### ##### # #### ####
- # # # # # # # # # # # #
- #### # # # # # #### # # # ####
- # # ###### # # # # # # #
- # # # # # # # # # # # # # # #
- #### # # # # # #### # # #### ####
-**********************************************************************************/
-
-
-/**
- *
- * @brief This struct defines the statistics returned by this component.
- *
- * The component returns MIB2 EthObj variables which are obtained from the
- * hardware or maintained by this component.
- *
- *
- */
-typedef struct
-{
- UINT32 dot3StatsAlignmentErrors; /**< link error count (rx) */
- UINT32 dot3StatsFCSErrors; /**< link error count (rx) */
- UINT32 dot3StatsInternalMacReceiveErrors; /**< link error count (rx) */
- UINT32 RxOverrunDiscards; /**< NPE: discarded frames count (rx) */
- UINT32 RxLearnedEntryDiscards; /**< NPE: discarded frames count(rx) */
- UINT32 RxLargeFramesDiscards; /**< NPE: discarded frames count(rx) */
- UINT32 RxSTPBlockedDiscards; /**< NPE: discarded frames count(rx) */
- UINT32 RxVLANTypeFilterDiscards; /**< NPE: discarded frames count (rx) */
- UINT32 RxVLANIdFilterDiscards; /**< NPE: discarded frames count (rx) */
- UINT32 RxInvalidSourceDiscards; /**< NPE: discarded frames count (rx) */
- UINT32 RxBlackListDiscards; /**< NPE: discarded frames count (rx) */
- UINT32 RxWhiteListDiscards; /**< NPE: discarded frames count (rx) */
- UINT32 RxUnderflowEntryDiscards; /**< NPE: discarded frames count (rx) */
- UINT32 dot3StatsSingleCollisionFrames; /**< link error count (tx) */
- UINT32 dot3StatsMultipleCollisionFrames; /**< link error count (tx) */
- UINT32 dot3StatsDeferredTransmissions; /**< link error count (tx) */
- UINT32 dot3StatsLateCollisions; /**< link error count (tx) */
- UINT32 dot3StatsExcessiveCollsions; /**< link error count (tx) */
- UINT32 dot3StatsInternalMacTransmitErrors; /**< link error count (tx) */
- UINT32 dot3StatsCarrierSenseErrors; /**< link error count (tx) */
- UINT32 TxLargeFrameDiscards; /**< NPE: discarded frames count (tx) */
- UINT32 TxVLANIdFilterDiscards; /**< NPE: discarded frames count (tx) */
-
-}IxEthEthObjStats;
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccMibIIStatsGet(IxEthAccPortId portId ,IxEthEthObjStats *retStats )
- *
- * @brief Returns the statistics maintained for a port.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- *
- * @param portId @ref IxEthAccPortId [in]
- * @param retStats @ref IxEthEthObjStats [out]
- * @note Please note the user is responsible for cache coheriency of the retStat
- * buffer. The data is actually populated via the NPE's. As such cache safe
- * memory should be used in the retStats argument.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : Invalid arguments.
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccMibIIStatsGet(IxEthAccPortId portId, IxEthEthObjStats *retStats );
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccMibIIStatsGetClear(IxEthAccPortId portId, IxEthEthObjStats *retStats)
- *
- * @brief Returns and clears the statistics maintained for a port.
- *
- * @li Reentrant - yes
- * @li ISR Callable - yes
- *
- * @pre
- *
- * @param portId @ref IxEthAccPortId [in]
- * @param retStats @ref IxEthEthObjStats [out]
- * @note Please note the user is responsible for cache coheriency of the retStats
- * buffer. The data is actually populated via the NPE's. As such cache safe
- * memory should be used in the retStats argument.
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : invalid arguments.
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccMibIIStatsGetClear(IxEthAccPortId portId, IxEthEthObjStats *retStats);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccMibIIStatsClear(IxEthAccPortId portId)
- *
- * @brief Clears the statistics maintained for a port.
- *
- * @li Reentrant - yes
- * @li ISR Callable - no
- *
- * @pre
- *
- * @param portId @ref IxEthAccPortId [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : Invalid arguments.
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccMibIIStatsClear(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccMacInit(IxEthAccPortId portId)
- *
- * @brief Initializes the ethernet MAC settings
- *
- * @li Reentrant - no
- * @li ISR Callable - no
- *
- * @param portId @ref IxEthAccPortId [in]
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccMacInit(IxEthAccPortId portId);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccStatsShow(IxEthAccPortId portId)
- *
- *
- * @brief Displays a ports statistics on the standard io console using printf.
- *
- * @li Reentrant - no
- * @li ISR Callable - no
- *
- * @pre
- *
- * @param portId @ref IxEthAccPortId [in]
- *
- * @return void
- *
- * <hr>
- */
-PUBLIC void ixEthAccStatsShow(IxEthAccPortId portId);
-
-/*************************************************************************
-
- # # # # # # ##### # ####
- ## ## # # ## ## # # # # #
- # ## # # # # ## # # # # # #
- # # # # # # # # # # #
- # # # # # # # # # # #
- # # # # # # ##### # ####
-
-*************************************************************************/
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccMiiReadRtn (UINT8 phyAddr,
- UINT8 phyReg,
- UINT16 *value)
- *
- *
- * @brief Reads a 16 bit value from a PHY
- *
- * Reads a 16-bit word from a register of a MII-compliant PHY. Reading
- * is performed through the MII management interface. This function returns
- * when the read operation has successfully completed, or when a timeout has elapsed.
- *
- * @li Reentrant - no
- * @li ISR Callable - no
- *
- * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock.
- *
- * @param phyAddr UINT8 [in] - the address of the Ethernet PHY (0-31)
- * @param phyReg UINT8 [in] - the number of the MII register to read (0-31)
- * @param value UINT16 [in] - the value read from the register
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : failed to read the register.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccMiiReadRtn (UINT8 phyAddr, UINT8 phyReg, UINT16 *value);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccMiiWriteRtn (UINT8 phyAddr,
- UINT8 phyReg,
- UINT16 value)
- *
- *
- * @brief Writes a 16 bit value to a PHY
- *
- * Writes a 16-bit word from a register of a MII-compliant PHY. Writing
- * is performed through the MII management interface. This function returns
- * when the write operation has successfully completed, or when a timeout has elapsed.
- *
- * @li Reentrant - no
- * @li ISR Callable - no
- *
- * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock.
- *
- * @param phyAddr UINT8 [in] - the address of the Ethernet PHY (0-31)
- * @param phyReg UINT8 [in] - the number of the MII register to write (0-31)
- * @param value UINT16 [out] - the value to write to the register
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : failed to write register.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccMiiWriteRtn (UINT8 phyAddr, UINT8 phyReg, UINT16 value);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccMiiAccessTimeoutSet(UINT32 timeout)
- *
- * @brief Overrides the default timeout value and retry count when reading or
- * writing MII registers using ixEthAccMiiWriteRtn or ixEthAccMiiReadRtn
- *
- * The default behavior of the component is to use a IX_ETH_ACC_MII_10TH_SEC_IN_MILLIS ms
- * timeout (declared as 100 in IxEthAccMii_p.h) and a retry count of IX_ETH_ACC_MII_TIMEOUT_10TH_SECS
- * (declared as 5 in IxEthAccMii_p.h).
- *
- * The MII read and write functions will attempt to read the status of the register up
- * to the retry count times, delaying between each attempt with the timeout value.
- *
- * @li Reentrant - no
- * @li ISR Callable - no
- *
- * @pre
- *
- * @param timeout UINT32 [in] - new timeout value, in milliseconds
- * @param timeout UINT32 [in] - new retry count (a minimum value of 1 must be used)
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : invalid parameter(s)
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus
-ixEthAccMiiAccessTimeoutSet(UINT32 timeout, UINT32 retryCount);
-
-/**
- * @ingroup IxEthAcc
- *
- * @fn ixEthAccMiiStatsShow (UINT32 phyAddr)
- *
- *
- * @brief Displays detailed information on a specified PHY
- *
- * Displays the current values of the first eigth MII registers for a PHY,
- *
- * @li Reentrant - no
- * @li ISR Callable - no
- *
- * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and
- * generating the MDIO clock.
- *
- * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31)
- *
- * @return IxEthAccStatus
- * @li @a IX_ETH_ACC_SUCCESS
- * @li @a IX_ETH_ACC_FAIL : invalid arguments.
- *
- * <hr>
- */
-PUBLIC IxEthAccStatus ixEthAccMiiStatsShow (UINT32 phyAddr);
-
-
-
-/******* BOARD SPECIFIC DEPRECATED API *********/
-
-/* The following functions are high level functions which rely
- * on the properties and interface of some Ethernet PHYs. The
- * implementation is hardware specific and has been moved to
- * the hardware-specific component IxEthMii.
- */
-
- #include "IxEthMii.h"
-
-/**
- * @ingroup IxEthAcc
- *
- * @def ixEthAccMiiPhyScan
- *
- * @brief : deprecated API entry point. This definition
- * ensures backward compatibility
- *
- * See @ref ixEthMiiPhyScan
- *
- * @note this feature is board specific
- *
- */
-#define ixEthAccMiiPhyScan(phyPresent) ixEthMiiPhyScan(phyPresent,IXP425_ETH_ACC_MII_MAX_ADDR)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def ixEthAccMiiPhyConfig
- *
- * @brief : deprecated API entry point. This definition
- * ensures backward compatibility
- *
- * See @ref ixEthMiiPhyConfig
- *
- * @note this feature is board specific
- */
-#define ixEthAccMiiPhyConfig(phyAddr,speed100,fullDuplex,autonegotiate) \
- ixEthMiiPhyConfig(phyAddr,speed100,fullDuplex,autonegotiate)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def ixEthAccMiiPhyReset
- *
- * @brief : deprecated API entry point. This definition
- * ensures backward compatibility
- *
- * See @ref ixEthMiiPhyReset
- *
- * @note this feature is board specific
- */
-#define ixEthAccMiiPhyReset(phyAddr) \
- ixEthMiiPhyReset(phyAddr)
-
-/**
- * @ingroup IxEthAcc
- *
- * @def ixEthAccMiiLinkStatus
- *
- * @brief : deprecated API entry point. This definition
- * ensures backward compatibility
- *
- * See @ref ixEthMiiLinkStatus
- *
- * @note this feature is board specific
- */
-#define ixEthAccMiiLinkStatus(phyAddr,linkUp,speed100,fullDuplex,autoneg) \
- ixEthMiiLinkStatus(phyAddr,linkUp,speed100,fullDuplex,autoneg)
-
-
-
-/**
- * @ingroup IxEthAcc
- *
- * @def ixEthAccMiiShow
- *
- * @brief : deprecated API entry point. This definition
- * ensures backward compatibility
- *
- * See @ref ixEthMiiPhyShow
- *
- * @note this feature is board specific
- */
-#define ixEthAccMiiShow(phyAddr) \
- ixEthMiiPhyShow(phyAddr)
-
-#endif /* ndef IxEthAcc_H */
-/**
- *@}
- */
+++ /dev/null
-/**
- * @file IxEthAccDataPlane_p.h
- *
- * @author Intel Corporation
- * @date 12-Feb-2002
- *
- * @brief Internal Header file for IXP425 Ethernet Access component.
- *
- * Design Notes:
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-
-
-#ifndef IxEthAccDataPlane_p_H
-#define IxEthAccDataPlane_p_H
-
-#include <IxOsal.h>
-#include <IxQMgr.h>
-
-/**
- * @addtogroup IxEthAccPri
- *@{
- */
-
-/* typedefs global to this file*/
-
-typedef struct
-{
- IX_OSAL_MBUF *pHead;
- IX_OSAL_MBUF *pTail;
-}IxEthAccDataPlaneQList;
-
-
-/**
- * @struct IxEthAccDataPlaneStats
- * @brief Statistics data structure associated with the data plane
- *
- */
-typedef struct
-{
- UINT32 addToSwQ;
- UINT32 removeFromSwQ;
- UINT32 unchainedTxMBufs;
- UINT32 chainedTxMBufs;
- UINT32 unchainedTxDoneMBufs;
- UINT32 chainedTxDoneMBufs;
- UINT32 unchainedRxMBufs;
- UINT32 chainedRxMBufs;
- UINT32 unchainedRxFreeMBufs;
- UINT32 chainedRxFreeMBufs;
- UINT32 rxCallbackCounter;
- UINT32 rxCallbackBurstRead;
- UINT32 txDoneCallbackCounter;
- UINT32 unexpectedError;
-} IxEthAccDataPlaneStats;
-
-/**
- * @fn ixEthAccMbufFromSwQ
- * @brief used during disable steps to convert mbufs from
- * swq format, ready to be pushed into hw queues for NPE,
- * back into XScale format
- */
-IX_OSAL_MBUF *ixEthAccMbufFromSwQ(IX_OSAL_MBUF *mbuf);
-
-/**
- * @fn ixEthAccDataPlaneShow
- * @brief Show function (for data plane statistics
- */
-void ixEthAccDataPlaneShow(void);
-
-/*
- * lock dataplane when atomic operation is required
- */
-#define IX_ETH_ACC_DATA_PLANE_LOCK(arg) arg = ixOsalIrqLock();
-#define IX_ETH_ACC_DATA_PLANE_UNLOCK(arg) ixOsalIrqUnlock(arg);
-
-/*
- * Use MBUF fields
- */
-#define IX_ETHACC_NE_SHARED(mBufPtr) \
- ((IxEthAccNe *)&((mBufPtr)->ix_ne))
-
-#if 1
-
-#define IX_ETHACC_NE_NEXT(mBufPtr) (mBufPtr)->ix_ne.reserved[0]
-
-/* tm - wrong!! len and pkt_len are in the second word - #define IX_ETHACC_NE_LEN(mBufPtr) (mBufPtr)->ix_ne.reserved[3] */
-#define IX_ETHACC_NE_LEN(mBufPtr) (mBufPtr)->ix_ne.reserved[1]
-
-#define IX_ETHACC_NE_DATA(mBufPtr)(mBufPtr)->ix_ne.reserved[2]
-
-#else
-
-#define IX_ETHACC_NE_NEXT(mBufPtr) \
- IX_ETHACC_NE_SHARED(mBufPtr)->ixReserved_next
-
-#define IX_ETHACC_NE_LEN(mBufPtr) \
- IX_ETHACC_NE_SHARED(mBufPtr)->ixReserved_lengths
-
-#define IX_ETHACC_NE_DATA(mBufPtr) \
- IX_ETHACC_NE_SHARED(mBufPtr)->ixReserved_data
-#endif
-
-/*
- * Use MBUF next pointer field to chain data.
- */
-#define IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER(mbuf) (mbuf)->ix_ctrl.ix_chain
-
-
-
-#define IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(mbuf_list) ((mbuf_list.pHead) == NULL)
-
-
-#define IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD(mbuf_list,mbuf_to_add) \
- do { \
- int lockVal; \
- IX_ETH_ACC_DATA_PLANE_LOCK(lockVal); \
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.addToSwQ); \
- if ( (mbuf_list.pHead) != NULL ) \
- { \
- (IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_add))) = (mbuf_list.pHead);\
- (mbuf_list.pHead) = (mbuf_to_add); \
- } \
- else { \
- (mbuf_list.pTail) = (mbuf_list.pHead) = (mbuf_to_add); \
- IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_add)) = NULL; \
- } \
- IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal); \
- } while(0)
-
-
-#define IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_TAIL(mbuf_list,mbuf_to_add) \
- do { \
- int lockVal; \
- IX_ETH_ACC_DATA_PLANE_LOCK(lockVal); \
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.addToSwQ); \
- if ( (mbuf_list.pHead) == NULL ) \
- { \
- (mbuf_list.pHead) = mbuf_to_add; \
- IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_add)) = NULL; \
- } \
- else { \
- IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_list.pTail)) = (mbuf_to_add); \
- IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_add)) = NULL; \
- } \
- (mbuf_list.pTail) = mbuf_to_add; \
- IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal); \
- } while (0)
-
-
-#define IX_ETH_ACC_DATAPLANE_REMOVE_MBUF_FROM_Q_HEAD(mbuf_list,mbuf_to_rem) \
- do { \
- int lockVal; \
- IX_ETH_ACC_DATA_PLANE_LOCK(lockVal); \
- if ( (mbuf_list.pHead) != NULL ) \
- { \
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.removeFromSwQ); \
- (mbuf_to_rem) = (mbuf_list.pHead) ; \
- (mbuf_list.pHead) = (IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_rem)));\
- } \
- else { \
- (mbuf_to_rem) = NULL; \
- } \
- IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal); \
- } while (0)
-
-
-/**
- * @brief message handler QManager entries for NPE id => port ID conversion (NPE_B => 0, NPE_C => 1)
- */
-#define IX_ETH_ACC_PORT_TO_NPE_ID(port) \
- ixEthAccPortData[(port)].npeId
-
-#define IX_ETH_ACC_NPE_TO_PORT_ID(npe) ((npe == 0 ? 2 : (npe == 1 ? 0 : ( npe == 2 ? 1 : -1 ))))
-
-#define IX_ETH_ACC_PORT_TO_TX_Q_ID(port) \
- ixEthAccPortData[(port)].ixEthAccTxData.txQueue
-
-#define IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(port) \
- ixEthAccPortData[(port)].ixEthAccRxData.rxFreeQueue
-
-#define IX_ETH_ACC_PORT_TO_TX_Q_SOURCE(port) (port == IX_ETH_PORT_1 ? IX_ETH_ACC_TX_FRAME_ENET0_Q_SOURCE : (port == IX_ETH_PORT_2 ? IX_ETH_ACC_TX_FRAME_ENET1_Q_SOURCE : IX_ETH_ACC_TX_FRAME_ENET2_Q_SOURCE))
-
-#define IX_ETH_ACC_PORT_TO_RX_FREE_Q_SOURCE(port) (port == IX_ETH_PORT_1 ? IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q_SOURCE : (port == IX_ETH_PORT_2 ? IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q_SOURCE : IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q_SOURCE ))
-
-/* Flush the mbufs chain and all data pointed to by the mbuf */
-
-#ifndef NDEBUG
-#define IX_ETH_ACC_STATS_INC(x) (x++)
-#else
-#define IX_ETH_ACC_STATS_INC(x)
-#endif
-
-#define IX_ETH_ACC_MAX_TX_FRAMES_TO_SUBMIT 128
-
-void ixEthRxFrameQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId);
-void ixEthRxMultiBufferQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId);
-void ixEthTxFrameDoneQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId);
-
-#endif /* IxEthAccDataPlane_p_H */
-
-
-/**
- *@}
- */
-
+++ /dev/null
-/*
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-
-#ifndef IxEthAccMac_p_H
-#define IxEthAccMac_p_H
-
-#include "IxOsal.h"
-
-#define IX_ETH_ACC_MAX_MULTICAST_ADDRESSES 256
-#define IX_ETH_ACC_NUM_PORTS 3
-#define IX_ETH_ACC_MAX_FRAME_SIZE_DEFAULT 1536
-#define IX_ETH_ACC_MAX_FRAME_SIZE_UPPER_RANGE (65536-64)
-#define IX_ETH_ACC_MAX_FRAME_SIZE_LOWER_RANGE 64
-
-/*
- *
- * MAC register definitions
- *
- */
-#define IX_ETH_ACC_MAC_0_BASE IX_OSAL_IXP400_ETHA_PHYS_BASE
-#define IX_ETH_ACC_MAC_1_BASE IX_OSAL_IXP400_ETHB_PHYS_BASE
-#define IX_ETH_ACC_MAC_2_BASE IX_OSAL_IXP400_ETH_NPEA_PHYS_BASE
-
-#define IX_ETH_ACC_MAC_TX_CNTRL1 0x000
-#define IX_ETH_ACC_MAC_TX_CNTRL2 0x004
-#define IX_ETH_ACC_MAC_RX_CNTRL1 0x010
-#define IX_ETH_ACC_MAC_RX_CNTRL2 0x014
-#define IX_ETH_ACC_MAC_RANDOM_SEED 0x020
-#define IX_ETH_ACC_MAC_THRESH_P_EMPTY 0x030
-#define IX_ETH_ACC_MAC_THRESH_P_FULL 0x038
-#define IX_ETH_ACC_MAC_BUF_SIZE_TX 0x040
-#define IX_ETH_ACC_MAC_TX_DEFER 0x050
-#define IX_ETH_ACC_MAC_RX_DEFER 0x054
-#define IX_ETH_ACC_MAC_TX_TWO_DEFER_1 0x060
-#define IX_ETH_ACC_MAC_TX_TWO_DEFER_2 0x064
-#define IX_ETH_ACC_MAC_SLOT_TIME 0x070
-#define IX_ETH_ACC_MAC_MDIO_CMD_1 0x080
-#define IX_ETH_ACC_MAC_MDIO_CMD_2 0x084
-#define IX_ETH_ACC_MAC_MDIO_CMD_3 0x088
-#define IX_ETH_ACC_MAC_MDIO_CMD_4 0x08c
-#define IX_ETH_ACC_MAC_MDIO_STS_1 0x090
-#define IX_ETH_ACC_MAC_MDIO_STS_2 0x094
-#define IX_ETH_ACC_MAC_MDIO_STS_3 0x098
-#define IX_ETH_ACC_MAC_MDIO_STS_4 0x09c
-#define IX_ETH_ACC_MAC_ADDR_MASK_1 0x0A0
-#define IX_ETH_ACC_MAC_ADDR_MASK_2 0x0A4
-#define IX_ETH_ACC_MAC_ADDR_MASK_3 0x0A8
-#define IX_ETH_ACC_MAC_ADDR_MASK_4 0x0AC
-#define IX_ETH_ACC_MAC_ADDR_MASK_5 0x0B0
-#define IX_ETH_ACC_MAC_ADDR_MASK_6 0x0B4
-#define IX_ETH_ACC_MAC_ADDR_1 0x0C0
-#define IX_ETH_ACC_MAC_ADDR_2 0x0C4
-#define IX_ETH_ACC_MAC_ADDR_3 0x0C8
-#define IX_ETH_ACC_MAC_ADDR_4 0x0CC
-#define IX_ETH_ACC_MAC_ADDR_5 0x0D0
-#define IX_ETH_ACC_MAC_ADDR_6 0x0D4
-#define IX_ETH_ACC_MAC_INT_CLK_THRESH 0x0E0
-#define IX_ETH_ACC_MAC_UNI_ADDR_1 0x0F0
-#define IX_ETH_ACC_MAC_UNI_ADDR_2 0x0F4
-#define IX_ETH_ACC_MAC_UNI_ADDR_3 0x0F8
-#define IX_ETH_ACC_MAC_UNI_ADDR_4 0x0FC
-#define IX_ETH_ACC_MAC_UNI_ADDR_5 0x100
-#define IX_ETH_ACC_MAC_UNI_ADDR_6 0x104
-#define IX_ETH_ACC_MAC_CORE_CNTRL 0x1FC
-
-
-/*
- *
- *Bit definitions
- *
- */
-
-/* TX Control Register 1*/
-
-#define IX_ETH_ACC_TX_CNTRL1_TX_EN BIT(0)
-#define IX_ETH_ACC_TX_CNTRL1_DUPLEX BIT(1)
-#define IX_ETH_ACC_TX_CNTRL1_RETRY BIT(2)
-#define IX_ETH_ACC_TX_CNTRL1_PAD_EN BIT(3)
-#define IX_ETH_ACC_TX_CNTRL1_FCS_EN BIT(4)
-#define IX_ETH_ACC_TX_CNTRL1_2DEFER BIT(5)
-#define IX_ETH_ACC_TX_CNTRL1_RMII BIT(6)
-
-/* TX Control Register 2 */
-#define IX_ETH_ACC_TX_CNTRL2_RETRIES_MASK 0xf
-
-/* RX Control Register 1 */
-#define IX_ETH_ACC_RX_CNTRL1_RX_EN BIT(0)
-#define IX_ETH_ACC_RX_CNTRL1_PADSTRIP_EN BIT(1)
-#define IX_ETH_ACC_RX_CNTRL1_CRC_EN BIT(2)
-#define IX_ETH_ACC_RX_CNTRL1_PAUSE_EN BIT(3)
-#define IX_ETH_ACC_RX_CNTRL1_LOOP_EN BIT(4)
-#define IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN BIT(5)
-#define IX_ETH_ACC_RX_CNTRL1_RX_RUNT_EN BIT(6)
-#define IX_ETH_ACC_RX_CNTRL1_BCAST_DIS BIT(7)
-
-/* RX Control Register 2 */
-#define IX_ETH_ACC_RX_CNTRL2_DEFER_EN BIT(0)
-
-
-
-/* Core Control Register */
-#define IX_ETH_ACC_CORE_RESET BIT(0)
-#define IX_ETH_ACC_CORE_RX_FIFO_FLUSH BIT(1)
-#define IX_ETH_ACC_CORE_TX_FIFO_FLUSH BIT(2)
-#define IX_ETH_ACC_CORE_SEND_JAM BIT(3)
-#define IX_ETH_ACC_CORE_MDC_EN BIT(4)
-
-/* 1st bit of 1st MAC octet */
-#define IX_ETH_ACC_ETH_MAC_BCAST_MCAST_BIT ( 1)
-
-
-/*
- *
- * Default values
- *
- */
-
-
-#define IX_ETH_ACC_TX_CNTRL1_DEFAULT (IX_ETH_ACC_TX_CNTRL1_TX_EN | \
- IX_ETH_ACC_TX_CNTRL1_RETRY | \
- IX_ETH_ACC_TX_CNTRL1_FCS_EN | \
- IX_ETH_ACC_TX_CNTRL1_2DEFER | \
- IX_ETH_ACC_TX_CNTRL1_PAD_EN)
-
-#define IX_ETH_ACC_TX_MAX_RETRIES_DEFAULT 0x0f
-
-#define IX_ETH_ACC_RX_CNTRL1_DEFAULT (IX_ETH_ACC_RX_CNTRL1_CRC_EN \
- | IX_ETH_ACC_RX_CNTRL1_RX_EN)
-
-#define IX_ETH_ACC_RX_CNTRL2_DEFAULT 0x0
-
-/* Thresholds determined by NPE firmware FS */
-#define IX_ETH_ACC_MAC_THRESH_P_EMPTY_DEFAULT 0x12
-#define IX_ETH_ACC_MAC_THRESH_P_FULL_DEFAULT 0x30
-
-/* Number of bytes that must be in the tx fifo before
- transmission commences*/
-#define IX_ETH_ACC_MAC_BUF_SIZE_TX_DEFAULT 0x8
-
-/* One-part deferral values */
-#define IX_ETH_ACC_MAC_TX_DEFER_DEFAULT 0x15
-#define IX_ETH_ACC_MAC_RX_DEFER_DEFAULT 0x16
-
-/* Two-part deferral values... */
-#define IX_ETH_ACC_MAC_TX_TWO_DEFER_1_DEFAULT 0x08
-#define IX_ETH_ACC_MAC_TX_TWO_DEFER_2_DEFAULT 0x07
-
-/* This value applies to MII */
-#define IX_ETH_ACC_MAC_SLOT_TIME_DEFAULT 0x80
-
-/* This value applies to RMII */
-#define IX_ETH_ACC_MAC_SLOT_TIME_RMII_DEFAULT 0xFF
-
-#define IX_ETH_ACC_MAC_ADDR_MASK_DEFAULT 0xFF
-
-#define IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT 0x1
-/*The following is a value chosen at random*/
-#define IX_ETH_ACC_RANDOM_SEED_DEFAULT 0x8
-
-/*By default we must configure the MAC to generate the
- MDC clock*/
-#define IX_ETH_ACC_CORE_DEFAULT (IX_ETH_ACC_CORE_MDC_EN)
-
-#define IXP425_ETH_ACC_MAX_PHY 2
-#define IXP425_ETH_ACC_MAX_AN_ENTRIES 20
-#define IX_ETH_ACC_MAC_RESET_DELAY 1
-
-#define IX_ETH_ACC_MAC_ALL_BITS_SET 0xFF
-
-#define IX_ETH_ACC_MAC_MSGID_SHL 24
-
-#define IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS 20
-#define IX_ETH_ACC_PORT_DISABLE_DELAY_COUNT 200 /* 4 seconds timeout */
-#define IX_ETH_ACC_PORT_DISABLE_RETRY_COUNT 3
-#define IX_ETH_ACC_MIB_STATS_DELAY_MSECS 2000 /* 2 seconds delay for ethernet stats */
-
-/*Register access macros*/
-#if (CPU == SIMSPARCSOLARIS)
-extern void registerWriteStub (UINT32 base, UINT32 offset, UINT32 val);
-extern UINT32 registerReadStub (UINT32 base, UINT32 offset);
-
-#define REG_WRITE(b,o,v) registerWriteStub(b, o, v)
-#define REG_READ(b,o,v) do { v = registerReadStub(b, o); } while (0)
-#else
-#define REG_WRITE(b,o,v) IX_OSAL_WRITE_LONG((volatile UINT32 *)(b + o), v)
-#define REG_READ(b,o,v) (v = IX_OSAL_READ_LONG((volatile UINT32 *)(b + o)))
-
-#endif
-
-void ixEthAccMacUnload(void);
-IxEthAccStatus ixEthAccMacMemInit(void);
-
-/* MAC core loopback */
-IxEthAccStatus ixEthAccPortLoopbackEnable(IxEthAccPortId portId);
-IxEthAccStatus ixEthAccPortLoopbackDisable(IxEthAccPortId portId);
-
-/* MAC core traffic control */
-IxEthAccStatus ixEthAccPortTxEnablePriv(IxEthAccPortId portId);
-IxEthAccStatus ixEthAccPortTxDisablePriv(IxEthAccPortId portId);
-IxEthAccStatus ixEthAccPortRxEnablePriv(IxEthAccPortId portId);
-IxEthAccStatus ixEthAccPortRxDisablePriv(IxEthAccPortId portId);
-IxEthAccStatus ixEthAccPortMacResetPriv(IxEthAccPortId portId);
-
-/* NPE software loopback */
-IxEthAccStatus ixEthAccNpeLoopbackDisablePriv(IxEthAccPortId portId);
-IxEthAccStatus ixEthAccNpeLoopbackEnablePriv(IxEthAccPortId portId);
-
-#endif /*IxEthAccMac_p_H*/
-
+++ /dev/null
-/**
- * @file IxEthAccMii_p.h
- *
- * @author Intel Corporation
- * @date
- *
- * @brief MII Header file
- *
- * Design Notes:
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxEthAccMii_p_H
-#define IxEthAccMii_p_H
-
-/* MII definitions - these have been verified against the LXT971 and LXT972 PHYs*/
-
-#define IXP425_ETH_ACC_MII_MAX_REG 32 /* max register per phy */
-
-#define IX_ETH_ACC_MII_REG_SHL 16
-#define IX_ETH_ACC_MII_ADDR_SHL 21
-
-/* Definitions for MII access routines*/
-
-#define IX_ETH_ACC_MII_GO BIT(31)
-#define IX_ETH_ACC_MII_WRITE BIT(26)
-#define IX_ETH_ACC_MII_TIMEOUT_10TH_SECS 5
-#define IX_ETH_ACC_MII_10TH_SEC_IN_MILLIS 100
-#define IX_ETH_ACC_MII_READ_FAIL BIT(31)
-
-#define IX_ETH_ACC_MII_PHY_DEF_DELAY 300 /* max delay before link up, etc. */
-#define IX_ETH_ACC_MII_PHY_NO_DELAY 0x0 /* do not delay */
-#define IX_ETH_ACC_MII_PHY_NULL 0xff /* PHY is not present */
-#define IX_ETH_ACC_MII_PHY_DEF_ADDR 0x0 /* default PHY's logical address */
-
-#ifndef IX_ETH_ACC_MII_MONITOR_DELAY
-# define IX_ETH_ACC_MII_MONITOR_DELAY 0x5 /* in seconds */
-#endif
-
-/* Register definition */
-
-#define IX_ETH_ACC_MII_CTRL_REG 0x0 /* Control Register */
-#define IX_ETH_ACC_MII_STAT_REG 0x1 /* Status Register */
-#define IX_ETH_ACC_MII_PHY_ID1_REG 0x2 /* PHY identifier 1 Register */
-#define IX_ETH_ACC_MII_PHY_ID2_REG 0x3 /* PHY identifier 2 Register */
-#define IX_ETH_ACC_MII_AN_ADS_REG 0x4 /* Auto-Negotiation */
- /* Advertisement Register */
-#define IX_ETH_ACC_MII_AN_PRTN_REG 0x5 /* Auto-Negotiation */
- /* partner ability Register */
-#define IX_ETH_ACC_MII_AN_EXP_REG 0x6 /* Auto-Negotiation */
- /* Expansion Register */
-#define IX_ETH_ACC_MII_AN_NEXT_REG 0x7 /* Auto-Negotiation */
- /* next-page transmit Register */
-
-IxEthAccStatus ixEthAccMdioShow (void);
-IxEthAccStatus ixEthAccMiiInit(void);
-void ixEthAccMiiUnload(void);
-
-#endif /*IxEthAccMii_p_H*/
+++ /dev/null
-/**
- * @file IxEthAccQueueAssign_p.h
- *
- * @author Intel Corporation
- * @date 06-Mar-2002
- *
- * @brief Mapping from QMgr Q's to internal assignment
- *
- * Design Notes:
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @addtogroup IxEthAccPri
- *@{
- */
-
-/*
- * Os/System dependancies.
- */
-#include "IxOsal.h"
-
-/*
- * Intermodule dependancies
- */
-#include "IxQMgr.h"
-#include "IxQueueAssignments.h"
-
-/* Check range of Q's assigned to this component. */
-#if IX_ETH_ACC_RX_FRAME_ETH_Q >= (IX_QMGR_MIN_QUEUPP_QID ) | \
- IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q >= (IX_QMGR_MIN_QUEUPP_QID) | \
- IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q >= (IX_QMGR_MIN_QUEUPP_QID) | \
- IX_ETH_ACC_TX_FRAME_ENET0_Q >= (IX_QMGR_MIN_QUEUPP_QID) | \
- IX_ETH_ACC_TX_FRAME_ENET1_Q >= (IX_QMGR_MIN_QUEUPP_QID) | \
- IX_ETH_ACC_TX_FRAME_DONE_ETH_Q >= (IX_QMGR_MIN_QUEUPP_QID)
-#error "Not all Ethernet Access Queues are betweem 1-31, requires full functionalty Q's unless otherwise validated "
-#endif
-
-/**
-*
-* @typedef IxEthAccQregInfo
-*
-* @brief
-*
-*/
-typedef struct
-{
- IxQMgrQId qId;
- char *qName;
- IxQMgrCallback qCallback;
- IxQMgrCallbackId callbackTag;
- IxQMgrQSizeInWords qSize;
- IxQMgrQEntrySizeInWords qWords;
- BOOL qNotificationEnableAtStartup;
- IxQMgrSourceId qConditionSource;
- IxQMgrWMLevel AlmostEmptyThreshold;
- IxQMgrWMLevel AlmostFullThreshold;
-
-} IxEthAccQregInfo;
-
-/*
- * Prototypes for all QM callbacks.
- */
-
-/*
- * Rx Callbacks
- */
-IX_ETH_ACC_PUBLIC
-void ixEthRxFrameQMCallback(IxQMgrQId, IxQMgrCallbackId);
-
-IX_ETH_ACC_PUBLIC
-void ixEthRxMultiBufferQMCallback(IxQMgrQId, IxQMgrCallbackId);
-
-IX_ETH_ACC_PUBLIC
-void ixEthRxFreeQMCallback(IxQMgrQId, IxQMgrCallbackId);
-
-/*
- * Tx Callback.
- */
-IX_ETH_ACC_PUBLIC
-void ixEthTxFrameQMCallback(IxQMgrQId, IxQMgrCallbackId);
-
-IX_ETH_ACC_PUBLIC
-void ixEthTxFrameDoneQMCallback(IxQMgrQId, IxQMgrCallbackId );
-
-
-#define IX_ETH_ACC_QM_QUEUE_DISPATCH_PRIORITY (IX_QMGR_Q_PRIORITY_0) /* Highest priority */
-
-/*
- * Queue watermarks
- */
-#define IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_NOT_E )
-#define IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_E )
-#define IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_E )
-#define IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_E )
-#define IX_ETH_ACC_TX_FRAME_ENET0_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_E )
-#define IX_ETH_ACC_TX_FRAME_ENET1_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_E )
-#define IX_ETH_ACC_TX_FRAME_ENET2_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_E )
-#define IX_ETH_ACC_TX_FRAME_DONE_ETH_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_NOT_E )
+++ /dev/null
-/**
- * @file IxEthAcc_p.h
- *
- * @author Intel Corporation
- * @date 12-Feb-2002
- *
- * @brief Internal Header file for IXP425 Ethernet Access component.
- *
- * Design Notes:
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @addtogroup IxEthAccPri
- *@{
- */
-
-#ifndef IxEthAcc_p_H
-#define IxEthAcc_p_H
-
-/*
- * Os/System dependancies.
- */
-#include "IxOsal.h"
-
-/*
- * Intermodule dependancies
- */
-#include "IxNpeDl.h"
-#include "IxQMgr.h"
-
-#include "IxEthNpe.h"
-
-/*
- * Intra module dependancies
- */
-
-#include "IxEthAccDataPlane_p.h"
-#include "IxEthAccMac_p.h"
-
-
-#define INLINE __inline__
-
-#ifdef NDEBUG
-
-#define IX_ETH_ACC_PRIVATE static
-
-#else
-
-#define IX_ETH_ACC_PRIVATE
-
-#endif /* ndef NDEBUG */
-
-#define IX_ETH_ACC_PUBLIC
-
-
-#define IX_ETH_ACC_IS_PORT_VALID(port) ((port) < IX_ETH_ACC_NUMBER_OF_PORTS ? TRUE : FALSE )
-
-
-
-#ifndef NDEBUG
-#define IX_ETH_ACC_FATAL_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
-#define IX_ETH_ACC_WARNING_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_WARNING,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
-#define IX_ETH_ACC_DEBUG_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
-#else
-#define IX_ETH_ACC_FATAL_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
-#define IX_ETH_ACC_WARNING_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_WARNING,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
-#define IX_ETH_ACC_DEBUG_LOG(a,b,c,d,e,f,g) {}
-#endif
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccInitDataPlane(void);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccQMgrQueuesConfig(void);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccQMgrRxCallbacksRegister(IxQMgrCallback ixQMgrCallback);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccSingleEthNpeCheck(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC void ixEthAccQMgrRxQEntryGet(UINT32 *numRxQueueEntries);
-
-/* prototypes for the private control plane functions (used by the control interface wrapper) */
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortEnablePriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDisablePriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortEnabledQueryPriv(IxEthAccPortId portId, BOOL *enabled);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeClearPriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeSetPriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastMacAddressSetPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastMacAddressGetPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressJoinPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressJoinAllPriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressLeavePriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressLeaveAllPriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastAddressShowPriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC void ixEthAccPortMulticastAddressShowPriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDuplexModeSetPriv(IxEthAccPortId portId, IxEthAccDuplexMode mode);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDuplexModeGetPriv(IxEthAccPortId portId, IxEthAccDuplexMode *mode);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendPaddingEnablePriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendPaddingDisablePriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendFCSEnablePriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendFCSDisablePriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortRxFrameAppendFCSEnablePriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortRxFrameAppendFCSDisablePriv(IxEthAccPortId portId);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccTxSchedulingDisciplineSetPriv(IxEthAccPortId portId, IxEthAccSchedulerDiscipline sched);
-IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccRxSchedulingDisciplineSetPriv(IxEthAccSchedulerDiscipline sched);
-
-/**
- * @struct ixEthAccRxDataStats
- * @brief Stats data structures for data path. - Not obtained from h/w
- *
- */
-typedef struct
-{
- UINT32 rxFrameClientCallback;
- UINT32 rxFreeRepOK;
- UINT32 rxFreeRepDelayed;
- UINT32 rxFreeRepFromSwQOK;
- UINT32 rxFreeRepFromSwQDelayed;
- UINT32 rxFreeLateNotificationEnabled;
- UINT32 rxFreeLowCallback;
- UINT32 rxFreeOverflow;
- UINT32 rxFreeLock;
- UINT32 rxDuringDisable;
- UINT32 rxSwQDuringDisable;
- UINT32 rxUnlearnedMacAddress;
- UINT32 rxPriority[IX_ETH_ACC_TX_PRIORITY_7 + 1];
- UINT32 rxUnexpectedError;
- UINT32 rxFiltered;
-} IxEthAccRxDataStats;
-
-/**
- * @struct IxEthAccTxDataStats
- * @brief Stats data structures for data path. - Not obtained from h/w
- *
- */
-typedef struct
-{
- UINT32 txQOK;
- UINT32 txQDelayed;
- UINT32 txFromSwQOK;
- UINT32 txFromSwQDelayed;
- UINT32 txLowThreshCallback;
- UINT32 txDoneClientCallback;
- UINT32 txDoneClientCallbackDisable;
- UINT32 txOverflow;
- UINT32 txLock;
- UINT32 txPriority[IX_ETH_ACC_TX_PRIORITY_7 + 1];
- UINT32 txLateNotificationEnabled;
- UINT32 txDoneDuringDisable;
- UINT32 txDoneSwQDuringDisable;
- UINT32 txUnexpectedError;
-} IxEthAccTxDataStats;
-
-/* port Disable state machine : list of states */
-typedef enum
-{
- /* general port states */
- DISABLED = 0,
- ACTIVE,
-
- /* particular Tx/Rx states */
- REPLENISH,
- RECEIVE,
- TRANSMIT,
- TRANSMIT_DONE
-} IxEthAccPortDisableState;
-
-typedef struct
-{
- BOOL fullDuplex;
- BOOL rxFCSAppend;
- BOOL txFCSAppend;
- BOOL txPADAppend;
- BOOL enabled;
- BOOL promiscuous;
- BOOL joinAll;
- IxOsalMutex ackMIBStatsLock;
- IxOsalMutex ackMIBStatsResetLock;
- IxOsalMutex MIBStatsGetAccessLock;
- IxOsalMutex MIBStatsGetResetAccessLock;
- IxOsalMutex npeLoopbackMessageLock;
- IxEthAccMacAddr mcastAddrsTable[IX_ETH_ACC_MAX_MULTICAST_ADDRESSES];
- UINT32 mcastAddrIndex;
- IX_OSAL_MBUF *portDisableTxMbufPtr;
- IX_OSAL_MBUF *portDisableRxMbufPtr;
-
- volatile IxEthAccPortDisableState portDisableState;
- volatile IxEthAccPortDisableState rxState;
- volatile IxEthAccPortDisableState txState;
-
- BOOL initDone;
- BOOL macInitialised;
-} IxEthAccMacState;
-
-/**
- * @struct IxEthAccRxInfo
- * @brief System-wide data structures associated with the data plane.
- *
- */
-typedef struct
-{
- IxQMgrQId higherPriorityQueue[IX_QMGR_MAX_NUM_QUEUES]; /**< higher priority queue list */
- IxEthAccSchedulerDiscipline schDiscipline; /**< Receive Xscale QoS type */
-} IxEthAccInfo;
-
-/**
- * @struct IxEthAccRxDataInfo
- * @brief Per Port data structures associated with the receive data plane.
- *
- */
-typedef struct
-{
- IxQMgrQId rxFreeQueue; /**< rxFree Queue for this port */
- IxEthAccPortRxCallback rxCallbackFn;
- UINT32 rxCallbackTag;
- IxEthAccDataPlaneQList freeBufferList;
- IxEthAccPortMultiBufferRxCallback rxMultiBufferCallbackFn;
- UINT32 rxMultiBufferCallbackTag;
- BOOL rxMultiBufferCallbackInUse;
- IxEthAccRxDataStats stats; /**< Receive s/w stats */
-} IxEthAccRxDataInfo;
-
-/**
- * @struct IxEthAccTxDataInfo
- * @brief Per Port data structures associated with the transmit data plane.
- *
- */
-typedef struct
-{
- IxEthAccPortTxDoneCallback txBufferDoneCallbackFn;
- UINT32 txCallbackTag;
- IxEthAccDataPlaneQList txQ[IX_ETH_ACC_NUM_TX_PRIORITIES]; /**< Transmit Q */
- IxEthAccSchedulerDiscipline schDiscipline; /**< Transmit Xscale QoS */
- IxQMgrQId txQueue; /**< txQueue for this port */
- IxEthAccTxDataStats stats; /**< Transmit s/w stats */
-} IxEthAccTxDataInfo;
-
-
-/**
- * @struct IxEthAccPortDataInfo
- * @brief Per Port data structures associated with the port data plane.
- *
- */
-typedef struct
-{
- BOOL portInitialized;
- UINT32 npeId; /**< NpeId for this port */
- IxEthAccTxDataInfo ixEthAccTxData; /**< Transmit data control structures */
- IxEthAccRxDataInfo ixEthAccRxData; /**< Recieve data control structures */
-} IxEthAccPortDataInfo;
-
-extern IxEthAccPortDataInfo ixEthAccPortData[];
-#define IX_ETH_IS_PORT_INITIALIZED(port) (ixEthAccPortData[port].portInitialized)
-
-extern BOOL ixEthAccServiceInit;
-#define IX_ETH_ACC_IS_SERVICE_INITIALIZED() (ixEthAccServiceInit == TRUE )
-
-/*
- * Maximum number of frames to consume from the Rx Frame Q.
- */
-
-#define IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK (128)
-
-/*
- * Max number of times to load the Rx Free Q from callback.
- */
-#define IX_ETH_ACC_MAX_RX_FREE_BUFFERS_LOAD (256) /* Set greater than depth of h/w Q + drain time at line rate */
-
-/*
- * Max number of times to read from the Tx Done Q in one sitting.
- */
-
-#define IX_ETH_ACC_MAX_TX_FRAME_DONE_CONSUME_PER_CALLBACK (256)
-
-/*
- * Max number of times to take buffers from S/w queues and write them to the H/w Tx
- * queues on receipt of a Tx low threshold callback
- */
-
-#define IX_ETH_ACC_MAX_TX_FRAME_TX_CONSUME_PER_CALLBACK (16)
-
-
-#define IX_ETH_ACC_FLUSH_CACHE(addr,size) IX_OSAL_CACHE_FLUSH((addr),(size))
-#define IX_ETH_ACC_INVALIDATE_CACHE(addr,size) IX_OSAL_CACHE_INVALIDATE((addr),(size))
-
-
-#define IX_ETH_ACC_MEMSET(start,value,size) memset(start,value,size)
-
-#endif /* ndef IxEthAcc_p_H */
-
-
-
+++ /dev/null
-/** @file IxEthDB.h
- *
- * @brief this file contains the public API of @ref IxEthDB component
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- *
- */
-
-#ifndef IxEthDB_H
-#define IxEthDB_H
-
-#include <IxOsBuffMgt.h>
-#include <IxTypes.h>
-
-/**
- * @defgroup IxEthDB IXP400 Ethernet Database (IxEthDB) API
- *
- * @brief ethDB is a library that does provides a MAC address database learning/filtering capability
- *
- *@{
- */
-
-#define INLINE __inline__
-
-#define IX_ETH_DB_PRIVATE PRIVATE /* imported from IxTypes.h */
-
-#define IX_ETH_DB_PUBLIC PUBLIC
-
-/**
- * @brief port ID => message handler NPE id conversion (0 => NPE_B, 1 => NPE_C)
- */
-#define IX_ETH_DB_PORT_ID_TO_NPE(id) (id == 0 ? 1 : (id == 1 ? 2 : (id == 2 ? 0 : -1)))
-
-/**
- * @def IX_ETH_DB_NPE_TO_PORT_ID(npe)
- * @brief message handler NPE id => port ID conversion (NPE_B => 0, NPE_C => 1)
- */
-#define IX_ETH_DB_NPE_TO_PORT_ID(npe) (npe == 0 ? 2 : (npe == 1 ? 0 : (npe == 2 ? 1 : -1)))
-
-/* temporary define - won't work for Azusa */
-#define IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(id) (IX_ETH_DB_PORT_ID_TO_NPE(id) << 4)
-#define IX_ETH_DB_NPE_LOGICAL_ID_TO_PORT_ID(id) (IX_ETH_DB_NPE_TO_PORT_ID(id >> 4))
-
-/**
- * @def IX_IEEE803_MAC_ADDRESS_SIZE
- * @brief The size of the MAC address
- */
-#define IX_IEEE803_MAC_ADDRESS_SIZE (6)
-
-/**
- * @def IX_IEEE802_1Q_QOS_PRIORITY_COUNT
- * @brief Number of QoS priorities defined by IEEE802.1Q
- */
-#define IX_IEEE802_1Q_QOS_PRIORITY_COUNT (8)
-
-/**
- * @enum IxEthDBStatus
- * @brief Ethernet Database API return values
- */
-typedef enum /* IxEthDBStatus */
-{
- IX_ETH_DB_SUCCESS = IX_SUCCESS, /**< Success */
- IX_ETH_DB_FAIL = IX_FAIL, /**< Failure */
- IX_ETH_DB_INVALID_PORT, /**< Invalid port */
- IX_ETH_DB_PORT_UNINITIALIZED, /**< Port not initialized */
- IX_ETH_DB_MAC_UNINITIALIZED, /**< MAC not initialized */
- IX_ETH_DB_INVALID_ARG, /**< Invalid argument */
- IX_ETH_DB_NO_SUCH_ADDR, /**< Address not found for search or delete operations */
- IX_ETH_DB_NOMEM, /**< Learning database memory full */
- IX_ETH_DB_BUSY, /**< Learning database cannot complete operation, access temporarily blocked */
- IX_ETH_DB_END, /**< Database browser passed the end of the record set */
- IX_ETH_DB_INVALID_VLAN, /**< Invalid VLAN ID (valid range is 0..4094, 0 signifies no VLAN membership, used for priority tagged frames) */
- IX_ETH_DB_INVALID_PRIORITY, /**< Invalid QoS priority/traffic class (valid range for QoS priority is 0..7, valid range for traffic class depends on run-time configuration) */
- IX_ETH_DB_NO_PERMISSION, /**< No permission for attempted operation */
- IX_ETH_DB_FEATURE_UNAVAILABLE, /**< Feature not available (or not enabled) */
- IX_ETH_DB_INVALID_KEY, /**< Invalid search key */
- IX_ETH_DB_INVALID_RECORD_TYPE /**< Invalid record type */
-} IxEthDBStatus;
-
-/** @brief VLAN ID type, valid range is 0..4094, 0 signifying no VLAN membership */
-typedef UINT32 IxEthDBVlanId;
-
-/** @brief 802.1Q VLAN tag, contains 3 bits user priority, 1 bit CFI, 12 bits VLAN ID */
-typedef UINT32 IxEthDBVlanTag;
-
-/** @brief QoS priority/traffic class type, valid range is 0..7, 0 being the lowest */
-typedef UINT32 IxEthDBPriority;
-
-/** @brief Priority mapping table; 0..7 QoS priorities used to index, table contains traffic classes */
-typedef UINT8 IxEthDBPriorityTable[8];
-
-/** @brief A 4096 bit array used to map the complete VLAN ID range */
-typedef UINT8 IxEthDBVlanSet[512];
-
-#define IX_ETH_DB_802_1Q_VLAN_MASK (0xFFF)
-#define IX_ETH_DB_802_1Q_QOS_MASK (0x7)
-
-#define IX_ETH_DB_802_1Q_MAX_VLAN_ID (0xFFE)
-
-/**
- * @def IX_ETH_DB_SET_VLAN_ID
- * @brief returns the given 802.1Q tag with the VLAN ID field substituted with the given VLAN ID
- *
- * This macro is used to change the VLAN ID in a 802.1Q tag.
- *
- * Example:
- *
- * tag = IX_ETH_DB_SET_VLAN_ID(tag, 32)
- *
- * inserts the VLAN ID "32" in the given tag.
- */
-#define IX_ETH_DB_SET_VLAN_ID(vlanTag, vlanID) (((vlanTag) & 0xF000) | ((vlanID) & IX_ETH_DB_802_1Q_VLAN_MASK))
-
-/**
-* @def IX_ETH_DB_GET_VLAN_ID
-* @brief returns the VLAN ID from the given 802.1Q tag
-*/
-#define IX_ETH_DB_GET_VLAN_ID(vlanTag) ((vlanTag) & IX_ETH_DB_802_1Q_VLAN_MASK)
-
-#define IX_ETH_DB_GET_QOS_PRIORITY(vlanTag) (((vlanTag) >> 13) & IX_ETH_DB_802_1Q_QOS_MASK)
-
-#define IX_ETH_DB_SET_QOS_PRIORITY(vlanTag, priority) (((vlanTag) & 0x1FFF) | (((priority) & IX_ETH_DB_802_1Q_QOS_MASK) << 13))
-
-#define IX_ETH_DB_CHECK_VLAN_TAG(vlanTag) { if(((vlanTag & 0xFFFF0000) != 0) || (IX_ETH_DB_GET_VLAN_ID(vlanTag) > 4094)) return IX_ETH_DB_INVALID_VLAN; }
-
-#define IX_ETH_DB_CHECK_VLAN_ID(vlanId) { if (vlanId > IX_ETH_DB_802_1Q_MAX_VLAN_ID) return IX_ETH_DB_INVALID_VLAN; }
-
-#define IX_IEEE802_1Q_VLAN_TPID (0x8100)
-
-typedef enum
-{
- IX_ETH_DB_UNTAGGED_FRAMES = 0x1, /**< Accepts untagged frames */
- IX_ETH_DB_VLAN_TAGGED_FRAMES = 0x2, /**< Accepts tagged frames */
- IX_ETH_DB_PRIORITY_TAGGED_FRAMES = 0x4, /**< Accepts tagged frames with VLAN ID set to 0 (no VLAN membership) */
- IX_ETH_DB_ACCEPT_ALL_FRAMES =
- IX_ETH_DB_UNTAGGED_FRAMES | IX_ETH_DB_VLAN_TAGGED_FRAMES /**< Accepts all the frames */
-} IxEthDBFrameFilter;
-
-typedef enum
-{
- IX_ETH_DB_PASS_THROUGH = 0x1, /**< Leave frame as-is */
- IX_ETH_DB_ADD_TAG = 0x2, /**< Add default port VLAN tag */
- IX_ETH_DB_REMOVE_TAG = 0x3 /**< Remove VLAN tag from frame */
-} IxEthDBTaggingAction;
-
-typedef enum
-{
- IX_ETH_DB_FIREWALL_WHITE_LIST = 0x1, /**< Firewall operates in white-list mode (MAC address based admission) */
- IX_ETH_DB_FIREWALL_BLACK_LIST = 0x2 /**< Firewall operates in black-list mode (MAC address based blocking) */
-} IxEthDBFirewallMode;
-
-typedef enum
-{
- IX_ETH_DB_FILTERING_RECORD = 0x01, /**< <table><caption> Filtering record </caption>
- * <tr><td> MAC address <td> static/dynamic type <td> age
- * </table>
- */
- IX_ETH_DB_FILTERING_VLAN_RECORD = 0x02, /**< <table><caption> VLAN-enabled filtering record </caption>
- * <tr><td> MAC address <td> static/dynamic type <td> age <td> 802.1Q tag
- * </table>
- */
- IX_ETH_DB_WIFI_RECORD = 0x04, /**< <table><caption> WiFi header conversion record </caption>
- * <tr><td> MAC address <td> optional gateway MAC address <td>
- * </table>
- */
- IX_ETH_DB_FIREWALL_RECORD = 0x08, /**< <table><caption> Firewall record </caption>
- * <tr><td> MAC address
- * </table>
- */
- IX_ETH_DB_GATEWAY_RECORD = 0x10, /**< <i>For internal use only</i> */
- IX_ETH_DB_MAX_RECORD_TYPE_INDEX = 0x10, /**< <i>For internal use only</i> */
- IX_ETH_DB_NO_RECORD_TYPE = 0, /**< None of the registered record types */
- IX_ETH_DB_ALL_FILTERING_RECORDS = IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD, /**< All the filtering records */
- IX_ETH_DB_ALL_RECORD_TYPES = IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD |
- IX_ETH_DB_WIFI_RECORD | IX_ETH_DB_FIREWALL_RECORD /**< All the record types registered within EthDB */
-} IxEthDBRecordType;
-
-typedef enum
-{
- IX_ETH_DB_LEARNING = 0x01, /**< Learning feature; enables EthDB to learn MAC address (filtering) records, including 802.1Q enabled records */
- IX_ETH_DB_FILTERING = 0x02, /**< Filtering feature; enables EthDB to communicate with the NPEs for downloading filtering information in the NPEs; depends on the learning feature */
- IX_ETH_DB_VLAN_QOS = 0x04, /**< VLAN/QoS feature; enables EthDB to configure NPEs to operate in VLAN/QoS aware modes */
- IX_ETH_DB_FIREWALL = 0x08, /**< Firewall feature; enables EthDB to configure NPEs to operate in firewall mode, using white/black address lists */
- IX_ETH_DB_SPANNING_TREE_PROTOCOL = 0x10, /**< Spanning tree protocol feature; enables EthDB to configure the NPEs as STP nodes */
- IX_ETH_DB_WIFI_HEADER_CONVERSION = 0x20 /**< WiFi 802.3 to 802.11 header conversion feature; enables EthDB to handle WiFi conversion data */
-} IxEthDBFeature;
-
-typedef UINT32 IxEthDBProperty; /**< Property ID type */
-
-typedef enum
-{
- IX_ETH_DB_INTEGER_PROPERTY = 0x1, /**< 4 byte unsigned integer type */
- IX_ETH_DB_STRING_PROPERTY = 0x2, /**< NULL-terminated string type of maximum 255 characters (including the terminator) */
- IX_ETH_DB_MAC_ADDR_PROPERTY = 0x3, /**< 6 byte MAC address type */
- IX_ETH_DB_BOOL_PROPERTY = 0x4 /**< 4 byte boolean type; can contain only TRUE and FALSE values */
-} IxEthDBPropertyType;
-
-/* list of supported properties for the IX_ETH_DB_VLAN_QOS feature */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_COUNT_PROPERTY (0x01) /**< Property identifying number the supported number of traffic classes */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY (0x10) /**< Rx queue assigned to traffic class 0 */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_1_RX_QUEUE_PROPERTY (0x11) /**< Rx queue assigned to traffic class 1 */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_2_RX_QUEUE_PROPERTY (0x12) /**< Rx queue assigned to traffic class 2 */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_3_RX_QUEUE_PROPERTY (0x13) /**< Rx queue assigned to traffic class 3 */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_4_RX_QUEUE_PROPERTY (0x14) /**< Rx queue assigned to traffic class 4 */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_5_RX_QUEUE_PROPERTY (0x15) /**< Rx queue assigned to traffic class 5 */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_6_RX_QUEUE_PROPERTY (0x16) /**< Rx queue assigned to traffic class 6 */
-#define IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY (0x17) /**< Rx queue assigned to traffic class 7 */
-
-/* private property used by EthAcc to indicate queue configuration complete */
-#define IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE (0x18)
-
-/**
- *
- * @brief The IEEE 802.3 Ethernet MAC address structure.
- *
- * The data should be packed with bytes xx:xx:xx:xx:xx:xx
- *
- * @note The data must be packed in network byte order.
- */
-typedef struct
-{
- UINT8 macAddress[IX_IEEE803_MAC_ADDRESS_SIZE];
-} IxEthDBMacAddr;
-
-/**
- * @ingroup IxEthDB
- *
- * @brief Definition of an IXP400 port.
- */
-typedef UINT32 IxEthDBPortId;
-
-/**
- * @ingroup IxEthDB
- *
- * @brief Port dependency map definition
- */
-typedef UINT8 IxEthDBPortMap[32];
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBInit(void)
- *
- * @brief Initializes the Ethernet learning/filtering database
- *
- * @note calling this function multiple times does not constitute an error;
- * redundant calls will be ignored, returning IX_ETH_DB_SUCCESS
- *
- * @retval IX_ETH_DB_SUCCESS initialization was successful
- * @retval IX_ETH_DB_FAIL initialization failed (OS error)
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBInit(void);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBUnload(void)
- *
- * @brief Stops and prepares the EthDB component for unloading.
- *
- * @retval IX_ETH_DB_SUCCESS de-initialization was successful
- * @retval IX_ETH_DB_BUSY de-initialization failed, ports must be disabled first
- * @retval IX_ETH_DB_FAIL de-initialization failed (OS error)
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBUnload(void);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn void ixEthDBPortInit(IxEthDBPortId portID)
- *
- * @brief Initializes a port
- *
- * This function is called automatically by the Ethernet Access
- * ixEthAccPortInit() routine for Ethernet NPE ports and should be manually
- * called for any user-defined port (any port that is not one of
- * the two Ethernet NPEs).
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to be initialized
- *
- * @see IxEthDBPortDefs.h for port definitions
- *
- * @note calling this function multiple times does not constitute an error;
- * redundant calls will be ignored
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBPortInit(IxEthDBPortId portID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID)
- *
- * @brief Enables a port
- *
- * This function is called automatically from the Ethernet Access component
- * ixEthAccPortEnable() routine for Ethernet NPE ports and should be manually
- * called for any user-defined port (any port that is not one of
- * the Ethernet NPEs).
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to enable processing on
- *
- * @retval IX_ETH_DB_SUCCESS if enabling is successful
- * @retval IX_ETH_DB_FAIL if the enabling was not successful due to
- * a message handler error
- * @retval IX_ETH_DB_MAC_UNINITIALIZED the MAC address of this port was
- * not initialized (only for Ethernet NPEs)
- * @retval IX_ETH_DB_INVALID_PORT if portID is invalid
- *
- * @pre ixEthDBPortAddressSet needs to be called prior to enabling the port events
- * for Ethernet NPEs
- *
- * @see ixEthDBPortAddressSet
- *
- * @see IxEthDBPortDefs.h for port definitions
- *
- * @note calling this function multiple times does not constitute an error;
- * redundant calls will be ignored
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID)
- *
- * @brief Disables processing on a port
- *
- * This function is called automatically from the Ethernet Access component
- * ixEthAccPortDisable() routine for Ethernet NPE ports and should be manually
- * called for any user-defined port (any port that is not one of
- * the Ethernet NPEs).
- *
- * @note Calling ixEthAccPortDisable() will disable the respective Ethernet NPE.
- * After Ethernet NPEs are disabled they are stopped therefore
- * when re-enabled they need to be reset, downloaded with microcode and started.
- * For learning to restart working the user needs to call again
- * ixEthAccPortUnicastMacAddressSet or ixEthDBUnicastAddressSet
- * with the respective port MAC address.
- * Residual MAC addresses learnt before the port was disabled are deleted as soon
- * as the port is disabled. This only applies to dynamic (learnt) entries, static
- * entries do not dissapear when the port is disabled.
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to disable processing on
- *
- * @retval IX_ETH_DB_SUCCESS if disabling is successful
- * @retval IX_ETH_DB_FAIL if the disabling was not successful due to
- * a message handler error
- * @retval IX_ETH_DB_INVALID_PORT if portID is invalid
- *
- * @note calling this function multiple times after the first time completed successfully
- * does not constitute an error; redundant calls will be ignored and return IX_ETH_DB_SUCCESS
-*/
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Sets the port MAC address
- *
- * This function is to be called from the Ethernet Access component top-level
- * ixEthDBUnicastAddressSet(). Event processing cannot be enabled for a port
- * until its MAC address has been set.
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port whose MAC address is set
- * @param macAddr @ref IxEthDBMacAddr [in] - port MAC address
- *
- * @retval IX_ETH_DB_SUCCESS MAC address was set successfully
- * @retval IX_ETH_DB_FAIL MAC address was not set due to a message handler failure
- * @retval IX_ETH_DB_INVALID_PORT if the port is not an Ethernet NPE
- *
- * @see IxEthDBPortDefs.h for port definitions
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringPortMaximumFrameSizeSet(IxEthDBPortId portID, UINT32 maximumFrameSize)
- *
- * @brief Set the maximum frame size supported on the given port ID
- *
- * This functions set the maximum frame size supported on a specific port ID
- *
- * - Reentrant - yes
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to configure
- * @param maximumFrameSize UINT32 [in] - maximum frame size to configure
- *
- * @retval IX_ETH_DB_SUCCESS the port is configured
- * @retval IX_ETH_DB_PORT_UNINITIALIZED the port has not been initialized
- * @retval IX_ETH_DB_INVALID_PORT portID is invalid
- * @retval IX_ETH_DB_INVALID_ARG size parameter is out of range
- * @retval IX_ETH_DB_NO_PERMISSION selected port is not an Ethernet NPE
- * @retval IX_FAIL unknown OS or NPE communication error
- *
- * @note
- * This maximum frame size is used to filter the frames based on their
- * destination addresses and the capabilities of the destination port.
- * The mximum value that can be set for a NPE port is 16320.
- * (IX_ETHNPE_ACC_FRAME_LENGTH_MAX)
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringPortMaximumFrameSizeSet(IxEthDBPortId portID, UINT32 maximumFrameSize);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringStaticEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Populate the Ethernet learning/filtering database with a static MAC address
- *
- * Populates the Ethernet learning/filtering database with a static MAC address. The entry will not be subject to aging.
- * If there is an entry (static or dynamic) with the corresponding MAC address on any port this entry will take precedence.
- * Any other entry with the same MAC address will be removed.
- *
- * - Reentrant - yes
- * - ISR Callable - yes
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to add the static address to
- * @param macAddr @ref IxEthDBMacAddr [in] - static MAC address to add
- *
- * @retval IX_ETH_DB_SUCCESS the add was successful
- * @retval IX_ETH_DB_FAIL failed to populate the database entry
- * @retval IX_ETH_DB_BUSY failed due to a temporary busy condition (i.e. lack of CPU cycles), try again later
- * @retval IX_ETH_DB_INVALID_PORT portID is invalid
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer argument
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringStaticEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringDynamicEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Populate the Ethernet learning/filtering database with a dynamic MAC address
- *
- * Populates the Ethernet learning/filtering database with a dynamic MAC address. This entry will be subject to normal
- * aging function, if aging is enabled on its port.
- * If there is an entry (static or dynamic) with the same MAC address on any port this entry will take precedence.
- * Any other entry with the same MAC address will be removed.
- *
- * - Reentrant - yes
- * - ISR Callable - yes
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to add the dynamic address to
- * @param macAddr @ref IxEthDBMacAddr [in] - static MAC address to add
- *
- * @retval IX_ETH_DB_SUCCESS the add was successful
- * @retval IX_ETH_DB_FAIL failed to populate the database entry
- * @retval IX_ETH_DB_BUSY failed due to a temporary busy condition (i.e. lack of CPU cycles), try again later
- * @retval IX_ETH_DB_INVALID_PORT portID is invalid
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer argument
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringDynamicEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringEntryDelete(IxEthDBMacAddr *macAddr)
- *
- * @brief Removes a MAC address entry from the Ethernet learning/filtering database
- *
- * @param macAddr IxEthDBMacAddr [in] - MAC address to remove
- *
- * - Reentrant - yes
- * - ISR Callable - no
- *
- * @retval IX_ETH_DB_SUCCESS the removal was successful
- * @retval IX_ETH_DB_NO_SUCH_ADDR failed to remove the address (not in the database)
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer argument
- * @retval IX_ETH_DB_BUSY failed due to a temporary busy condition (i.e. lack of CPU cycles), try again later
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringEntryDelete(IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringPortSearch(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Search the Ethernet learning/filtering database for the given MAC address and port ID
- *
- * This functions searches the database for a specific port ID and MAC address. Both the port ID
- * and the MAC address have to match in order for the record to be reported as found.
- *
- * - Reentrant - yes
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to search for
- * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to search for
- *
- * @retval IX_ETH_DB_SUCCESS the record exists in the database
- * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer argument
- * @retval IX_ETH_DB_NO_SUCH_ADDR the record was not found in the database
- * @retval IX_ETH_DB_INVALID_PORT portID is invalid
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringPortSearch(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringDatabaseSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Search the Ethernet learning/filtering database for a MAC address and return the port ID
- *
- * Searches the database for a MAC address. The function returns the portID for the
- * MAC address record, if found. If no match is found the function returns IX_ETH_DB_NO_SUCH_ADDR.
- * The portID is only valid if the function finds a match.
- *
- * - Reentrant - yes
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID the address belongs to (populated only on a successful search)
- * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to search for
- *
- * @retval IX_ETH_DB_SUCCESS the record exists in the database
- * @retval IX_ETH_DB_NO_SUCH_ADDR the record was not found in the database
- * @retval IX_ETH_DB_INVALID_ARG invalid macAddr or portID pointer argument(s)
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringDatabaseSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringPortUpdatingSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Search the filtering database for a MAC address, return the port ID and reset the record age
- *
- * Searches the database for a MAC address. The function returns the portID for the
- * MAC address record and resets the entry age to 0, if found.
- * If no match is found the function returns IX_ETH_DB_NO_SUCH_ADDR.
- * The portID is only valid if the function finds a match.
- *
- * - Reentrant - yes
- * - ISR Callable - no
- *
- * @retval IX_ETH_DB_SUCCESS the MAC address was found
- * @retval IX_ETH_DB_NO_SUCH_ADDR the MAC address was not found
- * @retval IX_ETH_DB_INVALID_ARG invalid macAddr or portID pointer argument(s)
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringPortUpdatingSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @def IX_ETH_DB_MAINTENANCE_TIME
- *
- * @brief The @ref ixEthDBDatabaseMaintenance must be called by the user at a frequency of
- * IX_ETH_DB_MAINTENANCE_TIME
- *
- */
-#define IX_ETH_DB_MAINTENANCE_TIME (1 * 60) /* 1 Minute */
-
-/**
- * @ingroup IxEthDB
- *
- * @def IX_ETH_DB_LEARNING_ENTRY_AGE_TIME
- *
- * @brief The define specifies the filtering database age entry time. Static entries older than
- * IX_ETH_DB_LEARNING_ENTRY_AGE_TIME +/- IX_ETH_DB_MAINTENANCE_TIME shall be removed.
- *
- */
-#define IX_ETH_DB_LEARNING_ENTRY_AGE_TIME (15 * 60 ) /* 15 Mins */
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortAgingDisable(IxEthDBPortId portID)
- *
- * @brief Disable the aging function for a specific port
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to disable aging on
- *
- * - Reentrant - yes
- * - ISR Callable - no
- *
- * @retval IX_ETH_DB_SUCCESS aging disabled successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is invalid
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortAgingDisable(IxEthDBPortId portID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortAgingEnable(IxEthDBPortId portID)
- *
- * @brief Enable the aging function for a specific port
- *
- * Enables the aging of dynamic MAC address entries stored in the learning/filtering database
- *
- * @note The aging function relies on the @ref ixEthDBDatabaseMaintenance being called with a period of
- * @ref IX_ETH_DB_MAINTENANCE_TIME seconds.
- *
- * - Reentrant - yes
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to enable aging on
- *
- * @retval IX_ETH_DB_SUCCESS aging enabled successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is invalid
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortAgingEnable(IxEthDBPortId portID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn void ixEthDBDatabaseMaintenance(void)
- *
- * @brief Performs a maintenance operation on the Ethernet learning/filtering database
- *
- * In order to perform a database maintenance this function must be called every
- * @ref IX_ETH_DB_MAINTENANCE_TIME seconds. It should be called regardless of whether learning is
- * enabled or not.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @note this function call will be ignored if the learning feature is disabled
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBDatabaseMaintenance(void);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringDatabaseShow(IxEthDBPortId portID)
- *
- * @brief This function displays the Mac Ethernet MAC address filtering tables.
- *
- * It displays the MAC address, port ID, entry type (dynamic/static),and age for
- * the given port ID.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to display the MAC address entries
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is invalid
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized
- * @retval IX_ETH_DB_FAIL record browser failed due to an internal busy or lock condition
- *
- * @note this function is deprecated and kept for compatibility reasons; use @ref ixEthDBFilteringDatabaseShowRecords instead
- *
- * @see ixEthDBFilteringDatabaseShowRecords
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringDatabaseShow(IxEthDBPortId portID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn void ixEthDBFilteringDatabaseShowAll(void)
- *
- * @brief Displays the MAC address recorded in the filtering database for all registered
- * ports (see IxEthDBPortDefs.h), grouped by port ID.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @retval void
- *
- * @note this function is deprecated and kept for compatibility reasons; use @ref ixEthDBFilteringDatabaseShowRecords instead
- *
- * @see ixEthDBFilteringDatabaseShowRecords
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBFilteringDatabaseShowAll(void);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFilteringDatabaseShowRecords(IxEthDBPortId portID, IxEthDBRecordType recordFilter)
- *
- * @brief This function displays per port database records, given a record type filter
- *
- * The supported record type filters are:
- *
- * - IX_ETH_DB_FILTERING_RECORD - displays the non-VLAN filtering records (MAC address, age, static/dynamic)
- * - IX_ETH_DB_FILTERING_VLAN_RECORD - displays the VLAN filtering records (MAC address, age, static/dynamic, VLAN ID, CFI, QoS class)
- * - IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD - displays the previous two types of records
- * - IX_ETH_DB_WIFI_RECORD - displays the WiFi header conversion records (MAC address, optional gateway MAC address) and WiFi header conversion parameters (BBSID, Duration/ID)
- * - IX_ETH_DB_FIREWALL_RECORD - displays the firewall MAC address table and firewall operating mode (white list/black list)
- * - IX_ETH_DB_ALL_RECORD_TYPES - displays all the record types
- * - IX_ETH_DB_NO_RECORD_TYPE - displays only the port status (no records are displayed)
- *
- * Additionally, the status of each port will be displayed, containg the following information: type, capabilities, enabled status,
- * aging enabled status, group membership and maximum frame size.
- *
- * The port ID can either be an actual port or IX_ETH_DB_ALL_PORTS, in which case the requested information
- * will be displayed for all the ports (grouped by port)
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param portID ID of the port to display information on (use IX_ETH_DB_ALL_PORTS for all the ports)
- * @param recordFilter record type filter
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is invalid
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringDatabaseShowRecords(IxEthDBPortId portID, IxEthDBRecordType recordFilter);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortDependencyMapSet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap)
- *
- * @brief Sets the dependency port map for a port
- *
- * @param portID ID of the port to set the dependency map to
- * @param dependencyPortMap new dependency map (as bitmap, each bit set indicates a port being included)
- *
- * This function is used to share filtering information between ports.
- * By adding a port into another port's dependency map the target port
- * filtering data will import the filtering data from the port it depends on.
- * Any changes to filtering data for a port - such as adding, updating or removing records -
- * will trigger updates in the filtering information for all the ports depending on
- * on the updated port.
- *
- * For example, if ports 2 and 3 are set in the port 0 dependency map the filtering
- * information for port 0 will also include the filtering information from ports 2 and 3.
- * Adding a record to port 2 will also trigger an update not only on port 2 but also on
- * port 0.
- *
- * The dependency map is a 256 bit array where each bit corresponds to a port corresponding to the
- * bit offset (bit 0 - port 0, bit 1 - port 1 etc). Setting a bit to 1 indicates that the corresponding
- * port is the port map. For example, a dependency port map of 0x14 consists in the ports with IDs 2 and 4.
- * Note that the last bit (offset 255) is reserved and should never be set (it will be automatically
- * cleared by the function).
- *
- * By default, each port has a dependency port map consisting only of itself, i.e.
- *
- * @verbatim
- IxEthDBPortMap portMap;
-
- // clear all ports from port map
- memset(portMap, 0, sizeof (portMap));
-
- // include portID in port map
- portMap[portID / 8] = 1 << (portID % 8);
- @endverbatim
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @note Setting dependency maps is useful for NPE ports, which benefit from automatic updates
- * of filtering information. Setting dependency maps for user-defined ports is not an error
- * but will have no actual effect.
- *
- * @note Including a port in its own dependency map is not compulsory, however note that
- * in this case updating the port will not trigger an update on the port itself, which
- * might not be the intended behavior
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>dependencyPortMap</i> pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Filtering is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortDependencyMapSet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortDependencyMapGet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap)
- *
- * @brief Retrieves the dependency port map for a port
- *
- * @param portID ID of the port to set the dependency map to
- * @param dependencyPortMap location where the port dependency map is to be copied
- *
- * This function will copy the port dependency map to a user specified location.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>dependencyPortMap</i> pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Filtering is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortDependencyMapGet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortVlanTagSet(IxEthDBPortId portID, IxEthDBVlanTag vlanTag)
- *
- * @brief Sets the default 802.1Q VLAN tag for a given port
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to set the default VLAN tag to
- * @param vlanTag @ref IxEthDBVlanTag [in] - default 802.1Q VLAN tag
- *
- * The tag format has 16 bits and it is defined in the IEEE802.1Q specification.
- * This tag will be used for tagging untagged frames (if enabled) and classifying
- * unexpedited traffic into an internal traffic class (using the user priority field).
- *
- * <table border="1"> <caption> 802.1Q tag format </caption>
- * <tr> <td> <b> 3 bits <td> <b> 1 bit <td> <b> 12 bits </b>
- * <tr> <td> user priority <td> CFI <td> VID
- * </table>
- *
- * User Priority : Defines user priority, giving eight (2^3) priority levels. IEEE 802.1P defines
- * the operation for these 3 user priority bits
- *
- * CFI : Canonical Format Indicator is always set to zero for Ethernet switches. CFI is used for
- * compatibility reason between Ethernet type network and Token Ring type network. If a frame received
- * at an Ethernet port has a CFI set to 1, then that frame should not be forwarded as it is to an untagged port.
- *
- * VID : VLAN ID is the identification of the VLAN, which is basically used by the standard 802.1Q.
- * It has 12 bits and allow the id entification of 4096 (2^12) VLANs. Of the 4096 possible VIDs, a VID of 0
- * is used to identify priority frames and value 4095 (FFF) is reserved, so the maximum possible VLAN
- * configurations are 4,094.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_ETH_DB_INVALID_VLAN <i>vlanTag</i> argument does not parse to a valid 802.1Q VLAN tag
- *
- * @note a VLAN ID value of 0 indicates that the port is not part of any VLAN
- * @note the value of the cannonical frame indicator (CFI) field is ignored, the
- * field being used only in frame tagging operations
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanTagSet(IxEthDBPortId portID, IxEthDBVlanTag vlanTag);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortVlanTagGet(IxEthDBPortId portID, IxEthDBVlanTag *vlanTag)
- *
- * @brief Retrieves the default 802.1Q port VLAN tag for a given port (see also @ref ixEthDBPortVlanTagSet)
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to retrieve the default VLAN tag from
- * @param vlanTag @ref IxEthDBVlanTag [out] - location to write the default port 802.1Q VLAN tag to
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid vlanTag pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanTagGet(IxEthDBPortId portID, IxEthDBVlanTag *vlanTag);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBVlanTagSet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag vlanTag)
- *
- * @brief Sets the 802.1Q VLAN tag for a database record
- *
- * @param macAddr MAC address
- * @param vlanTag 802.1Q VLAN tag
- *
- * This function is used together with @ref ixEthDBVlanTagGet to provide MAC-based VLAN classification support.
- * Please note that the bridging application must contain specific code to make use of this feature (see below).
- *
- * VLAN tags can be set only in IX_ETH_DB_FILTERING_RECORD or IX_ETH_DB_FILTERING_VLAN_RECORD type records.
- * If to an IX_ETH_DB_FILTERING_RECORD type record is added a VLAN tag the record type is automatically
- * changed to IX_ETH_DB_FILTERING_VLAN_RECORD. Once this has occurred the record type will never
- * revert to a non-VLAN type (unless deleted and re-added).
- *
- * Record types used for different purposes (such as IX_ETH_DB_WIFI_RECORD) will be ignored by
- * this function.
- *
- * After using this function to associate a VLAN ID with a MAC address the VLAN ID can be extracted knowing the
- * MAC address using @ref ixEthDBVlanTagGet. This mechanism can be used to implement MAC-based VLAN classification
- * if a bridging application searches for the VLAN tag when receiving a frame based on the source MAC address
- * (contained in the <i>ixp_ne_src_mac</i> field of the buffer header).
- * If found in the database, the application can instruct the NPE to tag the frame by writing the VLAN tag
- * in the <i>ixp_ne_vlan_tci</i> field of the buffer header. This way the NPE will inspect the Egress tagging
- * rule associated with the given VLAN ID on the Tx port and tag the frame if Egress tagging on the VLAN is
- * allowed. Additionally, Egress tagging can be forced by setting the <i>ixp_ne_tx_flags.tag_over</i> and
- * <i>ixp_ne_tx_flags.tag_mode</i> flags in the buffer header.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @note this function will <b>not</b> add a filtering record, it can only be used to update an existing one
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer
- * @retval IX_ETH_DB_NO_SUCH_ADDR a filtering record with the specified MAC address was not found
- * @retval IX_ETH_DB_INVALID_VLAN <i>vlanTag</i> argument does not parse to a valid 802.1Q VLAN tag
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBVlanTagSet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag vlanTag);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn ixEthDBVlanTagGet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag *vlanTag)
- *
- * @brief Retrieves the 802.1Q VLAN tag from a database record given the record MAC address
- *
- * @param macAddr MAC address
- * @param vlanTag location to write the record 802.1Q VLAN tag to
- *
- * @note VLAN tags can be retrieved only from IX_ETH_DB_FILTERING_VLAN_RECORD type records
- *
- * This function is used together with ixEthDBVlanTagSet to provide MAC-based VLAN classification support.
- * Please note that the bridging application must contain specific code to make use of this feature (see @ref ixEthDBVlanTagSet).
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> or <i>vlanTag</i> pointer
- * @retval IX_ETH_DB_NO_SUCH_ADDR a filtering record with the specified MAC address was not found
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBVlanTagGet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag *vlanTag);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortVlanMembershipAdd(IxEthDBPortId portID, IxEthDBVlanId vlanID)
- *
- * @brief Adds a VLAN ID to a port's VLAN membership table
- *
- * Adding a VLAN ID to a port's VLAN membership table will cause frames tagged with the specified
- * VLAN ID to be accepted by the frame filter, if Ingress VLAN membership filtering is enabled.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to add the VLAN ID membership to
- * @param vlanID @ref IxEthDBVlanId [in] - VLAN ID to be added to the port membership table
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_VLAN vlanID is not a valid VLAN ID
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- *
- * @note A port's default VLAN ID is always in its own membership table, hence there
- * is no need to explicitly add it using this function (although it is not an error
- * to do so)
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanMembershipAdd(IxEthDBPortId portID, IxEthDBVlanId vlanID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortVlanMembershipRangeAdd(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax)
- *
- * @brief Adds a VLAN ID range to a port's VLAN membership table
- *
- * All the VLAN IDs in the specified range will be added to the port VLAN
- * membership table, including the range start and end VLAN IDs. Tagged frames with
- * VLAN IDs in the specified range will be accepted by the frame filter, if Ingress VLAN
- * membership filtering is enabled.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to add the VLAN membership range into
- * @param vlanIDMin @ref IxEthDBVlanId [in] - start of the VLAN ID range
- * @param vlanIDMax @ref IxEthDBVlanId [in] - end of the VLAN ID range
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_VLAN the specified VLAN IDs are invalid or do not constitute a range
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- *
- * @note Is is valid to use the same VLAN ID for both vlanIDMin and vlanIDMax, in which case this
- * function will behave as @ref ixEthDBPortVlanMembershipAdd
- *
- * @note A port's default VLAN ID is always in its own membership table, hence there is no need
- * to explicitly add it using this function (although it is not an error to do so)
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanMembershipRangeAdd(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortVlanMembershipRemove(IxEthDBPortId portID, IxEthDBVlanId vlanID)
- *
- * @brief Removes a VLAN ID from a port's VLAN membership table
- *
- * Frames tagged with a VLAN ID which is not in a port's VLAN membership table
- * will be discarded by the frame filter, if Ingress membership filtering is enabled.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to remove the VLAN ID membership from
- * @param vlanID @ref IxEthDBVlanId [in] - VLAN ID to be removed from the port membership table
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_INVALID_VLAN vlanID is not a valid VLAN ID
- * @retval IX_ETH_DB_NO_PERMISSION attempted to remove the default VLAN ID
- * from the port membership table (vlanID was set to the default port VLAN ID)
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- *
- * @note A port's default VLAN ID cannot be removed from the port's membership
- * table; attempting it will return IX_ETH_DB_NO_PERMISSION
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanMembershipRemove(IxEthDBPortId portID, IxEthDBVlanId vlanID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortVlanMembershipRangeRemove(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax)
- *
- * @brief Removes a VLAN ID range from a port's VLAN membership table
- *
- * All the VLAN IDs in the specified range will be removed from the port VLAN
- * membership table, including the range start and end VLAN IDs. Tagged frames
- * with VLAN IDs in the range will be discarded by the frame filter, if Ingress
- * membership filtering is enabled.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to remove the VLAN membership range from
- * @param vlanIDMin @ref IxEthDBVlanId [in] - start of the VLAN ID range
- * @param vlanIDMax @ref IxEthDBVlanId [in] - end of the VLAN ID range
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_VLAN the specified VLAN IDs are invalid or do not constitute a range
- * @retval IX_ETH_DB_NO_PERMISSION attempted to remove the default VLAN ID
- * from the port membership table (both vlanIDMin and vlanIDMax were set to the default port VLAN ID)
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- *
- * @note Is is valid to use the same VLAN ID for both vlanIDMin and vlanIDMax, in which case
- * function will behave as @ref ixEthDBPortVlanMembershipRemove
- *
- * @note If the given range overlaps the default port VLAN ID this function
- * will remove all the VLAN IDs in the range except for the port VLAN ID from its
- * own membership table. This situation will be silently dealt with (no error message
- * will be returned) as long as the range contains more than one value (i.e. at least
- * one other value, apart from the default port VLAN ID). If the function is called
- * with the vlanIDMin and vlanIDMax parameters both set to the port default VLAN ID, the
- * function will infer that an attempt was specifically made to remove the default port
- * VLAN ID from the port membership table, in which case the return value will be
- * IX_ETH_DB_NO_PERMISSION.
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanMembershipRangeRemove(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortVlanMembershipSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
- *
- * @brief Sets a port's VLAN membership table
- *
- * Sets a port's VLAN membership table from a complete VLAN table containing all the possible
- * 4096 VLAN IDs. The table format is an array containing 4096 bits (512 bytes), where each bit
- * indicates whether the VLAN at that bit index is in the port's membership list (if set) or
- * not (unset).
- *
- * The bit at index 0, indicating VLAN ID 0, indicates no VLAN membership and therefore no
- * other bit must be set if bit 0 is set.
- *
- * The bit at index 4095 is reserved and should never be set (it will be ignored if set).
- *
- * The bit referencing the same VLAN ID as the default port VLAN ID should always be set, as
- * the membership list must contain at least the default port VLAN ID.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to set the VLAN membership table to
- * @param vlanSet @ref IxEthDBVlanSet [in] - pointer to the VLAN membership table
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>vlanSet</i> pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanMembershipSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPortVlanMembershipGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
- *
- * @brief Retrieves a port's VLAN membership table
- *
- * Retrieves the complete VLAN membership table from a port, containing all the possible
- * 4096 VLAN IDs. The table format is an array containing 4096 bits (512 bytes), where each bit
- * indicates whether the VLAN at that bit index is in the port's membership list (if set) or
- * not (unset).
- *
- * The bit at index 0, indicating VLAN ID 0, indicates no VLAN membership and therefore no
- * other bit will be set if bit 0 is set.
- *
- * The bit at index 4095 is reserved and will not be set (it will be ignored if set).
- *
- * The bit referencing the same VLAN ID as the default port VLAN ID will always be set, as
- * the membership list must contain at least the default port VLAN ID.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to retrieve the VLAN membership table from
- * @param vlanSet @ref IxEthDBVlanSet [out] - pointer a location where the VLAN membership table will be
- * written to
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>vlanSet</i> pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanMembershipGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBAcceptableFrameTypeSet(IxEthDBPortId portID, IxEthDBFrameFilter frameFilter)
- *
- * @brief Sets a port's acceptable frame type filter
- *
- * The acceptable frame type is one (or a combination) of the following values:
- * - IX_ETH_DB_ACCEPT_ALL_FRAMES - accepts all the frames
- * - IX_ETH_DB_UNTAGGED_FRAMES - accepts untagged frames
- * - IX_ETH_DB_VLAN_TAGGED_FRAMES - accepts tagged frames
- * - IX_ETH_DB_PRIORITY_TAGGED_FRAMES - accepts tagged frames with VLAN ID set to 0 (no VLAN membership)
- *
- * Except for using the exact values given above only the following combinations are valid:
- * - IX_ETH_DB_UNTAGGED_FRAMES | IX_ETH_DB_VLAN_TAGGED_FRAMES
- * - IX_ETH_DB_UNTAGGED_FRAMES | IX_ETH_DB_PRIORITY_TAGGED_FRAMES
- *
- * Please note that IX_ETH_DB_UNTAGGED_FRAMES | IX_ETH_DB_VLAN_TAGGED_FRAMES is equivalent
- * to IX_ETH_DB_ACCEPT_ALL_FRAMES.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @note by default the acceptable frame type filter is set to IX_ETH_DB_ACCEPT_ALL_FRAMES
- *
- * @note setting the acceptable frame type to PRIORITY_TAGGED_FRAMES is internally
- * accomplished by changing the frame filter to VLAN_TAGGED_FRAMES and setting the
- * VLAN membership list to include only VLAN ID 0; the membership list will need
- * to be restored manually to an appropriate value if the acceptable frame type
- * filter is changed back to ACCEPT_ALL_FRAMES or VLAN_TAGGED_FRAMES; failure to do so
- * will filter all VLAN traffic bar frames tagged with VLAN ID 0
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to set the acceptable frame type filter to
- * @param frameFilter @ref IxEthDBFrameFilter [in] - acceptable frame type filter
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid frame type filter
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBAcceptableFrameTypeSet(IxEthDBPortId portID, IxEthDBFrameFilter frameFilter);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBAcceptableFrameTypeGet(IxEthDBPortId portID, IxEthDBFrameFilter *frameFilter)
- *
- * @brief Retrieves a port's acceptable frame type filter
- *
- * For a description of the acceptable frame types see @ref ixEthDBAcceptableFrameTypeSet
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID to retrieve the acceptable frame type filter from
- * @param frameFilter @ref IxEthDBFrameFilter [out] - location to store the acceptable frame type filter
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>frameFilter</i> pointer argument
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBAcceptableFrameTypeGet(IxEthDBPortId portID, IxEthDBFrameFilter *frameFilter);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPriorityMappingTableSet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable)
- *
- * @brief Sets a port's priority mapping table
- *
- * The priority mapping table is an 8x2 table mapping a QoS (user) priority into an internal
- * traffic class. There are 8 valid QoS priorities (0..7, 0 being the lowest) which can be
- * mapped into one of the 4 available traffic classes (0..3, 0 being the lowest).
- * If a custom priority mapping table is not specified using this function the following
- * default priority table will be used (as per IEEE 802.1Q and IEEE 802.1D):
- *
- * <table border="1"> <caption> QoS traffic classes </caption>
- * <tr> <td> <b> QoS priority <td> <b> Default traffic class <td> <b> Traffic type </b>
- * <tr> <td> 0 <td> 1 <td> Best effort, default class for unexpedited traffic
- * <tr> <td> 1 <td> 0 <td> Background traffic
- * <tr> <td> 2 <td> 0 <td> Spare bandwidth
- * <tr> <td> 3 <td> 1 <td> Excellent effort
- * <tr> <td> 4 <td> 2 <td> Controlled load
- * <tr> <td> 5 <td> 2 <td> Video traffic
- * <tr> <td> 6 <td> 3 <td> Voice traffic
- * <tr> <td> 7 <td> 3 <td> Network control
- * </table>
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - port ID of the port to set the priority mapping table to
- * @param priorityTable @ref IxEthDBPriorityTable [in] - location of the user priority table
- *
- * @note The provided table will be copied into internal data structures in EthDB and
- * can be deallocated by the called after this function has completed its execution, if
- * so desired
- *
- * @warning The number of available traffic classes differs depending on the NPE images
- * and queue configuration. Check IxEthDBQoS.h for up-to-date information on the availability of
- * traffic classes. Note that specifiying a traffic class in the priority map which exceeds
- * the system availability will produce an IX_ETH_DB_INVALID_PRIORITY return error code and no
- * priority will be remapped.
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>priorityTable</i> pointer
- * @retval IX_ETH_DB_INVALID_PRIORITY at least one priority value exceeds
- * the current number of available traffic classes
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPriorityMappingTableSet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPriorityMappingTableGet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable)
- *
- * @brief Retrieves a port's priority mapping table
- *
- * The priority mapping table for the given port will be copied in the location
- * specified by the caller using "priorityTable"
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param portID ID @ref IxEthDBPortId [in] - of the port to retrieve the priority mapping table from
- * @param priorityTable @ref IxEthDBPriorityTable [out] - pointer to a user specified location where the table will be copied to
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid priorityTable pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPriorityMappingTableGet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPriorityMappingClassSet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority trafficClass)
- *
- * @brief Sets one QoS/user priority => traffic class mapping in a port's priority mapping table
- *
- * This function establishes a mapping between a user (QoS) priority and an internal traffic class.
- * The mapping will be saved in the port's priority mapping table. Use this function when not all
- * the QoS priorities need remapping (see also @ref ixEthDBPriorityMappingTableSet)
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to set the mapping to
- * @param userPriority @ref IxEthDBPriority [in] - user (QoS) priority, between 0 and 7 (0 being the lowest)
- * @param trafficClass @ref IxEthDBPriority [in] - internal traffic class, between 0 and 3 (0 being the lowest)
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_PRIORITY <i>userPriority</i> out of range or
- * <i>trafficClass</i> is beyond the number of currently available traffic classes
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPriorityMappingClassSet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority trafficClass);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBPriorityMappingClassGet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority *trafficClass)
- *
- * @brief Retrieves one QoS/user priority => traffic class mapping in a port's priority mapping table
- *
- * This function retrieves the internal traffic class associated with a QoS (user) priority from a given
- * port's priority mapping table. Use this function when not all the QoS priority mappings are
- * required (see also @ref ixEthDBPriorityMappingTableGet)
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to set the mapping to
- * @param userPriority @ref IxEthDBPriority [in] - user (QoS) priority, between 0 and 7 (0 being the lowest)
- * @param trafficClass @ref IxEthDBPriority [out] - location to write the corresponding internal traffic class to
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_PRIORITY invalid userPriority value (out of range)
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>trafficClass</i> pointer argument
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPriorityMappingClassGet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority *trafficClass);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL enabled)
- *
- * @brief Enables or disables Egress VLAN tagging for a port and a given VLAN
- *
- * This function enables or disables Egress VLAN tagging for the given port and VLAN ID.
- * If the VLAN tagging for a certain VLAN ID is enabled then all the frames to be
- * transmitted on the given port tagged with the same VLAN ID will be transmitted in a tagged format.
- * If tagging is not enabled for the given VLAN ID, the VLAN tag from the frames matching
- * this VLAN ID will be removed (the frames will be untagged).
- *
- * VLAN ID 4095 is reserved and should never be used with this function.
- * VLAN ID 0 has the special meaning of "No VLAN membership" and it is used in this
- * context to allow the port to send priority-tagged frames or not.
- *
- * By default, no Egress VLAN tagging is enabled on any port.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to enable or disable the VLAN ID Egress tagging on
- * @param vlanID @ref IxEthDBVlanId [in] - VLAN ID to be matched against outgoing frames
- * @param enabled BOOL [in] - TRUE to enable Egress VLAN tagging on the port and given VLAN, and
- * FALSE to disable Egress VLAN tagging
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_VLAN invalid VLAN ID (out of range)
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL enabled);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL *enabled)
- *
- * @brief Retrieves the Egress VLAN tagging enabling status for a port and VLAN ID
- *
- * @param portID [in] - ID of the port to extract the Egress VLAN ID tagging status from
- * @param vlanID VLAN [in] - ID whose tagging status is to be extracted
- * @param enabled [in] - user-specifed location where the status is copied to; following
- * the successfull execution of this function the value will be TRUE if Egress VLAN
- * tagging is enabled for the given port and VLAN ID, and FALSE otherwise
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @see ixEthDBEgressVlanEntryTaggingEnabledGet
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_VLAN invalid VLAN ID (out of range)
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>enabled</i> argument pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL *enabled);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBEgressVlanRangeTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax, BOOL enabled)
- *
- * @brief Enables or disables Egress VLAN tagging for a port and given VLAN range
- *
- * This function is very similar to @ref ixEthDBEgressVlanEntryTaggingEnabledSet with the
- * difference that it can manipulate the Egress tagging status on multiple VLAN IDs,
- * defined by a contiguous range. Note that both limits in the range are explicitly
- * included in the execution of this function.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to enable or disable the VLAN ID Egress tagging on
- * @param vlanIDMin @ref IxEthDBVlanId [in] - start of the VLAN range to be matched against outgoing frames
- * @param vlanIDMax @ref IxEthDBVlanId [in] - end of the VLAN range to be matched against outgoing frames
- * @param enabled BOOL [in] - TRUE to enable Egress VLAN tagging on the port and given VLAN range,
- * and FALSE to disable Egress VLAN tagging
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_VLAN invalid VLAN ID (out of range), or do not constitute a range
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_ETH_DB_NO_PERMISSION attempted to explicitly remove the default port VLAN ID from the tagging table
- * @retval IX_FAIL unknown OS or NPE communication error
- *
- * @note Specifically removing the default port VLAN ID from the Egress tagging table by setting both vlanIDMin and vlanIDMax
- * to the VLAN ID portion of the PVID is not allowed by this function and will return IX_ETH_DB_NO_PERMISSION.
- * However, this can be circumvented, should the user specifically desire this, by either using a
- * larger range (vlanIDMin < vlanIDMax) or by using ixEthDBEgressVlanEntryTaggingEnabledSet.
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBEgressVlanRangeTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax, BOOL enabled);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBEgressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
- *
- * @brief Sets the complete Egress VLAN tagging table for a port
- *
- * This function is used to set the VLAN tagging/untagging per VLAN ID for a given port
- * covering the entire VLAN ID range (0..4094). The <i>vlanSet</i> parameter is a 4096
- * bit array, each bit indicating the Egress behavior for the corresponding VLAN ID.
- * If a bit is set then outgoing frames with the corresponding VLAN ID will be transmitted
- * with the VLAN tag, otherwise the frame will be transmitted without the VLAN tag.
- *
- * Bit 0 has a special significance, indicating tagging or tag removal for priority-tagged
- * frames.
- *
- * Bit 4095 is reserved and should never be set (it will be ignored if set).
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port whose Egress VLAN tagging behavior is set
- * @param vlanSet @ref IxEthDBVlanSet [in] - 4096 bit array controlling per-VLAN tagging and untagging
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>vlanSet</i> pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- *
- * @warning This function will automatically add the default port VLAN ID to the Egress tagging table
- * every time it is called. The user should manually call ixEthDBEgressVlanEntryTaggingEnabledSet to
- * prevent tagging on the default port VLAN ID if the default behavior is not intended.
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBEgressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBEgressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
- *
- * @brief Retrieves the complete Egress VLAN tagging table from a port
- *
- * This function copies the 4096 bit table controlling the Egress VLAN tagging into a user specified
- * area. Each bit in the array indicates whether tagging for the corresponding VLAN (the bit position
- * in the array) is enabled (the bit is set) or not (the bit is unset).
- *
- * Bit 4095 is reserved and should not be set (it will be ignored if set).
- *
- * @see ixEthDBEgressVlanTaggingEnabledSet
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port whose Egress VLAN tagging behavior is retrieved
- * @param vlanSet @ref IxEthDBVlanSet [out] - user location to copy the Egress tagging table into; should have
- * room to store 4096 bits (512 bytes)
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>vlanSet</i> pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBEgressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBIngressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBTaggingAction taggingAction)
- *
- * @brief Sets the Ingress VLAN tagging behavior for a port
- *
- * A port's Ingress tagging behavior is controlled by the taggingAction parameter,
- * which can take one of the following values:
- *
- * - IX_ETH_DB_PASS_THROUGH - leaves the frame unchanged (does not add or remove the VLAN tag)
- * - IX_ETH_DB_ADD_TAG - adds the VLAN tag if not present, using the default port VID
- * - IX_ETH_DB_REMOVE_TAG - removes the VLAN tag if present
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port whose Ingress VLAN tagging behavior is set
- * @param taggingAction @ref IxEthDBTaggingAction [in] - tagging behavior for the port
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>taggingAction</i> argument
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBIngressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBTaggingAction taggingAction);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBIngressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBTaggingAction *taggingAction)
- *
- * @brief Retrieves the Ingress VLAN tagging behavior from a port (see @ref ixEthDBIngressVlanTaggingEnabledSet)
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port whose Ingress VLAN tagging behavior is set
- * @param taggingAction @ref IxEthDBTaggingAction [out] - location where the tagging behavior for the port is written to
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>taggingAction</i> pointer argument
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBIngressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBTaggingAction *taggingAction);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBVlanPortExtractionEnable(IxEthDBPortId portID, BOOL enable)
- *
- * @brief Enables or disables port ID extraction
- *
- * This feature can be used in the situation when a multi-port device (e.g. a switch)
- * is connected to an IXP4xx port and the device can provide incoming frame port
- * identification by tagging the TPID field in the Ethernet frame. Enabling
- * port extraction will instruct the NPE to copy the TPID field from the frame and
- * place it in the <i>ixp_ne_src_port</i> of the <i>ixp_buf</i> header. In addition,
- * the NPE restores the TPID field to 0.
- *
- * If the frame is not tagged the NPE will fill the <i>ixp_ne_src_port</i> with the
- * port ID of the MII interface the frame was received from.
- *
- * The TPID field is the least significant byte of the type/length field, which is
- * normally set to 0x8100 for 802.1Q-tagged frames.
- *
- * This feature is disabled by default.
- *
- * @param portID ID of the port to configure port ID extraction on
- * @param enable TRUE to enable port ID extraction and FALSE to disable it
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port
- * @retval IX_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBVlanPortExtractionEnable(IxEthDBPortId portID, BOOL enable);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFeatureCapabilityGet(IxEthDBPortId portID, IxEthDBFeature *featureSet)
- *
- * @brief Retrieves the feature capability set for a port
- *
- * This function retrieves the feature capability set for a port or the common capabilities shared between all
- * the ports, writing the feature capability set in a user specified location.
- *
- * The feature capability set will consist of a set formed by OR-ing one or more of the following values:
- * - IX_ETH_DB_LEARNING - Learning feature; enables EthDB to learn MAC address (filtering) records, including 802.1Q enabled records
- * - IX_ETH_DB_FILTERING - Filtering feature; enables EthDB to communicate with the NPEs for downloading filtering information in the NPEs; depends on the learning feature
- * - IX_ETH_DB_VLAN_QOS - VLAN/QoS feature; enables EthDB to configure NPEs to operate in VLAN/QoS aware modes
- * - IX_ETH_DB_FIREWALL - Firewall feature; enables EthDB to configure NPEs to operate in firewall mode, using white/black address lists
- * - IX_ETH_DB_SPANNING_TREE_PROTOCOL - Spanning tree protocol feature; enables EthDB to configure the NPEs as STP nodes
- * - IX_ETH_DB_WIFI_HEADER_CONVERSION - WiFi 802.3 to 802.11 header conversion feature; enables EthDB to handle WiFi conversion data
- *
- * Note that EthDB provides only the LEARNING feature for non-NPE ports.
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to retrieve the capability set for
- * (use IX_ETH_DB_ALL_PORTS to retrieve the common capabilities shared between all the ports)
- * @param featureSet @ref IxEthDBFeature [out] - location where the capability set will be written to
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>featureSet</i> pointer
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeatureCapabilityGet(IxEthDBPortId portID, IxEthDBFeature *featureSet);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, BOOL enabled)
- *
- * @brief Enables or disables one or more EthDB features
- *
- * Selects one or more features (see @ref ixEthDBFeatureCapabilityGet for a description of the supported
- * features) to be enabled or disabled on the selected port (or all the ports).
- *
- * Note that some features are mutually incompatible:
- * - IX_ETH_DB_FILTERING is incompatible with IX_ETH_DB_WIFI_HEADER_CONVERSION
- *
- * Also note that some features require other features to be enabled:
- * - IX_ETH_DB_FILTERING requires IX_ETH_DB_LEARNING
- *
- * This function will either enable the entire selected feature set for the selected port (or all the ports),
- * in which case it will return IX_ETH_DB_SUCCESS, or in case of error it will not enable any feature at all
- * and return an appropriate error message.
- *
- * The following features are enabled by default (for ports with the respective capability),
- * for compatibility reasons with previous versions of CSR:
- * - IX_ETH_DB_LEARNING
- * - IX_ETH_DB_FILTERING
- *
- * All other features are disabled by default and require manual enabling using ixEthDBFeatureEnable.
- *
- * <b>Default settings for VLAN, QoS, Firewall and WiFi header conversion features:</b>
- *
- * <i>VLAN</i>
- *
- * When the VLAN/QoS feature is enabled for a port for the first time the default VLAN behavior
- * of the port is set to be as <b>permissive</b> (it will accept all the frames) and
- * <b>non-interferential</b> (it will not change any frames) as possible:
- * - the port VLAN ID (VID) is set to 0
- * - the Ingress acceptable frame filter is set to accept all frames
- * - the VLAN port membership is set to the complete VLAN range (0 - 4094)
- * - the Ingress tagging mode is set to pass-through (will not change frames)
- * - the Egress tagging mode is to send tagged frames in the entire VLAN range (0 - 4094)
- *
- * Note that further disabling and re-enabling the VLAN feature for a given port will not reset the port VLAN behavior
- * to the settings listed above. Any VLAN settings made by the user are kept.
- *
- * <i>QoS</i>
- *
- * The following default priority mapping table will be used (as per IEEE 802.1Q and IEEE 802.1D):
- *
- * <table border="1"> <caption> QoS traffic classes </caption>
- * <tr> <td> <b> QoS priority <td> <b> Default traffic class <td> <b> Traffic type </b>
- * <tr> <td> 0 <td> 1 <td> Best effort, default class for unexpedited traffic
- * <tr> <td> 1 <td> 0 <td> Background traffic
- * <tr> <td> 2 <td> 0 <td> Spare bandwidth
- * <tr> <td> 3 <td> 1 <td> Excellent effort
- * <tr> <td> 4 <td> 2 <td> Controlled load
- * <tr> <td> 5 <td> 2 <td> Video traffic
- * <tr> <td> 6 <td> 3 <td> Voice traffic
- * <tr> <td> 7 <td> 3 <td> Network control
- * </table>
- *
- * <i> Firewall </i>
- *
- * The port firewall is configured by default in <b>black-list mode</b>, and the firewall address table is empty.
- * This means the firewall will not filter any frames until the feature is configured and the firewall table is
- * downloaded to the NPE.
- *
- * <i> Spanning Tree </i>
- *
- * The port is set to <b>STP unblocked mode</b>, therefore it will accept all frames until re-configured.
- *
- * <i> WiFi header conversion </i>
- *
- * The WiFi header conversion database is empty, therefore no actual header conversion will take place until this
- * feature is configured and the conversion table downloaded to the NPE.
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port to enable or disable the features on (use IX_ETH_DB_ALL_PORTS for all the ports)
- * @param feature @ref IxEthDBFeature [in] - feature or feature set to enable or disable
- * @param enabled BOOL [in] - TRUE to enable the feature and FALSE to disable it
- *
- * @note Certain features, from a functional point of view, cannot be disabled as such at NPE level;
- * when such features are set to <i>disabled</i> using the EthDB API they will be configured in such
- * a way to determine a behavior equivalent to the feature being disabled. As well as this, disabled
- * features cannot be configured or accessed via the EthDB API (except for getting their status).
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_NO_PERMISSION attempted to enable mutually exclusive features,
- * or a feature that depends on another feature which is not present or enabled
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE at least one of the features selected is unavailable
- * @retval IX_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, BOOL enabled);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFeatureStatusGet(IxEthDBPortId portID, IxEthDBFeature feature, BOOL *present, BOOL *enabled)
- *
- * @brief Retrieves the availability and status of a feature set
- *
- * This function returns the availability and status for a feature set.
- * Note that if more than one feature is selected (e.g. IX_ETH_DB_LEARNING | IX_ETH_DB_FILTERING)
- * the "present" and "enabled" return values will be set to TRUE only if all the features in the
- * feature set are present and enabled (not only some).
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param feature @ref IxEthDBFeature [in] - identifier of the feature to retrieve the status for
- * @param present BOOL [out] - location where a boolean flag indicating whether this feature is present will be written to
- * @param enabled BOOL [out] - location where a boolean flag indicating whether this feature is enabled will be written to
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG either <i>present</i> or <i>enabled</i> pointer argument is invalid
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeatureStatusGet(IxEthDBPortId portID, IxEthDBFeature feature, BOOL *present, BOOL *enabled);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFeaturePropertyGet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, IxEthDBPropertyType *type, void *value)
- *
- * @brief Retrieves the value of a feature property
- *
- * The EthDB features usually contain feature-specific properties describing or
- * controlling how the feature operates. While essential properties (e.g. the
- * firewall operating mode) have their own API, secondary properties can be
- * retrieved using this function.
- *
- * Properties can be read-only or read-write. ixEthDBFeaturePropertyGet operates with
- * both types of features.
- *
- * Properties have types associated with them. A descriptor indicating the property
- * type is returned in the <i>type</i> argument for convenience.
- *
- * The currently supported properties and their corresponding features are as follows:
- *
- * <table border="1"> <caption> Properties for IX_ETH_DB_VLAN_QOS </caption>
- * <tr> <td> <b> Property identifier <td> <b> Property type <td> <b> Property value <td> <b> Read-Only </b>
- * <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_COUNT_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> number of internal traffic classes <td> Yes
- * <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> queue assignment for traffic class 0 <td> Yes
- * <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_1_RX_QUEUE_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> queue assignment for traffic class 1 <td> Yes
- * <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_2_RX_QUEUE_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> queue assignment for traffic class 2 <td> Yes
- * <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_3_RX_QUEUE_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> queue assignment for traffic class 3 <td> Yes
- * <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_4_RX_QUEUE_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> queue assignment for traffic class 4 <td> Yes
- * <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_5_RX_QUEUE_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> queue assignment for traffic class 5 <td> Yes
- * <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_6_RX_QUEUE_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> queue assignment for traffic class 6 <td> Yes
- * <tr> <td> IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY <td> IX_ETH_DB_INTEGER_PROPERTY <td> queue assignment for traffic class 7 <td> Yes
- * </table>
- *
- * @see ixEthDBFeaturePropertySet
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param feature @ref IxEthDBFeature [in] - EthDB feature for which the property is retrieved
- * @param property @ref IxEthDBProperty [in] - property identifier
- * @param type @ref IxEthDBPropertyType [out] - location where the property type will be stored
- * @param value void [out] - location where the property value will be stored
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_INVALID_ARG invalid property identifier, <i>type</i> or <i>value</i> pointer arguments
- * @retval IX_ETH_DB_FAIL incorrect property value or unknown error
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeaturePropertyGet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, IxEthDBPropertyType *type, void *value);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFeaturePropertySet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, void *value)
- *
- * @brief Sets the value of a feature property
- *
- * Unlike @ref ixEthDBFeaturePropertyGet, this function operates only with read-write properties
- *
- * The currently supported properties and their corresponding features are as follows:
- *
- * - IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE (for IX_ETH_DB_VLAN_QOS): freezes the availability of traffic classes
- * to the number of traffic classes currently in use
- *
- * Note that this function creates deep copies of the property values; once the function is invoked the client
- * can free or reuse the memory area containing the original property value.
- *
- * Copy behavior for different property types is defined as follows:
- *
- * - IX_ETH_DB_INTEGER_PROPERTY - 4 bytes are copied from the source location
- * - IX_ETH_DB_STRING_PROPERTY - the source string will be copied up to the NULL '\0' string terminator, maximum of 255 characters
- * - IX_ETH_DB_MAC_ADDR_PROPERTY - 6 bytes are copied from the source location
- * - IX_ETH_DB_BOOL_PROPERTY - 4 bytes are copied from the source location; the only allowed values are TRUE (1L) and false (0L)
- *
- * @see ixEthDBFeaturePropertySet
- *
- * @warning IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE is provided for EthAcc internal use;
- * do not attempt to set this property directly
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param feature @ref IxEthDBFeature [in] - EthDB feature for which the property is set
- * @param property @ref IxEthDBProperty [in] - property identifier
- * @param value void [in] - location where the property value is to be copied from
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_INVALID_ARG invalid property identifier, <i>value</i> pointer, or invalid property value
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeaturePropertySet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, void *value);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBDatabaseClear(IxEthDBPortId portID, IxEthDBRecordType recordType)
- *
- * @brief Deletes a set of record types from the Ethernet Database
- *
- * This function deletes all the records of certain types (specified in the recordType filter)
- * associated with a port. Additionally, the IX_ETH_DB_ALL_PORTS value can be used as port ID
- * to indicate that the specified record types should be deleted for all the ports.
- *
- * The record type filter can be an ORed combination of the following types:
- *
- * <caption> Record types </caption>
- * - IX_ETH_DB_FILTERING_RECORD <table><caption> Filtering record </caption>
- * <tr><td> MAC address <td> static/dynamic type <td> age </tr>
- * </table>
- *
- * - IX_ETH_DB_FILTERING_VLAN_RECORD <table><caption> VLAN-enabled filtering record </caption>
- * <tr><td> MAC address <td> static/dynamic type <td> age <td> 802.1Q tag </tr>
- * </table>
- *
- * - IX_ETH_DB_WIFI_RECORD <table><caption> WiFi header conversion record </caption>
- * <tr><td> MAC address <td> optional gateway MAC address <td> </tr>
- * </table>
- *
- * - IX_ETH_DB_FIREWALL_RECORD <table><caption> Firewall record </caption>
- * <tr><td> MAC address </tr>
- * </table>
- * - IX_ETH_DB_ALL_RECORD_TYPES
- *
- * Any combination of the above types is valid e.g.
- *
- * (IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD | IX_ETH_DB_FIREWALL_RECORD),
- *
- * although some might be redundant (it is not an error to do so) e.g.
- *
- * (IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_ALL_RECORD_TYPES)
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param recordType @ref IxEthDBRecordType [in] - record type filter
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>recordType</i> filter
- *
- * @note If the record type filter contains any unrecognized value (hence the
- * IX_ETH_DB_INVALID_ARG error value is returned) no actual records will be deleted.
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBDatabaseClear(IxEthDBPortId portID, IxEthDBRecordType recordType);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBWiFiStationEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Adds an "Access Point to Station" record to the database, for 802.3 => 802.11 frame
- * header conversion
- *
- * Frame header conversion is controlled by the set of MAC addresses
- * added using @ref ixEthDBWiFiStationEntryAdd and @ref ixEthDBWiFiAccessPointEntryAdd.
- * Conversion arguments are added using @ref ixEthDBWiFiFrameControlSet,
- * @ref ixEthDBWiFiDurationIDSet and @ref ixEthDBWiFiBBSIDSet.
- *
- * Note that adding the same MAC address twice will not return an error
- * (but will not accomplish anything either), while re-adding a record previously added
- * as an "Access Point to Access Point" will migrate the record to the "Access Point
- * to Station" type.
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to add
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_INVALID_ARG macAddr is an invalid pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer argument
- * @retval IX_ETH_DB_NOMEM maximum number of records reached
- * @retval IX_ETH_DB_BUSY lock condition or transaction in progress, try again later
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiStationEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBWiFiAccessPointEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr, IxEthDBMacAddr *gatewayMacAddr)
- *
- * @brief Adds an "Access Point to Access Point" record to the database
- *
- * @see ixEthDBWiFiStationEntryAdd
- *
- * Note that adding the same MAC address twice will simply overwrite the previously
- * defined gateway MAC address value in the same record, if the record was previously of the
- * "Access Point to Access Point" type.
- *
- * Re-adding a MAC address as "Access Point to Access Point", which was previously added as
- * "Access Point to Station" will migrate the record type to "Access Point to Access Point" and
- * record the gateway MAC address.
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to add
- * @param gatewayMacAddr @ref IxEthDBMacAddr [in] - MAC address of the gateway Access Point
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG macAddr is an invalid pointer
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> or <i>gatewayMacAddr</i> pointer argument
- * @retval IX_ETH_DB_NOMEM maximum number of records reached
- * @retval IX_ETH_DB_BUSY lock condition or transaction in progress, try again later
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiAccessPointEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr, IxEthDBMacAddr *gatewayMacAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBWiFiEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Removes a WiFi station record
- *
- * This function removes both types of WiFi records ("Access Point to Station" and
- * "Access Point to Access Point").
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to remove
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer argument
- * @retval IX_ETH_DB_NO_SUCH_ADDR specified address was not found in the database
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled
- * @retval IX_ETH_DB_BUSY lock condition or transaction in progress, try again later
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBWiFiConversionTableDownload(IxEthDBPortId portID)
- *
- * @brief Downloads the MAC address table for 802.3 => 802.11 frame header
- * conversion to the NPE
- *
- * Note that the frame conversion MAC address table must be individually downloaded
- * to each NPE for which the frame header conversion feature is enabled (i.e. it
- * is not possible to specify IX_ETH_DB_ALL_PORTS).
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled
- * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiConversionTableDownload(IxEthDBPortId portID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBWiFiFrameControlSet(IxEthDBPortId portID, UINT16 frameControl)
- *
- * @brief Sets the GlobalFrameControl field
- *
- * The GlobalFrameControl field is a 2-byte value inserted in the <i>Frame Control</i>
- * field for all 802.3 to 802.11 frame header conversions
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param frameControl UINT16 [in] - GlobalFrameControl value
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled
- * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiFrameControlSet(IxEthDBPortId portID, UINT16 frameControl);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBWiFiDurationIDSet(IxEthDBPortId portID, UINT16 durationID)
- *
- * @brief Sets the GlobalDurationID field
- *
- * The GlobalDurationID field is a 2-byte value inserted in the <i>Duration/ID</i>
- * field for all 802.3 to 802.11 frame header conversions
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param durationID UINT16 [in] - GlobalDurationID field
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled
- * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiDurationIDSet(IxEthDBPortId portID, UINT16 durationID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBWiFiBBSIDSet(IxEthDBPortId portID, IxEthDBMacAddr *bbsid)
- *
- * @brief Sets the BBSID field
- *
- * The BBSID field is a 6-byte value which
- * identifies the infrastructure of the service set managed
- * by the Access Point having the IXP400 as its processor. The value
- * is written in the <i>BBSID</i> field of the 802.11 frame header.
- * The BBSID value is the MAC address of the Access Point.
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param bbsid @ref IxEthDBMacAddr [in] - pointer to 6 bytes containing the BSSID
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>bbsid</i> pointer argument
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled
- * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBWiFiBBSIDSet(IxEthDBPortId portID, IxEthDBMacAddr *bbsid);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBSpanningTreeBlockingStateSet(IxEthDBPortId portID, BOOL blocked)
- *
- * @brief Sets the STP blocked/unblocked state for a port
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param blocked BOOL [in] - TRUE to set the port as STP blocked, FALSE to set it as unblocked
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Spanning Tree Protocol feature not enabled
- * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBSpanningTreeBlockingStateSet(IxEthDBPortId portID, BOOL blocked);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBSpanningTreeBlockingStateGet(IxEthDBPortId portID, BOOL *blocked)
- *
- * @brief Retrieves the STP blocked/unblocked state for a port
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param blocked BOOL * [in] - set to TRUE if the port is STP blocked, FALSE otherwise
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>blocked</i> pointer argument
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Spanning Tree Protocol feature not enabled
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBSpanningTreeBlockingStateGet(IxEthDBPortId portID, BOOL *blocked);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFirewallModeSet(IxEthDBPortId portID, IxEthDBFirewallMode mode)
- *
- * @brief Sets the firewall mode to use white or black listing
- *
- * When enabled, the NPE MAC address based firewall support operates in two modes:
- *
- * - white-list mode (MAC address based admission)
- * - <i>mode</i> set to IX_ETH_DB_FIREWALL_WHITE_LIST
- * - only packets originating from MAC addresses contained in the firewall address list
- * are allowed on the Rx path
- * - black-list mode (MAC address based blocking)
- * - <i>mode</i> set to IX_ETH_DB_FIREWALL_BLACK_LIST
- * - packets originating from MAC addresses contained in the firewall address list
- * are discarded
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param mode @ref IxEthDBFirewallMode [in] - firewall mode (IX_ETH_DB_FIREWALL_WHITE_LIST or IX_ETH_DB_FIREWALL_BLACK_LIST)
- *
- * @note by default the firewall operates in black-list mode with an empty address
- * list, hence it doesn't filter any packets
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled
- * @retval IX_ETH_DB_INVALID_ARGUMENT <i>mode</i> argument is not a valid firewall configuration mode
- * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error
-*/
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFirewallModeSet(IxEthDBPortId portID, IxEthDBFirewallMode mode);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn ixEthDBFirewallInvalidAddressFilterEnable(IxEthDBPortId portID, BOOL enable)
- *
- * @brief Enables or disables invalid MAC address filtering
- *
- * According to IEEE802 it is illegal for a source address to be a multicast
- * or broadcast address. If this feature is enabled the NPE inspects the source
- * MAC addresses of incoming frames and discards them if invalid addresses are
- * detected.
- *
- * By default this service is enabled, if the firewall feature is supported by the
- * NPE image.
- *
- * @param portID ID of the port
- * @param enable TRUE to enable invalid MAC address filtering and FALSE to disable it
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled
- * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFirewallInvalidAddressFilterEnable(IxEthDBPortId portID, BOOL enable);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFirewallEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Adds a MAC address to the firewall address list
- *
- * Note that adding the same MAC address twice will not return an error
- * but will not actually accomplish anything.
- *
- * The firewall MAC address list has a limited number of entries; once
- * the maximum number of entries has been reached this function will failed
- * to add more addresses, returning IX_ETH_DB_NOMEM.
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to be added
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer argument
- * @retval IX_ETH_DB_NOMEM maximum number of records reached
- * @retval IX_ETH_DB_BUSY lock condition or transaction in progress, try again later
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFirewallEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFirewallEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
- *
- * @brief Removes a MAC address from the firewall address list
- *
- * @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to be removed
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer argument
- * @retval IX_ETH_DB_NO_SUCH_ADDR address not found
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFirewallEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBFirewallTableDownload(IxEthDBPortId portID)
- *
- * @brief Downloads the MAC firewall table to a port
- *
- * @param portID ID of the port
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
- * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized
- * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled
- * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFirewallTableDownload(IxEthDBPortId portID);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBUserFieldSet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void *field)
- *
- * @brief Adds a user-defined field to a database record
- *
- * This function associates a user-defined field to a database record.
- * The user-defined field is passed as a <i>(void *)</i> parameter, hence it can be used
- * for any purpose (such as identifying a structure). Retrieving the user-defined field from
- * a record is done using @ref ixEthDBUserFieldGet. Note that EthDB never uses the user-defined
- * field for any internal operation and it is not aware of the significance of its contents. The
- * field is only stored as a pointer.
- *
- * The database record is identified using a combination of the given parameters, depending on the record type.
- * All the record types require the record MAC address.
- *
- * - IX_ETH_DB_FILTERING_RECORD requires only the MAC address
- * - IX_ETH_DB_VLAN_FILTERING_RECORD requires the MAC address and the VLAN ID
- * - IX_ETH_DB_WIFI_RECORD requires the MAC address and the portID
- * - IX_ETH_DB_FIREWALL_RECORD requires the MAC address and the portID
- *
- * Please note that if a parameter is not required it is completely ignored (it does not undergo parameter checking).
- * The user-defined field can be cleared using a <b>NULL</b> <i>field</i> parameter.
- *
- * @param recordType @ref IxEthDBRecordType [in] - type of record (can be IX_ETH_DB_FILTERING_RECORD,
- * IX_ETH_DB_FILTERING_VLAN_RECORD, IX_ETH_DB_WIFI_RECORD or IX_ETH_DB_FIREWALL_RECORD)
- * @param portID @ref IxEthDBPortId [in] - ID of the port (required only for WIFI and FIREWALL records)
- * @param macAddr @ref IxEthDBMacAddr * [in] - MAC address of the record
- * @param vlanID @ref IxEthDBVlanId [in] - VLAN ID of the record (required only for FILTERING_VLAN records)
- * @param field void * [in] - user defined field
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID was required but it is not a valid port identifier
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> pointer argument
- * @retval IX_ETH_DB_NO_SUCH_ADDR record not found
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBUserFieldSet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void *field);
-
-/**
- * @ingroup IxEthDB
- *
- * @fn IxEthDBStatus ixEthDBUserFieldGet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void **field)
- *
- * @brief Retrieves a user-defined field from a database record
- *
- * The database record is identified using a combination of the given parameters, depending on the record type.
- * All the record types require the record MAC address.
- *
- * - IX_ETH_DB_FILTERING_RECORD requires only the MAC address
- * - IX_ETH_DB_VLAN_FILTERING_RECORD requires the MAC address and the VLAN ID
- * - IX_ETH_DB_WIFI_RECORD requires the MAC address and the portID
- * - IX_ETH_DB_FIREWALL_RECORD requires the MAC address and the portID
- *
- * Please note that if a parameter is not required it is completely ignored (it does not undergo parameter checking).
- *
- * If no user-defined field was registered with the specified record then <b>NULL</b> will be written
- * at the location specified by <i>field</i>.
- *
- * @param recordType type of record (can be IX_ETH_DB_FILTERING_RECORD, IX_ETH_DB_FILTERING_VLAN_RECORD, IX_ETH_DB_WIFI_RECORD
- * or IX_ETH_DB_FIREWALL_RECORD)
- * @param portID ID of the port (required only for WIFI and FIREWALL records)
- * @param macAddr MAC address of the record
- * @param vlanID VLAN ID of the record (required only for FILTERING_VLAN records)
- * @param field location to write the user defined field into
- *
- * @retval IX_ETH_DB_SUCCESS operation completed successfully
- * @retval IX_ETH_DB_INVALID_PORT portID was required but it is not a valid port identifier
- * @retval IX_ETH_DB_INVALID_ARG invalid <i>macAddr</i> or <i>field</i> pointer arguments
- * @retval IX_ETH_DB_NO_SUCH_ADDR record not found
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBUserFieldGet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portId, IxEthDBVlanId vlanID, void **field);
-
-/**
- * @}
- */
-
-#endif /* IxEthDB_H */
+++ /dev/null
-/**
- * @file IxEthAccDBLocks_p.h
- *
- * @brief Definition of transaction lock stacks and lock utility macros
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxEthAccDBLocks_p_H
-#define IxEthAccDBLocks_p_H
-
-#include "IxOsPrintf.h"
-
-/* Lock and lock stacks */
-typedef struct
-{
- IxOsalFastMutex* locks[MAX_LOCKS];
- UINT32 stackPointer, basePointer;
-} LockStack;
-
-#define TRY_LOCK(mutex) \
- { \
- if (ixOsalFastMutexTryLock(mutex) != IX_SUCCESS) \
- { \
- return IX_ETH_DB_BUSY; \
- } \
- }
-
-
-#define UNLOCK(mutex) { ixOsalFastMutexUnlock(mutex); }
-
-#define INIT_STACK(stack) \
- { \
- (stack)->basePointer = 0; \
- (stack)->stackPointer = 0; \
- }
-
-#define PUSH_LOCK(stack, lock) \
- { \
- if ((stack)->stackPointer == MAX_LOCKS) \
- { \
- ERROR_LOG("Ethernet DB: maximum number of elements in a lock stack has been exceeded on push, heavy chaining?\n"); \
- UNROLL_STACK(stack); \
- \
- return IX_ETH_DB_NOMEM; \
- } \
- \
- if (ixOsalFastMutexTryLock(lock) == IX_SUCCESS) \
- { \
- (stack)->locks[(stack)->stackPointer++] = (lock); \
- } \
- else \
- { \
- UNROLL_STACK(stack); \
- \
- return IX_ETH_DB_BUSY; \
- } \
- }
-
-#define POP_LOCK(stack) \
- { \
- ixOsalFastMutexUnlock((stack)->locks[--(stack)->stackPointer]); \
- }
-
-#define UNROLL_STACK(stack) \
- { \
- while ((stack)->stackPointer > (stack)->basePointer) \
- { \
- POP_LOCK(stack); \
- } \
- }
-
-#define SHIFT_STACK(stack) \
- { \
- if ((stack)->basePointer == MAX_LOCKS - 1) \
- { \
- ERROR_LOG("Ethernet DB: maximum number of elements in a lock stack has been exceeded on shift, heavy chaining?\n"); \
- UNROLL_STACK(stack); \
- \
- return IX_ETH_DB_BUSY; \
- } \
- \
- ixOsalFastMutexUnlock((stack)->locks[(stack)->basePointer++]); \
- }
-
-#endif /* IxEthAccDBLocks_p_H */
+++ /dev/null
-/**
- * @file IxEthDBLog_p.h
- *
- * @brief definitions of log macros and log configuration
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include <IxOsal.h>
-
-#ifdef IX_UNIT_TEST
-#define NULL_PRINT_ROUTINE(format, arg...) /* nothing */
-#else
-#define NULL_PRINT_ROUTINE if(0) printf
-#endif
-
-/***************************************************
- * Globals *
- ***************************************************/
-/* safe to permanently leave these on */
-#define HAS_ERROR_LOG
-#define HAS_ERROR_IRQ_LOG
-#define HAS_WARNING_LOG
-
-/***************************************************
- * Log Configuration *
- ***************************************************/
-
-/* debug output can be turned on unless specifically
- declared as a non-debug build */
-#ifndef NDEBUG
-
-#undef HAS_EVENTS_TRACE
-#undef HAS_EVENTS_VERBOSE_TRACE
-
-#undef HAS_SUPPORT_TRACE
-#undef HAS_SUPPORT_VERBOSE_TRACE
-
-#undef HAS_NPE_TRACE
-#undef HAS_NPE_VERBOSE_TRACE
-#undef HAS_DUMP_NPE_TREE
-
-#undef HAS_UPDATE_TRACE
-#undef HAS_UPDATE_VERBOSE_TRACE
-
-#endif /* NDEBUG */
-
-
-/***************************************************
- * Log Macros *
- ***************************************************/
-
-/************** Globals ******************/
-
-#ifdef HAS_ERROR_LOG
-
- #define ERROR_LOG printf
-
-#else
-
- #define ERROR_LOG NULL_PRINT_ROUTINE
-
-#endif
-
-#ifdef HAS_ERROR_IRQ_LOG
-
- #define ERROR_IRQ_LOG(format, arg1, arg2, arg3, arg4, arg5, arg6) ixOsalLog(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, format, arg1, arg2, arg3, arg4, arg5, arg6)
-
-#else
-
- #define ERROR_IRQ_LOG(format, arg1, arg2, arg3, arg4, arg5, arg6) /* nothing */
-
-#endif
-
-#ifdef HAS_WARNING_LOG
-
- #define WARNING_LOG printf
-
-#else
-
- #define WARNING_LOG NULL_PRINT_ROUTINE
-
-#endif
-
-/************** Events *******************/
-
-#ifdef HAS_EVENTS_TRACE
-
- #define IX_ETH_DB_EVENTS_TRACE printf
- #define IX_ETH_DB_IRQ_EVENTS_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, format, arg1, arg2, arg3, arg4, arg5, arg6)
-
- #ifdef HAS_EVENTS_VERBOSE_TRACE
-
- #define IX_ETH_DB_EVENTS_VERBOSE_TRACE printf
-
- #else
-
- #define IX_ETH_DB_EVENTS_VERBOSE_TRACE NULL_PRINT_ROUTINE
-
- #endif /* HAS_EVENTS_VERBOSE_TRACE */
-
-#else
-
- #define IX_ETH_DB_EVENTS_TRACE NULL_PRINT_ROUTINE
- #define IX_ETH_DB_EVENTS_VERBOSE_TRACE NULL_PRINT_ROUTINE
- #define IX_ETH_DB_IRQ_EVENTS_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) /* nothing */
-
-#endif /* HAS_EVENTS_TRACE */
-
-/************** Support *******************/
-
-#ifdef HAS_SUPPORT_TRACE
-
- #define IX_ETH_DB_SUPPORT_TRACE printf
- #define IX_ETH_DB_SUPPORT_IRQ_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, format, arg1, arg2, arg3, arg4, arg5, arg6)
-
- #ifdef HAS_SUPPORT_VERBOSE_TRACE
-
- #define IX_ETH_DB_SUPPORT_VERBOSE_TRACE printf
-
- #else
-
- #define IX_ETH_DB_SUPPORT_VERBOSE_TRACE NULL_PRINT_ROUTINE
-
- #endif /* HAS_SUPPORT_VERBOSE_TRACE */
-
-#else
-
- #define IX_ETH_DB_SUPPORT_TRACE NULL_PRINT_ROUTINE
- #define IX_ETH_DB_SUPPORT_VERBOSE_TRACE NULL_PRINT_ROUTINE
- #define IX_ETH_DB_SUPPORT_IRQ_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) /* nothing */
-
-#endif /* HAS_SUPPORT_TRACE */
-
-/************** NPE Adaptor *******************/
-
-#ifdef HAS_NPE_TRACE
-
- #define IX_ETH_DB_NPE_TRACE printf
- #define IX_ETH_DB_NPE_IRQ_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, format, arg1, arg2, arg3, arg4, arg5, arg6)
-
- #ifdef HAS_NPE_VERBOSE_TRACE
-
- #define IX_ETH_DB_NPE_VERBOSE_TRACE printf
-
- #else
-
- #define IX_ETH_DB_NPE_VERBOSE_TRACE NULL_PRINT_ROUTINE
-
- #endif /* HAS_NPE_VERBOSE_TRACE */
-
-#else
-
- #define IX_ETH_DB_NPE_TRACE NULL_PRINT_ROUTINE
- #define IX_ETH_DB_NPE_VERBOSE_TRACE NULL_PRINT_ROUTINE
- #define IX_ETH_DB_NPE_IRQ_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) /* nothing */
-
-#endif /* HAS_NPE_TRACE */
-
-#ifdef HAS_DUMP_NPE_TREE
-
-#define IX_ETH_DB_NPE_DUMP_ELT(eltBaseAddress, eltSize) ixEthELTDumpTree(eltBaseAddress, eltSize)
-
-#else
-
-#define IX_ETH_DB_NPE_DUMP_ELT(eltBaseAddress, eltSize) /* nothing */
-
-#endif /* HAS_DUMP_NPE_TREE */
-
-/************** Port Update *******************/
-
-#ifdef HAS_UPDATE_TRACE
-
- #define IX_ETH_DB_UPDATE_TRACE printf
-
- #ifdef HAS_UPDATE_VERBOSE_TRACE
-
- #define IX_ETH_DB_UPDATE_VERBOSE_TRACE printf
-
- #else
-
- #define IX_ETH_DB_UPDATE_VERBOSE_TRACE NULL_PRINT_ROUTINE
-
- #endif
-
-#else /* HAS_UPDATE_VERBOSE_TRACE */
-
- #define IX_ETH_DB_UPDATE_TRACE NULL_PRINT_ROUTINE
- #define IX_ETH_DB_UPDATE_VERBOSE_TRACE NULL_PRINT_ROUTINE
-
-#endif /* HAS_UPDATE_TRACE */
+++ /dev/null
-/**
- * @file IxEthDBMessages_p.h
- *
- * @brief Definitions of NPE messages
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxEthDBMessages_p_H
-#define IxEthDBMessages_p_H
-
-#include <IxEthNpe.h>
-#include <IxOsCacheMMU.h>
-#include "IxEthDB_p.h"
-
-/* events watched by the Eth event processor */
-#define IX_ETH_DB_MIN_EVENT_ID (IX_ETHNPE_EDB_GETMACADDRESSDATABASE)
-#define IX_ETH_DB_MAX_EVENT_ID (IX_ETHNPE_PC_SETAPMACTABLE)
-
-/* macros to fill and extract data from NPE messages - place any endian conversions here */
-#define RESET_ELT_MESSAGE(message) { memset((void *) &(message), 0, sizeof((message))); }
-#define NPE_MSG_ID(msg) ((msg).data[0] >> 24)
-
-#define FILL_SETPORTVLANTABLEENTRY_MSG(message, portID, setOffset, vlanMembershipSet, ttiSet) \
- do { \
- message.data[0] = (IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY << 24) | (portID << 16) | (setOffset * 2); \
- message.data[1] = (vlanMembershipSet << 8) | ttiSet; \
- } while (0);
-
-#define FILL_SETPORTVLANTABLERANGE_MSG(message, portID, offset, length, zone) \
- do { \
- message.data[0] = IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE << 24 | portID << 16 | offset << 9 | length << 1; \
- message.data[1] = (UINT32) zone; \
- } while (0);
-
-#define FILL_SETDEFAULTRXVID_MSG(message, portID, tpid, vlanTag) \
- do { \
- message.data[0] = (IX_ETHNPE_VLAN_SETDEFAULTRXVID << 24) \
- | (portID << 16); \
- \
- message.data[1] = (tpid << 16) | vlanTag; \
- } while (0);
-
-#define FILL_SETRXTAGMODE_MSG(message, portID, filterMode, tagMode) \
- do { \
- message.data[0] = IX_ETHNPE_VLAN_SETRXTAGMODE << 24 \
- | portID << 16 \
- | filterMode << 2 \
- | tagMode; \
- \
- message.data[1] = 0; \
- } while (0);
-
-#define FILL_SETRXQOSENTRY(message, portID, classIndex, trafficClass, aqmQueue) \
- do { \
- message.data[0] = IX_ETHNPE_VLAN_SETRXQOSENTRY << 24 \
- | portID << 16 \
- | classIndex; \
- \
- message.data[1] = trafficClass << 24 \
- | 0x1 << 23 \
- | aqmQueue << 16 \
- | aqmQueue << 4; \
- } while (0);
-
-#define FILL_SETPORTIDEXTRACTIONMODE(message, portID, enable) \
- do { \
- message.data[0] = IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE << 24 \
- | portID << 16 \
- | (enable ? 0x1 : 0x0); \
- \
- message.data[1] = 0; \
- } while (0);
-
-
-#define FILL_SETBLOCKINGSTATE_MSG(message, portID, blocked) \
- do { \
- message.data[0] = IX_ETHNPE_STP_SETBLOCKINGSTATE << 24 \
- | portID << 16 \
- | (blocked ? 0x1 : 0x0); \
- \
- message.data[1] = 0; \
- } while (0);
-
-#define FILL_SETBBSID_MSG(message, portID, bbsid) \
- do { \
- message.data[0] = IX_ETHNPE_PC_SETBBSID << 24 \
- | portID << 16 \
- | bbsid->macAddress[0] << 8 \
- | bbsid->macAddress[1]; \
- \
- message.data[1] = bbsid->macAddress[2] << 24 \
- | bbsid->macAddress[3] << 16 \
- | bbsid->macAddress[4] << 8 \
- | bbsid->macAddress[5]; \
- } while (0);
-
-#define FILL_SETFRAMECONTROLDURATIONID(message, portID, frameControlDurationID) \
- do { \
- message.data[0] = (IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID << 24) | (portID << 16); \
- message.data[1] = frameControlDurationID; \
- } while (0);
-
-#define FILL_SETAPMACTABLE_MSG(message, zone) \
- do { \
- message.data[0] = IX_ETHNPE_PC_SETAPMACTABLE << 24 \
- | 0 << 8 /* always use index 0 */ \
- | 64; /* 32 entries, 8 bytes each, 4 bytes in a word */ \
- message.data[1] = (UINT32) zone; \
- } while (0);
-
-#define FILL_SETFIREWALLMODE_MSG(message, portID, epDelta, mode, address) \
- do { \
- message.data[0] = IX_ETHNPE_FW_SETFIREWALLMODE << 24 \
- | portID << 16 \
- | (epDelta & 0xFF) << 8 \
- | mode; \
- \
- message.data[1] = (UINT32) address; \
- } while (0);
-
-#define FILL_SETMACADDRESSDATABASE_MSG(message, portID, epDelta, blockCount, address) \
- do { \
- message.data[0] = IX_ETHNPE_EDB_SETMACADDRESSSDATABASE << 24 \
- | (epDelta & 0xFF) << 8 \
- | (blockCount & 0xFF); \
- \
- message.data[1] = (UINT32) address; \
- } while (0);
-
-#define FILL_GETMACADDRESSDATABASE(message, npeId, zone) \
- do { \
- message.data[0] = IX_ETHNPE_EDB_GETMACADDRESSDATABASE << 24; \
- message.data[1] = (UINT32) zone; \
- } while (0);
-
-#define FILL_SETMAXFRAMELENGTHS_MSG(message, portID, maxRxFrameSize, maxTxFrameSize) \
- do { \
- message.data[0] = IX_ETHNPE_SETMAXFRAMELENGTHS << 24 \
- | portID << 16 \
- | ((maxRxFrameSize + 63) / 64) << 8 /* max Rx 64-byte blocks */ \
- | (maxTxFrameSize + 63) / 64; /* max Tx 64-byte blocks */ \
- \
- message.data[1] = maxRxFrameSize << 16 | maxTxFrameSize; \
- } while (0);
-
-#define FILL_SETPORTADDRESS_MSG(message, portID, macAddress) \
- do { \
- message.data[0] = IX_ETHNPE_EDB_SETPORTADDRESS << 24 \
- | portID << 16 \
- | macAddress[0] << 8 \
- | macAddress[1]; \
- \
- message.data[1] = macAddress[2] << 24 \
- | macAddress[3] << 16 \
- | macAddress[4] << 8 \
- | macAddress[5]; \
- } while (0);
-
-/* access to a MAC node in the NPE tree */
-#define NPE_NODE_BYTE(eltNodeAddr, offset) (((UINT8 *) (eltNodeAddr))[offset])
-
-/* browsing of the implicit linear binary tree structure of the NPE tree */
-#define LEFT_CHILD_OFFSET(offset) ((offset) << 1)
-#define RIGHT_CHILD_OFFSET(offset) (((offset) << 1) + 1)
-
-#define IX_EDB_FLAGS_ACTIVE (0x2)
-#define IX_EDB_FLAGS_VALID (0x1)
-#define IX_EDB_FLAGS_RESERVED (0xfc)
-#define IX_EDB_FLAGS_INACTIVE_VALID (0x1)
-
-#define IX_EDB_NPE_NODE_ELT_PORT_ID_OFFSET (6)
-#define IX_EDB_NPE_NODE_ELT_FLAGS_OFFSET (7)
-#define IX_EDB_NPE_NODE_WIFI_INDEX_OFFSET (6)
-#define IX_EDB_NPE_NODE_WIFI_FLAGS_OFFSET (7)
-#define IX_EDB_NPE_NODE_FW_FLAGS_OFFSET (1)
-#define IX_EDB_NPE_NODE_FW_RESERVED_OFFSET (6)
-#define IX_EDB_NPE_NODE_FW_ADDR_OFFSET (2)
-
-#define IX_EDB_NPE_NODE_VALID(address) ((NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_FLAGS_OFFSET) & IX_EDB_FLAGS_VALID) != 0)
-#define IX_EDB_NPE_NODE_ACTIVE(address) ((NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_FLAGS_OFFSET) & IX_EDB_FLAGS_ACTIVE) != 0)
-#define IX_EDB_NPE_NODE_PORT_ID(address) (NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_PORT_ID_OFFSET))
-
-/* macros to send messages to the NPEs */
-#define IX_ETHDB_ASYNC_SEND_NPE_MSG(npeId, msg, result) \
- do { \
- result = ixNpeMhMessageSend(npeId, msg, IX_NPEMH_SEND_RETRIES_DEFAULT); \
- \
- if (result != IX_SUCCESS) \
- { \
- ERROR_LOG("DB: Failed to send NPE message\n"); \
- } \
- } while (0);
-
-#define IX_ETHDB_SYNC_SEND_NPE_MSG(npeId, msg, result) \
- do { \
- result = ixNpeMhMessageWithResponseSend(npeId, msg, msg.data[0] >> 24, ixEthDBNpeMsgAck, IX_NPEMH_SEND_RETRIES_DEFAULT); \
- \
- if (result == IX_SUCCESS) \
- { \
- result = ixOsalMutexLock(&ixEthDBPortInfo[IX_ETH_DB_NPE_TO_PORT_ID(npeId)].npeAckLock, IX_ETH_DB_NPE_TIMEOUT); \
- \
- if (result != IX_SUCCESS) \
- { \
- ERROR_LOG("DB: NPE failed to respond within %dms\n", IX_ETH_DB_NPE_TIMEOUT); \
- } \
- } \
- else \
- { \
- ERROR_LOG("DB: Failed to send NPE message\n"); \
- } \
- } while (0);
-
-#ifndef IX_NDEBUG
-#define IX_ETH_DB_NPE_MSG_HISTORY_DEPTH (100)
-extern IX_ETH_DB_PUBLIC UINT32 npeMsgHistory[IX_ETH_DB_NPE_MSG_HISTORY_DEPTH][2];
-extern IX_ETH_DB_PUBLIC UINT32 npeMsgHistoryLen;
-#endif
-
-#define IX_ETHDB_SEND_NPE_MSG(npeId, msg, result) { LOG_NPE_MSG(msg); IX_ETHDB_SYNC_SEND_NPE_MSG(npeId, msg, result); }
-
-#endif /* IxEthDBMessages_p_H */
+++ /dev/null
-/**
- * @file IxEthDBPortDefs.h
- *
- * @brief Public definition of the ports and port capabilities
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxEthDBPortDefs IXP400 Ethernet Database Port Definitions (IxEthDBPortDefs)
- *
- * @brief IXP400 Public definition of the ports and port capabilities
- *
- * @{
- */
-
-#ifndef IxEthDBPortDefs_H
-#define IxEthDBPortDefs_H
-
-/**
- * @brief Port types - currently only Ethernet NPEs are recognized as specific types
- * All other (user-defined) ports must be specified as IX_ETH_GENERIC
- */
-typedef enum
-{
- IX_ETH_GENERIC = 0, /**< generic ethernet port */
- IX_ETH_NPE /**< specific Ethernet NPE */
-} IxEthDBPortType;
-
-/**
- * @brief Port capabilities - used by ixEthAccDatabaseMaintenance to decide whether it
- * should manually age entries or not depending on the port capabilities.
- *
- * Ethernet NPEs have aging capabilities, meaning that they will age the entries
- * automatically (by themselves).*/
-typedef enum
-{
- IX_ETH_NO_CAPABILITIES = 0, /**< no aging capabilities */
- IX_ETH_ENTRY_AGING = 0x1 /**< aging capabilities present */
-} IxEthDBPortCapability;
-
-/**
- * @brief Port Definition - a structure contains the Port type and capabilities
- */
-typedef struct
-{
- IxEthDBPortType type;
- IxEthDBPortCapability capabilities;
-} IxEthDBPortDefinition;
-
-/**
- * @brief Port definitions structure, indexed on the port ID
- * @warning Ports 0 and 1 are used by the Ethernet access component therefore
- * it is essential to be left untouched. Port 2 here (WAN) is given as
- * an example port. The NPE firmware also assumes the NPE B to be
- * the port 0 and NPE C to be the port 1.
- *
- * @note that only 32 ports (0..31) are supported by EthDB
- */
-static const IxEthDBPortDefinition ixEthDBPortDefinitions[] =
-{
- /* id type capabilities */
- { /* 0 */ IX_ETH_NPE, IX_ETH_NO_CAPABILITIES }, /* Ethernet NPE B */
- { /* 1 */ IX_ETH_NPE, IX_ETH_NO_CAPABILITIES }, /* Ethernet NPE C */
- { /* 2 */ IX_ETH_NPE, IX_ETH_NO_CAPABILITIES }, /* Ethernet NPE A */
- { /* 3 */ IX_ETH_GENERIC, IX_ETH_NO_CAPABILITIES }, /* WAN port */
-};
-
-/**
- * @def IX_ETH_DB_NUMBER_OF_PORTS
- * @brief number of supported ports
- */
-#define IX_ETH_DB_NUMBER_OF_PORTS (sizeof (ixEthDBPortDefinitions) / sizeof (ixEthDBPortDefinitions[0]))
-
-/**
- * @def IX_ETH_DB_UNKNOWN_PORT
- * @brief definition of an unknown port
- */
-#define IX_ETH_DB_UNKNOWN_PORT (0xff)
-
-/**
- * @def IX_ETH_DB_ALL_PORTS
- * @brief Special port ID indicating all the ports
- * @note This port ID can be used only by a subset of the EthDB API; each
- * function specifically mentions whether this is a valid parameter as the port ID
- */
-#define IX_ETH_DB_ALL_PORTS (IX_ETH_DB_NUMBER_OF_PORTS + 1)
-
-/**
- * @def IX_ETH_DB_PORTS_ASSERTION
- * @brief catch invalid port definitions (<2) with a
- * compile-time assertion resulting in a duplicate case error.
- */
-#define IX_ETH_DB_PORTS_ASSERTION { switch(0) { case 0 : ; case 1 : ; case IX_ETH_DB_NUMBER_OF_PORTS : ; }}
-
-/**
- * @def IX_ETH_DB_CHECK_PORT(portID)
- * @brief safety checks to verify whether the port is invalid or uninitialized
- */
-#define IX_ETH_DB_CHECK_PORT(portID) \
-{ \
- if ((portID) >= IX_ETH_DB_NUMBER_OF_PORTS) \
- { \
- return IX_ETH_DB_INVALID_PORT; \
- } \
- \
- if (!ixEthDBPortInfo[(portID)].enabled) \
- { \
- return IX_ETH_DB_PORT_UNINITIALIZED; \
- } \
-}
-
-/**
- * @def IX_ETH_DB_CHECK_PORT_ALL(portID)
- * @brief safety checks to verify whether the port is invalid or uninitialized;
- * tolerates the use of IX_ETH_DB_ALL_PORTS
- */
-#define IX_ETH_DB_CHECK_PORT_ALL(portID) \
-{ \
- if ((portID) != IX_ETH_DB_ALL_PORTS) \
- IX_ETH_DB_CHECK_PORT(portID) \
-}
-
-#endif /* IxEthDBPortDefs_H */
-/**
- *@}
- */
+++ /dev/null
-/**
- * @file IxEthDBQoS.h
- *
- * @brief Public definitions for QoS traffic classes
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxEthDBPortDefs IXP400 Ethernet QoS definitions
- *
- * @brief IXP00 Public definitions for QoS traffic classes
- *
- * @{
- */
-
-#ifndef IxEthDBQoS_H
-#define IxEthDBQoS_H
-
-/**
- * @def IX_ETH_DB_QUEUE_UNAVAILABLE
- * @brief alias to indicate a queue (traffic class) is not available
- */
-#define IX_ETH_DB_QUEUE_UNAVAILABLE (0)
-
-#ifndef IX_IEEE802_1Q_QOS_PRIORITY_COUNT
-/**
- * @def IX_IEEE802_1Q_QOS_PRIORITY_COUNT
- * @brief number of QoS priorities, according to IEEE 802.1Q
- */
-#define IX_IEEE802_1Q_QOS_PRIORITY_COUNT (8)
-#endif
-
-/**
- * @brief array containing all the supported traffic class configurations
- */
-static const
-UINT8 ixEthDBQueueAssignments[][IX_IEEE802_1Q_QOS_PRIORITY_COUNT] =
-{
- { 4, 5, 6, 7, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE },
- { 15, 16, 17, 18, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE },
- { 11, 23, 26, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE },
- { 4, 5, 6, 7, 8, 9, 10, 11 }
- /* add here all other cases of queue configuration structures and update ixEthDBTrafficClassDefinitions to use them */
-};
-
-/**
- * @brief value used to index the NPE A functionality ID in the traffic class definition table
- */
-#define IX_ETH_DB_NPE_A_FUNCTIONALITY_ID_INDEX (0)
-
-/**
- * @brief value used to index the traffic class count in the traffic class definition table
- */
-#define IX_ETH_DB_TRAFFIC_CLASS_COUNT_INDEX (1)
-
-/**
- * @brief value used to index the queue assignment index in the traffic class definition table
- */
-#define IX_ETH_DB_QUEUE_ASSIGNMENT_INDEX (2)
-
-/**
- * @brief traffic class definitions
- *
- * This array contains the default traffic class definition configuration,
- * as well as any special cases dictated by the functionality ID of NPE A.
- *
- * The default case should not be removed (otherwise the Ethernet
- * components will assert a fatal failure on initialization).
- */
-static const
-UINT8 ixEthDBTrafficClassDefinitions[][3] =
-{
- /* NPE A functionality ID | traffic class count | queue assignment index (points to the queue enumeration in ixEthDBQueueAssignments) */
- { 0x00, 4, 0 }, /* default case - DO NOT REMOVE */
- { 0x04, 4, 1 }, /* NPE A image ID 0.4.0.0 */
- { 0x09, 3, 2 }, /* NPE A image ID 0.9.0.0 */
- { 0x80, 8, 3 }, /* NPE A image ID 10.80.02.0 */
- { 0x81, 8, 3 }, /* NPE A image ID 10.81.02.0 */
- { 0x82, 8, 3 } /* NPE A image ID 10.82.02.0 */
-};
-
-/**
- * @brief IEEE 802.1Q recommended QoS Priority => traffic class maps
- *
- * @verbatim
- Number of available traffic classes
- 1 2 3 4 5 6 7 8
- QoS Priority
- 0 0 0 0 1 1 1 1 2
- 1 0 0 0 0 0 0 0 0
- 2 0 0 0 0 0 0 0 1
- 3 0 0 0 1 1 2 2 3
- 4 0 1 1 2 2 3 3 4
- 5 0 1 1 2 3 4 4 5
- 6 0 1 2 3 4 5 5 6
- 7 0 1 2 3 4 5 6 7
-
- @endverbatim
- */
-static const
-UINT8 ixEthIEEE802_1QUserPriorityToTrafficClassMapping[IX_IEEE802_1Q_QOS_PRIORITY_COUNT][IX_IEEE802_1Q_QOS_PRIORITY_COUNT] =
- {
- { 0, 0, 0, 0, 0, 0, 0, 0 }, /* 1 traffic class available */
- { 0, 0, 0, 0, 1, 1, 1, 1 }, /* 2 traffic classes available */
- { 0, 0, 0, 0, 1, 1, 2, 2 }, /* 3 traffic classes available */
- { 1, 0, 0, 1, 2, 2, 3, 3 }, /* 4 traffic classes available */
- { 1, 0, 0, 1, 2, 3, 4, 4 }, /* 5 traffic classes available */
- { 1, 0, 0, 2, 3, 4, 5, 5 }, /* 6 traffic classes available */
- { 1, 0, 0, 2, 3, 4, 5, 6 }, /* 7 traffic classes available */
- { 2, 0, 1, 3, 4, 5, 6, 7 } /* 8 traffic classes available */
- };
-
-#endif /* IxEthDBQoS_H */
-
-/**
- *@}
- */
+++ /dev/null
-/**
- * @file IxEthDB_p.h
- *
- * @brief Private MAC learning API
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxEthDB_p_H
-#define IxEthDB_p_H
-
-#include <IxTypes.h>
-#include <IxOsal.h>
-#include <IxEthDB.h>
-#include <IxNpeMh.h>
-#include <IxEthDBPortDefs.h>
-
-#include "IxEthDBMessages_p.h"
-#include "IxEthDBLog_p.h"
-
-#if (CPU==SIMSPARCSOLARIS)
-
-/* when running unit tests intLock() won't protect the event queue so we lock it manually */
-#define TEST_FIXTURE_LOCK_EVENT_QUEUE { ixOsalMutexLock(&eventQueueLock, IX_OSAL_WAIT_FOREVER); }
-#define TEST_FIXTURE_UNLOCK_EVENT_QUEUE { ixOsalMutexUnlock(&eventQueueLock); }
-
-#else
-
-#define TEST_FIXTURE_LOCK_EVENT_QUEUE /* nothing */
-#define TEST_FIXTURE_UNLOCK_EVENT_QUEUE /* nothing */
-
-#endif /* #if(CPU==SIMSPARCSOLARIS) */
-
-#ifndef IX_UNIT_TEST
-
-#define TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER /* nothing */
-#define TEST_FIXTURE_MARK_OVERFLOW_EVENT /* nothing */
-
-#else
-
-extern int dbAccessCounter;
-extern int overflowEvent;
-
-#define TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER { dbAccessCounter++; }
-#define TEST_FIXTURE_MARK_OVERFLOW_EVENT { overflowEvent = 1; }
-
-#endif
-
-/* code readability markers */
-#define __mempool__ /* memory pool marker */
-#define __lock__ /* hash write locking marker */
-#define __smartpointer__ /* smart pointer marker - warning: use only clone() when duplicating! */
-#define __alignment__ /* marker for data used only as alignment zones */
-
-/* constants */
-#define IX_ETH_DB_NPE_TIMEOUT (100) /* NPE response timeout, in ms */
-
-/**
- * number of hash table buckets
- * it should be at least 8x the predicted number of entries for performance
- * each bucket needs 8 bytes
- */
-#define NUM_BUCKETS (8192)
-
-/**
- * number of hash table buckets to preload when incrementing bucket iterator
- * = two cache lines
- */
-#define IX_ETHDB_CACHE_LINE_AHEAD (2)
-
-#define IX_ETHDB_BUCKETPTR_AHEAD ((IX_ETHDB_CACHE_LINE_AHEAD * IX_OSAL_CACHE_LINE_SIZE)/sizeof(void *))
-
-#define IX_ETHDB_BUCKET_INDEX_MASK (((IX_OSAL_CACHE_LINE_SIZE)/sizeof(void *)) - 1)
-
-/* locks */
-#define MAX_LOCKS (20) /**< maximum number of locks used simultaneously, do not tamper with */
-
-/* learning tree constants */
-#define INITIAL_ELT_SIZE (8) /**< initial byte size of tree (empty unused root size) */
-#define MAX_ELT_SIZE (512) /**< maximum number of entries (includes unused root) */
-#define MAX_GW_SIZE (32) /**< maximum number of gateway entries (including unused root) */
-#define MAX_FW_SIZE (32) /**< maximum number of firewall entries (including unused root) */
-#define ELT_ENTRY_SIZE (8) /**< entry size, in bytes */
-#define ELT_ROOT_OFFSET (ELT_ENTRY_SIZE) /**< tree root offset, in bytes - node preceeding root is unused */
-#define FULL_ELT_BYTE_SIZE (MAX_ELT_SIZE * ELT_ENTRY_SIZE) /**< full size of tree, in bytes, including unused root */
-#define FULL_GW_BYTE_SIZE (MAX_GW_SIZE * ELT_ENTRY_SIZE) /**< full size of gateway list, in bytes, including unused root */
-#define FULL_FW_BYTE_SIZE (MAX_FW_SIZE * ELT_ENTRY_SIZE) /**< full size of firewall table, in bytes, including unused root */
-
-/* maximum size of the VLAN table:
- * 4096 bits (one per VLAN)
- * 8 bits in one byte
- * interleaved VLAN membership and VLAN TTI (*2) */
-#define FULL_VLAN_BYTE_SIZE (4096 / 8 * 2)
-
-/* upper 9 bits used as set index, lower 3 bits as byte index */
-#define VLAN_SET_OFFSET(vlanID) ((vlanID) >> 3)
-#define VLAN_SET_MASK(vlanID) (0x7 - ((vlanID) & 0x7))
-
-/* Update zone definitions */
-#define NPE_TREE_MEM_SIZE (4096) /* ((511 entries + 1 unused root) * 8 bytes/entry) */
-
-/* check the above value, we rely on 4k */
-#if NPE_TREE_MEM_SIZE != 4096
- #error NPE_TREE_MEM_SIZE is not defined to 4096 bytes!
-#endif
-
-/* Size Filtering limits (Jumbo frame filtering) */
-#define IX_ETHDB_MAX_FRAME_SIZE 65535 /* other ports than NPE ports */
-#define IX_ETHDB_MIN_FRAME_SIZE 1 /* other ports than NPE ports */
-#define IX_ETHDB_MAX_NPE_FRAME_SIZE 16320 /* NPE ports firmware limit */
-#define IX_ETHDB_MIN_NPE_FRAME_SIZE 1 /* NPE ports firmware limit */
-#define IX_ETHDB_DEFAULT_FRAME_SIZE 1522
-
-/* memory management pool sizes */
-
-/*
- * Note:
- *
- * NODE_POOL_SIZE controls the maximum number of elements in the database at any one time.
- * It should be large enough to cover all the search trees of all the ports simultaneously.
- *
- * MAC_POOL_SIZE should be higher than NODE_POOL_SIZE by at least the total number of MAC addresses
- * possible to be held at any time in all the ports.
- *
- * TREE_POOL_SIZE should follow the same guideline as for MAC_POOL_SIZE.
- *
- * The database structure described here (2000/4000/4000) is enough for two NPEs holding at most 511
- * entries each plus one PCI NIC holding at most 900 entries.
- */
-
-#define NODE_POOL_SIZE (2000) /**< number of HashNode objects - also master number of elements in the database; each entry has 16 bytes */
-#define MAC_POOL_SIZE (4000) /**< number of MacDescriptor objects; each entry has 28 bytes */
-#define TREE_POOL_SIZE (4000) /**< number of MacTreeNode objects; each entry has 16 bytes */
-
-/* retry policies */
-#define BUSY_RETRY_ENABLED (TRUE) /**< if set to TRUE the API will retry automatically calls returning BUSY */
-#define FOREVER_RETRY (TRUE) /**< if set to TRUE the API will retry forever BUSY calls */
-#define MAX_RETRIES (400) /**< upper retry limit - used only when FOREVER_RETRY is FALSE */
-#define BUSY_RETRY_YIELD (5) /**< ticks to yield for every failed retry */
-
-/* event management */
-#define EVENT_QUEUE_SIZE (500) /**< size of the sink collecting events from the Message Handler FIFO */
-#define EVENT_PROCESSING_LIMIT (100) /**< batch processing control size (how many events are extracted from the queue at once) */
-
-/* MAC descriptors */
-#define STATIC_ENTRY (TRUE)
-#define DYNAMIC_ENTRY (FALSE)
-
-/* age reset on next maintenance - incrementing by 1 will reset to 0 */
-#define AGE_RESET (0xFFFFFFFF)
-
-/* dependency maps */
-#define EMPTY_DEPENDENCY_MAP (0)
-
-/* trees */
-#define RIGHT (1)
-#define LEFT (-1)
-
-/* macros */
-#define IX_ETH_DB_CHECK_PORT_EXISTS(portID) \
-{ \
- if ((portID) >= IX_ETH_DB_NUMBER_OF_PORTS) \
- { \
- return IX_ETH_DB_INVALID_PORT; \
- } \
-}
-
-#define IX_ETH_DB_CHECK_PORT_INITIALIZED(portID) \
-{ \
- if ((portID) >= IX_ETH_DB_NUMBER_OF_PORTS) \
- { \
- return IX_ETH_DB_INVALID_PORT; \
- } \
- else \
- { \
- if (!ixEthDBPortInfo[portID].initialized) \
- { \
- return IX_ETH_DB_PORT_UNINITIALIZED; \
- } \
- } \
-}
-
-/* single NPE check */
-#define IX_ETH_DB_CHECK_SINGLE_NPE(portID) \
- if (ixEthDBSingleEthNpeCheck(portID) != IX_ETH_DB_SUCCESS) \
- { \
- WARNING_LOG("EthDB: port ID %d is unavailable\n",(UINT32) portID); \
- \
- return IX_ETH_DB_INVALID_PORT; \
- }
-
-/* feature check */
-#define IX_ETH_DB_CHECK_FEATURE(portID, feature) \
- if ((ixEthDBPortInfo[portID].featureStatus & feature) == 0) \
- { \
- return IX_ETH_DB_FEATURE_UNAVAILABLE; \
- }
-
-/* busy retrying */
-#define BUSY_RETRY(functionCall) \
- { \
- UINT32 retries = 0; \
- IxEthDBStatus br_result; \
- \
- while ((br_result = functionCall) == IX_ETH_DB_BUSY \
- && BUSY_RETRY_ENABLED && (FOREVER_RETRY || ++retries < MAX_RETRIES)) { ixOsalSleep(BUSY_RETRY_YIELD); }; \
- \
- if ((!FOREVER_RETRY && retries == MAX_RETRIES) || (br_result == IX_ETH_DB_FAIL)) \
- {\
- ERROR_LOG("Ethernet Learning Database Error: BUSY_RETRY failed at %s:%d\n", __FILE__, __LINE__); \
- }\
- }
-
-#define BUSY_RETRY_WITH_RESULT(functionCall, brwr_result) \
- { \
- UINT32 retries = 0; \
- \
- while ((brwr_result = functionCall) == IX_ETH_DB_BUSY \
- && BUSY_RETRY_ENABLED && (FOREVER_RETRY || ++retries < MAX_RETRIES)) { ixOsalSleep(BUSY_RETRY_YIELD); }; \
- \
- if ((!FOREVER_RETRY && retries == MAX_RETRIES) || (brwr_result == IX_ETH_DB_FAIL)) \
- {\
- ERROR_LOG("Ethernet Learning Database Error: BUSY_RETRY_WITH_RESULT failed at %s:%d\n", __FILE__, __LINE__); \
- }\
- }
-
-/* iterators */
-#define IS_ITERATOR_VALID(iteratorPtr) ((iteratorPtr)->node != NULL)
-
-/* dependency port maps */
-
-/* Warning: if port indexing starts from 1 replace (portID) with (portID - 1) in DEPENDENCY_MAP (and make sure IX_ETH_DB_NUMBER_OF_PORTS is big enough) */
-
-/* gives an empty dependency map */
-#define SET_EMPTY_DEPENDENCY_MAP(map) { int i = 0; for (; i < 32 ; i++) map[i] = 0; }
-
-#define IS_EMPTY_DEPENDENCY_MAP(result, map) { int i = 0 ; result = TRUE; for (; i < 32 ; i++) if (map[i] != 0) { result = FALSE; break; }}
-
-/**
- * gives a map consisting only of 'portID'
- */
-#define SET_DEPENDENCY_MAP(map, portID) {SET_EMPTY_DEPENDENCY_MAP(map); map[portID >> 3] = 1 << (portID & 0x7);}
-
-/**
- * gives a map resulting from joining map1 and map2
- */
-#define JOIN_MAPS(map, map1, map2) { int i = 0; for (; i < 32 ; i++) map[i] = map1[i] | map2[i]; }
-
-/**
- * gives the map resulting from joining portID and map
- */
-#define JOIN_PORT_TO_MAP(map, portID) { map[portID >> 3] |= 1 << (portID & 0x7); }
-
-/**
- * gives the map resulting from excluding portID from map
- */
-#define EXCLUDE_PORT_FROM_MAP(map, portID) { map[portID >> 3] &= ~(1 << (portID & 0x7); }
-
-/**
- * returns TRUE if map1 is a subset of map2 and FALSE otherwise
- */
-#define IS_MAP_SUBSET(result, map1, map2) { int i = 0; result = TRUE; for (; i < 32 ; i++) if ((map1[i] | map2[i]) != map2[i]) result = FALSE; }
-
-/**
- * returns TRUE is portID is part of map and FALSE otherwise
- */
-#define IS_PORT_INCLUDED(portID, map) ((map[portID >> 3] & (1 << (portID & 0x7))) != 0)
-
-/**
- * returns the difference between map1 and map2 (ports included in map1 and not included in map2)
- */
-#define DIFF_MAPS(map, map1, map2) { int i = 0; for (; i < 32 ; i++) map[i] = map1[i] ^ (map1[i] & map2[i]); }
-
-/**
- * returns TRUE if the maps collide (have at least one port in common) and FALSE otherwise
- */
-#define MAPS_COLLIDE(result, map1, map2) { int i = 0; result = FALSE; for (; i < 32 ; i++) if ((map1[i] & map2[i]) != 0) result = TRUE; }
-
-/* size (number of ports) of a dependency map */
-#define GET_MAP_SIZE(map, size) { int i = 0, b = 0; size = 0; for (; i < 32 ; i++) { char y = map[i]; for (; b < 8 && (y >>= 1); b++) size += (y & 1); }}
-
-/* copy map2 into map1 */
-#define COPY_DEPENDENCY_MAP(map1, map2) { memcpy (map1, map2, sizeof (map1)); }
-
-/* definition of a port map size/port number which cannot be reached (we support at most 32 ports) */
-#define MAX_PORT_SIZE (0xFF)
-#define MAX_PORT_NUMBER (0xFF)
-
-#define IX_ETH_DB_CHECK_REFERENCE(ptr) { if ((ptr) == NULL) { return IX_ETH_DB_INVALID_ARG; } }
-#define IX_ETH_DB_CHECK_MAP(portID, map) { if (!IS_PORT_INCLUDED(portID, map)) { return IX_ETH_DB_INVALID_ARG; } }
-
-/* event queue macros */
-#define EVENT_QUEUE_WRAP(offset) ((offset) >= EVENT_QUEUE_SIZE ? (offset) - EVENT_QUEUE_SIZE : (offset))
-
-#define CAN_ENQUEUE(eventQueuePtr) ((eventQueuePtr)->length < EVENT_QUEUE_SIZE)
-
-#define QUEUE_HEAD(eventQueuePtr) (&(eventQueuePtr)->queue[EVENT_QUEUE_WRAP((eventQueuePtr)->base + (eventQueuePtr)->length)])
-
-#define QUEUE_TAIL(eventQueuePtr) (&(eventQueuePtr)->queue[(eventQueuePtr)->base])
-
-#define PUSH_UPDATE_QUEUE(eventQueuePtr) { (eventQueuePtr)->length++; }
-
-#define SHIFT_UPDATE_QUEUE(eventQueuePtr) \
- { \
- (eventQueuePtr)->base = EVENT_QUEUE_WRAP((eventQueuePtr)->base + 1); \
- (eventQueuePtr)->length--; \
- }
-
-#define RESET_QUEUE(eventQueuePtr) \
- { \
- (eventQueuePtr)->base = 0; \
- (eventQueuePtr)->length = 0; \
- }
-
-/* node stack macros - used to browse a tree without using a recursive function */
-#define NODE_STACK_INIT(stack) { (stack)->nodeCount = 0; }
-#define NODE_STACK_PUSH(stack, node, offset) { (stack)->nodes[(stack)->nodeCount] = (node); (stack)->offsets[(stack)->nodeCount++] = (offset); }
-#define NODE_STACK_POP(stack, node, offset) { (node) = (stack)->nodes[--(stack)->nodeCount]; offset = (stack)->offsets[(stack)->nodeCount]; }
-#define NODE_STACK_NONEMPTY(stack) ((stack)->nodeCount != 0)
-
-#ifndef IX_NDEBUG
-#define IX_ETH_DB_NPE_MSG_HISTORY_DEPTH (100)
-#define LOG_NPE_MSG(msg) \
- do { \
- UINT32 npeMsgHistoryIndex = (npeMsgHistoryLen++) % IX_ETH_DB_NPE_MSG_HISTORY_DEPTH; \
- npeMsgHistory[npeMsgHistoryIndex][0] = msg.data[0]; \
- npeMsgHistory[npeMsgHistoryIndex][1] = msg.data[1]; \
- } while (0);
-#else
-#define LOG_NPE_MSG() /* nothing */
-#endif
-
-/* ----------- Data -------------- */
-
-/* typedefs */
-
-typedef UINT32 (*HashFunction)(void *entity);
-typedef BOOL (*MatchFunction)(void *reference, void *entry);
-typedef void (*FreeFunction)(void *entry);
-
-/**
- * basic component of a hash table
- */
-typedef struct HashNode_t
-{
- void *data; /**< specific data */
- struct HashNode_t *next; /**< used for bucket chaining */
-
- __mempool__ struct HashNode_t *nextFree; /**< memory pool management */
-
- __lock__ IxOsalFastMutex lock; /**< node lock */
-} HashNode;
-
-/**
- * @brief hash table iterator definition
- *
- * an iterator is an object which can be used
- * to browse a hash table
- */
-typedef struct
-{
- UINT32 bucketIndex; /**< index of the currently iterated bucket */
- HashNode *previousNode; /**< reference to the previously iterated node within the current bucket */
- HashNode *node; /**< reference to the currently iterated node */
-} HashIterator;
-
-/**
- * definition of a MAC descriptor (a database record)
- */
-
-typedef enum
-{
- IX_ETH_DB_WIFI_AP_TO_STA = 0x0,
- IX_ETH_DB_WIFI_AP_TO_AP = 0x1
-} IxEthDBWiFiRecordType;
-
-typedef union
-{
- struct
- {
- UINT32 age;
- BOOL staticEntry; /**< TRUE if this address is static (doesn't age) */
- } filteringData;
-
- struct
- {
- UINT32 age;
- BOOL staticEntry;
- UINT32 ieee802_1qTag;
- } filteringVlanData;
-
- struct
- {
- IxEthDBWiFiRecordType type; /**< AP_TO_AP (0x1) or AP_TO_STA (0x0) */
- UINT32 gwAddressIndex; /**< used only when linearizing the entries for NPE usage */
- UINT8 gwMacAddress[IX_IEEE803_MAC_ADDRESS_SIZE];
-
- __alignment__ UINT8 reserved2[2];
- } wifiData;
-} IxEthDBRecordData;
-
-typedef struct MacDescriptor_t
-{
- UINT8 macAddress[IX_IEEE803_MAC_ADDRESS_SIZE];
-
- __alignment__ UINT8 reserved1[2];
-
- UINT32 portID;
- IxEthDBRecordType type;
- IxEthDBRecordData recordData;
-
- /* used for internal operations, such as NPE linearization */
- void *internal;
-
- /* custom user data */
- void *user;
-
- __mempool__ struct MacDescriptor_t *nextFree; /**< memory pool management */
- __smartpointer__ UINT32 refCount; /**< smart pointer reference counter */
-} MacDescriptor;
-
-/**
- * hash table definition
- */
-typedef struct
-{
- HashNode *hashBuckets[NUM_BUCKETS];
- UINT32 numBuckets;
-
- __lock__ IxOsalFastMutex bucketLocks[NUM_BUCKETS];
-
- HashFunction entryHashFunction;
- MatchFunction *matchFunctions;
- FreeFunction freeFunction;
-} HashTable;
-
-typedef enum
-{
- IX_ETH_DB_MAC_KEY = 1,
- IX_ETH_DB_MAC_PORT_KEY = 2,
- IX_ETH_DB_MAC_VLAN_KEY = 3,
- IX_ETH_DB_MAX_KEY_INDEX = 3
-} IxEthDBSearchKeyType;
-
-typedef struct MacTreeNode_t
-{
- __smartpointer__ MacDescriptor *descriptor;
- struct MacTreeNode_t *left, *right;
-
- __mempool__ struct MacTreeNode_t *nextFree;
-} MacTreeNode;
-
-typedef IxEthDBStatus (*IxEthDBPortUpdateHandler)(IxEthDBPortId portID, IxEthDBRecordType type);
-
-typedef void (*IxEthDBNoteWriteFn)(void *address, MacTreeNode *node);
-
-typedef struct
-{
- BOOL updateEnabled; /**< TRUE if updates are enabled for port */
- BOOL userControlled; /**< TRUE if the user has manually used ixEthDBPortUpdateEnableSet */
- BOOL treeInitialized; /**< TRUE if the NPE has received an initial tree */
- IxEthDBPortUpdateHandler updateHandler; /**< port update handler routine */
- void *npeUpdateZone; /**< port update memory zone */
- void *npeGwUpdateZone; /**< port update memory zone for gateways */
- void *vlanUpdateZone; /**< port update memory zone for VLAN tables */
- MacTreeNode *searchTree; /**< internal search tree, in MacTreeNode representation */
- BOOL searchTreePendingWrite; /**< TRUE if searchTree holds a tree pending write to the port */
-} PortUpdateMethod;
-
-typedef struct
-{
- IxEthDBPortId portID; /**< port ID */
- BOOL enabled; /**< TRUE if the port is enabled */
- BOOL agingEnabled; /**< TRUE if aging on this port is enabled */
- BOOL initialized;
- IxEthDBPortMap dependencyPortMap; /**< dependency port map for this port */
- PortUpdateMethod updateMethod; /**< update method structure */
- BOOL macAddressUploaded; /**< TRUE if the MAC address was uploaded into the port */
- UINT32 maxRxFrameSize; /**< maximum Rx frame size for this port */
- UINT32 maxTxFrameSize; /**< maximum Rx frame size for this port */
-
- UINT8 bbsid[6];
- __alignment__ UINT8 reserved[2];
- UINT32 frameControlDurationID; /**< Frame Control - Duration/ID WiFi control */
-
- IxEthDBVlanTag vlanTag; /**< default VLAN tag for port */
- IxEthDBPriorityTable priorityTable; /**< QoS <=> internal priority mapping */
- IxEthDBVlanSet vlanMembership;
- IxEthDBVlanSet transmitTaggingInfo;
- IxEthDBFrameFilter frameFilter;
- IxEthDBTaggingAction taggingAction;
-
- UINT32 npeFrameFilter;
- UINT32 npeTaggingAction;
-
- IxEthDBFirewallMode firewallMode;
- BOOL srcAddressFilterEnabled;
-
- BOOL stpBlocked;
-
- IxEthDBFeature featureCapability;
- IxEthDBFeature featureStatus;
-
- UINT32 ixEthDBTrafficClassAQMAssignments[IX_IEEE802_1Q_QOS_PRIORITY_COUNT];
-
- UINT32 ixEthDBTrafficClassCount;
-
- UINT32 ixEthDBTrafficClassAvailable;
-
-
-
- __lock__ IxOsalMutex npeAckLock;
-} PortInfo;
-
-/* list of port information structures indexed on port Ids */
-extern IX_ETH_DB_PUBLIC PortInfo ixEthDBPortInfo[IX_ETH_DB_NUMBER_OF_PORTS];
-
-typedef enum
-{
- IX_ETH_DB_ADD_FILTERING_RECORD = 0xFF0001,
- IX_ETH_DB_REMOVE_FILTERING_RECORD = 0xFF0002
-} PortEventType;
-
-typedef struct
-{
- UINT32 eventType;
- IxEthDBPortId portID;
- IxEthDBMacAddr macAddr;
- BOOL staticEntry;
-} PortEvent;
-
-typedef struct
-{
- PortEvent queue[EVENT_QUEUE_SIZE];
- UINT32 base;
- UINT32 length;
-} PortEventQueue;
-
-typedef struct
-{
- IxEthDBPortId portID; /**< originating port */
- MacDescriptor *macDescriptors[MAX_ELT_SIZE]; /**< addresses to be synced into db */
- UINT32 addressCount; /**< number of addresses */
-} TreeSyncInfo;
-
-typedef struct
-{
- MacTreeNode *nodes[MAX_ELT_SIZE];
- UINT32 offsets[MAX_ELT_SIZE];
- UINT32 nodeCount;
-} MacTreeNodeStack;
-
-/* Prototypes */
-
-/* ----------- Memory management -------------- */
-
-IX_ETH_DB_PUBLIC void ixEthDBInitMemoryPools(void);
-
-IX_ETH_DB_PUBLIC HashNode* ixEthDBAllocHashNode(void);
-IX_ETH_DB_PUBLIC void ixEthDBFreeHashNode(HashNode *);
-
-IX_ETH_DB_PUBLIC __smartpointer__ MacDescriptor* ixEthDBAllocMacDescriptor(void);
-IX_ETH_DB_PUBLIC __smartpointer__ MacDescriptor* ixEthDBCloneMacDescriptor(MacDescriptor *macDescriptor);
-IX_ETH_DB_PUBLIC __smartpointer__ void ixEthDBFreeMacDescriptor(MacDescriptor *);
-
-IX_ETH_DB_PUBLIC __smartpointer__ MacTreeNode* ixEthDBAllocMacTreeNode(void);
-IX_ETH_DB_PUBLIC __smartpointer__ MacTreeNode* ixEthDBCloneMacTreeNode(MacTreeNode *);
-IX_ETH_DB_PUBLIC __smartpointer__ void ixEthDBFreeMacTreeNode(MacTreeNode *);
-
-IX_ETH_DB_PUBLIC void ixEthDBPoolFreeMacTreeNode(MacTreeNode *);
-IX_ETH_DB_PUBLIC UINT32 ixEthDBSearchTreeUsageGet(MacTreeNode *tree);
-IX_ETH_DB_PUBLIC int ixEthDBShowMemoryStatus(void);
-
-/* Hash Table */
-IX_ETH_DB_PUBLIC void ixEthDBInitHash(HashTable *hashTable, UINT32 numBuckets, HashFunction entryHashFunction, MatchFunction *matchFunctions, FreeFunction freeFunction);
-
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBAddHashEntry(HashTable *hashTable, void *entry);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBRemoveHashEntry(HashTable *hashTable, int keyType, void *reference);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBSearchHashEntry(HashTable *hashTable, int keyType, void *reference, HashNode **searchResult);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPeekHashEntry(HashTable *hashTable, int keyType, void *reference);
-IX_ETH_DB_PUBLIC void ixEthDBReleaseHashNode(HashNode *node);
-
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBInitHashIterator(HashTable *hashTable, HashIterator *iterator);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBIncrementHashIterator(HashTable *hashTable, HashIterator *iterator);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBRemoveEntryAtHashIterator(HashTable *hashTable, HashIterator *iterator);
-IX_ETH_DB_PUBLIC void ixEthDBReleaseHashIterator(HashIterator *iterator);
-
-/* API Support */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAddr);
-IX_ETH_DB_PUBLIC void ixEthDBMaximumFrameSizeAckCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg);
-
-/* DB Core functions */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBInit(void);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBAdd(MacDescriptor *newRecordTemplate, IxEthDBPortMap updateTrigger);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBRemove(MacDescriptor *templateRecord, IxEthDBPortMap updateTrigger);
-IX_ETH_DB_PUBLIC HashNode* ixEthDBSearch(IxEthDBMacAddr *macAddress, IxEthDBRecordType typeFilter);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPeek(IxEthDBMacAddr *macAddress, IxEthDBRecordType typeFilter);
-
-/* Learning support */
-IX_ETH_DB_PUBLIC UINT32 ixEthDBAddressCompare(UINT8 *mac1, UINT8 *mac2);
-IX_ETH_DB_PUBLIC BOOL ixEthDBAddressMatch(void *reference, void *entry);
-IX_ETH_DB_PUBLIC UINT32 ixEthDBEntryXORHash(void *macDescriptor);
-IX_ETH_DB_PUBLIC UINT32 ixEthDBKeyXORHash(void *macAddress);
-
-/* Port updates */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBNPEUpdateHandler(IxEthDBPortId portID, IxEthDBRecordType type);
-IX_ETH_DB_PUBLIC void ixEthDBUpdatePortLearningTrees(IxEthDBPortMap triggerPorts);
-IX_ETH_DB_PUBLIC void ixEthDBNPEAccessRequest(IxEthDBPortId portID);
-IX_ETH_DB_PUBLIC void ixEthDBUpdateLock(void);
-IX_ETH_DB_PUBLIC void ixEthDBUpdateUnlock(void);
-IX_ETH_DB_PUBLIC MacTreeNode* ixEthDBQuery(MacTreeNode *searchTree, IxEthDBPortMap query, IxEthDBRecordType recordFilter, UINT32 maximumEntries);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBFirewallUpdate(IxEthDBPortId portID, void *address, UINT32 epDelta);
-
-/* Init/unload */
-IX_ETH_DB_PUBLIC void ixEthDBPortSetAckCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBEventProcessorInit(void);
-IX_ETH_DB_PUBLIC void ixEthDBPortInit(IxEthDBPortId portID);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID);
-IX_ETH_DB_PUBLIC void ixEthDBNPEUpdateAreasInit(void);
-IX_ETH_DB_PUBLIC UINT32 ixEthDBMatchMethodsRegister(MatchFunction *matchFunctions);
-IX_ETH_DB_PUBLIC UINT32 ixEthDBRecordSerializeMethodsRegister(void);
-IX_ETH_DB_PUBLIC UINT32 ixEthDBUpdateTypeRegister(BOOL *typeArray);
-IX_ETH_DB_PUBLIC void ixEthDBNPEUpdateAreasUnload(void);
-IX_ETH_DB_PUBLIC void ixEthDBFeatureCapabilityScan(void);
-IX_ETH_DB_PUBLIC UINT32 ixEthDBKeyTypeRegister(UINT32 *keyType);
-
-/* Event processing */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBDefaultEventCallbackEnable(IxEthDBPortId portID, BOOL enable);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBTriggerAddPortUpdate(IxEthDBMacAddr *macAddr, IxEthDBPortId portID, BOOL staticEntry);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBTriggerRemovePortUpdate(IxEthDBMacAddr *macAddr, IxEthDBPortId portID);
-IX_ETH_DB_PUBLIC void ixEthDBNPEEventCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg);
-
-/* NPE adaptor */
-IX_ETH_DB_PUBLIC void ixEthDBGetMacDatabaseCbk(IxNpeMhNpeId npeID, IxNpeMhMessage msg);
-IX_ETH_DB_PUBLIC void ixEthDBNpeMsgAck(IxNpeMhNpeId npeID, IxNpeMhMessage msg);
-IX_ETH_DB_PUBLIC void ixEthDBNPESyncScan(IxEthDBPortId portID, void *eltBaseAddress, UINT32 eltSize);
-IX_ETH_DB_PUBLIC void ixEthDBNPETreeWrite(IxEthDBRecordType type, UINT32 totalSize, void *baseAddress, MacTreeNode *tree, UINT32 *blocks, UINT32 *startIndex);
-IX_ETH_DB_PUBLIC void ixEthDBNPEGatewayNodeWrite(void *address, MacTreeNode *node);
-
-/* Other public API functions */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBStartLearningFunction(void);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBStopLearningFunction(void);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortUpdateEnableSet(IxEthDBPortId portID, BOOL enableUpdate);
-
-/* Maximum Tx/Rx public functions */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBFilteringPortMaximumRxFrameSizeSet(IxEthDBPortId portID, UINT32 maximumRxFrameSize);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBFilteringPortMaximumTxFrameSizeSet(IxEthDBPortId portID, UINT32 maximumTxFrameSize);
-
-/* VLAN-related */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortVlanTableSet(IxEthDBPortId portID, IxEthDBVlanSet portVlanTable, IxEthDBVlanSet vlanSet);
-
-/* Record search */
-IX_ETH_DB_PUBLIC BOOL ixEthDBAddressRecordMatch(void *untypedReference, void *untypedEntry);
-IX_ETH_DB_PUBLIC BOOL ixEthDBVlanRecordMatch(void *untypedReference, void *untypedEntry);
-IX_ETH_DB_PUBLIC BOOL ixEthDBPortRecordMatch(void *untypedReference, void *untypedEntry);
-IX_ETH_DB_PUBLIC BOOL ixEthDBNullMatch(void *reference, void *entry);
-IX_ETH_DB_PUBLIC HashNode* ixEthDBPortSearch(IxEthDBMacAddr *macAddress, IxEthDBPortId portID, IxEthDBRecordType typeFilter);
-IX_ETH_DB_PUBLIC HashNode* ixEthDBVlanSearch(IxEthDBMacAddr *macAddress, IxEthDBVlanId vlanID, IxEthDBRecordType typeFilter);
-
-/* Utilities */
-IX_ETH_DB_PUBLIC const char* mac2string(const unsigned char *mac);
-IX_ETH_DB_PUBLIC void showHashInfo(void);
-IX_ETH_DB_PUBLIC int ixEthDBAnalyzeHash(void);
-IX_ETH_DB_PUBLIC const char* errorString(IxEthDBStatus error);
-IX_ETH_DB_PUBLIC int numHashElements(void);
-IX_ETH_DB_PUBLIC void zapHashtable(void);
-IX_ETH_DB_PUBLIC BOOL ixEthDBCheckSingleBitValue(UINT32 value);
-
-/* Single Eth NPE Check */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBSingleEthNpeCheck(IxEthDBPortId portId);
-
-#endif /* IxEthDB_p_H */
-
+++ /dev/null
-/**
- * @file IxEthMii.h
- *
- * @brief this file contains the public API of @ref IxEthMii component
- *
- * Design notes :
- * The main intent of this API is to inplement MII high level fonctionalitoes
- * to support the codelets provided with the IXP400 software releases. It
- * superceedes previous interfaces provided with @ref IxEThAcc component.
- *
- * This API has been tested with the PHYs provided with the
- * IXP400 development platforms. It may not work for specific Ethernet PHYs
- * used on specific boards.
- *
- * This source code detects and interface the LXT972, LXT973 and KS6995
- * Ethernet PHYs.
- *
- * This source code should be considered as an example which may need
- * to be adapted for different hardware implementations.
- *
- * It is strongly recommended to use public domain and GPL utilities
- * like libmii, mii-diag for MII interface support.
- *
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxEthMii_H
-#define IxEthMii_H
-
-#include <IxTypes.h>
-
-/**
- * @defgroup IxEthMii IXP400 Ethernet Phy Access (IxEthMii) API
- *
- * @brief ethMii is a library that does provides access to the
- * Ethernet PHYs
- *
- *@{
- */
-
-/**
- * @ingroup IxEthMii
- *
- * @fn ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount)
- *
- * @brief Scan the MDIO bus for PHYs
- * This function scans PHY addresses 0 through 31, and sets phyPresent[n] to
- * TRUE if a phy is discovered at address n.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock.
- *
- * @param phyPresent BOOL [in] - boolean array of IXP425_ETH_ACC_MII_MAX_ADDR entries
- * @param maxPhyCount UINT32 [in] - number of PHYs to search for (the scan will stop when
- * the indicated number of PHYs is found).
- *
- * @return IX_STATUS
- * - IX_ETH_ACC_SUCCESS
- * - IX_ETH_ACC_FAIL : invalid arguments.
- *
- * <hr>
- */
-PUBLIC IX_STATUS ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount);
-
-/**
- * @ingroup IxEthMii
- *
- * @fn ixEthMiiPhyConfig(UINT32 phyAddr,
- BOOL speed100,
- BOOL fullDuplex,
- BOOL autonegotiate)
- *
- *
- * @brief Configure a PHY
- * Configure a PHY's speed, duplex and autonegotiation status
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock.
- *
- * @param phyAddr UINT32 [in]
- * @param speed100 BOOL [in] - set to TRUE for 100Mbit/s operation, FALSE for 10Mbit/s
- * @param fullDuplex BOOL [in] - set to TRUE for Full Duplex, FALSE for Half Duplex
- * @param autonegotiate BOOL [in] - set to TRUE to enable autonegotiation
- *
- * @return IX_STATUS
- * - IX_SUCCESS
- * - IX_FAIL : invalid arguments.
- *
- * <hr>
- */
-PUBLIC IX_STATUS ixEthMiiPhyConfig(UINT32 phyAddr,
- BOOL speed100,
- BOOL fullDuplex,
- BOOL autonegotiate);
-
-/**
- * @ingroup IxEthMii
- *
- * @fn ixEthMiiPhyLoopbackEnable(UINT32 phyAddr)
- *
- *
- * @brief Enable PHY Loopback in a specific Eth MII port
- *
- * @note When PHY Loopback is enabled, frames sent out to the PHY from the
- * IXP400 will be looped back to the IXP400. They will not be transmitted out
- * on the wire.
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31)
- *
- * @return IX_STATUS
- * - IX_SUCCESS
- * - IX_FAIL : invalid arguments.
- * <hr>
- */
-PUBLIC IX_STATUS
-ixEthMiiPhyLoopbackEnable (UINT32 phyAddr);
-
-/**
- * @ingroup IxEthMii
- *
- * @fn ixEthMiiPhyLoopbackDisable(UINT32 phyAddr)
- *
- *
- * @brief Disable PHY Loopback in a specific Eth MII port
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31)
- *
- * @return IX_STATUS
- * - IX_SUCCESS
- * - IX_FAIL : invalid arguments.
- * <hr>
- */
-PUBLIC IX_STATUS
-ixEthMiiPhyLoopbackDisable (UINT32 phyAddr);
-
-/**
- * @ingroup IxEthMii
- *
- * @fn ixEthMiiPhyReset(UINT32 phyAddr)
- *
- * @brief Reset a PHY
- * Reset a PHY
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock.
- *
- * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31)
- *
- * @return IX_STATUS
- * - IX_SUCCESS
- * - IX_FAIL : invalid arguments.
- *
- * <hr>
- */
-PUBLIC IX_STATUS ixEthMiiPhyReset(UINT32 phyAddr);
-
-
-/**
- * @ingroup IxEthMii
- *
- * @fn ixEthMiiLinkStatus(UINT32 phyAddr,
- BOOL *linkUp,
- BOOL *speed100,
- BOOL *fullDuplex,
- BOOL *autoneg)
- *
- * @brief Retrieve the current status of a PHY
- * Retrieve the link, speed, duplex and autonegotiation status of a PHY
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock.
- *
- * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31)
- * @param linkUp BOOL [out] - set to TRUE if the link is up
- * @param speed100 BOOL [out] - set to TRUE indicates 100Mbit/s, FALSE indicates 10Mbit/s
- * @param fullDuplex BOOL [out] - set to TRUE indicates Full Duplex, FALSE indicates Half Duplex
- * @param autoneg BOOL [out] - set to TRUE indicates autonegotiation is enabled, FALSE indicates autonegotiation is disabled
- *
- * @return IX_STATUS
- * - IX_SUCCESS
- * - IX_FAIL : invalid arguments.
- *
- * <hr>
- */
-PUBLIC IX_STATUS ixEthMiiLinkStatus(UINT32 phyAddr,
- BOOL *linkUp,
- BOOL *speed100,
- BOOL *fullDuplex,
- BOOL *autoneg);
-
-/**
- * @ingroup IxEthMii
- *
- * @fn ixEthMiiPhyShow (UINT32 phyAddr)
- *
- *
- * @brief Display information on a specified PHY
- * Display link status, speed, duplex and Auto Negotiation status
- *
- * - Reentrant - no
- * - ISR Callable - no
- *
- * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock.
- *
- * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31)
- *
- * @return IX_STATUS
- * - IX_SUCCESS
- * - IX_FAIL : invalid arguments.
- *
- * <hr>
- */
-PUBLIC IX_STATUS ixEthMiiPhyShow (UINT32 phyAddr);
-
-#endif /* ndef IxEthMii_H */
-/**
- *@}
- */
+++ /dev/null
-/**
- * @file IxEthMii_p.h
- *
- * @author Intel Corporation
- * @date
- *
- * @brief MII Header file
- *
- * Design Notes:
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxEthMii_p_H
-#define IxEthMii_p_H
-
-
-/* MII definitions - these have been verified against the LXT971 and
- LXT972 PHYs*/
-
-#define IX_ETH_MII_MAX_REG_NUM 0x20 /* max number of registers */
-
-#define IX_ETH_MII_CTRL_REG 0x0 /* Control Register */
-#define IX_ETH_MII_STAT_REG 0x1 /* Status Register */
-#define IX_ETH_MII_PHY_ID1_REG 0x2 /* PHY identifier 1 Register */
-#define IX_ETH_MII_PHY_ID2_REG 0x3 /* PHY identifier 2 Register */
-#define IX_ETH_MII_AN_ADS_REG 0x4 /* Auto-Negotiation */
- /* Advertisement Register */
-#define IX_ETH_MII_AN_PRTN_REG 0x5 /* Auto-Negotiation */
- /* partner ability Register */
-#define IX_ETH_MII_AN_EXP_REG 0x6 /* Auto-Negotiation */
- /* Expansion Register */
-#define IX_ETH_MII_AN_NEXT_REG 0x7 /* Auto-Negotiation */
- /* next-page transmit Register */
-
-#define IX_ETH_MII_STAT2_REG 0x11 /* Status Register 2*/
-
-
-/* MII control register bit */
-
-#define IX_ETH_MII_CR_COLL_TEST 0x0080 /* collision test */
-#define IX_ETH_MII_CR_FDX 0x0100 /* FDX =1, half duplex =0 */
-#define IX_ETH_MII_CR_RESTART 0x0200 /* restart auto negotiation */
-#define IX_ETH_MII_CR_ISOLATE 0x0400 /* isolate PHY from MII */
-#define IX_ETH_MII_CR_POWER_DOWN 0x0800 /* power down */
-#define IX_ETH_MII_CR_AUTO_EN 0x1000 /* auto-negotiation enable */
-#define IX_ETH_MII_CR_100 0x2000 /* 0 = 10mb, 1 = 100mb */
-#define IX_ETH_MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
-#define IX_ETH_MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
-#define IX_ETH_MII_CR_NORM_EN 0x0000 /* just enable the PHY */
-#define IX_ETH_MII_CR_DEF_0_MASK 0xca7f /* they must return zero */
-#define IX_ETH_MII_CR_RES_MASK 0x007f /* reserved bits, return zero */
-
-/* MII Status register bit definitions */
-
-#define IX_ETH_MII_SR_LINK_STATUS 0x0004 /* link Status -- 1 = link */
-#define IX_ETH_MII_SR_AUTO_SEL 0x0008 /* auto speed select capable */
-#define IX_ETH_MII_SR_REMOTE_FAULT 0x0010 /* Remote fault detect */
-#define IX_ETH_MII_SR_AUTO_NEG 0x0020 /* auto negotiation complete */
-#define IX_ETH_MII_SR_10T_HALF_DPX 0x0800 /* 10BaseT HD capable */
-#define IX_ETH_MII_SR_10T_FULL_DPX 0x1000 /* 10BaseT FD capable */
-#define IX_ETH_MII_SR_TX_HALF_DPX 0x2000 /* TX HD capable */
-#define IX_ETH_MII_SR_TX_FULL_DPX 0x4000 /* TX FD capable */
-#define IX_ETH_MII_SR_T4 0x8000 /* T4 capable */
-#define IX_ETH_MII_SR_ABIL_MASK 0xff80 /* abilities mask */
-#define IX_ETH_MII_SR_EXT_CAP 0x0001 /* extended capabilities */
-
-
-/* LXT971/2 Status 2 register bit definitions */
-#define IX_ETH_MII_SR2_100 0x4000
-#define IX_ETH_MII_SR2_TX 0x2000
-#define IX_ETH_MII_SR2_RX 0x1000
-#define IX_ETH_MII_SR2_COL 0x0800
-#define IX_ETH_MII_SR2_LINK 0x0400
-#define IX_ETH_MII_SR2_FD 0x0200
-#define IX_ETH_MII_SR2_AUTO 0x0100
-#define IX_ETH_MII_SR2_AUTO_CMPLT 0x0080
-#define IX_ETH_MII_SR2_POLARITY 0x0020
-#define IX_ETH_MII_SR2_PAUSE 0x0010
-#define IX_ETH_MII_SR2_ERROR 0x0008
-
-/* MII Link Code word bit definitions */
-
-#define IX_ETH_MII_BP_FAULT 0x2000 /* remote fault */
-#define IX_ETH_MII_BP_ACK 0x4000 /* acknowledge */
-#define IX_ETH_MII_BP_NP 0x8000 /* nexp page is supported */
-
-/* MII Next Page bit definitions */
-
-#define IX_ETH_MII_NP_TOGGLE 0x0800 /* toggle bit */
-#define IX_ETH_MII_NP_ACK2 0x1000 /* acknowledge two */
-#define IX_ETH_MII_NP_MSG 0x2000 /* message page */
-#define IX_ETH_MII_NP_ACK1 0x4000 /* acknowledge one */
-#define IX_ETH_MII_NP_NP 0x8000 /* nexp page will follow */
-
-/* MII Expansion Register bit definitions */
-
-#define IX_ETH_MII_EXP_FAULT 0x0010 /* parallel detection fault */
-#define IX_ETH_MII_EXP_PRTN_NP 0x0008 /* link partner next-page able */
-#define IX_ETH_MII_EXP_LOC_NP 0x0004 /* local PHY next-page able */
-#define IX_ETH_MII_EXP_PR 0x0002 /* full page received */
-#define IX_ETH_MII_EXP_PRT_AN 0x0001 /* link partner auto neg able */
-
-/* technology ability field bit definitions */
-
-#define IX_ETH_MII_TECH_10BASE_T 0x0020 /* 10Base-T */
-#define IX_ETH_MII_TECH_10BASE_FD 0x0040 /* 10Base-T Full Duplex */
-#define IX_ETH_MII_TECH_100BASE_TX 0x0080 /* 100Base-TX */
-#define IX_ETH_MII_TECH_100BASE_TX_FD 0x0100 /* 100Base-TX Full Duplex */
-
-#define IX_ETH_MII_TECH_100BASE_T4 0x0200 /* 100Base-T4 */
-#define IX_ETH_MII_ADS_TECH_MASK 0x1fe0 /* technology abilities mask */
-#define IX_ETH_MII_TECH_MASK IX_ETH_MII_ADS_TECH_MASK
-#define IX_ETH_MII_ADS_SEL_MASK 0x001f /* selector field mask */
-
-#define IX_ETH_MII_AN_FAIL 0x10 /* auto-negotiation fail */
-#define IX_ETH_MII_STAT_FAIL 0x20 /* errors in the status register */
-#define IX_ETH_MII_PHY_NO_ABLE 0x40 /* the PHY lacks some abilities */
-
-/* Definitions for MII access routines*/
-
-#define IX_ETH_MII_GO BIT(31)
-#define IX_ETH_MII_WRITE BIT(26)
-#define IX_ETH_MII_TIMEOUT_10TH_SECS (5)
-#define IX_ETH_MII_10TH_SEC_IN_MILLIS (100)
-#define IX_ETH_MII_READ_FAIL BIT(31)
-
-/* When we reset the PHY we delay for 2 seconds to allow the reset to
- complete*/
-#define IX_ETH_MII_RESET_DELAY_MS (2000)
-#define IX_ETH_MII_RESET_POLL_MS (50)
-
-#define IX_ETH_MII_REG_SHL 16
-#define IX_ETH_MII_ADDR_SHL 21
-
-/* supported PHYs */
-#define IX_ETH_MII_LXT971_PHY_ID 0x001378E0
-#define IX_ETH_MII_LXT972_PHY_ID 0x001378E2
-#define IX_ETH_MII_LXT973_PHY_ID 0x00137A10
-#define IX_ETH_MII_LXT973A3_PHY_ID 0x00137A11
-#define IX_ETH_MII_KS8995_PHY_ID 0x00221450
-#define IX_ETH_MII_LXT9785_PHY_ID 0x001378FF
-
-
-#define IX_ETH_MII_INVALID_PHY_ID 0x00000000
-#define IX_ETH_MII_UNKNOWN_PHY_ID 0xffffffff
-
-#endif /*IxEthAccMii_p_H*/
+++ /dev/null
-#ifndef __doxygen_HIDE /* This file is not part of the API */
-
-/**
- * @file IxEthNpe.h
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxEthNpe IXP400 Ethernet NPE (IxEthNpe) API
- *
- * @brief Contains the API for Ethernet NPE.
- *
- * All messages given to NPE, get back an acknowledgment. The acknowledgment
- * is identical to the message sent to the NPE (except for NPE_GETSTATUS message).
- *
- * @{
- */
-
-
-/*--------------------------------------------------------------------------
- * APB Message IDs - XScale->NPE
- *------------------------------------------------------------------------*/
-
-/**
- * @def IX_ETHNPE_NPE_GETSTATUS
- *
- * @brief Request from the XScale client for the NPE to return the firmware
- * version of the currently executing image.
- *
- * Acknowledgment message id is same as the request message id.
- * NPE returns the firmware version ID to XScale.
- */
-#define IX_ETHNPE_NPE_GETSTATUS 0x00
-
-/**
- * @def IX_ETHNPE_EDB_SETPORTADDRESS
- *
- * @brief Request from the XScale client for the NPE to set the Ethernet
- * port's port ID and MAC address.
- */
-#define IX_ETHNPE_EDB_SETPORTADDRESS 0x01
-
-/**
- * @def IX_ETHNPE_EDB_GETMACADDRESSDATABASE
- *
- * @brief Request from XScale client to the NPE requesting upload of
- * Ethernet Filtering Database or Header Conversion Database from NPE's
- * data memory to XScale accessible SDRAM.
- */
-#define IX_ETHNPE_EDB_GETMACADDRESSDATABASE 0x02
-
-/**
- * @def IX_ETHNPE_EDB_SETMACADDRESSSDATABASE
- *
- * @brief Request from XScale client to the NPE requesting download of
- * Ethernet Filtering Database or Header Conversion Database from SDRAM
- * to the NPE's datamemory.
- */
-#define IX_ETHNPE_EDB_SETMACADDRESSSDATABASE 0x03
-
-/**
- * @def IX_ETHNPE_GETSTATS
- *
- * @brief Request from the XScale client for the current MAC port statistics
- * data to be written to the (empty) statistics structure and the specified
- * location in externa memory.
- */
-#define IX_ETHNPE_GETSTATS 0x04
-
-/**
- * @def IX_ETHNPE_RESETSTATS
- *
- * @brief Request from the XScale client to the NPE to reset all of its internal
- * MAC port statistics state variables.
- *
- * As a side effect, this message entails an implicit request that the NPE
- * write the current MAC port statistics into the MAC statistics structure
- * at the specified location in external memory.
- */
-#define IX_ETHNPE_RESETSTATS 0x05
-
-/**
- * @def IX_ETHNPE_SETMAXFRAMELENGTHS
- *
- * @brief Request from the XScale client to the NPE to configure maximum framelengths
- * and block sizes in receive and transmit direction.
- */
-#define IX_ETHNPE_SETMAXFRAMELENGTHS 0x06
-
-/**
- * @def IX_ETHNPE_VLAN_SETRXTAGMODE
- *
- * @brief Request from the XScale client to the NPE to configure VLAN frame type
- * filtering and VLAN the tagging mode for the receiver.
- */
-#define IX_ETHNPE_VLAN_SETRXTAGMODE 0x07
-
-/**
- * @def IX_ETHNPE_VLAN_SETDEFAULTRXVID
- *
- * @brief Request from the XScale client to the NPE to set receiver's default
- * VLAN tag (PVID)and internal traffic class.
- */
-#define IX_ETHNPE_VLAN_SETDEFAULTRXVID 0x08
-
-/**
- * @def IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY
- *
- * @brief Request from the XScale client to the NPE to configure VLAN Port
- * membership and Tx tagging for 8 consecutive VLANID's.
- */
-#define IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY 0x09
-
-/**
- * @def IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE
- *
- * @brief Request from the XScale client to the NPE to configure VLAN Port
- * membership and Tx tagging for a range of VLANID's.
- */
-#define IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE 0x0A
-
-/**
- * @def IX_ETHNPE_VLAN_SETRXQOSENTRY
- *
- * @brief Request from the XScale client to the NPE to map a user priority
- * to QoS class and an AQM queue number.
- */
-#define IX_ETHNPE_VLAN_SETRXQOSENTRY 0x0B
-
-/**
- * @def IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE
- *
- * @brief Request from the XScale client to the NPE to enable or disable
- * portID extraction from VLAN-tagged frames for the specified port.
- */
-#define IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C
-
-/**
- * @def IX_ETHNPE_STP_SETBLOCKINGSTATE
- *
- * @brief Request from the XScale client to the NPE to block or unblock
- * forwarding for spanning tree BPDUs.
- */
-#define IX_ETHNPE_STP_SETBLOCKINGSTATE 0x0D
-
-/**
- * @def IX_ETHNPE_FW_SETFIREWALLMODE
- *
- * @brief Request from the XScale client to the NPE to configure firewall
- * services modes of operation and/or download Ethernet Firewall Database from
- * SDRAM to NPE.
- */
-#define IX_ETHNPE_FW_SETFIREWALLMODE 0x0E
-
-/**
- * @def IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID
- *
- * @brief Request from the XScale client to the NPE to set global frame control
- * and duration/ID field for the 802.3 to 802.11 protocol header conversion
- * service.
- */
-#define IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID 0x0F
-
-/**
- * @def IX_ETHNPE_PC_SETBBSID
- *
- * @brief Request from the XScale client to the NPE to set global BBSID field
- * value for the 802.3 to 802.11 protocol header conversion service.
- */
-#define IX_ETHNPE_PC_SETBBSID 0x10
-
-/**
- * @def IX_ETHNPE_PC_SETAPMACTABLE
- *
- * @brief Request from the XScale client to the NPE to update a block/section/
- * range of the AP MAC Address Table.
- */
-#define IX_ETHNPE_PC_SETAPMACTABLE 0x11
-
-/**
- * @def IX_ETHNPE_SETLOOPBACK_MODE
- *
- * @brief Turn on or off the NPE frame loopback.
- */
-#define IX_ETHNPE_SETLOOPBACK_MODE (0x12)
-
-/*--------------------------------------------------------------------------
- * APB Message IDs - NPE->XScale
- *------------------------------------------------------------------------*/
-
-/**
- * @def IX_ETHNPE_NPE_GETSTATUS_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_NPE_GETSTATUS message. NPE firmware version
- * id is returned in the message.
- */
-#define IX_ETHNPE_NPE_GETSTATUS_ACK 0x00
-
-/**
- * @def IX_ETHNPE_EDB_SETPORTADDRESS_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_EDB_SETPORTADDRESS message.
- */
-#define IX_ETHNPE_EDB_SETPORTADDRESS_ACK 0x01
-
-/**
- * @def IX_ETHNPE_EDB_GETMACADDRESSDATABASE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_EDB_GETMACADDRESSDATABASE message
- */
-#define IX_ETHNPE_EDB_GETMACADDRESSDATABASE_ACK 0x02
-
-/**
- * @def IX_ETHNPE_EDB_SETMACADDRESSSDATABASE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_EDB_SETMACADDRESSSDATABASE message.
- */
-#define IX_ETHNPE_EDB_SETMACADDRESSSDATABASE_ACK 0x03
-
-/**
- * @def IX_ETHNPE_GETSTATS_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_GETSTATS message.
- */
-#define IX_ETHNPE_GETSTATS_ACK 0x04
-
-/**
- * @def IX_ETHNPE_RESETSTATS_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_RESETSTATS message.
- */
-#define IX_ETHNPE_RESETSTATS_ACK 0x05
-
-/**
- * @def IX_ETHNPE_SETMAXFRAMELENGTHS_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_SETMAXFRAMELENGTHS message.
- */
-#define IX_ETHNPE_SETMAXFRAMELENGTHS_ACK 0x06
-
-/**
- * @def IX_ETHNPE_VLAN_SETRXTAGMODE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_VLAN_SETRXTAGMODE message.
- */
-#define IX_ETHNPE_VLAN_SETRXTAGMODE_ACK 0x07
-
-/**
- * @def IX_ETHNPE_VLAN_SETDEFAULTRXVID_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_VLAN_SETDEFAULTRXVID message.
- */
-#define IX_ETHNPE_VLAN_SETDEFAULTRXVID_ACK 0x08
-
-/**
- * @def IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY message.
- */
-#define IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY_ACK 0x09
-
-/**
- * @def IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE message.
- */
-#define IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE_ACK 0x0A
-
-/**
- * @def IX_ETHNPE_VLAN_SETRXQOSENTRY_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_VLAN_SETRXQOSENTRY message.
- */
-#define IX_ETHNPE_VLAN_SETRXQOSENTRY_ACK 0x0B
-
-/**
- * @def IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE message.
- */
-#define IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE_ACK 0x0C
-
-/**
- * @def IX_ETHNPE_STP_SETBLOCKINGSTATE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_STP_SETBLOCKINGSTATE message.
- */
-#define IX_ETHNPE_STP_SETBLOCKINGSTATE_ACK 0x0D
-
-/**
- * @def IX_ETHNPE_FW_SETFIREWALLMODE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_FW_SETFIREWALLMODE message.
- */
-#define IX_ETHNPE_FW_SETFIREWALLMODE_ACK 0x0E
-
-/**
- * @def IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID message.
- */
-#define IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID_ACK 0x0F
-
-/**
- * @def IX_ETHNPE_PC_SETBBSID_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_PC_SETBBSID message.
- */
-#define IX_ETHNPE_PC_SETBBSID_ACK 0x10
-
-/**
- * @def IX_ETHNPE_PC_SETAPMACTABLE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_PC_SETAPMACTABLE message.
- */
-#define IX_ETHNPE_PC_SETAPMACTABLE_ACK 0x11
-
-/**
- * @def IX_ETHNPE_SETLOOPBACK_MODE_ACK
- *
- * @brief Acknowledgment to IX_ETHNPE_SETLOOPBACK_MODE message.
- */
-#define IX_ETHNPE_SETLOOPBACK_MODE_ACK (0x12)
-
-/*--------------------------------------------------------------------------
- * Queue Manager Queue entry bit field boundary definitions
- *------------------------------------------------------------------------*/
-
-/**
- * @def MASK(hi,lo)
- *
- * @brief Macro for mask
- */
-#define MASK(hi,lo) (((1 << (1 + ((hi) - (lo)))) - 1) << (lo))
-
-/**
- * @def BITS(x,hi,lo)
- *
- * @brief Macro for bits
- */
-#define BITS(x,hi,lo) (((x) & MASK(hi,lo)) >> (lo))
-
-/**
- * @def IX_ETHNPE_QM_Q_RXENET_LENGTH_MASK
- *
- * @brief QMgr Queue LENGTH field mask
- */
-#define IX_ETHNPE_QM_Q_RXENET_LENGTH_MASK 0x3fff
-
-/**
- * @def IX_ETHNPE_QM_Q_FIELD_FLAG_R
- *
- * @brief QMgr Queue FLAG field right boundary
- */
-#define IX_ETHNPE_QM_Q_FIELD_FLAG_R 20
-
-/**
- * @def IX_ETHNPE_QM_Q_FIELD_FLAG_MASK
- *
- * @brief QMgr Queue FLAG field mask
- *
- * Multicast bit : BIT(4)
- * Broadcast bit : BIT(5)
- * IP bit : BIT(6) (linux only)
- *
- */
-#ifdef __vxworks
-#define IX_ETHNPE_QM_Q_FIELD_FLAG_MASK 0x30
-#else
-#define IX_ETHNPE_QM_Q_FIELD_FLAG_MASK 0x70
-#endif
-
-
-/**
- * @def IX_ETHNPE_QM_Q_FIELD_NPEID_L
- *
- * @brief QMgr Queue NPE ID field left boundary
- */
-#define IX_ETHNPE_QM_Q_FIELD_NPEID_L 1
-
-/**
- * @def IX_ETHNPE_QM_Q_FIELD_NPEID_R
- *
- * @brief QMgr Queue NPE ID field right boundary
- */
-#define IX_ETHNPE_QM_Q_FIELD_NPEID_R 0
-
-/**
- * @def IX_ETHNPE_QM_Q_FIELD_PRIOR_L
- *
- * @brief QMgr Queue Priority field left boundary
- */
-#define IX_ETHNPE_QM_Q_FIELD_PRIOR_L 2
-
-/**
- * @def IX_ETHNPE_QM_Q_FIELD_PRIOR_R
- *
- * @brief QMgr Queue Priority field right boundary
- */
-#define IX_ETHNPE_QM_Q_FIELD_PRIOR_R 0
-
-/**
- * @def IX_ETHNPE_QM_Q_FIELD_ADDR_L
- *
- * @brief QMgr Queue Address field left boundary
- */
-#define IX_ETHNPE_QM_Q_FIELD_ADDR_L 31
-
-/**
- * @def IX_ETHNPE_QM_Q_FIELD_ADDR_R
- *
- * @brief QMgr Queue Address field right boundary
- */
-#define IX_ETHNPE_QM_Q_FIELD_ADDR_R 5
-
-/*--------------------------------------------------------------------------
- * Queue Manager Queue entry bit field masks
- *------------------------------------------------------------------------*/
-
-/**
- * @def IX_ETHNPE_QM_Q_FREEENET_ADDR_MASK
- *
- * @brief Macro to mask the Address field of the FreeEnet Queue Manager Entry
- */
-#define IX_ETHNPE_QM_Q_FREEENET_ADDR_MASK \
- MASK (IX_ETHNPE_QM_Q_FIELD_ADDR_L, \
- IX_ETHNPE_QM_Q_FIELD_ADDR_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_RXENET_NPEID_MASK
- *
- * @brief Macro to mask the NPE ID field of the RxEnet Queue Manager Entry
- */
-#define IX_ETHNPE_QM_Q_RXENET_NPEID_MASK \
- MASK (IX_ETHNPE_QM_Q_FIELD_NPEID_L, \
- IX_ETHNPE_QM_Q_FIELD_NPEID_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_RXENET_ADDR_MASK
- *
- * @brief Macro to mask the Mbuf Address field of the RxEnet Queue Manager Entry
- */
-#define IX_ETHNPE_QM_Q_RXENET_ADDR_MASK \
- MASK (IX_ETHNPE_QM_Q_FIELD_ADDR_L, \
- IX_ETHNPE_QM_Q_FIELD_ADDR_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_TXENET_PRIOR_MASK
- *
- * @brief Macro to mask the Priority field of the TxEnet Queue Manager Entry
- */
-#define IX_ETHNPE_QM_Q_TXENET_PRIOR_MASK \
- MASK (IX_ETHNPE_QM_Q_FIELD_PRIOR_L, \
- IX_ETHNPE_QM_Q_FIELD_PRIOR_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_TXENET_ADDR_MASK
- *
- * @brief Macro to mask the Mbuf Address field of the TxEnet Queue Manager Entry
- */
-#define IX_ETHNPE_QM_Q_TXENET_ADDR_MASK \
- MASK (IX_ETHNPE_QM_Q_FIELD_ADDR_L, \
- IX_ETHNPE_QM_Q_FIELD_ADDR_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_TXENETDONE_NPEID_MASK
- *
- * @brief Macro to mask the NPE ID field of the TxEnetDone Queue Manager Entry
- */
-#define IX_ETHNPE_QM_Q_TXENETDONE_NPEID_MASK \
- MASK (IX_ETHNPE_QM_Q_FIELD_NPEID_L, \
- IX_ETHNPE_QM_Q_FIELD_NPEID_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_TXENETDONE_ADDR_MASK
- *
- * @brief Macro to mask the Mbuf Address field of the TxEnetDone Queue Manager
- * Entry
- */
-#define IX_ETHNPE_QM_Q_TXENETDONE_ADDR_MASK \
- MASK (IX_ETHNPE_QM_Q_FIELD_ADDR_L, \
- IX_ETHNPE_QM_Q_FIELD_ADDR_R)
-
-/*--------------------------------------------------------------------------
- * Queue Manager Queue entry bit field value extraction macros
- *------------------------------------------------------------------------*/
-
-/**
- * @def IX_ETHNPE_QM_Q_FREEENET_ADDR_VAL(x)
- *
- * @brief Extraction macro for Address field of FreeNet Queue Manager Entry
- *
- * Pointer to an mbuf buffer descriptor
- */
-#define IX_ETHNPE_QM_Q_FREEENET_ADDR_VAL(x) \
- ((x) & IX_ETHNPE_QM_Q_FREEENET_ADDR_MASK)
-
-/**
- * @def IX_ETHNPE_QM_Q_RXENET_NPEID_VAL(x)
- *
- * @brief Extraction macro for NPE ID field of RxEnet Queue Manager Entry
- *
- * Set to 0 for entries originating from the Eth0 NPE;
- * Set to 1 for entries originating from the Eth1 NPE.
- */
-#define IX_ETHNPE_QM_Q_RXENET_NPEID_VAL(x) \
- BITS (x, IX_ETHNPE_QM_Q_FIELD_NPEID_L, \
- IX_ETHNPE_QM_Q_FIELD_NPEID_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_RXENET_PORTID_VAL(x)
- *
- * @brief Extraction macro for Port ID field of RxEnet Queue Manager Entry
- *
- * 0-5: Assignable (by the XScale client) to any of the physical ports.
- * 6: It is reserved
- * 7: Indication that the NPE did not find the associated frame's destination MAC address within
- * its internal filtering database.
- */
-#define IX_ETHNPE_QM_Q_RXENET_PORTID_VAL(x) \
- BITS (x, IX_ETHNPE_QM_Q_FIELD_PORTID_L, \
- IX_ETHNPE_QM_Q_Field_PortID_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_RXENET_ADDR_VAL(x)
- *
- * @brief Extraction macro for Address field of RxEnet Queue Manager Entry
- *
- * Pointer to an mbuf buffer descriptor
- */
-#define IX_ETHNPE_QM_Q_RXENET_ADDR_VAL(x) \
- ((x) & IX_ETHNPE_QM_Q_RXENET_ADDR_MASK)
-
-/**
- * @def IX_ETHNPE_QM_Q_TXENET_PRIOR_VAL(x)
- *
- * @brief Extraction macro for Priority field of TxEnet Queue Manager Entry
- *
- * Priority of the packet (as described in IEEE 802.1D). This field is
- * cleared upon return from the Ethernet NPE to the TxEnetDone queue.
- */
-#define IX_ETHNPE_QM_Q_TXENET_PRIOR_VAL(x) \
- BITS (x, IX_ETHNPE_QM_Q_FIELD_PRIOR_L, \
- IX_ETHNPE_QM_Q_FIELD_PRIOR_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_TXENET_ADDR_VAL(x)
- *
- * @brief Extraction macro for Address field of Queue Manager TxEnet Queue
- * Manager Entry
- *
- * Pointer to an mbuf buffer descriptor
- */
-#define IX_ETHNPE_QM_Q_TXENET_ADDR_VAL(x) \
- ((x) & IX_ETHNPE_QM_Q_TXENET_ADDR_MASK)
-
-/**
- * @def IX_ETHNPE_QM_Q_TXENETDONE_NPEID_VAL(x)
- *
- * @brief Extraction macro for NPE ID field of TxEnetDone Queue Manager Entry
- *
- * Set to 0 for entries originating from the Eth0 NPE; set to 1 for en-tries
- * originating from the Eth1 NPE.
- */
-#define IX_ETHNPE_QM_Q_TXENETDONE_NPEID_VAL(x) \
- BITS (x, IX_ETHNPE_QM_Q_FIELD_NPEID_L, \
- IX_ETHNPE_QM_Q_FIELD_NPEID_R)
-
-/**
- * @def IX_ETHNPE_QM_Q_TXENETDONE_ADDR_VAL(x)
- *
- * @brief Extraction macro for Address field of TxEnetDone Queue Manager Entry
- *
- * Pointer to an mbuf buffer descriptor
- */
-#define IX_ETHNPE_QM_Q_TXENETDONE_ADDR_VAL(x) \
- ((x) & IX_ETHNPE_QM_Q_TXENETDONE_ADDR_MASK)
-
-
-/*--------------------------------------------------------------------------
- * NPE limits
- *------------------------------------------------------------------------*/
-
-/**
- * @def IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN
- *
- * @brief Macro to check the minimum length of a rx free buffer
- */
-#define IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN (64)
-
-/**
- * @def IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MASK
- *
- * @brief Mask to apply to the mbuf length before submitting it to the NPE
- * (the NPE handles only rx free mbufs which are multiple of 64)
- *
- * @sa IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MASK
- */
-#define IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MASK (~63)
-
-/**
- * @def IX_ETHNPE_ACC_RXFREE_BUFFER_ROUND_UP(size)
- *
- * @brief Round up to get the size necessary to receive without chaining
- * the frames which are (size) bytes (the NPE operates by multiple of 64)
- * e.g. To receive 1514 bytes frames, the size of the buffers in replenish
- * has to be at least (1514+63)&(~63) = 1536 bytes.
- *
- */
-#define IX_ETHNPE_ACC_RXFREE_BUFFER_ROUND_UP(size) (((size) + 63) & ~63)
-
-/**
- * @def IX_ETHNPE_ACC_RXFREE_BUFFER_ROUND_DOWN(size)
- *
- * @brief Round down to apply to the mbuf length before submitting
- * it to the NPE. (the NPE operates by multiple of 64)
- *
- */
-#define IX_ETHNPE_ACC_RXFREE_BUFFER_ROUND_DOWN(size) ((size) & ~63)
-
-/**
- * @def IX_ETHNPE_ACC_FRAME_LENGTH_MAX
- *
- * @brief maximum mbuf length supported by the NPE
- *
- * @sa IX_ETHNPE_ACC_FRAME_LENGTH_MAX
- */
-#define IX_ETHNPE_ACC_FRAME_LENGTH_MAX (16320)
-
-/**
- * @def IX_ETHNPE_ACC_FRAME_LENGTH_DEFAULT
- *
- * @brief default mbuf length supported by the NPE
- *
- * @sa IX_ETHNPE_ACC_FRAME_LENGTH_DEFAULT
- */
-#define IX_ETHNPE_ACC_FRAME_LENGTH_DEFAULT (1522)
-
-/**
- * @def IX_ETHNPE_ACC_LENGTH_OFFSET
- *
- * @brief Offset of the cluster length field in the word shared with the NPEs
- */
-#define IX_ETHNPE_ACC_LENGTH_OFFSET 16
-
-/**
- * @def IX_ETHNPE_ACC_PKTLENGTH_MASK
- *
- * @brief Mask of the cluster length field in the word shared with the NPEs
- */
-#define IX_ETHNPE_ACC_PKTLENGTH_MASK 0x3fff
-
-
-/**
- *@}
- */
-
-#endif /* __doxygen_HIDE */
+++ /dev/null
-/**
- * @file IxFeatureCtrl.h
- *
- * @date 30-Jan-2003
-
- * @brief This file contains the public API of the IXP400 Feature Control
- * component.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-/* ------------------------------------------------------
- Doxygen group definitions
- ------------------------------------------------------ */
-/**
- * @defgroup IxFeatureCtrlAPI IXP400 Feature Control (IxFeatureCtrl) API
- *
- * @brief The Public API for the IXP400 Feature Control.
- *
- * @{
- */
-
-#ifndef IXFEATURECTRL_H
-#define IXFEATURECTRL_H
-
-/*
- * User defined include files
- */
-#include "IxOsal.h"
-
-/*
- * #defines and macros
- */
-
-/*************************************************************
- * The following are IxFeatureCtrlComponentCheck return values.
- ************************************************************/
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURE_CTRL_COMPONENT_DISABLED
- *
- * @brief Hardware Component is disabled/unavailable.
- * Return status by ixFeatureCtrlComponentCheck()
- */
-#define IX_FEATURE_CTRL_COMPONENT_DISABLED 0
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURE_CTRL_COMPONENT_ENABLED
- *
- * @brief Hardware Component is available.
- * Return status by ixFeatureCtrlComponentCheck()
- */
-#define IX_FEATURE_CTRL_COMPONENT_ENABLED 1
-
-/***********************************************************************************
- * Product ID in XScale CP15 - Register 0
- * - It contains information on the maximum XScale Core Frequency and
- * Silicon Stepping.
- * - XScale Core Frequency Id indicates only the maximum XScale frequency
- * achievable and not the running XScale frequency (maybe stepped down).
- * - The register is read by using ixFeatureCtrlProductIdRead.
- * - Usage example:
- * productId = ixFeatureCtrlProductIdRead();
- * if( (productId & IX_FEATURE_CTRL_SILICON_STEPPING_MASK) ==
- * IX_FEATURE_CTRL_SILICON_TYPE_A0 )
- * if( (productId & IX_FEATURE_CTRL_XSCALE_FREQ_MASK) ==
- * IX_FEATURE_CTRL_XSCALE_FREQ_533 )
- *
- * 31 28 27 24 23 20 19 16 15 12 11 9 8 4 3 0
- * --------------------------------------------------------------------------------
- * | 0x6 | 0x9 | 0x0 | 0x5 | 0x4 | Device ID | XScale Core Freq Id | Si Stepping Id |
- * --------------------------------------------------------------------------------
- *
- * Maximum Achievable XScale Core Frequency Id : 533MHz - 0x1C
- * 400MHz - 0x1D
- * 266MHz - 0x1F
- *
- * <b>THE CORE FREQUENCY ID IS NOT APPLICABLE TO IXP46X <\b>
- *
- * The above is applicable to IXP42X only. CP15 in IXP46X does not contain any
- * Frequency ID.
- *
- * Si Stepping Id : A - 0x0
- * B - 0x1
- *
- * XScale Core freq Id - Device ID [11:9] : IXP42X - 0x0
- * IXP46X - 0x1
- *************************************************************************************/
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURE_CTRL_SILICON_TYPE_A0
- *
- * @brief This is the value of A0 Silicon in product ID.
- */
-#define IX_FEATURE_CTRL_SILICON_TYPE_A0 0
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURE_CTRL_SILICON_TYPE_B0
- *
- * @brief This is the value of B0 Silicon in product ID.
- */
-#define IX_FEATURE_CTRL_SILICON_TYPE_B0 1
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURE_CTRL_SILICON_STEPPING_MASK
- *
- * @brief This is the mask of silicon stepping in product ID.
- */
-#define IX_FEATURE_CTRL_SILICON_STEPPING_MASK 0xF
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURE_CTRL_DEVICE_TYPE_MASK
- *
- * @brief This is the mask of silicon stepping in product ID.
- */
-#define IX_FEATURE_CTRL_DEVICE_TYPE_MASK (0x7)
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURE_CTRL_DEVICE_TYPE_OFFSET
- *
- * @brief This is the mask of silicon stepping in product ID.
- */
-#define IX_FEATURE_CTRL_DEVICE_TYPE_OFFSET 9
-
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURE_CTRL_XSCALE_FREQ_533
- *
- * @brief This is the value of 533MHz XScale Core in product ID.
- */
-#define IX_FEATURE_CTRL_XSCALE_FREQ_533 ((0x1C)<<4)
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURE_CTRL_XSCALE_FREQ_400
- *
- * @brief This is the value of 400MHz XScale Core in product ID.
- */
-#define IX_FEATURE_CTRL_XSCALE_FREQ_400 ((0x1D)<<4)
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURE_CTRL_XSCALE_FREQ_266
- *
- * @brief This is the value of 266MHz XScale Core in product ID.
- */
-#define IX_FEATURE_CTRL_XSCALE_FREQ_266 ((0x1F)<<4)
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURE_CTRL_XSCALE_FREQ_MASK
- *
- * @brief This is the mask of XScale Core in product ID.
- */
-#define IX_FEATURE_CTRL_XSCALE_FREQ_MASK ((0xFF)<<4)
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURECTRL_REG_UTOPIA_32PHY
- *
- * @brief Maximum UTOPIA PHY available is 32.
- *
- */
-#define IX_FEATURECTRL_REG_UTOPIA_32PHY 0x0
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURECTRL_REG_UTOPIA_16PHY
- *
- * @brief Maximum UTOPIA PHY available is 16.
- *
- */
-#define IX_FEATURECTRL_REG_UTOPIA_16PHY 0x1
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURECTRL_REG_UTOPIA_8PHY
- *
- * @brief Maximum UTOPIA PHY available to is 8.
- *
- */
-#define IX_FEATURECTRL_REG_UTOPIA_8PHY 0x2
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURECTRL_REG_UTOPIA_4PHY
- *
- * @brief Maximum UTOPIA PHY available to is 4.
- *
- */
-#define IX_FEATURECTRL_REG_UTOPIA_4PHY 0x3
-
-#ifdef __ixp46X
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURECTRL_REG_XSCALE_533FREQ
- *
- * @brief Maximum frequency available to IXP46x is 533 MHz.
- *
- */
-#define IX_FEATURECTRL_REG_XSCALE_533FREQ 0x0
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURECTRL_REG_XSCALE_667FREQ
- *
- * @brief Maximum frequency available to IXP46x is 667 MHz.
- *
- */
-#define IX_FEATURECTRL_REG_XSCALE_667FREQ 0x1
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURECTRL_REG_XSCALE_400FREQ
- *
- * @brief Maximum frequency available to IXP46x is 400 MHz.
- *
- */
-#define IX_FEATURECTRL_REG_XSCALE_400FREQ 0x2
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURECTRL_REG_XSCALE_266FREQ
- *
- * @brief Maximum frequency available to IXP46x is 266 MHz.
- *
- */
-#define IX_FEATURECTRL_REG_XSCALE_266FREQ 0x3
-
-#endif /* __ixp46X */
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE
- *
- * @brief Component selected is not available for device
- *
- */
-#define IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE 0x0000
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @def IX_FEATURECTRL_COMPONENT_ALWAYS_AVAILABLE
- *
- * @brief Component selected is not available for device
- *
- */
-#define IX_FEATURECTRL_COMPONENT_ALWAYS_AVAILABLE 0xffff
-
-/**
- * @defgroup IxFeatureCtrlSwConfig Software Configuration for Access Component
- *
- * @ingroup IxFeatureCtrlAPI
- *
- * @brief This section describes software configuration in access component. The
- * configuration can be changed at run-time. ixFeatureCtrlSwConfigurationCheck( )
- * will be used across applicable access component to check the configuration.
- * ixFeatureCtrlSwConfigurationWrite( ) is used to write the software configuration.
- *
- * @note <b>All software configurations are default to be enabled.</b>
- *
- * @{
- */
-/**
- * @ingroup IxFeatureCtrlSwConfig
- *
- * @def IX_FEATURE_CTRL_SWCONFIG_DISABLED
- *
- * @brief Software configuration is disabled.
- *
- */
-#define IX_FEATURE_CTRL_SWCONFIG_DISABLED 0
-
-/**
- * @ingroup IxFeatureCtrlSwConfig
- *
- * @def IX_FEATURE_CTRL_SWCONFIG_ENABLED
- *
- * @brief Software configuration is enabled.
- *
- */
-#define IX_FEATURE_CTRL_SWCONFIG_ENABLED 1
-
-/**
- * Section for enums
- **/
-
-/**
- * @ingroup IxFeatureCtrlBuildDevice
- *
- * @enum IxFeatureCtrlBuildDevice
- *
- * @brief Indicates software build type.
- *
- * Default build type is IXP42X
- *
- */
-typedef enum
-{
- IX_FEATURE_CTRL_SW_BUILD_IXP42X = 0, /**<Build type is IXP42X */
- IX_FEATURE_CTRL_SW_BUILD_IXP46X /**<Build type is IXP46X */
-} IxFeatureCtrlBuildDevice;
-
-/**
- * @ingroup IxFeatureCtrlSwConfig
- *
- * @enum IxFeatureCtrlSwConfig
- *
- * @brief Enumeration for software configuration in access components.
- *
- * Entry for new run-time software configuration should be added here.
- */
-typedef enum
-{
- IX_FEATURECTRL_ETH_LEARNING = 0, /**< EthDB Learning Feature */
- IX_FEATURECTRL_ORIGB0_DISPATCHER, /**< IXP42X B0 and IXP46X dispatcher without
- livelock prevention functionality Feature */
- IX_FEATURECTRL_SWCONFIG_MAX /**< Maximum boudary for IxFeatureCtrlSwConfig */
-} IxFeatureCtrlSwConfig;
-
-
-/************************************************************************
- * IXP400 Feature Control Register
- * - It contains the information (available/unavailable) of IXP425&IXP46X
- * hardware components in their corresponding bit location.
- * - Bit value of 0 means the hardware component is available
- * or not software disabled. Hardware component that is available
- * can be software disabled.
- * - Bit value of 1 means the hardware is unavailable or software
- * disabled.Hardware component that is unavailable cannot be software
- * enabled.
- * - Use ixFeatureCtrlHwCapabilityRead() to read the hardware component's
- * availability.
- * - Use ixFeatureCtrlRead() to get the current IXP425/IXP46X feature control
- * register value.
- *
- * Bit Field Description (Hardware Component Availability)
- * --- ---------------------------------------------------
- * 0 RComp Circuitry
- * 1 USB Controller
- * 2 Hashing Coprocessor
- * 3 AES Coprocessor
- * 4 DES Coprocessor
- * 5 HDLC Coprocessor
- * 6 AAL Coprocessor - Always available in IXP46X
- * 7 HSS Coprocesspr
- * 8 Utopia Coprocessor
- * 9 Ethernet 0 Coprocessor
- * 10 Ethernet 1 Coprocessor
- * 11 NPE A
- * 12 NPE B
- * 13 NPE C
- * 14 PCI Controller
- * 15 ECC/TimeSync Coprocessor - Only applicable to IXP46X
- * 16-17 Utopia PHY Limit Status : 0x0 - 32 PHY
- * 0x1 - 16 PHY
- * 0x2 - 8 PHY
- * 0x3 - 4 PHY
- *
- * Portions below are only applicable to IXP46X
- * 18 USB Host Coprocessor
- * 19 NPE A Ethernet - 0 for Enable if Utopia = 1
- * 20 NPE B Ethernet coprocessor 1-3.
- * 21 RSA Crypto Block coprocessor.
- * 22-23 Processor frequency : 0x0 - 533 MHz
- * 0x1 - 667 MHz
- * 0x2 - 400 MHz
- * 0x3 - 266 MHz
- * 24-31 Reserved
- *
- ************************************************************************/
-/*Section generic to both IXP42X and IXP46X*/
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @enum IxFeatureCtrlComponentType
- *
- * @brief Enumeration for components availavble
- *
- */
-typedef enum
-{
- IX_FEATURECTRL_RCOMP = 0, /**<bit location for RComp Circuitry*/
- IX_FEATURECTRL_USB, /**<bit location for USB Controller*/
- IX_FEATURECTRL_HASH, /**<bit location for Hashing Coprocessor*/
- IX_FEATURECTRL_AES, /**<bit location for AES Coprocessor*/
- IX_FEATURECTRL_DES, /**<bit location for DES Coprocessor*/
- IX_FEATURECTRL_HDLC, /**<bit location for HDLC Coprocessor*/
- IX_FEATURECTRL_AAL, /**<bit location for AAL Coprocessor*/
- IX_FEATURECTRL_HSS, /**<bit location for HSS Coprocessor*/
- IX_FEATURECTRL_UTOPIA, /**<bit location for UTOPIA Coprocessor*/
- IX_FEATURECTRL_ETH0, /**<bit location for Ethernet 0 Coprocessor*/
- IX_FEATURECTRL_ETH1, /**<bit location for Ethernet 1 Coprocessor*/
- IX_FEATURECTRL_NPEA, /**<bit location for NPE A*/
- IX_FEATURECTRL_NPEB, /**<bit location for NPE B*/
- IX_FEATURECTRL_NPEC, /**<bit location for NPE C*/
- IX_FEATURECTRL_PCI, /**<bit location for PCI Controller*/
- IX_FEATURECTRL_ECC_TIMESYNC, /**<bit location for TimeSync Coprocessor*/
- IX_FEATURECTRL_UTOPIA_PHY_LIMIT, /**<bit location for Utopia PHY Limit Status*/
- IX_FEATURECTRL_UTOPIA_PHY_LIMIT_BIT2, /**<2nd bit of PHY limit status*/
- IX_FEATURECTRL_USB_HOST_CONTROLLER, /**<bit location for USB host controller*/
- IX_FEATURECTRL_NPEA_ETH, /**<bit location for NPE-A Ethernet Disable*/
- IX_FEATURECTRL_NPEB_ETH, /**<bit location for NPE-B Ethernet 1-3 Coprocessors Disable*/
- IX_FEATURECTRL_RSA, /**<bit location for RSA Crypto block Coprocessors Disable*/
- IX_FEATURECTRL_XSCALE_MAX_FREQ, /**<bit location for XScale max frequency*/
- IX_FEATURECTRL_XSCALE_MAX_FREQ_BIT2, /**<2nd xscale max freq bit NOT TO BE USED */
- IX_FEATURECTRL_MAX_COMPONENTS
-} IxFeatureCtrlComponentType;
-
-/**
- * @ingroup IxFeatureCtrlDeviceId
- *
- * @enum IxFeatureCtrlDeviceId
- *
- * @brief Enumeration for device type.
- *
- * @warning This enum is closely related to the npe image. Its format should comply
- * with formats used in the npe image ImageID. This is indicated by the
- * first nibble of the image ID. This should also be in sync with the
- * with what is defined in CP15. Current available formats are
- * - IXP42X - 0000
- * - IXP46X - 0001
- *
- */
-typedef enum
-{
- IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X = 0, /**<Device type is IXP42X */
- IX_FEATURE_CTRL_DEVICE_TYPE_IXP46X, /**<Device type is IXP46X */
- IX_FEATURE_CTRL_DEVICE_TYPE_MAX /**<Max devices */
-} IxFeatureCtrlDeviceId;
-
-
-/**
- * @} addtogroup IxFeatureCtrlSwConfig
- */
-
-/*
- * Typedefs
- */
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @typedef IxFeatureCtrlReg
- *
- * @brief Feature Control Register that contains hardware components'
- * availability information.
- */
-typedef UINT32 IxFeatureCtrlReg;
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @typedef IxFeatureCtrlProductId
- *
- * @brief Product ID of Silicon that contains Silicon Stepping and
- * Maximum XScale Core Frequency information.
- */
-typedef UINT32 IxFeatureCtrlProductId;
-
-/*
- * Prototypes for interface functions
- */
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @fn IxFeatureCtrlReg ixFeatureCtrlRead (void)
- *
- * @brief This function reads out the CURRENT value of Feature Control Register.
- * The current value may not be the same as that of the hardware component
- * availability.
- *
- * The bit location of each hardware component is defined above.
- * A value of '1' in bit means the hardware component is not available. A value of '0'
- * means the hardware component is available.
- *
- * @return
- * - IxFeatureCtrlReg - the current value of IXP400 Feature Control Register
- */
-PUBLIC IxFeatureCtrlReg
-ixFeatureCtrlRead (void);
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @fn IxFeatureDeviceId ixFeatureCtrlDeviceRead (void)
- *
- * @brief This function gets the type of device that the software is currently running
- * on
- *
- * This function reads the feature Ctrl register specifically to obtain the device id.
- * The definitions of the avilable IDs are as above.
- *
- * @return
- * - IxFeatureCtrlDeviceId - the type of device currently running
- */
-IxFeatureCtrlDeviceId
-ixFeatureCtrlDeviceRead (void);
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @fn IxFeatureCtrlBuildDevice ixFeatureCtrlSoftwareBuildGet (void)
- *
- * @brief This function refers to the value set by the compiler flag to determine
- * the type of device the software is built for.
- *
- * The function reads the compiler flag to determine the device the software is
- * built for. When the user executes build in the command line,
- * a compile time flag (__ixp42X/__ixp46X is set. This API reads this
- * flag and returns the software build type to the calling client.
- *
- * @return
- * - IxFeatureCtrlBuildDevice - the type of device software is built for.
- */
-IxFeatureCtrlBuildDevice
-ixFeatureCtrlSoftwareBuildGet (void);
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @fn IxFeatureCtrlReg ixFeatureCtrlHwCapabilityRead (void)
- *
- * @brief This function reads out the hardware capability of a silicon type as defined in
- * feature control register.This value is different from that returned by
- * ixFeatureCtrlRead() because this function returns the actual hardware component
- * availability.
- *
- * The bit location of each hardware component is defined above.
- * A value of '1' in bit means the hardware component is not available. A value of '0'
- * means the hardware component is available.
- *
- * @return
- * - IxFeatureCtrlReg - the hardware capability of IXP400.
- *
- * @warning
- * - This function must not be called when IXP400 is running as the result
- * is undefined.
- */
-PUBLIC IxFeatureCtrlReg
-ixFeatureCtrlHwCapabilityRead (void);
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @fn void ixFeatureCtrlWrite (IxFeatureCtrlReg expUnitReg)
- *
- * @brief This function write the value stored in IxFeatureCtrlReg expUnitReg
- * to the Feature Control Register.
- *
- * The bit location of each hardware component is defined above.
- * The write is only effective on available hardware components. Writing '1' in a
- * bit will software disable the respective hardware component. A '0' will mean that
- * the hardware component will remain to be operable.
- *
- * @param expUnitReg @ref IxFeatureCtrlReg [in] - The value to be written to feature control
- * register.
- *
- * @return none
- *
- */
-PUBLIC void
-ixFeatureCtrlWrite (IxFeatureCtrlReg expUnitReg);
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @fn IX_STATUS ixFeatureCtrlComponentCheck (IxFeatureCtrlComponentType componentType)
- *
- * @brief This function will check the availability of hardware component specified
- * as componentType value.
- *
- * Usage Example:<br>
- * - if(IX_FEATURE_CTRL_COMPONENT_DISABLED !=
- * ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0)) <br>
- * - if(IX_FEATURE_CTRL_COMPONENT_ENABLED ==
- * ixFeatureCtrlComponentCheck(IX_FEATURECTRL_PCI)) <br>
- *
- * This function is typically called during component initialization time.
- *
- * @param componentType @ref IxFeatureCtrlComponentType [in] - the type of a component as
- * defined above as IX_FEATURECTRL_XXX (Exp: IX_FEATURECTRL_PCI, IX_FEATURECTRL_ETH0)
-
- *
- * @return
- * - IX_FEATURE_CTRL_COMPONENT_ENABLED if component is available
- * - IX_FEATURE_CTRL_COMPONENT_DISABLED if component is unavailable
- */
-PUBLIC IX_STATUS
-ixFeatureCtrlComponentCheck (IxFeatureCtrlComponentType componentType);
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @fn IxFeatureCtrlProductId ixFeatureCtrlProductIdRead (void)
- *
- * @brief This function will return IXP400 product ID i.e. CP15,
- * Register 0.
- *
- * @return
- * - IxFeatureCtrlProductId - the value of product ID.
- *
- */
-PUBLIC IxFeatureCtrlProductId
-ixFeatureCtrlProductIdRead (void) ;
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @fn IX_STATUS ixFeatureCtrlSwConfigurationCheck (IxFeatureCtrlSwConfig swConfigType)
- *
- * @brief This function checks whether the specified software configuration is
- * enabled or disabled.
- *
- * Usage Example:<br>
- * - if(IX_FEATURE_CTRL_SWCONFIG_DISABLED !=
- * ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING)) <br>
- * - if(IX_FEATURE_CTRL_SWCONFIG_ENABLED ==
- * ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING)) <br>
- *
- * This function is typically called during access component initialization time.
- *
- * @param swConfigType @ref IxFeatureCtrlSwConfig [in] - the type of a software configuration
- * defined in IxFeatureCtrlSwConfig enumeration.
- *
- * @return
- * - IX_FEATURE_CTRL_SWCONFIG_ENABLED if software configuration is enabled.
- * - IX_FEATURE_CTRL_SWCONFIG_DISABLED if software configuration is disabled.
- */
-PUBLIC IX_STATUS
-ixFeatureCtrlSwConfigurationCheck (IxFeatureCtrlSwConfig swConfigType);
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @fn void ixFeatureCtrlSwConfigurationWrite (IxFeatureCtrlSwConfig swConfigType, BOOL enabled)
- *
- * @brief This function enable/disable the specified software configuration.
- *
- * Usage Example:<br>
- * - ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, TRUE) is used
- * to enable Ethernet Learning Feature <br>
- * - ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, FALSE) is used
- * to disable Ethernet Learning Feature <br>
- *
- * @param swConfigType IxFeatureCtrlSwConfig [in] - the type of a software configuration
- * defined in IxFeatureCtrlSwConfig enumeration.
- * @param enabled BOOL [in] - To enable(TRUE) / disable (FALSE) the specified software
- * configuration.
- *
- * @return none
- *
- */
-PUBLIC void
-ixFeatureCtrlSwConfigurationWrite (IxFeatureCtrlSwConfig swConfigType, BOOL enabled);
-
-/**
- * @ingroup IxFeatureCtrlAPI
- *
- * @fn void ixFeatureCtrlIxp400SwVersionShow (void)
- *
- * @brief This function shows the current software release information for IXP400
- *
- * @return none
- *
- */
-PUBLIC void
-ixFeatureCtrlIxp400SwVersionShow (void);
-
-#endif /* IXFEATURECTRL_H */
-
-/**
- * @} defgroup IxFeatureCtrlAPI
- */
+++ /dev/null
-/**
- * @file IxHssAcc.h
- *
- * @date 07-DEC-2001
- *
- * @brief This file contains the public API of the IXP400 HSS Access
- * component
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-/* ------------------------------------------------------
- Doxygen group definitions
- ------------------------------------------------------ */
-/**
- * @defgroup IxHssAccAPI IXP400 HSS Access (IxHssAcc) API
- *
- * @brief The public API for the IXP400 HssAccess component
- *
- * IxHssAcc is the access layer to the HSS packetised and channelised
- * services
- *
- * <b> Design Notes </b><br>
- * <UL>
- * <LI>When a packet-pipe is configured for 56Kbps RAW mode, byte alignment of
- * the transmitted data is not preserved. All raw data that is transmitted
- * will be received in proper order by the receiver, but the first bit of
- * the packet may be seen at any offset within a byte; all subsequent bytes
- * will have the same offset for the duration of the packet. The same offset
- * also applies to all subsequent packets received on the packet-pipe too.
- * (Similar results will occur for data received from remote end.) While
- * this behavior will also occur for 56Kbps HDLC mode, the HDLC
- * encoding/decoding will preserve the original byte alignment at the
- * receiver end.
- * </UL>
- *
- * <b> 56Kbps Packetised Service Bandwidth Limitation </b><br>
- * <UL>
- * <LI>IxHssAcc supports 56Kbps packetised service at a maximum aggregate rate
- * for all HSS ports/HDLC channels of 12.288Mbps[1] in each direction, i.e.
- * it supports 56Kbps packetised service on up to 8 T1 trunks. It does
- * not support 56Kbps packetised service on 8 E1 trunks (i.e. 4 trunks per
- * HSS port) unless those trunks are running 'fractional E1' with maximum
- * aggregate rate of 12.288 Mbps in each direction.<br>
- * [1] 12.288Mbps = 1.536Mbp * 8 T1
- * </UL>
- * @{ */
-
-#ifndef IXHSSACC_H
-#define IXHSSACC_H
-
-#include "IxOsal.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-/**
- * @def IX_HSSACC_TSLOTS_PER_HSS_PORT
- *
- * @brief The max number of TDM timeslots supported per HSS port - 4E1's =
- * 32x4 = 128
- */
-#define IX_HSSACC_TSLOTS_PER_HSS_PORT 128
-
-/* -----------------------------------------------------------
- The following are HssAccess return values returned through
- service interfaces. The globally defined IX_SUCCESS (0) and
- IX_FAIL (1) in IxOsalTypes.h are also used.
- ----------------------------------------------------------- */
-/**
- * @def IX_HSSACC_PARAM_ERR
- *
- * @brief HssAccess function return value for a parameter error
- */
-#define IX_HSSACC_PARAM_ERR 2
-
-/**
- * @def IX_HSSACC_RESOURCE_ERR
- *
- * @brief HssAccess function return value for a resource error
- */
-#define IX_HSSACC_RESOURCE_ERR 3
-
-/**
- * @def IX_HSSACC_PKT_DISCONNECTING
- *
- * @brief Indicates that a disconnect call is progressing and will
- * disconnect soon
- */
-#define IX_HSSACC_PKT_DISCONNECTING 4
-
-/**
- * @def IX_HSSACC_Q_WRITE_OVERFLOW
- *
- * @brief Indicates that an attempt to Tx or to replenish an
- * RxFree Q failed due to Q overflow.
- */
-#define IX_HSSACC_Q_WRITE_OVERFLOW 5
-
-/* -------------------------------------------------------------------
- The following errors are HSS/NPE errors returned on error retrieval
- ------------------------------------------------------------------- */
-/**
- * @def IX_HSSACC_NO_ERROR
- *
- * @brief HSS port no error present
- */
-#define IX_HSSACC_NO_ERROR 0
-
-/**
- * @def IX_HSSACC_TX_FRM_SYNC_ERR
- *
- * @brief HSS port TX Frame Sync error
- */
-#define IX_HSSACC_TX_FRM_SYNC_ERR 1
-
-/**
- * @def IX_HSSACC_TX_OVER_RUN_ERR
- *
- * @brief HSS port TX over-run error
- */
-#define IX_HSSACC_TX_OVER_RUN_ERR 2
-
-/**
- * @def IX_HSSACC_CHANNELISED_SW_TX_ERR
- *
- * @brief NPE software error in channelised TX
- */
-#define IX_HSSACC_CHANNELISED_SW_TX_ERR 3
-
-/**
- * @def IX_HSSACC_PACKETISED_SW_TX_ERR
- *
- * @brief NPE software error in packetised TX
- */
-#define IX_HSSACC_PACKETISED_SW_TX_ERR 4
-
-/**
- * @def IX_HSSACC_RX_FRM_SYNC_ERR
- *
- * @brief HSS port RX Frame Sync error
- */
-#define IX_HSSACC_RX_FRM_SYNC_ERR 5
-
-/**
- * @def IX_HSSACC_RX_OVER_RUN_ERR
- *
- * @brief HSS port RX over-run error
- */
-#define IX_HSSACC_RX_OVER_RUN_ERR 6
-
-/**
- * @def IX_HSSACC_CHANNELISED_SW_RX_ERR
- *
- * @brief NPE software error in channelised RX
- */
-#define IX_HSSACC_CHANNELISED_SW_RX_ERR 7
-
-/**
- * @def IX_HSSACC_PACKETISED_SW_RX_ERR
- *
- * @brief NPE software error in packetised TX
- */
-#define IX_HSSACC_PACKETISED_SW_RX_ERR 8
-
-/* -----------------------------------
- Packetised service specific defines
- ----------------------------------- */
-
-/**
- * @def IX_HSSACC_PKT_MIN_RX_MBUF_SIZE
- *
- * @brief Minimum size of the Rx mbuf in bytes which the client must supply
- * to the component.
- */
-#define IX_HSSACC_PKT_MIN_RX_MBUF_SIZE 64
-
-/* --------------------------------------------------------------------
- Enumerated Types - these enumerated values may be used in setting up
- the contents of hardware registers
- -------------------------------------------------------------------- */
-/**
- * @enum IxHssAccHssPort
- * @brief The HSS port ID - There are two identical ports (0-1).
- *
- */
-typedef enum
-{
- IX_HSSACC_HSS_PORT_0, /**< HSS Port 0 */
- IX_HSSACC_HSS_PORT_1, /**< HSS Port 1 */
- IX_HSSACC_HSS_PORT_MAX /**< Delimiter for error checks */
-} IxHssAccHssPort;
-
-/**
- * @enum IxHssAccHdlcPort
- * @brief The HDLC port ID - There are four identical HDLC ports (0-3) per
- * HSS port and they correspond to the 4 E1/T1 trunks.
- *
- */
-typedef enum
-{
- IX_HSSACC_HDLC_PORT_0, /**< HDLC Port 0 */
- IX_HSSACC_HDLC_PORT_1, /**< HDLC Port 1 */
- IX_HSSACC_HDLC_PORT_2, /**< HDLC Port 2 */
- IX_HSSACC_HDLC_PORT_3, /**< HDLC Port 3 */
- IX_HSSACC_HDLC_PORT_MAX /**< Delimiter for error checks */
-} IxHssAccHdlcPort;
-
-/**
- * @enum IxHssAccTdmSlotUsage
- * @brief The HSS TDM stream timeslot assignment types
- *
- */
-typedef enum
-{
- IX_HSSACC_TDMMAP_UNASSIGNED, /**< Unassigned */
- IX_HSSACC_TDMMAP_HDLC, /**< HDLC - packetised */
- IX_HSSACC_TDMMAP_VOICE56K, /**< Voice56K - channelised */
- IX_HSSACC_TDMMAP_VOICE64K, /**< Voice64K - channelised */
- IX_HSSACC_TDMMAP_MAX /**< Delimiter for error checks */
-} IxHssAccTdmSlotUsage;
-
-/**
- * @enum IxHssAccFrmSyncType
- * @brief The HSS frame sync pulse type
- *
- */
-typedef enum
-{
- IX_HSSACC_FRM_SYNC_ACTIVE_LOW, /**< Frame sync is sampled low */
- IX_HSSACC_FRM_SYNC_ACTIVE_HIGH, /**< sampled high */
- IX_HSSACC_FRM_SYNC_FALLINGEDGE, /**< sampled on a falling edge */
- IX_HSSACC_FRM_SYNC_RISINGEDGE, /**< sampled on a rising edge */
- IX_HSSACC_FRM_SYNC_TYPE_MAX /**< Delimiter for error checks */
-} IxHssAccFrmSyncType;
-
-/**
- * @enum IxHssAccFrmSyncEnable
- * @brief The IxHssAccFrmSyncEnable determines how the frame sync pulse is
- * used
- * */
-typedef enum
-{
- IX_HSSACC_FRM_SYNC_INPUT, /**< Frame sync is sampled as an input */
- IX_HSSACC_FRM_SYNC_INVALID_VALUE, /**< 1 is not used */
- IX_HSSACC_FRM_SYNC_OUTPUT_FALLING, /**< Frame sync is an output generated
- off a falling clock edge */
- IX_HSSACC_FRM_SYNC_OUTPUT_RISING, /**< Frame sync is an output generated
- off a rising clock edge */
- IX_HSSACC_FRM_SYNC_ENABLE_MAX /**< Delimiter for error checks */
-} IxHssAccFrmSyncEnable;
-
-/**
- * @enum IxHssAccClkEdge
- * @brief IxHssAccClkEdge is used to determine the clk edge to use for
- * framing and data
- *
- */
-typedef enum
-{
- IX_HSSACC_CLK_EDGE_FALLING, /**< Clock sampled off a falling edge */
- IX_HSSACC_CLK_EDGE_RISING, /**< Clock sampled off a rising edge */
- IX_HSSACC_CLK_EDGE_MAX /**< Delimiter for error checks */
-} IxHssAccClkEdge;
-
-/**
- * @enum IxHssAccClkDir
- * @brief The HSS clock direction
- *
- */
-typedef enum
-{
- IX_HSSACC_SYNC_CLK_DIR_INPUT, /**< Clock is an input */
- IX_HSSACC_SYNC_CLK_DIR_OUTPUT, /**< Clock is an output */
- IX_HSSACC_SYNC_CLK_DIR_MAX /**< Delimiter for error checks */
-} IxHssAccClkDir;
-
-/**
- * @enum IxHssAccFrmPulseUsage
- * @brief The HSS frame pulse usage
- *
- */
-typedef enum
-{
- IX_HSSACC_FRM_PULSE_ENABLED, /**< Generate/Receive frame pulses */
- IX_HSSACC_FRM_PULSE_DISABLED, /**< Disregard frame pulses */
- IX_HSSACC_FRM_PULSE_MAX /**< Delimiter for error checks */
-} IxHssAccFrmPulseUsage;
-
-/**
- * @enum IxHssAccDataRate
- * @brief The HSS Data rate in relation to the clock
- *
- */
-typedef enum
-{
- IX_HSSACC_CLK_RATE, /**< Data rate is at the configured clk speed */
- IX_HSSACC_HALF_CLK_RATE, /**< Data rate is half the configured clk speed */
- IX_HSSACC_DATA_RATE_MAX /**< Delimiter for error checks */
-} IxHssAccDataRate;
-
-/**
- * @enum IxHssAccDataPolarity
- * @brief The HSS data polarity type
- *
- */
-typedef enum
-{
- IX_HSSACC_DATA_POLARITY_SAME, /**< Don't invert data between NPE and
- HSS FIFOs */
- IX_HSSACC_DATA_POLARITY_INVERT, /**< Invert data between NPE and HSS
- FIFOs */
- IX_HSSACC_DATA_POLARITY_MAX /**< Delimiter for error checks */
-} IxHssAccDataPolarity;
-
-/**
- * @enum IxHssAccBitEndian
- * @brief HSS Data endianness
- *
- */
-typedef enum
-{
- IX_HSSACC_LSB_ENDIAN, /**< TX/RX Least Significant Bit first */
- IX_HSSACC_MSB_ENDIAN, /**< TX/RX Most Significant Bit first */
- IX_HSSACC_ENDIAN_MAX /**< Delimiter for the purposes of error checks */
-} IxHssAccBitEndian;
-
-
-/**
- * @enum IxHssAccDrainMode
- * @brief Tx pin open drain mode
- *
- */
-typedef enum
-{
- IX_HSSACC_TX_PINS_NORMAL, /**< Normal mode */
- IX_HSSACC_TX_PINS_OPEN_DRAIN, /**< Open Drain mode */
- IX_HSSACC_TX_PINS_MAX /**< Delimiter for error checks */
-} IxHssAccDrainMode;
-
-/**
- * @enum IxHssAccSOFType
- * @brief HSS start of frame types
- *
- */
-typedef enum
-{
- IX_HSSACC_SOF_FBIT, /**< Framing bit transmitted and expected on rx */
- IX_HSSACC_SOF_DATA, /**< Framing bit not transmitted nor expected on rx */
- IX_HSSACC_SOF_MAX /**< Delimiter for error checks */
-} IxHssAccSOFType;
-
-/**
- * @enum IxHssAccDataEnable
- * @brief IxHssAccDataEnable is used to determine whether or not to drive
- * the data pins
- *
- */
-typedef enum
-{
- IX_HSSACC_DE_TRI_STATE, /**< TRI-State the data pins */
- IX_HSSACC_DE_DATA, /**< Push data out the data pins */
- IX_HSSACC_DE_MAX /**< Delimiter for error checks */
-} IxHssAccDataEnable;
-
-/**
- * @enum IxHssAccTxSigType
- * @brief IxHssAccTxSigType is used to determine how to drive the data pins
- *
- */
-typedef enum
-{
- IX_HSSACC_TXSIG_LOW, /**< Drive the data pins low */
- IX_HSSACC_TXSIG_HIGH, /**< Drive the data pins high */
- IX_HSSACC_TXSIG_HIGH_IMP, /**< Drive the data pins with high impedance */
- IX_HSSACC_TXSIG_MAX /**< Delimiter for error checks */
-} IxHssAccTxSigType;
-
-/**
- * @enum IxHssAccFbType
- * @brief IxHssAccFbType determines how to drive the Fbit
- *
- * @warning This will only be used for T1 @ 1.544MHz
- *
- */
-typedef enum
-{
- IX_HSSACC_FB_FIFO, /**< Fbit is dictated in FIFO */
- IX_HSSACC_FB_HIGH_IMP, /**< Fbit is high impedance */
- IX_HSSACC_FB_MAX /**< Delimiter for error checks */
-} IxHssAccFbType;
-
-/**
- * @enum IxHssAcc56kEndianness
- * @brief 56k data endianness when using the 56k type
- *
- */
-typedef enum
-{
- IX_HSSACC_56KE_BIT_7_UNUSED, /**< High bit is unused */
- IX_HSSACC_56KE_BIT_0_UNUSED, /**< Low bit is unused */
- IX_HSSACC_56KE_MAX /**< Delimiter for error checks */
-} IxHssAcc56kEndianness;
-
-/**
- * @enum IxHssAcc56kSel
- * @brief 56k data transmission type when using the 56k type
- *
- */
-typedef enum
-{
- IX_HSSACC_56KS_32_8_DATA, /**< 32/8 bit data */
- IX_HSSACC_56KS_56K_DATA, /**< 56K data */
- IX_HSSACC_56KS_MAX /**< Delimiter for error checks */
-} IxHssAcc56kSel;
-
-
-/**
- * @enum IxHssAccClkSpeed
- * @brief IxHssAccClkSpeed represents the HSS clock speeds available
- *
- */
-typedef enum
-{
- IX_HSSACC_CLK_SPEED_512KHZ, /**< 512KHz */
- IX_HSSACC_CLK_SPEED_1536KHZ, /**< 1.536MHz */
- IX_HSSACC_CLK_SPEED_1544KHZ, /**< 1.544MHz */
- IX_HSSACC_CLK_SPEED_2048KHZ, /**< 2.048MHz */
- IX_HSSACC_CLK_SPEED_4096KHZ, /**< 4.096MHz */
- IX_HSSACC_CLK_SPEED_8192KHZ, /**< 8.192MHz */
- IX_HSSACC_CLK_SPEED_MAX /**< Delimiter for error checking */
-} IxHssAccClkSpeed;
-
-/**
- * @enum IxHssAccPktStatus
- * @brief Indicates the status of packets passed to the client
- *
- */
-typedef enum
-{
- IX_HSSACC_PKT_OK, /**< Error free.*/
- IX_HSSACC_STOP_SHUTDOWN_ERROR, /**< Errored due to stop or shutdown
- occurrance.*/
- IX_HSSACC_HDLC_ALN_ERROR, /**< HDLC alignment error */
- IX_HSSACC_HDLC_FCS_ERROR, /**< HDLC Frame Check Sum error.*/
- IX_HSSACC_RXFREE_Q_EMPTY_ERROR, /**< RxFree Q became empty
- while receiving this packet.*/
- IX_HSSACC_HDLC_MAX_FRAME_SIZE_EXCEEDED, /**< HDLC frame size
- received is greater than
- max specified at connect.*/
- IX_HSSACC_HDLC_ABORT_ERROR, /**< HDLC frame received is invalid due to an
- abort sequence received.*/
- IX_HSSACC_DISCONNECT_IN_PROGRESS /**< Packet returned
- because a disconnect is in progress */
-} IxHssAccPktStatus;
-
-
-/**
- * @enum IxHssAccPktCrcType
- * @brief HDLC CRC type
- *
- */
-typedef enum
-{
- IX_HSSACC_PKT_16_BIT_CRC = 16, /**< 16 bit CRC is being used */
- IX_HSSACC_PKT_32_BIT_CRC = 32 /**< 32 bit CRC is being used */
-} IxHssAccPktCrcType;
-
-/**
- * @enum IxHssAccPktHdlcIdleType
- * @brief HDLC idle transmission type
- *
- */
-typedef enum
-{
- IX_HSSACC_HDLC_IDLE_ONES, /**< idle tx/rx will be a succession of ones */
- IX_HSSACC_HDLC_IDLE_FLAGS /**< idle tx/rx will be repeated flags */
-} IxHssAccPktHdlcIdleType;
-
-/**
- * @brief Structure containing HSS port configuration parameters
- *
- * Note: All of these are used for TX. Only some are specific to RX.
- *
- */
-typedef struct
-{
- IxHssAccFrmSyncType frmSyncType; /**< frame sync pulse type (tx/rx) */
- IxHssAccFrmSyncEnable frmSyncIO; /**< how the frame sync pulse is
- used (tx/rx) */
- IxHssAccClkEdge frmSyncClkEdge; /**< frame sync clock edge type
- (tx/rx) */
- IxHssAccClkEdge dataClkEdge; /**< data clock edge type (tx/rx) */
- IxHssAccClkDir clkDirection; /**< clock direction (tx/rx) */
- IxHssAccFrmPulseUsage frmPulseUsage; /**< whether to use the frame sync
- pulse or not (tx/rx) */
- IxHssAccDataRate dataRate; /**< data rate in relation to the
- clock (tx/rx) */
- IxHssAccDataPolarity dataPolarity; /**< data polarity type (tx/rx) */
- IxHssAccBitEndian dataEndianness; /**< data endianness (tx/rx) */
- IxHssAccDrainMode drainMode; /**< tx pin open drain mode (tx) */
- IxHssAccSOFType fBitUsage; /**< start of frame types (tx/rx) */
- IxHssAccDataEnable dataEnable; /**< whether or not to drive the data
- pins (tx) */
- IxHssAccTxSigType voice56kType; /**< how to drive the data pins for
- voice56k type (tx) */
- IxHssAccTxSigType unassignedType; /**< how to drive the data pins for
- unassigned type (tx) */
- IxHssAccFbType fBitType; /**< how to drive the Fbit (tx) */
- IxHssAcc56kEndianness voice56kEndian;/**< 56k data endianness when using
- the 56k type (tx) */
- IxHssAcc56kSel voice56kSel; /**< 56k data transmission type when
- using the 56k type (tx) */
- unsigned frmOffset; /**< frame pulse offset in bits wrt
- the first timeslot (0-1023) (tx/rx) */
- unsigned maxFrmSize; /**< frame size in bits (1-1024)
- (tx/rx) */
-} IxHssAccPortConfig;
-
-/**
- * @brief Structure containing HSS configuration parameters
- *
- */
-typedef struct
-{
- IxHssAccPortConfig txPortConfig; /**< HSS tx port configuration */
- IxHssAccPortConfig rxPortConfig; /**< HSS rx port configuration */
- unsigned numChannelised; /**< The number of channelised
- timeslots (0-32) */
- unsigned hssPktChannelCount; /**< The number of packetised
- clients (0 - 4) */
- UINT8 channelisedIdlePattern; /**< The byte to be transmitted on
- channelised service when there
- is no client data to tx */
- BOOL loopback; /**< The HSS loopback state */
- unsigned packetizedIdlePattern; /**< The data to be transmitted on
- packetised service when there is
- no client data to tx */
- IxHssAccClkSpeed clkSpeed; /**< The HSS clock speed */
-} IxHssAccConfigParams;
-
-/**
- * @brief This structure contains 56Kbps, HDLC-mode configuration parameters
- *
- */
-typedef struct
-{
- BOOL hdlc56kMode; /**< 56kbps(TRUE)/64kbps(FALSE) HDLC */
- IxHssAcc56kEndianness hdlc56kEndian; /**< 56kbps data endianness
- - ignored if hdlc56kMode is FALSE*/
- BOOL hdlc56kUnusedBitPolarity0; /**< The polarity '0'(TRUE)/'1'(FALSE) of the unused
- bit while in 56kbps mode
- - ignored if hdlc56kMode is FALSE*/
-} IxHssAccHdlcMode;
-
-/**
- * @brief This structure contains information required by the NPE to
- * configure the HDLC co-processor
- *
- */
-typedef struct
-{
- IxHssAccPktHdlcIdleType hdlcIdleType; /**< What to transmit when a HDLC port is idle */
- IxHssAccBitEndian dataEndian; /**< The HDLC data endianness */
- IxHssAccPktCrcType crcType; /**< The CRC type to be used for this HDLC port */
-} IxHssAccPktHdlcFraming;
-
-/**
- * @typedef UINT32 IxHssAccPktUserId
- *
- * @brief The client supplied value which will be supplied as a parameter
- * with a given callback.
- *
- * This value will be passed into the ixHssAccPktPortConnect function once each
- * with given callbacks. This value will then be passed back to the client
- * as one of the parameters to each of these callbacks,
- * when these callbacks are called.
- */
-typedef UINT32 IxHssAccPktUserId;
-
-
-/**
- * @typedef IxHssAccLastErrorCallback
- * @brief Prototype of the clients function to accept notification of the
- * last error
- *
- * This function is registered through the config. The client will initiate
- * the last error retrieval. The HssAccess component will send a message to
- * the NPE through the NPE Message Handler. When a response to the read is
- * received, the NPE Message Handler will callback the HssAccess component
- * which will execute this function in the same IxNpeMh context. The client
- * will be passed the last error and the related service port (packetised
- * 0-3, channelised 0)
- *
- * @param lastHssError unsigned [in] - The last Hss error registered that
- * has been registered.
- * @param servicePort unsigned [in] - This is the service port number.
- * (packetised 0-3, channelised 0)
- *
- * @return void
- */
-typedef void (*IxHssAccLastErrorCallback) (unsigned lastHssError,
- unsigned servicePort);
-
-/**
- * @typedef IxHssAccPktRxCallback
- * @brief Prototype of the clients function to accept notification of
- * packetised rx
- *
- * This function is registered through the ixHssAccPktPortConnect. hssPktAcc will pass
- * received data in the form of mbufs to the client. The mbuf passed back
- * to the client could contain a chain of buffers, depending on the packet
- * size received.
- *
- * @param *buffer @ref IX_OSAL_MBUF [in] - This is the mbuf which contains the
- * payload received.
- * @param numHssErrs unsigned [in] - This is the number of hssErrors
- * the Npe has received
- * @param pktStatus @ref IxHssAccPktStatus [in] - This is the status of the
- * mbuf that has been received.
- * @param rxUserId @ref IxHssAccPktUserId [in] - This is the client supplied value
- * passed in at ixHssAccPktPortConnect time which is now returned to the client.
- *
- * @return void
- */
-typedef void (*IxHssAccPktRxCallback) (IX_OSAL_MBUF *buffer,
- unsigned numHssErrs,
- IxHssAccPktStatus pktStatus,
- IxHssAccPktUserId rxUserId);
-
-/**
- * @typedef IxHssAccPktRxFreeLowCallback
- * @brief Prototype of the clients function to accept notification of
- * requirement of more Rx Free buffers
- *
- * The client can choose to register a callback of this type when
- * calling a connecting. This function is registered through the ixHssAccPktPortConnect.
- * If defined, the access layer will provide the trigger for
- * this callback. The callback will be responsible for supplying mbufs to
- * the access layer for use on the receive path from the HSS using
- * ixHssPktAccFreeBufReplenish.
- *
- * @return void
- */
-typedef void (*IxHssAccPktRxFreeLowCallback) (IxHssAccPktUserId rxFreeLowUserId);
-
-/**
- * @typedef IxHssAccPktTxDoneCallback
- * @brief Prototype of the clients function to accept notification of
- * completion with Tx buffers
- *
- * This function is registered through the ixHssAccPktPortConnect. It enables
- * the hssPktAcc to pass buffers back to the client
- * when transmission is complete.
- *
- * @param *buffer @ref IX_OSAL_MBUF [in] - This is the mbuf which contained
- * the payload that was for Tx.
- * @param numHssErrs unsigned [in] - This is the number of hssErrors
- * the Npe has received
- * @param pktStatus @ref IxHssAccPktStatus [in] - This is the status of the
- * mbuf that has been transmitted.
- * @param txDoneUserId @ref IxHssAccPktUserId [in] - This is the client supplied value
- * passed in at ixHssAccPktPortConnect time which is now returned to the client.
- *
- * @return void
- */
-typedef void (*IxHssAccPktTxDoneCallback) (IX_OSAL_MBUF *buffer,
- unsigned numHssErrs,
- IxHssAccPktStatus pktStatus,
- IxHssAccPktUserId txDoneUserId);
-
-/**
- * @typedef IxHssAccChanRxCallback
- * @brief Prototype of the clients function to accept notification of
- * channelised rx
- *
- * This callback, if defined by the client in the connect, will get called
- * in the context of an IRQ. The IRQ will be triggered when the hssSyncQMQ
- * is not empty. The queued entry will be dequeued and this function will
- * be executed.
- *
- * @param hssPortId @ref IxHssAccHssPort - The HSS port Id. There are two
- * identical ports (0-1).
- * @param txOffset unsigned [in] - an offset indicating from where within
- * the txPtrList the NPE is currently transmitting from.
- * @param rxOffset unsigned [in] - an offset indicating where within the
- * receive buffers the NPE has just written the received data to.
- * @param numHssErrs unsigned [in] - This is the number of hssErrors
- * the Npe has received
- *
- * @return void
- */
-typedef void (*IxHssAccChanRxCallback) (IxHssAccHssPort hssPortId,
- unsigned rxOffset,
- unsigned txOffset,
- unsigned numHssErrs);
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccPortInit (IxHssAccHssPort hssPortId,
- IxHssAccConfigParams *configParams,
- IxHssAccTdmSlotUsage *tdmMap,
- IxHssAccLastErrorCallback lastHssErrorCallback)
- *
- * @brief Initialise a HSS port. No channelised or packetised connections
- * should exist in the HssAccess layer while this interface is being called.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1).
- * @param *configParams @ref IxHssAccConfigParams [in] - A pointer to the HSS
- * configuration structure
- * @param *tdmMap @ref IxHssAccTdmSlotUsage [in] - A pointer to an array of size
- * IX_HSSACC_TSLOTS_PER_HSS_PORT, defining the slot usage over the HSS port
- * @param lastHssErrorCallback @ref IxHssAccLastErrorCallback [in] - Client
- * callback to report last error
- *
- * @return
- * - IX_SUCCESS The function executed successfully
- * - IX_FAIL The function did not execute successfully
- * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- * parameter error
- */
-PUBLIC IX_STATUS
-ixHssAccPortInit (IxHssAccHssPort hssPortId,
- IxHssAccConfigParams *configParams,
- IxHssAccTdmSlotUsage *tdmMap,
- IxHssAccLastErrorCallback lastHssErrorCallback);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccLastErrorRetrievalInitiate (
- IxHssAccHssPort hssPortId)
- *
- * @brief Initiate the retrieval of the last HSS error. The HSS port
- * should be configured before attempting to call this interface.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - the HSS port ID
- *
- * @return
- * - IX_SUCCESS The function executed successfully
- * - IX_FAIL The function did not execute successfully
- * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- * parameter error
- */
-PUBLIC IX_STATUS
-ixHssAccLastErrorRetrievalInitiate (IxHssAccHssPort hssPortId);
-
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccInit ()
- *
- * @brief This function is responsible for initialising resources for use
- * by the packetised and channelised clients. It should be called after
- * HSS NPE image has been downloaded into NPE-A and before any other
- * HssAccess interface is called.
- * No other HssAccPacketised interface should be called while this interface
- * is being processed.
- *
- * @return
- * - IX_SUCCESS The function executed successfully
- * - IX_FAIL The function did not execute successfully
- * - IX_HSSACC_RESOURCE_ERR The function did not execute successfully due
- * to a resource error
- */
-PUBLIC IX_STATUS
-ixHssAccInit (void);
-
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn ixHssAccPktPortConnect (IxHssAccHssPort hssPortId,
- IxHssAccHdlcPort hdlcPortId,
- BOOL hdlcFraming,
- IxHssAccHdlcMode hdlcMode,
- BOOL hdlcBitInvert,
- unsigned blockSizeInWords,
- UINT32 rawIdleBlockPattern,
- IxHssAccPktHdlcFraming hdlcTxFraming,
- IxHssAccPktHdlcFraming hdlcRxFraming,
- unsigned frmFlagStart,
- IxHssAccPktRxCallback rxCallback,
- IxHssAccPktUserId rxUserId,
- IxHssAccPktRxFreeLowCallback rxFreeLowCallback,
- IxHssAccPktUserId rxFreeLowUserId,
- IxHssAccPktTxDoneCallback txDoneCallback,
- IxHssAccPktUserId txDoneUserId)
- *
- * @brief This function is responsible for connecting a client to one of
- * the 4 available HDLC ports. The HSS port should be configured before
- * attempting a connect. No other HssAccPacketised interface should be
- * called while this connect is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1).
- * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port and
- * it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3
- * @param hdlcFraming BOOL [in] - This value determines whether the service
- * will use HDLC data or the debug, raw data type i.e. no HDLC processing
- * @param hdlcMode @ref IxHssAccHdlcMode [in] - This structure contains 56Kbps, HDLC-mode
- * configuration parameters
- * @param hdlcBitInvert BOOL [in] - This value determines whether bit inversion
- * will occur between HDLC and HSS co-processors i.e. post-HDLC processing for
- * transmit and pre-HDLC processing for receive, for the specified HDLC Termination
- * Point
- * @param blockSizeInWords unsigned [in] - The max tx/rx block size
- * @param rawIdleBlockPattern UINT32 [in] - Tx idle pattern in raw mode
- * @param hdlcTxFraming @ref IxHssAccPktHdlcFraming [in] - This structure contains
- * the following information required by the NPE to configure the HDLC
- * co-processor for TX
- * @param hdlcRxFraming @ref IxHssAccPktHdlcFraming [in] - This structure contains
- * the following information required by the NPE to configure the HDLC
- * co-processor for RX
- * @param frmFlagStart unsigned - Number of flags to precede to
- * transmitted flags (0-2).
- * @param rxCallback @ref IxHssAccPktRxCallback [in] - Pointer to
- * the clients packet receive function.
- * @param rxUserId @ref IxHssAccPktUserId [in] - The client supplied rx value
- * to be passed back as an argument to the supplied rxCallback
- * @param rxFreeLowCallback @ref IxHssAccPktRxFreeLowCallback [in] - Pointer to
- * the clients Rx free buffer request function. If NULL, assume client will
- * trigger independently.
- * @param rxFreeLowUserId @ref IxHssAccPktUserId [in] - The client supplied RxFreeLow value
- * to be passed back as an argument to the supplied rxFreeLowCallback
- * @param txDoneCallback @ref IxHssAccPktTxDoneCallback [in] - Pointer to the
- * clients Tx done callback function
- * @param txDoneUserId @ref IxHssAccPktUserId [in] - The client supplied txDone value
- * to be passed back as an argument to the supplied txDoneCallback
- *
- * @return
- * - IX_SUCCESS The function executed successfully
- * - IX_FAIL The function did not execute successfully
- * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- * parameter error
- * - IX_HSSACC_RESOURCE_ERR The function did not execute successfully due
- * to a resource error
- */
-PUBLIC IX_STATUS
-ixHssAccPktPortConnect (IxHssAccHssPort hssPortId,
- IxHssAccHdlcPort hdlcPortId,
- BOOL hdlcFraming,
- IxHssAccHdlcMode hdlcMode,
- BOOL hdlcBitInvert,
- unsigned blockSizeInWords,
- UINT32 rawIdleBlockPattern,
- IxHssAccPktHdlcFraming hdlcTxFraming,
- IxHssAccPktHdlcFraming hdlcRxFraming,
- unsigned frmFlagStart,
- IxHssAccPktRxCallback rxCallback,
- IxHssAccPktUserId rxUserId,
- IxHssAccPktRxFreeLowCallback rxFreeLowCallback,
- IxHssAccPktUserId rxFreeLowUserId,
- IxHssAccPktTxDoneCallback txDoneCallback,
- IxHssAccPktUserId txDoneUserId);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccPktPortEnable (IxHssAccHssPort hssPortId,
- IxHssAccHdlcPort hdlcPortId)
- *
- * @brief This function is responsible for enabling a packetised service
- * for the specified HSS/HDLC port combination. It enables the RX flow. The
- * client must have already connected to a packetised service and is responsible
- * for ensuring an adequate amount of RX mbufs have been supplied to the access
- * component before enabling the packetised service. This function must be called
- * on a given port before any call to ixHssAccPktPortTx on the same port.
- * No other HssAccPacketised interface should be called while this interface is
- * being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1).
- * @param hdlcPortId @ref IxHssAccHdlcPort [in] - The port id (0,1,2,3) to enable the service
- * on.
- *
- * @return
- * - IX_SUCCESS The function executed successfully
- * - IX_FAIL The function did not execute successfully
- * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- * parameter error
- */
-PUBLIC IX_STATUS
-ixHssAccPktPortEnable (IxHssAccHssPort hssPortId,
- IxHssAccHdlcPort hdlcPortId);
-
-/**
- * @fn IX_STATUS ixHssAccPktPortDisable (IxHssAccHssPort hssPortId,
- IxHssAccHdlcPort hdlcPortId)
- *
- * @brief This function is responsible for disabling a packetised service
- * for the specified HSS/HDLC port combination. It disables the RX flow.
- * The client must have already connected to and enabled a packetised service
- * for the specified HDLC port. This disable interface can be called before a
- * disconnect, but is not required to.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1).
- * @param hdlcPortId @ref IxHssAccHdlcPort [in] - The port id (0,1,2,3) to disable
- * the service on.
- *
- * @return
- * - IX_SUCCESS The function executed successfully
- * - IX_FAIL The function did not execute successfully
- * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- * parameter error
- */
-PUBLIC IX_STATUS
-ixHssAccPktPortDisable (IxHssAccHssPort hssPortId,
- IxHssAccHdlcPort hdlcPortId);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccPktPortDisconnect (IxHssAccHssPort hssPortId,
- IxHssAccHdlcPort hdlcPortId)
- *
- * @brief This function is responsible for disconnecting a client from one
- * of the 4 available HDLC ports. It is not required that the Rx Flow
- * has been disabled before calling this function. If the RX Flow has not been
- * disabled, the disconnect will disable it before proceeding with the
- * disconnect. No other HssAccPacketised
- * interface should be called while this interface is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1).
- * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port
- * to disconnect and it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3
- *
- * @return
- * - IX_SUCCESS The function executed successfully
- * - IX_FAIL The function did not execute successfully
- * - IX_HSSACC_PKT_DISCONNECTING The function has initiated the disconnecting
- * procedure but it has not completed yet.
- */
-PUBLIC IX_STATUS
-ixHssAccPktPortDisconnect (IxHssAccHssPort hssPortId,
- IxHssAccHdlcPort hdlcPortId);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn BOOL ixHssAccPktPortIsDisconnectComplete (IxHssAccHssPort hssPortId,
- IxHssAccHdlcPort hdlcPortId)
- *
- * @brief This function is called to check if a given HSS/HDLC port
- * combination is in a connected state or not. This function may be called
- * at any time to determine a ports state. No other HssAccPacketised
- * interface should be called while this interface is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1).
- * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port
- * to disconnect and it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3
- *
- * @return
- * - TRUE The state of this HSS/HDLC port combination is disconnected,
- * so if a disconnect was called, it is now completed.
- * - FALSE The state of this HSS/HDLC port combination is connected,
- * so if a disconnect was called, it is not yet completed.
- */
-PUBLIC BOOL
-ixHssAccPktPortIsDisconnectComplete (IxHssAccHssPort hssPortId,
- IxHssAccHdlcPort hdlcPortId);
-
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccPktPortRxFreeReplenish (IxHssAccHssPort hssPortId,
- IxHssAccHdlcPort hdlcPortId,
- IX_OSAL_MBUF *buffer)
- *
- * @brief Function which the client calls at regular intervals to provide
- * mbufs to the access component for RX. A connection should exist for
- * the specified hssPortId/hdlcPortId combination before attempting to call this
- * interface. Also, the connection should not be in a disconnecting state.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1).
- * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port
- * and it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3
- * @param *buffer @ref IX_OSAL_MBUF [in] - A pointer to a free mbuf to filled with payload.
- *
- * @return
- * - IX_SUCCESS The function executed successfully
- * - IX_FAIL The function did not execute successfully
- * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- * parameter error
- * - IX_HSSACC_RESOURCE_ERR The function did not execute successfully due
- * to a resource error
- * - IX_HSSACC_Q_WRITE_OVERFLOW The function did not succeed due to a Q
- * overflow
- */
-PUBLIC IX_STATUS
-ixHssAccPktPortRxFreeReplenish (IxHssAccHssPort hssPortId,
- IxHssAccHdlcPort hdlcPortId,
- IX_OSAL_MBUF *buffer);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccPktPortTx (IxHssAccHssPort hssPortId,
- IxHssAccHdlcPort hdlcPortId,
- IX_OSAL_MBUF *buffer)
- *
- * @brief Function which the client calls when it wants to transmit
- * packetised data. An enabled connection should exist on the specified
- * hssPortId/hdlcPortId combination before attempting to call this interface.
- * No other HssAccPacketised
- * interface should be called while this interface is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1).
- * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port
- * and it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3
- * @param *buffer @ref IX_OSAL_MBUF [in] - A pointer to a chain of mbufs which the
- * client has filled with the payload
- *
- * @return
- * - IX_SUCCESS The function executed successfully
- * - IX_FAIL The function did not execute successfully
- * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- * parameter error
- * - IX_HSSACC_RESOURCE_ERR The function did not execute successfully due
- * to a resource error. See note.
- * - IX_HSSACC_Q_WRITE_OVERFLOW The function did not succeed due to a Q
- * overflow
- *
- * @note IX_HSSACC_RESOURCE_ERR is returned when a free descriptor cannot be
- * obtained to send the chain of mbufs to the NPE. This is a normal scenario.
- * HssAcc has a pool of descriptors and this error means that they are currently
- * all in use.
- * The recommended approach to this is to retry until a descriptor becomes free
- * and the packet is successfully transmitted.
- * Alternatively, the user could wait until the next IxHssAccPktTxDoneCallback
- * callback is triggered, and then retry, as it is this event that causes a
- * transmit descriptor to be freed.
- */
-PUBLIC IX_STATUS
-ixHssAccPktPortTx (IxHssAccHssPort hssPortId,
- IxHssAccHdlcPort hdlcPortId,
- IX_OSAL_MBUF *buffer);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccChanConnect (IxHssAccHssPort hssPortId,
- unsigned bytesPerTSTrigger,
- UINT8 *rxCircular,
- unsigned numRxBytesPerTS,
- UINT32 *txPtrList,
- unsigned numTxPtrLists,
- unsigned numTxBytesPerBlk,
- IxHssAccChanRxCallback rxCallback)
- *
- * @brief This function allows the client to connect to the Tx/Rx NPE
- * Channelised Service. There can only be one client per HSS port. The
- * client is responsible for ensuring that the HSS port is configured
- * appropriately before its connect request. No other HssAccChannelised
- * interface should be called while this interface is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1).
- * @param bytesPerTSTrigger unsigned [in] - The NPE will trigger the access
- * component after bytesPerTSTrigger have been received for all trunk
- * timeslots. This figure is a multiple of 8 e.g. 8 for 1ms trigger, 16 for
- * 2ms trigger.
- * @param *rxCircular UINT8 [in] - A pointer to memory allocated by the
- * client to be filled by data received. The buffer at this address is part
- * of a pool of buffers to be accessed in a circular fashion. This address
- * will be written to by the NPE. Therefore, it needs to be a physical address.
- * @param numRxBytesPerTS unsigned [in] - The number of bytes allocated per
- * timeslot within the receive memory. This figure will depend on the
- * latency of the system. It needs to be deep enough for data to be read by
- * the client before the NPE re-writes over that memory e.g. if the client
- * samples at a rate of 40bytes per timeslot, numRxBytesPerTS may need to
- * be 40bytes * 3. This would give the client 3 * 5ms of time before
- * received data is over-written.
- * @param *txPtrList UINT32 [in] - The address of an area of contiguous
- * memory allocated by the client to be populated with pointers to data for
- * transmission. Each pointer list contains a pointer per active channel.
- * The txPtrs will point to data to be transmitted by the NPE. Therefore,
- * they must point to physical addresses.
- * @param numTxPtrLists unsigned [in] - The number of pointer lists in
- * txPtrList. This figure is dependent on jitter.
- * @param numTxBytesPerBlk unsigned [in] - The size of the Tx data, in
- * bytes, that each pointer within the PtrList points to.
- * @param rxCallback @ref IxHssAccChanRxCallback [in] - A client function
- * pointer to be called back to handle the actual tx/rx of channelised
- * data. If this is not NULL, an ISR will call this function. If this
- * pointer is NULL, it implies that the client will use a polling mechanism
- * to detect when the tx and rx of channelised data is to occur. The client
- * will use hssChanAccStatus for this.
- *
- * @return
- * - IX_SUCCESS The function executed successfully
- * - IX_FAIL The function did not execute successfully
- * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- * parameter error
- */
-
-PUBLIC IX_STATUS
-ixHssAccChanConnect (IxHssAccHssPort hssPortId,
- unsigned bytesPerTSTrigger,
- UINT8 *rxCircular,
- unsigned numRxBytesPerTS,
- UINT32 *txPtrList,
- unsigned numTxPtrLists,
- unsigned numTxBytesPerBlk,
- IxHssAccChanRxCallback rxCallback);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccChanPortEnable (IxHssAccHssPort hssPortId)
- *
- * @brief This function is responsible for enabling a channelised service
- * for the specified HSS port. It enables the NPE RX flow. The client must
- * have already connected to a channelised service before enabling the
- * channelised service. No other HssAccChannelised
- * interface should be called while this interface is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1).
- *
- * @return
- * - IX_SUCCESS The function executed successfully
- * - IX_FAIL The function did not execute successfully
- * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- * parameter error
- */
-PUBLIC IX_STATUS
-ixHssAccChanPortEnable (IxHssAccHssPort hssPortId);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccChanPortDisable (IxHssAccHssPort hssPortId)
- *
- * @brief This function is responsible for disabling a channelised service
- * for the specified HSS port. It disables the NPE RX flow. The client must
- * have already connected to and enabled a channelised service for the
- * specified HSS port. This disable interface can be called before a
- * disconnect, but is not required to. No other HssAccChannelised
- * interface should be called while this interface is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1).
- *
- * @return
- * - IX_SUCCESS The function executed successfully
- * - IX_FAIL The function did not execute successfully
- * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- * parameter error
- */
-PUBLIC IX_STATUS
-ixHssAccChanPortDisable (IxHssAccHssPort hssPortId);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccChanDisconnect (IxHssAccHssPort hssPortId)
- *
- * @brief This function allows the client to Disconnect from a channelised
- * service. If the NPE RX Flow has not been disabled, the disconnect will
- * disable it before proceeding with other disconnect functionality.
- * No other HssAccChannelised interface should be called while this
- * interface is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1).
- *
- * @return
- * - IX_SUCCESS The function executed successfully
- * - IX_FAIL The function did not execute successfully
- * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- * parameter error
- */
-PUBLIC IX_STATUS
-ixHssAccChanDisconnect (IxHssAccHssPort hssPortId);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn IX_STATUS ixHssAccChanStatusQuery (IxHssAccHssPort hssPortId,
- BOOL *dataRecvd,
- unsigned *rxOffset,
- unsigned *txOffset,
- unsigned *numHssErrs)
- *
- * @brief This function is called by the client to query whether or not
- * channelised data has been received. If there is, hssChanAcc will return
- * the details in the output parameters. An enabled connection should
- * exist on the specified hssPortId before attempting to call this interface.
- * No other HssAccChannelised interface should be called while this
- * interface is being processed.
- *
- * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two
- * identical ports (0-1).
- * @param *dataRecvd BOOL [out] - This BOOL indicates to the client whether
- * or not the access component has read any data for the client. If
- * FALSE, the other output parameters will not have been written to.
- * @param *rxOffset unsigned [out] - An offset to indicate to the client
- * where within the receive buffers the NPE has just written the received
- * data to.
- * @param *txOffset unsigned [out] - An offset to indicate to the client
- * from where within the txPtrList the NPE is currently transmitting from
- * @param *numHssErrs unsigned [out] - The total number of HSS port errors
- * since initial port configuration
- *
- *
- * @return
- * - IX_SUCCESS The function executed successfully
- * - IX_FAIL The function did not execute successfully
- * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a
- * parameter error
- */
-PUBLIC IX_STATUS
-ixHssAccChanStatusQuery (IxHssAccHssPort hssPortId,
- BOOL *dataRecvd,
- unsigned *rxOffset,
- unsigned *txOffset,
- unsigned *numHssErrs);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn void ixHssAccShow (void)
- *
- * @brief This function will display the current state of the IxHssAcc
- * component. The output is sent to stdout.
- *
- * @return void
- */
-PUBLIC void
-ixHssAccShow (void);
-
-/**
- *
- * @ingroup IxHssAccAPI
- *
- * @fn void ixHssAccStatsInit (void)
- *
- * @brief This function will reset the IxHssAcc statistics.
- *
- * @return void
- */
-PUBLIC void
-ixHssAccStatsInit (void);
-
-#endif /* IXHSSACC_H */
-
-/**
- * @} defgroup IxHssAcc
- */
+++ /dev/null
-/**
- * @file IxI2cDrv.h
- *
- * @brief Header file for the IXP400 I2C Driver (IxI2cDrv)
- *
- * @version $Revision: 0.1 $
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxI2cDrv IXP400 I2C Driver(IxI2cDrv) API
- *
- * @brief IXP400 I2C Driver Public API
- *
- * @{
- */
-#ifndef IXI2CDRV_H
-#define IXI2CDRV_H
-
-#ifdef __ixp46X
-#include "IxOsal.h"
-
-/*
- * Section for #define
- */
-
-/**
- * @ingroup IxI2cDrv
- * @brief The interval of micro/mili seconds the IXP will wait before it polls for
- * status from the ixI2cIntrXferStatus; Every 20us is 1 byte @
- * 400Kbps and 4 bytes @ 100Kbps. This is dependent on delay type selected
- * through the API ixI2cDrvDelayTypeSelect.
- */
-#define IX_I2C_US_POLL_FOR_XFER_STATUS 20
-
-/**
- * @ingroup IxI2cDrv
- * @brief The number of tries that will be attempted to call a callback
- * function if the callback does not or is unable to resolve the
- * issue it is called to resolve
- */
-#define IX_I2C_NUM_OF_TRIES_TO_CALL_CALLBACK_FUNC 10
-
-
-/**
- * @ingroup IxI2cDrv
- * @brief Number of tries slave will poll the IDBR Rx full bit before it
- * gives up
- */
-#define IX_I2C_NUM_TO_POLL_IDBR_RX_FULL 0x100
-
-/**
- * @ingroup IxI2cDrv
- * @brief Number of tries slave will poll the IDBR Tx empty bit before it
- * gives up
- */
-#define IX_I2C_NUM_TO_POLL_IDBR_TX_EMPTY 0x100
-
-/*
- * Section for enum
- */
-
-/**
- * @ingroup IxI2cDrv
- *
- * @enum IxI2cMasterStatus
- *
- * @brief The master status - transfer complete, bus error or arbitration loss
- */
-typedef enum
-{
- IX_I2C_MASTER_XFER_COMPLETE = IX_SUCCESS,
- IX_I2C_MASTER_XFER_BUS_ERROR,
- IX_I2C_MASTER_XFER_ARB_LOSS
-} IxI2cMasterStatus;
-
-
-/**
- * @ingroup IxI2cDrv
- *
- * @enum IX_I2C_STATUS
- *
- * @brief The status that can be returned in a I2C driver initialization
- */
-typedef enum
-{
- IX_I2C_SUCCESS = IX_SUCCESS, /**< Success status */
- IX_I2C_FAIL, /**< Fail status */
- IX_I2C_NOT_SUPPORTED, /**< hardware does not have dedicated I2C hardware */
- IX_I2C_NULL_POINTER, /**< parameter passed in is NULL */
- IX_I2C_INVALID_SPEED_MODE_ENUM_VALUE, /**< speed mode selected is invalid */
- IX_I2C_INVALID_FLOW_MODE_ENUM_VALUE, /**< flow mode selected is invalid */
- IX_I2C_SLAVE_ADDR_CB_MISSING, /**< slave callback is NULL */
- IX_I2C_GEN_CALL_CB_MISSING, /**< general callback is NULL */
- IX_I2C_INVALID_SLAVE_ADDR, /**< invalid slave address specified */
- IX_I2C_INT_BIND_FAIL, /**< interrupt bind fail */
- IX_I2C_INT_UNBIND_FAIL, /**< interrupt unbind fail */
- IX_I2C_NOT_INIT, /**< I2C is not initialized yet */
- IX_I2C_MASTER_BUS_BUSY, /**< master detected a I2C bus busy */
- IX_I2C_MASTER_ARB_LOSS, /**< master experienced arbitration loss */
- IX_I2C_MASTER_XFER_ERROR, /**< master experienced a transfer error */
- IX_I2C_MASTER_BUS_ERROR, /**< master detected a I2C bus error */
- IX_I2C_MASTER_NO_BUFFER, /**< no buffer provided for master transfer */
- IX_I2C_MASTER_INVALID_XFER_MODE, /**< xfer mode selected is invalid */
- IX_I2C_SLAVE_ADDR_NOT_DETECTED, /**< polled slave addr not detected */
- IX_I2C_GEN_CALL_ADDR_DETECTED, /**< polling detected general call */
- IX_I2C_SLAVE_READ_DETECTED, /**< polling detected slave read request */
- IX_I2C_SLAVE_WRITE_DETECTED, /**< polling detected slave write request */
- IX_I2C_SLAVE_NO_BUFFER, /**< no buffer provided for slave transfers */
- IX_I2C_DATA_SIZE_ZERO, /**< data size transfer is zero - invalid */
- IX_I2C_SLAVE_WRITE_BUFFER_EMPTY, /**< slave buffer is used till empty */
- IX_I2C_SLAVE_WRITE_ERROR, /**< slave write experienced an error */
- IX_I2C_SLAVE_OR_GEN_READ_BUFFER_FULL, /**< slave buffer is filled up */
- IX_I2C_SLAVE_OR_GEN_READ_ERROR /**< slave read experienced an error */
-} IX_I2C_STATUS;
-
-/**
- * @ingroup IxI2cDrv
- *
- * @enum IxI2cSpeedMode
- *
- * @brief Type of speed modes supported by the I2C hardware.
- */
-typedef enum
-{
- IX_I2C_NORMAL_MODE = 0x0,
- IX_I2C_FAST_MODE
-} IxI2cSpeedMode;
-
-/**
- * @ingroup IxI2cDrv
- *
- * @enum IxI2cXferMode
- *
- * @brief Used for indicating it is a repeated start or normal transfer
- */
-typedef enum
-{
- IX_I2C_NORMAL = 0x0,
- IX_I2C_REPEATED_START
-} IxI2cXferMode;
-
-/**
- * @ingroup IxI2cDrv
- *
- * @enum IxI2cFlowMode
- *
- * @brief Used for indicating it is a poll or interrupt mode
- */
-typedef enum
-{
- IX_I2C_POLL_MODE = 0x0,
- IX_I2C_INTERRUPT_MODE
-} IxI2cFlowMode;
-
-/**
- * @ingroup IxI2cDrv
- *
- * @enum IxI2cDelayMode
- *
- * @brief Used for selecting looping delay or OS scheduler delay
- */
-typedef enum
-{
- IX_I2C_LOOP_DELAY = 1, /**< delay in microseconds */
- IX_I2C_SCHED_DELAY /**< delay in miliseconds */
-} IxI2cDelayMode;
-
-/**
- * @ingroup IxI2cDrv
- *
- * @brief The pointer to the function that will be called when the master
- * has completed its receive. The parameter that is passed will
- * provide the status of the read (success, arb loss, or bus
- * error), the transfer mode (normal or repeated start, the
- * buffer pointer and number of bytes transferred.
- */
-typedef void (*IxI2cMasterReadCallbackP)(IxI2cMasterStatus, IxI2cXferMode, char*, UINT32);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @brief The pointer to the function that will be called when the master
- * has completed its transmit. The parameter that is passed will
- * provide the status of the write (success, arb loss, or buss
- * error), the transfer mode (normal or repeated start), the
- * buffer pointer and number of bytes transferred.
- */
-typedef void (*IxI2cMasterWriteCallbackP)(IxI2cMasterStatus, IxI2cXferMode, char*, UINT32);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @brief The pointer to the function that will be called when a slave
- * address detected in interrupt mode for a read. The parameters
- * that is passed will provide the read status, buffer pointer,
- * buffer size, and the bytes received. When a start of a read
- * is initiated there will be no buffer allocated and this callback
- * will be called to request for a buffer. While receiving, if the
- * buffer gets filled, this callback will be called to request for
- * a new buffer while sending the filled buffer's pointer and size,
- * and data size received. When the receive is complete, this
- * callback will be called to process the data and free the memory
- * by passing the buffer's pointer and size, and data size received.
- */
-typedef void (*IxI2cSlaveReadCallbackP)(IX_I2C_STATUS, char*, UINT32, UINT32);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @brief The pointer to the function that will be called when a slave
- * address detected in interrupt mode for a write. The parameters
- * that is passed will provide the write status, buffer pointer,
- * buffer size, and the bytes received. When a start of a write is
- * initiated there will be no buffer allocated and this callback
- * will be called to request for a buffer and to fill it with data.
- * While transmitting, if the data in the buffer empties, this
- * callback will be called to request for more data to be filled in
- * the same or new buffer. When the transmit is complete, this
- * callback will be called to free the memory or other actions to
- * be taken.
- */
-typedef void (*IxI2cSlaveWriteCallbackP)(IX_I2C_STATUS, char*, UINT32, UINT32);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @brief The pointer to the function that will be called when a general
- * call detected in interrupt mode for a read. The parameters that
- * is passed will provide the read status, buffer pointer, buffer
- * size, and the bytes received. When a start of a read is
- * initiated there will be no buffer allocated and this callback
- * will be called to request for a buffer. While receiving, if the
- * buffer gets filled, this callback will be called to request for
- * a new buffer while sending the filled buffer's pointer and size,
- * and data size received. When the receive is complete, this
- * callback will be called to process the data and free the memory
- * by passing the buffer's pointer and size, and data size received.
- */
-typedef void (*IxI2cGenCallCallbackP)(IX_I2C_STATUS, char*, UINT32, UINT32);
-
-/*
- * Section for struct
- */
-
-/**
- * @brief contains all the variables required to initialize the I2C unit
- *
- * Structure to be filled and used for calling initialization
- */
-typedef struct
-{
- IxI2cSpeedMode I2cSpeedSelect; /**<Select either normal (100kbps)
- or fast mode (400kbps)*/
- IxI2cFlowMode I2cFlowSelect; /**<Select interrupt or poll mode*/
- IxI2cMasterReadCallbackP MasterReadCBP;
- /**<The master read callback pointer */
- IxI2cMasterWriteCallbackP MasterWriteCBP;
- /**<The master write callback pointer */
- IxI2cSlaveReadCallbackP SlaveReadCBP;
- /**<The slave read callback pointer */
- IxI2cSlaveWriteCallbackP SlaveWriteCBP;
- /**<The slave write callback pointer */
- IxI2cGenCallCallbackP GenCallCBP;
- /**<The general call callback pointer */
- BOOL I2cGenCallResponseEnable; /**<Enable/disable the unit to
- respond to generall calls.*/
- BOOL I2cSlaveAddrResponseEnable;/**<Enable/disable the unit to
- respond to the slave address set in
- ISAR*/
- BOOL SCLEnable; /**<Enable/disable the unit from
- driving the SCL line during master
- mode operation*/
- UINT8 I2cHWAddr; /**<The address the unit will
- response to as a slave device*/
-} IxI2cInitVars;
-
-/**
- * @brief contains results of counters and their overflow
- *
- * Structure contains all values of counters and associated overflows.
- */
-typedef struct
-{
- UINT32 ixI2cMasterXmitCounter; /**<Total bytes transmitted as
- master.*/
- UINT32 ixI2cMasterFailedXmitCounter; /**<Total bytes failed for
- transmission as master.*/
- UINT32 ixI2cMasterRcvCounter; /**<Total bytes received as
- master.*/
- UINT32 ixI2cMasterFailedRcvCounter; /**<Total bytes failed for
- receival as master.*/
- UINT32 ixI2cSlaveXmitCounter; /**<Total bytes transmitted as
- slave.*/
- UINT32 ixI2cSlaveFailedXmitCounter; /**<Total bytes failed for
- transmission as slave.*/
- UINT32 ixI2cSlaveRcvCounter; /**<Total bytes received as
- slave.*/
- UINT32 ixI2cSlaveFailedRcvCounter; /**<Total bytes failed for
- receival as slave.*/
- UINT32 ixI2cGenAddrCallSucceedCounter; /**<Total bytes successfully
- transmitted for general address.*/
- UINT32 ixI2cGenAddrCallFailedCounter; /**<Total bytes failed transmission
- for general address.*/
- UINT32 ixI2cArbLossCounter; /**<Total instances of arbitration
- loss has occured.*/
-} IxI2cStatsCounters;
-
-
-/*
- * Section for prototypes interface functions
- */
-
-/**
- * @ingroup IxI2cDrv
- *
- * @fn ixI2cDrvInit(
- IxI2cInitVars *InitVarsSelected)
- *
- * @brief Initializes the I2C Driver.
- *
- * @param "IxI2cInitVars [in] *InitVarsSelected" - struct containing required
- * variables for initialization
- *
- * Global Data :
- * - None.
- *
- * This API will check if the hardware supports this I2C driver and the validity
- * of the parameters passed in. It will continue to process the parameters
- * passed in by setting the speed of the I2C unit (100kbps or 400kbps), setting
- * the flow to either interrupt or poll mode, setting the address of the I2C unit,
- * enabling/disabling the respond to General Calls, enabling/disabling the respond
- * to Slave Address and SCL line driving. If it is interrupt mode, then it will
- * register the callback routines for master, slavetransfer and general call receive.
- *
- * @return
- * - IX_I2C_SUCCESS - Successfully initialize and enable the I2C
- * hardware.
- * - IX_I2C_NOT_SUPPORTED - The hardware does not support or have a
- * dedicated I2C unit to support this driver
- * - IX_I2C_NULL_POINTER - The parameter passed in is a NULL pointed
- * - IX_I2C_INVALID_SPEED_MODE_ENUM_VALUE - The speed mode selected in the
- * InitVarsSelected is invalid
- * - IX_I2C_INVALID_FLOW_MODE_ENUM_VALUE - The flow mode selected in the
- * InitVarsSelected is invalid
- * - IX_I2C_INVALID_SLAVE_ADDR - The address 0x0 is reserved for
- * general call.
- * - IX_I2C_SLAVE_ADDR_CB_MISSING - interrupt mode is selected but
- * slave address callback pointer is NULL
- * - IX_I2C_GEN_CALL_CB_MISSING - interrupt mode is selected but
- * general call callback pointer is NULL
- * - IX_I2C_INT_BIND_FAIL - The ISR for the I2C failed to bind
- * - IX_I2C_INT_UNBIND_FAIL - The ISR for the I2C failed to unbind
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvInit(IxI2cInitVars *InitVarsSelected);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @fn ixI2cDrvUninit(
- void)
- *
- * @brief Disables the I2C hardware
- *
- * @param - None
- *
- * Global Data :
- * - None.
- *
- * This API will disable the I2C hardware, unbind interrupt, and unmap memory.
- *
- * @return
- * - IX_I2C_SUCCESS - successfully un-initialized I2C
- * - IX_I2C_INT_UNBIND_FAIL - failed to unbind the I2C interrupt
- * - IX_I2C_NOT_INIT - I2C not init yet.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvUninit(void);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @fn ixI2cDrvSlaveAddrSet(
- UINT8 SlaveAddrSet)
- *
- * @brief Sets the I2C Slave Address
- *
- * @param "UINT8 [in] SlaveAddrSet" - Slave Address to be inserted into ISAR
- *
- * Global Data :
- * - None.
- *
- * This API will insert the SlaveAddrSet into the ISAR.
- *
- * @return
- * - IX_I2C_SUCCESS - successfuly set the slave addr
- * - IX_I2C_INVALID_SLAVE_ADDR - invalid slave address (zero) specified
- * - IX_I2C_NOT_INIT - I2C not init yet.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvSlaveAddrSet(UINT8 SlaveAddrSet);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @fn ixI2cDrvBusScan(
- void)
- *
- * @brief scans the I2C bus for slave devices
- *
- * @param - None
- *
- * Global Data :
- * - None.
- *
- * This API will prompt all slave addresses for a reply except its own
- *
- * @return
- * - IX_I2C_SUCCESS - found at least one slave device
- * - IX_I2C_FAIL - Fail to find even one slave device
- * - IX_I2C_BUS_BUSY - The I2C bus is busy (held by another I2C master)
- * - IX_I2C_ARB_LOSS - The I2C bus was loss to another I2C master
- * - IX_I2C_NOT_INIT - I2C not init yet.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvBusScan(void);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @fn ixI2cDrvWriteTransfer(
- UINT8 SlaveAddr,
- char *bufP,
- UINT32 dataSize,
- IxI2cXferMode XferModeSelect)
- *
- * @param "UINT8 [in] SlaveAddr" - The slave address to request data from.
- * @param "char [in] *bufP" - The pointer to the data to be transmitted.
- * @param "UINT32 [in] dataSize" - The number of bytes requested.
- * @param "IxI2cXferMode [in] XferModeSelect" - the transfer mode selected,
- * either repeated start (ends w/o stop) or normal (start and stop)
- *
- * Global Data :
- * - None.
- *
- * This API will try to obtain master control of the I2C bus and transmit the
- * number of bytes, specified by dataSize, to the user specified slave
- * address from the buffer pointer. It will use either interrupt or poll mode
- * depending on the method selected.
- *
- * If in interrupt mode and IxI2cMasterWriteCallbackP is not NULL, the driver
- * will initiate the transfer and return immediately. The function pointed to
- * by IxI2cMasterWriteCallbackP will be called in the interrupt service
- * handlers when the operation is complete.
- *
- * If in interrupt mode and IxI2cMasterWriteCallbackP is NULL, then the driver
- * will wait for the operation to complete, and then return.
- *
- * And if the repeated start transfer mode is selected, then it will not send a
- * stop signal at the end of all the transfers.
- * *NOTE*: If repeated start transfer mode is selected, it has to end with a
- * normal mode transfer mode else the bus will continue to be held
- * by the IXP.
- *
- * @return
- * - IX_I2C_SUCCESS - Successfuuly wrote data to slave.
- * - IX_I2C_MASTER_BUS_BUSY - The I2C bus is busy (held by another I2C master)
- * - IX_I2C_MASTER_ARB_LOSS - The I2C bus was loss to another I2C master
- * - IX_I2C_MASTER_XFER_ERROR - There was a transfer error
- * - IX_I2C_MASTER_BUS_ERROR - There was a bus error during transfer
- * - IX_I2C_MASTER_NO_BUFFER - buffer pointer is NULL
- * - IX_I2C_MASTER_INVALID_XFER_MODE - Xfer mode selected is invalid
- * - IX_I2C_DATA_SIZE_ZERO - dataSize passed in is zero, which is invalid
- * - IX_I2C_NOT_INIT - I2C not init yet.
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvWriteTransfer(
- UINT8 SlaveAddr,
- char *bufP,
- UINT32 dataSize,
- IxI2cXferMode XferModeSelect);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @fn ixI2cDrvReadTransfer(
- UINT8 SlaveAddr,
- char *bufP,
- UINT32 dataSize,
- IxI2cXferMode XferModeSelect)
- *
- * @brief Initiates a transfer to receive bytes of data from a slave
- * device through the I2C bus.
- *
- * @param "UINT8 [in] SlaveAddr" - The slave address to request data from.
- * @param "char [out] *bufP" - The pointer to the buffer to store the
- * requested data.
- * @param "UINT32 [in] dataSize" - The number of bytes requested.
- * @param "IxI2cXferMode [in] XferModeSelect" - the transfer mode selected,
- * either repeated start (ends w/o stop) or normal (start and stop)
- *
- * Global Data :
- * - None.
- *
- * This API will try to obtain master control of the I2C bus and receive the
- * number of bytes, specified by dataSize, from the user specified address
- * into the receive buffer. It will use either interrupt or poll mode depending
- * on the mode selected.
- *
- * If in interrupt mode and IxI2cMasterReadCallbackP is not NULL, the driver
- * will initiate the transfer and return immediately. The function pointed to
- * by IxI2cMasterReadCallbackP will be called in the interrupt service
- * handlers when the operation is complete.
- *
- * If in interrupt mode and IxI2cMasterReadCallbackP is NULL, then the driver will
- * wait for the operation to complete, and then return.
- *
- * And if the repeated start transfer mode is selected, then it will not send a
- * stop signal at the end of all the transfers.
- * *NOTE*: If repeated start transfer mode is selected, it has to end with a
- * normal mode transfer mode else the bus will continue to be held
- * by the IXP.
- *
- * @return
- * - IX_I2C_SUCCESS - Successfuuly read slave data
- * - IX_I2C_MASTER_BUS_BUSY - The I2C bus is busy (held by another I2C master)
- * - IX_I2C_MASTER_ARB_LOSS - The I2C bus was loss to another I2C master
- * - IX_I2C_MASTER_XFER_ERROR - There was a bus error during transfer
- * - IX_I2C_MASTER_BUS_ERROR - There was a bus error during transfer
- * - IX_I2C_MASTER_NO_BUFFER - buffer pointer is NULL
- * - IX_I2C_MASTER_INVALID_XFER_MODE - Xfer mode selected is invalid
- * - IX_I2C_INVALID_SLAVE_ADDR - invalid slave address (zero) specified
- * - IX_I2C_DATA_SIZE_ZERO - dataSize passed in is zero, which is invalid
- * - IX_I2C_NOT_INIT - I2C not init yet.
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvReadTransfer(
- UINT8 SlaveAddr,
- char *bufP,
- UINT32 dataSize,
- IxI2cXferMode XferModeSelect);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @fn ixI2cDrvSlaveAddrAndGenCallDetectedCheck(
- void)
- *
- * @brief Checks the I2C Status Register to determine if a slave address is
- * detected
- *
- * @param - None
- *
- * Global Data :
- * - None.
- *
- * This API is used in polled mode to determine if the I2C unit is requested
- * for a slave or general call transfer. If it is requested for a slave
- * transfer then it will determine if it is a general call (read only), read,
- * or write transfer requested.
- *
- * @return
- * - IX_I2C_SLAVE_ADDR_NOT_DETECTED - The I2C unit is not requested for slave
- * transfer
- * - IX_I2C_GEN_CALL_ADDR_DETECTED - The I2C unit is not requested for slave
- * transfer but for general call
- * - IX_I2C_SLAVE_READ_DETECTED - The I2C unit is requested for a read
- * - IX_I2C_SLAVE_WRITE_DETECTED - The I2C unit is requested for a write
- * - IX_I2C_NOT_INIT - I2C not init yet.
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvSlaveAddrAndGenCallDetectedCheck(void);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @fn ixI2cDrvSlaveOrGenDataReceive(
- char *bufP,
- UINT32 bufSize,
- UINT32 *dataSizeRcvd)
- *
- * @brief Performs the slave receive or general call receive data transfer
- *
- * @param "char [in] *bufP" - the pointer to the buffer to store data
- * "UINT32 [in] bufSize" - the buffer size allocated
- * "UINT32 [in] *dataSizeRcvd" - the length of data received in bytes
- *
- * Global Data :
- * - None.
- *
- * This API is only used in polled mode to perform the slave read or general call
- * receive data. It will continuously store the data received into bufP until
- * complete or until bufP is full in which it will return
- * IX_I2C_SLAVE_OR_GEN_READ_BUFFER_FULL. If in interrupt mode, the callback will be
- * used.
- *
- * @return
- * - IX_I2C_SUCCESS - The I2C driver transferred the data successfully.
- * - IX_I2C_SLAVE_OR_GEN_READ_BUFFER_FULL - The I2C driver has ran out of
- * space to store the received data.
- * - IX_I2C_SLAVE_OR_GEN_READ_ERROR - The I2C driver didn't manage to
- * detect the IDBR Rx Full bit
- * - IX_I2C_DATA_SIZE_ZERO - bufSize passed in is zero, which is invalid
- * - IX_I2C_SLAVE_NO_BUFFER - buffer pointer is NULL
- * - IX_I2C_NULL_POINTER - dataSizeRcvd is NULL
- * - IX_I2C_NOT_INIT - I2C not init yet.
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvSlaveOrGenDataReceive(
- char *bufP,
- UINT32 bufSize,
- UINT32 *dataSizeRcvd);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @fn ixI2cDrvSlaveDataTransmit(
- char *bufP,
- UINT32 dataSize,
- UINT32 *dataSizeXmtd)
- *
- * @brief Performs the slave write data transfer
- *
- * @param "char [in] *bufP" - the pointer to the buffer for data to be
- * transmitted
- * "UINT32 [in] bufSize" - the buffer size allocated
- * "UINT32 [in] *dataSizeRcvd" - the length of data trasnmitted in
- * bytes
- *
- * Global Data :
- * - None.
- *
- * This API is only used in polled mode to perform the slave transmit data. It
- * will continuously transmit the data from bufP until complete or until bufP
- * is empty in which it will return IX_I2C_SLAVE_WRITE_BUFFER_EMPTY. If in
- * interrupt mode, the callback will be used.
- *
- * @return
- * - IX_I2C_SUCCESS - The I2C driver transferred the data successfully.
- * - IX_I2C_SLAVE_WRITE_BUFFER_EMPTY - The I2C driver needs more data to
- * transmit.
- * - IX_I2C_SLAVE_WRITE_ERROR -The I2C driver didn't manage to detect the
- * IDBR Tx empty bit or the slave stop bit.
- * - IX_I2C_DATA_SIZE_ZERO - dataSize passed in is zero, which is invalid
- * - IX_I2C_SLAVE_NO_BUFFER - buffer pointer is NULL
- * - IX_I2C_NULL_POINTER - dataSizeXmtd is NULL
- * - IX_I2C_NOT_INIT - I2C not init yet.
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvSlaveDataTransmit(
- char *bufP,
- UINT32 dataSize,
- UINT32 *dataSizeXmtd);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @fn ixI2cDrvSlaveOrGenCallBufReplenish(
- char *bufP,
- UINT32 bufSize)
- *
- * @brief Replenishes the buffer which stores buffer info for both slave and
- * general call
- *
- * @param "char [in] *bufP" - pointer to the buffer allocated
- * "UINT32 [in] bufSize" - size of the buffer
- *
- * Global Data :
- * - None.
- *
- * This API is only used in interrupt mode for replenishing the same buffer
- * that is used by both slave and generall call by updating the buffer info
- * with new info and clearing previous offsets set by previous transfers.
- *
- * @return
- * - None
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC void
-ixI2cDrvSlaveOrGenCallBufReplenish(
- char *bufP,
- UINT32 bufSize);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @fn ixI2cDrvStatsGet(IxI2cStatsCounters *I2cStats)
- *
- * @brief Returns the I2C Statistics through the pointer passed in
- *
- * @param - "IxI2cStatsCounters [out] *I2cStats" - I2C statistics counter will
- * be read and written to the location pointed by this pointer.
- *
- * Global Data :
- * - None.
- *
- * This API will return the statistics counters of the I2C driver.
- *
- * @return
- * - IX_I2C_NULL_POINTER - pointer passed in is NULL
- * - IX_I2C_SUCCESS - successfully obtained I2C statistics
- *
- * @li Reentrant : yes
- * @li ISR Callable : no
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvStatsGet(IxI2cStatsCounters *I2cStats);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @fn ixI2cDrvStatsReset(void)
- *
- * @brief Reset I2C statistics counters.
- *
- * @param - None
- *
- * Global Data :
- * - None.
- *
- * This API will reset the statistics counters of the I2C driver.
- *
- * @return
- * - None
- *
- * @li Reentrant : yes
- * @li ISR Callable : no
- *
- */
-PUBLIC void
-ixI2cDrvStatsReset(void);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @fn ixI2cDrvShow(void)
- *
- * @brief Displays the I2C status register and the statistics counter.
- *
- * @param - None
- *
- * Global Data :
- * - None.
- *
- * This API will display the I2C Status register and is useful if any error
- * occurs. It displays the detection of bus error, slave address, general call,
- * address, IDBR receive full, IDBR transmit empty, arbitration loss, slave
- * STOP signal, I2C bus busy, unit busy, ack/nack, and read/write mode. It will
- * also call the ixI2cDrvGetStats and then display the statistics counter.
- *
- * @return
- * - IX_I2C_SUCCESS - successfully displayed statistics and status register
- * - IX_I2C_NOT_INIT - I2C not init yet.
- *
- * @li Reentrant : yes
- * @li ISR Callable : no
- *
- */
-PUBLIC IX_I2C_STATUS
-ixI2cDrvShow(void);
-
-/**
- * @ingroup IxI2cDrv
- *
- * @fn ixI2cDrvDelayTypeSelect (IxI2cDelayMode delayMechanismSelect)
- *
- * @brief Sets the delay type of either looping delay or OS scheduler delay
- * according to the argument provided.
- *
- * @param - "IxI2cDelayMode [in] delayTypeSelect" - the I2C delay type selected
- *
- * Global Data :
- * - None.
- *
- * This API will set the delay type used by the I2C Driver to either looping
- * delay or OS scheduler delay.
- *
- * @return
- * - None
- *
- * @li Reentrant : yes
- * @li ISR Callable : no
- *
- */
-PUBLIC void
-ixI2cDrvDelayTypeSelect (IxI2cDelayMode delayTypeSelect);
-
-#endif /* __ixp46X */
-#endif /* IXI2CDRV_H */
+++ /dev/null
-#ifndef __doxygen_HIDE /* This file is not part of the API */
-
-/**
- * @file IxNpeA.h
- *
- * @date 22-Mar-2002
- *
- * @brief Header file for the IXP400 ATM NPE API
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxNpeA IXP400 NPE-A (IxNpeA) API
- *
- * @brief The Public API for the IXP400 NPE-A
- *
- * @{
- */
-
-#ifndef IX_NPE_A_H
-#define IX_NPE_A_H
-
-#include "IxQMgr.h"
-#include "IxOsal.h"
-#include "IxQueueAssignments.h"
-
-/* General Message Ids */
-
-/* ATM Message Ids */
-
-/**
- * @def IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_WRITE
- *
- * @brief ATM Message ID command to write the data to the offset in the
- * Utopia Configuration Table
- */
-#define IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_WRITE 0x20
-
-/**
- * @def IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_LOAD
- *
- * @brief ATM Message ID command triggers the NPE to copy the Utopia
- * Configuration Table to the Utopia coprocessor
- */
-#define IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_LOAD 0x21
-
-/**
- * @def IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_UPLOAD
- *
- * @brief ATM Message ID command triggers the NPE to read-back the Utopia
- * status registers and update the Utopia Status Table.
- */
-#define IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_UPLOAD 0x22
-
-/**
- * @def IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_READ
- *
- * @brief ATM Message ID command to read the Utopia Status Table at the
- * specified offset.
- */
-#define IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_READ 0x23
-
-/**
- * @def IX_NPE_A_MSSG_ATM_TX_ENABLE
- *
- * @brief ATM Message ID command triggers the NPE to re-enable processing
- * of any entries on the TxVcQ for this port.
- *
- * This command will be ignored for a port already enabled
- */
-#define IX_NPE_A_MSSG_ATM_TX_ENABLE 0x25
-
- /**
- * @def IX_NPE_A_MSSG_ATM_TX_DISABLE
- *
- * @brief ATM Message ID command triggers the NPE to disable processing on
- * this port
- *
- * This command will be ignored for a port already disabled
- */
-#define IX_NPE_A_MSSG_ATM_TX_DISABLE 0x26
-
-/**
- * @def IX_NPE_A_MSSG_ATM_RX_ENABLE
- *
- * @brief ATM Message ID command triggers the NPE to process any received
- * cells for this VC according to the VC Lookup Table.
- *
- * Re-issuing this command with different contents for a VC that is not
- * disabled will cause unpredictable behavior.
- */
-#define IX_NPE_A_MSSG_ATM_RX_ENABLE 0x27
-
-/**
- * @def IX_NPE_A_MSSG_ATM_RX_DISABLE
- *
- * @brief ATM Message ID command triggers the NPE to disable processing for
- * this VC.
- *
- * This command will be ignored for a VC already disabled
- */
-#define IX_NPE_A_MSSG_ATM_RX_DISABLE 0x28
-
-/**
- * @def IX_NPE_A_MSSG_ATM_STATUS_READ
- *
- * @brief ATM Message ID command to read the ATM status. The data is returned via
- * a response message
- */
-#define IX_NPE_A_MSSG_ATM_STATUS_READ 0x29
-
-/*--------------------------------------------------------------------------
- * HSS Message IDs
- *--------------------------------------------------------------------------*/
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PORT_CONFIG_WRITE
- *
- * @brief HSS Message ID command writes the ConfigWord value to the location
- * in the HSS_CONFIG_TABLE specified by offset for HSS port hPort.
- */
-#define IX_NPE_A_MSSG_HSS_PORT_CONFIG_WRITE 0x40
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PORT_CONFIG_LOAD
- *
- * @brief HSS Message ID command triggers the NPE to copy the contents of the
- * HSS Configuration Table to the appropriate configuration registers in the
- * HSS coprocessor for the port specified by hPort.
- */
-#define IX_NPE_A_MSSG_HSS_PORT_CONFIG_LOAD 0x41
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PORT_ERROR_READ
- *
- * @brief HSS Message ID command triggers the NPE to return an HssErrorReadResponse
- * message for HSS port hPort.
- */
-#define IX_NPE_A_MSSG_HSS_PORT_ERROR_READ 0x42
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_FLOW_ENABLE
- *
- * @brief HSS Message ID command triggers the NPE to reset internal status and
- * enable the HssChannelized operation on the HSS port specified by hPort.
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_FLOW_ENABLE 0x43
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_FLOW_DISABLE
- *
- * @brief HSS Message ID command triggers the NPE to disable the HssChannelized
- * operation on the HSS port specified by hPort.
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_FLOW_DISABLE 0x44
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_IDLE_PATTERN_WRITE
- *
- * @brief HSS Message ID command writes the HSSnC_IDLE_PATTERN value for HSS
- * port hPort. (n=hPort)
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_IDLE_PATTERN_WRITE 0x45
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_NUM_CHANS_WRITE
- *
- * @brief HSS Message ID command writes the HSSnC_NUM_CHANNELS value for HSS
- * port hPort. (n=hPort)
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_NUM_CHANS_WRITE 0x46
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_ADDR_WRITE
- *
- * @brief HSS Message ID command writes the HSSnC_RX_BUF_ADDR value for HSS
- * port hPort. (n=hPort)
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_ADDR_WRITE 0x47
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_CFG_WRITE
- *
- * @brief HSS Message ID command writes the HSSnC_RX_BUF_SIZEB and
- * HSSnC_RX_TRIG_PERIOD values for HSS port hPort. (n=hPort)
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_CFG_WRITE 0x48
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_TX_BLK_CFG_WRITE
- *
- * @brief HSS Message ID command writes the HSSnC_TX_BLK1_SIZEB,
- * HSSnC_TX_BLK1_SIZEW, HSSnC_TX_BLK2_SIZEB, and HSSnC_TX_BLK2_SIZEW values
- * for HSS port hPort. (n=hPort)
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_TX_BLK_CFG_WRITE 0x49
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_ADDR_WRITE
- * @brief HSS Message ID command writes the HSSnC_TX_BUF_ADDR value for HSS
- * port hPort. (n=hPort)
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_ADDR_WRITE 0x4A
-
-/**
- * @def IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_SIZE_WRITE
- *
- * @brief HSS Message ID command writes the HSSnC_TX_BUF_SIZEN value for HSS
- * port hPort. (n=hPort)
- */
-#define IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_SIZE_WRITE 0x4B
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_ENABLE
- *
- * @brief HSS Message ID command triggers the NPE to reset internal status and
- * enable the HssPacketized operation for the flow specified by pPipe on
- * the HSS port specified by hPort.
- */
-#define IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_ENABLE 0x50
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_DISABLE
- * @brief HSS Message ID command triggers the NPE to disable the HssPacketized
- * operation for the flow specified by pPipe on the HSS port specified by hPort.
- */
-#define IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_DISABLE 0x51
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PKT_NUM_PIPES_WRITE
- * @brief HSS Message ID command writes the HSSnP_NUM_PIPES value for HSS
- * port hPort.(n=hPort)
- */
-#define IX_NPE_A_MSSG_HSS_PKT_NUM_PIPES_WRITE 0x52
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_FIFO_SIZEW_WRITE
- *
- * @brief HSS Message ID command writes the HSSnP_PIPEp_FIFOSIZEW value for
- * packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe)
- */
-#define IX_NPE_A_MSSG_HSS_PKT_PIPE_FIFO_SIZEW_WRITE 0x53
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_HDLC_CFG_WRITE
- *
- * @brief HSS Message ID command writes the HSSnP_PIPEp_HDLC_RXCFG and
- * HSSnP_PIPEp_HDLC_TXCFG values for packet-pipe pPipe on HSS port hPort.
- * (n=hPort, p=pPipe)
- */
-#define IX_NPE_A_MSSG_HSS_PKT_PIPE_HDLC_CFG_WRITE 0x54
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_IDLE_PATTERN_WRITE
- *
- * @brief HSS Message ID command writes the HSSnP_PIPEp_IDLE_PATTERN value
- * for packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe)
- */
-#define IX_NPE_A_MSSG_HSS_PKT_PIPE_IDLE_PATTERN_WRITE 0x55
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_RX_SIZE_WRITE
- *
- * @brief HSS Message ID command writes the HSSnP_PIPEp_RXSIZEB value for
- * packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe)
- */
-#define IX_NPE_A_MSSG_HSS_PKT_PIPE_RX_SIZE_WRITE 0x56
-
-/**
- * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_MODE_WRITE
- *
- * @brief HSS Message ID command writes the HSSnP_PIPEp_MODE value for
- * packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe)
- */
-#define IX_NPE_A_MSSG_HSS_PKT_PIPE_MODE_WRITE 0x57
-
-
-
-/* Queue Entry Masks */
-
-/*--------------------------------------------------------------------------
- * ATM Descriptor Structure offsets
- *--------------------------------------------------------------------------*/
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_STATUS_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Status field
- *
- * It is used for descriptor error reporting.
- */
-#define IX_NPE_A_RXDESCRIPTOR_STATUS_OFFSET 0
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_VCID_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor VC ID field
- *
- * It is used to hold an identifier number for this VC
- */
-#define IX_NPE_A_RXDESCRIPTOR_VCID_OFFSET 1
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_CURRMBUFSIZE_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Current Mbuf
- * Size field
- *
- * Number of bytes the current mbuf data buffer can hold
- */
-#define IX_NPE_A_RXDESCRIPTOR_CURRMBUFSIZE_OFFSET 2
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_ATMHEADER_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor ATM Header
- */
-#define IX_NPE_A_RXDESCRIPTOR_ATMHEADER_OFFSET 4
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_CURRMBUFLEN_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Current MBuf length
- *
- *
- * RX - Initialized to zero. The NPE updates this field as each cell is received and
- * zeroes it with every new mbuf for chaining. Will not be bigger than currBbufSize.
- */
-#define IX_NPE_A_RXDESCRIPTOR_CURRMBUFLEN_OFFSET 12
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_TIMELIMIT__OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Time Limit field
- *
- * Contains the Payload Reassembly Time Limit (used for aal0_xx only)
- */
-#define IX_NPE_A_RXDESCRIPTOR_TIMELIMIT_OFFSET 14
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_PCURRMBUFF_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Current MBuf Pointer
- *
- * The current mbuf pointer of a chain of mbufs.
- */
-#define IX_NPE_A_RXDESCRIPTOR_PCURRMBUFF_OFFSET 20
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_PCURRMBUFDATA_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Current MBuf Pointer
- *
- * Pointer to the next byte to be read or next free location to be written.
- */
-#define IX_NPE_A_RXDESCRIPTOR_PCURRMBUFDATA_OFFSET 24
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_PNEXTMBUF_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Next MBuf Pointer
- *
- * Pointer to the next MBuf in a chain of MBufs.
- */
-#define IX_NPE_A_RXDESCRIPTOR_PNEXTMBUF_OFFSET 28
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_TOTALLENGTH_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Total Length
- *
- * Total number of bytes written to the chain of MBufs by the NPE
- */
-#define IX_NPE_A_RXDESCRIPTOR_TOTALLENGTH_OFFSET 32
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor AAL5 CRC Residue
- *
- * Current CRC value for a PDU
- */
-#define IX_NPE_A_RXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET 36
-
-/**
- * @def IX_NPE_A_RXDESCRIPTOR_SIZE
- *
- * @brief ATM Descriptor structure offset for Receive Descriptor Size
- *
- * The size of the Receive descriptor
- */
-#define IX_NPE_A_RXDESCRIPTOR_SIZE 40
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_PORT_OFFSET
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor Port
- *
- * Port identifier.
- */
-#define IX_NPE_A_TXDESCRIPTOR_PORT_OFFSET 0
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_RSVD_OFFSET
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor RSVD
- */
-#define IX_NPE_A_TXDESCRIPTOR_RSVD_OFFSET 1
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_CURRMBUFLEN_OFFSET
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor Current MBuf Length
- *
- * TX - Initialized by the XScale to the number of bytes in the current MBuf data buffer.
- * The NPE decrements this field for every transmitted cell. Thus, when the NPE writes a
- * descriptor the TxDone queue, this field will equal zero.
- */
-#define IX_NPE_A_TXDESCRIPTOR_CURRMBUFLEN_OFFSET 2
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_ATMHEADER_OFFSET
- * @brief ATM Descriptor structure offset for Transmit Descriptor ATM Header
- */
-#define IX_NPE_A_TXDESCRIPTOR_ATMHEADER_OFFSET 4
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_PCURRMBUFF_OFFSET
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor Pointer to the current MBuf chain
- */
-#define IX_NPE_A_TXDESCRIPTOR_PCURRMBUFF_OFFSET 8
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_PCURRMBUFDATA_OFFSET
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor Pointer to the current MBuf Data
- *
- * Pointer to the next byte to be read or next free location to be written.
- */
-#define IX_NPE_A_TXDESCRIPTOR_PCURRMBUFDATA_OFFSET 12
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_PNEXTMBUF_OFFSET
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor Pointer to the Next MBuf chain
- */
-#define IX_NPE_A_TXDESCRIPTOR_PNEXTMBUF_OFFSET 16
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_TOTALLENGTH_OFFSET
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor Total Length
- *
- * Total number of bytes written to the chain of MBufs by the NPE
- */
-#define IX_NPE_A_TXDESCRIPTOR_TOTALLENGTH_OFFSET 20
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor AAL5 CRC Residue
- *
- * Current CRC value for a PDU
- */
-#define IX_NPE_A_TXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET 24
-
-/**
- * @def IX_NPE_A_TXDESCRIPTOR_SIZE
- *
- * @brief ATM Descriptor structure offset for Transmit Descriptor Size
- */
-#define IX_NPE_A_TXDESCRIPTOR_SIZE 28
-
-/**
- * @def IX_NPE_A_CHAIN_DESC_COUNT_MAX
- *
- * @brief Maximum number of chained MBufs that can be chained together
- */
-#define IX_NPE_A_CHAIN_DESC_COUNT_MAX 256
-
-/*
- * Definition of the ATM cell header
- *
- * This would most conviently be defined as the bit field shown below.
- * Endian portability prevents this, therefore a set of macros
- * are defined to access the fields within the cell header assumed to
- * be passed as a UINT32.
- *
- * Changes to field sizes or orders must be reflected in the offset
- * definitions above.
- *
- * typedef struct
- * {
- * unsigned int gfc:4;
- * unsigned int vpi:8;
- * unsigned int vci:16;
- * unsigned int pti:3;
- * unsigned int clp:1;
- * } IxNpeA_AtmCellHeader;
- *
- */
-
-/** Mask to acess GFC */
-#define GFC_MASK 0xf0000000
-
-/** return GFC from ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_GFC_GET( header ) \
-(((header) & GFC_MASK) >> 28)
-
-/** set GFC into ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_GFC_SET( header,gfc ) \
-do { \
- (header) &= ~GFC_MASK; \
- (header) |= (((gfc) << 28) & GFC_MASK); \
-} while(0)
-
-/** Mask to acess VPI */
-#define VPI_MASK 0x0ff00000
-
-/** return VPI from ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_VPI_GET( header ) \
-(((header) & VPI_MASK) >> 20)
-
-/** set VPI into ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_VPI_SET( header, vpi ) \
-do { \
- (header) &= ~VPI_MASK; \
- (header) |= (((vpi) << 20) & VPI_MASK); \
-} while(0)
-
-/** Mask to acess VCI */
-#define VCI_MASK 0x000ffff0
-
-/** return VCI from ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_VCI_GET( header ) \
-(((header) & VCI_MASK) >> 4)
-
-/** set VCI into ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_VCI_SET( header, vci ) \
-do { \
- (header) &= ~VCI_MASK; \
- (header) |= (((vci) << 4) & VCI_MASK); \
-} while(0)
-
-/** Mask to acess PTI */
-#define PTI_MASK 0x0000000e
-
-/** return PTI from ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_PTI_GET( header ) \
-(((header) & PTI_MASK) >> 1)
-
-/** set PTI into ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_PTI_SET( header, pti ) \
-do { \
- (header) &= ~PTI_MASK; \
- (header) |= (((pti) << 1) & PTI_MASK); \
-} while(0)
-
-/** Mask to acess CLP */
-#define CLP_MASK 0x00000001
-
-/** return CLP from ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_CLP_GET( header ) \
-((header) & CLP_MASK)
-
-/** set CLP into ATM cell header */
-#define IX_NPE_A_ATMCELLHEADER_CLP_SET( header, clp ) \
-do { \
- (header) &= ~CLP_MASK; \
- (header) |= ((clp) & CLP_MASK); \
-} while(0)
-
-
-/*
-* Definition of the Rx bitfield
-*
-* This would most conviently be defined as the bit field shown below.
-* Endian portability prevents this, therefore a set of macros
-* are defined to access the fields within the rxBitfield assumed to
-* be passed as a UINT32.
-*
-* Changes to field sizes or orders must be reflected in the offset
-* definitions above.
-*
-* Rx bitfield
-* struct
-* { IX_NPEA_RXBITFIELD(
-* unsigned int status:1,
-* unsigned int port:7,
-* unsigned int vcId:8,
-* unsigned int currMbufSize:16);
-* } rxBitField;
-*
-*/
-
-/** Mask to acess the rxBitField status */
-#define STATUS_MASK 0x80000000
-
-/** return the rxBitField status */
-#define IX_NPE_A_RXBITFIELD_STATUS_GET( rxbitfield ) \
-(((rxbitfield) & STATUS_MASK) >> 31)
-
-/** set the rxBitField status */
-#define IX_NPE_A_RXBITFIELD_STATUS_SET( rxbitfield, status ) \
-do { \
- (rxbitfield) &= ~STATUS_MASK; \
- (rxbitfield) |= (((status) << 31) & STATUS_MASK); \
-} while(0)
-
-/** Mask to acess the rxBitField port */
-#define PORT_MASK 0x7f000000
-
-/** return the rxBitField port */
-#define IX_NPE_A_RXBITFIELD_PORT_GET( rxbitfield ) \
-(((rxbitfield) & PORT_MASK) >> 24)
-
-/** set the rxBitField port */
-#define IX_NPE_A_RXBITFIELD_PORT_SET( rxbitfield, port ) \
-do { \
- (rxbitfield) &= ~PORT_MASK; \
- (rxbitfield) |= (((port) << 24) & PORT_MASK); \
-} while(0)
-
-/** Mask to acess the rxBitField vcId */
-#define VCID_MASK 0x00ff0000
-
-/** return the rxBitField vcId */
-#define IX_NPE_A_RXBITFIELD_VCID_GET( rxbitfield ) \
-(((rxbitfield) & VCID_MASK) >> 16)
-
-/** set the rxBitField vcId */
-#define IX_NPE_A_RXBITFIELD_VCID_SET( rxbitfield, vcid ) \
-do { \
- (rxbitfield) &= ~VCID_MASK; \
- (rxbitfield) |= (((vcid) << 16) & VCID_MASK); \
-} while(0)
-
-/** Mask to acess the rxBitField mbuf size */
-#define CURRMBUFSIZE_MASK 0x0000ffff
-
-/** return the rxBitField mbuf size */
-#define IX_NPE_A_RXBITFIELD_CURRMBUFSIZE_GET( rxbitfield ) \
-((rxbitfield) & CURRMBUFSIZE_MASK)
-
-/** set the rxBitField mbuf size */
-#define IX_NPE_A_RXBITFIELD_CURRMBUFSIZE_SET( rxbitfield, currmbufsize ) \
-do { \
- (rxbitfield) &= ~CURRMBUFSIZE_MASK; \
- (rxbitfield) |= ((currmbufsize) & CURRMBUFSIZE_MASK); \
-} while(0)
-
-
-
-/**
- * @brief Tx Descriptor definition
- */
-typedef struct
-{
- UINT8 port; /**< Tx Port number */
- UINT8 aalType; /**< AAL Type */
- UINT16 currMbufLen; /**< mbuf length */
- UINT32 atmCellHeader; /**< ATM cell header */
- IX_OSAL_MBUF *pCurrMbuf; /**< pointer to mbuf */
- unsigned char *pCurrMbufData; /**< Pointer to mbuf->dat */
- IX_OSAL_MBUF *pNextMbuf; /**< Pointer to next mbuf */
- UINT32 totalLen; /**< Total Length */
- UINT32 aal5CrcResidue; /**< AAL5 CRC Residue */
-} IxNpeA_TxAtmVc;
-
-/* Changes to field sizes or orders must be reflected in the offset
- * definitions above. */
-
-
-
-
-/**
- * @brief Rx Descriptor definition
- */
-typedef struct
-{
- UINT32 rxBitField; /**< Recieved bit field */
- UINT32 atmCellHeader; /**< ATM Cell Header */
- UINT32 rsvdWord0; /**< Reserved field */
- UINT16 currMbufLen; /**< Mbuf Length */
- UINT8 timeLimit; /**< Payload Reassembly timeLimit (used for aal0_xx only) */
- UINT8 rsvdByte0; /**< Reserved field */
- UINT32 rsvdWord1; /**< Reserved field */
- IX_OSAL_MBUF *pCurrMbuf; /**< Pointer to current mbuf */
- unsigned char *pCurrMbufData; /**< Pointer to current mbuf->data */
- IX_OSAL_MBUF *pNextMbuf; /**< Pointer to next mbuf */
- UINT32 totalLen; /**< Total Length */
- UINT32 aal5CrcResidue; /**< AAL5 CRC Residue */
-} IxNpeA_RxAtmVc;
-
-
-/**
- * @brief NPE-A AAL Type
- */
-typedef enum
-{
- IX_NPE_A_AAL_TYPE_INVALID = 0, /**< Invalid AAL type */
- IX_NPE_A_AAL_TYPE_0_48 = 0x1, /**< AAL0 - 48 byte */
- IX_NPE_A_AAL_TYPE_0_52 = 0x2, /**< AAL0 - 52 byte */
- IX_NPE_A_AAL_TYPE_5 = 0x5, /**< AAL5 */
- IX_NPE_A_AAL_TYPE_OAM = 0xF /**< OAM */
-} IxNpeA_AalType;
-
-/**
- * @brief NPE-A Payload format 52-bytes & 48-bytes
- */
-typedef enum
-{
- IX_NPE_A_52_BYTE_PAYLOAD = 0, /**< 52 byte payload */
- IX_NPE_A_48_BYTE_PAYLOAD /**< 48 byte payload */
-} IxNpeA_PayloadFormat;
-
-/**
- * @brief HSS Packetized NpePacket Descriptor Structure
- */
-typedef struct
-{
- UINT8 status; /**< Status of the packet passed to the client */
- UINT8 errorCount; /**< Number of errors */
- UINT8 chainCount; /**< Mbuf chain count e.g. 0 - No mbuf chain */
- UINT8 rsvdByte0; /**< Reserved byte to make the descriptor word align */
-
- UINT16 packetLength; /**< Packet Length */
- UINT16 rsvdShort0; /**< Reserved short to make the descriptor a word align */
-
- IX_OSAL_MBUF *pRootMbuf; /**< Pointer to Root mbuf */
- IX_OSAL_MBUF *pNextMbuf; /**< Pointer to next mbuf */
- UINT8 *pMbufData; /**< Pointer to the current mbuf->data */
- UINT32 mbufLength; /**< Current mbuf length */
-
-} IxNpeA_NpePacketDescriptor;
-
-
-#endif
-/**
- *@}
- */
-
-#endif /* __doxygen_HIDE */
+++ /dev/null
-/**
- * @file IxNpeDl.h
- *
- * @date 14 December 2001
-
- * @brief This file contains the public API of the IXP400 NPE Downloader
- * component.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeDl IXP400 NPE-Downloader (IxNpeDl) API
- *
- * @brief The Public API for the IXP400 NPE Downloader
- *
- * @{
- */
-
-#ifndef IXNPEDL_H
-#define IXNPEDL_H
-
-/*
- * Put the user defined include files required
- */
-#include "IxOsalTypes.h"
-#include "IxNpeMicrocode.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-/**
- * @def IX_NPEDL_PARAM_ERR
- *
- * @brief NpeDl function return value for a parameter error
- */
-#define IX_NPEDL_PARAM_ERR 2
-
-/**
- * @def IX_NPEDL_RESOURCE_ERR
- *
- * @brief NpeDl function return value for a resource error
- */
-#define IX_NPEDL_RESOURCE_ERR 3
-
-/**
- * @def IX_NPEDL_CRITICAL_NPE_ERR
- *
- * @brief NpeDl function return value for a Critical NPE error occuring during
- download. Assume NPE is left in unstable condition if this value is
- returned or NPE is hang / halt.
- */
-#define IX_NPEDL_CRITICAL_NPE_ERR 4
-
-/**
- * @def IX_NPEDL_CRITICAL_MICROCODE_ERR
- *
- * @brief NpeDl function return value for a Critical Microcode error
- * discovered during download. Assume NPE is left in unstable condition
- * if this value is returned.
- */
-#define IX_NPEDL_CRITICAL_MICROCODE_ERR 5
-
-/**
- * @def IX_NPEDL_DEVICE_ERR
- *
- * @brief NpeDl function return value when image being downloaded
- * is not meant for the device in use
- */
-#define IX_NPEDL_DEVICE_ERR 6
-
-/**
- * @defgroup NPEImageID IXP400 NPE Image ID Definition
- *
- * @ingroup IxNpeDl
- *
- * @brief Definition of NPE Image ID to be passed to ixNpeDlNpeInitAndStart()
- * as input of type UINT32 which has the following fields format:
- *
- * Field [Bit Location] <BR>
- * -------------------- <BR>
- * Device ID [31 - 28] <BR>
- * NPE ID [27 - 24] <BR>
- * NPE Functionality ID [23 - 16] <BR>
- * Major Release Number [15 - 8] <BR>
- * Minor Release Number [7 - 0] <BR>
- *
- *
- * @{
- */
-
-/**
- * @def IX_NPEDL_NPEIMAGE_FIELD_MASK
- *
- * @brief Mask for NPE Image ID's Field
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define IX_NPEDL_NPEIMAGE_FIELD_MASK 0xff
-
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEID_MASK
- *
- * @brief Mask for NPE Image NPE ID's Field
- *
- */
-#define IX_NPEDL_NPEIMAGE_NPEID_MASK 0xf
-
-/**
- * @def IX_NPEDL_NPEIMAGE_DEVICEID_MASK
- *
- * @brief Mask for NPE Image Device ID's Field
- *
- */
-#define IX_NPEDL_NPEIMAGE_DEVICEID_MASK 0xf
-
-/**
- * @def IX_NPEDL_NPEIMAGE_BIT_LOC_NPEID
- *
- * @brief Location of NPE ID field in term of bit.
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define IX_NPEDL_NPEIMAGE_BIT_LOC_NPEID 24
-
-/**
- * @def IX_NPEDL_NPEIMAGE_BIT_LOC_FUNCTIONALITYID
- *
- * @brief Location of Functionality ID field in term of bit.
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define IX_NPEDL_NPEIMAGE_BIT_LOC_FUNCTIONALITYID 16
-
-/**
- * @def IX_NPEDL_NPEIMAGE_BIT_LOC_MAJOR
- *
- * @brief Location of Major Release Number field in term of bit.
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define IX_NPEDL_NPEIMAGE_BIT_LOC_MAJOR 8
-
-/**
- * @def IX_NPEDL_NPEIMAGE_BIT_LOC_MINOR
- *
- * @brief Location of Minor Release Number field in term of bit.
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define IX_NPEDL_NPEIMAGE_BIT_LOC_MINOR 0
-
-/**
- * @} addtogroup NPEImageID
- */
-
-/**
- * @def ixNpeDlMicrocodeImageOverride(x)
- *
- * @brief Map old terminology that uses term "image" to new term
- * "image library"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define ixNpeDlMicrocodeImageOverride(x) ixNpeDlMicrocodeImageLibraryOverride(x)
-
-/**
- * @def IxNpeDlVersionId
- *
- * @brief Map old terminology that uses term "version" to new term
- * "image"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define IxNpeDlVersionId IxNpeDlImageId
-
-/**
- * @def ixNpeDlVersionDownload
- *
- * @brief Map old terminology that uses term "version" to new term
- * "image"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define ixNpeDlVersionDownload(x,y) ixNpeDlImageDownload(x,y)
-
-/**
- * @def ixNpeDlAvailableVersionsCountGet
- *
- * @brief Map old terminology that uses term "version" to new term
- * "image"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define ixNpeDlAvailableVersionsCountGet(x) ixNpeDlAvailableImagesCountGet(x)
-
-/**
- * @def ixNpeDlAvailableVersionsListGet
- *
- * @brief Map old terminology that uses term "version" to new term
- * "image"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define ixNpeDlAvailableVersionsListGet(x,y) ixNpeDlAvailableImagesListGet(x,y)
-
- /**
- * @def ixNpeDlLoadedVersionGet
- *
- * @brief Map old terminology that uses term "version" to new term
- * "image"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define ixNpeDlLoadedVersionGet(x,y) ixNpeDlLoadedImageGet(x,y)
-
- /**
- * @def clientImage
- *
- * @brief Map old terminology that uses term "image" to new term
- * "image library"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define clientImage clientImageLibrary
-
- /**
- * @def versionIdPtr
- *
- * @brief Map old terminology that uses term "version" to new term
- * "image"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define versionIdPtr imageIdPtr
-
- /**
- * @def numVersionsPtr
- *
- * @brief Map old terminology that uses term "version" to new term
- * "image"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define numVersionsPtr numImagesPtr
-
-/**
- * @def versionIdListPtr
- *
- * @brief Map old terminology that uses term "version" to new term
- * "image"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define versionIdListPtr imageIdListPtr
-
-/**
- * @def IxNpeDlBuildId
- *
- * @brief Map old terminology that uses term "buildId" to new term
- * "functionalityId"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define IxNpeDlBuildId IxNpeDlFunctionalityId
-
-/**
- * @def buildId
- *
- * @brief Map old terminology that uses term "buildId" to new term
- * "functionalityId"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define buildId functionalityId
-
-/**
- * @def IX_NPEDL_MicrocodeImage
- *
- * @brief Map old terminology that uses term "image" to new term
- * "image library"
- *
- * @warning <b>THIS #define HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-#define IX_NPEDL_MicrocodeImage IX_NPEDL_MicrocodeImageLibrary
-
-/*
- * Typedefs
- */
-
-/**
- * @typedef IxNpeDlFunctionalityId
- * @brief Used to make up Functionality ID field of Image Id
- *
- * @warning <b>THIS typedef HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-typedef UINT8 IxNpeDlFunctionalityId;
-
-/**
- * @typedef IxNpeDlMajor
- * @brief Used to make up Major Release field of Image Id
- *
- * @warning <b>THIS typedef HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-typedef UINT8 IxNpeDlMajor;
-
-/**
- * @typedef IxNpeDlMinor
- * @brief Used to make up Minor Revision field of Image Id
- *
- * @warning <b>THIS typedef HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-typedef UINT8 IxNpeDlMinor;
-
-/*
- * Enums
- */
-
-/**
- * @brief NpeId numbers to identify NPE A, B or C
- * @note In this context, for IXP425 Silicon (B0):<br>
- * - NPE-A has HDLC, HSS, AAL and UTOPIA Coprocessors.<br>
- * - NPE-B has Ethernet Coprocessor.<br>
- * - NPE-C has Ethernet, AES, DES and HASH Coprocessors.<br>
- * - IXP400 Product Line have different combinations of coprocessors.
- */
-typedef enum
-{
- IX_NPEDL_NPEID_NPEA = 0, /**< Identifies NPE A */
- IX_NPEDL_NPEID_NPEB, /**< Identifies NPE B */
- IX_NPEDL_NPEID_NPEC, /**< Identifies NPE C */
- IX_NPEDL_NPEID_MAX /**< Total Number of NPEs */
-} IxNpeDlNpeId;
-
-/*
- * Structs
- */
-
-/**
- * @brief Image Id to identify each image contained in an image library
- *
- * @warning <b>THIS struct HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart for more information.
- */
-typedef struct
-{
- IxNpeDlNpeId npeId; /**< NPE ID */
- IxNpeDlFunctionalityId functionalityId; /**< Build ID indicates functionality of image */
- IxNpeDlMajor major; /**< Major Release Number */
- IxNpeDlMinor minor; /**< Minor Revision Number */
-} IxNpeDlImageId;
-
-/*
- * Prototypes for interface functions
- */
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlNpeInitAndStart (UINT32 imageId)
- *
- * @brief Stop, reset, download microcode (firmware) and finally start NPE.
- *
- * @param imageId UINT32 [in] - Id of the microcode image to download.
- *
- * This function locates the image specified by the <i>imageId</i> parameter
- * from the default microcode image library which is included internally by
- * this component.
- * It then stops and resets the NPE, loads the firmware image onto the NPE,
- * and then restarts the NPE.
- *
- * @note A list of valid image IDs is included in this header file.
- * See #defines with prefix IX_NPEDL_NPEIMAGE_...
- *
- * @note This function, along with @ref ixNpeDlCustomImageNpeInitAndStart
- * and @ref ixNpeDlLoadedImageFunctionalityGet, supercedes the following
- * functions which are deprecated and will be removed completely in a
- * future release:
- * - @ref ixNpeDlImageDownload
- * - @ref ixNpeDlAvailableImagesCountGet
- * - @ref ixNpeDlAvailableImagesListGet
- * - @ref ixNpeDlLatestImageGet
- * - @ref ixNpeDlLoadedImageGet
- * - @ref ixNpeDlMicrocodeImageLibraryOverride
- * - @ref ixNpeDlNpeExecutionStop
- * - @ref ixNpeDlNpeStopAndReset
- * - @ref ixNpeDlNpeExecutionStart
- *
- * @pre
- * - The Client is responsible for ensuring mutual access to the NPE.
- * @post
- * - The NPE Instruction Pipeline will be cleared if State Information
- * has been downloaded.
- * - If the download fails with a critical error, the NPE may
- * be left in an ususable state.
- * @return
- * - IX_SUCCESS if the download was successful;
- * - IX_NPEDL_PARAM_ERR if a parameter error occured
- * - IX_NPEDL_CRITICAL_NPE_ERR if a critical NPE error occured during
- * download
- * - IX_NPEDL_CRITICAL_MICROCODE_ERR if a critical microcode error
- * occured during download
- * - IX_NPEDL_DEVICE_ERR if the image being loaded is not meant for
- * the device currently running.
- * - IX_FAIL if NPE is not available or image is failed to be located.
- * A warning is issued if the NPE is not present.
- */
-PUBLIC IX_STATUS
-ixNpeDlNpeInitAndStart (UINT32 npeImageId);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlCustomImageNpeInitAndStart (UINT32 *imageLibrary,
- UINT32 imageId)
- *
- * @brief Stop, reset, download microcode (firmware) and finally start NPE
- *
- * @param imageId UINT32 [in] - Id of the microcode image to download.
- *
- * This function locates the image specified by the <i>imageId</i> parameter
- * from the specified microcode image library which is pointed to by the
- * <i>imageLibrary</i> parameter.
- * It then stops and resets the NPE, loads the firmware image onto the NPE,
- * and then restarts the NPE.
- *
- * This is a facility for users who wish to use an image from an external
- * library of NPE firmware images. To use a standard image from the
- * built-in library, see @ref ixNpeDlNpeInitAndStart instead.
- *
- * @note A list of valid image IDs is included in this header file.
- * See #defines with prefix IX_NPEDL_NPEIMAGE_...
- *
- * @note This function, along with @ref ixNpeDlNpeInitAndStart
- * and @ref ixNpeDlLoadedImageFunctionalityGet, supercedes the following
- * functions which are deprecated and will be removed completely in a
- * future release:
- * - @ref ixNpeDlImageDownload
- * - @ref ixNpeDlAvailableImagesCountGet
- * - @ref ixNpeDlAvailableImagesListGet
- * - @ref ixNpeDlLatestImageGet
- * - @ref ixNpeDlLoadedImageGet
- * - @ref ixNpeDlMicrocodeImageLibraryOverride
- * - @ref ixNpeDlNpeExecutionStop
- * - @ref ixNpeDlNpeStopAndReset
- * - @ref ixNpeDlNpeExecutionStart
- *
- * @pre
- * - The Client is responsible for ensuring mutual access to the NPE.
- * - The image library supplied must be in the correct format for use
- * by the NPE Downloader (IxNpeDl) component. Details of the library
- * format are contained in the Functional Specification document for
- * IxNpeDl.
- * @post
- * - The NPE Instruction Pipeline will be cleared if State Information
- * has been downloaded.
- * - If the download fails with a critical error, the NPE may
- * be left in an ususable state.
- * @return
- * - IX_SUCCESS if the download was successful;
- * - IX_NPEDL_PARAM_ERR if a parameter error occured
- * - IX_NPEDL_CRITICAL_NPE_ERR if a critical NPE error occured during
- * download
- * - IX_NPEDL_CRITICAL_MICROCODE_ERR if a critical microcode error
- * occured during download
- * - IX_NPEDL_DEVICE_ERR if the image being loaded is not meant for
- * the device currently running.
- * - IX_FAIL if NPE is not available or image is failed to be located.
- * A warning is issued if the NPE is not present.
- */
-PUBLIC IX_STATUS
-ixNpeDlCustomImageNpeInitAndStart (UINT32 *imageLibrary,
- UINT32 npeImageId);
-
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlLoadedImageFunctionalityGet (IxNpeDlNpeId npeId,
- UINT8 *functionalityId)
- *
- * @brief Gets the functionality of the image last loaded on a particular NPE
- *
- * @param npeId @ref IxNpeDlNpeId [in] - Id of the target NPE.
- * @param functionalityId UINT8* [out] - the functionality ID of the image
- * last loaded on the NPE.
- *
- * This function retrieves the functionality ID of the image most recently
- * downloaded successfully to the specified NPE. If the NPE does not contain
- * a valid image, this function returns a FAIL status.
- *
- * @warning This function is not intended for general use, as a knowledge of
- * how to interpret the functionality ID is required. As such, this function
- * should only be used by other Access Layer components of the IXP400 Software
- * Release.
- *
- * @pre
- *
- * @post
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_NPEDL_PARAM_ERR if a parameter error occured
- * - IX_FAIL if the NPE does not have a valid image loaded
- */
-PUBLIC IX_STATUS
-ixNpeDlLoadedImageFunctionalityGet (IxNpeDlNpeId npeId,
- UINT8 *functionalityId);
-
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn IX_STATUS ixNpeDlMicrocodeImageLibraryOverride (UINT32 *clientImageLibrary)
- *
- * @brief This instructs NPE Downloader to use client-supplied microcode image library.
- *
- * @param clientImageLibrary UINT32* [in] - Pointer to the client-supplied
- * NPE microcode image library
- *
- * This function sets NPE Downloader to use a client-supplied microcode image library
- * instead of the standard image library which is included by the NPE Downloader.
- * <b>This function is provided mainly for increased testability and should not
- * be used in normal circumstances.</b> When not used, NPE Downloader will use
- * a "built-in" image library, local to this component, which should always contain the
- * latest microcode for the NPEs.
- *
- * @warning <b>THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlCustomImageNpeInitAndStart.
- *
- * @pre
- * - <i>clientImageLibrary</i> should point to a microcode image library valid for use
- * by the NPE Downloader component.
- *
- * @post
- * - the client-supplied image library will be used for all subsequent operations
- * performed by the NPE Downloader
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_NPEDL_PARAM_ERR if a parameter error occured
- * - IX_FAIL if the client-supplied image library did not contain a valid signature
- */
-PUBLIC IX_STATUS
-ixNpeDlMicrocodeImageLibraryOverride (UINT32 *clientImageLibrary);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlImageDownload (IxNpeDlImageId *imageIdPtr,
- BOOL verify)
- *
- * @brief Stop, reset, download microcode and finally start NPE.
- *
- * @param imageIdPtr @ref IxNpeDlImageId* [in] - Pointer to Id of the microcode
- * image to download.
- * @param verify BOOL [in] - ON/OFF option to verify the download. If ON
- * (verify == TRUE), the Downloader will read back
- * each word written to the NPE registers to
- * ensure the download operation was successful.
- *
- * Using the <i>imageIdPtr</i>, this function locates a particular image of
- * microcode in the microcode image library in memory, and downloads the microcode
- * to a particular NPE.
- *
- * @warning <b>THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart and @ref ixNpeDlCustomImageNpeInitAndStart.
- *
- * @pre
- * - The Client is responsible for ensuring mutual access to the NPE.
- * - The Client should use ixNpeDlLatestImageGet() to obtain the latest
- * version of the image before attempting download.
- * @post
- * - The NPE Instruction Pipeline will be cleared if State Information
- * has been downloaded.
- * - If the download fails with a critical error, the NPE may
- * be left in an ususable state.
- * @return
- * - IX_SUCCESS if the download was successful;
- * - IX_NPEDL_PARAM_ERR if a parameter error occured
- * - IX_NPEDL_CRITICAL_NPE_ERR if a critical NPE error occured during
- * download
- * - IX_PARAM_CRITICAL_MICROCODE_ERR if a critical microcode error
- * occured during download
- * - IX_FAIL if NPE is not available or image is failed to be located.
- * A warning is issued if the NPE is not present.
- */
-PUBLIC IX_STATUS
-ixNpeDlImageDownload (IxNpeDlImageId *imageIdPtr,
- BOOL verify);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlAvailableImagesCountGet (UINT32 *numImagesPtr)
- *
- * @brief Get the number of Images available in a microcode image library
- *
- * @param numImagesPtr UINT32* [out] - A pointer to the number of images in
- * the image library.
- *
- * Gets the number of images available in the microcode image library.
- * Then returns this in a variable pointed to by <i>numImagesPtr</i>.
- *
- * @warning <b>THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart and @ref ixNpeDlCustomImageNpeInitAndStart.
- *
- * @pre
- * - The Client should declare the variable to which numImagesPtr points
- *
- * @post
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_NPEDL_PARAM_ERR if a parameter error occured
- * - IX_FAIL otherwise
- */
-PUBLIC IX_STATUS
-ixNpeDlAvailableImagesCountGet (UINT32 *numImagesPtr);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlAvailableImagesListGet (IxNpeDlImageId *imageIdListPtr,
- UINT32 *listSizePtr)
- *
- * @brief Get a list of the images available in a microcode image library
- *
- * @param imageIdListPtr @ref IxNpeDlImageId* [out] - Array to contain list of
- * image Ids (memory
- * allocated by Client).
- * @param listSizePtr UINT32* [inout] - As an input, this param should point
- * to the max number of Ids the
- * <i>imageIdListPtr</i> array can
- * hold. NpeDl will replace the input
- * value of this parameter with the
- * number of image Ids actually filled
- * into the array before returning.
- *
- * Finds list of images available in the microcode image library.
- * Fills these into the array pointed to by <i>imageIdListPtr</i>
- *
- * @warning <b>THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart and @ref ixNpeDlCustomImageNpeInitAndStart.
- *
- * @pre
- * - The Client should declare the variable to which numImagesPtr points
- * - The Client should create an array (<i>imageIdListPtr</i>) large
- * enough to contain all the image Ids in the image library
- *
- * @post
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_NPEDL_PARAM_ERR if a parameter error occured
- * - IX_FAIL otherwise
- */
-PUBLIC IX_STATUS
-ixNpeDlAvailableImagesListGet (IxNpeDlImageId *imageIdListPtr,
- UINT32 *listSizePtr);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlLoadedImageGet (IxNpeDlNpeId npeId,
- IxNpeDlImageId *imageIdPtr)
- *
- * @brief Gets the Id of the image currently loaded on a particular NPE
- *
- * @param npeId @ref IxNpeDlNpeId [in] - Id of the target NPE.
- * @param imageIdPtr @ref IxNpeDlImageId* [out] - Pointer to the where the
- * image id should be stored.
- *
- * If an image of microcode was previously downloaded successfully to the NPE
- * by NPE Downloader, this function returns in <i>imageIdPtr</i> the image
- * Id of that image loaded on the NPE.
- *
- * @pre
- * - The Client has allocated memory to the <i>imageIdPtr</i> pointer.
- *
- * @post
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_NPEDL_PARAM_ERR if a parameter error occured
- * - IX_FAIL if the NPE doesn't currently have a image loaded
- */
-PUBLIC IX_STATUS
-ixNpeDlLoadedImageGet (IxNpeDlNpeId npeId,
- IxNpeDlImageId *imageIdPtr);
-
-/**
- * @fn PUBLIC IX_STATUS ixNpeDlLatestImageGet (IxNpeDlNpeId npeId, IxNpeDlFunctionalityId
- functionalityId, IxNpeDlImageId *imageIdPtr)
- *
- * @brief This instructs NPE Downloader to get Id of the latest version for an
- * image that is specified by the client.
- *
- * @param npeId @ref IxNpeDlNpeId [in] - Id of the target NPE.
- * @param functionalityId @ref IxNpeDlFunctionalityId [in] - functionality of the image
- * @param imageIdPtr @ref IxNpeDlImageId* [out] - Pointer to the where the
- * image id should be stored.
- *
- * This function sets NPE Downloader to return the id of the latest version for
- * image. The user will select the image by providing a particular NPE
- * (specifying <i>npeId</i>) with particular functionality (specifying
- * <i>FunctionalityId</i>). The most recent version available as determined by the
- * highest Major and Minor revision numbers is returned in <i>imageIdPtr</i>.
- *
- * @warning <b>THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart and @ref ixNpeDlCustomImageNpeInitAndStart.
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_NPEDL_PARAM_ERR if a parameter error occured
- * - IX_FAIL otherwise
- */
-PUBLIC IX_STATUS
-ixNpeDlLatestImageGet (IxNpeDlNpeId npeId,
- IxNpeDlFunctionalityId functionalityId,
- IxNpeDlImageId *imageIdPtr);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlNpeStopAndReset (IxNpeDlNpeId npeId)
- *
- * @brief Stops and Resets an NPE
- *
- * @param npeId @ref IxNpeDlNpeId [in] - Id of the target NPE.
- *
- * This function performs a soft NPE reset by writing reset values to
- * particular NPE registers. Note that this does not reset NPE co-processors.
- * This implicitly stops NPE code execution before resetting the NPE.
- *
- * @note It is no longer necessary to call this function before downloading
- * a new image to the NPE. It is left on the API only to allow greater control
- * of NPE execution if required. Where appropriate, use @ref ixNpeDlNpeInitAndStart
- * or @ref ixNpeDlCustomImageNpeInitAndStart instead.
- *
- * @warning <b>THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart and @ref ixNpeDlCustomImageNpeInitAndStart.
- *
- * @pre
- * - The Client is responsible for ensuring mutual access to the NPE.
- *
- * @post
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_NPEDL_PARAM_ERR if a parameter error occured
- * - IX_FAIL otherwise
- * - IX_NPEDL_CRITICAL_NPE_ERR failed to reset NPE due to timeout error.
- * Timeout error could happen if NPE hang
- */
-PUBLIC IX_STATUS
-ixNpeDlNpeStopAndReset (IxNpeDlNpeId npeId);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlNpeExecutionStart (IxNpeDlNpeId npeId)
- *
- * @brief Starts code execution on a NPE
- *
- * @param npeId @ref IxNpeDlNpeId [in] - Id of the target NPE
- *
- * Starts execution of code on a particular NPE. A client would typically use
- * this after a download to NPE is performed, to start/restart code execution
- * on the NPE.
- *
- * @note It is no longer necessary to call this function after downloading
- * a new image to the NPE. It is left on the API only to allow greater control
- * of NPE execution if required. Where appropriate, use @ref ixNpeDlNpeInitAndStart
- * or @ref ixNpeDlCustomImageNpeInitAndStart instead.
- *
- * @warning <b>THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart and @ref ixNpeDlCustomImageNpeInitAndStart.
- *
- * @pre
- * - The Client is responsible for ensuring mutual access to the NPE.
- * - Note that this function does not set the NPE Next Program Counter
- * (NextPC), so it should be set beforehand if required by downloading
- * appropriate State Information (using ixNpeDlVersionDownload()).
- *
- * @post
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_NPEDL_PARAM_ERR if a parameter error occured
- * - IX_FAIL otherwise
- */
-PUBLIC IX_STATUS
-ixNpeDlNpeExecutionStart (IxNpeDlNpeId npeId);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlNpeExecutionStop (IxNpeDlNpeId npeId)
- *
- * @brief Stops code execution on a NPE
- *
- * @param npeId @ref IxNpeDlNpeId [in] - Id of the target NPE
- *
- * Stops execution of code on a particular NPE. This would typically be used
- * by a client before a download to NPE is performed, to stop code execution on
- * an NPE, unless ixNpeDlNpeStopAndReset() is used instead. Unlike
- * ixNpeDlNpeStopAndReset(), this function only halts the NPE and leaves
- * all registers and settings intact. This is useful, for example, between
- * stages of a multi-stage download, to stop the NPE prior to downloading the
- * next image while leaving the current state of the NPE intact..
- *
- * @warning <b>THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.</b>
- * It will be removed in a future release.
- * See @ref ixNpeDlNpeInitAndStart and @ref ixNpeDlCustomImageNpeInitAndStart.
- *
- * @pre
- * - The Client is responsible for ensuring mutual access to the NPE.
- *
- * @post
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_NPEDL_PARAM_ERR if a parameter error occured
- * - IX_FAIL otherwise
- */
-PUBLIC IX_STATUS
-ixNpeDlNpeExecutionStop (IxNpeDlNpeId npeId);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC IX_STATUS ixNpeDlUnload (void)
- *
- * @brief This function will uninitialise the IxNpeDl component.
- *
- * This function will uninitialise the IxNpeDl component. It should only be
- * called once, and only if the IxNpeDl component has already been initialised by
- * calling any of the following functions:
- * - @ref ixNpeDlNpeInitAndStart
- * - @ref ixNpeDlCustomImageNpeInitAndStart
- * - @ref ixNpeDlImageDownload (deprecated)
- * - @ref ixNpeDlNpeStopAndReset (deprecated)
- * - @ref ixNpeDlNpeExecutionStop (deprecated)
- * - @ref ixNpeDlNpeExecutionStart (deprecated)
- *
- * If possible, this function should be called before a soft reboot or unloading
- * a kernel module to perform any clean up operations required for IxNpeDl.
- *
- * The following actions will be performed by this function:
- * - Unmapping of any kernel memory mapped by IxNpeDl
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_FAIL otherwise
- */
-
-PUBLIC IX_STATUS
-ixNpeDlUnload (void);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC void ixNpeDlStatsShow (void)
- *
- * @brief This function will display run-time statistics from the IxNpeDl
- * component
- *
- * @return none
- */
-PUBLIC void
-ixNpeDlStatsShow (void);
-
-/**
- * @ingroup IxNpeDl
- *
- * @fn PUBLIC void ixNpeDlStatsReset (void)
- *
- * @brief This function will reset the statistics of the IxNpeDl component
- *
- * @return none
- */
-PUBLIC void
-ixNpeDlStatsReset (void);
-
-#endif /* IXNPEDL_H */
-
-/**
- * @} defgroup IxNpeDl
- */
-
-
+++ /dev/null
-/**
- * @file IxNpeDlImageMgr_p.h
- *
- * @author Intel Corporation
- * @date 14 December 2001
-
- * @brief This file contains the private API for the ImageMgr module
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeDlImageMgr_p IxNpeDlImageMgr_p
- *
- * @brief The private API for the IxNpeDl ImageMgr module
- *
- * @{
- */
-
-#ifndef IXNPEDLIMAGEMGR_P_H
-#define IXNPEDLIMAGEMGR_P_H
-
-
-/*
- * Put the user defined include files required.
- */
-#include "IxNpeDl.h"
-#include "IxOsalTypes.h"
-
-
-/*
- * #defines and macros
- */
-
-/**
- * @def IX_NPEDL_IMAGEMGR_SIGNATURE
- *
- * @brief Signature found as 1st word in a microcode image library
- */
-#define IX_NPEDL_IMAGEMGR_SIGNATURE 0xDEADBEEF
-
-/**
- * @def IX_NPEDL_IMAGEMGR_END_OF_HEADER
- *
- * @brief Marks end of header in a microcode image library
- */
-#define IX_NPEDL_IMAGEMGR_END_OF_HEADER 0xFFFFFFFF
-
-/**
- * @def IX_NPEDL_IMAGEID_NPEID_OFFSET
- *
- * @brief Offset from LSB of NPE ID field in Image ID
- */
-#define IX_NPEDL_IMAGEID_NPEID_OFFSET 24
-
-/**
- * @def IX_NPEDL_IMAGEID_DEVICEID_OFFSET
- *
- * @brief Offset from LSB of Device ID field in Image ID
- */
-#define IX_NPEDL_IMAGEID_DEVICEID_OFFSET 28
-
-/**
- * @def IX_NPEDL_IMAGEID_FUNCTIONID_OFFSET
- *
- * @brief Offset from LSB of Functionality ID field in Image ID
- */
-#define IX_NPEDL_IMAGEID_FUNCTIONID_OFFSET 16
-
-/**
- * @def IX_NPEDL_IMAGEID_MAJOR_OFFSET
- *
- * @brief Offset from LSB of Major revision field in Image ID
- */
-#define IX_NPEDL_IMAGEID_MAJOR_OFFSET 8
-
-/**
- * @def IX_NPEDL_IMAGEID_MINOR_OFFSET
- *
- * @brief Offset from LSB of Minor revision field in Image ID
- */
-#define IX_NPEDL_IMAGEID_MINOR_OFFSET 0
-
-
-/**
- * @def IX_NPEDL_NPEID_FROM_IMAGEID_GET
- *
- * @brief Macro to extract NPE ID field from Image ID
- */
-#define IX_NPEDL_NPEID_FROM_IMAGEID_GET(imageId) \
- (((imageId) >> IX_NPEDL_IMAGEID_NPEID_OFFSET) & \
- IX_NPEDL_NPEIMAGE_NPEID_MASK)
-
-/**
- * @def IX_NPEDL_DEVICEID_FROM_IMAGEID_GET
- *
- * @brief Macro to extract NPE ID field from Image ID
- */
-#define IX_NPEDL_DEVICEID_FROM_IMAGEID_GET(imageId) \
- (((imageId) >> IX_NPEDL_IMAGEID_DEVICEID_OFFSET) & \
- IX_NPEDL_NPEIMAGE_DEVICEID_MASK)
-
-/**
- * @def IX_NPEDL_FUNCTIONID_FROM_IMAGEID_GET
- *
- * @brief Macro to extract Functionality ID field from Image ID
- */
-#define IX_NPEDL_FUNCTIONID_FROM_IMAGEID_GET(imageId) \
- (((imageId) >> IX_NPEDL_IMAGEID_FUNCTIONID_OFFSET) & \
- IX_NPEDL_NPEIMAGE_FIELD_MASK)
-
-/**
- * @def IX_NPEDL_MAJOR_FROM_IMAGEID_GET
- *
- * @brief Macro to extract Major revision field from Image ID
- */
-#define IX_NPEDL_MAJOR_FROM_IMAGEID_GET(imageId) \
- (((imageId) >> IX_NPEDL_IMAGEID_MAJOR_OFFSET) & \
- IX_NPEDL_NPEIMAGE_FIELD_MASK)
-
-/**
- * @def IX_NPEDL_MINOR_FROM_IMAGEID_GET
- *
- * @brief Macro to extract Minor revision field from Image ID
- */
-#define IX_NPEDL_MINOR_FROM_IMAGEID_GET(imageId) \
- (((imageId) >> IX_NPEDL_IMAGEID_MINOR_OFFSET) & \
- IX_NPEDL_NPEIMAGE_FIELD_MASK)
-
-
-/*
- * Prototypes for interface functions
- */
-
-/**
- * @fn IX_STATUS ixNpeDlImageMgrMicrocodeImageLibraryOverride (UINT32 *clientImageLibrary)
- *
- * @brief This instructs NPE Downloader to use client-supplied microcode image library.
- *
- * This function sets NPE Downloader to use a client-supplied microcode image library
- * instead of the standard image library which is included by the NPE Downloader.
- *
- * @note THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.
- * It will be removed in a future release.
- * See API header file IxNpeDl.h for more information.
- *
- * @pre
- * - <i>clientImageLibrary</i> should point to a microcode image library valid for use
- * by the NPE Downloader component.
- *
- * @post
- * - the client-supplied image uibrary will be used for all subsequent operations
- * performed by the NPE Downloader
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_FAIL if the client-supplied image library did not contain a valid signature
- */
-IX_STATUS
-ixNpeDlImageMgrMicrocodeImageLibraryOverride (UINT32 *clientImageLibrary);
-
-
-/**
- * @fn IX_STATUS ixNpeDlImageMgrImageListExtract (IxNpeDlImageId *imageListPtr,
- UINT32 *numImages)
- *
- * @brief Extracts a list of images available in the NPE microcode image library.
- *
- * @param IxNpeDlImageId* [out] imageListPtr - pointer to array to contain
- * a list of images. If NULL,
- * only the number of images
- * is returned (in
- * <i>numImages</i>)
- * @param UINT32* [inout] numImages - As input, it points to a variable
- * containing the number of images which
- * can be stored in the
- * <i>imageListPtr</i> array. Its value
- * is ignored as input if
- * <i>imageListPtr</i> is NULL. As an
- * output, it will contain number of
- * images in the image library.
- *
- * This function reads the header of the microcode image library and extracts a list of the
- * images available in the image library. It can also be used to find the number of
- * images in the image library.
- *
- * @note THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.
- * It will be removed in a future release.
- * See API header file IxNpeDl.h for more information.
- *
- * @pre
- * - if <i>imageListPtr</i> != NULL, <i>numImages</i> should reflect the
- * number of image Id elements the <i>imageListPtr</i> can contain.
- *
- * @post
- * - <i>numImages</i> will reflect the number of image Id's found in the
- * microcode image library.
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_FAIL otherwise
- */
-IX_STATUS
-ixNpeDlImageMgrImageListExtract (IxNpeDlImageId *imageListPtr,
- UINT32 *numImages);
-
-
-/**
- * @fn IX_STATUS ixNpeDlImageMgrImageLocate (IxNpeDlImageId *imageId,
- UINT32 **imagePtr,
- UINT32 *imageSize)
- *
- * @brief Finds a image block in the NPE microcode image library.
- *
- * @param IxNpeDlImageId* [in] imageId - the id of the image to locate
- * @param UINT32** [out] imagePtr - pointer to the image in memory
- * @param UINT32* [out] imageSize - size (in 32-bit words) of image
- *
- * This function examines the header of the microcode image library for the location
- * and size of the specified image.
- *
- * @note THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.
- * It will be removed in a future release.
- * See API header file IxNpeDl.h for more information.
- *
- * @pre
- *
- * @post
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_FAIL otherwise
- */
-IX_STATUS
-ixNpeDlImageMgrImageLocate (IxNpeDlImageId *imageId,
- UINT32 **imagePtr,
- UINT32 *imageSize);
-
-/**
- * @fn IX_STATUS ixNpeDlImageMgrLatestImageExtract (IxNpeDlImageId *imageId)
- *
- * @brief Finds the most recent version of an image in the NPE image library.
- *
- * @param IxNpeDlImageId* [inout] imageId - the id of the image
- *
- * This function determines the most recent version of a specified image by its
- * higest major release and minor revision numbers
- *
- * @note THIS FUNCTION HAS BEEN DEPRECATED AND SHOULD NOT BE USED.
- * It will be removed in a future release.
- * See API header file IxNpeDl.h for more information.
- *
- * @pre
- *
- * @post
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_FAIL otherwise
- */
-IX_STATUS
-ixNpeDlImageMgrLatestImageExtract (IxNpeDlImageId *imageId);
-
-/**
- * @fn void ixNpeDlImageMgrStatsShow (void)
- *
- * @brief This function will display the statistics of the IxNpeDl ImageMgr
- * module
- *
- * @return none
- */
-void
-ixNpeDlImageMgrStatsShow (void);
-
-
-/**
- * @fn void ixNpeDlImageMgrStatsReset (void)
- *
- * @brief This function will reset the statistics of the IxNpeDl ImageMgr
- * module
- *
- * @return none
- */
-void
-ixNpeDlImageMgrStatsReset (void);
-
-
-/**
- * @fn IX_STATUS ixNpeDlImageMgrImageGet (UINT32 *imageLibrary,
- UINT32 imageId,
- UINT32 **imagePtr,
- UINT32 *imageSize)
- *
- * @brief Finds a image block in the NPE microcode image library.
- *
- * @param UINT32* [in] imageLibrary - the image library to use
- * @param UINT32 [in] imageId - the id of the image to locate
- * @param UINT32** [out] imagePtr - pointer to the image in memory
- * @param UINT32* [out] imageSize - size (in 32-bit words) of image
- *
- * This function examines the header of the specified microcode image library
- * for the location and size of the specified image. It returns a pointer to
- * the image in the <i>imagePtr</i> parameter.
- * If no image library is specified (imageLibrary == NULL), then the default
- * built-in image library will be used.
- *
- * @pre
- *
- * @post
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_FAIL otherwise
- */
-IX_STATUS
-ixNpeDlImageMgrImageFind (UINT32 *imageLibrary,
- UINT32 imageId,
- UINT32 **imagePtr,
- UINT32 *imageSize);
-
-
-#endif /* IXNPEDLIMAGEMGR_P_H */
-
-/**
- * @} defgroup IxNpeDlImageMgr_p
- */
+++ /dev/null
-/**
- * @file IxNpeDlMacros_p.h
- *
- * @author Intel Corporation
- * @date 21 January 2002
- *
- * @brief This file contains the macros for the IxNpeDl component.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeDlMacros_p IxNpeDlMacros_p
- *
- * @brief Macros for the IxNpeDl component.
- *
- * @{
- */
-
-#ifndef IXNPEDLMACROS_P_H
-#define IXNPEDLMACROS_P_H
-
-
-/*
- * Put the user defined include files required.
- */
-#if (CPU != XSCALE)
-/* To support IxNpeDl unit tests... */
-#include <stdio.h>
-#include "test/IxNpeDlTestReg.h"
-
-#else
-#include "IxOsal.h"
-
-#endif
-
-
-/*
- * Typedefs
- */
-
-/**
- * @typedef IxNpeDlTraceTypes
- * @brief Enumeration defining IxNpeDl trace levels
- */
-typedef enum
-{
- IX_NPEDL_TRACE_OFF, /**< no trace */
- IX_NPEDL_DEBUG, /**< debug */
- IX_NPEDL_FN_ENTRY_EXIT /**< function entry/exit */
-} IxNpeDlTraceTypes;
-
-
-/*
- * #defines and macros.
- */
-
-/* Implementation of the following macros for use with IxNpeDl unit test code */
-#if (CPU != XSCALE)
-
-
-/**
- * @def IX_NPEDL_TRACE_LEVEL
- *
- * @brief IxNpeDl debug trace level
- */
-#define IX_NPEDL_TRACE_LEVEL IX_NPEDL_FN_ENTRY_EXIT
-
-/**
- * @def IX_NPEDL_ERROR_REPORT
- *
- * @brief Mechanism for reporting IxNpeDl software errors
- *
- * @param char* [in] STR - Error string to report
- *
- * This macro simply prints the error string passed.
- * Intended for use with IxNpeDl unit test code.
- *
- * @return none
- */
-#define IX_NPEDL_ERROR_REPORT(STR) printf ("IxNpeDl ERROR: %s\n", (STR));
-
-/**
- * @def IX_NPEDL_WARNING_REPORT
- *
- * @brief Mechanism for reporting IxNpeDl software errors
- *
- * @param char* [in] STR - Error string to report
- *
- * This macro simply prints the error string passed.
- * Intended for use with IxNpeDl unit test code.
- *
- * @return none
- */
-#define IX_NPEDL_WARNING_REPORT(STR) printf ("IxNpeDl WARNING: %s\n", (STR));
-
-/**
- * @def IX_NPEDL_TRACE0
- *
- * @brief Mechanism for tracing debug for the IxNpeDl component, for no arguments
- *
- * @param unsigned [in] LEVEL - one of IxNpeDlTraceTypes enumerated values
- * @param char* [in] STR - Trace string
- *
- * This macro simply prints the trace string passed, if the level is supported.
- * Intended for use with IxNpeDl unit test code.
- *
- * @return none
- */
-#define IX_NPEDL_TRACE0(LEVEL, STR) \
-{ \
- if (LEVEL <= IX_NPEDL_TRACE_LEVEL) \
- { \
- printf ("IxNpeDl TRACE: "); \
- printf ((STR)); \
- printf ("\n"); \
- } \
-}
-
- /**
- * @def IX_NPEDL_TRACE1
- *
- * @brief Mechanism for tracing debug for the IxNpeDl component, with 1 argument
- *
- * @param unsigned [in] LEVEL - one of IxNpeDlTraceTypes enumerated values
- * @param char* [in] STR - Trace string
- * @param argType [in] ARG1 - Argument to trace
- *
- * This macro simply prints the trace string passed, if the level is supported.
- * Intended for use with IxNpeDl unit test code.
- *
- * @return none
- */
-#define IX_NPEDL_TRACE1(LEVEL, STR, ARG1) \
-{ \
- if (LEVEL <= IX_NPEDL_TRACE_LEVEL) \
- { \
- printf ("IxNpeDl TRACE: "); \
- printf (STR, ARG1); \
- printf ("\n"); \
- } \
-}
-
-/**
- * @def IX_NPEDL_TRACE2
- *
- * @brief Mechanism for tracing debug for the IxNpeDl component, with 2 arguments
- *
- * @param unsigned [in] LEVEL - one of IxNpeDlTraceTypes enumerated values
- * @param char* [in] STR - Trace string
- * @param argType [in] ARG1 - Argument to trace
- * @param argType [in] ARG2 - Argument to trace
- *
- * This macro simply prints the trace string passed, if the level is supported.
- * Intended for use with IxNpeDl unit test code.
- *
- * @return none
- */
-#define IX_NPEDL_TRACE2(LEVEL, STR, ARG1, ARG2) \
-{ \
- if (LEVEL <= IX_NPEDL_TRACE_LEVEL) \
- { \
- printf ("IxNpeDl TRACE: "); \
- printf (STR, ARG1, ARG2); \
- printf ("\n"); \
- } \
-}
-
-
-/**
- * @def IX_NPEDL_REG_WRITE
- *
- * @brief Mechanism for writing to a memory-mapped register
- *
- * @param UINT32 [in] base - Base memory address for this NPE's registers
- * @param UINT32 [in] offset - Offset from base memory address
- * @param UINT32 [in] value - Value to write to register
- *
- * This macro calls a function from Unit Test code to write a register. This
- * allows extra flexibility for unit testing of the IxNpeDl component.
- *
- * @return none
- */
-#define IX_NPEDL_REG_WRITE(base, offset, value) \
-{ \
- ixNpeDlTestRegWrite (base, offset, value); \
-}
-
-
-/**
- * @def IX_NPEDL_REG_READ
- *
- * @brief Mechanism for reading from a memory-mapped register
- *
- * @param UINT32 [in] base - Base memory address for this NPE's registers
- * @param UINT32 [in] offset - Offset from base memory address
- * @param UINT32 *[out] value - Value read from register
- *
- * This macro calls a function from Unit Test code to read a register. This
- * allows extra flexibility for unit testing of the IxNpeDl component.
- *
- * @return none
- */
-#define IX_NPEDL_REG_READ(base, offset, value) \
-{ \
- ixNpeDlTestRegRead (base, offset, value); \
-}
-
-
-/* Implementation of the following macros when integrated with IxOsal */
-#else /* #if (CPU != XSCALE) */
-
-
-/**
- * @def IX_NPEDL_TRACE_LEVEL
- *
- * @brief IxNpeDl debug trace level
- */
-#define IX_NPEDL_TRACE_LEVEL IX_NPEDL_DEBUG
-
-
-/**
- * @def IX_NPEDL_ERROR_REPORT
- *
- * @brief Mechanism for reporting IxNpeDl software errors
- *
- * @param char* [in] STR - Error string to report
- *
- * This macro is used to report IxNpeDl software errors.
- *
- * @return none
- */
-#define IX_NPEDL_ERROR_REPORT(STR) \
- ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, STR, 0, 0, 0, 0, 0, 0);
-
-/**
- * @def IX_NPEDL_WARNING_REPORT
- *
- * @brief Mechanism for reporting IxNpeDl software warnings
- *
- * @param char* [in] STR - Warning string to report
- *
- * This macro is used to report IxNpeDl software warnings.
- *
- * @return none
- */
-#define IX_NPEDL_WARNING_REPORT(STR) \
- ixOsalLog (IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, STR, 0, 0, 0, 0, 0, 0);
-
-
-/**
- * @def IX_NPEDL_TRACE0
- *
- * @brief Mechanism for tracing debug for the IxNpeDl component, for no arguments
- *
- * @param unsigned [in] LEVEL - one of IxNpeDlTraceTypes enumerated values
- * @param char* [in] STR - Trace string
- *
- * This macro simply prints the trace string passed, if the level is supported.
- *
- * @return none
- */
-#define IX_NPEDL_TRACE0(LEVEL, STR) \
-{ \
- if (LEVEL <= IX_NPEDL_TRACE_LEVEL) \
- { \
- if (LEVEL == IX_NPEDL_FN_ENTRY_EXIT) \
- { \
- ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, IX_OSAL_LOG_DEV_STDOUT, STR, 0, 0, 0, 0, 0, 0); \
- } \
- else if (LEVEL == IX_NPEDL_DEBUG) \
- { \
- ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, STR, 0, 0, 0, 0, 0, 0); \
- } \
- } \
-}
-
-/**
- * @def IX_NPEDL_TRACE1
- *
- * @brief Mechanism for tracing debug for the IxNpeDl component, with 1 argument
- *
- * @param unsigned [in] LEVEL - one of IxNpeDlTraceTypes enumerated values
- * @param char* [in] STR - Trace string
- * @param argType [in] ARG1 - Argument to trace
- *
- * This macro simply prints the trace string passed, if the level is supported.
- *
- * @return none
- */
-#define IX_NPEDL_TRACE1(LEVEL, STR, ARG1) \
-{ \
- if (LEVEL <= IX_NPEDL_TRACE_LEVEL) \
- { \
- if (LEVEL == IX_NPEDL_FN_ENTRY_EXIT) \
- { \
- ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, IX_OSAL_LOG_DEV_STDOUT, STR, ARG1, 0, 0, 0, 0, 0); \
- } \
- else if (LEVEL == IX_NPEDL_DEBUG) \
- { \
- ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, STR, ARG1, 0, 0, 0, 0, 0); \
- } \
- } \
-}
-
-/**
- * @def IX_NPEDL_TRACE2
- *
- * @brief Mechanism for tracing debug for the IxNpeDl component, with 2 arguments
- *
- * @param unsigned [in] LEVEL - one of IxNpeDlTraceTypes enumerated values
- * @param char* [in] STR - Trace string
- * @param argType [in] ARG1 - Argument to trace
- * @param argType [in] ARG2 - Argument to trace
- *
- * This macro simply prints the trace string passed, if the level is supported.
- *
- * @return none
- */
-#define IX_NPEDL_TRACE2(LEVEL, STR, ARG1, ARG2) \
-{ \
- if (LEVEL <= IX_NPEDL_TRACE_LEVEL) \
- { \
- if (LEVEL == IX_NPEDL_FN_ENTRY_EXIT) \
- { \
- ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, IX_OSAL_LOG_DEV_STDOUT, STR, ARG1, ARG2, 0, 0, 0, 0); \
- } \
- else if (LEVEL == IX_NPEDL_DEBUG) \
- { \
- ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, STR, ARG1, ARG2, 0, 0, 0, 0); \
- } \
- } \
-}
-
-/**
- * @def IX_NPEDL_REG_WRITE
- *
- * @brief Mechanism for writing to a memory-mapped register
- *
- * @param UINT32 [in] base - Base memory address for this NPE's registers
- * @param UINT32 [in] offset - Offset from base memory address
- * @param UINT32 [in] value - Value to write to register
- *
- * This macro forms the address of the register from base address + offset, and
- * dereferences that address to write the contents of the register.
- *
- * @return none
- */
-#define IX_NPEDL_REG_WRITE(base, offset, value) \
- IX_OSAL_WRITE_LONG(((base) + (offset)), (value))
-
-
-
-/**
- * @def IX_NPEDL_REG_READ
- *
- * @brief Mechanism for reading from a memory-mapped register
- *
- * @param UINT32 [in] base - Base memory address for this NPE's registers
- * @param UINT32 [in] offset - Offset from base memory address
- * @param UINT32 *[out] value - Value read from register
- *
- * This macro forms the address of the register from base address + offset, and
- * dereferences that address to read the register contents.
- *
- * @return none
- */
-#define IX_NPEDL_REG_READ(base, offset, value) \
- *(value) = IX_OSAL_READ_LONG(((base) + (offset)))
-
-#endif /* #if (CPU != XSCALE) */
-
-#endif /* IXNPEDLMACROS_P_H */
-
-/**
- * @} defgroup IxNpeDlMacros_p
- */
+++ /dev/null
-/**
- * @file IxNpeDlNpeMgrEcRegisters_p.h
- *
- * @author Intel Corporation
- * @date 14 December 2001
-
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-
-#ifndef IXNPEDLNPEMGRECREGISTERS_P_H
-#define IXNPEDLNPEMGRECREGISTERS_P_H
-
-#include "IxOsal.h"
-
-/*
- * Base Memory Addresses for accessing NPE registers
- */
-
-#define IX_NPEDL_NPE_BASE (IX_OSAL_IXP400_PERIPHERAL_PHYS_BASE)
-
-#define IX_NPEDL_NPEA_OFFSET (0x6000) /**< NPE-A register base offset */
-#define IX_NPEDL_NPEB_OFFSET (0x7000) /**< NPE-B register base offset */
-#define IX_NPEDL_NPEC_OFFSET (0x8000) /**< NPE-C register base offset */
-
-/**
- * @def IX_NPEDL_NPEBASEADDRESS_NPEA
- * @brief Base Memory Address of NPE-A Configuration Bus registers
- */
-#define IX_NPEDL_NPEBASEADDRESS_NPEA (IX_NPEDL_NPE_BASE + IX_NPEDL_NPEA_OFFSET)
-
-/**
- * @def IX_NPEDL_NPEBASEADDRESS_NPEB
- * @brief Base Memory Address of NPE-B Configuration Bus registers
- */
-#define IX_NPEDL_NPEBASEADDRESS_NPEB (IX_NPEDL_NPE_BASE + IX_NPEDL_NPEB_OFFSET)
-
-/**
- * @def IX_NPEDL_NPEBASEADDRESS_NPEC
- * @brief Base Memory Address of NPE-C Configuration Bus registers
- */
-#define IX_NPEDL_NPEBASEADDRESS_NPEC (IX_NPEDL_NPE_BASE + IX_NPEDL_NPEC_OFFSET)
-
-
-/*
- * Instruction Memory Size (in words) for each NPE
- */
-
-/**
- * @def IX_NPEDL_INS_MEMSIZE_WORDS_NPEA
- * @brief Size (in words) of NPE-A Instruction Memory
- */
-#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEA 4096
-
-/**
- * @def IX_NPEDL_INS_MEMSIZE_WORDS_NPEB
- * @brief Size (in words) of NPE-B Instruction Memory
- */
-#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEB 2048
-
-/**
- * @def IX_NPEDL_INS_MEMSIZE_WORDS_NPEC
- * @brief Size (in words) of NPE-B Instruction Memory
- */
-#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEC 2048
-
-
-/*
- * Data Memory Size (in words) for each NPE
- */
-
-/**
- * @def IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA
- * @brief Size (in words) of NPE-A Data Memory
- */
-#define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA 2048
-
-/**
- * @def IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB
- * @brief Size (in words) of NPE-B Data Memory
- */
-#define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB 2048
-
-/**
- * @def IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC
- * @brief Size (in words) of NPE-C Data Memory
- */
-#define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC 2048
-
-
-/*
- * Configuration Bus Register offsets (in bytes) from NPE Base Address
- */
-
-/**
- * @def IX_NPEDL_REG_OFFSET_EXAD
- * @brief Offset (in bytes) of EXAD (Execution Address) register from NPE Base
- * Address
- */
-#define IX_NPEDL_REG_OFFSET_EXAD 0x00000000
-
-/**
- * @def IX_NPEDL_REG_OFFSET_EXDATA
- * @brief Offset (in bytes) of EXDATA (Execution Data) register from NPE Base
- * Address
- */
-#define IX_NPEDL_REG_OFFSET_EXDATA 0x00000004
-
-/**
- * @def IX_NPEDL_REG_OFFSET_EXCTL
- * @brief Offset (in bytes) of EXCTL (Execution Control) register from NPE Base
- * Address
- */
-#define IX_NPEDL_REG_OFFSET_EXCTL 0x00000008
-
-/**
- * @def IX_NPEDL_REG_OFFSET_EXCT
- * @brief Offset (in bytes) of EXCT (Execution Count) register from NPE Base
- * Address
- */
-#define IX_NPEDL_REG_OFFSET_EXCT 0x0000000C
-
-/**
- * @def IX_NPEDL_REG_OFFSET_AP0
- * @brief Offset (in bytes) of AP0 (Action Point 0) register from NPE Base
- * Address
- */
-#define IX_NPEDL_REG_OFFSET_AP0 0x00000010
-
-/**
- * @def IX_NPEDL_REG_OFFSET_AP1
- * @brief Offset (in bytes) of AP1 (Action Point 1) register from NPE Base
- * Address
- */
-#define IX_NPEDL_REG_OFFSET_AP1 0x00000014
-
-/**
- * @def IX_NPEDL_REG_OFFSET_AP2
- * @brief Offset (in bytes) of AP2 (Action Point 2) register from NPE Base
- * Address
- */
-#define IX_NPEDL_REG_OFFSET_AP2 0x00000018
-
-/**
- * @def IX_NPEDL_REG_OFFSET_AP3
- * @brief Offset (in bytes) of AP3 (Action Point 3) register from NPE Base
- * Address
- */
-#define IX_NPEDL_REG_OFFSET_AP3 0x0000001C
-
-/**
- * @def IX_NPEDL_REG_OFFSET_WFIFO
- * @brief Offset (in bytes) of WFIFO (Watchpoint FIFO) register from NPE Base
- * Address
- */
-#define IX_NPEDL_REG_OFFSET_WFIFO 0x00000020
-
-/**
- * @def IX_NPEDL_REG_OFFSET_WC
- * @brief Offset (in bytes) of WC (Watch Count) register from NPE Base
- * Address
- */
-#define IX_NPEDL_REG_OFFSET_WC 0x00000024
-
-/**
- * @def IX_NPEDL_REG_OFFSET_PROFCT
- * @brief Offset (in bytes) of PROFCT (Profile Count) register from NPE Base
- * Address
- */
-#define IX_NPEDL_REG_OFFSET_PROFCT 0x00000028
-
-/**
- * @def IX_NPEDL_REG_OFFSET_STAT
- * @brief Offset (in bytes) of STAT (Messaging Status) register from NPE Base
- * Address
- */
-#define IX_NPEDL_REG_OFFSET_STAT 0x0000002C
-
-/**
- * @def IX_NPEDL_REG_OFFSET_CTL
- * @brief Offset (in bytes) of CTL (Messaging Control) register from NPE Base
- * Address
- */
-#define IX_NPEDL_REG_OFFSET_CTL 0x00000030
-
-/**
- * @def IX_NPEDL_REG_OFFSET_MBST
- * @brief Offset (in bytes) of MBST (Mailbox Status) register from NPE Base
- * Address
- */
-#define IX_NPEDL_REG_OFFSET_MBST 0x00000034
-
-/**
- * @def IX_NPEDL_REG_OFFSET_FIFO
- * @brief Offset (in bytes) of FIFO (messaging in/out FIFO) register from NPE
- * Base Address
- */
-#define IX_NPEDL_REG_OFFSET_FIFO 0x00000038
-
-
-/*
- * Non-zero reset values for the Configuration Bus registers
- */
-
-/**
- * @def IX_NPEDL_REG_RESET_FIFO
- * @brief Reset value for Mailbox (MBST) register
- * NOTE that if used, it should be complemented with an NPE intruction
- * to clear the Mailbox at the NPE side as well
- */
-#define IX_NPEDL_REG_RESET_MBST 0x0000F0F0
-
-
-/*
- * Bit-masks used to read/write particular bits in Configuration Bus registers
- */
-
-/**
- * @def IX_NPEDL_MASK_WFIFO_VALID
- * @brief Masks the VALID bit in the WFIFO register
- */
-#define IX_NPEDL_MASK_WFIFO_VALID 0x80000000
-
-/**
- * @def IX_NPEDL_MASK_STAT_OFNE
- * @brief Masks the OFNE bit in the STAT register
- */
-#define IX_NPEDL_MASK_STAT_OFNE 0x00010000
-
-/**
- * @def IX_NPEDL_MASK_STAT_IFNE
- * @brief Masks the IFNE bit in the STAT register
- */
-#define IX_NPEDL_MASK_STAT_IFNE 0x00080000
-
-
-/*
- * EXCTL (Execution Control) Register commands
-*/
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_NPE_STEP
- * @brief EXCTL Command to Step execution of an NPE Instruction
- */
-
-#define IX_NPEDL_EXCTL_CMD_NPE_STEP 0x01
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_NPE_START
- * @brief EXCTL Command to Start NPE execution
- */
-#define IX_NPEDL_EXCTL_CMD_NPE_START 0x02
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_NPE_STOP
- * @brief EXCTL Command to Stop NPE execution
- */
-#define IX_NPEDL_EXCTL_CMD_NPE_STOP 0x03
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE
- * @brief EXCTL Command to Clear NPE instruction pipeline
- */
-#define IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE 0x04
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_RD_INS_MEM
- * @brief EXCTL Command to read NPE instruction memory at address in EXAD
- * register and return value in EXDATA register
- */
-#define IX_NPEDL_EXCTL_CMD_RD_INS_MEM 0x10
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_WR_INS_MEM
- * @brief EXCTL Command to write NPE instruction memory at address in EXAD
- * register with data in EXDATA register
- */
-#define IX_NPEDL_EXCTL_CMD_WR_INS_MEM 0x11
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_RD_DATA_MEM
- * @brief EXCTL Command to read NPE data memory at address in EXAD
- * register and return value in EXDATA register
- */
-#define IX_NPEDL_EXCTL_CMD_RD_DATA_MEM 0x12
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_WR_DATA_MEM
- * @brief EXCTL Command to write NPE data memory at address in EXAD
- * register with data in EXDATA register
- */
-#define IX_NPEDL_EXCTL_CMD_WR_DATA_MEM 0x13
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_RD_ECS_REG
- * @brief EXCTL Command to read Execution Access register at address in EXAD
- * register and return value in EXDATA register
- */
-#define IX_NPEDL_EXCTL_CMD_RD_ECS_REG 0x14
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_WR_ECS_REG
- * @brief EXCTL Command to write Execution Access register at address in EXAD
- * register with data in EXDATA register
- */
-#define IX_NPEDL_EXCTL_CMD_WR_ECS_REG 0x15
-
-/**
- * @def IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT
- * @brief EXCTL Command to clear Profile Count register
- */
-#define IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT 0x0C
-
-
-/*
- * EXCTL (Execution Control) Register status bit masks
- */
-
-/**
- * @def IX_NPEDL_EXCTL_STATUS_RUN
- * @brief Masks the RUN status bit in the EXCTL register
- */
-#define IX_NPEDL_EXCTL_STATUS_RUN 0x80000000
-
-/**
- * @def IX_NPEDL_EXCTL_STATUS_STOP
- * @brief Masks the STOP status bit in the EXCTL register
- */
-#define IX_NPEDL_EXCTL_STATUS_STOP 0x40000000
-
-/**
- * @def IX_NPEDL_EXCTL_STATUS_CLEAR
- * @brief Masks the CLEAR status bit in the EXCTL register
- */
-#define IX_NPEDL_EXCTL_STATUS_CLEAR 0x20000000
-
-/**
- * @def IX_NPEDL_EXCTL_STATUS_ECS_K
- * @brief Masks the K (pipeline Klean) status bit in the EXCTL register
- */
-#define IX_NPEDL_EXCTL_STATUS_ECS_K 0x00800000
-
-
-/*
- * Executing Context Stack (ECS) level registers
- */
-
-/**
- * @def IX_NPEDL_ECS_BG_CTXT_REG_0
- * @brief Execution Access register address for register 0 at Backgound
- * Executing Context Stack level
- */
-#define IX_NPEDL_ECS_BG_CTXT_REG_0 0x00
-
-/**
- * @def IX_NPEDL_ECS_BG_CTXT_REG_1
- * @brief Execution Access register address for register 1 at Backgound
- * Executing Context Stack level
- */
-#define IX_NPEDL_ECS_BG_CTXT_REG_1 0x01
-
-/**
- * @def IX_NPEDL_ECS_BG_CTXT_REG_2
- * @brief Execution Access register address for register 2 at Backgound
- * Executing Context Stack level
- */
-#define IX_NPEDL_ECS_BG_CTXT_REG_2 0x02
-
-/**
- * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_0
- * @brief Execution Access register address for register 0 at Priority 1
- * Executing Context Stack level
- */
-#define IX_NPEDL_ECS_PRI_1_CTXT_REG_0 0x04
-
-/**
- * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_1
- * @brief Execution Access register address for register 1 at Priority 1
- * Executing Context Stack level
- */
-#define IX_NPEDL_ECS_PRI_1_CTXT_REG_1 0x05
-
-/**
- * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_2
- * @brief Execution Access register address for register 2 at Priority 1
- * Executing Context Stack level
- */
-#define IX_NPEDL_ECS_PRI_1_CTXT_REG_2 0x06
-
-/**
- * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_0
- * @brief Execution Access register address for register 0 at Priority 2
- * Executing Context Stack level
- */
-#define IX_NPEDL_ECS_PRI_2_CTXT_REG_0 0x08
-
-/**
- * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_1
- * @brief Execution Access register address for register 1 at Priority 2
- * Executing Context Stack level
- */
-#define IX_NPEDL_ECS_PRI_2_CTXT_REG_1 0x09
-
-/**
- * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_2
- * @brief Execution Access register address for register 2 at Priority 2
- * Executing Context Stack level
- */
-#define IX_NPEDL_ECS_PRI_2_CTXT_REG_2 0x0A
-
-/**
- * @def IX_NPEDL_ECS_DBG_CTXT_REG_0
- * @brief Execution Access register address for register 0 at Debug
- * Executing Context Stack level
- */
-#define IX_NPEDL_ECS_DBG_CTXT_REG_0 0x0C
-
-/**
- * @def IX_NPEDL_ECS_DBG_CTXT_REG_1
- * @brief Execution Access register address for register 1 at Debug
- * Executing Context Stack level
- */
-#define IX_NPEDL_ECS_DBG_CTXT_REG_1 0x0D
-
-/**
- * @def IX_NPEDL_ECS_DBG_CTXT_REG_2
- * @brief Execution Access register address for register 2 at Debug
- * Executing Context Stack level
- */
-#define IX_NPEDL_ECS_DBG_CTXT_REG_2 0x0E
-
-/**
- * @def IX_NPEDL_ECS_INSTRUCT_REG
- * @brief Execution Access register address for NPE Instruction Register
- */
-#define IX_NPEDL_ECS_INSTRUCT_REG 0x11
-
-
-/*
- * Execution Access register reset values
- */
-
-/**
- * @def IX_NPEDL_ECS_BG_CTXT_REG_0_RESET
- * @brief Reset value for Execution Access Background ECS level register 0
- */
-#define IX_NPEDL_ECS_BG_CTXT_REG_0_RESET 0xA0000000
-
-/**
- * @def IX_NPEDL_ECS_BG_CTXT_REG_1_RESET
- * @brief Reset value for Execution Access Background ECS level register 1
- */
-#define IX_NPEDL_ECS_BG_CTXT_REG_1_RESET 0x01000000
-
-/**
- * @def IX_NPEDL_ECS_BG_CTXT_REG_2_RESET
- * @brief Reset value for Execution Access Background ECS level register 2
- */
-#define IX_NPEDL_ECS_BG_CTXT_REG_2_RESET 0x00008000
-
-/**
- * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET
- * @brief Reset value for Execution Access Priority 1 ECS level register 0
- */
-#define IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET 0x20000080
-
-/**
- * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET
- * @brief Reset value for Execution Access Priority 1 ECS level register 1
- */
-#define IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET 0x01000000
-
-/**
- * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET
- * @brief Reset value for Execution Access Priority 1 ECS level register 2
- */
-#define IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET 0x00008000
-
-/**
- * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET
- * @brief Reset value for Execution Access Priority 2 ECS level register 0
- */
-#define IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET 0x20000080
-
-/**
- * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET
- * @brief Reset value for Execution Access Priority 2 ECS level register 1
- */
-#define IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET 0x01000000
-
-/**
- * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET
- * @brief Reset value for Execution Access Priority 2 ECS level register 2
- */
-#define IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET 0x00008000
-
-/**
- * @def IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET
- * @brief Reset value for Execution Access Debug ECS level register 0
- */
-#define IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET 0x20000000
-
-/**
- * @def IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET
- * @brief Reset value for Execution Access Debug ECS level register 1
- */
-#define IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET 0x00000000
-
-/**
- * @def IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET
- * @brief Reset value for Execution Access Debug ECS level register 2
- */
-#define IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET 0x001E0000
-
-/**
- * @def IX_NPEDL_ECS_INSTRUCT_REG_RESET
- * @brief Reset value for Execution Access NPE Instruction Register
- */
-#define IX_NPEDL_ECS_INSTRUCT_REG_RESET 0x1003C00F
-
-
-/*
- * masks used to read/write particular bits in Execution Access registers
- */
-
-/**
- * @def IX_NPEDL_MASK_ECS_REG_0_ACTIVE
- * @brief Mask the A (Active) bit in Execution Access Register 0 of all ECS
- * levels
- */
-#define IX_NPEDL_MASK_ECS_REG_0_ACTIVE 0x80000000
-
-/**
- * @def IX_NPEDL_MASK_ECS_REG_0_NEXTPC
- * @brief Mask the NextPC bits in Execution Access Register 0 of all ECS
- * levels (except Debug ECS level)
- */
-#define IX_NPEDL_MASK_ECS_REG_0_NEXTPC 0x1FFF0000
-
-/**
- * @def IX_NPEDL_MASK_ECS_REG_0_LDUR
- * @brief Mask the LDUR bits in Execution Access Register 0 of all ECS levels
- */
-#define IX_NPEDL_MASK_ECS_REG_0_LDUR 0x00000700
-
-/**
- * @def IX_NPEDL_MASK_ECS_REG_1_CCTXT
- * @brief Mask the NextPC bits in Execution Access Register 1 of all ECS levels
- */
-#define IX_NPEDL_MASK_ECS_REG_1_CCTXT 0x000F0000
-
-/**
- * @def IX_NPEDL_MASK_ECS_REG_1_SELCTXT
- * @brief Mask the NextPC bits in Execution Access Register 1 of all ECS levels
- */
-#define IX_NPEDL_MASK_ECS_REG_1_SELCTXT 0x0000000F
-
-/**
- * @def IX_NPEDL_MASK_ECS_DBG_REG_2_IF
- * @brief Mask the IF bit in Execution Access Register 2 of Debug ECS level
- */
-#define IX_NPEDL_MASK_ECS_DBG_REG_2_IF 0x00100000
-
-/**
- * @def IX_NPEDL_MASK_ECS_DBG_REG_2_IE
- * @brief Mask the IE bit in Execution Access Register 2 of Debug ECS level
- */
-#define IX_NPEDL_MASK_ECS_DBG_REG_2_IE 0x00080000
-
-
-/*
- * Bit-Offsets from LSB of particular bit-fields in Execution Access registers
- */
-
-/**
- * @def IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC
- * @brief LSB-offset of NextPC field in Execution Access Register 0 of all ECS
- * levels (except Debug ECS level)
- */
-#define IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC 16
-
-/**
- * @def IX_NPEDL_OFFSET_ECS_REG_0_LDUR
- * @brief LSB-offset of LDUR field in Execution Access Register 0 of all ECS
- * levels
- */
-#define IX_NPEDL_OFFSET_ECS_REG_0_LDUR 8
-
-/**
- * @def IX_NPEDL_OFFSET_ECS_REG_1_CCTXT
- * @brief LSB-offset of CCTXT field in Execution Access Register 1 of all ECS
- * levels
- */
-#define IX_NPEDL_OFFSET_ECS_REG_1_CCTXT 16
-
-/**
- * @def IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT
- * @brief LSB-offset of SELCTXT field in Execution Access Register 1 of all ECS
- * levels
- */
-#define IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT 0
-
-
-/*
- * NPE core & co-processor instruction templates to load into NPE Instruction
- * Register, for read/write of NPE register file registers
- */
-
-/**
- * @def IX_NPEDL_INSTR_RD_REG_BYTE
- * @brief NPE Instruction, used to read an 8-bit NPE internal logical register
- * and return the value in the EXDATA register (aligned to MSB).
- * NPE Assembler instruction: "mov8 d0, d0 &&& DBG_WrExec"
- */
-#define IX_NPEDL_INSTR_RD_REG_BYTE 0x0FC00000
-
-/**
- * @def IX_NPEDL_INSTR_RD_REG_SHORT
- * @brief NPE Instruction, used to read a 16-bit NPE internal logical register
- * and return the value in the EXDATA register (aligned to MSB).
- * NPE Assembler instruction: "mov16 d0, d0 &&& DBG_WrExec"
- */
-#define IX_NPEDL_INSTR_RD_REG_SHORT 0x0FC08010
-
-/**
- * @def IX_NPEDL_INSTR_RD_REG_WORD
- * @brief NPE Instruction, used to read a 16-bit NPE internal logical register
- * and return the value in the EXDATA register.
- * NPE Assembler instruction: "mov32 d0, d0 &&& DBG_WrExec"
- */
-#define IX_NPEDL_INSTR_RD_REG_WORD 0x0FC08210
-
-/**
- * @def IX_NPEDL_INSTR_WR_REG_BYTE
- * @brief NPE Immediate-Mode Instruction, used to write an 8-bit NPE internal
- * logical register.
- * NPE Assembler instruction: "mov8 d0, #0"
- */
-#define IX_NPEDL_INSTR_WR_REG_BYTE 0x00004000
-
-/**
- * @def IX_NPEDL_INSTR_WR_REG_SHORT
- * @brief NPE Immediate-Mode Instruction, used to write a 16-bit NPE internal
- * logical register.
- * NPE Assembler instruction: "mov16 d0, #0"
- */
-#define IX_NPEDL_INSTR_WR_REG_SHORT 0x0000C000
-
-/**
- * @def IX_NPEDL_INSTR_RD_FIFO
- * @brief NPE Immediate-Mode Instruction, used to write a 16-bit NPE internal
- * logical register.
- * NPE Assembler instruction: "cprd32 d0 &&& DBG_RdInFIFO"
- */
-#define IX_NPEDL_INSTR_RD_FIFO 0x0F888220
-
-/**
- * @def IX_NPEDL_INSTR_RESET_MBOX
- * @brief NPE Instruction, used to reset Mailbox (MBST) register
- * NPE Assembler instruction: "mov32 d0, d0 &&& DBG_ClearM"
- */
-#define IX_NPEDL_INSTR_RESET_MBOX 0x0FAC8210
-
-
-/*
- * Bit-offsets from LSB, of particular bit-fields in an NPE instruction
- */
-
-/**
- * @def IX_NPEDL_OFFSET_INSTR_SRC
- * @brief LSB-offset to SRC (source operand) field of an NPE Instruction
- */
-#define IX_NPEDL_OFFSET_INSTR_SRC 4
-
-/**
- * @def IX_NPEDL_OFFSET_INSTR_DEST
- * @brief LSB-offset to DEST (destination operand) field of an NPE Instruction
- */
-#define IX_NPEDL_OFFSET_INSTR_DEST 9
-
-/**
- * @def IX_NPEDL_OFFSET_INSTR_COPROC
- * @brief LSB-offset to COPROC (coprocessor instruction) field of an NPE
- * Instruction
- */
-#define IX_NPEDL_OFFSET_INSTR_COPROC 18
-
-
-/*
- * masks used to read/write particular bits of an NPE Instruction
- */
-
-/**
- * @def IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA
- * @brief Mask the bits of 16-bit data value (least-sig 5 bits) to be used in
- * SRC field of immediate-mode NPE instruction
- */
-#define IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA 0x1F
-
-/**
- * @def IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA
- * @brief Mask the bits of 16-bit data value (most-sig 11 bits) to be used in
- * COPROC field of immediate-mode NPE instruction
- */
-#define IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA 0xFFE0
-
-/**
- * @def IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA
- * @brief LSB offset of the bit-field of 16-bit data value (most-sig 11 bits)
- * to be used in COPROC field of immediate-mode NPE instruction
- */
-#define IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA 5
-
-/**
- * @def IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA
- * @brief Number of left-shifts required to align most-sig 11 bits of 16-bit
- * data value into COPROC field of immediate-mode NPE instruction
- */
-#define IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA \
- (IX_NPEDL_OFFSET_INSTR_COPROC - IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA)
-
-/**
- * @def IX_NPEDL_WR_INSTR_LDUR
- * @brief LDUR value used with immediate-mode NPE Instructions by the NpeDl
- * for writing to NPE internal logical registers
- */
-#define IX_NPEDL_WR_INSTR_LDUR 1
-
-/**
- * @def IX_NPEDL_RD_INSTR_LDUR
- * @brief LDUR value used with NON-immediate-mode NPE Instructions by the NpeDl
- * for reading from NPE internal logical registers
- */
-#define IX_NPEDL_RD_INSTR_LDUR 0
-
-
-/**
- * @enum IxNpeDlCtxtRegNum
- * @brief Numeric values to identify the NPE internal Context Store registers
- */
-typedef enum
-{
- IX_NPEDL_CTXT_REG_STEVT = 0, /**< identifies STEVT */
- IX_NPEDL_CTXT_REG_STARTPC, /**< identifies STARTPC */
- IX_NPEDL_CTXT_REG_REGMAP, /**< identifies REGMAP */
- IX_NPEDL_CTXT_REG_CINDEX, /**< identifies CINDEX */
- IX_NPEDL_CTXT_REG_MAX /**< Total number of Context Store registers */
-} IxNpeDlCtxtRegNum;
-
-
-/*
- * NPE Context Store register logical addresses
- */
-
-/**
- * @def IX_NPEDL_CTXT_REG_ADDR_STEVT
- * @brief Logical address of STEVT NPE internal Context Store register
- */
-#define IX_NPEDL_CTXT_REG_ADDR_STEVT 0x0000001B
-
-/**
- * @def IX_NPEDL_CTXT_REG_ADDR_STARTPC
- * @brief Logical address of STARTPC NPE internal Context Store register
- */
-#define IX_NPEDL_CTXT_REG_ADDR_STARTPC 0x0000001C
-
-/**
- * @def IX_NPEDL_CTXT_REG_ADDR_REGMAP
- * @brief Logical address of REGMAP NPE internal Context Store register
- */
-#define IX_NPEDL_CTXT_REG_ADDR_REGMAP 0x0000001E
-
-/**
- * @def IX_NPEDL_CTXT_REG_ADDR_CINDEX
- * @brief Logical address of CINDEX NPE internal Context Store register
- */
-#define IX_NPEDL_CTXT_REG_ADDR_CINDEX 0x0000001F
-
-
-/*
- * NPE Context Store register reset values
- */
-
-/**
- * @def IX_NPEDL_CTXT_REG_RESET_STEVT
- * @brief Reset value of STEVT NPE internal Context Store register
- * (STEVT = off, 0x80)
- */
-#define IX_NPEDL_CTXT_REG_RESET_STEVT 0x80
-
-/**
- * @def IX_NPEDL_CTXT_REG_RESET_STARTPC
- * @brief Reset value of STARTPC NPE internal Context Store register
- * (STARTPC = 0x0000)
- */
-#define IX_NPEDL_CTXT_REG_RESET_STARTPC 0x0000
-
-/**
- * @def IX_NPEDL_CTXT_REG_RESET_REGMAP
- * @brief Reset value of REGMAP NPE internal Context Store register
- * (REGMAP = d0->p0, d8->p2, d16->p4)
- */
-#define IX_NPEDL_CTXT_REG_RESET_REGMAP 0x0820
-
-/**
- * @def IX_NPEDL_CTXT_REG_RESET_CINDEX
- * @brief Reset value of CINDEX NPE internal Context Store register
- * (CINDEX = 0)
- */
-#define IX_NPEDL_CTXT_REG_RESET_CINDEX 0x00
-
-
-/*
- * numeric range of context levels available on an NPE
- */
-
-/**
- * @def IX_NPEDL_CTXT_NUM_MIN
- * @brief Lowest NPE Context number in range
- */
-#define IX_NPEDL_CTXT_NUM_MIN 0
-
-/**
- * @def IX_NPEDL_CTXT_NUM_MAX
- * @brief Highest NPE Context number in range
- */
-#define IX_NPEDL_CTXT_NUM_MAX 15
-
-
-/*
- * Physical NPE internal registers
- */
-
-/**
- * @def IX_NPEDL_TOTAL_NUM_PHYS_REG
- * @brief Number of Physical registers currently supported
- * Initial NPE implementations will have a 32-word register file.
- * Later implementations may have a 64-word register file.
- */
-#define IX_NPEDL_TOTAL_NUM_PHYS_REG 32
-
-/**
- * @def IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP
- * @brief LSB-offset of Regmap number in Physical NPE register address, used
- * for Physical To Logical register address mapping in the NPE
- */
-#define IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP 1
-
-/**
- * @def IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR
- * @brief Mask to extract a logical NPE register address from a physical
- * register address, used for Physical To Logical address mapping
- */
-#define IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR 0x1
-
-#endif /* IXNPEDLNPEMGRECREGISTERS_P_H */
+++ /dev/null
-/**
- * @file IxNpeDlNpeMgrUtils_p.h
- *
- * @author Intel Corporation
- * @date 18 February 2002
- * @brief This file contains the private API for the NpeMgr module.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-
-/**
- * @defgroup IxNpeDlNpeMgrUtils_p IxNpeDlNpeMgrUtils_p
- *
- * @brief The private API for the IxNpeDl NpeMgr Utils module
- *
- * @{
- */
-
-#ifndef IXNPEDLNPEMGRUTILS_P_H
-#define IXNPEDLNPEMGRUTILS_P_H
-
-
-/*
- * Put the user defined include files required.
- */
-#include "IxNpeDl.h"
-#include "IxOsalTypes.h"
-#include "IxNpeDlNpeMgrEcRegisters_p.h"
-
-
-/*
- * Function Prototypes
- */
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrInsMemWrite (UINT32 npeBaseAddress,
- UINT32 insMemAddress,
- UINT32 insMemData,
- BOOL verify)
- *
- * @brief Writes a word to NPE Instruction memory
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * @param UINT32 [in] insMemAddress - NPE instruction memory address to write
- * @param UINT32 [in] insMemData - data to write to instruction memory
- * @param BOOL [in] verify - if TRUE, verify the memory location is
- * written successfully.
- *
- * This function is used to write a single word of data to a location in NPE
- * instruction memory. If the <i>verify</i> option is ON, NpeDl will read back
- * from the memory location to verify that it was written successfully
- *
- * @pre
- *
- * @post
- *
- * @return
- * - IX_FAIL if verify is TRUE and the memory location was not written
- * successfully
- * - IX_SUCCESS otherwise
- */
-IX_STATUS
-ixNpeDlNpeMgrInsMemWrite (UINT32 npeBaseAddress, UINT32 insMemAddress,
- UINT32 insMemData, BOOL verify);
-
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrDataMemWrite (UINT32 npeBaseAddress,
- UINT32 dataMemAddress,
- UINT32 dataMemData,
- BOOL verify)
- *
- * @brief Writes a word to NPE Data memory
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * @param UINT32 [in] dataMemAddress - NPE data memory address to write
- * @param UINT32 [in] dataMemData - data to write to NPE data memory
- * @param BOOL [in] verify - if TRUE, verify the memory location is
- * written successfully.
- *
- * This function is used to write a single word of data to a location in NPE
- * data memory. If the <i>verify</i> option is ON, NpeDl will read back from
- * the memory location to verify that it was written successfully
- *
- * @pre
- *
- * @post
- *
- * @return
- * - IX_FAIL if verify is TRUE and the memory location was not written
- * successfully
- * - IX_SUCCESS otherwise
- */
-IX_STATUS
-ixNpeDlNpeMgrDataMemWrite (UINT32 npeBaseAddress, UINT32 dataMemAddress,
- UINT32 dataMemData, BOOL verify);
-
-
-/**
- * @fn void ixNpeDlNpeMgrExecAccRegWrite (UINT32 npeBaseAddress,
- UINT32 regAddress,
- UINT32 regData)
- *
- * @brief Writes a word to an NPE Execution Access register
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * @param UINT32 [in] regAddress - NPE Execution Access register address
- * @param UINT32 [in] regData - data to write to register
- *
- * This function is used to write a single word of data to an NPE Execution
- * Access register.
- *
- * @pre
- *
- * @post
- *
- * @return none
- */
-void
-ixNpeDlNpeMgrExecAccRegWrite (UINT32 npeBaseAddress, UINT32 regAddress,
- UINT32 regData);
-
-
-/**
- * @fn UINT32 ixNpeDlNpeMgrExecAccRegRead (UINT32 npeBaseAddress,
- UINT32 regAddress)
- *
- * @brief Reads the contents of an NPE Execution Access register
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * @param UINT32 [in] regAddress - NPE Execution Access register address
- *
- * This function is used to read the contents of an NPE Execution
- * Access register.
- *
- * @pre
- *
- * @post
- *
- * @return The value read from the Execution Access register
- */
-UINT32
-ixNpeDlNpeMgrExecAccRegRead (UINT32 npeBaseAddress, UINT32 regAddress);
-
-
-/**
- * @fn void ixNpeDlNpeMgrCommandIssue (UINT32 npeBaseAddress,
- UINT32 command)
- *
- * @brief Issues an NPE Execution Control command
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * @param UINT32 [in] command - Command to issue
- *
- * This function is used to issue a stand-alone NPE Execution Control command
- * (e.g. command to Stop NPE execution)
- *
- * @pre
- *
- * @post
- *
- * @return none
- */
-void
-ixNpeDlNpeMgrCommandIssue (UINT32 npeBaseAddress, UINT32 command);
-
-
-/**
- * @fn void ixNpeDlNpeMgrDebugInstructionPreExec (UINT32 npeBaseAddress)
- *
- * @brief Prepare to executes one or more NPE instructions in the Debug
- * Execution Stack level.
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- *
- * This function should be called once before a sequence of calls to
- * ixNpeDlNpeMgrDebugInstructionExec().
- *
- * @pre
- *
- * @post
- * - ixNpeDlNpeMgrDebugInstructionPostExec() should be called to restore
- * registers values altered by this function
- *
- * @return none
- */
-void
-ixNpeDlNpeMgrDebugInstructionPreExec (UINT32 npeBaseAddress);
-
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrDebugInstructionExec (UINT32 npeBaseAddress,
- UINT32 npeInstruction,
- UINT32 ctxtNum,
- UINT32 ldur)
- *
- * @brief Executes a single instruction on the NPE at the Debug Execution Stack
- * level
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * @param UINT32 [in] npeInstruction - Value to write to INSTR (Instruction)
- * register
- * @param UINT32 [in] ctxtNum - context the instruction will be executed
- * in and which context store it may access
- * @param UINT32 [in] ldur - Long Immediate Duration, set to non-zero
- * to use long-immediate mode instruction
- *
- * This function is used to execute a single instruction in the NPE pipeline at
- * the debug Execution Context Stack level. It won't disturb the state of other
- * executing contexts. Its useful for performing NPE operations, such as
- * writing to NPE Context Store registers and physical registers, that cannot
- * be carried out directly using the Configuration Bus registers. This function
- * will return TIMEOUT status if NPE not responding due to NPS is hang / halt.
- *
- * @pre
- * - The NPE should be stopped and in a clean state
- * - ixNpeDlNpeMgrDebugInstructionPreExec() should be called once before
- * a sequential of 1 or more calls to this function
- *
- * @post
- * - ixNpeDlNpeMgrDebugInstructionPostExec() should be called after
- * a sequence of calls to this function
- *
- * @return
- * - IX_NPEDL_CRITICAL_NPE_ERR if execution of instruction failed / timeout
- * - IX_SUCCESS otherwise
- */
-IX_STATUS
-ixNpeDlNpeMgrDebugInstructionExec (UINT32 npeBaseAddress,
- UINT32 npeInstruction,
- UINT32 ctxtNum, UINT32 ldur);
-
-
-/**
- * @fn void ixNpeDlNpeMgrDebugInstructionPostExec (UINT32 npeBaseAddress)
- *
- * @brief Clean up after executing one or more NPE instructions in the
- * Debug Stack Level
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- *
- * This function should be called once following a sequence of calls to
- * ixNpeDlNpeMgrDebugInstructionExec().
- *
- * @pre
- * - ixNpeDlNpeMgrDebugInstructionPreExec() was called earlier
- *
- * @post
- * - The Instruction Pipeline will cleared
- *
- * @return none
- */
-void
-ixNpeDlNpeMgrDebugInstructionPostExec (UINT32 npeBaseAddress);
-
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrPhysicalRegWrite (UINT32 npeBaseAddress,
- UINT32 regAddr,
- UINT32 regValue,
- BOOL verify)
- *
- * @brief Write one of the 32* 32-bit physical registers in the NPE data
- * register file
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * @param UINT32 [in] regAddr - number of the physical register (0-31)*
- * @param UINT32 [in] regValue - value to write to the physical register
- * @param BOOL [in] verify - if TRUE, verify the register is written
- * successfully.
- *
- * This function writes a physical register in the NPE data register file.
- * If the <i>verify</i> option is ON, NpeDl will read back the register to
- * verify that it was written successfully
- * *Note that release 1.0 of this software supports 32 physical
- * registers, but 64 may be supported in future versions.
- *
- * @pre
- * - The NPE should be stopped and in a clean state
- * - ixNpeDlNpeMgrDebugInstructionPreExec() should be called once before
- * a sequential of 1 or more calls to this function
- *
- * @post
- * - Contents of REGMAP Context Store register for Context 0 will be altered
- * - ixNpeDlNpeMgrDebugInstructionPostExec() should be called after
- * a sequence of calls to this function
- *
- * @return
- * - IX_FAIL if verify is TRUE and the Context Register was not written
- * successfully
- * - IX_SUCCESS if Context Register was written successfully
- * - IX_NPEDL_CRITICAL_NPE_ERR if Context Register was not written
- * successfully due to timeout error where NPE is not responding
- */
-IX_STATUS
-ixNpeDlNpeMgrPhysicalRegWrite (UINT32 npeBaseAddress, UINT32 regAddr,
- UINT32 regValue, BOOL verify);
-
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrCtxtRegWrite (UINT32 npeBaseAddress,
- UINT32 ctxtNum,
- IxNpeDlCtxtRegNum ctxtReg,
- UINT32 ctxtRegVal,
- BOOL verify)
- *
- * @brief Writes a value to a Context Store register on an NPE
- *
- * @param UINT32 [in] npeBaseAddress - Base Address of NPE
- * @param UINT32 [in] ctxtNum - context store to access
- * @param IxNpeDlCtxtRegNum [in] ctxtReg - which Context Store reg to write
- * @param UINT32 [in] ctxtRegVal - value to write to the Context Store
- * register
- * @param BOOL [in] verify - if TRUE, verify the register is
- * written successfully.
- *
- * This function writes the contents of a Context Store register in the NPE
- * register file. If the <i>verify</i> option is ON, NpeDl will read back the
- * register to verify that it was written successfully
- *
- * @pre
- * - The NPE should be stopped and in a clean state
- * - ixNpeDlNpeMgrDebugInstructionPreExec() should be called once before
- * a sequential of 1 or more calls to this function
- *
- * @post
- * - ixNpeDlNpeMgrDebugInstructionPostExec() should be called after
- * a sequence of calls to this function
- *
- * @return
- * - IX_FAIL if verify is TRUE and the Context Register was not written
- * successfully
- * - IX_SUCCESS if Context Register was written successfully
- * - IX_NPEDL_CRITICAL_NPE_ERR if Context Register was not written
- * successfully due to timeout error where NPE is not responding
- */
-IX_STATUS
-ixNpeDlNpeMgrCtxtRegWrite (UINT32 npeBaseAddress, UINT32 ctxtNum,
- IxNpeDlCtxtRegNum ctxtReg, UINT32 ctxtRegVal,
- BOOL verify);
-
-
-/**
- * @fn void ixNpeDlNpeMgrUtilsStatsShow (void)
- *
- * @brief This function will display the statistics of the IxNpeDl NpeMgrUtils
- * module
- *
- * @return none
- */
-void
-ixNpeDlNpeMgrUtilsStatsShow (void);
-
-
-/**
- * @fn void ixNpeDlNpeMgrUtilsStatsReset (void)
- *
- * @brief This function will reset the statistics of the IxNpeDl NpeMgrUtils
- * module
- *
- * @return none
- */
-void
-ixNpeDlNpeMgrUtilsStatsReset (void);
-
-
-#endif /* IXNPEDLNPEMGRUTILS_P_H */
+++ /dev/null
-/**
- * @file IxNpeDlNpeMgr_p.h
- *
- * @author Intel Corporation
- * @date 14 December 2001
- * @brief This file contains the private API for the NpeMgr module.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-
-/**
- * @defgroup IxNpeDlNpeMgr_p IxNpeDlNpeMgr_p
- *
- * @brief The private API for the IxNpeDl NpeMgr module
- *
- * @{
- */
-
-#ifndef IXNPEDLNPEMGR_P_H
-#define IXNPEDLNPEMGR_P_H
-
-
-/*
- * Put the user defined include files required.
- */
-#include "IxNpeDl.h"
-#include "IxOsalTypes.h"
-
-
-/*
- * Function Prototypes
- */
-
-
-/**
- * @fn void ixNpeDlNpeMgrInit (void)
- *
- * @brief Initialises the NpeMgr module
- *
- * @param none
- *
- * This function initialises the NpeMgr module.
- * It should be called before any other function in this module is called.
- * It only needs to be called once, but can be called multiple times safely.
- * The code will ASSERT on failure.
- *
- * @pre
- * - It must be called before any other function in this module
- *
- * @post
- * - NPE Configuration Register memory space will be mapped using
- * IxOsal. This memory will not be unmapped by this module.
- *
- * @return none
- */
-void
-ixNpeDlNpeMgrInit (void);
-
-
-/**
- * @fn IX_STATUS ixNpeMhNpeMgrUninit (void)
- *
- * @brief This function will uninitialise the IxNpeDlNpeMgr sub-component.
- *
- * This function will uninitialise the IxNpeDlNpeMgr sub-component.
- * It should only be called once, and only if the IxNpeDlNpeMgr sub-component
- * has already been initialised by calling @ref ixNpeDlNpeMgrInit().
- * No other IxNpeDlNpeMgr sub-component API functions should be called
- * until @ref ixNpeDlNpeMgrInit() is called again.
- * If possible, this function should be called before a soft reboot or unloading
- * a kernel module to perform any clean up operations required for IxNpeMh.
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_FAIL otherwise
- */
-
-IX_STATUS ixNpeDlNpeMgrUninit (void);
-
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrImageLoad (IxNpeDlNpeId npeId,
- UINT32 *imageCodePtr,
- BOOL verify)
- *
- * @brief Loads a image of microcode onto an NPE
- *
- * @param IxNpeDlNpeId [in] npeId - Id of target NPE
- * @param UINT32* [in] imageCodePtr - pointer to image code in image to be
- * downloaded
- * @param BOOL [in] verify - if TRUE, verify each word written to
- * NPE memory.
- *
- * This function loads a image containing blocks of microcode onto a
- * particular NPE. If the <i>verify</i> option is ON, NpeDl will read back each
- * word written and verify that it was written successfully
- *
- * @pre
- * - The NPE should be stopped beforehand
- *
- * @post
- * - The NPE Instruction Pipeline may be flushed clean
- *
- * @return
- * - IX_SUCCESS if the download was successful
- * - IX_FAIL if the download failed
- * - IX_NPEDL_CRITICAL_NPE_ERR if the download failed due to timeout error
- * where NPE is not responding
- */
-IX_STATUS
-ixNpeDlNpeMgrImageLoad (IxNpeDlNpeId npeId, UINT32 *imageCodePtr,
- BOOL verify);
-
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrNpeReset (IxNpeDlNpeId npeId)
- *
- * @brief sets a NPE to RESET state
- *
- * @param IxNpeDlNpeId [in] npeId - id of target NPE
- *
- * This function performs a soft NPE reset by writing reset values to the
- * Configuration Bus Execution Control registers, the Execution Context Stack
- * registers, the Physical Register file, and the Context Store registers for
- * each context number. It also clears inFIFO, outFIFO and Watchpoint FIFO.
- * It does not reset NPE Co-processors.
- *
- * @pre
- * - The NPE should be stopped beforehand
- *
- * @post
- * - NPE NextProgram Counter (NextPC) will be set to a fixed initial value,
- * such as 0. This should be explicitly set by downloading State
- * Information before starting NPE Execution.
- * - The NPE Instruction Pipeline will be in a clean state.
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_FAIL if the operation failed
- * - IX_NPEDL_CRITICAL_NPE_ERR if the operation failed due to NPE hang
- */
-IX_STATUS
-ixNpeDlNpeMgrNpeReset (IxNpeDlNpeId npeId);
-
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrNpeStart (IxNpeDlNpeId npeId)
- *
- * @brief Starts NPE Execution
- *
- * @param IxNpeDlNpeId [in] npeId - Id of target NPE
- *
- * Ensures only background Execution Stack Level is Active, clears instruction
- * pipeline, and starts Execution on a NPE by sending a Start NPE command to
- * the NPE. Checks the execution status of the NPE to verify that it is
- * running.
- *
- * @pre
- * - The NPE should be stopped beforehand.
- * - Note that this function does not set the NPE Next Program Counter
- * (NextPC), so it should be set beforehand if required by downloading
- * appropriate State Information.
- *
- * @post
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_FAIL otherwise
- */
-IX_STATUS
-ixNpeDlNpeMgrNpeStart (IxNpeDlNpeId npeId);
-
-
-/**
- * @fn IX_STATUS ixNpeDlNpeMgrNpeStop (IxNpeDlNpeId npeId)
- *
- * @brief Halts NPE Execution
- *
- * @param IxNpeDlNpeId [in] npeId - id of target NPE
- *
- * Stops execution on an NPE by sending a Stop NPE command to the NPE.
- * Checks the execution status of the NPE to verify that it has stopped.
- *
- * @pre
- *
- * @post
- *
- * @return
- * - IX_SUCCESS if the operation was successful
- * - IX_FAIL otherwise
- */
-IX_STATUS
-ixNpeDlNpeMgrNpeStop (IxNpeDlNpeId npeId);
-
-
-/**
- * @fn void ixNpeDlNpeMgrStatsShow (void)
- *
- * @brief This function will display statistics of the IxNpeDl NpeMgr module
- *
- * @return none
- */
-void
-ixNpeDlNpeMgrStatsShow (void);
-
-
-/**
- * @fn void ixNpeDlNpeMgrStatsReset (void)
- *
- * @brief This function will reset the statistics of the IxNpeDl NpeMgr module
- *
- * @return none
- */
-void
-ixNpeDlNpeMgrStatsReset (void);
-
-
-#endif /* IXNPEDLIMAGEMGR_P_H */
-
-/**
- * @} defgroup IxNpeDlNpeMgr_p
- */
+++ /dev/null
-/**
- * @file IxNpeMh.h
- *
- * @date 14 Dec 2001
- *
- * @brief This file contains the public API for the IXP400 NPE Message
- * Handler component.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeMh IXP400 NPE Message Handler (IxNpeMh) API
- *
- * @brief The public API for the IXP400 NPE Message Handler component.
- *
- * @{
- */
-
-#ifndef IXNPEMH_H
-#define IXNPEMH_H
-
-#include "IxOsalTypes.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-#define IX_NPEMH_MIN_MESSAGE_ID (0x00) /**< minimum valid message ID */
-#define IX_NPEMH_MAX_MESSAGE_ID (0xFF) /**< maximum valid message ID */
-
-#define IX_NPEMH_SEND_RETRIES_DEFAULT (3) /**< default msg send retries */
-
-
-/**
- * @def IX_NPEMH_CRITICAL_NPE_ERR
- *
- * @brief NpeMH function return value for a Critical NPE error occuring during
- sending/receiving message. Assume NPE hang / halt if this value is
- returned.
- */
-#define IX_NPEMH_CRITICAL_NPE_ERR 2
-
-/**
- * @enum IxNpeMhNpeId
- *
- * @brief The ID of a particular NPE.
- * @note In this context, for IXP425 Silicon (B0):<br>
- * - NPE-A has HDLC, HSS, AAL and UTOPIA Coprocessors.<br>
- * - NPE-B has Ethernet Coprocessor.<br>
- * - NPE-C has Ethernet, AES, DES and HASH Coprocessors.<br>
- * - IXP400 Product Line have different combinations of coprocessors.
- */
-
-typedef enum
-{
- IX_NPEMH_NPEID_NPEA = 0, /**< ID for NPE-A */
- IX_NPEMH_NPEID_NPEB, /**< ID for NPE-B */
- IX_NPEMH_NPEID_NPEC, /**< ID for NPE-C */
- IX_NPEMH_NUM_NPES /**< Number of NPEs */
-} IxNpeMhNpeId;
-
-/**
- * @enum IxNpeMhNpeInterrupts
- *
- * @brief Indicator specifying whether or not NPE interrupts should drive
- * receiving of messages from the NPEs.
- */
-
-typedef enum
-{
- IX_NPEMH_NPEINTERRUPTS_NO = 0, /**< Don't use NPE interrupts */
- IX_NPEMH_NPEINTERRUPTS_YES /**< Do use NPE interrupts */
-} IxNpeMhNpeInterrupts;
-
-/**
- * @brief The 2-word message structure to send to and receive from the
- * NPEs.
- */
-
-typedef struct
-{
- UINT32 data[2]; /**< the actual data of the message */
-} IxNpeMhMessage;
-
-/** message ID */
-typedef UINT32 IxNpeMhMessageId;
-
-/**
- * @typedef IxNpeMhCallback
- *
- * @brief This prototype shows the format of a message callback function.
- *
- * This prototype shows the format of a message callback function. The
- * message callback will be passed the message to be handled and will also
- * be told from which NPE the message was received. The message callback
- * will either be registered by ixNpeMhUnsolicitedCallbackRegister() or
- * passed as a parameter to ixNpeMhMessageWithResponseSend(). It will be
- * called from within an ISR triggered by the NPE's "outFIFO not empty"
- * interrupt (see ixNpeMhInitialize()). The parameters passed are the ID
- * of the NPE that the message was received from, and the message to be
- * handled.<P><B>Re-entrancy:</B> This function is only a prototype, and
- * will be implemented by the client. It does not need to be re-entrant.
- */
-
-typedef void (*IxNpeMhCallback) (IxNpeMhNpeId, IxNpeMhMessage);
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhInitialize (
- IxNpeMhNpeInterrupts npeInterrupts)
- *
- * @brief This function will initialise the IxNpeMh component.
- *
- * @param npeInterrupts @ref IxNpeMhNpeInterrupts [in] - This parameter
- * dictates whether or not the IxNpeMh component will service NPE "outFIFO
- * not empty" interrupts to trigger receiving and processing of messages
- * from the NPEs. If not then the client must use ixNpeMhMessagesReceive()
- * to control message receiving and processing.
- *
- * This function will initialise the IxNpeMh component. It should only be
- * called once, prior to using the IxNpeMh component. The following
- * actions will be performed by this function:<OL><LI>Initialization of
- * internal data structures (e.g. solicited and unsolicited callback
- * tables).</LI><LI>Configuration of the interface with the NPEs (e.g.
- * enabling of NPE "outFIFO not empty" interrupts).</LI><LI>Registration of
- * ISRs that will receive and handle messages when the NPEs' "outFIFO not
- * empty" interrupts fire (if npeInterrupts equals
- * IX_NPEMH_NPEINTERRUPTS_YES).</LI></OL>
- *
- * @return The function returns a status indicating success or failure.
- */
-
-PUBLIC IX_STATUS ixNpeMhInitialize (
- IxNpeMhNpeInterrupts npeInterrupts);
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhUnload (void)
- *
- * @brief This function will uninitialise the IxNpeMh component.
- *
- * This function will uninitialise the IxNpeMh component. It should only be
- * called once, and only if the IxNpeMh component has already been initialised.
- * No other IxNpeMh API functions should be called until @ref ixNpeMhInitialize
- * is called again.
- * If possible, this function should be called before a soft reboot or unloading
- * a kernel module to perform any clean up operations required for IxNpeMh.
- *
- * The following actions will be performed by this function:
- * <OL><LI>Unmapping of kernel memory mapped by the function
- * @ref ixNpeMhInitialize.</LI></OL>
- *
- * @return The function returns a status indicating success or failure.
- */
-
-PUBLIC IX_STATUS ixNpeMhUnload (void);
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhUnsolicitedCallbackRegister (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId messageId,
- IxNpeMhCallback unsolicitedCallback)
- *
- * @brief This function will register an unsolicited callback for a
- * particular NPE and message ID.
- *
- * @param npeId @ref IxNpeMhNpeId [in] - The ID of the NPE whose messages
- * the unsolicited callback will handle.
- * @param messageId @ref IxNpeMhMessageId [in] - The ID of the messages the
- * unsolicited callback will handle.
- * @param unsolicitedCallback @ref IxNpeMhCallback [in] - The unsolicited
- * callback function. A value of NULL will deregister any previously
- * registered callback for this NPE and message ID.
- *
- * This function will register an unsolicited message callback for a
- * particular NPE and message ID.<P>If an unsolicited callback is already
- * registered for the specified NPE and message ID then the callback will
- * be overwritten. Only one client will be responsible for handling a
- * particular message ID associated with a NPE. Registering a NULL
- * unsolicited callback will deregister any previously registered
- * callback.<P>The callback function will be called from an ISR that will
- * be triggered by the NPE's "outFIFO not empty" interrupt (see
- * ixNpeMhInitialize()) to handle any unsolicited messages of the specific
- * message ID received from the NPE. Unsolicited messages will be handled
- * in the order they are received.<P>If no unsolicited callback can be
- * found for a received message then it is assumed that the message is
- * solicited.<P>If more than one client may be interested in a particular
- * unsolicited message then the suggested strategy is to register a
- * callback for the message that can itself distribute the message to
- * multiple clients as necessary.<P>See also
- * ixNpeMhUnsolicitedCallbackForRangeRegister().<P><B>Re-entrancy:</B> This
- * function will be callable from any thread at any time. IxOsal
- * will be used for any necessary resource protection.
- *
- * @return The function returns a status indicating success or failure.
- */
-
-PUBLIC IX_STATUS ixNpeMhUnsolicitedCallbackRegister (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId messageId,
- IxNpeMhCallback unsolicitedCallback);
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhUnsolicitedCallbackForRangeRegister (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId minMessageId,
- IxNpeMhMessageId maxMessageId,
- IxNpeMhCallback unsolicitedCallback)
- *
- * @brief This function will register an unsolicited callback for a
- * particular NPE and range of message IDs.
- *
- * @param npeId @ref IxNpeMhNpeId [in] - The ID of the NPE whose messages the
- * unsolicited callback will handle.
- * @param minMessageId @ref IxNpeMhMessageId [in] - The minimum message ID in
- * the range of message IDs the unsolicited callback will handle.
- * @param maxMessageId @ref IxNpeMhMessageId [in] - The maximum message ID in
- * the range of message IDs the unsolicited callback will handle.
- * @param unsolicitedCallback @ref IxNpeMhCallback [in] - The unsolicited
- * callback function. A value of NULL will deregister any previously
- * registered callback(s) for this NPE and range of message IDs.
- *
- * This function will register an unsolicited callback for a particular NPE
- * and range of message IDs. It is a convenience function that is
- * effectively the same as calling ixNpeMhUnsolicitedCallbackRegister() for
- * each ID in the specified range. See
- * ixNpeMhUnsolicitedCallbackRegister() for more
- * information.<P><B>Re-entrancy:</B> This function will be callable from
- * any thread at any time. IxOsal will be used for any necessary
- * resource protection.
- *
- * @return The function returns a status indicating success or failure.
- */
-
-PUBLIC IX_STATUS ixNpeMhUnsolicitedCallbackForRangeRegister (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId minMessageId,
- IxNpeMhMessageId maxMessageId,
- IxNpeMhCallback unsolicitedCallback);
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhMessageSend (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage message,
- UINT32 maxSendRetries)
- *
- * @brief This function will send a message to a particular NPE.
- *
- * @param npeId @ref IxNpeMhNpeId [in] - The ID of the NPE to send the message
- * to.
- * @param message @ref IxNpeMhMessage [in] - The message to send.
- * @param maxSendRetries UINT32 [in] - Max num. of retries to perform
- * if the NPE's inFIFO is full.
- *
- * This function will send a message to a particular NPE. It will be the
- * client's responsibility to ensure that the message is properly formed.
- * The return status will signify to the client if the message was
- * successfully sent or not.<P>If the message is sent to the NPE then this
- * function will return a status of success. Note that this will only mean
- * the message has been placed in the NPE's inFIFO. There will be no way
- * of knowing that the NPE has actually read the message, but once in the
- * incoming message queue it will be safe to assume that the NPE will
- * process it.
- * <P>The inFIFO may fill up sometimes if the Xscale is sending messages
- * faster than the NPE can handle them. This forces us to retry attempts
- * to send the message until the NPE services the inFIFO. The client should
- * specify a ceiling value for the number of retries suitable to their
- * needs. IX_NPEMH_SEND_RETRIES_DEFAULT can be used as a default value for
- * the <i>maxSendRetries</i> parameter for this function. Each retry
- * exceeding this default number will incur a blocking delay of 1 microsecond,
- * to avoid consuming too much AHB bus bandwidth while performing retries.
- * <P>Note this function <B>must</B> only be used for messages.
- * that do not solicit responses. If the message being sent will solicit a
- * response then the ixNpeMhMessageWithResponseSend() function <B>must</B>
- * be used to ensure that the response is correctly
- * handled. <P> This function will return timeout status if NPE hang / halt
- * while sending message. The timeout error is not related to the
- * <i>maxSendRetries</i> as mentioned above. The timeout error will only occur
- * if the first word of the message has been sent to NPE (not exceeding
- * <i>maxSendRetries</i> when sending 1st message word), but the second word of
- * the message can't be written to NPE's inFIFO due to NPE hang / halt after
- * maximum waiting time (IX_NPE_MH_MAX_NUM_OF_RETRIES).
- * <P><B>Re-entrancy:</B> This function will be callable from any
- * thread at any time. IxOsal will be used for any necessary
- * resource protection.
- *
- * @return The function returns a status indicating success, failure or timeout.
- */
-
-PUBLIC IX_STATUS ixNpeMhMessageSend (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage message,
- UINT32 maxSendRetries);
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhMessageWithResponseSend (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage message,
- IxNpeMhMessageId solicitedMessageId,
- IxNpeMhCallback solicitedCallback,
- UINT32 maxSendRetries)
- *
- * @brief This function is equivalent to the ixNpeMhMessageSend() function,
- * but must be used when the message being sent will solicited a response.
- *
- * @param npeId @ref IxNpeMhNpeId [in] - The ID of the NPE to send the message
- * to.
- * @param message @ref IxNpeMhMessage [in] - The message to send.
- * @param solicitedMessageId @ref IxNpeMhMessageId [in] - The ID of the
- * solicited response message.
- * @param solicitedCallback @ref IxNpeMhCallback [in] - The function to use to
- * pass the response message back to the client. A value of NULL will
- * cause the response message to be discarded.
- * @param maxSendRetries UINT32 [in] - Max num. of retries to perform
- * if the NPE's inFIFO is full.
- *
- * This function is equivalent to the ixNpeMhMessageSend() function, but
- * must be used when the message being sent will solicited a
- * response.<P>The client must specify the ID of the solicited response
- * message to allow the response to be recognised when it is received. The
- * client must also specify a callback function to handle the received
- * response. The IxNpeMh component will not offer the facility to send a
- * message to a NPE and receive a response within the same context.<P>Note
- * if the client is not interested in the response, specifying a NULL
- * callback will cause the response message to be discarded.<P>The
- * solicited callback will be stored and called some time later from an ISR
- * that will be triggered by the NPE's "outFIFO not empty" interrupt (see
- * ixNpeMhInitialize()) to handle the response message corresponding to the
- * message sent. Response messages will be handled in the order they are
- * received.<P>
- * <P>The inFIFO may fill up sometimes if the Xscale is sending messages
- * faster than the NPE can handle them. This forces us to retry attempts
- * to send the message until the NPE services the inFIFO. The client should
- * specify a ceiling value for the number of retries suitable to their
- * needs. IX_NPEMH_SEND_RETRIES_DEFAULT can be used as a default value for
- * the <i>maxSendRetries</i> parameter for this function. Each retry
- * exceeding this default number will incur a blocking delay of 1 microsecond,
- * to avoid consuming too much AHB bus bandwidth while performing retries.
- * <P> This function will return timeout status if NPE hang / halt
- * while sending message. The timeout error is not related to the
- * <i>maxSendRetries</i> as mentioned above. The timeout error will only occur
- * if the first word of the message has been sent to NPE (not exceeding
- * <i>maxSendRetries</i> when sending 1st message word), but the second word of
- * the message can't be written to NPE's inFIFO due to NPE hang / halt after
- * maximum waiting time (IX_NPE_MH_MAX_NUM_OF_RETRIES).
- * <P><B>Re-entrancy:</B> This function will be callable from any
- * thread at any time. IxOsal will be used for any necessary
- * resource protection.
- *
- * @return The function returns a status indicating success or failure.
- */
-
-PUBLIC IX_STATUS ixNpeMhMessageWithResponseSend (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage message,
- IxNpeMhMessageId solicitedMessageId,
- IxNpeMhCallback solicitedCallback,
- UINT32 maxSendRetries);
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhMessagesReceive (
- IxNpeMhNpeId npeId)
- *
- * @brief This function will receive messages from a particular NPE and
- * pass each message to the client via a solicited callback (for solicited
- * messages) or an unsolicited callback (for unsolicited messages).
- *
- * @param npeId @ref IxNpeMhNpeId [in] - The ID of the NPE to receive and
- * process messages from.
- *
- * This function will receive messages from a particular NPE and pass each
- * message to the client via a solicited callback (for solicited messages)
- * or an unsolicited callback (for unsolicited messages).<P>If the IxNpeMh
- * component is initialised to service NPE "outFIFO not empty" interrupts
- * (see ixNpeMhInitialize()) then there is no need to call this function.
- * This function is only provided as an alternative mechanism to control
- * the receiving and processing of messages from the NPEs.<P> This function
- * will return timeout status if NPE hang / halt while receiving message. The
- * timeout error will only occur if this function has read the first word of
- * the message and can't read second word of the message from NPE's outFIFO
- * after maximum retries (IX_NPE_MH_MAX_NUM_OF_RETRIES).
- * <P>Note this function cannot be called from within
- * an ISR as it will use resource protection mechanisms.<P><B>Re-entrancy:</B>
- * This function will be callable from any thread at any time. IxOsal will be
- * used for any necessary resource protection.
- *
- * @return The function returns a status indicating success, failure or timeout.
- */
-
-PUBLIC IX_STATUS ixNpeMhMessagesReceive (
- IxNpeMhNpeId npeId);
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhShow (
- IxNpeMhNpeId npeId)
- *
- * @brief This function will display the current state of the IxNpeMh
- * component.
- *
- * <B>Re-entrancy:</B> This function will be callable from
- * any thread at any time. However, no resource protection will be used
- * so as not to impact system performance. As this function is only
- * reading statistical information then this is acceptable.
- *
- * @param npeId @ref IxNpeMhNpeId [in] - The ID of the NPE to display state
- * information for.
- *
- * @return The function returns a status indicating success or failure.
- */
-
-PUBLIC IX_STATUS ixNpeMhShow (
- IxNpeMhNpeId npeId);
-
-/**
- * @ingroup IxNpeMh
- *
- * @fn IX_STATUS ixNpeMhShowReset (
- IxNpeMhNpeId npeId)
- *
- * @brief This function will reset the current state of the IxNpeMh
- * component.
- *
- * <B>Re-entrancy:</B> This function will be callable from
- * any thread at any time. However, no resource protection will be used
- * so as not to impact system performance. As this function is only
- * writing statistical information then this is acceptable.
- *
- * @param npeId @ref IxNpeMhNpeId [in] - The ID of the NPE to reset state
- * information for.
- *
- * @return The function returns a status indicating success or failure.
- */
-
-PUBLIC IX_STATUS ixNpeMhShowReset (
- IxNpeMhNpeId npeId);
-
-#endif /* IXNPEMH_H */
-
-/**
- * @} defgroup IxNpeMh
- */
+++ /dev/null
-/**
- * @file IxNpeMhConfig_p.h
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the private API for the Configuration module.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeMhConfig_p IxNpeMhConfig_p
- *
- * @brief The private API for the Configuration module.
- *
- * @{
- */
-
-#ifndef IXNPEMHCONFIG_P_H
-#define IXNPEMHCONFIG_P_H
-
-#include "IxOsal.h"
-
-#include "IxNpeMh.h"
-#include "IxNpeMhMacros_p.h"
-
-/*
- * inline definition
- */
-/* enable function inlining for performances */
-#ifdef IXNPEMHSOLICITEDCBMGR_C
-/* Non-inline functions will be defined in this translation unit.
- Reason is that in GNU Compiler, if the Optimization is turn off, all extern inline
- functions will not be compiled.
-*/
-# ifndef __wince
-# ifndef IXNPEMHCONFIG_INLINE
-# define IXNPEMHCONFIG_INLINE
-# endif
-# else
-# ifndef IXNPEMHCONFIG_INLINE
-# define IXNPEMHCONFIG_INLINE IX_OSAL_INLINE_EXTERN
-# endif
-# endif /* __wince*/
-
-#else
-
-# ifndef IXNPEMHCONFIG_INLINE
-# define IXNPEMHCONFIG_INLINE IX_OSAL_INLINE_EXTERN
-# endif /* IXNPEMHCONFIG_INLINE */
-#endif /* IXNPEMHSOLICITEDCBMGR_C */
-/*
- * Typedefs and #defines, etc.
- */
-
-typedef void (*IxNpeMhConfigIsr) (int); /**< ISR function pointer */
-
-/**
- * @struct IxNpeMhConfigNpeInfo
- *
- * @brief This structure is used to maintain the configuration information
- * associated with an NPE.
- */
-
-typedef struct
-{
- IxOsalMutex mutex; /**< mutex */
- UINT32 interruptId; /**< interrupt ID */
- UINT32 virtualRegisterBase; /**< register virtual base address */
- UINT32 statusRegister; /**< status register virtual address */
- UINT32 controlRegister; /**< control register virtual address */
- UINT32 inFifoRegister; /**< inFIFO register virutal address */
- UINT32 outFifoRegister; /**< outFIFO register virtual address */
- IxNpeMhConfigIsr isr; /**< isr routine for handling interrupt */
- BOOL oldInterruptState; /**< old interrupt state (TRUE => enabled) */
-} IxNpeMhConfigNpeInfo;
-
-
-/*
- * #defines for function return types, etc.
- */
-
-/**< NPE register base address */
-#define IX_NPEMH_NPE_BASE (IX_OSAL_IXP400_PERIPHERAL_PHYS_BASE)
-
-#define IX_NPEMH_NPEA_OFFSET (0x6000) /**< NPE-A register base offset */
-#define IX_NPEMH_NPEB_OFFSET (0x7000) /**< NPE-B register base offset */
-#define IX_NPEMH_NPEC_OFFSET (0x8000) /**< NPE-C register base offset */
-
-#define IX_NPEMH_NPESTAT_OFFSET (0x002C) /**< NPE status register offset */
-#define IX_NPEMH_NPECTL_OFFSET (0x0030) /**< NPE control register offset */
-#define IX_NPEMH_NPEFIFO_OFFSET (0x0038) /**< NPE FIFO register offset */
-
-/** NPE-A register base address */
-#define IX_NPEMH_NPEA_BASE (IX_NPEMH_NPE_BASE + IX_NPEMH_NPEA_OFFSET)
-/** NPE-B register base address */
-#define IX_NPEMH_NPEB_BASE (IX_NPEMH_NPE_BASE + IX_NPEMH_NPEB_OFFSET)
-/** NPE-C register base address */
-#define IX_NPEMH_NPEC_BASE (IX_NPEMH_NPE_BASE + IX_NPEMH_NPEC_OFFSET)
-
-/* NPE-A configuration */
-
-/** NPE-A interrupt */
-#define IX_NPEMH_NPEA_INT (IX_OSAL_IXP400_NPEA_IRQ_LVL)
-/** NPE-A FIFO register */
-#define IX_NPEMH_NPEA_FIFO (IX_NPEMH_NPEA_BASE + IX_NPEMH_NPEFIFO_OFFSET)
-/** NPE-A control register */
-#define IX_NPEMH_NPEA_CTL (IX_NPEMH_NPEA_BASE + IX_NPEMH_NPECTL_OFFSET)
-/** NPE-A status register */
-#define IX_NPEMH_NPEA_STAT (IX_NPEMH_NPEA_BASE + IX_NPEMH_NPESTAT_OFFSET)
-
-/* NPE-B configuration */
-
-/** NPE-B interrupt */
-#define IX_NPEMH_NPEB_INT (IX_OSAL_IXP400_NPEB_IRQ_LVL)
-/** NPE-B FIFO register */
-#define IX_NPEMH_NPEB_FIFO (IX_NPEMH_NPEB_BASE + IX_NPEMH_NPEFIFO_OFFSET)
-/** NPE-B control register */
-#define IX_NPEMH_NPEB_CTL (IX_NPEMH_NPEB_BASE + IX_NPEMH_NPECTL_OFFSET)
-/** NPE-B status register */
-#define IX_NPEMH_NPEB_STAT (IX_NPEMH_NPEB_BASE + IX_NPEMH_NPESTAT_OFFSET)
-
-/* NPE-C configuration */
-
-/** NPE-C interrupt */
-#define IX_NPEMH_NPEC_INT (IX_OSAL_IXP400_NPEC_IRQ_LVL)
-/** NPE-C FIFO register */
-#define IX_NPEMH_NPEC_FIFO (IX_NPEMH_NPEC_BASE + IX_NPEMH_NPEFIFO_OFFSET)
-/** NPE-C control register */
-#define IX_NPEMH_NPEC_CTL (IX_NPEMH_NPEC_BASE + IX_NPEMH_NPECTL_OFFSET)
-/** NPE-C status register */
-#define IX_NPEMH_NPEC_STAT (IX_NPEMH_NPEC_BASE + IX_NPEMH_NPESTAT_OFFSET)
-
-/* NPE control register bit definitions */
-#define IX_NPEMH_NPE_CTL_OFE (1 << 16) /**< OutFifoEnable */
-#define IX_NPEMH_NPE_CTL_IFE (1 << 17) /**< InFifoEnable */
-#define IX_NPEMH_NPE_CTL_OFEWE (1 << 24) /**< OutFifoEnableWriteEnable */
-#define IX_NPEMH_NPE_CTL_IFEWE (1 << 25) /**< InFifoEnableWriteEnable */
-
-/* NPE status register bit definitions */
-#define IX_NPEMH_NPE_STAT_OFNE (1 << 16) /**< OutFifoNotEmpty */
-#define IX_NPEMH_NPE_STAT_IFNF (1 << 17) /**< InFifoNotFull */
-#define IX_NPEMH_NPE_STAT_OFNF (1 << 18) /**< OutFifoNotFull */
-#define IX_NPEMH_NPE_STAT_IFNE (1 << 19) /**< InFifoNotEmpty */
-#define IX_NPEMH_NPE_STAT_MBINT (1 << 20) /**< Mailbox interrupt */
-#define IX_NPEMH_NPE_STAT_IFINT (1 << 21) /**< InFifo interrupt */
-#define IX_NPEMH_NPE_STAT_OFINT (1 << 22) /**< OutFifo interrupt */
-#define IX_NPEMH_NPE_STAT_WFINT (1 << 23) /**< WatchFifo interrupt */
-
-
-/**
- * Variable declarations. Externs are followed by static variables.
- */
-extern IxNpeMhConfigNpeInfo ixNpeMhConfigNpeInfo[IX_NPEMH_NUM_NPES];
-
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- * @fn void ixNpeMhConfigInitialize (
- IxNpeMhNpeInterrupts npeInterrupts)
- *
- * @brief This function initialises the Configuration module.
- *
- * @param IxNpeMhNpeInterrupts npeInterrupts (in) - whether or not to
- * service the NPE "outFIFO not empty" interrupts.
- *
- * @return No return value.
- */
-
-void ixNpeMhConfigInitialize (
- IxNpeMhNpeInterrupts npeInterrupts);
-
-/**
- * @fn void ixNpeMhConfigUninit (void)
- *
- * @brief This function uninitialises the Configuration module.
- *
- * @return No return value.
- */
-
-void ixNpeMhConfigUninit (void);
-
-/**
- * @fn void ixNpeMhConfigIsrRegister (
- IxNpeMhNpeId npeId,
- IxNpeMhConfigIsr isr)
- *
- * @brief This function registers an ISR to handle NPE "outFIFO not
- * empty" interrupts.
- *
- * @param IxNpeMhNpeId npeId (in) - the ID of the NPE whose interrupt will
- * be handled.
- * @param IxNpeMhConfigIsr isr (in) - the ISR function pointer that the
- * interrupt will trigger.
- *
- * @return No return value.
- */
-
-void ixNpeMhConfigIsrRegister (
- IxNpeMhNpeId npeId,
- IxNpeMhConfigIsr isr);
-
-/**
- * @fn BOOL ixNpeMhConfigNpeInterruptEnable (
- IxNpeMhNpeId npeId)
- *
- * @brief This function enables a NPE's "outFIFO not empty" interrupt.
- *
- * @param IxNpeMhNpeId npeId (in) - the ID of the NPE whose interrupt will
- * be enabled.
- *
- * @return Returns the previous state of the interrupt (TRUE => enabled).
- */
-
-BOOL ixNpeMhConfigNpeInterruptEnable (
- IxNpeMhNpeId npeId);
-
-/**
- * @fn BOOL ixNpeMhConfigNpeInterruptDisable (
- IxNpeMhNpeId npeId)
- *
- * @brief This function disables a NPE's "outFIFO not empty" interrupt
- *
- * @param IxNpeMhNpeId npeId (in) - the ID of the NPE whose interrupt will
- * be disabled.
- *
- * @return Returns the previous state of the interrupt (TRUE => enabled).
- */
-
-BOOL ixNpeMhConfigNpeInterruptDisable (
- IxNpeMhNpeId npeId);
-
-/**
- * @fn IxNpeMhMessageId ixNpeMhConfigMessageIdGet (
- IxNpeMhMessage message)
- *
- * @brief This function gets the ID of a message.
- *
- * @param IxNpeMhMessage message (in) - the message to get the ID of.
- *
- * @return the ID of the message
- */
-
-IxNpeMhMessageId ixNpeMhConfigMessageIdGet (
- IxNpeMhMessage message);
-
-/**
- * @fn BOOL ixNpeMhConfigNpeIdIsValid (
- IxNpeMhNpeId npeId)
- *
- * @brief This function checks to see if a NPE ID is valid.
- *
- * @param IxNpeMhNpeId npeId (in) - the NPE ID to validate.
- *
- * @return True if the NPE ID is valid, otherwise False.
- */
-
-BOOL ixNpeMhConfigNpeIdIsValid (
- IxNpeMhNpeId npeId);
-
-/**
- * @fn void ixNpeMhConfigLockGet (
- IxNpeMhNpeId npeId)
- *
- * @brief This function gets a lock for exclusive NPE interaction, and
- * disables the NPE's "outFIFO not empty" interrupt.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which to get the
- * lock and disable its interrupt.
- *
- * @return No return value.
- */
-
-void ixNpeMhConfigLockGet (
- IxNpeMhNpeId npeId);
-
-/**
- * @fn void ixNpeMhConfigLockRelease (
- IxNpeMhNpeId npeId)
- *
- * @brief This function releases a lock for exclusive NPE interaction, and
- * enables the NPE's "outFIFO not empty" interrupt.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which to release
- * the lock and enable its interrupt.
- *
- * @return No return value.
- */
-
-void ixNpeMhConfigLockRelease (
- IxNpeMhNpeId npeId);
-
-/**
- * @fn BOOL ixNpeMhConfigInFifoIsEmpty (
- IxNpeMhNpeId npeId)
- *
- * @brief This inline function checks if a NPE's inFIFO is empty.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the inFIFO
- * will be checked.
- *
- * @return True if the inFIFO is empty, otherwise False.
- */
-
-IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigInFifoIsEmpty (
- IxNpeMhNpeId npeId);
-
-/**
- * @fn BOOL ixNpeMhConfigInFifoIsFull (
- IxNpeMhNpeId npeId)
- *
- * @brief This inline function checks if a NPE's inFIFO is full.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the inFIFO
- * will be checked.
- *
- * @return True if the inFIFO is full, otherwise False.
- */
-
-IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigInFifoIsFull (
- IxNpeMhNpeId npeId);
-
-/**
- * @fn BOOL ixNpeMhConfigOutFifoIsEmpty (
- IxNpeMhNpeId npeId)
- *
- * @brief This inline function checks if a NPE's outFIFO is empty.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the outFIFO
- * will be checked.
- *
- * @return True if the outFIFO is empty, otherwise False.
- */
-
-IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigOutFifoIsEmpty (
- IxNpeMhNpeId npeId);
-
-/**
- * @fn BOOL ixNpeMhConfigOutFifoIsFull (
- IxNpeMhNpeId npeId)
- *
- * @brief This inline function checks if a NPE's outFIFO is full.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the outFIFO
- * will be checked.
- *
- * @return True if the outFIFO is full, otherwise False.
- */
-
-IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigOutFifoIsFull (
- IxNpeMhNpeId npeId);
-
-/**
- * @fn IX_STATUS ixNpeMhConfigInFifoWrite (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage message)
- *
- * @brief This function writes a message to a NPE's inFIFO. The caller
- * must first check that the NPE's inFifo is not full. After writing the first
- * word of the message, this function will keep polling NPE's inFIFO is not
- * full to write the second word. If inFIFO is not available after maximum
- * retries (IX_NPE_MH_MAX_NUM_OF_RETRIES), this function will return TIMEOUT
- * status to indicate NPE hang / halt.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the inFIFO
- * will be written to.
- * @param IxNpeMhMessage message (in) - The message to write.
- *
- * @return The function returns a status indicating success, failure or timeout.
- */
-
-IX_STATUS ixNpeMhConfigInFifoWrite (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage message);
-
-/**
- * @fn IX_STATUS ixNpeMhConfigOutFifoRead (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage *message)
- *
- * @brief This function reads a message from a NPE's outFIFO. The caller
- * must first check that the NPE's outFifo is not empty. After reading the first
- * word of the message, this function will keep polling NPE's outFIFO is not
- * empty to read the second word. If outFIFO is empty after maximum
- * retries (IX_NPE_MH_MAX_NUM_OF_RETRIES), this function will return TIMEOUT
- * status to indicate NPE hang / halt.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the outFIFO
- * will be read from.
- * @param IxNpeMhMessage message (out) - The message read.
- *
- * @return The function returns a status indicating success, failure or timeout.
- */
-
-IX_STATUS ixNpeMhConfigOutFifoRead (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage *message);
-
-/**
- * @fn void ixNpeMhConfigShow (
- IxNpeMhNpeId npeId)
- *
- * @brief This function will display the current state of the Configuration
- * module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to display state
- * information for.
- *
- * @return No return value.
- */
-
-void ixNpeMhConfigShow (
- IxNpeMhNpeId npeId);
-
-/**
- * @fn void ixNpeMhConfigShowReset (
- IxNpeMhNpeId npeId)
- *
- * @brief This function will reset the current state of the Configuration
- * module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to reset state
- * information for.
- *
- * @return No return value.
- */
-
-void ixNpeMhConfigShowReset (
- IxNpeMhNpeId npeId);
-
-/*
- * Inline functions
- */
-
-/*
- * This inline function checks if a NPE's inFIFO is empty.
- */
-
-IXNPEMHCONFIG_INLINE
-BOOL ixNpeMhConfigInFifoIsEmpty (
- IxNpeMhNpeId npeId)
-{
- UINT32 ifne;
- volatile UINT32 *statusReg =
- (UINT32 *)ixNpeMhConfigNpeInfo[npeId].statusRegister;
-
- /* get the IFNE (InFifoNotEmpty) bit of the status register */
- IX_NPEMH_REGISTER_READ_BITS (statusReg, &ifne, IX_NPEMH_NPE_STAT_IFNE);
-
- /* if the IFNE status bit is unset then the inFIFO is empty */
- return (ifne == 0);
-}
-
-
-/*
- * This inline function checks if a NPE's inFIFO is full.
- */
-IXNPEMHCONFIG_INLINE
-BOOL ixNpeMhConfigInFifoIsFull (
- IxNpeMhNpeId npeId)
-{
- UINT32 ifnf;
- volatile UINT32 *statusReg =
- (UINT32 *)ixNpeMhConfigNpeInfo[npeId].statusRegister;
-
- /* get the IFNF (InFifoNotFull) bit of the status register */
- IX_NPEMH_REGISTER_READ_BITS (statusReg, &ifnf, IX_NPEMH_NPE_STAT_IFNF);
-
- /* if the IFNF status bit is unset then the inFIFO is full */
- return (ifnf == 0);
-}
-
-
-/*
- * This inline function checks if a NPE's outFIFO is empty.
- */
-IXNPEMHCONFIG_INLINE
-BOOL ixNpeMhConfigOutFifoIsEmpty (
- IxNpeMhNpeId npeId)
-{
- UINT32 ofne;
- volatile UINT32 *statusReg =
- (UINT32 *)ixNpeMhConfigNpeInfo[npeId].statusRegister;
-
- /* get the OFNE (OutFifoNotEmpty) bit of the status register */
- IX_NPEMH_REGISTER_READ_BITS (statusReg, &ofne, IX_NPEMH_NPE_STAT_OFNE);
-
- /* if the OFNE status bit is unset then the outFIFO is empty */
- return (ofne == 0);
-}
-
-/*
- * This inline function checks if a NPE's outFIFO is full.
- */
-IXNPEMHCONFIG_INLINE
-BOOL ixNpeMhConfigOutFifoIsFull (
- IxNpeMhNpeId npeId)
-{
- UINT32 ofnf;
- volatile UINT32 *statusReg =
- (UINT32 *)ixNpeMhConfigNpeInfo[npeId].statusRegister;
-
- /* get the OFNF (OutFifoNotFull) bit of the status register */
- IX_NPEMH_REGISTER_READ_BITS (statusReg, &ofnf, IX_NPEMH_NPE_STAT_OFNF);
-
- /* if the OFNF status bit is unset then the outFIFO is full */
- return (ofnf == 0);
-}
-
-#endif /* IXNPEMHCONFIG_P_H */
-
-/**
- * @} defgroup IxNpeMhConfig_p
- */
+++ /dev/null
-/**
- * @file IxNpeMhMacros_p.h
- *
- * @author Intel Corporation
- * @date 21 Jan 2002
- *
- * @brief This file contains the macros for the IxNpeMh component.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeMhMacros_p IxNpeMhMacros_p
- *
- * @brief Macros for the IxNpeMh component.
- *
- * @{
- */
-
-#ifndef IXNPEMHMACROS_P_H
-#define IXNPEMHMACROS_P_H
-
-/* if we are running as a unit test */
-#ifdef IX_UNIT_TEST
-#undef NDEBUG
-#endif /* #ifdef IX_UNIT_TEST */
-
-#include "IxOsal.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-#define IX_NPEMH_SHOW_TEXT_WIDTH (40) /**< text width for stats display */
-#define IX_NPEMH_SHOW_STAT_WIDTH (10) /**< stat width for stats display */
-
-/**
- * @def IX_NPEMH_SHOW
- *
- * @brief Macro for displaying a stat preceded by a textual description.
- */
-
-#define IX_NPEMH_SHOW(TEXT, STAT) \
- ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, \
- "%-40s: %10d\n", (int) TEXT, (int) STAT, 0, 0, 0, 0)
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- * @typedef IxNpeMhTraceTypes
- *
- * @brief Enumeration defining IxNpeMh trace levels
- */
-
-typedef enum
-{
- IX_NPEMH_TRACE_OFF = IX_OSAL_LOG_LVL_NONE, /**< no trace */
- IX_NPEMH_WARNING = IX_OSAL_LOG_LVL_WARNING, /**< warning */
- IX_NPEMH_DEBUG = IX_OSAL_LOG_LVL_MESSAGE, /**< debug */
- IX_NPEMH_FN_ENTRY_EXIT = IX_OSAL_LOG_LVL_DEBUG3 /**< function entry/exit */
-} IxNpeMhTraceTypes;
-
-#ifdef IX_UNIT_TEST
-#define IX_NPEMH_TRACE_LEVEL (IX_NPEMH_FN_ENTRY_EXIT) /**< trace level */
-#else
-#define IX_NPEMH_TRACE_LEVEL (IX_NPEMH_TRACE_OFF) /**< trace level */
-#endif
-
-/**
- * @def IX_NPEMH_TRACE0
- *
- * @brief Trace macro taking 0 arguments.
- */
-
-#define IX_NPEMH_TRACE0(LEVEL, STR) \
- IX_NPEMH_TRACE6(LEVEL, STR, 0, 0, 0, 0, 0, 0)
-
-/**
- * @def IX_NPEMH_TRACE1
- *
- * @brief Trace macro taking 1 argument.
- */
-
-#define IX_NPEMH_TRACE1(LEVEL, STR, ARG1) \
- IX_NPEMH_TRACE6(LEVEL, STR, ARG1, 0, 0, 0, 0, 0)
-
-/**
- * @def IX_NPEMH_TRACE2
- *
- * @brief Trace macro taking 2 arguments.
- */
-
-#define IX_NPEMH_TRACE2(LEVEL, STR, ARG1, ARG2) \
- IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, 0, 0, 0, 0)
-
-/**
- * @def IX_NPEMH_TRACE3
- *
- * @brief Trace macro taking 3 arguments.
- */
-
-#define IX_NPEMH_TRACE3(LEVEL, STR, ARG1, ARG2, ARG3) \
- IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, 0, 0, 0)
-
-/**
- * @def IX_NPEMH_TRACE4
- *
- * @brief Trace macro taking 4 arguments.
- */
-
-#define IX_NPEMH_TRACE4(LEVEL, STR, ARG1, ARG2, ARG3, ARG4) \
- IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, 0, 0)
-
-/**
- * @def IX_NPEMH_TRACE5
- *
- * @brief Trace macro taking 5 arguments.
- */
-
-#define IX_NPEMH_TRACE5(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, ARG5) \
- IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, ARG5, 0)
-
-/**
- * @def IX_NPEMH_TRACE6
- *
- * @brief Trace macro taking 6 arguments.
- */
-
-#define IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6) \
-{ \
- if (LEVEL <= IX_NPEMH_TRACE_LEVEL) \
- { \
- (void) ixOsalLog (LEVEL, IX_OSAL_LOG_DEV_STDOUT, (STR), \
- (int)(ARG1), (int)(ARG2), (int)(ARG3), \
- (int)(ARG4), (int)(ARG5), (int)(ARG6)); \
- } \
-}
-
-/**
- * @def IX_NPEMH_ERROR_REPORT
- *
- * @brief Error reporting facility.
- */
-
-#define IX_NPEMH_ERROR_REPORT(STR) \
-{ \
- (void) ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, \
- (STR), 0, 0, 0, 0, 0, 0); \
-}
-
-/* if we are running on XScale, i.e. real environment */
-#if CPU==XSCALE
-
-/**
- * @def IX_NPEMH_REGISTER_READ
- *
- * @brief This macro reads a memory-mapped register.
- */
-
-#define IX_NPEMH_REGISTER_READ(registerAddress, value) \
-{ \
- *value = IX_OSAL_READ_LONG(registerAddress); \
-}
-
-/**
- * @def IX_NPEMH_REGISTER_READ_BITS
- *
- * @brief This macro partially reads a memory-mapped register.
- */
-
-#define IX_NPEMH_REGISTER_READ_BITS(registerAddress, value, mask) \
-{ \
- *value = (IX_OSAL_READ_LONG(registerAddress) & mask); \
-}
-
-/**
- * @def IX_NPEMH_REGISTER_WRITE
- *
- * @brief This macro writes a memory-mapped register.
- */
-
-#define IX_NPEMH_REGISTER_WRITE(registerAddress, value) \
-{ \
- IX_OSAL_WRITE_LONG(registerAddress, value); \
-}
-
-/**
- * @def IX_NPEMH_REGISTER_WRITE_BITS
- *
- * @brief This macro partially writes a memory-mapped register.
- */
-
-#define IX_NPEMH_REGISTER_WRITE_BITS(registerAddress, value, mask) \
-{ \
- UINT32 orig = IX_OSAL_READ_LONG(registerAddress); \
- orig &= (~mask); \
- orig |= (value & mask); \
- IX_OSAL_WRITE_LONG(registerAddress, orig); \
-}
-
-
-/* if we are running as a unit test */
-#else /* #if CPU==XSCALE */
-
-#include "IxNpeMhTestRegister.h"
-
-/**
- * @def IX_NPEMH_REGISTER_READ
- *
- * @brief This macro reads a memory-mapped register.
- */
-
-#define IX_NPEMH_REGISTER_READ(registerAddress, value) \
-{ \
- ixNpeMhTestRegisterRead (registerAddress, value); \
-}
-
-/**
- * @def IX_NPEMH_REGISTER_READ_BITS
- *
- * @brief This macro partially reads a memory-mapped register.
- */
-
-#define IX_NPEMH_REGISTER_READ_BITS(registerAddress, value, mask) \
-{ \
- ixNpeMhTestRegisterReadBits (registerAddress, value, mask); \
-}
-
-/**
- * @def IX_NPEMH_REGISTER_WRITE
- *
- * @brief This macro writes a memory-mapped register.
- */
-
-#define IX_NPEMH_REGISTER_WRITE(registerAddress, value) \
-{ \
- ixNpeMhTestRegisterWrite (registerAddress, value); \
-}
-
-/**
- * @def IX_NPEMH_REGISTER_WRITE_BITS
- *
- * @brief This macro partially writes a memory-mapped register.
- */
-
-#define IX_NPEMH_REGISTER_WRITE_BITS(registerAddress, value, mask) \
-{ \
- ixNpeMhTestRegisterWriteBits (registerAddress, value, mask); \
-}
-
-#endif /* #if CPU==XSCALE */
-
-#endif /* IXNPEMHMACROS_P_H */
-
-/**
- * @} defgroup IxNpeMhMacros_p
- */
+++ /dev/null
-/**
- * @file IxNpeMhReceive_p.h
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the private API for the Receive module.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeMhReceive_p IxNpeMhReceive_p
- *
- * @brief The private API for the Receive module.
- *
- * @{
- */
-
-#ifndef IXNPEMHRECEIVE_P_H
-#define IXNPEMHRECEIVE_P_H
-
-#include "IxNpeMh.h"
-#include "IxOsalTypes.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- * @fn void ixNpeMhReceiveInitialize (void)
- *
- * @brief This function registers an internal ISR to handle the NPEs'
- * "outFIFO not empty" interrupts and receive messages from the NPEs when
- * they become available.
- *
- * @return No return value.
- */
-
-void ixNpeMhReceiveInitialize (void);
-
-/**
- * @fn IX_STATUS ixNpeMhReceiveMessagesReceive (
- IxNpeMhNpeId npeId)
- *
- * @brief This function reads messages from a particular NPE's outFIFO
- * until the outFIFO is empty, and for each message looks first for an
- * unsolicited callback, then a solicited callback, to pass the message
- * back to the client. If no callback can be found the message is
- * discarded and an error reported. This function will return TIMEOUT
- * status if NPE hang / halt.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to receive
- * messages from.
- *
- * @return The function returns a status indicating success, failure or timeout.
- */
-
-IX_STATUS ixNpeMhReceiveMessagesReceive (
- IxNpeMhNpeId npeId);
-
-/**
- * @fn void ixNpeMhReceiveShow (
- IxNpeMhNpeId npeId)
- *
- * @brief This function will display the current state of the Receive
- * module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to display state
- * information for.
- *
- * @return No return status.
- */
-
-void ixNpeMhReceiveShow (
- IxNpeMhNpeId npeId);
-
-/**
- * @fn void ixNpeMhReceiveShowReset (
- IxNpeMhNpeId npeId)
- *
- * @brief This function will reset the current state of the Receive
- * module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to reset state
- * information for.
- *
- * @return No return status.
- */
-
-void ixNpeMhReceiveShowReset (
- IxNpeMhNpeId npeId);
-
-#endif /* IXNPEMHRECEIVE_P_H */
-
-/**
- * @} defgroup IxNpeMhReceive_p
- */
+++ /dev/null
-/**
- * @file IxNpeMhSend_p.h
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the private API for the Send module.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeMhSend_p IxNpeMhSend_p
- *
- * @brief The private API for the Send module.
- *
- * @{
- */
-
-#ifndef IXNPEMHSEND_P_H
-#define IXNPEMHSEND_P_H
-
-#include "IxNpeMh.h"
-#include "IxOsalTypes.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- * @fn IX_STATUS ixNpeMhSendMessageSend (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage message,
- UINT32 maxSendRetries)
- *
- * @brief This function writes a message to the specified NPE's inFIFO,
- * and must be used when the message being sent does not solicit a response
- * from the NPE. This function will return TIMEOUT status if NPE hang / halt.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to send the message
- * to.
- * @param IxNpeMhMessage message (in) - The message to send.
- * @param UINT32 maxSendRetries (in) - Max num. of retries to perform
- * if the NPE's inFIFO is full.
- *
- * @return The function returns a status indicating success, failure or timeout.
- */
-
-IX_STATUS ixNpeMhSendMessageSend (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage message,
- UINT32 maxSendRetries);
-
-/**
- * @fn IX_STATUS ixNpeMhSendMessageWithResponseSend (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage message,
- IxNpeMhMessageId solicitedMessageId,
- IxNpeMhCallback solicitedCallback,
- UINT32 maxSendRetries)
- *
- * @brief This function writes a message to the specified NPE's inFIFO,
- * and must be used when the message being sent solicits a response from
- * the NPE. The ID of the solicited response must be specified so that it
- * can be recognised, and a callback provided to pass the response back to
- * the client. This function will return TIMEOUT status if NPE hang / halt.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to send the message
- * to.
- * @param IxNpeMhMessage message (in) - The message to send.
- * @param IxNpeMhMessageId solicitedMessageId (in) - The ID of the
- * solicited response.
- * @param IxNpeMhCallback solicitedCallback (in) - The callback to pass the
- * solicited response back to the client.
- * @param UINT32 maxSendRetries (in) - Max num. of retries to perform
- * if the NPE's inFIFO is full.
- *
- * @return The function returns a status indicating success, failure or timeout.
- */
-
-IX_STATUS ixNpeMhSendMessageWithResponseSend (
- IxNpeMhNpeId npeId,
- IxNpeMhMessage message,
- IxNpeMhMessageId solicitedMessageId,
- IxNpeMhCallback solicitedCallback,
- UINT32 maxSendRetries);
-
-/**
- * @fn void ixNpeMhSendShow (
- IxNpeMhNpeId npeId)
- *
- * @brief This function will display the current state of the Send module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to display state
- * information for.
- *
- * @return No return value.
- */
-
-void ixNpeMhSendShow (
- IxNpeMhNpeId npeId);
-
-/**
- * @fn void ixNpeMhSendShowReset (
- IxNpeMhNpeId npeId)
- *
- * @brief This function will reset the current state of the Send module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to reset state
- * information for.
- *
- * @return No return value.
- */
-
-void ixNpeMhSendShowReset (
- IxNpeMhNpeId npeId);
-
-#endif /* IXNPEMHSEND_P_H */
-
-/**
- * @} defgroup IxNpeMhSend_p
- */
+++ /dev/null
-/**
- * @file IxNpeMhSolicitedCbMgr_p.h
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the private API for the Solicited Callback
- * Manager module.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeMhSolicitedCbMgr_p IxNpeMhSolicitedCbMgr_p
- *
- * @brief The private API for the Solicited Callback Manager module.
- *
- * @{
- */
-
-#ifndef IXNPEMHSOLICITEDCBMGR_P_H
-#define IXNPEMHSOLICITEDCBMGR_P_H
-
-#include "IxNpeMh.h"
-#include "IxOsalTypes.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-/** Maximum number of solicited callbacks that can be stored in the list */
-#define IX_NPEMH_MAX_CALLBACKS (16)
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- * @fn void ixNpeMhSolicitedCbMgrInitialize (void)
- *
- * @brief This function initializes the Solicited Callback Manager module,
- * setting up a callback data structure for each NPE.
- *
- * @return No return value.
- */
-
-void ixNpeMhSolicitedCbMgrInitialize (void);
-
-/**
- * @fn IX_STATUS ixNpeMhSolicitedCbMgrCallbackSave (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId solicitedMessageId,
- IxNpeMhCallback solicitedCallback)
- *
- * @brief This function saves a callback in the specified NPE's callback
- * list. If the callback list is full the function will fail.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE in whose callback
- * list the callback will be saved.
- * @param IxNpeMhMessageId solicitedMessageId (in) - The ID of the message
- * that this callback is for.
- * @param IxNpeMhCallback solicitedCallback (in) - The callback function
- * pointer to save.
- *
- * @return The function returns a status indicating success or failure.
- */
-
-IX_STATUS ixNpeMhSolicitedCbMgrCallbackSave (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId solicitedMessageId,
- IxNpeMhCallback solicitedCallback);
-
-/**
- * @fn void ixNpeMhSolicitedCbMgrCallbackRetrieve (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId solicitedMessageId,
- IxNpeMhCallback *solicitedCallback)
- *
- * @brief This function retrieves the first ID-matching callback from the
- * specified NPE's callback list. If no matching callback can be found the
- * function will fail.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE from whose callback
- * list the callback will be retrieved.
- * @param IxNpeMhMessageId solicitedMessageId (in) - The ID of the message
- * that the callback is for.
- * @param IxNpeMhCallback solicitedCallback (out) - The callback function
- * pointer retrieved.
- *
- * @return No return value.
- */
-
-void ixNpeMhSolicitedCbMgrCallbackRetrieve (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId solicitedMessageId,
- IxNpeMhCallback *solicitedCallback);
-
-/**
- * @fn void ixNpeMhSolicitedCbMgrShow (
- IxNpeMhNpeId npeId)
- *
- * @brief This function will display the current state of the Solicited
- * Callback Manager module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to display state
- * information for.
- *
- * @return No return value.
- */
-
-void ixNpeMhSolicitedCbMgrShow (
- IxNpeMhNpeId npeId);
-
-/**
- * @fn void ixNpeMhSolicitedCbMgrShowReset (
- IxNpeMhNpeId npeId)
- *
- * @brief This function will reset the current state of the Solicited
- * Callback Manager module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to reset state
- * information for.
- *
- * @return No return value.
- */
-
-void ixNpeMhSolicitedCbMgrShowReset (
- IxNpeMhNpeId npeId);
-
-#endif /* IXNPEMHSOLICITEDCBMGR_P_H */
-
-/**
- * @} defgroup IxNpeMhSolicitedCbMgr_p
- */
+++ /dev/null
-/**
- * @file IxNpeMhUnsolicitedCbMgr_p.h
- *
- * @author Intel Corporation
- * @date 18 Jan 2002
- *
- * @brief This file contains the private API for the Unsolicited Callback
- * Manager module.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxNpeMhUnsolicitedCbMgr_p IxNpeMhUnsolicitedCbMgr_p
- *
- * @brief The private API for the Unsolicited Callback Manager module.
- *
- * @{
- */
-
-#ifndef IXNPEMHUNSOLICITEDCBMGR_P_H
-#define IXNPEMHUNSOLICITEDCBMGR_P_H
-
-#include "IxNpeMh.h"
-#include "IxOsalTypes.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- * @fn void ixNpeMhUnsolicitedCbMgrInitialize (void)
- *
- * @brief This function initializes the Unsolicited Callback Manager
- * module, setting up a callback data structure for each NPE.
- *
- * @return No return value.
- */
-
-void ixNpeMhUnsolicitedCbMgrInitialize (void);
-
-/**
- * @fn void ixNpeMhUnsolicitedCbMgrCallbackSave (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId unsolicitedMessageId,
- IxNpeMhCallback unsolicitedCallback)
- *
- * @brief This function saves a callback in the specified NPE's callback
- * table. If a callback already exists for the specified ID then it will
- * be overwritten.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE in whose callback
- * table the callback will be saved.
- * @param IxNpeMhMessageId unsolicitedMessageId (in) - The ID of the
- * messages that this callback is for.
- * @param IxNpeMhCallback unsolicitedCallback (in) - The callback function
- * pointer to save.
- *
- * @return No return value.
- */
-
-void ixNpeMhUnsolicitedCbMgrCallbackSave (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId unsolicitedMessageId,
- IxNpeMhCallback unsolicitedCallback);
-
-/**
- * @fn void ixNpeMhUnsolicitedCbMgrCallbackRetrieve (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId unsolicitedMessageId,
- IxNpeMhCallback *unsolicitedCallback)
- *
- * @brief This function retrieves the callback for the specified ID from
- * the specified NPE's callback table. If no callback is registered for
- * the specified ID and NPE then a callback value of NULL will be returned.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE from whose callback
- * table the callback will be retrieved.
- * @param IxNpeMhMessageId unsolicitedMessageId (in) - The ID of the
- * messages that the callback is for.
- * @param IxNpeMhCallback unsolicitedCallback (out) - The callback function
- * pointer retrieved.
- *
- * @return No return value.
- */
-
-void ixNpeMhUnsolicitedCbMgrCallbackRetrieve (
- IxNpeMhNpeId npeId,
- IxNpeMhMessageId unsolicitedMessageId,
- IxNpeMhCallback *unsolicitedCallback);
-
-/**
- * @fn void ixNpeMhUnsolicitedCbMgrShow (
- IxNpeMhNpeId npeId)
- *
- * @brief This function will display the current state of the Unsolicited
- * Callback Manager module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to display state
- * information for.
- *
- * @return No return value.
- */
-
-void ixNpeMhUnsolicitedCbMgrShow (
- IxNpeMhNpeId npeId);
-
-/**
- * @fn void ixNpeMhUnsolicitedCbMgrShowReset (
- IxNpeMhNpeId npeId)
- *
- * @brief This function will reset the current state of the Unsolicited
- * Callback Manager module.
- *
- * @param IxNpeMhNpeId npeId (in) - The ID of the NPE to reset state
- * information for.
- *
- * @return No return value.
- */
-
-void ixNpeMhUnsolicitedCbMgrShowReset (
- IxNpeMhNpeId npeId);
-
-#endif /* IXNPEMHUNSOLICITEDCBMGR_P_H */
-
-/**
- * @} defgroup IxNpeMhUnsolicitedCbMgr_p
- */
+++ /dev/null
-/**
- * @date April 18, 2005
- *
- * @brief IXP400 NPE Microcode Image file
- *
- * This file was generated by the IxNpeDlImageGen tool.
- * It contains a NPE microcode image suitable for use
- * with the NPE Downloader (IxNpeDl) component in the
- * IXP400 Access Driver software library.
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxNpeMicrocode IXP400 NPE Microcode Image Library
- *
- * @brief Library containing a set of NPE firmware images, for use
- * with NPE Downloader s/w component
- *
- * @{
- */
-
-/**
- * @def IX_NPE_IMAGE_INCLUDE
- *
- * @brief Wrap the following Image identifiers with "#if IX_NPE_IMAGE_INCLUDE ... #endif" to include the image in the library
- */
-#define IX_NPE_IMAGE_INCLUDE 1
-
-/**
- * @def IX_NPE_IMAGE_OMIT
- *
- * @brief Wrap the following Image identifiers with "#if IX_NPE_IMAGE_OMIT ... #endif" to OMIT the image from the library
- */
-#define IX_NPE_IMAGE_OMIT 0
-
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_HSS0
- *
- * @brief NPE Image Id for NPE-A with HSS-0 Only feature. It supports 32 channelized and 4 packetized.
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_HSS0 0x00010000
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_SPHY_1_PORT
- *
- * @brief NPE Image Id for NPE-A with HSS-0 and ATM feature. For HSS, it supports 16/32 channelized and 4/0 packetized. For ATM, it supports AAL5, AAL0 and OAM for UTOPIA SPHY, 1 logical port, 32 VCs. It also has Fast Path support.
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_SPHY_1_PORT 0x00020000
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_MPHY_1_PORT
- *
- * @brief NPE Image Id for NPE-A with HSS-0 and ATM feature. For HSS, it supports 16/32 channelized and 4/0 packetized. For ATM, it supports AAL5, AAL0 and OAM for UTOPIA MPHY, 1 logical port, 32 VCs. It also has Fast Path support.
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_MPHY_1_PORT 0x00030000
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_ATM_MPHY_12_PORT
- *
- * @brief NPE Image Id for NPE-A with ATM-Only feature. It supports AAL5, AAL0 and OAM for UTOPIA MPHY, 12 logical ports, 32 VCs. It also has Fast Path support.
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_ATM_MPHY_12_PORT 0x00040000
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_DMA
- *
- * @brief NPE Image Id for NPE-A with DMA-Only feature.
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_DMA 0x00150100
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_HSS_2_PORT
- *
- * @brief NPE Image Id for NPE-A with HSS-0 and HSS-1 feature. Each HSS port supports 32 channelized and 4 packetized.
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_HSS_2_PORT 0x00090000
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_ETH
- *
- * @brief NPE Image Id for NPE-A with Basic Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_ETH 0x10800200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL
- *
- * @brief NPE Image Id for NPE-A with Basic Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL 0x10800200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
- *
- * @brief NPE Image Id for NPE-A with Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL, VLAN_QOS
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS 0x10810200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEA_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
- *
- * @brief NPE Image Id for NPE-A with Ethernet Rx/Tx which includes: SPANNING_TREE, FIREWALL, VLAN_QOS, HEADER_CONVERSION
- */
-#define IX_NPEDL_NPEIMAGE_NPEA_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV 0x10820200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEB_ETH
- *
- * @brief NPE Image Id for NPE-B with Basic Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL
- */
-#define IX_NPEDL_NPEIMAGE_NPEB_ETH 0x01000200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL
- *
- * @brief NPE Image Id for NPE-B with Basic Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL
- */
-#define IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL 0x01000200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
- *
- * @brief NPE Image Id for NPE-B with Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL, VLAN_QOS
- */
-#define IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS 0x01010200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEB_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
- *
- * @brief NPE Image Id for NPE-B with Ethernet Rx/Tx which includes: SPANNING_TREE, FIREWALL, VLAN_QOS, HEADER_CONVERSION
- */
-#define IX_NPEDL_NPEIMAGE_NPEB_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV 0x01020200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEB_DMA
- *
- * @brief NPE Image Id for NPE-B with DMA-Only feature.
- */
-#define IX_NPEDL_NPEIMAGE_NPEB_DMA 0x01020100
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEC_ETH
- *
- * @brief NPE Image Id for NPE-C with Basic Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL
- */
-#define IX_NPEDL_NPEIMAGE_NPEC_ETH 0x02000200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL
- *
- * @brief NPE Image Id for NPE-C with Basic Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL
- */
-#define IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL 0x02000200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
- *
- * @brief NPE Image Id for NPE-C with Ethernet Rx/Tx which includes: MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL, VLAN_QOS
- */
-#define IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS 0x02010200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEC_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
- *
- * @brief NPE Image Id for NPE-C with Ethernet Rx/Tx which includes: SPANNING_TREE, FIREWALL, VLAN_QOS, HEADER_CONVERSION
- */
-#define IX_NPEDL_NPEIMAGE_NPEC_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV 0x02020200
-#endif
-
-#if IX_NPE_IMAGE_INCLUDE
-/**
- * @def IX_NPEDL_NPEIMAGE_NPEC_DMA
- *
- * @brief NPE Image Id for NPE-C with DMA-Only feature.
- */
-#define IX_NPEDL_NPEIMAGE_NPEC_DMA 0x02080100
-#endif
-
-/* Number of NPE firmware images in this library */
-#define IX_NPE_MICROCODE_AVAILABLE_VERSIONS_COUNT 17
-
-/* Location of Microcode Images */
-#ifdef IX_NPE_MICROCODE_FIRMWARE_INCLUDED
-#ifdef IX_NPEDL_READ_MICROCODE_FROM_FILE
-
-extern UINT32* ixNpeMicrocode_binaryArray;
-
-#else
-
-extern unsigned IxNpeMicrocode_array[];
-
-#endif
-#endif
-
-/*
- * sr: undef all but the bare minimum to reduce flash usage for U-Boot
- */
-#undef IX_NPEDL_NPEIMAGE_NPEA_HSS0
-#undef IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_SPHY_1_PORT
-#undef IX_NPEDL_NPEIMAGE_NPEA_HSS0_ATM_MPHY_1_PORT
-#undef IX_NPEDL_NPEIMAGE_NPEA_ATM_MPHY_12_PORT
-#undef IX_NPEDL_NPEIMAGE_NPEA_DMA
-#undef IX_NPEDL_NPEIMAGE_NPEA_HSS_2_PORT
-#undef IX_NPEDL_NPEIMAGE_NPEA_ETH
-#undef IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL
-#undef IX_NPEDL_NPEIMAGE_NPEA_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS
-#undef IX_NPEDL_NPEIMAGE_NPEA_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
-#undef IX_NPEDL_NPEIMAGE_NPEB_ETH
-#undef IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL
-/* #undef IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS */
-#undef IX_NPEDL_NPEIMAGE_NPEB_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
-#undef IX_NPEDL_NPEIMAGE_NPEB_DMA
-#undef IX_NPEDL_NPEIMAGE_NPEC_ETH
-#undef IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL
-/* #undef IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS */
-#undef IX_NPEDL_NPEIMAGE_NPEC_ETH_SPAN_FIREWALL_VLAN_QOS_HDR_CONV
-#undef IX_NPEDL_NPEIMAGE_NPEC_DMA
-
-/**
- * @} defgroup IxNpeMicrocode
- */
+++ /dev/null
-/**
- * @file IxOsBufLib.h (Replaced by OSAL)
- *
- * @date 9 Oct 2002
- *
- * @brief This file contains the mbuf pool initialisation entry point
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- *
- */
-
-#ifndef IXOSBUFLIB_H
-#define IXOSBUFLIB_H
-
-#include "IxOsalBackward.h"
-
-#endif /* IXOSBUFLIB_H */
-
+++ /dev/null
-/**
- * @file (Replaced by OSAL)
- *
- * @brief This file includes the OS dependant MBUF header files.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#ifndef IxOsBuffMgt_inc
-#define IxOsBuffMgt_inc
-
-#include "IxOsalBackward.h"
-
-#endif /* ndef IxOsBuffMgt_inc */
+++ /dev/null
-/**
- * @file IxOsBuffPoolMgt.h (Replaced by OSAL)
- *
- * @date 9 Oct 2002
- *
- * @brief This file contains the mbuf pool implementation API
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- * This module contains the implementation of the OS Services buffer pool
- * management service. This module provides routines for creating pools
- * of buffers for exchange of network data, getting and returning buffers
- * from and to the pool, and some other utility functions.
- * <P>
- * Currently, the pool has 2 underlying implementations - one for the vxWorks
- * OS, and another which attempts to be OS-agnostic so that it can be used on
- * other OS's such as Linux. The API is largely the same for all OS's,
- * but there are some differences to be aware of. These are documented
- * in the API descriptions below.
- * <P>
- * The most significant difference is this: when this module is used with
- * the WindRiver VxWorks OS, it will create a pool of vxWorks "MBufs".
- * These can be used directly with the vxWorks "netBufLib" OS Library.
- * For other OS's, it will create a pool of generic buffers. These may need
- * to be converted into other buffer types (sk_buff's in Linux, for example)
- * before being used with any built-in OS routines available for
- * manipulating network data buffers.
- *
- * @sa IxOsBuffMgt.h
- */
-
-#ifndef IXOSBUFFPOOLMGT_H
-#define IXOSBUFFPOOLMGT_H
-
-#include "IxOsalBackward.h"
-
-#endif /* IXOSBUFFPOOLMGT_H */
-
+++ /dev/null
-/**
- * @file IxOsCacheMMU.h
- *
- * @brief this file contains the API of the @ref IxCacheMMU component
- *
- * <hr>
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsCacheMMU_H
-
-#ifndef __doxygen_hide
-#define IxOsCacheMMU_H
-#endif /* __doxygen_hide */
-
-#ifdef __doxygen_HIDE
-#define IX_OS_CACHE_DOXYGEN
-#endif /* __doxygen_HIDE */
-
-#include "IxOsalBackward.h"
-
-#endif /* IxOsCacheMMU_H */
-
+++ /dev/null
-/**
- * @file IxOsPrintf.h
- *
- * @brief this file contains the API of the @ref IxOsServices component
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxTypes.h"
-
-#ifndef IxOsPrintf_H
-
-#ifndef __doxygen_hide
-#define IxOsPrintf_H
-#endif /* __doxygen_hide */
-
-#ifdef __wince
-
-#ifndef IX_USE_SERCONSOLE
-
-static int
-ixLogMsg(
- char *pFormat,
- ...
- )
-{
-#ifndef IN_KERNEL
- static WCHAR pOutputString[256];
- static char pNarrowStr[256];
- int returnCnt = 0;
- va_list ap;
-
- pOutputString[0] = 0;
- pNarrowStr[0] = 0;
-
- va_start(ap, pFormat);
-
- returnCnt = _vsnprintf(pNarrowStr, 256, pFormat, ap);
-
- MultiByteToWideChar(
- CP_ACP,
- MB_PRECOMPOSED,
- pNarrowStr,
- -1,
- pOutputString,
- 256
- );
-
- OutputDebugString(pOutputString);
-
- return returnCnt;
-#else
- return 0;
-#endif
-}
-#define printf ixLogMsg
-
-#endif /* IX_USE_SERCONSOLE */
-
-#endif /* __wince */
-
-/**
- * @} IxOsPrintf
- */
-
-#endif /* IxOsPrintf_H */
+++ /dev/null
-/**
- * @file (Replaced by OSAL)
- *
- * @brief this file contains the API of the @ref IxOsServices component
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-#ifndef IxOsServices_H
-
-#ifndef __doxygen_hide
-#define IxOsServices_H
-#endif /* __doxygen_hide */
-
-#include "IxOsalBackward.h"
-
-#endif /* IxOsServices_H */
-
-
+++ /dev/null
-/**
- * @file IxOsServicesComponents.h (Replaced by OSAL)
- *
- * @brief Header file for memory access
- *
- * @par
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsServicesComponents_H
-#define IxOsServicesComponents_H
-
-#include "IxOsalBackward.h"
- * codelets_parityENAcc
- * timeSyncAcc
- * parityENAcc
- * sspAcc
- * i2c
- * integration_sspAcc
- * integration_i2c
-#define ix_timeSyncAcc 36
-#define ix_parityENAcc 37
-#define ix_codelets_parityENAcc 38
-#define ix_sspAcc 39
-#define ix_i2c 40
-#define ix_integration_sspAcc 41
-#define ix_integration_i2c 42
-#define ix_osal 43
-#define ix_integration_parityENAcc 44
-#define ix_integration_timeSyncAcc 45
-
-/***************************
- * timeSyncAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_timeSyncAcc)
-
-#if defined (IX_OSSERV_VXWORKS_LE)
-
-#define CSR_LE_DATA_COHERENT_MAPPING
-
-#endif /* IX_OSSERV_VXWORKS_LE */
-
-#endif /* timeSyncAcc */
-
-/***************************
- * parityENAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_parityENAcc)
-
-#if defined (IX_OSSERV_VXWORKS_LE)
-
-#define CSR_LE_DATA_COHERENT_MAPPING
-
-#endif /* IX_OSSERV_VXWORKS_LE */
-
-#endif /* parityENAcc */
-
-/***************************
- * codelets_parityENAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_parityENAcc)
-
-#if defined (IX_OSSERV_VXWORKS_LE)
-
-#define CSR_LE_DATA_COHERENT_MAPPING
-
-#endif /* IX_OSSERV_VXWORKS_LE */
-
-#endif /* codelets_parityENAcc */
-
-#endif /* IxOsServicesComponents_H */
-
-/***************************
- * integration_timeSyncAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_integration_timeSyncAcc)
-
-#if defined (IX_OSSERV_VXWORKS_LE)
-
-#define CSR_LE_DATA_COHERENT_MAPPING
-
-#endif /* IX_OSSERV_VXWORKS_LE */
-
-#endif /* integration_timeSyncAcc */
-
-/***************************
- * integration_parityENAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_integration_parityENAcc)
-
-#if defined (IX_OSSERV_VXWORKS_LE)
-
-#define CSR_LE_DATA_COHERENT_MAPPING
-
-#endif /* IX_OSSERV_VXWORKS_LE */
-
-#endif /* integration_parityENAcc */
+++ /dev/null
-/**
- * @file IxOsServicesEndianess.h (Replaced by OSAL)
- *
- * @brief Header file for determining system endianess and OS
- *
- * @par
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsServicesEndianess_H
-#define IxOsServicesEndianess_H
-
-#include "IxOsalBackward.h"
-
-#endif /* IxOsServicesEndianess_H */
+++ /dev/null
-/**
- * @file IxOsServicesMemAccess.h (Replaced by OSAL)
- *
- * @brief Header file for memory access
- *
- * @par
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsServicesMemAccess_H
-#define IxOsServicesMemAccess_H
-
-#include "IxOsalBackward.h"
-
-#endif /* IxOsServicesMemAccess_H */
+++ /dev/null
-/**
- * @file IxOsServicesMemMap.h (Replaced by OSAL)
- *
- * @brief Header file for memory access maps
- *
- * @par
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsServicesMemMap_H
-#define IxOsServicesMemMap_H
-
-#include "IxOsalBackward.h"
-#define IX_OSSERV_ETH_NPEA_MAP_SIZE (0x1000) /**< Eth for NPEA map size */
-#define IX_OSSERV_ETH_NPEA_PHYS_BASE IXP425_Eth_NPEA_BASE_PHYS
-
-#endif /* IxOsServicesMemMap_H */
+++ /dev/null
-/**
- * @file IxOsal.h
- *
- * @brief Top include file for OSAL
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsal_H
-#define IxOsal_H
-
-/* Basic types */
-#include "IxOsalTypes.h"
-
-/* Include assert */
-#include "IxOsalAssert.h"
-
-/*
- * Config header gives users option to choose IO MEM
- * and buffer management modules
- */
-
-#include "IxOsalConfig.h"
-
-/*
- * Symbol file needed by some OS.
- */
-#include "IxOsalUtilitySymbols.h"
-
-/* OS-specific header */
-#include "IxOsalOs.h"
-
-
-/**
- * @defgroup IxOsal Operating System Abstraction Layer (IxOsal) API
- *
- * @brief This service provides a thin layer of OS dependency services.
- *
- * This file contains the API to the functions which are some what OS dependant and would
- * require porting to a particular OS.
- * A primary focus of the component development is to make them as OS independent as possible.
- * All other components should abstract their OS dependency to this module.
- * Services overview
- * -# Data types, constants, defines
- * -# Interrupts
- * - bind interrupts to handlers
- * - unbind interrupts from handlers
- * - disables all interrupts
- * - enables all interrupts
- * - selectively disables interrupts
- * - enables an interrupt level
- * - disables an interrupt level
- * -# Memory
- * - allocates memory
- * - frees memory
- * - copies memory zones
- * - fills a memory zone
- * - allocates cache-safe memory
- * - frees cache-safe memory
- * - physical to virtual address translation
- * - virtual to physical address translation
- * - cache to memory flush
- * - cache line invalidate
- * -# Threads
- * - creates a new thread
- * - starts a newly created thread
- * - kills an existing thread
- * - exits a running thread
- * - sets the priority of an existing thread
- * - suspends thread execution
- * - resumes thread execution
- * -# IPC
- * - creates a message queue
- * - deletes a message queue
- * - sends a message to a message queue
- * - receives a message from a message queue
- * -# Thread Synchronisation
- * - initializes a mutex
- * - locks a mutex
- * - unlocks a mutex
- * - non-blocking attempt to lock a mutex
- * - destroys a mutex object
- * - initializes a fast mutex
- * - non-blocking attempt to lock a fast mutex
- * - unlocks a fast mutex
- * - destroys a fast mutex object
- * - initializes a semaphore
- * - posts to (increments) a semaphore
- * - waits on (decrements) a semaphore
- * - non-blocking wait on semaphore
- * - gets semaphore value
- * - destroys a semaphore object
- * - yields execution of current thread
- * -# Time functions
- * - yielding sleep for a number of milliseconds
- * - busy sleep for a number of microseconds
- * - value of the timestamp counter
- * - resolution of the timestamp counter
- * - system clock rate, in ticks
- * - current system time
- * - converts ixOsalTimeVal into ticks
- * - converts ticks into ixOsalTimeVal
- * - converts ixOsalTimeVal to milliseconds
- * - converts milliseconds to IxOsalTimeval
- * - "equal" comparison for IxOsalTimeval
- * - "less than" comparison for IxOsalTimeval
- * - "greater than" comparison for IxOsalTimeval
- * - "add" operator for IxOsalTimeval
- * - "subtract" operator for IxOsalTimeval
- * -# Logging
- * - sets the current logging verbosity level
- * - interrupt-safe logging function
- * -# Timer services
- * - schedules a repeating timer
- * - schedules a single-shot timer
- * - cancels a running timer
- * - displays all the running timers
- * -# Optional Modules
- * - Buffer management module
- * - I/O memory and endianess support module
- *
- * @{
- */
-
-
-/*
- * Prototypes
- */
-
-/* ========================== Interrupts ================================
- *
- */
-
-/**
- * @ingroup IxOsal
- *
- * @brief Binds an interrupt handler to an interrupt level
- *
- * @param irqLevel (in) - interrupt level
- * @param irqHandler (in) - interrupt handler
- * @param parameter (in) - custom parameter to be passed to the
- * interrupt handler
- *
- * Binds an interrupt handler to an interrupt level. The operation will
- * fail if the wrong level is selected, if the handler is NULL, or if the
- * interrupt is already bound. This functions binds the specified C
- * routine to an interrupt level. When called, the "parameter" value will
- * be passed to the routine.
- *
- * Reentrant: no
- * IRQ safe: no
- *
- * @return IX_SUCCESS if the operation succeeded or IX_FAIL otherwise
- */
-PUBLIC IX_STATUS ixOsalIrqBind (UINT32 irqLevel,
- IxOsalVoidFnVoidPtr irqHandler,
- void *parameter);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Unbinds an interrupt handler from an interrupt level
- *
- * @param irqLevel (in) - interrupt level
- *
- * Unbinds the selected interrupt level from any previously registered
- * handler
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return IX_SUCCESS if the operation succeeded or IX_FAIL otherwise
- */
-PUBLIC IX_STATUS ixOsalIrqUnbind (UINT32 irqLevel);
-
-
-/**
- * @ingroup IxOsal
- *
- * @brief Disables all interrupts
- *
- * @param - none
- *
- * Disables all the interrupts and prevents tasks scheduling
- *
- * @li Reentrant: no
- * @li IRQ safe: yes
- *
- * @return interrupt enable status prior to locking
- */
-PUBLIC UINT32 ixOsalIrqLock (void);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Enables all interrupts
- *
- * @param irqEnable (in) - interrupt enable status, prior to interrupt
- * locking
- *
- * Enables the interrupts and task scheduling, cancelling the effect
- * of ixOsalIrqLock()
- *
- * @li Reentrant: no
- * @li IRQ safe: yes
- *
- * @return IX_SUCCESS if the operation succeeded or IX_FAIL otherwise
- */
-PUBLIC void ixOsalIrqUnlock (UINT32 irqEnable);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Selectively disables interrupts
- *
- * @param irqLevel new interrupt level
- *
- * Disables the interrupts below the specified interrupt level
- *
- * @li Reentrant: no
- * @li IRQ safe: yes
- *
- * @note Depending on the implementation this function can disable all
- * the interrupts
- *
- * @return previous interrupt level
- */
-PUBLIC UINT32 ixOsalIrqLevelSet (UINT32 irqLevel);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Enables an interrupt level
- *
- * @param irqLevel interrupt level to enable
- *
- * Enables the specified interrupt level
- *
- * @li Reentrant: no
- * @li IRQ safe: yes
- *
- * @return - none
- */
-PUBLIC void ixOsalIrqEnable (UINT32 irqLevel);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Disables an interrupt level
- *
- * @param irqLevel interrupt level to disable
- *
- * Disables the specified interrupt level
- *
- * @li Reentrant: no
- * @li IRQ safe: yes
- *
- * @return - none
- */
-PUBLIC void ixOsalIrqDisable (UINT32 irqLevel);
-
-
-/* ============================= Memory =================================
- *
- */
-
-/**
- * @ingroup IxOsal
- *
- * @brief Allocates memory
- *
- * @param size - memory size to allocate, in bytes
- *
- * Allocates a memory zone of a given size
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return Pointer to the allocated zone or NULL if the allocation failed
- */
-PUBLIC void *ixOsalMemAlloc (UINT32 size);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Frees memory
- *
- * @param ptr - pointer to the memory zone
- *
- * Frees a previously allocated memory zone
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - none
- */
-PUBLIC void ixOsalMemFree (void *ptr);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Copies memory zones
- *
- * @param dest - destination memory zone
- * @param src - source memory zone
- * @param count - number of bytes to copy
- *
- * Copies count bytes from the source memory zone pointed by src into the
- * memory zone pointed by dest.
- *
- * @li Reentrant: no
- * @li IRQ safe: yes
- *
- * @return Pointer to the destination memory zone
- */
-PUBLIC void *ixOsalMemCopy (void *dest, void *src, UINT32 count);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Fills a memory zone
- *
- * @param ptr - pointer to the memory zone
- * @param filler - byte to fill the memory zone with
- * @param count - number of bytes to fill
- *
- * Fills a memory zone with a given constant byte
- *
- * @li Reentrant: no
- * @li IRQ safe: yes
- *
- * @return Pointer to the memory zone
- */
-PUBLIC void *ixOsalMemSet (void *ptr, UINT8 filler, UINT32 count);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Allocates cache-safe memory
- *
- * @param size - size, in bytes, of the allocated zone
- *
- * Allocates a cache-safe memory zone of at least "size" bytes and returns
- * the pointer to the memory zone. This memory zone, depending on the
- * platform, is either uncached or aligned on a cache line boundary to make
- * the CACHE_FLUSH and CACHE_INVALIDATE macros safe to use. The memory
- * allocated with this function MUST be freed with ixOsalCacheDmaFree(),
- * otherwise memory corruption can occur.
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return Pointer to the memory zone or NULL if allocation failed
- *
- * @note It is important to note that cache coherence is maintained in
- * software by using the IX_OSAL_CACHE_FLUSH and IX_OSAL_CACHE_INVALIDATE
- * macros to maintain consistency between cache and external memory.
- */
-PUBLIC void *ixOsalCacheDmaMalloc (UINT32 size);
-
-/* Macros for ixOsalCacheDmaMalloc*/
-#define IX_OSAL_CACHE_DMA_MALLOC(size) ixOsalCacheDmaMalloc(size)
-
-/**
- * @ingroup IxOsal
- *
- * @brief Frees cache-safe memory
- *
- * @param ptr - pointer to the memory zone
- *
- * Frees a memory zone previously allocated with ixOsalCacheDmaMalloc()
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - none
- */
-PUBLIC void ixOsalCacheDmaFree (void *ptr);
-
-#define IX_OSAL_CACHE_DMA_FREE(ptr) ixOsalCacheDmaFree(ptr)
-
-/**
- * @ingroup IxOsal
- *
- * @brief physical to virtual address translation
- *
- * @param physAddr - physical address
- *
- * Converts a physical address into its equivalent MMU-mapped virtual address
- *
- * @li Reentrant: no
- * @li IRQ safe: yes
- *
- * @return Corresponding virtual address, as UINT32
- */
-#define IX_OSAL_MMU_PHYS_TO_VIRT(physAddr) \
- IX_OSAL_OS_MMU_PHYS_TO_VIRT(physAddr)
-
-
-/**
- * @ingroup IxOsal
- *
- * @brief virtual to physical address translation
- *
- * @param virtAddr - virtual address
- *
- * Converts a virtual address into its equivalent MMU-mapped physical address
- *
- * @li Reentrant: no
- * @li IRQ safe: yes
- *
- * @return Corresponding physical address, as UINT32
- */
-#define IX_OSAL_MMU_VIRT_TO_PHYS(virtAddr) \
- IX_OSAL_OS_MMU_VIRT_TO_PHYS(virtAddr)
-
-
-
-/**
- * @ingroup IxOsal
- *
- * @brief cache to memory flush
- *
- * @param addr - memory address to flush from cache
- * @param size - number of bytes to flush (rounded up to a cache line)
- *
- * Flushes the cached value of the memory zone pointed by "addr" into memory,
- * rounding up to a cache line. Use before the zone is to be read by a
- * processing unit which is not cache coherent with the main CPU.
- *
- * @li Reentrant: no
- * @li IRQ safe: yes
- *
- * @return - none
- */
-#define IX_OSAL_CACHE_FLUSH(addr, size) IX_OSAL_OS_CACHE_FLUSH(addr, size)
-
-
-
-/**
- * @ingroup IxOsal
- *
- * @brief cache line invalidate
- *
- * @param addr - memory address to invalidate in cache
- * @param size - number of bytes to invalidate (rounded up to a cache line)
- *
- * Invalidates the cached value of the memory zone pointed by "addr",
- * rounding up to a cache line. Use before reading the zone from the main
- * CPU, if the zone has been updated by a processing unit which is not cache
- * coherent with the main CPU.
- *
- * @li Reentrant: no
- * @li IRQ safe: yes
- *
- * @return - none
- */
-#define IX_OSAL_CACHE_INVALIDATE(addr, size) IX_OSAL_OS_CACHE_INVALIDATE(addr, size)
-
-
-/* ============================= Threads =================================
- *
- */
-
-/**
- * @ingroup IxOsal
- *
- * @brief Creates a new thread
- *
- * @param thread - handle of the thread to be created
- * @param threadAttr - pointer to a thread attribute object
- * @param startRoutine - thread entry point
- * @param arg - argument given to the thread
- *
- * Creates a thread given a thread handle and a thread attribute object. The
- * same thread attribute object can be used to create separate threads. "NULL"
- * can be specified as the attribute, in which case the default values will
- * be used. The thread needs to be explicitly started using ixOsalThreadStart().
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalThreadCreate (IxOsalThread * thread,
- IxOsalThreadAttr * threadAttr,
- IxOsalVoidFnVoidPtr startRoutine,
- void *arg);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Starts a newly created thread
- *
- * @param thread - handle of the thread to be started
- *
- * Starts a thread given its thread handle. This function is to be called
- * only once, following the thread initialization.
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalThreadStart (IxOsalThread * thread);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Kills an existing thread
- *
- * @param thread - handle of the thread to be killed
- *
- * Kills a thread given its thread handle.
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @note It is not possible to kill threads in Linux kernel mode. This
- * function will only send a SIGTERM signal, and it is the responsibility
- * of the thread to check for the presence of this signal with
- * signal_pending().
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalThreadKill (IxOsalThread * thread);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Exits a running thread
- *
- * Terminates the calling thread
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - This function never returns
- */
-PUBLIC void ixOsalThreadExit (void);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Sets the priority of an existing thread
- *
- * @param thread - handle of the thread
- * @param priority - new priority, between 0 and 255 (0 being the highest)
- *
- * Sets the thread priority
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalThreadPrioritySet (IxOsalThread * thread,
- UINT32 priority);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Suspends thread execution
- *
- * @param thread - handle of the thread
- *
- * Suspends the thread execution
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalThreadSuspend (IxOsalThread * thread);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Resumes thread execution
- *
- * @param thread - handle of the thread
- *
- * Resumes the thread execution
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalThreadResume (IxOsalThread * thread);
-
-
-/* ======================= Message Queues (IPC) ==========================
- *
- */
-
-/**
- * @ingroup IxOsal
- *
- * @brief Creates a message queue
- *
- * @param queue - queue handle
- * @param msgCount - maximum number of messages to hold in the queue
- * @param msgLen - maximum length of each message, in bytes
- *
- * Creates a message queue of msgCount messages, each containing msgLen bytes
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMessageQueueCreate (IxOsalMessageQueue * queue,
- UINT32 msgCount, UINT32 msgLen);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Deletes a message queue
- *
- * @param queue - queue handle
- *
- * Deletes a message queue
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMessageQueueDelete (IxOsalMessageQueue * queue);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Sends a message to a message queue
- *
- * @param queue - queue handle
- * @param message - message to send
- *
- * Sends a message to the message queue. The message will be copied (at the
- * configured size of the message) into the queue.
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMessageQueueSend (IxOsalMessageQueue * queue,
- UINT8 * message);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Receives a message from a message queue
- *
- * @param queue - queue handle
- * @param message - pointer to where the message should be copied to
- *
- * Retrieves the first message from the message queue
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMessageQueueReceive (IxOsalMessageQueue * queue,
- UINT8 * message);
-
-
-/* ======================= Thread Synchronisation ========================
- *
- */
-
-/**
- * @ingroup IxOsal
- *
- * @brief initializes a mutex
- *
- * @param mutex - mutex handle
- *
- * Initializes a mutex object
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMutexInit (IxOsalMutex * mutex);
-
-/**
- * @ingroup IxOsal
- *
- * @brief locks a mutex
- *
- * @param mutex - mutex handle
- * @param timeout - timeout in ms; IX_OSAL_WAIT_FOREVER (-1) to wait forever
- * or IX_OSAL_WAIT_NONE to return immediately
- *
- * Locks a mutex object
- *
- * @li Reentrant: yes
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMutexLock (IxOsalMutex * mutex, INT32 timeout);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Unlocks a mutex
- *
- * @param mutex - mutex handle
- *
- * Unlocks a mutex object
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMutexUnlock (IxOsalMutex * mutex);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Non-blocking attempt to lock a mutex
- *
- * @param mutex - mutex handle
- *
- * Attempts to lock a mutex object, returning immediately with IX_SUCCESS if
- * the lock was successful or IX_FAIL if the lock failed
- *
- * @li Reentrant: yes
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMutexTryLock (IxOsalMutex * mutex);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Destroys a mutex object
- *
- * @param mutex - mutex handle
- * @param
- *
- * Destroys a mutex object; the caller should ensure that no thread is
- * blocked on this mutex
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalMutexDestroy (IxOsalMutex * mutex);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Initializes a fast mutex
- *
- * @param mutex - fast mutex handle
- *
- * Initializes a fast mutex object
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalFastMutexInit (IxOsalFastMutex * mutex);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Non-blocking attempt to lock a fast mutex
- *
- * @param mutex - fast mutex handle
- *
- * Attempts to lock a fast mutex object, returning immediately with
- * IX_SUCCESS if the lock was successful or IX_FAIL if the lock failed
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalFastMutexTryLock (IxOsalFastMutex * mutex);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Unlocks a fast mutex
- *
- * @param mutex - fast mutex handle
- *
- * Unlocks a fast mutex object
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalFastMutexUnlock (IxOsalFastMutex * mutex);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Destroys a fast mutex object
- *
- * @param mutex - fast mutex handle
- *
- * Destroys a fast mutex object
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalFastMutexDestroy (IxOsalFastMutex * mutex);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Initializes a semaphore
- *
- * @param semaphore - semaphore handle
- * @param value - initial semaphore value
- *
- * Initializes a semaphore object
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalSemaphoreInit (IxOsalSemaphore * semaphore,
- UINT32 value);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Posts to (increments) a semaphore
- *
- * @param semaphore - semaphore handle
- *
- * Increments a semaphore object
- *
- * @li Reentrant: no
- * @li IRQ safe: yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalSemaphorePost (IxOsalSemaphore * semaphore);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Waits on (decrements) a semaphore
- *
- * @param semaphore - semaphore handle
- * @param timeout - timeout, in ms; IX_OSAL_WAIT_FOREVER (-1) if the thread
- * is to block indefinitely or IX_OSAL_WAIT_NONE (0) if the thread is to
- * return immediately even if the call fails
- *
- * Decrements a semaphore, blocking if the semaphore is
- * unavailable (value is 0).
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalSemaphoreWait (IxOsalSemaphore * semaphore,
- INT32 timeout);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Non-blocking wait on semaphore
- *
- * @param semaphore - semaphore handle
- *
- * Decrements a semaphore, not blocking the calling thread if the semaphore
- * is unavailable
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalSemaphoreTryWait (IxOsalSemaphore * semaphore);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Gets semaphore value
- *
- * @param semaphore - semaphore handle
- * @param value - location to store the semaphore value
- *
- * Retrieves the current value of a semaphore object
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalSemaphoreGetValue (IxOsalSemaphore * semaphore,
- UINT32 * value);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Destroys a semaphore object
- *
- * @param semaphore - semaphore handle
- *
- * Destroys a semaphore object; the caller should ensure that no thread is
- * blocked on this semaphore
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalSemaphoreDestroy (IxOsalSemaphore * semaphore);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Yields execution of current thread
- *
- * Yields the execution of the current thread
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - none
- */
-PUBLIC void ixOsalYield (void);
-
-
-/* ========================== Time functions ===========================
- *
- */
-
-/**
- * @ingroup IxOsal
- *
- * @brief Yielding sleep for a number of milliseconds
- *
- * @param milliseconds - number of milliseconds to sleep
- *
- * The calling thread will sleep for the specified number of milliseconds.
- * This sleep is yielding, hence other tasks will be scheduled by the
- * operating system during the sleep period. Calling this function with an
- * argument of 0 will place the thread at the end of the current scheduling
- * loop.
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - none
- */
-PUBLIC void ixOsalSleep (UINT32 milliseconds);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Busy sleep for a number of microseconds
- *
- * @param microseconds - number of microseconds to sleep
- *
- * Sleeps for the specified number of microseconds, without explicitly
- * yielding thread execution to the OS scheduler
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - none
- */
-PUBLIC void ixOsalBusySleep (UINT32 microseconds);
-
-/**
- * @ingroup IxOsal
- *
- * @brief XXX
- *
- * Retrieves the current timestamp
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - The current timestamp
- *
- * @note The implementation of this function is platform-specific. Not
- * all the platforms provide a high-resolution timestamp counter.
- */
-PUBLIC UINT32 ixOsalTimestampGet (void);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Resolution of the timestamp counter
- *
- * Retrieves the resolution (frequency) of the timestamp counter.
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - The resolution of the timestamp counter
- *
- * @note The implementation of this function is platform-specific. Not all
- * the platforms provide a high-resolution timestamp counter.
- */
-PUBLIC UINT32 ixOsalTimestampResolutionGet (void);
-
-/**
- * @ingroup IxOsal
- *
- * @brief System clock rate, in ticks
- *
- * Retrieves the resolution (number of ticks per second) of the system clock
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - The system clock rate
- *
- * @note The implementation of this function is platform and OS-specific.
- * The system clock rate is not always available - e.g. Linux does not
- * provide this information in user mode
- */
-PUBLIC UINT32 ixOsalSysClockRateGet (void);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Current system time
- *
- * @param tv - pointer to an IxOsalTimeval structure to store the current
- * time in
- *
- * Retrieves the current system time (real-time)
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - none
- *
- * @note The implementation of this function is platform-specific. Not all
- * platforms have a real-time clock.
- */
-PUBLIC void ixOsalTimeGet (IxOsalTimeval * tv);
-
-
-
-/* Internal function to convert timer val to ticks.
- * NOTE - This should not be called by the user.
- * Use the macro IX_OSAL_TIMEVAL_TO_TICKS
- * OS-independent, implemented in framework.
- */
-PUBLIC UINT32 ixOsalTimevalToTicks (IxOsalTimeval tv);
-
-
-/**
- * @ingroup IxOsal
- *
- * @brief Converts ixOsalTimeVal into ticks
- *
- * @param tv - an IxOsalTimeval structure
- *
- * Converts an IxOsalTimeval structure into OS ticks
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - Corresponding number of ticks
- *
- * Note: This function is OS-independent. Implemented by core.
- */
-#define IX_OSAL_TIMEVAL_TO_TICKS(tv) ixOsalTimevalToTicks(tv)
-
-
-
-/* Internal function to convert ticks to timer val
- * NOTE - This should not be called by the user.
- * Use the macro IX_OSAL_TICKS_TO_TIMEVAL
- */
-
-PUBLIC void ixOsalTicksToTimeval (UINT32 ticks, IxOsalTimeval * pTv);
-
-
-/**
- * @ingroup IxOsal
- *
- * @brief Converts ticks into ixOsalTimeVal
- *
- * @param ticks - number of ticks
- * @param pTv - pointer to the destination structure
- *
- * Converts the specified number of ticks into an IxOsalTimeval structure
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - Corresponding IxOsalTimeval structure
- * Note: This function is OS-independent. Implemented by core.
- */
-#define IX_OSAL_TICKS_TO_TIMEVAL(ticks, pTv) \
- ixOsalTicksToTimeval(ticks, pTv)
-
-
-
-
-/**
- * @ingroup IxOsal
- *
- * @brief Converts ixOsalTimeVal to milliseconds
- *
- * @param tv - IxOsalTimeval structure to convert
- *
- * Converts an IxOsalTimeval structure into milliseconds
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - Corresponding number of milliseconds
- * Note: This function is OS-independent. Implemented by core.
- */
-#define IX_OSAL_TIMEVAL_TO_MS(tv) ((tv.secs * 1000) + (tv.nsecs / 1000000))
-
-
-/**
- * @ingroup IxOsal
- *
- * @brief Converts milliseconds to IxOsalTimeval
- *
- * @param milliseconds - number of milliseconds to convert
- * @param pTv - pointer to the destination structure
- *
- * Converts a millisecond value into an IxOsalTimeval structure
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - Corresponding IxOsalTimeval structure
- * Note: This function is OS-independent. Implemented by core.
- */
-#define IX_OSAL_MS_TO_TIMEVAL(milliseconds, pTv) \
- ((IxOsalTimeval *) pTv)->secs = milliseconds / 1000; \
- ((IxOsalTimeval *) pTv)->nsecs = (milliseconds % 1000) * 1000000
-
-
-/**
- * @ingroup IxOsal
- *
- * @brief "equal" comparison for IxOsalTimeval
- *
- * @param tvA, tvB - IxOsalTimeval structures to compare
- *
- * Compares two IxOsalTimeval structures for equality
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - TRUE if the structures are equal
- * - FALSE otherwise
- * Note: This function is OS-independant
- */
-#define IX_OSAL_TIME_EQ(tvA, tvB) \
- ((tvA).secs == (tvB).secs && (tvA).nsecs == (tvB).nsecs)
-
-
-/**
- * @ingroup IxOsal
- *
- * @brief "less than" comparison for IxOsalTimeval
- *
- * @param tvA, tvB - IxOsalTimeval structures to compare
- *
- * Compares two IxOsalTimeval structures to determine if the first one is
- * less than the second one
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - TRUE if tvA < tvB
- * - FALSE otherwise
- * Note: This function is OS-independent. Implemented by core.
- */
-#define IX_OSAL_TIME_LT(tvA,tvB) \
- ((tvA).secs < (tvB).secs || \
- ((tvA).secs == (tvB).secs && (tvA).nsecs < (tvB).nsecs))
-
-
-/**
- * @ingroup IxOsal
- *
- * @brief "greater than" comparison for IxOsalTimeval
- *
- * @param tvA, tvB - IxOsalTimeval structures to compare
- *
- * Compares two IxOsalTimeval structures to determine if the first one is
- * greater than the second one
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - TRUE if tvA > tvB
- * - FALSE otherwise
- * Note: This function is OS-independent.
- */
-#define IX_OSAL_TIME_GT(tvA, tvB) \
- ((tvA).secs > (tvB).secs || \
- ((tvA).secs == (tvB).secs && (tvA).nsecs > (tvB).nsecs))
-
-
-/**
- * @ingroup IxOsal
- *
- * @brief "add" operator for IxOsalTimeval
- *
- * @param tvA, tvB - IxOsalTimeval structures to add
- *
- * Adds the second IxOsalTimevalStruct to the first one (equivalent to
- * tvA += tvB)
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - none
- * Note: This function is OS-independent.
- */
-#define IX_OSAL_TIME_ADD(tvA, tvB) \
- (tvA).secs += (tvB).secs; \
- (tvA).nsecs += (tvB).nsecs; \
- if ((tvA).nsecs >= IX_OSAL_BILLION) \
- { \
- (tvA).secs++; \
- (tvA).nsecs -= IX_OSAL_BILLION; }
-
-
-/**
- * @ingroup IxOsal
- *
- * @brief "subtract" operator for IxOsalTimeval
- *
- * @param tvA, tvB - IxOsalTimeval structures to subtract
- *
- * Subtracts the second IxOsalTimevalStruct from the first one (equivalent
- * to tvA -= tvB)
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - none
- * Note: This function is OS-independent. Implemented by core.
- */
-#define IX_OSAL_TIME_SUB(tvA, tvB) \
- if ((tvA).nsecs >= (tvB).nsecs) \
- { \
- (tvA).secs -= (tvB).secs; \
- (tvA).nsecs -= (tvB).nsecs; \
- } \
- else \
- { \
- (tvA).secs -= ((tvB).secs + 1); \
- (tvA).nsecs += IX_OSAL_BILLION - (tvB).nsecs; \
- }
-
-
-/* ============================= Logging ==============================
- *
- */
-
-/**
- * @ingroup IxOsal
- *
- * @brief Interrupt-safe logging function
- *
- * @param level - identifier prefix for the message
- * @param device - output device
- * @param format - message format, in a printf format
- * @param ... - up to 6 arguments to be printed
- *
- * IRQ-safe logging function, similar to printf. Accepts up to 6 arguments
- * to print (excluding the level, device and the format). This function will
- * actually display the message only if the level is lower than the current
- * verbosity level or if the IX_OSAL_LOG_USER level is used. An output device
- * must be specified (see IxOsalTypes.h).
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - Beside the exceptions documented in the note below, the returned
- * value is the number of printed characters, or -1 if the parameters are
- * incorrect (NULL format, unknown output device)
- *
- * @note The exceptions to the return value are:
- * VxWorks: The return value is 32 if the specified level is 1 and 64
- * if the specified level is greater than 1 and less or equal than 9.
- * WinCE: If compiled for EBOOT then the return value is always 0.
- *
- * @note The given print format should take into account the specified
- * output device. IX_OSAL_STDOUT supports all the usual print formats,
- * however a custom hex display specified by IX_OSAL_HEX would support
- * only a fixed number of hexadecimal digits.
- */
-PUBLIC INT32 ixOsalLog (IxOsalLogLevel level,
- IxOsalLogDevice device,
- char *format,
- int arg1,
- int arg2, int arg3, int arg4, int arg5, int arg6);
-
-/**
- * @ingroup IxOsal
- *
- * @brief sets the current logging verbosity level
- *
- * @param level - new log verbosity level
- *
- * Sets the log verbosity level. The default value is IX_OSAL_LOG_ERROR.
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * @return - Old log verbosity level
- */
-PUBLIC UINT32 ixOsalLogLevelSet (UINT32 level);
-
-
-/* ============================= Logging ==============================
- *
- */
-
-/**
- * @ingroup IxOsal
- *
- * @brief Schedules a repeating timer
- *
- * @param timer - handle of the timer object
- * @param period - timer trigger period, in milliseconds
- * @param priority - timer priority (0 being the highest)
- * @param callback - user callback to invoke when the timer triggers
- * @param param - custom parameter passed to the callback
- *
- * Schedules a timer to be called every period milliseconds. The timer
- * will invoke the specified callback function possibly in interrupt
- * context, passing the given parameter. If several timers trigger at the
- * same time contention issues are dealt according to the specified timer
- * priorities.
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalRepeatingTimerSchedule (IxOsalTimer * timer,
- UINT32 period,
- UINT32 priority,
- IxOsalVoidFnVoidPtr callback,
- void *param);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Schedules a single-shot timer
- *
- * @param timer - handle of the timer object
- * @param period - timer trigger period, in milliseconds
- * @param priority - timer priority (0 being the highest)
- * @param callback - user callback to invoke when the timer triggers
- * @param param - custom parameter passed to the callback
- *
- * Schedules a timer to be called after period milliseconds. The timer
- * will cease to function past its first trigger. The timer will invoke
- * the specified callback function, possibly in interrupt context, passing
- * the given parameter. If several timers trigger at the same time contention
- * issues are dealt according to the specified timer priorities.
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS
-ixOsalSingleShotTimerSchedule (IxOsalTimer * timer,
- UINT32 period,
- UINT32 priority,
- IxOsalVoidFnVoidPtr callback, void *param);
-
-/**
- * @ingroup IxOsal
- *
- * @brief Cancels a running timer
- *
- * @param timer - handle of the timer object
- *
- * Cancels a single-shot or repeating timer.
- *
- * @li Reentrant: no
- * @li IRQ safe: yes
- *
- * @return - IX_SUCCESS/IX_FAIL
- */
-PUBLIC IX_STATUS ixOsalTimerCancel (IxOsalTimer * timer);
-
-/**
- * @ingroup IxOsal
- *
- * @brief displays all the running timers
- *
- * Displays a list with all the running timers and their parameters (handle,
- * period, type, priority, callback and user parameter)
- *
- * @li Reentrant: no
- * @li IRQ safe: no
- *
- * @return - none
- */
-PUBLIC void ixOsalTimersShow (void);
-
-
-/* ============================= Version ==============================
- *
- */
-
-/**
- * @ingroup IxOsal
- *
- * @brief provides the name of the Operating System running
- *
- * @param osName - Pointer to a NULL-terminated string of characters
- * that holds the name of the OS running.
- * This is both an input and an ouput parameter
- * @param maxSize - Input parameter that defines the maximum number of
- * bytes that can be stored in osName
- *
- * Returns a string of characters that describe the Operating System name
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * return - IX_SUCCESS for successful retrieval
- * - IX_FAIL if (osType == NULL | maxSize =< 0)
- */
-PUBLIC IX_STATUS ixOsalOsNameGet (INT8* osName, INT32 maxSize);
-
-/**
- * @ingroup IxOsal
- *
- * @brief provides the version of the Operating System running
- *
- * @param osVersion - Pointer to a NULL terminated string of characters
- * that holds the version of the OS running.
- * This is both an input and an ouput parameter
- * @param maxSize - Input parameter that defines the maximum number of
- * bytes that can be stored in osVersion
- *
- * Returns a string of characters that describe the Operating System's version
- *
- * @li Reentrant: yes
- * @li IRQ safe: yes
- *
- * return - IX_SUCCESS for successful retrieval
- * - IX_FAIL if (osVersion == NULL | maxSize =< 0)
- */
-PUBLIC IX_STATUS ixOsalOsVersionGet(INT8* osVersion, INT32 maxSize);
-
-
-
-/**
- * @} IxOsal
- */
-
-#endif /* IxOsal_H */
+++ /dev/null
-/*
- * @file IxOsalAssert.h
- * @author Intel Corporation
- * @date 25-08-2004
- *
- * @brief description goes here
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IX_OSAL_ASSERT_H
-#define IX_OSAL_ASSERT_H
-
-/*
- * Put the system defined include files required
- * @par
- * <TAGGED>
- */
-
-#include "IxOsalOsAssert.h"
-
-/**
- * @brief Assert macro, assert the condition is true. This
- * will not be compiled out.
- * N.B. will result in a system crash if it is false.
- */
-#define IX_OSAL_ASSERT(c) IX_OSAL_OS_ASSERT(c)
-
-
-/**
- * @brief Ensure macro, ensure the condition is true.
- * This will be conditionally compiled out and
- * may be used for test purposes.
- */
-#ifdef IX_OSAL_ENSURE_ON
-#define IX_OSAL_ENSURE(c, str) do { \
-if (!(c)) ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, str, \
-0, 0, 0, 0, 0, 0); } while (0)
-
-#else
-#define IX_OSAL_ENSURE(c, str)
-#endif
-
-
-#endif /* IX_OSAL_ASSERT_H */
+++ /dev/null
-/**
- * This file is intended to provide backward
- * compatibility for main osService/OSSL
- * APIs.
- *
- * It shall be phased out gradually and users
- * are strongly recommended to use IX_OSAL API.
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IX_OSAL_BACKWARD_H
-#define IX_OSAL_BACKWARD_H
-
-#include "IxOsal.h"
-
-#include "IxOsalBackwardCacheMMU.h"
-
-#include "IxOsalBackwardOsServices.h"
-
-#include "IxOsalBackwardMemMap.h"
-
-#include "IxOsalBackwardBufferMgt.h"
-
-#include "IxOsalBackwardOssl.h"
-
-#include "IxOsalBackwardAssert.h"
-
-#endif /* IX_OSAL_BACKWARD_H */
+++ /dev/null
-/**
- * This file is intended to provide backward
- * compatibility for main osService/OSSL
- * APIs.
- *
- * It shall be phased out gradually and users
- * are strongly recommended to use IX_OSAL API.
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IX_OSAL_BACKWARD_ASSERT_H
-#define IX_OSAL_BACKWARD_ASSERT_H
-
-#define IX_ENSURE(c, str) IX_OSAL_ENSURE(c, str)
-#define IX_ASSERT(c) IX_OSAL_ASSERT(c)
-
-#endif /* IX_OSAL_BACKWARD_ASSERT_H */
+++ /dev/null
-/**
- * This file is intended to provide backward
- * compatibility for main osService/OSSL
- * APIs.
- *
- * It shall be phased out gradually and users
- * are strongly recommended to use IX_OSAL API.
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IX_OSAL_BACKWARD_BUFFER_MGT_H
-#define IX_OSAL_BACKWARD_BUFFER_MGT_H
-
-typedef IX_OSAL_MBUF IX_MBUF;
-
-typedef IX_OSAL_MBUF_POOL IX_MBUF_POOL;
-
-
-#define IX_MBUF_NEXT_BUFFER_IN_PKT_PTR(m_blk_ptr) \
- IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(m_blk_ptr)
-
-
-#define IX_MBUF_NEXT_PKT_IN_CHAIN_PTR(m_blk_ptr) \
- IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m_blk_ptr)
-
-
-#define IX_MBUF_MDATA(m_blk_ptr) \
- IX_OSAL_MBUF_MDATA(m_blk_ptr)
-
-
-#define IX_MBUF_MLEN(m_blk_ptr) \
- IX_OSAL_MBUF_MLEN(m_blk_ptr)
-
-
-#define IX_MBUF_TYPE(m_blk_ptr) \
- IX_OSAL_MBUF_MTYPE(m_blk_ptr)
-
-/* Same as IX_MBUF_TYPE */
-#define IX_MBUF_MTYPE(m_blk_ptr) \
- IX_OSAL_MBUF_MTYPE(m_blk_ptr)
-
-#define IX_MBUF_FLAGS(m_blk_ptr) \
- IX_OSAL_MBUF_FLAGS(m_blk_ptr)
-
-
-#define IX_MBUF_NET_POOL(m_blk_ptr) \
- IX_OSAL_MBUF_NET_POOL(m_blk_ptr)
-
-
-#define IX_MBUF_PKT_LEN(m_blk_ptr) \
- IX_OSAL_MBUF_PKT_LEN(m_blk_ptr)
-
-
-#define IX_MBUF_PRIV(m_blk_ptr) \
- IX_OSAL_MBUF_PRIV(m_blk_ptr)
-
-
-#define IX_MBUF_ALLOCATED_BUFF_LEN(m_blk_ptr) \
- IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(m_blk_ptr)
-
-
-#define IX_MBUF_ALLOCATED_BUFF_DATA(m_blk_ptr) \
- IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(m_blk_ptr)
-
-
-#define IX_MBUF_POOL_SIZE_ALIGN(size) \
- IX_OSAL_MBUF_POOL_SIZE_ALIGN(size)
-
-
-#define IX_MBUF_POOL_MBUF_AREA_SIZE_ALIGNED(count) \
- IX_OSAL_MBUF_POOL_MBUF_AREA_SIZE_ALIGNED(count)
-
-
-#define IX_MBUF_POOL_DATA_AREA_SIZE_ALIGNED(count, size) \
- IX_OSAL_MBUF_POOL_DATA_AREA_SIZE_ALIGNED(count, size)
-
-
-#define IX_MBUF_POOL_MBUF_AREA_ALLOC(count, memAreaSize) \
- IX_OSAL_MBUF_POOL_MBUF_AREA_ALLOC(count, memAreaSize)
-
-
-#define IX_MBUF_POOL_DATA_AREA_ALLOC(count, size, memAreaSize) \
- IX_OSAL_MBUF_POOL_DATA_AREA_ALLOC(count, size, memAreaSize)
-
-IX_STATUS
-ixOsalOsIxp400BackwardPoolInit (IX_OSAL_MBUF_POOL ** poolPtrPtr,
- UINT32 count, UINT32 size, const char *name);
-
-
-/* This one needs extra steps*/
-#define IX_MBUF_POOL_INIT(poolPtr, count, size, name) \
- ixOsalOsIxp400BackwardPoolInit( poolPtr, count, size, name)
-
-
-#define IX_MBUF_POOL_INIT_NO_ALLOC(poolPtrPtr, bufPtr, dataPtr, count, size, name) \
- (*poolPtrPtr = IX_OSAL_MBUF_NO_ALLOC_POOL_INIT(bufPtr, dataPtr, count, size, name))
-
-
-IX_STATUS
-ixOsalOsIxp400BackwardMbufPoolGet (IX_OSAL_MBUF_POOL * poolPtr,
- IX_OSAL_MBUF ** newBufPtrPtr);
-
-#define IX_MBUF_POOL_GET(poolPtr, bufPtrPtr) \
- ixOsalOsIxp400BackwardMbufPoolGet(poolPtr, bufPtrPtr)
-
-
-#define IX_MBUF_POOL_PUT(bufPtr) \
- IX_OSAL_MBUF_POOL_PUT(bufPtr)
-
-
-#define IX_MBUF_POOL_PUT_CHAIN(bufPtr) \
- IX_OSAL_MBUF_POOL_PUT_CHAIN(bufPtr)
-
-
-#define IX_MBUF_POOL_SHOW(poolPtr) \
- IX_OSAL_MBUF_POOL_SHOW(poolPtr)
-
-
-#define IX_MBUF_POOL_MDATA_RESET(bufPtr) \
- IX_OSAL_MBUF_POOL_MDATA_RESET(bufPtr)
-
-#endif /* IX_OSAL_BACKWARD_BUFFER_MGT_H */
+++ /dev/null
-/**
- * This file is intended to provide backward
- * compatibility for main osService/OSSL
- * APIs.
- *
- * It shall be phased out gradually and users
- * are strongly recommended to use IX_OSAL API.
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IX_OSAL_BACKWARD_CACHE_MMU_H
-#define IX_OSAL_BACKWARD_CACHE_MMU_H
-
-#ifdef IX_OSAL_CACHED
-#define IX_ACC_CACHE_ENABLED
-#endif
-
-#define IX_XSCALE_CACHE_LINE_SIZE IX_OSAL_CACHE_LINE_SIZE
-
-#define IX_ACC_DRV_DMA_MALLOC(size) IX_OSAL_CACHE_DMA_MALLOC(size)
-
-#define IX_ACC_DRV_DMA_FREE(ptr,size) IX_OSAL_CACHE_DMA_FREE(ptr)
-
-#define IX_MMU_VIRTUAL_TO_PHYSICAL_TRANSLATION(addr) IX_OSAL_MMU_VIRT_TO_PHYS(addr)
-
-#define IX_MMU_PHYSICAL_TO_VIRTUAL_TRANSLATION(addr) IX_OSAL_MMU_PHYS_TO_VIRT(addr)
-
-#define IX_ACC_DATA_CACHE_INVALIDATE(addr,size) IX_OSAL_CACHE_INVALIDATE(addr, size)
-
-#define IX_ACC_DATA_CACHE_FLUSH(addr,size) IX_OSAL_CACHE_FLUSH(addr,size)
-
-#endif /* IX_OSAL_BACKWARD_CACHE_MMU_H */
+++ /dev/null
-/**
- * This file is intended to provide backward
- * compatibility for main osService/OSSL
- * APIs.
- *
- * It shall be phased out gradually and users
- * are strongly recommended to use IX_OSAL API.
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#ifndef IX_OSAL_BACKWARD_MEM_MAP_H
-#define IX_OSAL_BACKWARD_MEM_MAP_H
-
-#include "IxOsal.h"
-
-#define IX_OSSERV_SWAP_LONG(wData) IX_OSAL_SWAP_LONG(wData)
-#define IX_OSSERV_SWAP_SHORT(sData) IX_OSAL_SWAP_SHORT(sData)
-
-#define IX_OSSERV_SWAP_SHORT_ADDRESS(sAddr) IX_OSAL_SWAP_SHORT_ADDRESS(sAddr)
-#define IX_OSSERV_SWAP_BYTE_ADDRESS(bAddr) IX_OSAL_SWAP_BYTE_ADDRESS(bAddr)
-
-#define IX_OSSERV_BE_XSTOBUSL(wData) IX_OSAL_BE_XSTOBUSL(wData)
-#define IX_OSSERV_BE_XSTOBUSS(sData) IX_OSAL_BE_XSTOBUSS(sData)
-#define IX_OSSERV_BE_XSTOBUSB(bData) IX_OSAL_BE_XSTOBUSB(bData)
-#define IX_OSSERV_BE_BUSTOXSL(wData) IX_OSAL_BE_BUSTOXSL(wData)
-#define IX_OSSERV_BE_BUSTOXSS(sData) IX_OSAL_BE_BUSTOXSS(sData)
-#define IX_OSSERV_BE_BUSTOXSB(bData) IX_OSAL_BE_BUSTOXSB(bData)
-
-#define IX_OSSERV_LE_AC_XSTOBUSL(wAddr) IX_OSAL_LE_AC_XSTOBUSL(wAddr)
-#define IX_OSSERV_LE_AC_XSTOBUSS(sAddr) IX_OSAL_LE_AC_XSTOBUSS(sAddr)
-#define IX_OSSERV_LE_AC_XSTOBUSB(bAddr) IX_OSAL_LE_AC_XSTOBUSB(bAddr)
-#define IX_OSSERV_LE_AC_BUSTOXSL(wAddr) IX_OSAL_LE_AC_BUSTOXSL(wAddr)
-#define IX_OSSERV_LE_AC_BUSTOXSS(sAddr) IX_OSAL_LE_AC_BUSTOXSS(sAddr)
-#define IX_OSSERV_LE_AC_BUSTOXSB(bAddr) IX_OSAL_LE_AC_BUSTOXSB(bAddr)
-
-#define IX_OSSERV_LE_DC_XSTOBUSL(wData) IX_OSAL_LE_DC_XSTOBUSL(wData)
-#define IX_OSSERV_LE_DC_XSTOBUSS(sData) IX_OSAL_LE_DC_XSTOBUSS(sData)
-#define IX_OSSERV_LE_DC_XSTOBUSB(bData) IX_OSAL_LE_DC_XSTOBUSB(bData)
-#define IX_OSSERV_LE_DC_BUSTOXSL(wData) IX_OSAL_LE_DC_BUSTOXSL(wData)
-#define IX_OSSERV_LE_DC_BUSTOXSS(sData) IX_OSAL_LE_DC_BUSTOXSS(sData)
-#define IX_OSSERV_LE_DC_BUSTOXSB(bData) IX_OSAL_LE_DC_BUSTOXSB(bData)
-
-#define IX_OSSERV_READ_LONG(wAddr) IX_OSAL_READ_LONG(wAddr)
-#define IX_OSSERV_READ_SHORT(sAddr) IX_OSAL_READ_SHORT(sAddr)
-#define IX_OSSERV_READ_BYTE(bAddr) IX_OSAL_READ_BYTE(bAddr)
-#define IX_OSSERV_WRITE_LONG(wAddr, wData) IX_OSAL_WRITE_LONG(wAddr, wData)
-#define IX_OSSERV_WRITE_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT(sAddr, sData)
-#define IX_OSSERV_WRITE_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE(bAddr, bData)
-
-
-#define IX_OSSERV_READ_NPE_SHARED_LONG(wAddr) IX_OSAL_READ_BE_SHARED_LONG(wAddr)
-#define IX_OSSERV_READ_NPE_SHARED_SHORT(sAddr) IX_OSAL_READ_BE_SHARED_SHORT(sAddr)
-#define IX_OSSERV_WRITE_NPE_SHARED_LONG(wAddr, wData) IX_OSAL_WRITE_BE_SHARED_LONG(wAddr, wData)
-#define IX_OSSERV_WRITE_NPE_SHARED_SHORT(sAddr, sData) IX_OSAL_WRITE_BE_SHARED_SHORT(sAddr, sData)
-
-#define IX_OSSERV_SWAP_NPE_SHARED_LONG(wData) IX_OSAL_SWAP_BE_SHARED_LONG(wData)
-#define IX_OSSERV_SWAP_NPE_SHARED_SHORT(sData) IX_OSAL_SWAP_BE_SHARED_SHORT(sData)
-
-
-/* Map osServ address/size */
-#define IX_OSSERV_QMGR_MAP_SIZE IX_OSAL_IXP400_QMGR_MAP_SIZE
-#define IX_OSSERV_EXP_REG_MAP_SIZE IX_OSAL_IXP400_EXP_REG_MAP_SIZE
-#define IX_OSSERV_UART1_MAP_SIZE IX_OSAL_IXP400_UART1_MAP_SIZE
-#define IX_OSSERV_UART2_MAP_SIZE IX_OSAL_IXP400_UART2_MAP_SIZE
-#define IX_OSSERV_PMU_MAP_SIZE IX_OSAL_IXP400_PMU_MAP_SIZE
-#define IX_OSSERV_OSTS_MAP_SIZE IX_OSAL_IXP400_OSTS_MAP_SIZE
-#define IX_OSSERV_NPEA_MAP_SIZE IX_OSAL_IXP400_NPEA_MAP_SIZE
-#define IX_OSSERV_NPEB_MAP_SIZE IX_OSAL_IXP400_NPEB_MAP_SIZE
-#define IX_OSSERV_NPEC_MAP_SIZE IX_OSAL_IXP400_NPEC_MAP_SIZE
-#define IX_OSSERV_ETHA_MAP_SIZE IX_OSAL_IXP400_ETHA_MAP_SIZE
-#define IX_OSSERV_ETHB_MAP_SIZE IX_OSAL_IXP400_ETHB_MAP_SIZE
-#define IX_OSSERV_USB_MAP_SIZE IX_OSAL_IXP400_USB_MAP_SIZE
-#define IX_OSSERV_GPIO_MAP_SIZE IX_OSAL_IXP400_GPIO_MAP_SIZE
-#define IX_OSSERV_EXP_BUS_MAP_SIZE IX_OSAL_IXP400_EXP_BUS_MAP_SIZE
-#define IX_OSSERV_EXP_BUS_CS0_MAP_SIZE IX_OSAL_IXP400_EXP_BUS_CS0_MAP_SIZE
-#define IX_OSSERV_EXP_BUS_CS1_MAP_SIZE IX_OSAL_IXP400_EXP_BUS_CS1_MAP_SIZE
-#define IX_OSSERV_EXP_BUS_CS4_MAP_SIZE IX_OSAL_IXP400_EXP_BUS_CS4_MAP_SIZE
-
-
-#define IX_OSSERV_GPIO_PHYS_BASE IX_OSAL_IXP400_GPIO_PHYS_BASE
-#define IX_OSSERV_UART1_PHYS_BASE IX_OSAL_IXP400_UART1_PHYS_BASE
-#define IX_OSSERV_UART2_PHYS_BASE IX_OSAL_IXP400_UART2_PHYS_BASE
-#define IX_OSSERV_ETHA_PHYS_BASE IX_OSAL_IXP400_ETHA_PHYS_BASE
-#define IX_OSSERV_ETHB_PHYS_BASE IX_OSAL_IXP400_ETHB_PHYS_BASE
-#define IX_OSSERV_NPEA_PHYS_BASE IX_OSAL_IXP400_NPEA_PHYS_BASE
-#define IX_OSSERV_NPEB_PHYS_BASE IX_OSAL_IXP400_NPEB_PHYS_BASE
-#define IX_OSSERV_NPEC_PHYS_BASE IX_OSAL_IXP400_NPEC_PHYS_BASE
-#define IX_OSSERV_PERIPHERAL_PHYS_BASE IX_OSAL_IXP400_PERIPHERAL_PHYS_BASE
-#define IX_OSSERV_QMGR_PHYS_BASE IX_OSAL_IXP400_QMGR_PHYS_BASE
-#define IX_OSSERV_OSTS_PHYS_BASE IX_OSAL_IXP400_OSTS_PHYS_BASE
-#define IX_OSSERV_USB_PHYS_BASE IX_OSAL_IXP400_USB_PHYS_BASE
-#define IX_OSSERV_EXP_BUS_PHYS_BASE IX_OSAL_IXP400_EXP_BUS_PHYS_BASE
-#define IX_OSSERV_EXP_BUS_BOOT_PHYS_BASE IX_OSAL_IXP400_EXP_BUS_BOOT_PHYS_BASE
-#define IX_OSSERV_EXP_BUS_CS0_PHYS_BASE IX_OSAL_IXP400_EXP_BUS_CS0_PHYS_BASE
-#define IX_OSSERV_EXP_BUS_CS1_PHYS_BASE IX_OSAL_IXP400_EXP_BUS_CS1_PHYS_BASE
-#define IX_OSSERV_EXP_BUS_CS4_PHYS_BASE IX_OSAL_IXP400_EXP_BUS_CS4_PHYS_BASE
-#define IX_OSSERV_EXP_BUS_REGS_PHYS_BASE IX_OSAL_IXP400_EXP_BUS_REGS_PHYS_BASE
-
-#define IX_OSSERV_MEM_MAP(physAddr, size) IX_OSAL_MEM_MAP(physAddr, size)
-
-#define IX_OSSERV_MEM_UNMAP(virtAddr) IX_OSAL_MEM_UNMAP(virtAddr)
-
-#endif /* IX_OSAL_BACKWARD_MEM_MAP_H */
+++ /dev/null
-/**
- * This file is intended to provide backward
- * compatibility for main osService/OSSL
- * APIs.
- *
- * It shall be phased out gradually and users
- * are strongly recommended to use IX_OSAL API.
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IX_OSAL_BACKWARD_OSSERVICES_H
-#define IX_OSAL_BACKWARD_OSSERVICES_H
-
-#ifndef __vxworks
-typedef UINT32 IX_IRQ_STATUS;
-#else
-typedef int IX_IRQ_STATUS;
-#endif
-
-typedef IxOsalMutex IxMutex;
-
-typedef IxOsalFastMutex IxFastMutex;
-
-typedef IxOsalVoidFnVoidPtr IxVoidFnVoidPtr;
-
-typedef IxOsalVoidFnPtr IxVoidFnPtr;
-
-
-#define LOG_NONE IX_OSAL_LOG_LVL_NONE
-#define LOG_USER IX_OSAL_LOG_LVL_USER
-#define LOG_FATAL IX_OSAL_LOG_LVL_FATAL
-#define LOG_ERROR IX_OSAL_LOG_LVL_ERROR
-#define LOG_WARNING IX_OSAL_LOG_LVL_WARNING
-#define LOG_MESSAGE IX_OSAL_LOG_LVL_MESSAGE
-#define LOG_DEBUG1 IX_OSAL_LOG_LVL_DEBUG1
-#define LOG_DEBUG2 IX_OSAL_LOG_LVL_DEBUG2
-#define LOG_DEBUG3 IX_OSAL_LOG_LVL_DEBUG3
-#ifndef __vxworks
-#define LOG_ALL IX_OSAL_LOG_LVL_ALL
-#endif
-
-PUBLIC IX_STATUS
-ixOsServIntBind (int level, void (*routine) (void *), void *parameter);
-
-PUBLIC IX_STATUS ixOsServIntUnbind (int level);
-
-
-PUBLIC int ixOsServIntLock (void);
-
-PUBLIC void ixOsServIntUnlock (int lockKey);
-
-
-PUBLIC int ixOsServIntLevelSet (int level);
-
-PUBLIC IX_STATUS ixOsServMutexInit (IxMutex * mutex);
-
-PUBLIC IX_STATUS ixOsServMutexLock (IxMutex * mutex);
-
-PUBLIC IX_STATUS ixOsServMutexUnlock (IxMutex * mutex);
-
-PUBLIC IX_STATUS ixOsServMutexDestroy (IxMutex * mutex);
-
-PUBLIC IX_STATUS ixOsServFastMutexInit (IxFastMutex * mutex);
-
-PUBLIC IX_STATUS ixOsServFastMutexTryLock (IxFastMutex * mutex);
-
-PUBLIC IX_STATUS ixOsServFastMutexUnlock (IxFastMutex * mutex);
-
-PUBLIC int
-ixOsServLog (int level, char *format, int arg1, int arg2, int arg3, int arg4,
- int arg5, int arg6);
-
-
-PUBLIC int ixOsServLogLevelSet (int level);
-
-PUBLIC void ixOsServSleep (int microseconds);
-
-PUBLIC void ixOsServTaskSleep (int milliseconds);
-
-PUBLIC unsigned int ixOsServTimestampGet (void);
-
-
-PUBLIC void ixOsServUnload (void);
-
-PUBLIC void ixOsServYield (void);
-
-#endif
-/* IX_OSAL_BACKWARD_OSSERVICES_H */
+++ /dev/null
-/**
- * This file is intended to provide backward
- * compatibility for main osService/OSSL
- * APIs.
- *
- * It shall be phased out gradually and users
- * are strongly recommended to use IX_OSAL API.
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IX_OSAL_BACKWARD_OSSL_H
-#define IX_OSAL_BACKWARD_OSSL_H
-
-
-typedef IxOsalThread ix_ossl_thread_t;
-
-typedef IxOsalSemaphore ix_ossl_sem_t;
-
-typedef IxOsalMutex ix_ossl_mutex_t;
-
-typedef IxOsalTimeval ix_ossl_time_t;
-
-
-/* Map sub-fields for ix_ossl_time_t */
-#define tv_sec secs
-#define tv_nec nsecs
-
-
-typedef IX_STATUS ix_error;
-
-typedef UINT32 ix_ossl_thread_priority;
-
-typedef UINT32 ix_uint32;
-
-
-#define IX_OSSL_ERROR_SUCCESS IX_SUCCESS
-
-#define IX_ERROR_SUCCESS IX_SUCCESS
-
-
-typedef enum
-{
- IX_OSSL_SEM_UNAVAILABLE = 0,
- IX_OSSL_SEM_AVAILABLE
-} ix_ossl_sem_state;
-
-
-typedef enum
-{
- IX_OSSL_MUTEX_UNLOCK = 0,
- IX_OSSL_MUTEX_LOCK
-} ix_ossl_mutex_state;
-
-
-typedef IxOsalVoidFnVoidPtr ix_ossl_thread_entry_point_t;
-
-
-#define IX_OSSL_THREAD_PRI_HIGH 90
-#define IX_OSSL_THREAD_PRI_MEDIUM 160
-#define IX_OSSL_THREAD_PRI_LOW 240
-
-
-#define IX_OSSL_WAIT_FOREVER IX_OSAL_WAIT_FOREVER
-
-#define IX_OSSL_WAIT_NONE IX_OSAL_WAIT_NONE
-
-#define BILLION IX_OSAL_BILLION
-
-#define IX_OSSL_TIME_EQ(a,b) IX_OSAL_TIME_EQ(a,b)
-
-#define IX_OSSL_TIME_GT(a,b) IX_OSAL_TIME_GT(a,b)
-
-#define IX_OSSL_TIME_LT(a,b) IX_OSAL_TIME_LT(a,b)
-
-#define IX_OSSL_TIME_ADD(a,b) IX_OSAL_TIME_ADD(a,b)
-
-#define IX_OSSL_TIME_SUB(a,b) IX_OSAL_TIME_SUB(a,b)
-
-
-/* a is tick, b is timeval */
-#define IX_OSSL_TIME_CONVERT_TO_TICK(a,b) \
- (a) = IX_OSAL_TIMEVAL_TO_TICKS(b)
-
-
-
-
-PUBLIC IX_STATUS
-ixOsalOsIxp400BackwardOsslThreadCreate (IxOsalVoidFnVoidPtr entryPoint,
- void *arg, IxOsalThread * ptrThread);
-
-#define ix_ossl_thread_create(entryPoint, arg, ptrTid) \
- ixOsalOsIxp400BackwardOsslThreadCreate(entryPoint, arg, ptrTid)
-
-
-/* void ix_ossl_thread_exit(ix_error retError, void* retObj) */
-#define ix_ossl_thread_exit(retError, retObj) \
- ixOsalThreadExit()
-
-
-PUBLIC IX_STATUS ixOsalOsIxp400BackwardOsslThreadKill (IxOsalThread tid);
-
-/* ix_error ix_ossl_thread_kill(tid) */
-#define ix_ossl_thread_kill(tid) \
- ixOsalOsIxp400BackwardOsslThreadKill(tid)
-
-
-PUBLIC IX_STATUS
-ixOsalOsIxp400BackwardOsslThreadSetPriority (IxOsalThread tid,
- UINT32 priority);
-
-
-/*
- * ix_error ix_ossl_thread_set_priority(ix_ossl_thread_t tid,
- * ix_ossl_thread_priority priority
- * );
- */
-
-#define ix_ossl_thread_set_priority(tid, priority) \
- ixOsalOsIxp400BackwardOsslThreadSetPriority(tid, priority)
-
-
-PUBLIC IX_STATUS ixOsalOsIxp400BackwardOsslTickGet (int *pticks);
-
-#define ix_ossl_tick_get(pticks) \
- ixOsalOsIxp400BackwardOsslTickGet(pticks)
-
-PUBLIC IX_STATUS ixOsalOsIxp400BackwardOsslThreadDelay (int ticks);
-
-#define ix_ossl_thread_delay(ticks) ixOsalOsIxp400BackwardOsslThreadDelay(ticks)
-
-
-
-/* ix_error ix_ossl_sem_init(int start_value, ix_ossl_sem_t* sid); */
-/* Note sid is a pointer to semaphore */
-#define ix_ossl_sem_init(value, sid) \
- ixOsalSemaphoreInit(sid, value)
-
-
-PUBLIC IX_STATUS
-ixOsalOsIxp400BackwardOsslSemaphoreWait (IxOsalSemaphore semaphore,
- INT32 timeout);
-
-
-/*
-ix_error ix_ossl_sem_take(
- ix_ossl_sem_t sid,
- ix_uint32 timeout
- );
-*/
-
-#define ix_ossl_sem_take( sid, timeout) \
- ixOsalOsIxp400BackwardOsslSemaphoreWait(sid, timeout)
-
-
-
-PUBLIC IX_STATUS
-ixOsalOsIxp400BackwardOsslSemaphorePost (IxOsalSemaphore sid);
-
-/*ix_error ix_ossl_sem_give(ix_ossl_sem_t sid); */
-#define ix_ossl_sem_give(sid) \
- ixOsalOsIxp400BackwardOsslSemaphorePost(sid);
-
-
-PUBLIC IX_STATUS ixOsalOsIxp400BackwardSemaphoreDestroy (IxOsalSemaphore sid);
-
-#define ix_ossl_sem_fini(sid) \
- ixOsalOsIxp400BackwardSemaphoreDestroy(sid)
-
-
-PUBLIC IX_STATUS
-ixOsalOsIxp400BackwardOsslMutexInit (ix_ossl_mutex_state start_state,
- IxOsalMutex * pMutex);
-
-
-/* ix_error ix_ossl_mutex_init(ix_ossl_mutex_state start_state, ix_ossl_mutex_t* mid); */
-#define ix_ossl_mutex_init(start_state, pMutex) \
- ixOsalOsIxp400BackwardOsslMutexInit(start_state, pMutex)
-
-
-PUBLIC IX_STATUS
-ixOsalOsIxp400BackwardOsslMutexLock (IxOsalMutex mid, INT32 timeout);
-
-/*
-ix_error ix_ossl_mutex_lock(
- ix_ossl_mutex_t mid,
- ix_uint32 timeout
- );
-*/
-#define ix_ossl_mutex_lock(mid, timeout) \
- ixOsalOsIxp400BackwardOsslMutexLock(mid, timout)
-
-
-PUBLIC IX_STATUS ixOsalOsIxp400BackwardOsslMutexUnlock (IxOsalMutex mid);
-
-/* ix_error ix_ossl_mutex_unlock(ix_ossl_mutex_t mid); */
-#define ix_ossl_mutex_unlock(mid) \
- ixOsalOsIxp400BackwardOsslMutexUnlock(mid)
-
-PUBLIC IX_STATUS ixOsalOsIxp400BackwardOsslMutexDestroy (IxOsalMutex mid);
-
-#define ix_ossl_mutex_fini(mid) \
- ixOsalOsIxp400BackwardOsslMutexDestroy(mid);
-
-#define ix_ossl_sleep(sleeptime_ms) \
- ixOsalSleep(sleeptime_ms)
-
-PUBLIC IX_STATUS ixOsalOsIxp400BackwardOsslSleepTick (UINT32 ticks);
-
-#define ix_ossl_sleep_tick(sleeptime_ticks) \
- ixOsalOsIxp400BackwardOsslSleepTick(sleeptime_ticks)
-
-
-PUBLIC IX_STATUS ixOsalOsIxp400BackwardOsslTimeGet (IxOsalTimeval * pTv);
-
-#define ix_ossl_time_get(pTv) \
- ixOsalOsIxp400BackwardOsslTimeGet(pTv)
-
-
-typedef UINT32 ix_ossl_size_t;
-
-#define ix_ossl_malloc(arg_size) \
- ixOsalMemAlloc(arg_size)
-
-#define ix_ossl_free(arg_pMemory) \
- ixOsalMemFree(arg_pMemory)
-
-
-#define ix_ossl_memcpy(arg_pDest, arg_pSrc,arg_Count) \
- ixOsalMemCopy(arg_pDest, arg_pSrc,arg_Count)
-
-#define ix_ossl_memset(arg_pDest, arg_pChar, arg_Count) \
- ixOsalMemSet(arg_pDest, arg_pChar, arg_Count)
-
-
-#endif /* IX_OSAL_BACKWARD_OSSL_H */
+++ /dev/null
-/**
- * @file IxOsalBufferMgt.h
- *
- * @brief OSAL Buffer pool management and buffer management definitions.
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-/* @par
- * -- Copyright Notice --
- *
- * @par
- * Copyright 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994
- * The Regents of the University of California. All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the University nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsalBufferMgt_H
-#define IxOsalBufferMgt_H
-
-#include "IxOsal.h"
-/**
- * @defgroup IxOsalBufferMgt OSAL Buffer Management Module.
- *
- * @brief Buffer management module for IxOsal
- *
- * @{
- */
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_MAX_POOLS
- *
- * @brief The maximum number of pools that can be allocated, must be
- * a multiple of 32 as required by implementation logic.
- * @note This can safely be increased if more pools are required.
- */
-#define IX_OSAL_MBUF_MAX_POOLS 32
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_NAME_LEN
- *
- * @brief The maximum string length of the pool name
- */
-#define IX_OSAL_MBUF_POOL_NAME_LEN 64
-
-
-
-/**
- * Define IX_OSAL_MBUF
- */
-
-
-/* forward declaration of internal structure */
-struct __IXP_BUF;
-
-/*
- * OS can define it in IxOsalOs.h to skip the following
- * definition.
- */
-#ifndef IX_OSAL_ATTRIBUTE_ALIGN32
-#define IX_OSAL_ATTRIBUTE_ALIGN32 __attribute__ ((aligned(32)))
-#endif
-
-/* release v1.4 backward compatible definitions */
-struct __IX_MBUF
-{
- struct __IXP_BUF *ix_next IX_OSAL_ATTRIBUTE_ALIGN32;
- struct __IXP_BUF *ix_nextPacket;
- UINT8 *ix_data;
- UINT32 ix_len;
- unsigned char ix_type;
- unsigned char ix_flags;
- unsigned short ix_reserved;
- UINT32 ix_rsvd;
- UINT32 ix_PktLen;
- void *ix_priv;
-};
-
-struct __IX_CTRL
-{
- UINT32 ix_reserved[2]; /**< Reserved field */
- UINT32 ix_signature; /**< Field to indicate if buffers are allocated by the system */
- UINT32 ix_allocated_len; /**< Allocated buffer length */
- UINT32 ix_allocated_data; /**< Allocated buffer data pointer */
- void *ix_pool; /**< pointer to the buffer pool */
- struct __IXP_BUF *ix_chain; /**< chaining */
- void *ix_osbuf_ptr; /**< Storage for OS-specific buffer pointer */
-};
-
-struct __IX_NE_SHARED
-{
- UINT32 reserved[8] IX_OSAL_ATTRIBUTE_ALIGN32; /**< Reserved area for NPE Service-specific usage */
-};
-
-
-/*
- * IXP buffer structure
- */
-typedef struct __IXP_BUF
-{
- struct __IX_MBUF ix_mbuf IX_OSAL_ATTRIBUTE_ALIGN32; /**< buffer header */
- struct __IX_CTRL ix_ctrl; /**< buffer management */
- struct __IX_NE_SHARED ix_ne; /**< Reserved area for NPE Service-specific usage*/
-} IXP_BUF;
-
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def typedef IX_OSAL_MBUF
- *
- * @brief Generic IXP mbuf format.
- */
-typedef IXP_BUF IX_OSAL_MBUF;
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_IXP_NEXT_BUFFER_IN_PKT_PTR(m_blk_ptr)
- *
- * @brief Return pointer to the next mbuf in a single packet
- */
-#define IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(m_blk_ptr) \
- (m_blk_ptr)->ix_mbuf.ix_next
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m_blk_ptr)
- *
- * @brief Return pointer to the next packet in the chain
- */
-#define IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m_blk_ptr) \
- (m_blk_ptr)->ix_mbuf.ix_nextPacket
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_MDATA(m_blk_ptr)
- *
- * @brief Return pointer to the data in the mbuf
- */
-#define IX_OSAL_MBUF_MDATA(m_blk_ptr) (m_blk_ptr)->ix_mbuf.ix_data
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_MLEN(m_blk_ptr)
- *
- * @brief Return the data length
- */
-#define IX_OSAL_MBUF_MLEN(m_blk_ptr) \
- (m_blk_ptr)->ix_mbuf.ix_len
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_MTYPE(m_blk_ptr)
- *
- * @brief Return the data type in the mbuf
- */
-#define IX_OSAL_MBUF_MTYPE(m_blk_ptr) \
- (m_blk_ptr)->ix_mbuf.ix_type
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_FLAGS(m_blk_ptr)
- *
- * @brief Return the buffer flags
- */
-#define IX_OSAL_MBUF_FLAGS(m_blk_ptr) \
- (m_blk_ptr)->ix_mbuf.ix_flags
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_NET_POOL(m_blk_ptr)
- *
- * @brief Return pointer to a network pool
- */
-#define IX_OSAL_MBUF_NET_POOL(m_blk_ptr) \
- (m_blk_ptr)->ix_ctrl.ix_pool
-
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_PKT_LEN(m_blk_ptr)
- *
- * @brief Return the total length of all the data in
- * the mbuf chain for this packet
- */
-#define IX_OSAL_MBUF_PKT_LEN(m_blk_ptr) \
- (m_blk_ptr)->ix_mbuf.ix_PktLen
-
-
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_PRIV(m_blk_ptr)
- *
- * @brief Return the private field
- */
-#define IX_OSAL_MBUF_PRIV(m_blk_ptr) \
- (m_blk_ptr)->ix_mbuf.ix_priv
-
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_SIGNATURE(m_blk_ptr)
- *
- * @brief Return the signature field of IX_OSAL_MBUF
- */
-#define IX_OSAL_MBUF_SIGNATURE(m_blk_ptr) \
- (m_blk_ptr)->ix_ctrl.ix_signature
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_OSBUF_PTR(m_blk_ptr)
- *
- * @brief Return ix_osbuf_ptr field of IX_OSAL_MBUF, which is used to store OS-specific buffer pointer during a buffer conversion.
- */
-#define IX_OSAL_MBUF_OSBUF_PTR(m_blk_ptr) \
- (m_blk_ptr)->ix_ctrl.ix_osbuf_ptr
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(m_blk_ptr)
- *
- * @brief Return the allocated buffer size
- */
-#define IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(m_blk_ptr) \
- (m_blk_ptr)->ix_ctrl.ix_allocated_len
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(m_blk_ptr)
- *
- * @brief Return the allocated buffer pointer
- */
-#define IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(m_blk_ptr) \
- (m_blk_ptr)->ix_ctrl.ix_allocated_data
-
-
-
-/* Name length */
-#define IX_OSAL_MBUF_POOL_NAME_LEN 64
-
-
-/****************************************************
- * Macros for buffer pool management
- ****************************************************/
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_FREE_COUNT(m_pool_ptr
- *
- * @brief Return the total number of freed buffers left in the pool.
- */
-#define IX_OSAL_MBUF_POOL_FREE_COUNT(m_pool_ptr) \
- ixOsalBuffPoolFreeCountGet(m_pool_ptr)
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_SIZE_ALIGN
- *
- * @brief This macro takes an integer as an argument and
- * rounds it up to be a multiple of the memory cache-line
- * size.
- *
- * @param int [in] size - the size integer to be rounded up
- *
- * @return int - the size, rounded up to a multiple of
- * the cache-line size
- */
-#define IX_OSAL_MBUF_POOL_SIZE_ALIGN(size) \
- ((((size) + (IX_OSAL_CACHE_LINE_SIZE - 1)) / \
- IX_OSAL_CACHE_LINE_SIZE) * \
- IX_OSAL_CACHE_LINE_SIZE)
-
-/* Don't use this directly, use macro */
-PUBLIC UINT32 ixOsalBuffPoolMbufAreaSizeGet (int count);
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_MBUF_AREA_SIZE_ALIGNED
- *
- * @brief This macro calculates, from the number of mbufs required, the
- * size of the memory area required to contain the mbuf headers for the
- * buffers in the pool. The size to be used for each mbuf header is
- * rounded up to a multiple of the cache-line size, to ensure
- * each mbuf header aligns on a cache-line boundary.
- * This macro is used by IX_OSAL_MBUF_POOL_MBUF_AREA_ALLOC()
- *
- * @param int [in] count - the number of buffers the pool will contain
- *
- * @return int - the total size required for the pool mbuf area (aligned)
- */
-#define IX_OSAL_MBUF_POOL_MBUF_AREA_SIZE_ALIGNED(count) \
- ixOsalBuffPoolMbufAreaSizeGet(count)
-
-
-/* Don't use this directly, use macro */
-PUBLIC UINT32 ixOsalBuffPoolDataAreaSizeGet (int count, int size);
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_DATA_AREA_SIZE_ALIGNED
- *
- * @brief This macro calculates, from the number of mbufs required and the
- * size of the data portion for each mbuf, the size of the data memory area
- * required. The size is adjusted to ensure alignment on cache line boundaries.
- * This macro is used by IX_OSAL_MBUF_POOL_DATA_AREA_ALLOC()
- *
- *
- * @param int [in] count - The number of mbufs in the pool.
- * @param int [in] size - The desired size for each mbuf data portion.
- * This size will be rounded up to a multiple of the
- * cache-line size to ensure alignment on cache-line
- * boundaries for each data block.
- *
- * @return int - the total size required for the pool data area (aligned)
- */
-#define IX_OSAL_MBUF_POOL_DATA_AREA_SIZE_ALIGNED(count, size) \
- ixOsalBuffPoolDataAreaSizeGet((count), (size))
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_MBUF_AREA_ALLOC
- *
- * @brief Allocates the memory area needed for the number of mbuf headers
- * specified by <i>count</i>.
- * This macro ensures the mbuf headers align on cache line boundaries.
- * This macro evaluates to a pointer to the memory allocated.
- *
- * @param int [in] count - the number of mbufs the pool will contain
- * @param int [out] memAreaSize - the total amount of memory allocated
- *
- * @return void * - a pointer to the allocated memory area
- */
-#define IX_OSAL_MBUF_POOL_MBUF_AREA_ALLOC(count, memAreaSize) \
- IX_OSAL_CACHE_DMA_MALLOC((memAreaSize = \
- IX_OSAL_MBUF_POOL_MBUF_AREA_SIZE_ALIGNED(count)))
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_DATA_AREA_ALLOC
- *
- * @brief Allocates the memory pool for the data portion of the pool mbufs.
- * The number of mbufs is specified by <i>count</i>. The size of the data
- * portion of each mbuf is specified by <i>size</i>.
- * This macro ensures the mbufs are aligned on cache line boundaries
- * This macro evaluates to a pointer to the memory allocated.
- *
- * @param int [in] count - the number of mbufs the pool will contain
- * @param int [in] size - the desired size (in bytes) required for the data
- * portion of each mbuf. Note that this size may be
- * rounded up to ensure alignment on cache-line
- * boundaries.
- * @param int [out] memAreaSize - the total amount of memory allocated
- *
- * @return void * - a pointer to the allocated memory area
- */
-#define IX_OSAL_MBUF_POOL_DATA_AREA_ALLOC(count, size, memAreaSize) \
- IX_OSAL_CACHE_DMA_MALLOC((memAreaSize = \
- IX_OSAL_MBUF_POOL_DATA_AREA_SIZE_ALIGNED(count,size)))
-
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_INIT
- *
- * @brief Wrapper macro for ixOsalPoolInit()
- * See function description below for details.
- */
-#define IX_OSAL_MBUF_POOL_INIT(count, size, name) \
- ixOsalPoolInit((count), (size), (name))
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_NO_ALLOC_POOL_INIT
- *
- * @return Pointer to the new pool or NULL if the initialization failed.
- *
- * @brief Wrapper macro for ixOsalNoAllocPoolInit()
- * See function description below for details.
- *
- */
-#define IX_OSAL_MBUF_NO_ALLOC_POOL_INIT(bufPtr, dataPtr, count, size, name) \
- ixOsalNoAllocPoolInit( (bufPtr), (dataPtr), (count), (size), (name))
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_GET
- *
- * @brief Wrapper macro for ixOsalMbufAlloc()
- * See function description below for details.
- */
-#define IX_OSAL_MBUF_POOL_GET(poolPtr) \
- ixOsalMbufAlloc(poolPtr)
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_PUT
- *
- * @brief Wrapper macro for ixOsalMbufFree()
- * See function description below for details.
- */
-#define IX_OSAL_MBUF_POOL_PUT(bufPtr) \
- ixOsalMbufFree(bufPtr)
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_PUT_CHAIN
- *
- * @brief Wrapper macro for ixOsalMbufChainFree()
- * See function description below for details.
- */
-#define IX_OSAL_MBUF_POOL_PUT_CHAIN(bufPtr) \
- ixOsalMbufChainFree(bufPtr)
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_SHOW
- *
- * @brief Wrapper macro for ixOsalMbufPoolShow()
- * See function description below for details.
- */
-#define IX_OSAL_MBUF_POOL_SHOW(poolPtr) \
- ixOsalMbufPoolShow(poolPtr)
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_MDATA_RESET
- *
- * @brief Wrapper macro for ixOsalMbufDataPtrReset()
- * See function description below for details.
- */
-#define IX_OSAL_MBUF_POOL_MDATA_RESET(bufPtr) \
- ixOsalMbufDataPtrReset(bufPtr)
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_MBUF_POOL_UNINIT
- *
- * @brief Wrapper macro for ixOsalBuffPoolUninit()
- * See function description below for details.
- */
-#define IX_OSAL_MBUF_POOL_UNINIT(m_pool_ptr) \
- ixOsalBuffPoolUninit(m_pool_ptr)
-
-/*
- * Include OS-specific bufferMgt definitions
- */
-#include "IxOsalOsBufferMgt.h"
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_CONVERT_OSBUF_TO_IXPBUF( osBufPtr, ixpBufPtr)
- *
- * @brief Convert pre-allocated os-specific buffer format to OSAL IXP_BUF (IX_OSAL_MBUF) format.
- * It is users' responsibility to provide pre-allocated and valid buffer pointers.
- * @param osBufPtr (in) - a pre-allocated os-specific buffer pointer.
- * @param ixpBufPtr (in)- a pre-allocated OSAL IXP_BUF pointer
- * @return None
- */
-#define IX_OSAL_CONVERT_OSBUF_TO_IXPBUF( osBufPtr, ixpBufPtr) \
- IX_OSAL_OS_CONVERT_OSBUF_TO_IXPBUF( osBufPtr, ixpBufPtr)
-
-
-/**
- * @ingroup IxOsalBufferMgt
- *
- * @def IX_OSAL_CONVERT_IXPBUF_TO_OSBUF( ixpBufPtr, osBufPtr)
- *
- * @brief Convert pre-allocated OSAL IXP_BUF (IX_OSAL_MBUF) format to os-specific buffer pointers.
- * @param ixpBufPtr (in) - OSAL IXP_BUF pointer
- * @param osBufPtr (out) - os-specific buffer pointer.
- * @return None
- */
-
-#define IX_OSAL_CONVERT_IXPBUF_TO_OSBUF( ixpBufPtr, osBufPtr) \
- IX_OSAL_OS_CONVERT_IXPBUF_TO_OSBUF( ixpBufPtr, osBufPtr)
-
-
-PUBLIC IX_OSAL_MBUF_POOL *ixOsalPoolInit (UINT32 count,
- UINT32 size, const char *name);
-
-PUBLIC IX_OSAL_MBUF_POOL *ixOsalNoAllocPoolInit (void *poolBufPtr,
- void *poolDataPtr,
- UINT32 count,
- UINT32 size,
- const char *name);
-
-PUBLIC IX_OSAL_MBUF *ixOsalMbufAlloc (IX_OSAL_MBUF_POOL * pool);
-
-PUBLIC IX_OSAL_MBUF *ixOsalMbufFree (IX_OSAL_MBUF * mbuf);
-
-PUBLIC void ixOsalMbufChainFree (IX_OSAL_MBUF * mbuf);
-
-PUBLIC void ixOsalMbufDataPtrReset (IX_OSAL_MBUF * mbuf);
-
-PUBLIC void ixOsalMbufPoolShow (IX_OSAL_MBUF_POOL * pool);
-
-PUBLIC IX_STATUS ixOsalBuffPoolUninit (IX_OSAL_MBUF_POOL * pool);
-
-PUBLIC UINT32 ixOsalBuffPoolFreeCountGet(IX_OSAL_MBUF_POOL * pool);
-
-
-/**
- * @} IxOsalBufferMgt
- */
-
-
-#endif /* IxOsalBufferMgt_H */
+++ /dev/null
-/**
- * @file IxOsalBufferMgtDefault.h
- *
- * @brief Default buffer pool management and buffer management
- * definitions.
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IX_OSAL_BUFFER_MGT_DEFAULT_H
-#define IX_OSAL_BUFFER_MGT_DEFAULT_H
-
-/**
- * @enum IxMbufPoolAllocationType
- * @brief Used to indicate how the pool memory was allocated
- */
-
-typedef enum
-{
- IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC = 0, /**< mbuf pool allocated by the system */
- IX_OSAL_MBUF_POOL_TYPE_USER_ALLOC /**< mbuf pool allocated by the user */
-} IxOsalMbufPoolAllocationType;
-
-
-/**
- * @brief Implementation of buffer pool structure for use with non-VxWorks OS
- */
-
-typedef struct
-{
- IX_OSAL_MBUF *nextFreeBuf; /**< Pointer to the next free mbuf */
- void *mbufMemPtr; /**< Pointer to the mbuf memory area */
- void *dataMemPtr; /**< Pointer to the data memory area */
- int bufDataSize; /**< The size of the data portion of each mbuf */
- int totalBufsInPool; /**< Total number of mbufs in the pool */
- int freeBufsInPool; /**< Number of free mbufs currently in the pool */
- int mbufMemSize; /**< The size of the pool mbuf memory area */
- int dataMemSize; /**< The size of the pool data memory area */
- char name[IX_OSAL_MBUF_POOL_NAME_LEN + 1]; /**< Descriptive name for pool */
- IxOsalMbufPoolAllocationType poolAllocType;
- unsigned int poolIdx; /**< Pool Index */
-} IxOsalMbufPool;
-
-typedef IxOsalMbufPool IX_OSAL_MBUF_POOL;
-
-
-PUBLIC IX_STATUS ixOsalBuffPoolUninit (IX_OSAL_MBUF_POOL * pool);
-
-
-#endif /* IX_OSAL_BUFFER_MGT_DEFAULT_H */
+++ /dev/null
-/**
- * @file IxOsalConfig.h
- *
- * @brief OSAL Configuration header file
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-/*
- * This file contains user-editable fields for modules inclusion.
- */
-#ifndef IxOsalConfig_H
-#define IxOsalConfig_H
-
-
-/*
- * Note: in the future these config options may
- * become build time decision.
- */
-
-/* Choose cache */
-#define IX_OSAL_CACHED
-/* #define IX_OSAL_UNCACHED */
-
-
-/*
- * Select the module headers to include
- */
-#include "IxOsalIoMem.h" /* I/O Memory Management module API */
-#include "IxOsalBufferMgt.h" /* Buffer Management module API */
-
-/*
- * Select main platform header file to use
- */
-#include "IxOsalOem.h"
-
-
-
-#endif /* IxOsalConfig_H */
+++ /dev/null
-/**
- * @file IxOsalEndianess.h (Obsolete file)
- *
- * @brief Header file for determining system endianess and OS
- *
- * @par
- * @version $Revision: 1.1
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#ifndef IxOsalEndianess_H
-#define IxOsalEndianess_H
-
-#if defined (__vxworks) || defined (__linux)
-
-/* get ntohl/ntohs/htohl/htons macros and CPU definitions for VxWorks */
-/* #include <netinet/in.h> */
-
-#elif defined (__wince)
-
-/* get ntohl/ntohs/htohl/htons macros definitions for WinCE */
-#include <Winsock2.h>
-
-#else
-
-#error Unknown OS, please add a section with the include file for htonl/htons/ntohl/ntohs
-
-#endif /* vxworks or linux or wince */
-
-/* Compiler specific endianness selector - WARNING this works only with arm gcc, use appropriate defines with diab */
-
-#ifndef __wince
-
-#if defined (__ARMEL__)
-
-#ifndef __LITTLE_ENDIAN
-
-#define __LITTLE_ENDIAN
-
-#endif /* _LITTLE_ENDIAN */
-
-#elif defined (__ARMEB__) || CPU == SIMSPARCSOLARIS
-
-#ifndef __BIG_ENDIAN
-
-#define __BIG_ENDIAN
-
-#endif /* __BIG_ENDIAN */
-
-#else
-
-#error Error, could not identify target endianness
-
-#endif /* endianness selector no WinCE OSes */
-
-#else /* ndef __wince */
-
-#define __LITTLE_ENDIAN
-
-#endif /* def __wince */
-
-
-/* OS mode selector */
-#if defined (__vxworks) && defined (__LITTLE_ENDIAN)
-
-#define IX_OSAL_VXWORKS_LE
-
-#elif defined (__vxworks) && defined (__BIG_ENDIAN)
-
-#define IX_OSAL_VXWORKS_BE
-
-#elif defined (__linux) && defined (__BIG_ENDIAN)
-
-#define IX_OSAL_LINUX_BE
-
-#elif defined (__linux) && defined (__LITTLE_ENDIAN)
-
-#define IX_OSAL_LINUX_LE
-
-#elif defined (BOOTLOADER_BLD) && defined (__LITTLE_ENDIAN)
-
-#define IX_OSAL_EBOOT_LE
-
-#elif defined (__wince) && defined (__LITTLE_ENDIAN)
-
-#define IX_OSAL_WINCE_LE
-
-#else
-
-#error Unknown OS/Endianess combination - only vxWorks BE LE, Linux BE LE, WinCE BE LE are supported
-
-#endif /* mode selector */
-
-
-
-#endif /* IxOsalEndianess_H */
+++ /dev/null
-/*
- * @file IxOsalIoMem.h
- * @author Intel Corporation
- * @date 25-08-2004
- *
- * @brief description goes here
- */
-
-/**
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsalIoMem_H
-#define IxOsalIoMem_H
-
-
-/*
- * Decide OS and Endianess, such as IX_OSAL_VXWORKS_LE.
- */
-#include "IxOsalEndianess.h"
-
-/**
- * @defgroup IxOsalIoMem Osal IoMem module
- *
- * @brief I/O memory and endianess support.
- *
- * @{
- */
-
-/* Low-level conversion macros - DO NOT USE UNLESS ABSOLUTELY NEEDED */
-#ifndef __wince
-
-
-/*
- * Private function to swap word
- */
-#ifdef __XSCALE__
-static __inline__ UINT32
-ixOsalCoreWordSwap (UINT32 wordIn)
-{
- /*
- * Storage for the swapped word
- */
- UINT32 wordOut;
-
- /*
- * wordIn = A, B, C, D
- */
- __asm__ (" eor r1, %1, %1, ror #16;" /* R1 = A^C, B^D, C^A, D^B */
- " bic r1, r1, #0x00ff0000;" /* R1 = A^C, 0 , C^A, D^B */
- " mov %0, %1, ror #8;" /* wordOut = D, A, B, C */
- " eor %0, %0, r1, lsr #8;" /* wordOut = D, C, B, A */
- : "=r" (wordOut): "r" (wordIn):"r1");
-
- return wordOut;
-}
-
-#define IX_OSAL_SWAP_LONG(wData) (ixOsalCoreWordSwap(wData))
-#else
-#define IX_OSAL_SWAP_LONG(wData) ((wData >> 24) | (((wData >> 16) & 0xFF) << 8) | (((wData >> 8) & 0xFF) << 16) | ((wData & 0xFF) << 24))
-#endif
-
-#else /* ndef __wince */
-#define IX_OSAL_SWAP_LONG(wData) ((((UINT32)wData << 24) | ((UINT32)wData >> 24)) | (((wData << 8) & 0xff0000) | ((wData >> 8) & 0xff00)))
-#endif /* ndef __wince */
-
-#define IX_OSAL_SWAP_SHORT(sData) ((sData >> 8) | ((sData & 0xFF) << 8))
-#define IX_OSAL_SWAP_SHORT_ADDRESS(sAddr) ((sAddr) ^ 0x2)
-#define IX_OSAL_SWAP_BYTE_ADDRESS(bAddr) ((bAddr) ^ 0x3)
-
-#define IX_OSAL_BE_XSTOBUSL(wData) (wData)
-#define IX_OSAL_BE_XSTOBUSS(sData) (sData)
-#define IX_OSAL_BE_XSTOBUSB(bData) (bData)
-#define IX_OSAL_BE_BUSTOXSL(wData) (wData)
-#define IX_OSAL_BE_BUSTOXSS(sData) (sData)
-#define IX_OSAL_BE_BUSTOXSB(bData) (bData)
-
-#define IX_OSAL_LE_AC_XSTOBUSL(wAddr) (wAddr)
-#define IX_OSAL_LE_AC_XSTOBUSS(sAddr) IX_OSAL_SWAP_SHORT_ADDRESS(sAddr)
-#define IX_OSAL_LE_AC_XSTOBUSB(bAddr) IX_OSAL_SWAP_BYTE_ADDRESS(bAddr)
-#define IX_OSAL_LE_AC_BUSTOXSL(wAddr) (wAddr)
-#define IX_OSAL_LE_AC_BUSTOXSS(sAddr) IX_OSAL_SWAP_SHORT_ADDRESS(sAddr)
-#define IX_OSAL_LE_AC_BUSTOXSB(bAddr) IX_OSAL_SWAP_BYTE_ADDRESS(bAddr)
-
-#define IX_OSAL_LE_DC_XSTOBUSL(wData) IX_OSAL_SWAP_LONG(wData)
-#define IX_OSAL_LE_DC_XSTOBUSS(sData) IX_OSAL_SWAP_SHORT(sData)
-#define IX_OSAL_LE_DC_XSTOBUSB(bData) (bData)
-#define IX_OSAL_LE_DC_BUSTOXSL(wData) IX_OSAL_SWAP_LONG(wData)
-#define IX_OSAL_LE_DC_BUSTOXSS(sData) IX_OSAL_SWAP_SHORT(sData)
-#define IX_OSAL_LE_DC_BUSTOXSB(bData) (bData)
-
-
-/*
- * Decide SDRAM mapping, then implement read/write
- */
-#include "IxOsalMemAccess.h"
-
-
-/**
- * @ingroup IxOsalIoMem
- * @enum IxOsalMapEntryType
- * @brief This is an emum for OSAL I/O mem map type.
- */
-typedef enum
-{
- IX_OSAL_STATIC_MAP = 0, /**<Set map entry type to static map */
- IX_OSAL_DYNAMIC_MAP /**<Set map entry type to dynamic map */
-} IxOsalMapEntryType;
-
-
-/**
- * @ingroup IxOsalIoMem
- * @enum IxOsalMapEndianessType
- * @brief This is an emum for OSAL I/O mem Endianess and Coherency mode.
- */
-typedef enum
-{
- IX_OSAL_BE = 0x1, /**<Set map endian mode to Big Endian */
- IX_OSAL_LE_AC = 0x2, /**<Set map endian mode to Little Endian, Address Coherent */
- IX_OSAL_LE_DC = 0x4, /**<Set map endian mode to Little Endian, Data Coherent */
- IX_OSAL_LE = 0x8 /**<Set map endian mode to Little Endian without specifying coherency mode */
-} IxOsalMapEndianessType;
-
-
-/**
- * @struct IxOsalMemoryMap
- * @brief IxOsalMemoryMap structure
- */
-typedef struct _IxOsalMemoryMap
-{
- IxOsalMapEntryType type; /**< map type - IX_OSAL_STATIC_MAP or IX_OSAL_DYNAMIC_MAP */
-
- UINT32 physicalAddress; /**< physical address of the memory mapped I/O zone */
-
- UINT32 size; /**< size of the map */
-
- UINT32 virtualAddress; /**< virtual address of the zone; must be predefined
- in the global memory map for static maps and has
- to be NULL for dynamic maps (populated on allocation)
- */
- /*
- * pointer to a map function called to map a dynamic map;
- * will populate the virtualAddress field
- */
- void (*mapFunction) (struct _IxOsalMemoryMap * map); /**< pointer to a map function called to map a dynamic map */
-
- /*
- * pointer to a map function called to unmap a dynamic map;
- * will reset the virtualAddress field to NULL
- */
- void (*unmapFunction) (struct _IxOsalMemoryMap * map); /**< pointer to a map function called to unmap a dynamic map */
-
- /*
- * reference count describing how many components share this map;
- * actual allocation/deallocation for dynamic maps is done only
- * between 0 <=> 1 transitions of the counter
- */
- UINT32 refCount; /**< reference count describing how many components share this map */
-
- /*
- * memory endian type for the map; can be a combination of IX_OSAL_BE (Big
- * Endian) and IX_OSAL_LE or IX_OSAL_LE_AC or IX_OSAL_LE_DC
- * (Little Endian, Address Coherent or Data Coherent). Any combination is
- * allowed provided it contains at most one LE flag - e.g.
- * (IX_OSAL_BE), (IX_OSAL_LE_AC), (IX_OSAL_BE | IX_OSAL_LE_DC) are valid
- * combinations while (IX_OSAL_BE | IX_OSAL_LE_DC | IX_OSAL_LE_AC) is not.
- */
- IxOsalMapEndianessType mapEndianType; /**< memory endian type for the map */
-
- char *name; /**< user-friendly name */
-} IxOsalMemoryMap;
-
-
-
-
-/* Internal function to map a memory zone
- * NOTE - This should not be called by the user.
- * Use the macro IX_OSAL_MEM_MAP instead
- */
-PUBLIC void *ixOsalIoMemMap (UINT32 requestedAddress,
- UINT32 size,
- IxOsalMapEndianessType requestedCoherency);
-
-
-/* Internal function to unmap a memory zone mapped with ixOsalIoMemMap
- * NOTE - This should not be called by the user.
- * Use the macro IX_OSAL_MEM_UNMAP instead
- */
-PUBLIC void ixOsalIoMemUnmap (UINT32 requestedAddress, UINT32 coherency);
-
-
-/* Internal function to convert virtual address to physical address
- * NOTE - This should not be called by the user.
- * Use the macro IX_OSAL_MMAP_VIRT_TO_PHYS */
-PUBLIC UINT32 ixOsalIoMemVirtToPhys (UINT32 virtualAddress, UINT32 coherency);
-
-
-/* Internal function to convert physical address to virtual address
- * NOTE - This should not be called by the user.
- * Use the macro IX_OSAL_MMAP_PHYS_TO_VIRT */
-PUBLIC UINT32
-ixOsalIoMemPhysToVirt (UINT32 physicalAddress, UINT32 coherency);
-
-/**
- * @ingroup IxOsalIoMem
- *
- * @def IX_OSAL_MEM_MAP(physAddr, size)
- *
- * @brief Map an I/O mapped physical memory zone to virtual zone and return virtual
- * pointer.
- * @param physAddr - the physical address
- * @param size - the size
- * @return start address of the virtual memory zone.
- *
- * @note This function maps an I/O mapped physical memory zone of the given size
- * into a virtual memory zone accessible by the caller and returns a cookie -
- * the start address of the virtual memory zone.
- * IX_OSAL_MMAP_PHYS_TO_VIRT should NOT therefore be used on the returned
- * virtual address.
- * The memory zone is to be unmapped using IX_OSAL_MEM_UNMAP once the caller has
- * finished using this zone (e.g. on driver unload) using the cookie as
- * parameter.
- * The IX_OSAL_READ/WRITE_LONG/SHORT macros should be used to read and write
- * the mapped memory, adding the necessary offsets to the address cookie.
- */
-#define IX_OSAL_MEM_MAP(physAddr, size) \
- ixOsalIoMemMap((physAddr), (size), IX_OSAL_COMPONENT_MAPPING)
-
-
-/**
- * @ingroup IxOsalIoMem
- *
- * @def IX_OSAL_MEM_UNMAP(virtAddr)
- *
- * @brief Unmap a previously mapped I/O memory zone using virtual pointer obtained
- * during the mapping operation.
- * pointer.
- * @param virtAddr - the virtual pointer to the zone to be unmapped.
- * @return none
- *
- * @note This function unmaps a previously mapped I/O memory zone using
- * the cookie obtained in the mapping operation. The memory zone in question
- * becomes unavailable to the caller once unmapped and the cookie should be
- * discarded.
- *
- * This function cannot fail if the given parameter is correct and does not
- * return a value.
- */
-#define IX_OSAL_MEM_UNMAP(virtAddr) \
- ixOsalIoMemUnmap ((virtAddr), IX_OSAL_COMPONENT_MAPPING)
-
-/**
- * @ingroup IxOsalIoMem
- *
- * @def IX_OSAL_MMAP_VIRT_TO_PHYS(virtAddr)
- *
- * @brief This function Converts a virtual address into a physical
- * address, including the dynamically mapped memory.
- *
- * @param virtAddr - virtual address to convert
- * Return value: corresponding physical address, or NULL
- */
-#define IX_OSAL_MMAP_VIRT_TO_PHYS(virtAddr) \
- ixOsalIoMemVirtToPhys(virtAddr, IX_OSAL_COMPONENT_MAPPING)
-
-
-/**
- * @ingroup IxOsalIoMem
- *
- * @def IX_OSAL_MMAP_PHYS_TO_VIRT(physAddr)
- *
- * @brief This function Converts a virtual address into a physical
- * address, including the dynamically mapped memory.
- *
- * @param physAddr - physical address to convert
- * Return value: corresponding virtual address, or NULL
- *
- */
-#define IX_OSAL_MMAP_PHYS_TO_VIRT(physAddr) \
- ixOsalIoMemPhysToVirt(physAddr, IX_OSAL_COMPONENT_MAPPING)
-
-/**
- * @} IxOsalIoMem
- */
-
-#endif /* IxOsalIoMem_H */
+++ /dev/null
-/**
- * @file IxOsalMemAccess.h
- *
- * @brief Header file for memory access
- *
- * @par
- * @version $Revision: 1.0 $
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsalMemAccess_H
-#define IxOsalMemAccess_H
-
-
-/* Global BE switch
- *
- * Should be set only in BE mode and only if the component uses I/O memory.
- */
-
-#if defined (__BIG_ENDIAN)
-
-#define IX_OSAL_BE_MAPPING
-
-#endif /* Global switch */
-
-
-/* By default only static memory maps in use;
- define IX_OSAL_DYNAMIC_MEMORY_MAP per component if dynamic maps are
- used instead in that component */
-#define IX_OSAL_STATIC_MEMORY_MAP
-
-
-/*
- * SDRAM coherency mode
- * Must be defined to BE, LE_DATA_COHERENT or LE_ADDRESS_COHERENT.
- * The mode changes depending on OS
- */
-#if defined (IX_OSAL_LINUX_BE) || defined (IX_OSAL_VXWORKS_BE)
-
-#define IX_SDRAM_BE
-
-#elif defined (IX_OSAL_VXWORKS_LE)
-
-#define IX_SDRAM_LE_DATA_COHERENT
-
-#elif defined (IX_OSAL_LINUX_LE)
-
-#define IX_SDRAM_LE_DATA_COHERENT
-
-#elif defined (IX_OSAL_WINCE_LE)
-
-#define IX_SDRAM_LE_DATA_COHERENT
-
-#elif defined (IX_OSAL_EBOOT_LE)
-
-#define IX_SDRAM_LE_ADDRESS_COHERENT
-
-#endif
-
-
-
-
-/**************************************
- * Retrieve current component mapping *
- **************************************/
-
-/*
- * Only use customized mapping for LE.
- *
- */
-#if defined (IX_OSAL_VXWORKS_LE) || defined (IX_OSAL_LINUX_LE) || defined (IX_OSAL_WINCE_LE) || defined (IX_OSAL_EBOOT_LE)
-
-#include "IxOsalOsIxp400CustomizedMapping.h"
-
-#endif
-
-
-/*******************************************************************
- * Turn off IX_STATIC_MEMORY map for components using dynamic maps *
- *******************************************************************/
-#ifdef IX_OSAL_DYNAMIC_MEMORY_MAP
-
-#undef IX_OSAL_STATIC_MEMORY_MAP
-
-#endif
-
-
-/************************************************************
- * Turn off BE access for components using LE or no mapping *
- ************************************************************/
-
-#if ( defined (IX_OSAL_LE_AC_MAPPING) || defined (IX_OSAL_LE_DC_MAPPING) || defined (IX_OSAL_NO_MAPPING) )
-
-#undef IX_OSAL_BE_MAPPING
-
-#endif
-
-
-/*****************
- * Safety checks *
- *****************/
-
-/* Default to no_mapping */
-#if !defined (IX_OSAL_BE_MAPPING) && !defined (IX_OSAL_LE_AC_MAPPING) && !defined (IX_OSAL_LE_DC_MAPPING) && !defined (IX_OSAL_NO_MAPPING)
-
-#define IX_OSAL_NO_MAPPING
-
-#endif /* check at least one mapping */
-
-/* No more than one mapping can be defined for a component */
-#if (defined (IX_OSAL_BE_MAPPING) && defined (IX_OSAL_LE_AC_MAPPING)) \
- ||(defined (IX_OSAL_BE_MAPPING) && defined (IX_OSAL_LE_DC_MAPPING)) \
- ||(defined (IX_OSAL_BE_MAPPING) && defined (IX_OSAL_NO_MAPPING)) \
- ||(defined (IX_OSAL_LE_DC_MAPPING) && defined (IX_OSAL_NO_MAPPING)) \
- ||(defined (IX_OSAL_LE_DC_MAPPING) && defined (IX_OSAL_LE_AC_MAPPING)) \
- ||(defined (IX_OSAL_LE_AC_MAPPING) && defined (IX_OSAL_NO_MAPPING))
-
-
-#ifdef IX_OSAL_BE_MAPPING
-#warning IX_OSAL_BE_MAPPING is defined
-#endif
-
-#ifdef IX_OSAL_LE_AC_MAPPING
-#warning IX_OSAL_LE_AC_MAPPING is defined
-#endif
-
-#ifdef IX_OSAL_LE_DC_MAPPING
-#warning IX_OSAL_LE_DC_MAPPING is defined
-#endif
-
-#ifdef IX_OSAL_NO_MAPPING
-#warning IX_OSAL_NO_MAPPING is defined
-#endif
-
-#error More than one I/O mapping is defined, please check your component mapping
-
-#endif /* check at most one mapping */
-
-
-/* Now set IX_OSAL_COMPONENT_MAPPING */
-
-#ifdef IX_OSAL_BE_MAPPING
-#define IX_OSAL_COMPONENT_MAPPING IX_OSAL_BE
-#endif
-
-#ifdef IX_OSAL_LE_AC_MAPPING
-#define IX_OSAL_COMPONENT_MAPPING IX_OSAL_LE_AC
-#endif
-
-#ifdef IX_OSAL_LE_DC_MAPPING
-#define IX_OSAL_COMPONENT_MAPPING IX_OSAL_LE_DC
-#endif
-
-#ifdef IX_OSAL_NO_MAPPING
-#define IX_OSAL_COMPONENT_MAPPING IX_OSAL_LE
-#endif
-
-
-/* SDRAM coherency should be defined */
-#if !defined (IX_SDRAM_BE) && !defined (IX_SDRAM_LE_DATA_COHERENT) && !defined (IX_SDRAM_LE_ADDRESS_COHERENT)
-
-#error SDRAM coherency must be defined
-
-#endif /* SDRAM coherency must be defined */
-
-/* SDRAM coherency cannot be defined in several ways */
-#if (defined (IX_SDRAM_BE) && (defined (IX_SDRAM_LE_DATA_COHERENT) || defined (IX_SDRAM_LE_ADDRESS_COHERENT))) \
- || (defined (IX_SDRAM_LE_DATA_COHERENT) && (defined (IX_SDRAM_BE) || defined (IX_SDRAM_LE_ADDRESS_COHERENT))) \
- || (defined (IX_SDRAM_LE_ADDRESS_COHERENT) && (defined (IX_SDRAM_BE) || defined (IX_SDRAM_LE_DATA_COHERENT)))
-
-#error SDRAM coherency cannot be defined in more than one way
-
-#endif /* SDRAM coherency must be defined exactly once */
-
-
-/*********************
- * Read/write macros *
- *********************/
-
-/* WARNING - except for addition of special cookie read/write macros (see below)
- these macros are NOT user serviceable. Please do not modify */
-
-#define IX_OSAL_READ_LONG_RAW(wAddr) (*(wAddr))
-#define IX_OSAL_READ_SHORT_RAW(sAddr) (*(sAddr))
-#define IX_OSAL_READ_BYTE_RAW(bAddr) (*(bAddr))
-#define IX_OSAL_WRITE_LONG_RAW(wAddr, wData) (*(wAddr) = (wData))
-#define IX_OSAL_WRITE_SHORT_RAW(sAddr,sData) (*(sAddr) = (sData))
-#define IX_OSAL_WRITE_BYTE_RAW(bAddr, bData) (*(bAddr) = (bData))
-
-#ifdef __linux
-
-/* Linux - specific cookie reads/writes.
- Redefine per OS if dynamic memory maps are used
- and I/O memory is accessed via functions instead of raw pointer access. */
-
-#define IX_OSAL_READ_LONG_COOKIE(wCookie) (readl((UINT32) (wCookie) ))
-#define IX_OSAL_READ_SHORT_COOKIE(sCookie) (readw((UINT32) (sCookie) ))
-#define IX_OSAL_READ_BYTE_COOKIE(bCookie) (readb((UINT32) (bCookie) ))
-#define IX_OSAL_WRITE_LONG_COOKIE(wCookie, wData) (writel(wData, (UINT32) (wCookie) ))
-#define IX_OSAL_WRITE_SHORT_COOKIE(sCookie, sData) (writew(sData, (UINT32) (sCookie) ))
-#define IX_OSAL_WRITE_BYTE_COOKIE(bCookie, bData) (writeb(bData, (UINT32) (bCookie) ))
-
-#endif /* linux */
-
-#ifdef __wince
-
-/* WinCE - specific cookie reads/writes. */
-
-static __inline__ UINT32
-ixOsalWinCEReadLCookie (volatile UINT32 * lCookie)
-{
- return *lCookie;
-}
-
-static __inline__ UINT16
-ixOsalWinCEReadWCookie (volatile UINT16 * wCookie)
-{
-#if 0
- UINT32 auxVal = *((volatile UINT32 *) wCookie);
- if ((unsigned) wCookie & 3)
- return (UINT16) (auxVal >> 16);
- else
- return (UINT16) (auxVal & 0xffff);
-#else
- return *wCookie;
-#endif
-}
-
-static __inline__ UINT8
-ixOsalWinCEReadBCookie (volatile UINT8 * bCookie)
-{
-#if 0
- UINT32 auxVal = *((volatile UINT32 *) bCookie);
- return (UINT8) ((auxVal >> (3 - (((unsigned) bCookie & 3) << 3)) & 0xff));
-#else
- return *bCookie;
-#endif
-}
-
-static __inline__ void
-ixOsalWinCEWriteLCookie (volatile UINT32 * lCookie, UINT32 lVal)
-{
- *lCookie = lVal;
-}
-
-static __inline__ void
-ixOsalWinCEWriteWCookie (volatile UINT16 * wCookie, UINT16 wVal)
-{
-#if 0
- volatile UINT32 *auxCookie =
- (volatile UINT32 *) ((unsigned) wCookie & ~3);
- if ((unsigned) wCookie & 3)
- {
- *auxCookie &= 0xffff;
- *auxCookie |= (UINT32) wVal << 16;
- }
- else
- {
- *auxCookie &= ~0xffff;
- *auxCookie |= (UINT32) wVal & 0xffff;
- }
-#else
- *wCookie = wVal;
-#endif
-}
-
-static __inline__ void
-ixOsalWinCEWriteBCookie (volatile UINT8 * bCookie, UINT8 bVal)
-{
-#if 0
- volatile UINT32 *auxCookie =
- (volatile UINT32 *) ((unsigned) bCookie & ~3);
- *auxCookie &= 0xff << (3 - (((unsigned) bCookie & 3) << 3));
- *auxCookie |= (UINT32) bVal << (3 - (((unsigned) bCookie & 3) << 3));
-#else
- *bCookie = bVal;
-#endif
-}
-
-
-#define IX_OSAL_READ_LONG_COOKIE(wCookie) (ixOsalWinCEReadLCookie(wCookie))
-#define IX_OSAL_READ_SHORT_COOKIE(sCookie) (ixOsalWinCEReadWCookie(sCookie))
-#define IX_OSAL_READ_BYTE_COOKIE(bCookie) (ixOsalWinCEReadBCookie(bCookie))
-#define IX_OSAL_WRITE_LONG_COOKIE(wCookie, wData) (ixOsalWinCEWriteLCookie(wCookie, wData))
-#define IX_OSAL_WRITE_SHORT_COOKIE(sCookie, sData) (ixOsalWinCEWriteWCookie(sCookie, sData))
-#define IX_OSAL_WRITE_BYTE_COOKIE(bCookie, bData) (ixOsalWinCEWriteBCookie(bCookie, bData))
-
-#endif /* wince */
-
-#if defined (__vxworks) || (defined (__linux) && defined (IX_OSAL_STATIC_MEMORY_MAP)) || \
- (defined (__wince) && defined (IX_OSAL_STATIC_MEMORY_MAP))
-
-#define IX_OSAL_READ_LONG_IO(wAddr) IX_OSAL_READ_LONG_RAW(wAddr)
-#define IX_OSAL_READ_SHORT_IO(sAddr) IX_OSAL_READ_SHORT_RAW(sAddr)
-#define IX_OSAL_READ_BYTE_IO(bAddr) IX_OSAL_READ_BYTE_RAW(bAddr)
-#define IX_OSAL_WRITE_LONG_IO(wAddr, wData) IX_OSAL_WRITE_LONG_RAW(wAddr, wData)
-#define IX_OSAL_WRITE_SHORT_IO(sAddr, sData) IX_OSAL_WRITE_SHORT_RAW(sAddr, sData)
-#define IX_OSAL_WRITE_BYTE_IO(bAddr, bData) IX_OSAL_WRITE_BYTE_RAW(bAddr, bData)
-
-#elif (defined (__linux) && !defined (IX_OSAL_STATIC_MEMORY_MAP)) || \
- (defined (__wince) && !defined (IX_OSAL_STATIC_MEMORY_MAP))
-
-#ifndef __wince
-#include <asm/io.h>
-#endif /* ndef __wince */
-
-#define IX_OSAL_READ_LONG_IO(wAddr) IX_OSAL_READ_LONG_COOKIE(wAddr)
-#define IX_OSAL_READ_SHORT_IO(sAddr) IX_OSAL_READ_SHORT_COOKIE(sAddr)
-#define IX_OSAL_READ_BYTE_IO(bAddr) IX_OSAL_READ_BYTE_COOKIE(bAddr)
-#define IX_OSAL_WRITE_LONG_IO(wAddr, wData) IX_OSAL_WRITE_LONG_COOKIE(wAddr, wData)
-#define IX_OSAL_WRITE_SHORT_IO(sAddr, sData) IX_OSAL_WRITE_SHORT_COOKIE(sAddr, sData)
-#define IX_OSAL_WRITE_BYTE_IO(bAddr, bData) IX_OSAL_WRITE_BYTE_COOKIE(bAddr, bData)
-
-#endif
-
-/* Define BE macros */
-#define IX_OSAL_READ_LONG_BE(wAddr) IX_OSAL_BE_BUSTOXSL(IX_OSAL_READ_LONG_IO((volatile UINT32 *) (wAddr) ))
-#define IX_OSAL_READ_SHORT_BE(sAddr) IX_OSAL_BE_BUSTOXSS(IX_OSAL_READ_SHORT_IO((volatile UINT16 *) (sAddr) ))
-#define IX_OSAL_READ_BYTE_BE(bAddr) IX_OSAL_BE_BUSTOXSB(IX_OSAL_READ_BYTE_IO((volatile UINT8 *) (bAddr) ))
-#define IX_OSAL_WRITE_LONG_BE(wAddr, wData) IX_OSAL_WRITE_LONG_IO((volatile UINT32 *) (wAddr), IX_OSAL_BE_XSTOBUSL((UINT32) (wData) ))
-#define IX_OSAL_WRITE_SHORT_BE(sAddr, sData) IX_OSAL_WRITE_SHORT_IO((volatile UINT16 *) (sAddr), IX_OSAL_BE_XSTOBUSS((UINT16) (sData) ))
-#define IX_OSAL_WRITE_BYTE_BE(bAddr, bData) IX_OSAL_WRITE_BYTE_IO((volatile UINT8 *) (bAddr), IX_OSAL_BE_XSTOBUSB((UINT8) (bData) ))
-
-/* Define LE AC macros */
-#define IX_OSAL_READ_LONG_LE_AC(wAddr) IX_OSAL_READ_LONG_IO((volatile UINT32 *) IX_OSAL_LE_AC_BUSTOXSL((UINT32) (wAddr) ))
-#define IX_OSAL_READ_SHORT_LE_AC(sAddr) IX_OSAL_READ_SHORT_IO((volatile UINT16 *) IX_OSAL_LE_AC_BUSTOXSS((UINT32) (sAddr) ))
-#define IX_OSAL_READ_BYTE_LE_AC(bAddr) IX_OSAL_READ_BYTE_IO((volatile UINT8 *) IX_OSAL_LE_AC_BUSTOXSB((UINT32) (bAddr) ))
-#define IX_OSAL_WRITE_LONG_LE_AC(wAddr, wData) IX_OSAL_WRITE_LONG_IO((volatile UINT32 *) IX_OSAL_LE_AC_XSTOBUSL((UINT32) (wAddr) ), (UINT32) (wData))
-#define IX_OSAL_WRITE_SHORT_LE_AC(sAddr, sData) IX_OSAL_WRITE_SHORT_IO((volatile UINT16 *) IX_OSAL_LE_AC_XSTOBUSS((UINT32) (sAddr) ), (UINT16) (sData))
-#define IX_OSAL_WRITE_BYTE_LE_AC(bAddr, bData) IX_OSAL_WRITE_BYTE_IO((volatile UINT8 *) IX_OSAL_LE_AC_XSTOBUSB((UINT32) (bAddr) ), (UINT8) (bData))
-
-
-/* Inline functions are required here to avoid reading the same I/O location 2 or 4 times for the byte swap */
-static __inline__ UINT32
-ixOsalDataCoherentLongReadSwap (volatile UINT32 * wAddr)
-{
- UINT32 wData = IX_OSAL_READ_LONG_IO (wAddr);
- return IX_OSAL_LE_DC_BUSTOXSL (wData);
-}
-
-static __inline__ UINT16
-ixOsalDataCoherentShortReadSwap (volatile UINT16 * sAddr)
-{
- UINT16 sData = IX_OSAL_READ_SHORT_IO (sAddr);
- return IX_OSAL_LE_DC_BUSTOXSS (sData);
-}
-
-static __inline__ void
-ixOsalDataCoherentLongWriteSwap (volatile UINT32 * wAddr, UINT32 wData)
-{
- wData = IX_OSAL_LE_DC_XSTOBUSL (wData);
- IX_OSAL_WRITE_LONG_IO (wAddr, wData);
-}
-
-static __inline__ void
-ixOsalDataCoherentShortWriteSwap (volatile UINT16 * sAddr, UINT16 sData)
-{
- sData = IX_OSAL_LE_DC_XSTOBUSS (sData);
- IX_OSAL_WRITE_SHORT_IO (sAddr, sData);
-}
-
-/* Define LE DC macros */
-
-#define IX_OSAL_READ_LONG_LE_DC(wAddr) ixOsalDataCoherentLongReadSwap((volatile UINT32 *) (wAddr) )
-#define IX_OSAL_READ_SHORT_LE_DC(sAddr) ixOsalDataCoherentShortReadSwap((volatile UINT16 *) (sAddr) )
-#define IX_OSAL_READ_BYTE_LE_DC(bAddr) IX_OSAL_LE_DC_BUSTOXSB(IX_OSAL_READ_BYTE_IO((volatile UINT8 *) (bAddr) ))
-#define IX_OSAL_WRITE_LONG_LE_DC(wAddr, wData) ixOsalDataCoherentLongWriteSwap((volatile UINT32 *) (wAddr), (UINT32) (wData))
-#define IX_OSAL_WRITE_SHORT_LE_DC(sAddr, sData) ixOsalDataCoherentShortWriteSwap((volatile UINT16 *) (sAddr), (UINT16) (sData))
-#define IX_OSAL_WRITE_BYTE_LE_DC(bAddr, bData) IX_OSAL_WRITE_BYTE_IO((volatile UINT8 *) (bAddr), IX_OSAL_LE_DC_XSTOBUSB((UINT8) (bData)))
-
-#if defined (IX_OSAL_BE_MAPPING)
-
-#define IX_OSAL_READ_LONG(wAddr) IX_OSAL_READ_LONG_BE(wAddr)
-#define IX_OSAL_READ_SHORT(sAddr) IX_OSAL_READ_SHORT_BE(sAddr)
-#define IX_OSAL_READ_BYTE(bAddr) IX_OSAL_READ_BYTE_BE(bAddr)
-#define IX_OSAL_WRITE_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_BE(wAddr, wData)
-#define IX_OSAL_WRITE_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_BE(sAddr, sData)
-#define IX_OSAL_WRITE_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_BE(bAddr, bData)
-
-#elif defined (IX_OSAL_LE_AC_MAPPING)
-
-#define IX_OSAL_READ_LONG(wAddr) IX_OSAL_READ_LONG_LE_AC(wAddr)
-#define IX_OSAL_READ_SHORT(sAddr) IX_OSAL_READ_SHORT_LE_AC(sAddr)
-#define IX_OSAL_READ_BYTE(bAddr) IX_OSAL_READ_BYTE_LE_AC(bAddr)
-#define IX_OSAL_WRITE_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_LE_AC(wAddr, wData)
-#define IX_OSAL_WRITE_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_LE_AC(sAddr, sData)
-#define IX_OSAL_WRITE_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_LE_AC(bAddr, bData)
-
-#elif defined (IX_OSAL_LE_DC_MAPPING)
-
-#define IX_OSAL_READ_LONG(wAddr) IX_OSAL_READ_LONG_LE_DC(wAddr)
-#define IX_OSAL_READ_SHORT(sAddr) IX_OSAL_READ_SHORT_LE_DC(sAddr)
-#define IX_OSAL_READ_BYTE(bAddr) IX_OSAL_READ_BYTE_LE_DC(bAddr)
-#define IX_OSAL_WRITE_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_LE_DC(wAddr, wData)
-#define IX_OSAL_WRITE_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_LE_DC(sAddr, sData)
-#define IX_OSAL_WRITE_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_LE_DC(bAddr, bData)
-
-#endif /* End of BE and LE coherency mode switch */
-
-
-/* Reads/writes to and from memory shared with NPEs - depends on the SDRAM coherency */
-
-#if defined (IX_SDRAM_BE)
-
-#define IX_OSAL_READ_BE_SHARED_LONG(wAddr) IX_OSAL_READ_LONG_RAW(wAddr)
-#define IX_OSAL_READ_BE_SHARED_SHORT(sAddr) IX_OSAL_READ_SHORT_RAW(sAddr)
-#define IX_OSAL_READ_BE_SHARED_BYTE(bAddr) IX_OSAL_READ_BYTE_RAW(bAddr)
-
-#define IX_OSAL_WRITE_BE_SHARED_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_RAW(wAddr, wData)
-#define IX_OSAL_WRITE_BE_SHARED_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_RAW(sAddr, sData)
-#define IX_OSAL_WRITE_BE_SHARED_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_RAW(bAddr, bData)
-
-#define IX_OSAL_SWAP_BE_SHARED_LONG(wData) (wData)
-#define IX_OSAL_SWAP_BE_SHARED_SHORT(sData) (sData)
-#define IX_OSAL_SWAP_BE_SHARED_BYTE(bData) (bData)
-
-#elif defined (IX_SDRAM_LE_ADDRESS_COHERENT)
-
-#define IX_OSAL_READ_BE_SHARED_LONG(wAddr) IX_OSAL_READ_LONG_RAW(wAddr)
-#define IX_OSAL_READ_BE_SHARED_SHORT(sAddr) IX_OSAL_READ_SHORT_RAW(IX_OSAL_SWAP_SHORT_ADDRESS(sAddr))
-#define IX_OSAL_READ_BE_SHARED_BYTE(bAddr) IX_OSAL_READ_BYTE_RAW(IX_OSAL_SWAP_BYTE_ADDRESS(bAddr))
-
-#define IX_OSAL_WRITE_BE_SHARED_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_RAW(wAddr, wData)
-#define IX_OSAL_WRITE_BE_SHARED_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_RAW(IX_OSAL_SWAP_SHORT_ADDRESS(sAddr), sData)
-#define IX_OSAL_WRITE_BE_SHARED_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_RAW(IX_OSAL_SWAP_BYTE_ADDRESS(bAddr), bData)
-
-#define IX_OSAL_SWAP_BE_SHARED_LONG(wData) (wData)
-#define IX_OSAL_SWAP_BE_SHARED_SHORT(sData) (sData)
-#define IX_OSAL_SWAP_BE_SHARED_BYTE(bData) (bData)
-
-#elif defined (IX_SDRAM_LE_DATA_COHERENT)
-
-#define IX_OSAL_READ_BE_SHARED_LONG(wAddr) IX_OSAL_SWAP_LONG(IX_OSAL_READ_LONG_RAW(wAddr))
-#define IX_OSAL_READ_BE_SHARED_SHORT(sAddr) IX_OSAL_SWAP_SHORT(IX_OSAL_READ_SHORT_RAW(sAddr))
-#define IX_OSAL_READ_BE_SHARED_BYTE(bAddr) IX_OSAL_READ_BYTE_RAW(bAddr)
-
-#define IX_OSAL_WRITE_BE_SHARED_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_RAW(wAddr, IX_OSAL_SWAP_LONG(wData))
-#define IX_OSAL_WRITE_BE_SHARED_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_RAW(sAddr, IX_OSAL_SWAP_SHORT(sData))
-#define IX_OSAL_WRITE_BE_SHARED_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_RAW(bAddr, bData)
-
-#define IX_OSAL_SWAP_BE_SHARED_LONG(wData) IX_OSAL_SWAP_LONG(wData)
-#define IX_OSAL_SWAP_BE_SHARED_SHORT(sData) IX_OSAL_SWAP_SHORT(sData)
-
-#endif
-
-
-#define IX_OSAL_COPY_BE_SHARED_LONG_ARRAY(wDestAddr, wSrcAddr, wCount) \
- { \
- UINT32 i; \
- \
- for ( i = 0 ; i < wCount ; i++ ) \
- { \
- * (((UINT32 *) wDestAddr) + i) = IX_OSAL_READ_BE_SHARED_LONG(((UINT32 *) wSrcAddr) + i); \
- }; \
- };
-
-#endif /* IxOsalMemAccess_H */
+++ /dev/null
-/**
- * @file IxOsalIxpOem.h
- *
- * @brief this file contains platform-specific defines.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsalOem_H
-#define IxOsalOem_H
-
-#include "IxOsalTypes.h"
-
-/* OS-specific header for Platform package */
-#include "IxOsalOsIxp400.h"
-
-/*
- * Platform Name
- */
-#define IX_OSAL_PLATFORM_NAME ixp400
-
-/*
- * Cache line size
- */
-#define IX_OSAL_CACHE_LINE_SIZE (32)
-
-
-/* Platform-specific fastmutex implementation */
-PUBLIC IX_STATUS ixOsalOemFastMutexTryLock (IxOsalFastMutex * mutex);
-
-/* Platform-specific init (MemMap) */
-PUBLIC IX_STATUS
-ixOsalOemInit (void);
-
-/* Platform-specific unload (MemMap) */
-PUBLIC void
-ixOsalOemUnload (void);
-
-/* Default implementations */
-
-PUBLIC UINT32
-ixOsalIxp400SharedTimestampGet (void);
-
-
-UINT32
-ixOsalIxp400SharedTimestampRateGet (void);
-
-UINT32
-ixOsalIxp400SharedSysClockRateGet (void);
-
-void
-ixOsalIxp400SharedTimeGet (IxOsalTimeval * tv);
-
-
-INT32
-ixOsalIxp400SharedLog (UINT32 level, UINT32 device, char *format,
- int arg1, int arg2, int arg3, int arg4,
- int arg5, int arg6);
-
-#endif /* IxOsal_Oem_H */
+++ /dev/null
-/**
- * @file IxOsalOsBufferMgt.h
- *
- * @brief vxworks-specific buffer management module definitions.
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#ifndef IX_OSAL_OS_BUFFER_MGT_H
-#define IX_OSAL_OS_BUFFER_MGT_H
-
-/*
- * use the defaul bufferMgt provided by OSAL framework.
- */
-#define IX_OSAL_USE_DEFAULT_BUFFER_MGT
-
-#include "IxOsalBufferMgtDefault.h"
-
-#if 0 /* FIXME */
-/* Define os-specific buffer macros for subfields */
-#define IX_OSAL_OSBUF_MDATA(osBufPtr) IX_OSAL_MBUF_MDATA(osBufPtr)
- ( ((M_BLK *) osBufPtr)->m_data )
-
-#define IX_OSAL_OSBUF_MLEN(osBufPtr) \
- ( ((M_BLK *) osBufPtr)->m_len )
-
-#define IX_OSAL_OSBUF_PKT_LEN(osBufPtr) \
- ( ((M_BLK *) osBufPtr)->m_pkthdr.len )
-
-#define IX_OSAL_OS_CONVERT_OSBUF_TO_IXPBUF( osBufPtr, ixpBufPtr) \
- { \
- IX_OSAL_MBUF_OSBUF_PTR( (IX_OSAL_MBUF *) ixpBufPtr) = (void *) osBufPtr; \
- IX_OSAL_MBUF_MDATA((IX_OSAL_MBUF *) ixpBufPtr) = IX_OSAL_OSBUF_MDATA(osBufPtr); \
- IX_OSAL_MBUF_PKT_LEN((IX_OSAL_MBUF *) ixpBufPtr) = IX_OSAL_OSBUF_PKT_LEN(osBufPtr); \
- IX_OSAL_MBUF_MLEN((IX_OSAL_MBUF *) ixpBufPtr) = IX_OSAL_OSBUF_MLEN(osBufPtr); \
- }
-
-#define IX_OSAL_OS_CONVERT_IXPBUF_TO_OSBUF( ixpBufPtr, osBufPtr) \
- { \
- if (ixpBufPtr == NULL) \
- { /* Do nothing */ } \
- else \
- { \
- (M_BLK *) osBufPtr = (M_BLK *) IX_OSAL_MBUF_OSBUF_PTR((IX_OSAL_MBUF *) ixpBufPtr); \
- if (osBufPtr == NULL) \
- { /* Do nothing */ } \
- else \
- { \
- IX_OSAL_OSBUF_MLEN(osBufPtr) =IX_OSAL_MBUF_MLEN((IX_OSAL_MBUF *) ixpBufPtr); \
- IX_OSAL_OSBUF_PKT_LEN(osBufPtr) =IX_OSAL_MBUF_PKT_LEN((IX_OSAL_MBUF *) ixpBufPtr); \
- } \
- } \
- }
-
-#endif /* FIXME */
-
-#endif /* #define IX_OSAL_OS_BUFFER_MGT_H */
+++ /dev/null
-/**
- * @file IxOsalOsIxp400.h
- *
- * @brief OS and platform specific definitions
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsalOsIxp400_H
-#define IxOsalOsIxp400_H
-
-#define BIT(x) (1<<(x))
-
-#define IXP425_EthA_BASE 0xc8009000
-#define IXP425_EthB_BASE 0xc800a000
-
-#define IXP425_PSMA_BASE 0xc8006000
-#define IXP425_PSMB_BASE 0xc8007000
-#define IXP425_PSMC_BASE 0xc8008000
-
-#define IXP425_PERIPHERAL_BASE 0xc8000000
-
-#define IXP425_QMGR_BASE 0x60000000
-#define IXP425_OSTS 0xC8005000
-
-#define IXP425_INT_LVL_NPEA 0
-#define IXP425_INT_LVL_NPEB 1
-#define IXP425_INT_LVL_NPEC 2
-
-#define IXP425_INT_LVL_QM1 3
-#define IXP425_INT_LVL_QM2 4
-
-#define IXP425_EXPANSION_BUS_BASE1 0x50000000
-#define IXP425_EXPANSION_BUS_BASE2 0x50000000
-#define IXP425_EXPANSION_BUS_CS1_BASE 0x51000000
-
-#define IXP425_EXP_CONFIG_BASE 0xC4000000
-
-/* physical addresses to be used when requesting memory with IX_OSAL_MEM_MAP */
-#define IX_OSAL_IXP400_INTC_PHYS_BASE IXP425_INTC_BASE
-#define IX_OSAL_IXP400_GPIO_PHYS_BASE IXP425_GPIO_BASE
-#define IX_OSAL_IXP400_UART1_PHYS_BASE IXP425_UART1_BASE
-#define IX_OSAL_IXP400_UART2_PHYS_BASE IXP425_UART2_BASE
-#define IX_OSAL_IXP400_ETHA_PHYS_BASE IXP425_EthA_BASE
-#define IX_OSAL_IXP400_ETHB_PHYS_BASE IXP425_EthB_BASE
-#define IX_OSAL_IXP400_NPEA_PHYS_BASE IXP425_NPEA_BASE
-#define IX_OSAL_IXP400_NPEB_PHYS_BASE IXP425_NPEB_BASE
-#define IX_OSAL_IXP400_NPEC_PHYS_BASE IXP425_NPEC_BASE
-#define IX_OSAL_IXP400_PERIPHERAL_PHYS_BASE IXP425_PERIPHERAL_BASE
-#define IX_OSAL_IXP400_QMGR_PHYS_BASE IXP425_QMGR_BASE
-#define IX_OSAL_IXP400_OSTS_PHYS_BASE IXP425_TIMER_BASE
-#define IX_OSAL_IXP400_USB_PHYS_BASE IXP425_USB_BASE
-#define IX_OSAL_IXP400_EXP_CFG_PHYS_BASE IXP425_EXP_CFG_BASE
-#define IX_OSAL_IXP400_EXP_BUS_PHYS_BASE IXP425_EXP_BUS_BASE2
-#define IX_OSAL_IXP400_EXP_BUS_BOOT_PHYS_BASE IXP425_EXP_BUS_BASE1
-#define IX_OSAL_IXP400_EXP_BUS_CS0_PHYS_BASE IXP425_EXP_BUS_CS0_BASE
-#define IX_OSAL_IXP400_EXP_BUS_CS1_PHYS_BASE IXP425_EXP_BUS_CS1_BASE
-#define IX_OSAL_IXP400_EXP_BUS_CS4_PHYS_BASE IXP425_EXP_BUS_CS4_BASE
-#define IX_OSAL_IXP400_EXP_BUS_REGS_PHYS_BASE IXP425_EXP_CFG_BASE
-#define IX_OSAL_IXP400_PCI_CFG_PHYS_BASE IXP425_PCI_CFG_BASE
-
-/* map sizes to be used when requesting memory with IX_OSAL_MEM_MAP */
-#define IX_OSAL_IXP400_QMGR_MAP_SIZE (0x4000) /**< Queue Manager map size */
-#define IX_OSAL_IXP400_PERIPHERAL_MAP_SIZE (0xC000) /**< Peripheral space map size */
-#define IX_OSAL_IXP400_UART1_MAP_SIZE (0x1000) /**< UART1 map size */
-#define IX_OSAL_IXP400_UART2_MAP_SIZE (0x1000) /**< UART2 map size */
-#define IX_OSAL_IXP400_PMU_MAP_SIZE (0x1000) /**< PMU map size */
-#define IX_OSAL_IXP400_OSTS_MAP_SIZE (0x1000) /**< OS Timers map size */
-#define IX_OSAL_IXP400_NPEA_MAP_SIZE (0x1000) /**< NPE A map size */
-#define IX_OSAL_IXP400_NPEB_MAP_SIZE (0x1000) /**< NPE B map size */
-#define IX_OSAL_IXP400_NPEC_MAP_SIZE (0x1000) /**< NPE C map size */
-#define IX_OSAL_IXP400_ETHA_MAP_SIZE (0x1000) /**< Eth A map size */
-#define IX_OSAL_IXP400_ETHB_MAP_SIZE (0x1000) /**< Eth B map size */
-#define IX_OSAL_IXP400_USB_MAP_SIZE (0x1000) /**< USB map size */
-#define IX_OSAL_IXP400_GPIO_MAP_SIZE (0x1000) /**< GPIO map size */
-#define IX_OSAL_IXP400_EXP_REG_MAP_SIZE (0x1000) /**< Exp Bus Config Registers map size */
-#define IX_OSAL_IXP400_EXP_BUS_MAP_SIZE (0x08000000) /**< Expansion bus map size */
-#define IX_OSAL_IXP400_EXP_BUS_CS0_MAP_SIZE (0x01000000) /**< CS0 map size */
-#define IX_OSAL_IXP400_EXP_BUS_CS1_MAP_SIZE (0x01000000) /**< CS1 map size */
-#define IX_OSAL_IXP400_EXP_BUS_CS4_MAP_SIZE (0x01000000) /**< CS4 map size */
-#define IX_OSAL_IXP400_PCI_CFG_MAP_SIZE (0x1000) /**< PCI Bus Config Registers map size */
-
-#define IX_OSAL_IXP400_EXP_FUSE (IXP425_EXP_CONFIG_BASE + 0x28)
-#define IX_OSAL_IXP400_ETH_NPEA_PHYS_BASE 0xC800C000
-#define IX_OSAL_IXP400_ETH_NPEA_MAP_SIZE 0x1000
-
-/*
- * Interrupt Levels
- */
-#define IX_OSAL_IXP400_NPEA_IRQ_LVL (0)
-#define IX_OSAL_IXP400_NPEB_IRQ_LVL (1)
-#define IX_OSAL_IXP400_NPEC_IRQ_LVL (2)
-#define IX_OSAL_IXP400_QM1_IRQ_LVL (3)
-#define IX_OSAL_IXP400_QM2_IRQ_LVL (4)
-#define IX_OSAL_IXP400_TIMER1_IRQ_LVL (5)
-#define IX_OSAL_IXP400_GPIO0_IRQ_LVL (6)
-#define IX_OSAL_IXP400_GPIO1_IRQ_LVL (7)
-#define IX_OSAL_IXP400_PCI_INT_IRQ_LVL (8)
-#define IX_OSAL_IXP400_PCI_DMA1_IRQ_LVL (9)
-#define IX_OSAL_IXP400_PCI_DMA2_IRQ_LVL (10)
-#define IX_OSAL_IXP400_TIMER2_IRQ_LVL (11)
-#define IX_OSAL_IXP400_USB_IRQ_LVL (12)
-#define IX_OSAL_IXP400_UART2_IRQ_LVL (13)
-#define IX_OSAL_IXP400_TIMESTAMP_IRQ_LVL (14)
-#define IX_OSAL_IXP400_UART1_IRQ_LVL (15)
-#define IX_OSAL_IXP400_WDOG_IRQ_LVL (16)
-#define IX_OSAL_IXP400_AHB_PMU_IRQ_LVL (17)
-#define IX_OSAL_IXP400_XSCALE_PMU_IRQ_LVL (18)
-#define IX_OSAL_IXP400_GPIO2_IRQ_LVL (19)
-#define IX_OSAL_IXP400_GPIO3_IRQ_LVL (20)
-#define IX_OSAL_IXP400_GPIO4_IRQ_LVL (21)
-#define IX_OSAL_IXP400_GPIO5_IRQ_LVL (22)
-#define IX_OSAL_IXP400_GPIO6_IRQ_LVL (23)
-#define IX_OSAL_IXP400_GPIO7_IRQ_LVL (24)
-#define IX_OSAL_IXP400_GPIO8_IRQ_LVL (25)
-#define IX_OSAL_IXP400_GPIO9_IRQ_LVL (26)
-#define IX_OSAL_IXP400_GPIO10_IRQ_LVL (27)
-#define IX_OSAL_IXP400_GPIO11_IRQ_LVL (28)
-#define IX_OSAL_IXP400_GPIO12_IRQ_LVL (29)
-#define IX_OSAL_IXP400_SW_INT1_IRQ_LVL (30)
-#define IX_OSAL_IXP400_SW_INT2_IRQ_LVL (31)
-
-/* USB interrupt level mask */
-#define IX_OSAL_IXP400_INT_LVL_USB IRQ_IXP425_USB
-
-/* USB IRQ */
-#define IX_OSAL_IXP400_USB_IRQ IRQ_IXP425_USB
-
-/*
- * OS name retrieval
- */
-#define IX_OSAL_OEM_OS_NAME_GET(name, limit) \
-ixOsalOsIxp400NameGet((INT8*)(name), (INT32) (limit))
-
-/*
- * OS version retrieval
- */
-#define IX_OSAL_OEM_OS_VERSION_GET(version, limit) \
-ixOsalOsIxp400VersionGet((INT8*)(version), (INT32) (limit))
-
-/*
- * Function to retrieve the OS name
- */
-PUBLIC IX_STATUS ixOsalOsIxp400NameGet(INT8* osName, INT32 maxSize);
-
-/*
- * Function to retrieve the OS version
- */
-PUBLIC IX_STATUS ixOsalOsIxp400VersionGet(INT8* osVersion, INT32 maxSize);
-
-/*
- * TimestampGet
- */
-PUBLIC UINT32 ixOsalOsIxp400TimestampGet (void);
-
-/*
- * Timestamp
- */
-#define IX_OSAL_OEM_TIMESTAMP_GET ixOsalOsIxp400TimestampGet
-
-
-/*
- * Timestamp resolution
- */
-PUBLIC UINT32 ixOsalOsIxp400TimestampResolutionGet (void);
-
-#define IX_OSAL_OEM_TIMESTAMP_RESOLUTION_GET ixOsalOsIxp400TimestampResolutionGet
-
-/*
- * Retrieves the system clock rate
- */
-PUBLIC UINT32 ixOsalOsIxp400SysClockRateGet (void);
-
-#define IX_OSAL_OEM_SYS_CLOCK_RATE_GET ixOsalOsIxp400SysClockRateGet
-
-/*
- * required by FS but is not really platform-specific.
- */
-#define IX_OSAL_OEM_TIME_GET(pTv) ixOsalTimeGet(pTv)
-
-
-
-/* linux map/unmap functions */
-PUBLIC void ixOsalLinuxMemMap (IxOsalMemoryMap * map);
-
-PUBLIC void ixOsalLinuxMemUnmap (IxOsalMemoryMap * map);
-
-
-/*********************
- * Memory map
- ********************/
-
-/* Global memmap only visible to IO MEM module */
-
-#ifdef IxOsalIoMem_C
-
-IxOsalMemoryMap ixOsalGlobalMemoryMap[] = {
- {
- /* Global BE and LE_AC map */
- IX_OSAL_STATIC_MAP, /* type */
- 0x00000000, /* physicalAddress */
- 0x30000000, /* size */
- 0x00000000, /* virtualAddress */
- NULL, /* mapFunction */
- NULL, /* unmapFunction */
- 0, /* refCount */
- IX_OSAL_BE | IX_OSAL_LE_AC,/* endianType */
- "global_low" /* name */
- },
-
- /* SDRAM LE_DC alias */
- {
- IX_OSAL_STATIC_MAP, /* type */
- 0x00000000, /* physicalAddress */
- 0x10000000, /* size */
- 0x30000000, /* virtualAddress */
- NULL, /* mapFunction */
- NULL, /* unmapFunction */
- 0, /* refCount */
- IX_OSAL_LE_DC, /* endianType */
- "sdram_dc" /* name */
- },
-
- /* QMGR LE_DC alias */
- {
- IX_OSAL_STATIC_MAP, /* type */
- 0x60000000, /* physicalAddress */
- 0x00100000, /* size */
- 0x60000000, /* virtualAddress */
- NULL, /* mapFunction */
- NULL, /* unmapFunction */
- 0, /* refCount */
- IX_OSAL_LE_DC, /* endianType */
- "qmgr_dc" /* name */
- },
-
- /* QMGR BE alias */
- {
- IX_OSAL_STATIC_MAP, /* type */
- 0x60000000, /* physicalAddress */
- 0x00100000, /* size */
- 0x60000000, /* virtualAddress */
- NULL, /* mapFunction */
- NULL, /* unmapFunction */
- 0, /* refCount */
- IX_OSAL_BE | IX_OSAL_LE_AC,/* endianType */
- "qmgr_be" /* name */
- },
-
- /* Global BE and LE_AC map */
- {
- IX_OSAL_STATIC_MAP, /* type */
- 0x40000000, /* physicalAddress */
- 0x20000000, /* size */
- 0x40000000, /* virtualAddress */
- NULL, /* mapFunction */
- NULL, /* unmapFunction */
- 0, /* refCount */
- IX_OSAL_BE | IX_OSAL_LE_AC,/* endianType */
- "Misc Cfg" /* name */
- },
-
- /* Global BE and LE_AC map */
- {
- IX_OSAL_STATIC_MAP, /* type */
- 0x70000000, /* physicalAddress */
- 0x8FFFFFFF, /* size */
- 0x70000000, /* virtualAddress */
- NULL, /* mapFunction */
- NULL, /* unmapFunction */
- 0, /* refCount */
- IX_OSAL_BE | IX_OSAL_LE_AC,/* endianType */
- "Exp Cfg" /* name */
- },
-};
-
-#endif /* IxOsalIoMem_C */
-#endif /* #define IxOsalOsIxp400_H */
+++ /dev/null
-/**
- * @file IxOsalOsIxp400CustomizedMapping.h
- *
- * @brief Set LE coherency modes for components.
- * The default setting is IX_OSAL_NO_MAPPING for LE.
- *
- *
- * By default IX_OSAL_STATIC_MEMORY_MAP is defined for all the components.
- * If any component uses a dynamic memory map it must define
- * IX_OSAL_DYNAMIC_MEMORY_MAP in its corresponding section.
- *
- *
- * @par
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsalOsIxp400CustomizedMapping_H
-#define IxOsalOsIxp400CustomizedMapping_H
-
-/*
- * only include this file in Little Endian
- */
-
-#if defined (IX_OSAL_LINUX_BE)
-#error Only include IxOsalOsIxp400CustomizedMapping.h in Little Endian
-#endif
-
- /*
- * Components don't have to be in this list if
- * the default mapping is OK.
- */
-#define ix_osal 1
-#define ix_dmaAcc 2
-#define ix_atmdAcc 3
-
-#define ix_atmsch 5
-#define ix_ethAcc 6
-#define ix_npeMh 7
-#define ix_qmgr 8
-#define ix_npeDl 9
-#define ix_atmm 10
-#define ix_hssAcc 11
-#define ix_ethDB 12
-#define ix_ethMii 13
-#define ix_timerCtrl 14
-#define ix_adsl 15
-#define ix_usb 16
-#define ix_uartAcc 17
-#define ix_featureCtrl 18
-#define ix_cryptoAcc 19
-#define ix_unloadAcc 33
-#define ix_perfProfAcc 34
-#define ix_parityENAcc 49
-#define ix_sspAcc 51
-#define ix_timeSyncAcc 52
-#define ix_i2c 53
-
-#define ix_codelets_uartAcc 21
-#define ix_codelets_timers 22
-#define ix_codelets_atm 23
-#define ix_codelets_ethAal5App 24
-#define ix_codelets_demoUtils 26
-#define ix_codelets_usb 27
-#define ix_codelets_hssAcc 28
-#define ix_codelets_dmaAcc 40
-#define ix_codelets_cryptoAcc 41
-#define ix_codelets_perfProfAcc 42
-#define ix_codelets_ethAcc 43
-#define ix_codelets_parityENAcc 54
-#define ix_codelets_timeSyncAcc 55
-
-
-#endif /* IxOsalOsIxp400CustomizedMapping_H */
-
-
-/***************************
- * osal
- ***************************/
-#if (IX_COMPONENT_NAME == ix_osal)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* osal */
-
-/***************************
- * dmaAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_dmaAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* dmaAcc */
-
-/***************************
- * atmdAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_atmdAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* atmdAcc */
-
-/***************************
- * atmsch
- ***************************/
-#if (IX_COMPONENT_NAME == ix_atmsch)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* atmsch */
-
-/***************************
- * ethAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_ethAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* ethAcc */
-
-/***************************
- * npeMh
- ***************************/
-#if (IX_COMPONENT_NAME == ix_npeMh)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* npeMh */
-
-/***************************
- * qmgr
- ***************************/
-#if (IX_COMPONENT_NAME == ix_qmgr)
-
-#define IX_OSAL_LE_DC_MAPPING
-
-#endif /* qmgr */
-
-/***************************
- * npeDl
- ***************************/
-#if (IX_COMPONENT_NAME == ix_npeDl)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* npeDl */
-
-/***************************
- * atmm
- ***************************/
-#if (IX_COMPONENT_NAME == ix_atmm)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* atmm */
-
-/***************************
- * ethMii
- ***************************/
-#if (IX_COMPONENT_NAME == ix_ethMii)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* ethMii */
-
-
-/***************************
- * adsl
- ***************************/
-#if (IX_COMPONENT_NAME == ix_adsl)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* adsl */
-
-/***************************
- * usb
- ***************************/
-#if (IX_COMPONENT_NAME == ix_usb)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* usb */
-
-/***************************
- * uartAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_uartAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* uartAcc */
-
-/***************************
- * featureCtrl
- ***************************/
-#if (IX_COMPONENT_NAME == ix_featureCtrl)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* featureCtrl */
-
-/***************************
- * cryptoAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_cryptoAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* cryptoAcc */
-
-/***************************
- * codelets_usb
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_usb)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_usb */
-
-
-/***************************
- * codelets_uartAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_uartAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_uartAcc */
-
-
-
-/***************************
- * codelets_timers
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_timers)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_timers */
-
-/***************************
- * codelets_atm
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_atm)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_atm */
-
-/***************************
- * codelets_ethAal5App
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_ethAal5App)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_ethAal5App */
-
-/***************************
- * codelets_ethAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_ethAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_ethAcc */
-
-
-/***************************
- * codelets_demoUtils
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_demoUtils)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_demoUtils */
-
-
-
-/***************************
- * perfProfAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_perfProfAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* perfProfAcc */
-
-
-/***************************
- * unloadAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_unloadAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* unloadAcc */
-
-
-
-
-
-/***************************
- * parityENAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_parityENAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* parityENAcc */
-
-/***************************
- * codelets_parityENAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_parityENAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_parityENAcc */
-
-
-
-
-/***************************
- * timeSyncAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_timeSyncAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* timeSyncAcc */
-
-
-/***************************
- * codelets_timeSyncAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_codelets_timeSyncAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* codelets_timeSyncAcc */
-
-
-
-
-/***************************
- * i2c
- ***************************/
-#if (IX_COMPONENT_NAME == ix_i2c)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* i2c */
-
-
-
-/***************************
- * sspAcc
- ***************************/
-#if (IX_COMPONENT_NAME == ix_sspAcc)
-
-#define IX_OSAL_LE_AC_MAPPING
-
-#endif /* sspAcc */
-
-
+++ /dev/null
-/**
- * @file IxOsalTypes.h
- *
- * @brief Define OSAL basic data types.
- *
- * This file contains fundamental data types used by OSAL.
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#ifndef IxOsalTypes_H
-#define IxOsalTypes_H
-
-#include <config.h>
-#include <common.h>
-
-#define __ixp42X /* sr: U-Boot needs this define */
-#define IXP425_EXP_CFG_BASE 0xC4000000
-#define diag_printf debug
-
-#undef SIMSPARCSOLARIS
-#define SIMSPARCSOLARIS 0xaffe /* sr: U-Boot gets confused with this solaris define */
-
-/*
- * Include the OS-specific type definitions
- */
-#include "IxOsalOsTypes.h"
-/**
- * @defgroup IxOsalTypes Osal basic data types.
- *
- * @brief Basic data types for Osal
- *
- * @{
- */
-
-/**
- * @brief OSAL status
- *
- * @note Possible OSAL return status include IX_SUCCESS and IX_FAIL.
- */
-typedef UINT32 IX_STATUS;
-
-/**
- * @brief VUINT32
- *
- * @note volatile UINT32
- */
-typedef volatile UINT32 VUINT32;
-
-/**
- * @brief VINT32
- *
- * @note volatile INT32
- */
-typedef volatile INT32 VINT32;
-
-
-#ifndef NUMELEMS
-#define NUMELEMS(x) (sizeof(x) / sizeof((x)[0]))
-#endif
-
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_BILLION
- *
- * @brief Alias for 1,000,000,000
- *
- */
-#define IX_OSAL_BILLION (1000000000)
-
-#ifndef TRUE
-#define TRUE 1L
-#endif
-
-#if TRUE != 1
-#error TRUE is not defined to 1
-#endif
-
-#ifndef FALSE
-#define FALSE 0L
-#endif
-
-#if FALSE != 0
-#error FALSE is not defined to 0
-#endif
-
-#ifndef NULL
-#define NULL 0L
-#endif
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_SUCCESS
- *
- * @brief Success status
- *
- */
-#ifndef IX_SUCCESS
-#define IX_SUCCESS 0L /**< #defined as 0L */
-#endif
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_FAIL
- *
- * @brief Failure status
- *
- */
-#ifndef IX_FAIL
-#define IX_FAIL 1L /**< #defined as 1L */
-#endif
-
-
-#ifndef PRIVATE
-#ifdef IX_PRIVATE_OFF
-#define PRIVATE /* nothing */
-#else
-#define PRIVATE static /**< #defined as static, except for debug builds */
-#endif /* IX_PRIVATE_OFF */
-#endif /* PRIVATE */
-
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_INLINE
- *
- * @brief Alias for __inline
- *
- */
-#ifndef IX_OSAL_INLINE
-#define IX_OSAL_INLINE __inline
-#endif /* IX_OSAL_INLINE */
-
-
-#ifndef __inline__
-#define __inline__ IX_OSAL_INLINE
-#endif
-
-
-/* Each OS can define its own PUBLIC, otherwise it will be empty. */
-#ifndef PUBLIC
-#define PUBLIC
-#endif /* PUBLIC */
-
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_INLINE_EXTERN
- *
- * @brief Alias for __inline extern
- *
- */
-#ifndef IX_OSAL_INLINE_EXTERN
-#define IX_OSAL_INLINE_EXTERN IX_OSAL_INLINE extern
-#endif
-
-/**
- * @ingroup IxOsalTypes
- * @enum IxOsalLogDevice
- * @brief This is an emum for OSAL log devices.
- */
-typedef enum
-{
- IX_OSAL_LOG_DEV_STDOUT = 0, /**< standard output (implemented by default) */
- IX_OSAL_LOG_DEV_STDERR = 1, /**< standard error (implemented */
- IX_OSAL_LOG_DEV_HEX_DISPLAY = 2, /**< hexadecimal display (not implemented) */
- IX_OSAL_LOG_DEV_ASCII_DISPLAY = 3 /**< ASCII-capable display (not implemented) */
-} IxOsalLogDevice;
-
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_LOG_ERROR
- *
- * @brief Alias for -1, used as log function error status
- *
- */
-#define IX_OSAL_LOG_ERROR (-1)
-
-/**
- * @ingroup IxOsalTypes
- * @enum IxOsalLogLevel
- * @brief This is an emum for OSAL log trace level.
- */
-typedef enum
-{
- IX_OSAL_LOG_LVL_NONE = 0, /**<No trace level */
- IX_OSAL_LOG_LVL_USER = 1, /**<Set trace level to user */
- IX_OSAL_LOG_LVL_FATAL = 2, /**<Set trace level to fatal */
- IX_OSAL_LOG_LVL_ERROR = 3, /**<Set trace level to error */
- IX_OSAL_LOG_LVL_WARNING = 4, /**<Set trace level to warning */
- IX_OSAL_LOG_LVL_MESSAGE = 5, /**<Set trace level to message */
- IX_OSAL_LOG_LVL_DEBUG1 = 6, /**<Set trace level to debug1 */
- IX_OSAL_LOG_LVL_DEBUG2 = 7, /**<Set trace level to debug2 */
- IX_OSAL_LOG_LVL_DEBUG3 = 8, /**<Set trace level to debug3 */
- IX_OSAL_LOG_LVL_ALL /**<Set trace level to all */
-} IxOsalLogLevel;
-
-
-/**
- * @ingroup IxOsalTypes
- * @brief Void function pointer prototype
- *
- * @note accepts a void pointer parameter
- * and does not return a value.
- */
-typedef void (*IxOsalVoidFnVoidPtr) (void *);
-
-typedef void (*IxOsalVoidFnPtr) (void);
-
-
-/**
- * @brief Timeval structure
- *
- * @note Contain subfields of seconds and nanoseconds..
- */
-typedef struct
-{
- UINT32 secs; /**< seconds */
- UINT32 nsecs; /**< nanoseconds */
-} IxOsalTimeval;
-
-
-/**
- * @ingroup IxOsalTypes
- * @brief IxOsalTimer
- *
- * @note OSAL timer handle
- *
- */
-typedef UINT32 IxOsalTimer;
-
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_WAIT_FOREVER
- *
- * @brief Definition for timeout forever, OS-specific.
- *
- */
-#define IX_OSAL_WAIT_FOREVER IX_OSAL_OS_WAIT_FOREVER
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_WAIT_NONE
- *
- * @brief Definition for timeout 0, OS-specific.
- *
- */
-#define IX_OSAL_WAIT_NONE IX_OSAL_OS_WAIT_NONE
-
-
-/**
- * @ingroup IxOsalTypes
- * @brief IxOsalMutex
- *
- * @note Mutex handle, OS-specific
- *
- */
-typedef IxOsalOsMutex IxOsalMutex;
-
-/**
- * @ingroup IxOsalTypes
- * @brief IxOsalFastMutex
- *
- * @note FastMutex handle, OS-specific
- *
- */
-typedef IxOsalOsFastMutex IxOsalFastMutex;
-
-/**
- * @ingroup IxOsalTypes
- * @brief IxOsalThread
- *
- * @note Thread handle, OS-specific
- *
- */
-typedef IxOsalOsThread IxOsalThread;
-
-/**
- * @ingroup IxOsalTypes
- * @brief IxOsalSemaphore
- *
- * @note Semaphore handle, OS-specific
- *
- */
-typedef IxOsalOsSemaphore IxOsalSemaphore;
-
-/**
- * @ingroup IxOsalTypes
- * @brief IxOsalMessageQueue
- *
- * @note Message Queue handle, OS-specific
- *
- */
-typedef IxOsalOsMessageQueue IxOsalMessageQueue;
-
-
-/**
- * @brief Thread Attribute
- * @note Default thread attribute
- */
-typedef struct
-{
- char *name; /**< name */
- UINT32 stackSize; /**< stack size */
- UINT32 priority; /**< priority */
-} IxOsalThreadAttr;
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_THREAD_DEFAULT_STACK_SIZE
- *
- * @brief Default thread stack size, OS-specific.
- *
- */
-#define IX_OSAL_THREAD_DEFAULT_STACK_SIZE (IX_OSAL_OS_THREAD_DEFAULT_STACK_SIZE)
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_THREAD_MAX_STACK_SIZE
- *
- * @brief Max stack size, OS-specific.
- *
- */
-#define IX_OSAL_THREAD_MAX_STACK_SIZE (IX_OSAL_OS_THREAD_MAX_STACK_SIZE)
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_DEFAULT_THREAD_PRIORITY
- *
- * @brief Default thread priority, OS-specific.
- *
- */
-#define IX_OSAL_DEFAULT_THREAD_PRIORITY (IX_OSAL_OS_DEFAULT_THREAD_PRIORITY)
-
-/**
- * @ingroup IxOsalTypes
- *
- * @def IX_OSAL_MAX_THREAD_PRIORITY
- *
- * @brief Max thread priority, OS-specific.
- *
- */
-#define IX_OSAL_MAX_THREAD_PRIORITY (IX_OSAL_OS_MAX_THREAD_PRIORITY)
-
-/**
- * @} IxOsalTypes
- */
-
-
-#endif /* IxOsalTypes_H */
+++ /dev/null
-/**
- * @file
- *
- * @brief OSAL Configuration header file
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxOsalUtilitySymbols_H
-#define IxOsalUtilitySymbols_H
-
-#include "IxOsalOsUtilitySymbols.h" /* OS-specific utility symbol definitions */
-
-#endif /* IxOsalUtilitySymbols_H */
+++ /dev/null
-/**
- * @file IxParityENAcc.h
- *
- * @author Intel Corporation
- * @date 24 Mar 2004
- *
- * @brief This file contains the public API for the IXP400 Parity Error
- * Notifier access component.
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxParityENAcc IXP400 Parity Error Notifier (IxParityENAcc) API
- *
- * @brief The public API for the Parity Error Notifier
- *
- * @{
- */
-
-#ifndef IXPARITYENACC_H
-#define IXPARITYENACC_H
-
-#ifdef __ixp46X
-
-#include "IxOsal.h"
-
-/*
- * #defines for function return types, etc.
- */
-
-/**
- * @ingroup IxParityENAcc
- *
- * @enum IxParityENAccStatus
- *
- * @brief The status as returend from the API
- */
-typedef enum /**< IxParityENAccStatus */
-{
- IX_PARITYENACC_SUCCESS = IX_SUCCESS, /**< The request is successful */
- IX_PARITYENACC_INVALID_PARAMETERS, /**< Invalid or NULL parameters passed */
- IX_PARITYENACC_NOT_INITIALISED, /**< Access layer has not been initialised before accessing the APIs */
- IX_PARITYENACC_ALREADY_INITIALISED, /**< Access layer has already been initialised */
- IX_PARITYENACC_OPERATION_FAILED, /**< Operation did not succeed due to hardware failure */
- IX_PARITYENACC_NO_PARITY /**< No parity condition exits or has already been cleared */
-} IxParityENAccStatus;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @enum IxParityENAccParityType
- *
- * @brief Odd or Even Parity Type
- */
-typedef enum /**< IxParityENAccParityType */
-{
- IX_PARITYENACC_EVEN_PARITY, /**< Even Parity */
- IX_PARITYENACC_ODD_PARITY /**< Odd Parity */
-} IxParityENAccParityType;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @enum IxParityENAccConfigOption
- *
- * @brief The parity error enable/disable configuration option
- */
-typedef enum /**< IxParityENAccConfigOption */
-{
- IX_PARITYENACC_DISABLE, /**< Disable parity error detection */
- IX_PARITYENACC_ENABLE /**< Enable parity error detection */
-} IxParityENAccConfigOption;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccNpeConfig
- *
- * @brief NPE parity detection is to be enabled/disabled
- */
-typedef struct /**< IxParityENAccNpeConfig */
-{
- IxParityENAccConfigOption ideEnabled; /**< NPE IMem, DMem and External */
- IxParityENAccParityType parityOddEven; /**< Parity - Odd or Even */
-} IxParityENAccNpeConfig ;
-
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccMcuConfig
- *
- * @brief MCU pairty detection is to be enabled/disabled
- */
-typedef struct /**< IxParityENAccMcuConfig */
-{
- IxParityENAccConfigOption singlebitDetectEnabled; /**< Single-bit parity error detection */
- IxParityENAccConfigOption singlebitCorrectionEnabled; /**< Single-bit parity error correction */
- IxParityENAccConfigOption multibitDetectionEnabled; /**< Multi-bit parity error detection */
-} IxParityENAccMcuConfig ;
-
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccEbcConfig
- *
- * @brief Expansion Bus Controller parity detection is to be enabled or disabled
- *
- * Note: All the Chip Select(s) and External Masters will have the same parity
- */
-typedef struct /**< IxParityENAccEbcConfig */
-{
- IxParityENAccConfigOption ebcCs0Enabled; /**< Expansion Bus Controller - Chip Select 0 */
- IxParityENAccConfigOption ebcCs1Enabled; /**< Expansion Bus Controller - Chip Select 1 */
- IxParityENAccConfigOption ebcCs2Enabled; /**< Expansion Bus Controller - Chip Select 2 */
- IxParityENAccConfigOption ebcCs3Enabled; /**< Expansion Bus Controller - Chip Select 3 */
- IxParityENAccConfigOption ebcCs4Enabled; /**< Expansion Bus Controller - Chip Select 4 */
- IxParityENAccConfigOption ebcCs5Enabled; /**< Expansion Bus Controller - Chip Select 5 */
- IxParityENAccConfigOption ebcCs6Enabled; /**< Expansion Bus Controller - Chip Select 6 */
- IxParityENAccConfigOption ebcCs7Enabled; /**< Expansion Bus Controller - Chip Select 7 */
- IxParityENAccConfigOption ebcExtMstEnabled; /**< External Master on Expansion bus */
- IxParityENAccParityType parityOddEven; /**< Parity - Odd or Even */
-} IxParityENAccEbcConfig ;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccHWParityConfig
- *
- * @brief Parity error configuration of the Hardware Blocks
- */
-typedef struct /**< IxParityENAccHWParityConfig */
-{
- IxParityENAccNpeConfig npeAConfig; /**< NPE A parity detection is to be enabled/disabled */
- IxParityENAccNpeConfig npeBConfig; /**< NPE B parity detection is to be enabled/disabled */
- IxParityENAccNpeConfig npeCConfig; /**< NPE C parity detection is to be enabled/disabled */
- IxParityENAccMcuConfig mcuConfig; /**< MCU pairty detection is to be enabled/disabled */
- IxParityENAccConfigOption swcpEnabled; /**< SWCP parity detection is to be enabled */
- IxParityENAccConfigOption aqmEnabled; /**< AQM parity detection is to be enabled */
- IxParityENAccEbcConfig ebcConfig; /**< Expansion Bus Controller parity detection is to be enabled/disabled */
-} IxParityENAccHWParityConfig;
-
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccNpeParityErrorStats
- *
- * @brief NPE parity error statistics
- */
-typedef struct /* IxParityENAccNpeParityErrorStats */
-{
- UINT32 parityErrorsIMem; /**< Parity errors in Instruction Memory */
- UINT32 parityErrorsDMem; /**< Parity errors in Data Memory */
- UINT32 parityErrorsExternal; /**< Parity errors in NPE External Entities */
-} IxParityENAccNpeParityErrorStats;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccMcuParityErrorStats
- *
- * @brief DDR Memory Control Unit parity error statistics
- *
- * Note: There could be two outstanding parity errors at any given time whose address
- * details captured. If there is no room for the new interrupt then it would be treated
- * as overflow parity condition.
- */
-typedef struct /* IxParityENAccMcuParityErrorStats */
-{
- UINT32 parityErrorsSingleBit; /**< Parity errors of the type Single-Bit */
- UINT32 parityErrorsMultiBit; /**< Parity errors of the type Multi-Bit */
- UINT32 parityErrorsOverflow; /**< Parity errors when more than two parity errors occured */
-} IxParityENAccMcuParityErrorStats;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccEbcParityErrorStats
- *
- * @brief Expansion Bus Controller parity error statistics
- */
-typedef struct /* IxParityENAccEbcParityErrorStats */
-{
- UINT32 parityErrorsInbound; /**< Odd bit parity errors on inbound transfers */
- UINT32 parityErrorsOutbound; /**< Odd bit parity errors on outbound transfers */
-} IxParityENAccEbcParityErrorStats;
-
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccParityErrorStats
- *
- * @brief Parity Error Statistics for the all the hardware blocks
- */
-typedef struct /**< IxParityENAccParityErrorStats */
-{
- IxParityENAccNpeParityErrorStats npeStats; /**< NPE parity error statistics */
- IxParityENAccMcuParityErrorStats mcuStats; /**< MCU parity error statistics */
- IxParityENAccEbcParityErrorStats ebcStats; /**< EBC parity error statistics */
- UINT32 swcpStats; /**< SWCP parity error statistics */
- UINT32 aqmStats; /**< AQM parity error statistics */
-} IxParityENAccParityErrorStats;
-
-
-/**
- * @ingroup IxParityENAcc
- *
- * @enum IxParityENAccParityErrorSource
- *
- * @brief The source of the parity error notification
- */
-typedef enum /**< IxParityENAccParityErrorSource */
-{
- IX_PARITYENACC_NPE_A_IMEM, /**< NPE A - Instruction memory */
- IX_PARITYENACC_NPE_A_DMEM, /**< NPE A - Data memory */
- IX_PARITYENACC_NPE_A_EXT, /**< NPE A - External Entity*/
- IX_PARITYENACC_NPE_B_IMEM, /**< NPE B - Instruction memory */
- IX_PARITYENACC_NPE_B_DMEM, /**< NPE B - Data memory */
- IX_PARITYENACC_NPE_B_EXT, /**< NPE B - External Entity*/
- IX_PARITYENACC_NPE_C_IMEM, /**< NPE C - Instruction memory */
- IX_PARITYENACC_NPE_C_DMEM, /**< NPE C - Data memory */
- IX_PARITYENACC_NPE_C_EXT, /**< NPE C - External Entity*/
- IX_PARITYENACC_SWCP, /**< SWCP */
- IX_PARITYENACC_AQM, /**< AQM */
- IX_PARITYENACC_MCU_SBIT, /**< DDR Memory Controller Unit - Single bit parity */
- IX_PARITYENACC_MCU_MBIT, /**< DDR Memory Controller Unit - Multi bit parity */
- IX_PARITYENACC_MCU_OVERFLOW, /**< DDR Memory Controller Unit - Parity errors in excess of two */
- IX_PARITYENACC_EBC_CS, /**< Expansion Bus Controller - Chip Select */
- IX_PARITYENACC_EBC_EXTMST /**< Expansion Bus Controller - External Master */
-} IxParityENAccParityErrorSource;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @enum IxParityENAccParityErrorAccess
- *
- * @brief The type of access resulting in parity error
- */
-typedef enum /**< IxParityENAccParityErrorAccess */
-{
- IX_PARITYENACC_READ, /**< Read Access */
- IX_PARITYENACC_WRITE /**< Write Access */
-} IxParityENAccParityErrorAccess;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @typedef IxParityENAccParityErrorAddress
- *
- * @brief The memory location which has parity error
- */
-typedef UINT32 IxParityENAccParityErrorAddress;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @typedef IxParityENAccParityErrorData
- *
- * @brief The data read from the memory location which has parity error
- */
-typedef UINT32 IxParityENAccParityErrorData;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @enum IxParityENAccParityErrorRequester
- *
- * @brief The requester interface through which the SDRAM memory access
- * resulted in the parity error.
- */
-typedef enum /**< IxParityENAccParityErrorRequester */
-{
- IX_PARITYENACC_MPI, /**< Direct Memory Port Interface */
- IX_PARITYENACC_AHB_BUS /**< South or North AHB Bus */
-} IxParityENAccParityErrorRequester;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @enum IxParityENAccAHBErrorMaster
- *
- * @brief The Master on the AHB bus interface whose transaction might have
- * resulted in the parity error notification to XScale.
- */
-typedef enum /**< IxParityENAccAHBErrorMaster */
-{
- IX_PARITYENACC_AHBN_MST_NPE_A, /**< NPE - A */
- IX_PARITYENACC_AHBN_MST_NPE_B, /**< NPE - B */
- IX_PARITYENACC_AHBN_MST_NPE_C, /**< NPE - C */
- IX_PARITYENACC_AHBS_MST_XSCALE, /**< XScale Bus Interface Unit */
- IX_PARITYENACC_AHBS_MST_PBC, /**< PCI Bus Controller */
- IX_PARITYENACC_AHBS_MST_EBC, /**< Expansion Bus Controller */
- IX_PARITYENACC_AHBS_MST_AHB_BRIDGE, /**< AHB Bridge */
- IX_PARITYENACC_AHBS_MST_USBH /**< USB Host Controller */
-} IxParityENAccAHBErrorMaster;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @enum IxParityENAccAHBErrorSlave
- *
- * @brief The Slave on the AHB bus interface whose transaction might have
- * resulted in the parity error notification to XScale.
- */
-typedef enum /**< IxParityENAccAHBErrorSlave */
-{
- IX_PARITYENACC_AHBN_SLV_MCU, /**< Memory Control Unit */
- IX_PARITYENACC_AHBN_SLV_AHB_BRIDGE, /**< AHB Bridge */
- IX_PARITYENACC_AHBS_SLV_MCU, /**< XScale Bus Interface Unit */
- IX_PARITYENACC_AHBS_SLV_APB_BRIDGE, /**< APB Bridge */
- IX_PARITYENACC_AHBS_SLV_AQM, /**< AQM */
- IX_PARITYENACC_AHBS_SLV_RSA, /**< RSA (Crypto Bus) */
- IX_PARITYENACC_AHBS_SLV_PBC, /**< PCI Bus Controller */
- IX_PARITYENACC_AHBS_SLV_EBC, /**< Expansion Bus Controller */
- IX_PARITYENACC_AHBS_SLV_USBH /**< USB Host Controller */
-} IxParityENAccAHBErrorSlave;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccAHBErrorTransaction
- *
- * @brief The Master and Slave on the AHB bus interface whose transaction might
- * have resulted in the parity error notification to XScale.
- *
- * NOTE: This information may be used in the data abort exception handler
- * to differentiate between the XScale and non-XScale access to the SDRAM
- * memory.
- */
-typedef struct /**< IxParityENAccAHBErrorTransaction */
-{
- IxParityENAccAHBErrorMaster ahbErrorMaster; /**< Master on AHB bus */
- IxParityENAccAHBErrorSlave ahbErrorSlave; /**< Slave on AHB bus */
-} IxParityENAccAHBErrorTransaction;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @struct IxParityENAccParityErrorContextMessage
- *
- * @brief Parity Error Context Message
- */
-typedef struct /**< IxParityENAccParityErrorContextMessage */
-{
- IxParityENAccParityErrorSource pecParitySource; /**< Source info of parity error */
- IxParityENAccParityErrorAccess pecAccessType; /**< Read or Write Access
- Read - NPE, SWCP, AQM, DDR MCU,
- Exp Bus Ctrlr (Outbound)
- Write - DDR MCU,
- Exp Bus Ctrlr (Inbound
- i.e., External Master) */
- IxParityENAccParityErrorAddress pecAddress; /**< Address faulty location
- Valid only for AQM, DDR MCU,
- Exp Bus Ctrlr */
- IxParityENAccParityErrorData pecData; /**< Data read from the faulty location
- Valid only for AQM and DDR MCU
- For DDR MCU it is the bit location
- of the Single-bit parity */
- IxParityENAccParityErrorRequester pecRequester; /**< Requester of SDRAM memory access
- Valid only for the DDR MCU */
- IxParityENAccAHBErrorTransaction ahbErrorTran; /**< Master and Slave information on the
- last AHB Error Transaction */
-} IxParityENAccParityErrorContextMessage;
-
-/**
- * @ingroup IxParityENAcc
- *
- * @typedef IxParityENAccCallback
- *
- * @brief This prototype shows the format of a callback function.
- *
- * The callback will be used to notify the parity error to the client application.
- * The callback will be registered by @ref ixParityENAccCallbackRegister.
- *
- * It will be called from an ISR when a parity error is detected and thus
- * needs to follow the interrupt callable function conventions.
- *
- */
-typedef void (*IxParityENAccCallback) (void);
-
-
-/*
- * Prototypes for interface functions.
- */
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccInit(void)
- *
- * @brief This function will initialise the IxParityENAcc component.
- *
- * This function will initialise the IxParityENAcc component. It should only be
- * called once, prior to using the IxParityENAcc component.
- *
- * <OL><LI>It initialises the internal data structures, registers the ISR that
- * will be triggered when a parity error occurs in IXP4xx silicon.</LI></OL>
- *
- * @li Re-entrant : No
- * @li ISR Callable : No
- *
- * @return @li IX_PARITYENACC_SUCCESS - Initialization is successful
- * @li IX_PARITYENACC_ALREADY_INITIALISED - The access layer has already
- * been initialized
- * @li IX_PARITYENACC_OPERATION_FAILED - The request failed because the
- * operation didn't succeed on the hardware. Refer to error trace/log
- * for details.
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccInit(void);
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccCallbackRegister (
- IxParityENAccCallback parityErrNfyCallBack)
- *
- * @brief This function will register a new callback with IxParityENAcc component.
- * It can also reregister a new callback replacing the old callback.
- *
- * @param parityErrNfyCallBack [in] - This parameter will specify the call-back
- * function supplied by the client application.
- *
- * This interface registers the user application supplied call-back handler with
- * the parity error handling access component after the init.
- *
- * The callback function will be called from an ISR that will be triggered by the
- * parity error in the IXP400 silicon.
- *
- * The following actions will be performed by this function:
- * <OL><LI>Check for the prior initialisation of the module before registering or
- * re-registering of the callback.
- * Check for parity error detection disabled before re-registration of the callback.
- * </LI></OL>
- *
- * @li Re-entrant : No
- * @li ISR Callable : No
- *
- * @return @li IX_PARITYENACC_SUCCESS - The parameters check passed and the
- * registration is successful.
- * @li IX_PARITYENACC_INVALID_PARAMETERS - Request failed due to NULL
- * parameter passed.
- * @li IX_PARITYENACC_OPERATION_FAILED - The request failed because the
- * parity error detection not yet disabled.
- * @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior to
- * the initialisation of the access layer.
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccCallbackRegister (
- IxParityENAccCallback parityErrNfyCallBack);
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccParityDetectionConfigure (
- const IxParityENAccHWParityConfig *hwParityConfig)
- *
- * @brief This interface allows the client application to enable the parity
- * error detection on the underlying hardware block.
- *
- * @param hwParityConfig [in] - Hardware blocks for which the parity error
- * detection is to be enabled or disabled.
- *
- * The client application allocates and provides the reference to the buffer.
- *
- * It will also verify whether the specific hardware block is functional or not.
- *
- * NOTE: Failure in enabling or disabling of one or more components result in
- * trace message but still returns IX_PARITYENACC_SUCCESS. Refer to the function
- * @ref ixParityENAccParityDetectionQuery on how to verify the failures while
- * enabling/disabling paritys error detection.
- *
- * It shall be invoked after the Init and CallbackRegister functions but before
- * any other function of the IxParityENAcc layer.
- *
- * @li Re-entrant : No
- * @li ISR Callable : No
- *
- * @return @li IX_PARITYENACC_SUCCESS - The parameters check passed and the
- * request to enable/disable is successful.
- * @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to
- * NULL parameter supplied.
- * @li IX_PARITYENACC_OPERATION_FAILED - The request failed because the
- * operation didn't succeed on the hardware.
- * @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior to
- * the initialisation of the access layer.
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccParityDetectionConfigure (
- const IxParityENAccHWParityConfig *hwParityConfig);
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccParityDetectionQuery (
- IxParityENAccHWParityConfig * const hwParityConfig)
- *
- * @brief This interface allows the client application to determine the
- * status of the parity error detection on the specified hardware blocks
- *
- * @param hwParityConfig [out] - Hardware blocks whose parity error detection
- * has been enabled or disabled.
- *
- * The client application allocates and provides the reference to the buffer.
- *
- * This interface can be used immediately after the interface @ref
- * ixParityENAccParityDetectionConfigure to see on which of the hardware blocks
- * the parity error detection has either been enabled or disabled based on the
- * client application request.
- *
- * @li Re-entrant : No
- * @li ISR Callable : No
- *
- * @return @li IX_PARITYENACC_SUCCESS - The parameters check passed and the
- * request to query on whether the hardware parity error detection
- * is enabled or disabled is successful.
- * @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to
- * NULL parameter or invalid values supplied.
- * @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior
- * to the initialisation of the access layer.
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccParityDetectionQuery(
- IxParityENAccHWParityConfig * const hwParityConfig);
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccParityErrorContextGet(
- IxParityENAccParityErrorContextMessage * const pecMessage)
- *
- * @brief This interface allows the client application to determine the
- * status of the parity error context on hardware block for which the
- * current parity error interrupt triggered.
- *
- * @param pecMessage [out] - The parity error context information of the
- * parity interrupt currently being process.
- *
- * The client application allocates and provides the reference to the buffer.
- *
- * Refer to the data structure @ref IxParityENAccParityErrorContextMessage
- * for details.
- *
- * The routine will will fetch the parity error context in the following
- * priority, if multiple parity errors observed.
- *
- * <pre>
- * 0 - MCU (Multi-bit and single-bit in that order)
- * 1 - NPE-A
- * 2 - NPE-B
- * 3 - NPE-C
- * 4 - SWCP
- * 5 - QM
- * 6 - EXP
- *
- * NOTE: The information provided in the @ref IxParityENAccAHBErrorTransaction
- * may be of help for the client application to decide on the course of action
- * to take. This info is taken from the Performance Monitoring Unit register
- * which records most recent error observed on the AHB bus. This information
- * might have been overwritten by some other error by the time it is retrieved.
- * </pre>
- *
- * @li Re-entrant : No
- * @li ISR Callable : Yes
- *
- * @return @li IX_PARITYENACC_SUCCESS-The parameters check passed and the
- * request to get the parity error context information is successful.
- * @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to
- * NULL parameter is passed
- * @li IX_PARITYENACC_OPERATION_FAILED - The request failed because
- * the operation didn't succeed on the hardware.
- * @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior
- * to the initialisation of the access layer.
- * @li IX_PARITYENACC_NO_PARITY - No parity condition exits or has
- * already been cleared
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccParityErrorContextGet(
- IxParityENAccParityErrorContextMessage * const pecMessage);
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccParityErrorInterruptClear (
- const IxParityENAccParityErrorContextMessage *pecMessage)
- *
- * @brief This interface helps the client application to clear off the
- * interrupt condition on the hardware block identified in the parity
- * error context message. Please refer to the table below as the operation
- * varies depending on the interrupt source.
- *
- * @param pecMessage [in] - The parity error context information of the
- * hardware block whose parity error interrupt condition is to disabled.
- *
- * The client application allocates and provides the reference to the buffer.
- *
- * <pre>
- * ****************************************************************************
- * Following actions will be taken during the interrupt clear for respective
- * hardware blocks.
- *
- * Parity Source Actions taken during Interrupt clear
- * ------------- -------------------------------------------------------
- * NPE-A Interrupt will be masked off at the interrupt controller
- * so that it will not trigger continuously.
- * Client application has to take appropriate action and
- * re-configure the parity error detection subsequently.
- * The client application will not be notified of further
- * interrupts, until the re-configuration is done using
- * @ref ixParityENAccParityDetectionConfigure.
- *
- * NPE-B Interrupt will be masked off at the interrupt controller
- * so that it will not trigger continuously.
- * Client application has to take appropriate action and
- * re-configure the parity error detection subsequently.
- * The client application will not be notified of further
- * interrupts, until the re-configuration is done using
- * @ref ixParityENAccParityDetectionConfigure.
- *
- * NPE-C Interrupt will be masked off at the interrupt controller
- * Client application has to take appropriate action and
- * re-configure the parity error detection subsequently.
- * The client application will not be notified of further
- * interrupts, until the re-configuration is done using
- * @ref ixParityENAccParityDetectionConfigure.
- *
- * SWCP Interrupt will be masked off at the interrupt controller.
- * Client application has to take appropriate action and
- * re-configure the parity error detection subsequently.
- * The client application will not be notified of further
- * interrupts, until the re-configuration is done using
- * @ref ixParityENAccParityDetectionConfigure.
- *
- * AQM Interrupt will be masked off at the interrupt controller.
- * Client application has to take appropriate action and
- * re-configure the parity error detection subsequently.
- * The client application will not be notified of further
- * interrupts, until the re-configuration is done using
- * @ref ixParityENAccParityDetectionConfigure.
- *
- * MCU Parity interrupt condition is cleared at the SDRAM MCU for
- * the following:
- * 1. Single-bit
- * 2. Multi-bit
- * 3. Overflow condition i.e., more than two parity conditions
- * occurred
- * Note that single-parity errors do not result in data abort
- * and not all data aborts caused by multi-bit parity error.
- *
- * EXP Parity interrupt condition is cleared at the expansion bus
- * controller for the following:
- * 1. External master initiated Inbound write
- * 2. Internal master (IXP400) initiated Outbound read
- * ****************************************************************************
- * </pre>
- * @li Re-entrant : No
- * @li ISR Callable : No
- *
- * @return @li IX_PARITYENACC_SUCCESS-The parameters check passed and the request
- * to clear the parity error interrupt condition is successful.
- * @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to
- * NULL parameters have been passed or contents have been
- * supplied with invalid values.
- * @li IX_PARITYENACC_OPERATION_FAILED - The request failed because
- * the operation didn't succeed on the hardware.
- * @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior
- * to the initialisation of the access layer.
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccParityErrorInterruptClear (
- const IxParityENAccParityErrorContextMessage *pecMessage);
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccStatsGet (
- IxParityENAccParityErrorStats * const ixParityErrorStats)
- *
- * @brief This interface allows the client application to retrieve parity
- * error statistics for all the hardware blocks
- *
- * @param ixParityErrorStats - [out] The statistics for all the hardware blocks.
- *
- * The client application allocates and provides the reference to the buffer.
- *
- * @li Re-entrant : No
- * @li ISR Callable : Yes
- *
- * @return @li IX_PARITYENACC_SUCCESS-The parameters check passed and the
- * request to retrieve parity error statistics for the hardware
- * block is successful.
- * @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to a
- * NULL parameter passed.
- * @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior
- * to the initialisation of the access layer.
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccStatsGet (
- IxParityENAccParityErrorStats * const ixParityErrorStats);
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccStatsShow (void)
- *
- * @brief This interface allows the client application to print all the
- * parity error statistics.
- *
- * @li Re-entrant : No
- * @li ISR Callable : No
- *
- * @return @li IX_PARITYENACC_SUCCESS - The request to show the pairty
- * error statistics is successful.
- * @li IX_PARITYENACC_NOT_INITIALISED - The operation requested
- * prior to the initialisation of the access layer.
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccStatsShow (void);
-
-/**
- * @ingroup IxParityENAcc
- *
- * @fn IxParityENAccStatus ixParityENAccStatsReset (void)
- *
- * @brief This interface allows the client application to reset all the
- * parity error statistics.
- *
- * @li Re-entrant : No
- * @li ISR Callable : No
- *
- * @return @li IX_PARITYENACC_SUCCESS - The request to reset the parity
- * error statistics is successful.
- * @li IX_PARITYENACC_NOT_INITIALISED - The operation requested
- * prior to the initialisation of the access layer.
- */
-
-PUBLIC IxParityENAccStatus ixParityENAccStatsReset (void);
-
-#endif /* IXPARITYENACC_H */
-#endif /* __ixp46X */
-
-/**
- * @} defgroup IxParityENAcc
- */
-
+++ /dev/null
-/**
- * @file IxPerfProfAcc.h
- *
- * @brief Header file for the IXP400 Perf Prof component (IxPerfProfAcc)
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxPerfProfAcc IXP400 Performance Profiling (IxPerfProfAcc) API
- *
- * @brief IXP400 Performance Profiling Utility component Public API.
- * @li NOTE: Xcycle measurement is not supported in Linux.
- *
- *
- * @{
- */
-#ifndef IXPERFPROFACC_H
-#define IXPERFPROFACC_H
-
-#include "IxOsal.h"
-
-#ifdef __linux
-#include <linux/proc_fs.h>
-#endif
-
-/*
- * Section for #define
- */
-/**
- * @ingroup IxPerfProfAcc
- *
- * @def IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES
- *
- * @brief This is the maximum number of profiling samples allowed, which can be
- * modified according to the user's discretion
- */
-#define IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES 0xFFFF
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @def IX_PERFPROF_ACC_BUS_PMU_MAX_PECS
- *
- * @brief This is the maximum number of Programmable Event Counters available.
- * This is a hardware specific and fixed value. Do not change.
- *
- */
-#define IX_PERFPROF_ACC_BUS_PMU_MAX_PECS 7
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @def IX_PERFPROF_ACC_XCYCLE_MAX_NUM_OF_MEASUREMENTS
- *
- * @brief Max number of measurement allowed. This constant is used when
- * creating storage array for Xcycle. When run in continuous mode,
- * Xcycle will wrap around and re-use buffer.
- */
-#define IX_PERFPROF_ACC_XCYCLE_MAX_NUM_OF_MEASUREMENTS 600
-
-#ifdef __linux
-/**
- * @ingroup IxPerfProfAcc
- *
- * @def IX_PERFPROF_ACC_XSCALE_PMU_SYMBOL_ACCURACY
- *
- * @brief Level of accuracy required for matching the PC Address to
- * symbol address. This is used when the XScale PMU time/event
- * sampling functions get the PC address and search for the
- * corresponding symbol address.
- */
-#define IX_PERFPROF_ACC_XSCALE_PMU_SYMBOL_ACCURACY 0xffff
-
-#endif /*__linux*/
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @def IX_PERFPROF_ACC_LOG
- *
- * @brief Mechanism for logging a formatted message for the PerfProfAcc component
- *
- * @param level UINT32 [in] - trace level
- * @param device UINT32 [in] - output device
- * @param str char* [in] - format string, similar to printf().
- * @param a UINT32 [in] - first argument to display
- * @param b UINT32 [in] - second argument to display
- * @param c UINT32 [in] - third argument to display
- * @param d UINT32 [in] - fourth argument to display
- * @param e UINT32 [in] - fifth argument to display
- * @param f UINT32 [in] - sixth argument to display
- *
- * @return none
- */
-#ifndef NDEBUG
-#define IX_PERFPROF_ACC_LOG(level, device, str, a, b, c, d, e, f)\
- (ixOsalLog (level, device, str, a, b, c, d, e, f))
-#else /*do nothing*/
-#define IX_PERFPROF_ACC_LOG(level, device, str, a, b, c, d, e, f)
-#endif /*ifdef NDEBUG */
-
-/*
- * Section for struct
- */
-
-/**
- * @brief contains summary of samples taken
- *
- * Structure contains all details of each program counter value - frequency
- * that PC occurs
- */
-typedef struct
-{
- UINT32 programCounter; /**<the program counter value of the sample*/
- UINT32 freq; /**<the frequency of the occurence of the sample*/
-} IxPerfProfAccXscalePmuSamplePcProfile;
-
-/**
- * @brief contains results of a counter
- *
- * Structure contains the results of a counter, which are split into the lower
- * and upper 32 bits of the final count
- */
-typedef struct
-{
- UINT32 lower32BitsEventCount; /**<lower 32bits value of the event counter*/
- UINT32 upper32BitsEventCount; /**<upper 32bits value of the event counter*/
-} IxPerfProfAccXscalePmuEvtCnt;
-
-/**
- * @brief contains results of counters and their overflow
- *
- * Structure contains all values of counters and associated overflows. The
- * specific event and clock counters are determined by the user
- */
-typedef struct
-{
- UINT32 clk_value; /**<current value of clock counter*/
- UINT32 clk_samples; /**<number of clock counter overflows*/
- UINT32 event1_value; /**<current value of event 1 counter*/
- UINT32 event1_samples; /**<number of event 1 counter overflows*/
- UINT32 event2_value; /**<current value of event 2 counter*/
- UINT32 event2_samples; /**<number of event 2 counter overflows*/
- UINT32 event3_value; /**<current value of event 3 counter*/
- UINT32 event3_samples; /**<number of event 3 counter overflows*/
- UINT32 event4_value; /**<current value of event 4 counter*/
- UINT32 event4_samples; /**<number of event 4 counter overflows*/
-} IxPerfProfAccXscalePmuResults;
-
-/**
- *
- * @brief Results obtained from Xcycle run
- */
-typedef struct
-{
- float maxIdlePercentage; /**<maximum percentage of Idle cycles*/
- float minIdlePercentage; /**<minimum percentage of Idle cycles*/
- float aveIdlePercentage; /**<average percentage of Idle cycles*/
- UINT32 totalMeasurements; /**<total number of measurement made */
-} IxPerfProfAccXcycleResults;
-
-/**
- *
- * @brief Results obtained from running the Bus Pmu component. The results
- * are obtained when the get functions is called.
- *
- */
-typedef struct
-{
- UINT32 statsToGetLower27Bit[IX_PERFPROF_ACC_BUS_PMU_MAX_PECS]; /**<Lower 27 Bit of counter value */
- UINT32 statsToGetUpper32Bit[IX_PERFPROF_ACC_BUS_PMU_MAX_PECS]; /**<Upper 32 Bit of counter value */
-} IxPerfProfAccBusPmuResults;
-
-/*
- * Section for enum
- */
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccBusPmuEventCounters1
- *
- * @brief Type of bus pmu events supported on PEC 1.
- *
- * Lists all bus pmu events.
- */
-typedef enum
-{
- IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_NPEA_GRANT_SELECT = 1, /**< Select North NPEA grant on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_NPEB_GRANT_SELECT, /**< Select North NPEB grant on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_NPEC_GRANT_SELECT, /**< Select North NPEC grant on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_BUS_IDLE_SELECT, /**< Select North bus idle on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_NPEA_REQ_SELECT, /**< Select North NPEA req on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_NPEB_REQ_SELECT, /**< Select North NPEB req on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_NORTH_NPEC_REQ_SELECT, /**< Select North NPEC req on PEC1*/
-
- IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_GSKT_GRANT_SELECT, /**< Select south gasket grant on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_ABB_GRANT_SELECT, /**< Select south abb grant on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_PCI_GRANT_SELECT, /**< Select south pci grant on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_APB_GRANT_SELECT, /**< Select south apb grant on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_GSKT_REQ_SELECT, /**< Select south gasket request on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_ABB_REQ_SELECT, /**< Select south abb request on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_PCI_REQ_SELECT, /**< Select south pci request on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_SOUTH_APB_REQ_SELECT, /**< Select south apb request on PEC1*/
-
- IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_0_HIT_SELECT, /**< Select sdram0 hit on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_1_HIT_SELECT, /**< Select sdram1 hit on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_2_HIT_SELECT, /**< Select sdram2 hit on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_3_HIT_SELECT, /**< Select sdram3 hit on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_4_MISS_SELECT, /**< Select sdram4 miss on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_5_MISS_SELECT, /**< Select sdram5 miss on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_6_MISS_SELECT, /**< Select sdram6 miss on PEC1*/
- IX_PERFPROF_ACC_BUS_PMU_PEC1_SDR_7_MISS_SELECT /**< Select sdram7 miss on PEC1*/
-} IxPerfProfAccBusPmuEventCounters1;
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccBusPmuEventCounters2
- *
- * @brief Type of bus pmu events supported on PEC 2.
- *
- * Lists all bus pmu events.
- */
-typedef enum
-{
- IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_NPEA_XFER_SELECT = 24, /**< Select North NPEA transfer on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_NPEB_XFER_SELECT, /**< Select North NPEB transfer on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_NPEC_XFER_SELECT, /**< Select North NPEC transfer on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_BUS_WRITE_SELECT, /**< Select North bus write on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_NPEA_OWN_SELECT, /**< Select North NPEA own on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_NPEB_OWN_SELECT, /**< Select North NPEB own on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_NORTH_NPEC_OWN_SELECT, /**< Select North NPEC own on PEC2*/
-
- IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_GSKT_XFER_SELECT, /**< Select South gasket transfer on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_ABB_XFER_SELECT, /**< Select South abb transfer on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_PCI_XFER_SELECT, /**< Select South pci transfer on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_APB_XFER_SELECT, /**< Select South apb transfer on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_GSKT_OWN_SELECT, /**< Select South gasket own on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_ABB_OWN_SELECT, /**< Select South abb own on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_PCI_OWN_SELECT, /**< Select South pci own on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_SOUTH_APB_OWN_SELECT, /**< Select South apb own transfer on PEC2*/
-
- IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_1_HIT_SELECT, /**< Select sdram1 hit on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_2_HIT_SELECT, /**< Select sdram2 hit on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_3_HIT_SELECT, /**< Select sdram3 hit on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_4_HIT_SELECT, /**< Select sdram4 hit on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_5_MISS_SELECT, /**< Select sdram5 miss on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_6_MISS_SELECT, /**< Select sdram6 miss on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_7_MISS_SELECT, /**< Select sdram7 miss on PEC2*/
- IX_PERFPROF_ACC_BUS_PMU_PEC2_SDR_0_MISS_SELECT /**< Select sdram0 miss on PEC2*/
-} IxPerfProfAccBusPmuEventCounters2;
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccBusPmuEventCounters3
- *
- * @brief Type of bus pmu events supported on PEC 3.
- *
- * Lists all bus pmu events.
- */
-typedef enum
-{
- IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_NPEA_RETRY_SELECT = 47, /**< Select north NPEA retry on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_NPEB_RETRY_SELECT, /**< Select north NPEB retry on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_NPEC_RETRY_SELECT, /**< Select north NPEC retry on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_BUS_READ_SELECT, /**< Select north bus read on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_NPEA_WRITE_SELECT, /**< Select north NPEA write on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_NPEB_WRITE_SELECT, /**< Select north NPEB write on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_NORTH_NPEC_WRITE_SELECT, /**< Select north NPEC wirte on PEC3*/
-
- IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_GSKT_RETRY_SELECT, /**< Select south gasket retry on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_ABB_RETRY_SELECT, /**< Select south abb retry on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_PCI_RETRY_SELECT, /**< Select south pci retry on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_APB_RETRY_SELECT, /**< Select south apb retry on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_GSKT_WRITE_SELECT, /**< Select south gasket write on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_ABB_WRITE_SELECT, /**< Select south abb write on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_PCI_WRITE_SELECT, /**< Select south pci write on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_SOUTH_APB_WRITE_SELECT, /**< Select south apb write on PEC3*/
-
- IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_2_HIT_SELECT, /**< Select sdram2 hit on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_3_HIT_SELECT, /**< Select sdram3 hit on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_4_HIT_SELECT, /**< Select sdram4 hit on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_5_HIT_SELECT, /**< Select sdram5 hit on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_6_MISS_SELECT, /**< Select sdram6 miss on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_7_MISS_SELECT, /**< Select sdram7 miss on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_0_MISS_SELECT, /**< Select sdram0 miss on PEC3*/
- IX_PERFPROF_ACC_BUS_PMU_PEC3_SDR_1_MISS_SELECT /**< Select sdram1 miss on PEC3*/
-} IxPerfProfAccBusPmuEventCounters3;
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccBusPmuEventCounters4
- *
- * @brief Type of bus pmu events supported on PEC 4.
- *
- * Lists all bus pmu events.
- */
-typedef enum
-{
- IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_PCI_SPLIT_SELECT = 70, /**< Select south pci split on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_EXP_SPLIT_SELECT, /**< Select south expansion split on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_APB_GRANT_SELECT, /**< Select south apb grant on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_APB_XFER_SELECT, /**< Select south apb transfer on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_GSKT_READ_SELECT, /**< Select south gasket read on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_ABB_READ_SELECT, /**< Select south abb read on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_PCI_READ_SELECT, /**< Select south pci read on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_SOUTH_APB_READ_SELECT, /**< Select south apb read on PEC4*/
-
- IX_PERFPROF_ACC_BUS_PMU_PEC4_NORTH_ABB_SPLIT_SELECT, /**< Select north abb split on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_NORTH_NPEA_REQ_SELECT, /**< Select north NPEA req on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_NORTH_NPEA_READ_SELECT, /**< Select north NPEA read on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_NORTH_NPEB_READ_SELECT, /**< Select north NPEB read on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_NORTH_NPEC_READ_SELECT, /**< Select north NPEC read on PEC4*/
-
- IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_3_HIT_SELECT, /**< Select sdram3 hit on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_4_HIT_SELECT, /**< Select sdram4 hit on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_5_HIT_SELECT, /**< Select sdram5 hit on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_6_HIT_SELECT, /**< Select sdram6 hit on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_7_MISS_SELECT, /**< Select sdram7 miss on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_0_MISS_SELECT, /**< Select sdram0 miss on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_1_MISS_SELECT, /**< Select sdram1 miss on PEC4*/
- IX_PERFPROF_ACC_BUS_PMU_PEC4_SDR_2_MISS_SELECT /**< Select sdram2 miss on PEC4*/
-} IxPerfProfAccBusPmuEventCounters4;
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccBusPmuEventCounters5
- *
- * @brief Type of bus pmu events supported on PEC 5.
- *
- * Lists all bus pmu events.
- */
-typedef enum
-{
- IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_ABB_GRANT_SELECT = 91, /**< Select south abb grant on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_ABB_XFER_SELECT, /**< Select south abb transfer on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_ABB_RETRY_SELECT, /**< Select south abb retry on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_EXP_SPLIT_SELECT, /**< Select south expansion split on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_ABB_REQ_SELECT, /**< Select south abb request on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_ABB_OWN_SELECT, /**< Select south abb own on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_SOUTH_BUS_IDLE_SELECT, /**< Select south bus idle on PEC5*/
-
- IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_GRANT_SELECT, /**< Select north NPEB grant on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_XFER_SELECT, /**< Select north NPEB transfer on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_RETRY_SELECT, /**< Select north NPEB retry on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_REQ_SELECT, /**< Select north NPEB request on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_OWN_SELECT, /**< Select north NPEB own on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_WRITE_SELECT, /**< Select north NPEB write on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_NORTH_NPEB_READ_SELECT, /**< Select north NPEB read on PEC5*/
-
- IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_4_HIT_SELECT, /**< Select north sdram4 hit on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_5_HIT_SELECT, /**< Select north sdram5 hit on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_6_HIT_SELECT, /**< Select north sdram6 hit on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_7_HIT_SELECT, /**< Select north sdram7 hit on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_0_MISS_SELECT, /**< Select north sdram0 miss on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_1_MISS_SELECT, /**< Select north sdram1 miss on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_2_MISS_SELECT, /**< Select north sdram2 miss on PEC5*/
- IX_PERFPROF_ACC_BUS_PMU_PEC5_SDR_3_MISS_SELECT /**< Select north sdram3 miss on PEC5*/
-} IxPerfProfAccBusPmuEventCounters5;
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccBusPmuEventCounters6
- *
- * @brief Type of bus pmu events supported on PEC 6.
- *
- * Lists all bus pmu events.
- */
-typedef enum
-{
- IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_PCI_GRANT_SELECT = 113, /**< Select south pci grant on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_PCI_XFER_SELECT, /**< Select south pci transfer on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_PCI_RETRY_SELECT, /**< Select south pci retry on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_PCI_SPLIT_SELECT, /**< Select south pci split on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_PCI_REQ_SELECT, /**< Select south pci request on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_PCI_OWN_SELECT, /**< Select south pci own on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_SOUTH_BUS_WRITE_SELECT, /**< Select south pci write on PEC6*/
-
- IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEC_GRANT_SELECT, /**< Select north NPEC grant on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEC_XFER_SELECT, /**< Select north NPEC transfer on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEC_RETRY_SELECT, /**< Select north NPEC retry on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEC_REQ_SELECT, /**< Select north NPEC request on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEC_OWN_SELECT, /**< Select north NPEC own on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEB_WRITE_SELECT, /**< Select north NPEB write on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_NORTH_NPEC_READ_SELECT, /**< Select north NPEC read on PEC6*/
-
- IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_5_HIT_SELECT, /**< Select sdram5 hit on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_6_HIT_SELECT, /**< Select sdram6 hit on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_7_HIT_SELECT, /**< Select sdram7 hit on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_0_HIT_SELECT, /**< Select sdram0 hit on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_1_MISS_SELECT, /**< Select sdram1 miss on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_2_MISS_SELECT, /**< Select sdram2 miss on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_3_MISS_SELECT, /**< Select sdram3 miss on PEC6*/
- IX_PERFPROF_ACC_BUS_PMU_PEC6_SDR_4_MISS_SELECT /**< Select sdram4 miss on PEC6*/
-} IxPerfProfAccBusPmuEventCounters6;
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccBusPmuEventCounters7
- *
- * @brief Type of bus pmu events supported on PEC 7.
- *
- * Lists all bus pmu events.
- */
-typedef enum
-{
- IX_PERFPROF_ACC_BUS_PMU_PEC7_SOUTH_APB_RETRY_SELECT = 135, /**< Select south apb retry on PEC7*/
- IX_PERFPROF_ACC_BUS_PMU_PEC7_SOUTH_APB_REQ_SELECT, /**< Select south apb request on PEC7*/
- IX_PERFPROF_ACC_BUS_PMU_PEC7_SOUTH_APB_OWN_SELECT, /**< Select south apb own on PEC7*/
- IX_PERFPROF_ACC_BUS_PMU_PEC7_SOUTH_BUS_READ_SELECT, /**< Select south bus read on PEC7*/
- IX_PERFPROF_ACC_BUS_PMU_PEC7_CYCLE_COUNT_SELECT /**< Select cycle count on PEC7*/
-} IxPerfProfAccBusPmuEventCounters7;
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccXscalePmuEvent
- *
- * @brief Type of xscale pmu events supported
- *
- * Lists all xscale pmu events. The maximum is a default value that the user
- * should not exceed.
- */
-typedef enum
-{
- IX_PERFPROF_ACC_XSCALE_PMU_EVENT_CACHE_MISS=0, /**< cache miss*/
- IX_PERFPROF_ACC_XSCALE_PMU_EVENT_CACHE_INSTRUCTION,/**< cache instruction*/
- IX_PERFPROF_ACC_XSCALE_PMU_EVENT_STALL, /**< event stall*/
- IX_PERFPROF_ACC_XSCALE_PMU_EVENT_INST_TLB_MISS, /**< instruction tlb miss*/
- IX_PERFPROF_ACC_XSCALE_PMU_EVENT_DATA_TLB_MISS, /**< data tlb miss*/
- IX_PERFPROF_ACC_XSCALE_PMU_EVENT_BRANCH_EXEC, /**< branch executed*/
- IX_PERFPROF_ACC_XSCALE_PMU_EVENT_BRANCH_MISPREDICT, /**<branch mispredict*/
- IX_PERFPROF_ACC_XSCALE_PMU_EVENT_INST_EXEC, /**< instruction executed*/
- IX_PERFPROF_ACC_XSCALE_PMU_EVENT_FULL_EVERYCYCLE, /**<
- *Stall - data cache
- *buffers are full.
- *This event occurs
- *every cycle where
- *condition present
- */
- IX_PERFPROF_ACC_XSCALE_PMU_EVENT_ONCE, /**<
- *Stall - data cache buffers are
- *full.This event occurs once
- *for each contiguous sequence
- */
- IX_PERFPROF_ACC_XSCALE_PMU_EVENT_DATA_CACHE_ACCESS, /**< data cache access*/
- IX_PERFPROF_ACC_XSCALE_PMU_EVENT_DATA_CACHE_MISS, /**< data cache miss*/
- IX_PERFPROF_ACC_XSCALE_PMU_EVENT_DATA_CACHE_WRITEBACK, /**<data cache
- *writeback
- */
- IX_PERFPROF_ACC_XSCALE_PMU_EVENT_SW_CHANGE_PC, /**< sw change pc*/
- IX_PERFPROF_ACC_XSCALE_PMU_EVENT_MAX /**< max value*/
-} IxPerfProfAccXscalePmuEvent;
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccStatus
- *
- * @brief Invalid Status Definitions
- *
- * These status will be used by the APIs to return to the user.
- */
-typedef enum
-{
- IX_PERFPROF_ACC_STATUS_SUCCESS = IX_SUCCESS, /**< success*/
- IX_PERFPROF_ACC_STATUS_FAIL = IX_FAIL, /**< fail*/
- IX_PERFPROF_ACC_STATUS_ANOTHER_UTIL_IN_PROGRESS,/**<another utility in
- *progress
- */
- IX_PERFPROF_ACC_STATUS_XCYCLE_MEASUREMENT_IN_PROGRESS, /**<measurement in
- *progress
- */
- IX_PERFPROF_ACC_STATUS_XCYCLE_NO_BASELINE, /**<no baseline yet*/
- IX_PERFPROF_ACC_STATUS_XCYCLE_MEASUREMENT_REQUEST_OUT_OF_RANGE, /**<
- * Measurement chosen
- * is out of range
- */
- IX_PERFPROF_ACC_STATUS_XCYCLE_PRIORITY_SET_FAIL, /**<
- * Cannot set
- * task priority
- */
- IX_PERFPROF_ACC_STATUS_XCYCLE_THREAD_CREATE_FAIL, /**<
- * Fail create thread
- */
- IX_PERFPROF_ACC_STATUS_XCYCLE_PRIORITY_RESTORE_FAIL, /**<
- *cannot restore
- *priority
- */
- IX_PERFPROF_ACC_STATUS_XCYCLE_MEASUREMENT_NOT_RUNNING, /**< xcycle not running*/
- IX_PERFPROF_ACC_STATUS_XSCALE_PMU_NUM_INVALID, /**< invalid number
- *entered
- */
- IX_PERFPROF_ACC_STATUS_XSCALE_PMU_EVENT_INVALID, /**< invalid pmu event*/
- IX_PERFPROF_ACC_STATUS_XSCALE_PMU_START_NOT_CALLED, /**<a start process
- *was not called
- *before attempting
- *a stop or results
- *get
- */
- IX_PERFPROF_ACC_STATUS_BUS_PMU_MODE_ERROR, /**< invalid mode*/
- IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC1_ERROR, /**< invalid pec1 entered*/
- IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC2_ERROR, /**< invalid pec2 entered*/
- IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC3_ERROR, /**< invalid pec3 entered*/
- IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC4_ERROR, /**< invalid pec4 entered*/
- IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC5_ERROR, /**< invalid pec5 entered*/
- IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC6_ERROR, /**< invalid pec6 entered*/
- IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC7_ERROR, /**< invalid pec7 entered*/
- IX_PERFPROF_ACC_STATUS_BUS_PMU_START_NOT_CALLED, /**<a start process
- *was not called
- *before attempting
- *a stop
- */
- IX_PERFPROF_ACC_STATUS_COMPONENT_NOT_SUPPORTED /**<Device or OS does not support component*/
-} IxPerfProfAccStatus;
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @enum IxPerfProfAccBusPmuMode
- *
- * @brief State selection of counters.
- *
- * These states will be used to determine the counters whose values are to be
- * read.
- */
-typedef enum
-{
- IX_PERFPROF_ACC_BUS_PMU_MODE_HALT=0, /**< halt state*/
- IX_PERFPROF_ACC_BUS_PMU_MODE_SOUTH, /**< south state*/
- IX_PERFPROF_ACC_BUS_PMU_MODE_NORTH, /**< north state*/
- IX_PERFPROF_ACC_BUS_PMU_MODE_SDRAM /**< SDRAM state*/
-} IxPerfProfAccBusPmuMode;
-
-/*
- * Section for prototypes interface functions
- */
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuEventCountStart(
- BOOL clkCntDiv,
- UINT32 numEvents,
- IxPerfProfAccXscalePmuEvent pmuEvent1,
- IxPerfProfAccXscalePmuEvent pmuEvent2,
- IxPerfProfAccXscalePmuEvent pmuEvent3,
- IxPerfProfAccXscalePmuEvent pmuEvent4 )
- *
- * @brief This API will start the clock and event counting
- *
- * @param clkCntDiv BOOL [in] - enables/disables the clock divider. When
- * true, the divider is enabled and the clock count will be incremented
- * by one at each 64th processor clock cycle. When false, the divider
- * is disabled and the clock count will be incremented at every
- * processor clock cycle.
- * @param numEvents UINT32 [in] - the number of PMU events that are to be
- * monitored as specified by the user. For clock counting only, this
- * is set to zero.
- * @param pmuEvent1 @ref IxPerfProfAccXscalePmuEvent [in] - the specific PMU
- * event to be monitored by counter 1
- * @param pmuEvent2 @ref IxPerfProfAccXscalePmuEvent [in] - the specific PMU
- * event to be monitored by counter 2
- * @param pmuEvent3 @ref IxPerfProfAccXscalePmuEvent [in] - the specific PMU
- * event to be monitored by counter 3
- * @param pmuEvent4 @ref IxPerfProfAccXscalePmuEvent [in] - the specific PMU
- * event to be monitored by counter 4
- *
- * This API will start the clock and xscale PMU event counting. Up to
- * 4 events can be monitored simultaneously. This API has to be called before
- * ixPerfProfAccXscalePmuEventCountStop can be called.
- *
- * @return
- * - IX_PERFPROF_ACC_STATUS_SUCCESS if clock and events counting are
- * started successfully
- * - IX_PERFPROF_ACC_STATUS_FAIL if unable to start the counting
- * - IX_PERFPROF_ACC_STATUS_XSCALE_PMU_NUM_INVALID if the number of events
- * specified is out of the valid range
- * - IX_PERFPROF_ACC_STATUS_XSCALE_PMU_EVENT_INVALID if the value of the PMU
- * event specified does not exist
- * - IX_PERFPROF_ACC_STATUS_ANOTHER_UTIL_IN_PROGRESS - another utility is
- * running
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXscalePmuEventCountStart(
- BOOL clkCntDiv,
- UINT32 numEvents,
- IxPerfProfAccXscalePmuEvent pmuEvent1,
- IxPerfProfAccXscalePmuEvent pmuEvent2,
- IxPerfProfAccXscalePmuEvent pmuEvent3,
- IxPerfProfAccXscalePmuEvent pmuEvent4 );
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuEventCountStop (
- IxPerfProfAccXscalePmuResults *eventCountStopResults)
- *
- * @brief This API will stop the clock and event counting
- *
- * @param *eventCountStopResults @ref IxPerfProfAccXscalePmuResults [out] - pointer
- * to struct containing results of counters and their overflow. It is the
- * users's responsibility to allocate the memory for this pointer.
- *
- * This API will stop the clock and xscale PMU events that are being counted.
- * The results of the clock and events count will be stored in the pointer
- * allocated by the user. It can only be called once
- * IxPerfProfAccEventCountStart has been called.
- *
- * @return
- * - IX_PERFPROF_ACC_STATUS_SUCCESS if clock and events counting are
- * stopped successfully
- * - IX_PERFPROF_ACC_STATUS_XSCALE_PMU_START_NOT_CALLED if
- * ixPerfProfAccXscalePmuEventCountStart is not called first.
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXscalePmuEventCountStop(
- IxPerfProfAccXscalePmuResults *eventCountStopResults);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuTimeSampStart(
- UINT32 samplingRate,
- BOOL clkCntDiv)
- *
- * @brief Starts the time based sampling
- *
- * @param samplingRate UINT32 [in] - sampling rate is the number of
- * clock counts before a counter overflow interrupt is generated,
- * at which, a sample is taken; the rate specified cannot be greater
- * than the counter size of 32bits or set to zero.
- * @param clkCntDiv BOOL [in] - enables/disables the clock divider. When
- * true, the divider is enabled and the clock count will be incremented
- * by one at each 64th processor clock cycle. When false, the divider
- * is disabled and the clock count will be incremented at every
- * processor clock cycle.
- *
- * This API starts the time based sampling to determine the frequency with
- * which lines of code are being executed. Sampling is done at the rate
- * specified by the user. At each sample,the value of the program counter
- * is determined. Each of these occurrences are recorded to determine the
- * frequency with which the Xscale code is being executed. This API has to be
- * called before ixPerfProfAccXscalePmuTimeSampStop can be called.
- *
- * @return
- * - IX_PERFPROF_ACC_STATUS_SUCCESS if time based sampling is started
- * successfully
- * - IX_PERFPROF_ACC_STATUS_FAIL if unable to start the sampling
- * - IX_PERFPROF_ACC_STATUS_ANOTHER_UTIL_IN_PROGRESS - another utility is
- * running
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXscalePmuTimeSampStart(
- UINT32 samplingRate,
- BOOL clkCntDiv);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuTimeSampStop(
- IxPerfProfAccXscalePmuEvtCnt *clkCount,
- IxPerfProfAccXscalePmuSamplePcProfile *timeProfile)
- *
- * @brief Stops the time based sampling
- *
- * @param *clkCount @ref IxPerfProfAccXscalePmuEvtCnt [out] - pointer to the
- * struct containing the final clock count and its overflow. It is the
- * user's responsibility to allocate the memory for this pointer.
- * @param *timeProfile @ref IxPerfProfAccXscalePmuSamplePcProfile [out] -
- * pointer to the array of profiles for each program counter value;
- * the user should set the size of the array to
- * IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES. It is the user's
- * responsibility to allocate the memory for this pointer.
- *
- * This API stops the time based sampling. The results are stored in the
- * pointers allocated by the user. It can only be called once
- * ixPerfProfAccXscalePmuTimeSampStart has been called.
- *
- * @return
- * - IX_PERFPROF_ACC_STATUS_SUCCESS if time based sampling is stopped
- * successfully
- * - IX_PERFPROF_ACC_STATUS_XSCALE_PMU_START_NOT_CALLED if
- * ixPerfProfAccXscalePmuTimeSampStart not called first
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXscalePmuTimeSampStop(
- IxPerfProfAccXscalePmuEvtCnt *clkCount,
- IxPerfProfAccXscalePmuSamplePcProfile *timeProfile);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuEventSampStart(
- UINT32 numEvents,
- IxPerfProfAccXscalePmuEvent pmuEvent1,
- UINT32 eventRate1,
- IxPerfProfAccXscalePmuEvent pmuEvent2,
- UINT32 eventRate2,
- IxPerfProfAccXscalePmuEvent pmuEvent3,
- UINT32 eventRate3,
- IxPerfProfAccXscalePmuEvent pmuEvent4,
- UINT32 eventRate4)
- *
- * @brief Starts the event based sampling
- *
- * @param numEvents UINT32 [in] - the number of PMU events that are
- * to be monitored as specified by the user. The value should be
- * between 1-4 events at a time.
- * @param pmuEvent1 @ref IxPerfProfAccXscalePmuEvent [in] - the specific PMU
- * event to be monitored by counter 1
- * @param eventRate1 UINT32 [in] - sampling rate of counter 1. The rate is
- * the number of events before a sample taken. If 0 is specified, the
- * the full counter value (0xFFFFFFFF) is used. The rate must not be
- * greater than the full counter value.
- * @param pmuEvent2 @ref IxPerfProfAccXscalePmuEvent [in] - the specific PMU
- * event to be monitored by counter 2
- * @param eventRate2 UINT32 [in] - sampling rate of counter 2. The rate is
- * the number of events before a sample taken. If 0 is specified, the
- * full counter value (0xFFFFFFFF) is used. The rate must not be
- * greater than the full counter value.
- * @param pmuEvent3 @ref IxPerfProfAccXscalePmuEvent [in] - the specific PMU
- * event to be monitored by counter 3
- * @param eventRate3 UINT32 [in] - sampling rate of counter 3. The rate is
- * the number of events before a sample taken. If 0 is specified, the
- * full counter value (0xFFFFFFFF) is used. The rate must not be
- * greater than the full counter value.
- * @param pmuEvent4 @ref IxPerfProfAccXscalePmuEvent [in] - the specific PMU
- * event to be monitored by counter 4
- * @param eventRate4 UINT32 [in] - sampling rate of counter 4. The rate is
- * the number of events before a sample taken. If 0 is specified, the
- * full counter value (0xFFFFFFFF) is used. The rate must not be
- * greater than the full counter value.
- *
- * Starts the event based sampling to determine the frequency with
- * which events are being executed. The sampling rate is the number of events,
- * as specified by the user, before a counter overflow interrupt is
- * generated. A sample is taken at each counter overflow interrupt. At each
- * sample,the value of the program counter determines the corresponding
- * location in the code. Each of these occurrences are recorded to determine
- * the frequency with which the Xscale code in each event is executed. This API
- * has to be called before ixPerfProfAccXscalePmuEventSampStop can be called.
- *
- * @return
- * - IX_PERFPROF_ACC_STATUS_SUCCESS if event based sampling is started
- * successfully
- * - IX_PERFPROF_ACC_STATUS_FAIL if unable to start the sampling
- * - IX_PERFPROF_ACC_STATUS_XSCALE_PMU_NUM_INVALID if the number of events
- * specified is out of the valid range
- * - IX_PERFPROF_ACC_STATUS_XSCALE_PMU_EVENT_INVALID if the value of the
- * PMU event specified does not exist
- * - IX_PERFPROF_ACC_STATUS_ANOTHER_UTIL_IN_PROGRESS - another utility is
- * running
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXscalePmuEventSampStart(
- UINT32 numEvents,
- IxPerfProfAccXscalePmuEvent pmuEvent1,
- UINT32 eventRate1,
- IxPerfProfAccXscalePmuEvent pmuEvent2,
- UINT32 eventRate2,
- IxPerfProfAccXscalePmuEvent pmuEvent3,
- UINT32 eventRate3,
- IxPerfProfAccXscalePmuEvent pmuEvent4,
- UINT32 eventRate4);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuEventSampStop(
- IxPerfProfAccXscalePmuSamplePcProfile *eventProfile1,
- IxPerfProfAccXscalePmuSamplePcProfile *eventProfile2,
- IxPerfProfAccXscalePmuSamplePcProfile *eventProfile3,
- IxPerfProfAccXscalePmuSamplePcProfile *eventProfile4)
- *
- * @brief Stops the event based sampling
- *
- * @param *eventProfile1 @ref IxPerfProfAccXscalePmuSamplePcProfile [out] -
- * pointer to the array of profiles for each program counter value;
- * the user should set the size of the array to
- * IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES. It is the
- * users's responsibility to allocate memory for this pointer.
- * @param *eventProfile2 @ref IxPerfProfAccXscalePmuSamplePcProfile [out] -
- * pointer to the array of profiles for each program counter value;
- * the user should set the size of the array to
- * IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES. It is the
- * users's responsibility to allocate memory for this pointer.
- * @param *eventProfile3 @ref IxPerfProfAccXscalePmuSamplePcProfile [out] -
- * pointer to the array of profiles for each program counter value;
- * the user should set the size of the array to
- * IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES. It is the
- * users's responsibility to allocate memory for this pointer.
- * @param *eventProfile4 @ref IxPerfProfAccXscalePmuSamplePcProfile [out] -
- * pointer to the array of profiles for each program counter value;
- * the user should set the size of the array to
- * IX_PERFPROF_ACC_XSCALE_PMU_MAX_PROFILE_SAMPLES. It is the
- * users's responsibility to allocate memory for this pointer.
- *
- * This API stops the event based sampling. The results are stored in the
- * pointers allocated by the user. It can only be called once
- * ixPerfProfAccEventSampStart has been called.
- *
- * @return
- * - IX_PERFPROF_ACC_STATUS_SUCCESS if event based sampling is stopped
- * successfully
- * - IX_PERFPROF_ACC_STATUS_XSCALE_PMU_START_NOT_CALLED if
- * ixPerfProfAccEventSampStart not called first.
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXscalePmuEventSampStop(
- IxPerfProfAccXscalePmuSamplePcProfile *eventProfile1,
- IxPerfProfAccXscalePmuSamplePcProfile *eventProfile2,
- IxPerfProfAccXscalePmuSamplePcProfile *eventProfile3,
- IxPerfProfAccXscalePmuSamplePcProfile *eventProfile4);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuResultsGet(IxPerfProfAccXscalePmuResults *results)
- *
- * @brief Reads the current value of the counters and their overflow
- *
- * @param *results @ref IxPerfProfAccXscalePmuResults [out] - pointer to the
- results struct. It is the user's responsibility to allocate memory
- for this pointer
- *
- * This API reads the value of all four event counters and the clock counter,
- * and the associated overflows. It does not give results associated with
- * sampling, i.e. PC and their frequencies. This API can be called at any time
- * once a process has been started. If it is called before a process has started
- * the user should be aware that the values it contains are default values and
- * might be meaningless. The values of the counters are stored in the pointer
- * allocated by the client.
- *
- * @return - none
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC void
-ixPerfProfAccXscalePmuResultsGet(IxPerfProfAccXscalePmuResults *results);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccBusPmuStart(
- IxPerfProfAccBusPmuMode mode,
- IxPerfProfAccBusPmuEventCounters1 pecEvent1,
- IxPerfProfAccBusPmuEventCounters2 pecEvent2,
- IxPerfProfAccBusPmuEventCounters3 pecEvent3,
- IxPerfProfAccBusPmuEventCounters4 pecEvent4,
- IxPerfProfAccBusPmuEventCounters5 pecEvent5,
- IxPerfProfAccBusPmuEventCounters6 pecEvent6,
- IxPerfProfAccBusPmuEventCounters7 pecEvent7)
- * @brief Initializes all the counters and selects events to be monitored.
- *
- * Function initializes all the counters and assigns the events associated
- * with the counters. Users send in the mode and events they want to count.
- * This API verifies if the combination chosen is appropriate
- * and sets all the registers accordingly. Selecting HALT mode will result
- * in an error. User should use ixPerfProfAccBusPmuStop() to HALT.
- *
- *
- * @param mode @ref IxPerfProfAccStateBusPmuMode [in] - Mode selection.
- * @param pecEvent1 @ref IxPerfProfAccBusPmuEventCounters1 [in] - Event for PEC1.
- * @param pecEvent2 @ref IxPerfProfAccBusPmuEventCounters2 [in] - Event for PEC2.
- * @param pecEvent3 @ref IxPerfProfAccBusPmuEventCounters3 [in] - Event for PEC3.
- * @param pecEvent4 @ref IxPerfProfAccBusPmuEventCounters4 [in] - Event for PEC4.
- * @param pecEvent5 @ref IxPerfProfAccBusPmuEventCounters5 [in] - Event for PEC5.
- * @param pecEvent6 @ref IxPerfProfAccBusPmuEventCounters6 [in] - Event for PEC6.
- * @param pecEvent7 @ref IxPerfProfAccBusPmuEventCounters7 [in] - Event for PEC7.
- *
- * @return
- * - IX_PERFPROF_ACC_STATUS_SUCCESS - Initialization executed
- * successfully.
- * - IX_PERFPROF_ACC_STATUS_BUS_PMU_MODE_ERROR - Error in selection of
- * mode. Only NORTH, SOUTH and SDRAM modes are allowed.
- * - IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC1_ERROR - Error in selection of
- * event for PEC1
- * - IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC2_ERROR - Error in selection of
- * event for PEC2
- * - IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC3_ERROR - Error in selection of
- * event for PEC3
- * - IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC4_ERROR - Error in selection of
- * event for PEC4
- * - IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC5_ERROR - Error in selection of
- * event for PEC5
- * - IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC6_ERROR - Error in selection of
- * event for PEC6
- * - IX_PERFPROF_ACC_STATUS_BUS_PMU_PEC7_ERROR - Error in selection of
- * event for PEC7
- * - IX_PERFPROF_ACC_STATUS_ANOTHER_UTIL_IN_PROGRESS - another utility
- * is running
- * - IX_PERFPROF_ACC_STATUS_FAIL - Failed to start because interrupt
- * service routine fails to bind.
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- **/
-PUBLIC
-IxPerfProfAccStatus ixPerfProfAccBusPmuStart (
- IxPerfProfAccBusPmuMode mode,
- IxPerfProfAccBusPmuEventCounters1 pecEvent1,
- IxPerfProfAccBusPmuEventCounters2 pecEvent2,
- IxPerfProfAccBusPmuEventCounters3 pecEvent3,
- IxPerfProfAccBusPmuEventCounters4 pecEvent4,
- IxPerfProfAccBusPmuEventCounters5 pecEvent5,
- IxPerfProfAccBusPmuEventCounters6 pecEvent6,
- IxPerfProfAccBusPmuEventCounters7 pecEvent7);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccBusPmuStop(void)
- * @brief Stops all counters.
- *
- * This function stops all the PECs by setting the halt bit in the ESR.
- *
- *
- * @return
- * - IX_PERFPROF_ACC_STATUS_SUCCESS - Counters successfully halted.
- * - IX_PERFPROF_ACC_STATUS_FAIL - Counters could'nt be halted.
- * - IX_PERFPROF_ACC_STATUS_BUS_PMU_START_NOT_CALLED - the
- * ixPerfProfAccBusPmuStart() function is not called.
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- **/
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccBusPmuStop (void);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccBusPmuResultsGet (
- IxPerfProfAccBusPmuResults *busPmuResults)
- * @brief Gets values of all counters
- *
- * This function is responsible for getting all the counter values from the
- * lower API and putting it into an array for the user.
- *
- * @param *busPmuResults @ref IxPerfProfAccBusPmuResults [out]
- * - Pointer to a structure of arrays to store all counter values.
- *
- * @return none
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- **/
-PUBLIC void
-ixPerfProfAccBusPmuResultsGet (IxPerfProfAccBusPmuResults *BusPmuResults);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccBusPmuPMSRGet (
- UINT32 *pmsrValue)
- * @brief Get values of PMSR
- *
- * This API gets the Previous Master Slave Register
- * value and returns it to the calling function. This value indicates
- * which master or slave accessed the north, south bus or sdram last.
- * The value returned by this function is a 32 bit value and is read
- * from location of an offset 0x0024 of the base value.
- *
- * The PMSR value returned indicate the following:
- * <pre>
- *
- * *************************************************************************************
- * * Bit * Name * Description *
- * * *
- * *************************************************************************************
- * * [31:18] *Reserved* *
- * *************************************************************************************
- * * [17:12] * PSS * Indicates which of the slaves on *
- * * * * ARBS was previously *
- * * * * accessed by the AHBS. *
- * * * * [000001] Expansion Bus *
- * * * * [000010] SDRAM Controller *
- * * * * [000100] PCI *
- * * * * [001000] Queue Manager *
- * * * * [010000] AHB-APB Bridge *
- * * * * [100000] Reserved *
- * *************************************************************************************
- * * [11:8] * PSN * Indicates which of the Slaves on *
- * * * * ARBN was previously *
- * * * * accessed the AHBN. *
- * * * * [0001] SDRAM Controller *
- * * * * [0010] AHB-AHB Bridge *
- * * * * [0100] Reserved *
- * * * * [1000] Reserved *
- * *************************************************************************************
- * * [7:4] * PMS * Indicates which of the Masters on *
- * * * * ARBS was previously *
- * * * * accessing the AHBS. *
- * * * * [0001] Gasket *
- * * * * [0010] AHB-AHB Bridge *
- * * * * [0100] PCI *
- * * * * [1000] APB *
- * *************************************************************************************
- * * [3:0] * PMN * Indicates which of the Masters on *
- * * * * ARBN was previously *
- * * * * accessing the AHBN. *
- * * * * [0001] NPEA *
- * * * * [0010] NPEB *
- * * * * [0100] NPEC *
- * * * * [1000] Reserved *
- * *************************************************************************************
- * </pre>
- *
- * @param *pmsrValue UINT32 [out] - Pointer to return PMSR value. Users need to
- * allocate storage for psmrValue.
- *
- * @return none
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- **/
-PUBLIC void
-ixPerfProfAccBusPmuPMSRGet (
-UINT32 *pmsrValue);
-
-
-/**
- * The APIs below are specifically used for Xcycle module.
- **/
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXcycleBaselineRun (
- UINT32 *numBaselineCycle)
- *
- * @brief Perform baseline for Xcycle
- *
- * @param *numBaselineCycle UINT32 [out] - pointer to baseline value after
- * calibration. Calling function are responsible for
- * allocating memory space for this pointer.
- *
- * Global Data :
- * - None.
- *
- * This function MUST be run before the Xcycle tool can be used. This
- * function must be run immediately when the OS boots up with no other
- * addition programs running.
- * Addition note : This API will measure the time needed to perform
- * a fix amount of CPU instructions (~ 1 second worth of loops) as a
- * highest priority task and with interrupt disabled. The time measured
- * is known as the baseline - interpreted as the shortest time
- * needed to complete the amount of CPU instructions. The baseline is
- * returned as unit of time in 66Mhz clock tick.
- *
- * @return
- * - IX_PERFPROF_ACC_STATUS_SUCCESS - successful run, result is returned
- * - IX_PERFPROF_ACC_STATUS_XCYCLE_PRIORITY_SET_FAIL - failed to change
- * task priority
- * - IX_PERFPROF_ACC_STATUS_XCYCLE_PRIORITY_RESTORE_FAIL - failed to
- * restore task priority
- * - IX_PERFPROF_ACC_STATUS_ANOTHER_UTIL_IN_PROGRESS - another utility
- * is running
- * - IX_PERFPROF_ACC_STATUS_XCYCLE_MEASUREMENT_IN_PROGRESS - Xcycle
- * tool has already started
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXcycleBaselineRun(
- UINT32 *numBaselineCycle);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXcycleStart(
- UINT32 numMeasurementsRequested);
- *
- * @brief Start the measurement
- *
- * @param numMeasurementsRequested UINT32 [in] - number of measurements
- * to perform. Value can be 0 to
- * IX_PERFPROF_ACC_XCYCLE_MAX_NUM_OF_MEASUREMENTS.
- * 0 indicate continuous measurement.
- *
- * Global Data :
- * - None.
- *
- *
- * Start the measurements immediately.
- * numMeasurementsRequested specifies number of measurements to run.
- * If numMeasurementsRequested is set to 0, the measurement will
- * be performed continuously until IxPerfProfAccXcycleStop()
- * is called.
- * It is estimated that 1 measurement takes approximately 1 second during
- * low CPU utilization, therefore 128 measurement takes approximately 128 sec.
- * When CPU utilization is high, the measurement will take longer.
- * This function spawn a task the perform the measurement and returns.
- * The measurement may continue even if this function returns.
- *
- * IMPORTANT: Under heavy CPU utilization, the task spawn by this
- * function may starve and fail to respond to stop command. User
- * may need to kill the task manually in this case.
- *
- * There are only IX_PERFPROF_ACC_XCYCLE_MAX_NUM_OF_MEASUREMENTS
- * storage available so storing is wrapped around if measurements are
- * more than IX_PERFPROF_ACC_XCYCLE_MAX_NUM_OF_MEASUREMENTS.
- *
- *
- * @return
- * - IX_PERFPROF_ACC_STATUS_SUCCESS - successful start, a thread is created
- * in the background to perform measurement.
- * - IX_PERFPROF_ACC_STATUS_XCYCLE_PRIORITY_SET_FAIL - failed to set
- * task priority
- * - IX_PERFPROF_ACC_STATUS_XCYCLE_THREAD_CREATE_FAIL - failed to create
- * thread to perform measurement.
- * - IX_PERFPROF_ACC_STATUS_XCYCLE_NO_BASELINE - baseline is not available
- * - IX_PERFPROF_ACC_STATUS_XCYCLE_MEASUREMENT_REQUEST_OUT_OF_RANGE -
- * value is larger than IX_PERFPROF_ACC_XCYCLE_MAX_NUM_OF_MEASUREMENTS
- * - IX_PERFPROF_ACC_STATUS_XCYCLE_MEASUREMENT_IN_PROGRESS - Xcycle tool
- * has already started
- * - IX_PERFPROF_ACC_STATUS_ANOTHER_UTIL_IN_PROGRESS - another utility is
- * running
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXcycleStart (
- UINT32 numMeasurementsRequested);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXcycleStop(void);
- *
- * @brief Stop the Xcycle measurement
- *
- * @param None
- *
- * Global Data :
- * - None.
- *
- * Stop Xcycle measurements immediately. If the measurements have stopped
- * or not started, return IX_PERFPROF_STATUS_XCYCLE_MEASUREMENT_NOT_RUNNING.
- * Note: This function does not stop measurement cold. The measurement thread
- * may need a few seconds to complete the last measurement. User needs to use
- * ixPerfProfAccXcycleInProgress() to determine if measurement is indeed
- * completed.
- *
- * @return
- * - IX_PERFPROF_ACC_STATUS_SUCCESS - successful measurement is stopped
- * - IX_PERFPROF_STATUS_XCYCLE_MEASUREMENT_NOT_RUNNING - no measurement running
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXcycleStop(void);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXcycleResultsGet(
- IxPerfProfAccXcycleResults *xcycleResult )
- *
- * @brief Get the results of Xcycle measurement
- *
- * @param *xcycleResult @ref IxPerfProfAccXcycleResults [out] - Pointer to
- * results of last measurements. Calling function are
- * responsible for allocating memory space for this pointer.
- *
- * Global Data :
- * - None.
- *
- * Retrieve the results of last measurement. User should use
- * ixPerfProfAccXcycleInProgress() to check if measurement is completed
- * before getting the results.
- *
- * @return
- * - IX_PERFPROF_ACC_STATUS_SUCCESS - successful
- * - IX_PERFPROF_ACC_STATUS_FAIL - result is not complete.
- * - IX_PERFPROF_ACC_STATUS_XCYCLE_NO_BASELINE - baseline is performed
- * - IX_PERFPROF_ACC_STATUS_XCYCLE_MEASUREMENT_IN_PROGRESS - Xcycle
- * tool is still running
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC IxPerfProfAccStatus
-ixPerfProfAccXcycleResultsGet (
- IxPerfProfAccXcycleResults *xcycleResult);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXcycleInProgress (void)
- *
- * @brief Check if Xcycle is running
- *
- * @param None
- * Global Data :
- * - None.
- *
- * Check if Xcycle measuring task is running.
- *
- * @return
- * - TRUE - Xcycle is running
- * - FALSE - Xcycle is not running
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-PUBLIC BOOL
-ixPerfProfAccXcycleInProgress(void);
-
-#ifdef __linux
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuTimeSampCreateProcFile
- *
- * @brief Enables proc file to call module function
- *
- * @param None
- *
- * Global Data :
- * - None.
- *
- * This function is declared globally to enable /proc directory system to call
- * and execute the function when the registered file is called. This function is not meant to
- * be called by the user.
- *
- * @return
- * - Length of data written to file.
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-int
-ixPerfProfAccXscalePmuTimeSampCreateProcFile (char *buf, char **start, off_t offset,
- int count, int *eof, void *data);
-
-/**
- * @ingroup IxPerfProfAcc
- *
- * @fn ixPerfProfAccXscalePmuEventSampCreateProcFile
- *
- * @brief Enables proc file to call module function
- *
- * @param None
- *
- * Global Data :
- * - None.
- *
- * This function is declared globally to enable /proc directory system to call
- * and execute the function when the registered file is called. This function is not meant to
- * be called by the user.
- *
- * @return
- * - Length of data written to file.
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- */
-int
-ixPerfProfAccXscalePmuEventSampCreateProcFile (char *buf, char **start, off_t offset,
- int count, int *eof, void *data);
-
-
-#endif /* ifdef __linux */
-
-#endif /* ndef IXPERFPROFACC_H */
-
-/**
- *@} defgroup IxPerfProfAcc
- */
-
-
+++ /dev/null
-/**
- * @file IxQMgr.h
- *
- * @date 30-Oct-2001
- *
- * @brief This file contains the public API of IxQMgr component.
- *
- * Some functions contained in this module are inline to achieve better
- * data-path performance. For this to work, the function definitions are
- * contained in this header file. The "normal" use of inline functions
- * is to use the inline functions in the module in which they are
- * defined. In this case these inline functions are used in external
- * modules and therefore the use of "inline extern". What this means
- * is as follows: if a function foo is declared as "inline extern" this
- * definition is only used for inlining, in no case is the function
- * compiled on its own. If the compiler cannot inline the function it
- * becomes an external reference. Therefore in IxQMgrQAccess.c all
- * inline functions are defined without the "inline extern" specifier
- * and so define the external references. In all other source files
- * including this header file, these funtions are defined as "inline
- * extern".
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-/* ------------------------------------------------------
- Doxygen group definitions
- ------------------------------------------------------ */
-/**
- * @defgroup IxQMgrAPI IXP400 Queue Manager (IxQMgr) API
- *
- * @brief The public API for the IXP400 QMgr component.
- *
- * IxQMgr is a low level interface to the AHB Queue Manager
- *
- * @{
- */
-
-#ifndef IXQMGR_H
-#define IXQMGR_H
-
-/*
- * User defined include files
- */
-
-#include "IxOsal.h"
-
-/*
- * Define QMgr's IoMem macros, in DC mode if in LE
- * regular if in BE. (Note: For Linux LSP gold release
- * may need to adjust mode.
- */
-#if defined (__BIG_ENDIAN)
-
-#define IX_QMGR_INLINE_READ_LONG IX_OSAL_READ_LONG_BE
-#define IX_QMGR_INLINE_WRITE_LONG IX_OSAL_WRITE_LONG_BE
-
-#else
-
-#define IX_QMGR_INLINE_READ_LONG IX_OSAL_READ_LONG_LE_DC
-#define IX_QMGR_INLINE_WRITE_LONG IX_OSAL_WRITE_LONG_LE_DC
-
-#endif
-
-/*
- * #defines and macros
- */
-
-/**
-*
-* @ingroup IxQMgrAPI
-*
-* @def IX_QMGR_INLINE
-*
-* @brief Inline definition, for inlining of Queue Access functions on API
-*
-* Please read the header information in this file for more details on the
-* use of function inlining in this component.
-*
-*/
-
-#ifndef __wince
-
-#ifdef IXQMGRQACCESS_C
-/* If IXQMGRQACCESS_C is set then the IxQmgrQAccess.c is including this file
- and must instantiate a concrete definition for each inlineable API function
- whether or not that function actually gets inlined. */
-# ifdef NO_INLINE_APIS
-# undef NO_INLINE_APIS
-# endif
-# define IX_QMGR_INLINE /* Empty Define */
-#else
-# ifndef NO_INLINE_APIS
-# define IX_QMGR_INLINE IX_OSAL_INLINE_EXTERN
-# else
-# define IX_QMGR_INLINE /* Empty Define */
-# endif
-#endif
-
-#else /* ndef __wince */
-
-# ifndef NO_INLINE_APIS
-# define NO_INLINE_APIS
-# endif
-# define IX_QMGR_INLINE
-
-#endif
-
-
-/**
-*
-* @ingroup IxQMgrAPI
-*
-* @def IX_QMGR_MAX_NUM_QUEUES
-*
-* @brief Number of queues supported by the AQM.
-*
-* This constant is used to indicate the number of AQM queues
-*
-*/
-#define IX_QMGR_MAX_NUM_QUEUES 64
-
-/**
-*
-* @ingroup IxQMgrAPI
-*
-* @def IX_QMGR_MIN_QID
-*
-* @brief Minimum queue identifier.
-*
-* This constant is used to indicate the smallest queue identifier
-*
-*/
-#define IX_QMGR_MIN_QID IX_QMGR_QUEUE_0
-
-/**
-*
-* @ingroup IxQMgrAPI
-*
-* @def IX_QMGR_MAX_QID
-*
-* @brief Maximum queue identifier.
-*
-* This constant is used to indicate the largest queue identifier
-*
-*/
-#define IX_QMGR_MAX_QID IX_QMGR_QUEUE_63
-
-/**
-*
-* @ingroup IxQMgrAPI
-*
-* @def IX_QMGR_MIN_QUEUPP_QID
-*
-* @brief Minimum queue identifier for reduced functionality queues.
-*
-* This constant is used to indicate Minimum queue identifier for reduced
-* functionality queues
-*
-*/
-#define IX_QMGR_MIN_QUEUPP_QID 32
-
-/**
-*
-* @ingroup IxQMgrAPI
-*
-* @def IX_QMGR_MAX_QNAME_LEN
-*
-* @brief Maximum queue name length.
-*
-* This constant is used to indicate the maximum null terminated string length
-* (excluding '\0') for a queue name
-*
-*/
-#define IX_QMGR_MAX_QNAME_LEN 16
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_WARNING
- *
- * @brief Warning return code.
- *
- * Execution complete, but there is a special case to handle
- *
- */
-#define IX_QMGR_WARNING 2
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_PARAMETER_ERROR
- *
- * @brief Parameter error return code (NULL pointer etc..).
- *
- * parameter error out of range/invalid
- *
- */
-#define IX_QMGR_PARAMETER_ERROR 3
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_INVALID_Q_ENTRY_SIZE
- *
- * @brief Invalid entry size return code.
- *
- * Invalid queue entry size for a queue read/write
- *
- */
-#define IX_QMGR_INVALID_Q_ENTRY_SIZE 4
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_INVALID_Q_ID
- *
- * @brief Invalid queue identifier return code.
- *
- * Invalid queue id, not in range 0-63
- *
- */
-#define IX_QMGR_INVALID_Q_ID 5
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_INVALID_CB_ID
- *
- * @brief Invalid callback identifier return code.
- *
- * Invalid callback id
- */
-#define IX_QMGR_INVALID_CB_ID 6
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_CB_ALREADY_SET
- *
- * @brief Callback set error return code.
- *
- * The specified callback has already been for this queue
- *
- */
-#define IX_QMGR_CB_ALREADY_SET 7
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_NO_AVAILABLE_SRAM
- *
- * @brief Sram consumed return code.
- *
- * All AQM Sram is consumed by queue configuration
- *
- */
-#define IX_QMGR_NO_AVAILABLE_SRAM 8
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_INVALID_INT_SOURCE_ID
- *
- * @brief Invalid queue interrupt source identifier return code.
- *
- * Invalid queue interrupt source given for notification enable
- */
-#define IX_QMGR_INVALID_INT_SOURCE_ID 9
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_INVALID_QSIZE
- *
- * @brief Invalid queue size error code.
- *
- * Invalid queue size not one of 16,32, 64, 128
- *
- *
- */
-#define IX_QMGR_INVALID_QSIZE 10
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_INVALID_Q_WM
- *
- * @brief Invalid queue watermark return code.
- *
- * Invalid queue watermark given for watermark set
- */
-#define IX_QMGR_INVALID_Q_WM 11
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_Q_NOT_CONFIGURED
- *
- * @brief Queue not configured return code.
- *
- * Returned to the client when a function has been called on an unconfigured
- * queue
- *
- */
-#define IX_QMGR_Q_NOT_CONFIGURED 12
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_Q_ALREADY_CONFIGURED
- *
- * @brief Queue already configured return code.
- *
- * Returned to client to indicate that a queue has already been configured
- */
-#define IX_QMGR_Q_ALREADY_CONFIGURED 13
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_Q_UNDERFLOW
- *
- * @brief Underflow return code.
- *
- * Underflow on a queue read has occurred
- *
- */
-#define IX_QMGR_Q_UNDERFLOW 14
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_Q_OVERFLOW
- *
- * @brief Overflow return code.
- *
- * Overflow on a queue write has occurred
- *
- */
-#define IX_QMGR_Q_OVERFLOW 15
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_Q_INVALID_PRIORITY
- *
- * @brief Invalid priority return code.
- *
- * Invalid priority, not one of 0,1,2
- */
-#define IX_QMGR_Q_INVALID_PRIORITY 16
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_ENTRY_INDEX_OUT_OF_BOUNDS
- *
- * @brief Entry index out of bounds return code.
- *
- * Entry index is greater than number of entries in queue.
- */
-#define IX_QMGR_ENTRY_INDEX_OUT_OF_BOUNDS 17
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def ixQMgrDispatcherLoopRun
- *
- * @brief Map old function name ixQMgrDispatcherLoopRun ()
- * to @ref ixQMgrDispatcherLoopRunA0 ().
- *
- */
-#define ixQMgrDispatcherLoopRun ixQMgrDispatcherLoopRunA0
-
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @def IX_QMGR_QUEUE
- *
- * @brief Definition of AQM queue numbers
- *
- */
-#define IX_QMGR_QUEUE_0 (0) /**< Queue Number 0 */
-#define IX_QMGR_QUEUE_1 (1) /**< Queue Number 1 */
-#define IX_QMGR_QUEUE_2 (2) /**< Queue Number 2 */
-#define IX_QMGR_QUEUE_3 (3) /**< Queue Number 3 */
-#define IX_QMGR_QUEUE_4 (4) /**< Queue Number 4 */
-#define IX_QMGR_QUEUE_5 (5) /**< Queue Number 5 */
-#define IX_QMGR_QUEUE_6 (6) /**< Queue Number 6 */
-#define IX_QMGR_QUEUE_7 (7) /**< Queue Number 7 */
-#define IX_QMGR_QUEUE_8 (8) /**< Queue Number 8 */
-#define IX_QMGR_QUEUE_9 (9) /**< Queue Number 9 */
-#define IX_QMGR_QUEUE_10 (10) /**< Queue Number 10 */
-#define IX_QMGR_QUEUE_11 (11) /**< Queue Number 11 */
-#define IX_QMGR_QUEUE_12 (12) /**< Queue Number 12 */
-#define IX_QMGR_QUEUE_13 (13) /**< Queue Number 13 */
-#define IX_QMGR_QUEUE_14 (14) /**< Queue Number 14 */
-#define IX_QMGR_QUEUE_15 (15) /**< Queue Number 15 */
-#define IX_QMGR_QUEUE_16 (16) /**< Queue Number 16 */
-#define IX_QMGR_QUEUE_17 (17) /**< Queue Number 17 */
-#define IX_QMGR_QUEUE_18 (18) /**< Queue Number 18 */
-#define IX_QMGR_QUEUE_19 (19) /**< Queue Number 19 */
-#define IX_QMGR_QUEUE_20 (20) /**< Queue Number 20 */
-#define IX_QMGR_QUEUE_21 (21) /**< Queue Number 21 */
-#define IX_QMGR_QUEUE_22 (22) /**< Queue Number 22 */
-#define IX_QMGR_QUEUE_23 (23) /**< Queue Number 23 */
-#define IX_QMGR_QUEUE_24 (24) /**< Queue Number 24 */
-#define IX_QMGR_QUEUE_25 (25) /**< Queue Number 25 */
-#define IX_QMGR_QUEUE_26 (26) /**< Queue Number 26 */
-#define IX_QMGR_QUEUE_27 (27) /**< Queue Number 27 */
-#define IX_QMGR_QUEUE_28 (28) /**< Queue Number 28 */
-#define IX_QMGR_QUEUE_29 (29) /**< Queue Number 29 */
-#define IX_QMGR_QUEUE_30 (30) /**< Queue Number 30 */
-#define IX_QMGR_QUEUE_31 (31) /**< Queue Number 31 */
-#define IX_QMGR_QUEUE_32 (32) /**< Queue Number 32 */
-#define IX_QMGR_QUEUE_33 (33) /**< Queue Number 33 */
-#define IX_QMGR_QUEUE_34 (34) /**< Queue Number 34 */
-#define IX_QMGR_QUEUE_35 (35) /**< Queue Number 35 */
-#define IX_QMGR_QUEUE_36 (36) /**< Queue Number 36 */
-#define IX_QMGR_QUEUE_37 (37) /**< Queue Number 37 */
-#define IX_QMGR_QUEUE_38 (38) /**< Queue Number 38 */
-#define IX_QMGR_QUEUE_39 (39) /**< Queue Number 39 */
-#define IX_QMGR_QUEUE_40 (40) /**< Queue Number 40 */
-#define IX_QMGR_QUEUE_41 (41) /**< Queue Number 41 */
-#define IX_QMGR_QUEUE_42 (42) /**< Queue Number 42 */
-#define IX_QMGR_QUEUE_43 (43) /**< Queue Number 43 */
-#define IX_QMGR_QUEUE_44 (44) /**< Queue Number 44 */
-#define IX_QMGR_QUEUE_45 (45) /**< Queue Number 45 */
-#define IX_QMGR_QUEUE_46 (46) /**< Queue Number 46 */
-#define IX_QMGR_QUEUE_47 (47) /**< Queue Number 47 */
-#define IX_QMGR_QUEUE_48 (48) /**< Queue Number 48 */
-#define IX_QMGR_QUEUE_49 (49) /**< Queue Number 49 */
-#define IX_QMGR_QUEUE_50 (50) /**< Queue Number 50 */
-#define IX_QMGR_QUEUE_51 (51) /**< Queue Number 51 */
-#define IX_QMGR_QUEUE_52 (52) /**< Queue Number 52 */
-#define IX_QMGR_QUEUE_53 (53) /**< Queue Number 53 */
-#define IX_QMGR_QUEUE_54 (54) /**< Queue Number 54 */
-#define IX_QMGR_QUEUE_55 (55) /**< Queue Number 55 */
-#define IX_QMGR_QUEUE_56 (56) /**< Queue Number 56 */
-#define IX_QMGR_QUEUE_57 (57) /**< Queue Number 57 */
-#define IX_QMGR_QUEUE_58 (58) /**< Queue Number 58 */
-#define IX_QMGR_QUEUE_59 (59) /**< Queue Number 59 */
-#define IX_QMGR_QUEUE_60 (60) /**< Queue Number 60 */
-#define IX_QMGR_QUEUE_61 (61) /**< Queue Number 61 */
-#define IX_QMGR_QUEUE_62 (62) /**< Queue Number 62 */
-#define IX_QMGR_QUEUE_63 (63) /**< Queue Number 63 */
-#define IX_QMGR_QUEUE_INVALID (64) /**< AQM Queue Number Delimiter */
-
-
-/*
- * Typedefs
- */
-
-/**
- * @typedef IxQMgrQId
- *
- * @ingroup IxQMgrAPI
- *
- * @brief Used in the API to identify the AQM queues.
- *
- */
-typedef int IxQMgrQId;
-
-/**
- * @typedef IxQMgrQStatus
- *
- * @ingroup IxQMgrAPI
- *
- * @brief Queue status.
- *
- * A queues status is defined by its relative fullness or relative emptiness.
- * Each of the queues 0-31 have Nearly Empty, Nearly Full, Empty, Full,
- * Underflow and Overflow status flags. Queues 32-63 have just Nearly Empty and
- * Full status flags.
- * The flags bit positions are outlined below:
- *
- * OF - bit-5<br>
- * UF - bit-4<br>
- * F - bit-3<br>
- * NF - bit-2<br>
- * NE - bit-1<br>
- * E - bit-0<br>
- *
- */
-typedef UINT32 IxQMgrQStatus;
-
-/**
- * @enum IxQMgrQStatusMask
- *
- * @ingroup IxQMgrAPI
- *
- * @brief Queue status mask.
- *
- * Masks for extracting the individual status flags from the IxQMgrStatus
- * word.
- *
- */
-typedef enum
-{
- IX_QMGR_Q_STATUS_E_BIT_MASK = 0x1,
- IX_QMGR_Q_STATUS_NE_BIT_MASK = 0x2,
- IX_QMGR_Q_STATUS_NF_BIT_MASK = 0x4,
- IX_QMGR_Q_STATUS_F_BIT_MASK = 0x8,
- IX_QMGR_Q_STATUS_UF_BIT_MASK = 0x10,
- IX_QMGR_Q_STATUS_OF_BIT_MASK = 0x20
-} IxQMgrQStatusMask;
-
-/**
- * @enum IxQMgrSourceId
- *
- * @ingroup IxQMgrAPI
- *
- * @brief Queue interrupt source select.
- *
- * This enum defines the different source conditions on a queue that result in
- * an interupt being fired by the AQM. Interrupt source is configurable for
- * queues 0-31 only. The interrupt source for queues 32-63 is hardwired to the
- * NE(Nearly Empty) status flag.
- *
- */
-typedef enum
-{
- IX_QMGR_Q_SOURCE_ID_E = 0, /**< Queue Empty due to last read */
- IX_QMGR_Q_SOURCE_ID_NE, /**< Queue Nearly Empty due to last read */
- IX_QMGR_Q_SOURCE_ID_NF, /**< Queue Nearly Full due to last write */
- IX_QMGR_Q_SOURCE_ID_F, /**< Queue Full due to last write */
- IX_QMGR_Q_SOURCE_ID_NOT_E, /**< Queue Not Empty due to last write */
- IX_QMGR_Q_SOURCE_ID_NOT_NE, /**< Queue Not Nearly Empty due to last write */
- IX_QMGR_Q_SOURCE_ID_NOT_NF, /**< Queue Not Nearly Full due to last read */
- IX_QMGR_Q_SOURCE_ID_NOT_F /**< Queue Not Full due to last read */
-} IxQMgrSourceId;
-
-/**
- * @enum IxQMgrQEntrySizeInWords
- *
- * @ingroup IxQMgrAPI
- *
- * @brief QMgr queue entry sizes.
- *
- * The entry size of a queue specifies the size of a queues entry in words.
- *
- */
-typedef enum
-{
- IX_QMGR_Q_ENTRY_SIZE1 = 1, /**< 1 word entry */
- IX_QMGR_Q_ENTRY_SIZE2 = 2, /**< 2 word entry */
- IX_QMGR_Q_ENTRY_SIZE4 = 4 /**< 4 word entry */
-} IxQMgrQEntrySizeInWords;
-
-/**
- * @enum IxQMgrQSizeInWords
- *
- * @ingroup IxQMgrAPI
- *
- * @brief QMgr queue sizes.
- *
- * These values define the allowed queue sizes for AQM queue. The sizes are
- * specified in words.
- *
- */
-typedef enum
-{
- IX_QMGR_Q_SIZE16 = 16, /**< 16 word buffer */
- IX_QMGR_Q_SIZE32 = 32, /**< 32 word buffer */
- IX_QMGR_Q_SIZE64 = 64, /**< 64 word buffer */
- IX_QMGR_Q_SIZE128 = 128, /**< 128 word buffer */
- IX_QMGR_Q_SIZE_INVALID = 129 /**< Insure that this is greater than largest
- * queue size supported by the hardware
- */
-} IxQMgrQSizeInWords;
-
-/**
- * @enum IxQMgrWMLevel
- *
- * @ingroup IxQMgrAPI
- *
- * @brief QMgr watermark levels.
- *
- * These values define the valid watermark levels(in ENTRIES) for queues. Each
- * queue 0-63 have configurable Nearly full and Nearly empty watermarks. For
- * queues 32-63 the Nearly full watermark has NO EFFECT.
- * If the Nearly full watermark is set to IX_QMGR_Q_WM_LEVEL16 this means that
- * the nearly full flag will be set by the hardware when there are >= 16 empty
- * entries in the specified queue.
- * If the Nearly empty watermark is set to IX_QMGR_Q_WM_LEVEL16 this means that
- * the Nearly empty flag will be set by the hardware when there are <= 16 full
- * entries in the specified queue.
- */
-typedef enum
-{
- IX_QMGR_Q_WM_LEVEL0 = 0, /**< 0 entry watermark */
- IX_QMGR_Q_WM_LEVEL1 = 1, /**< 1 entry watermark */
- IX_QMGR_Q_WM_LEVEL2 = 2, /**< 2 entry watermark */
- IX_QMGR_Q_WM_LEVEL4 = 4, /**< 4 entry watermark */
- IX_QMGR_Q_WM_LEVEL8 = 8, /**< 8 entry watermark */
- IX_QMGR_Q_WM_LEVEL16 = 16, /**< 16 entry watermark */
- IX_QMGR_Q_WM_LEVEL32 = 32, /**< 32 entry watermark */
- IX_QMGR_Q_WM_LEVEL64 = 64 /**< 64 entry watermark */
-} IxQMgrWMLevel;
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @enum IxQMgrDispatchGroup
- *
- * @brief QMgr dispatch group select identifiers.
- *
- * This enum defines the groups over which the dispatcher will process when
- * called. One of the enum values must be used as a input to
- * @a ixQMgrDispatcherLoopRunA0, @a ixQMgrDispatcherLoopRunB0
- * or @a ixQMgrDispatcherLoopRunB0LLP.
- *
- */
-typedef enum
-{
- IX_QMGR_QUELOW_GROUP = 0, /**< Queues 0-31 */
- IX_QMGR_QUEUPP_GROUP /**< Queues 32-63 */
-} IxQMgrDispatchGroup;
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @enum IxQMgrPriority
- *
- * @brief Dispatcher priority levels.
- *
- * This enum defines the different queue dispatch priority levels.
- * The lowest priority number (0) is the highest priority level.
- *
- */
-typedef enum
-{
- IX_QMGR_Q_PRIORITY_0 = 0, /**< Priority level 0 */
- IX_QMGR_Q_PRIORITY_1, /**< Priority level 1 */
- IX_QMGR_Q_PRIORITY_2, /**< Priority level 2 */
- IX_QMGR_Q_PRIORITY_INVALID /**< Invalid Priority level */
-} IxQMgrPriority;
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @enum IxQMgrType
- *
- * @brief Callback types as used with livelock prevention
- *
- * This enum defines the different callback types.
- * These types are only used when Livelock prevention is enabled.
- * The default is IX_QMGR_TYPE_REALTIME_OTHER.
- *
- */
-
-typedef enum
-{
- IX_QMGR_TYPE_REALTIME_OTHER = 0, /**< Real time callbacks-always allowed run*/
- IX_QMGR_TYPE_REALTIME_PERIODIC, /**< Periodic callbacks-always allowed run */
- IX_QMGR_TYPE_REALTIME_SPORADIC /**< Sporadic callbacks-only run if no
- periodic callbacks are in progress */
-} IxQMgrType;
-
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @typedef IxQMgrCallbackId
- *
- * @brief Uniquely identifies a callback function.
- *
- * A unique callback identifier associated with each callback
- * registered by clients.
- *
- */
-typedef unsigned IxQMgrCallbackId;
-
-/**
- * @typedef IxQMgrCallback
- *
- * @brief QMgr notification callback type.
- *
- * This defines the interface to all client callback functions.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier
- * @param cbId @ref IxQMgrCallbackId [in] - the callback identifier
- */
-typedef void (*IxQMgrCallback)(IxQMgrQId qId,
- IxQMgrCallbackId cbId);
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @typedef IxQMgrDispatcherFuncPtr
- *
- * @brief QMgr Dispatcher Loop function pointer.
- *
- * This defines the interface for QMgr Dispather functions.
- *
- * @param group @ref IxQMgrDispatchGroup [in] - the group of the
- * queue of which the dispatcher will run
- */
-typedef void (*IxQMgrDispatcherFuncPtr)(IxQMgrDispatchGroup group);
-
-/*
- * Function Prototypes
- */
-
-/* ------------------------------------------------------------
- Initialisation related functions
- ---------------------------------------------------------- */
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrInit (void)
- *
- * @brief Initialise the QMgr.
- *
- * This function must be called before and other QMgr function. It
- * sets up internal data structures.
- *
- * @return @li IX_SUCCESS, the IxQMgr successfully initialised
- * @return @li IX_FAIL, failed to initialize the Qmgr
- *
- */
-PUBLIC IX_STATUS
-ixQMgrInit (void);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrUnload (void)
- *
- * @brief Uninitialise the QMgr.
- *
- * This function will perform the tasks required to unload the QMgr component
- * cleanly. This includes unmapping kernel memory.
- * This should be called before a soft reboot or unloading of a kernel module.
- *
- * @pre It should only be called if @ref ixQMgrInit has already been called.
- *
- * @post No QMgr functions should be called until ixQMgrInit is called again.
- *
- * @return @li IX_SUCCESS, the IxQMgr successfully uninitialised
- * @return @li IX_FAIL, failed to uninitialize the Qmgr
- *
- */
-PUBLIC IX_STATUS
-ixQMgrUnload (void);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrShow (void)
- *
- * @brief Describe queue configuration and statistics for active queues.
- *
- * This function shows active queues, their configurations and statistics.
- *
- * @return @li void
- *
- */
-PUBLIC void
-ixQMgrShow (void);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQShow (IxQMgrQId qId)
- *
- * @brief Display aqueue configuration and statistics for a queue.
- *
- * This function shows queue configuration and statistics for a queue.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier.
- *
- * @return @li IX_SUCCESS, success
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId
- *
- */
-PUBLIC IX_STATUS
-ixQMgrQShow (IxQMgrQId qId);
-
-
-/* ------------------------------------------------------------
- Configuration related functions
- ---------------------------------------------------------- */
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQConfig (char *qName,
- IxQMgrQId qId,
- IxQMgrQSizeInWords qSizeInWords,
- IxQMgrQEntrySizeInWords qEntrySizeInWords)
- *
- * @brief Configure an AQM queue.
- *
- * This function is called by a client to setup a queue. The size and entrySize
- * qId and qName(NULL pointer) are checked for valid values. This function must
- * be called for each queue, before any queue accesses are made and after
- * ixQMgrInit() has been called. qName is assumed to be a '\0' terminated array
- * of 16 charachters or less.
- *
- * @param *qName char [in] - is the name provided by the client and is associated
- * with a QId by the QMgr.
- * @param qId @ref IxQMgrQId [in] - the qId of this queue
- * @param qSizeInWords @ref IxQMgrQSize [in] - the size of the queue can be one of 16,32
- * 64, 128 words.
- * @param qEntrySizeInWords @ref IxQMgrQEntrySizeInWords [in] - the size of a queue entry
- * can be one of 1,2,4 words.
- *
- * @return @li IX_SUCCESS, a specified queue has been successfully configured.
- * @return @li IX_FAIL, IxQMgr has not been initialised.
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid parameter(s).
- * @return @li IX_QMGR_INVALID_QSIZE, invalid queue size
- * @return @li IX_QMGR_INVALID_Q_ID, invalid queue id
- * @return @li IX_QMGR_INVALID_Q_ENTRY_SIZE, invalid queue entry size
- * @return @li IX_QMGR_Q_ALREADY_CONFIGURED, queue already configured
- *
- */
-PUBLIC IX_STATUS
-ixQMgrQConfig (char *qName,
- IxQMgrQId qId,
- IxQMgrQSizeInWords qSizeInWords,
- IxQMgrQEntrySizeInWords qEntrySizeInWords);
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQSizeInEntriesGet (IxQMgrQId qId,
- unsigned *qSizeInEntries)
- *
- * @brief Return the size of a queue in entries.
- *
- * This function returns the the size of the queue in entriese.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier
- * @param *qSizeInEntries @ref IxQMgrQSize [out] - queue size in entries
- *
- * @return @li IX_SUCCESS, successfully retrieved the number of full entrie
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid parameter(s).
- *
- */
-PUBLIC IX_STATUS
-ixQMgrQSizeInEntriesGet (IxQMgrQId qId,
- unsigned *qSizeInEntries);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrWatermarkSet (IxQMgrQId qId,
- IxQMgrWMLevel ne,
- IxQMgrWMLevel nf)
- *
- * @brief Set the Nearly Empty and Nearly Full Watermarks fo a queue.
- *
- * This function is called by a client to set the watermarks NE and NF for the
- * queue specified by qId.
- * The queue must be empty at the time this function is called, it is the clients
- * responsibility to ensure that the queue is empty.
- * This function will read the status of the queue before the watermarks are set
- * and again after the watermarks are set. If the status register has changed,
- * due to a queue access by an NPE for example, a warning is returned.
- * Queues 32-63 only support the NE flag, therefore the value of nf will be ignored
- * for these queues.
- *
- * @param qId @ref IxQMgrQId [in] - the QId of the queue.
- * @param ne @ref IxQMgrWMLevel [in] - the NE(Nearly Empty) watermark for this
- * queue. Valid values are 0,1,2,4,8,16,32 and
- * 64 entries.
- * @param nf @ref IxQMgrWMLevel [in] - the NF(Nearly Full) watermark for this queue.
- * Valid values are 0,1,2,4,8,16,32 and 64
- * entries.
- *
- * @return @li IX_SUCCESS, watermarks have been set for the queu
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId
- * @return @li IX_QMGR_INVALID_Q_WM, invalid watermark
- * @return @li IX_QMGR_WARNING, the status register may not be constistent
- *
- */
-PUBLIC IX_STATUS
-ixQMgrWatermarkSet (IxQMgrQId qId,
- IxQMgrWMLevel ne,
- IxQMgrWMLevel nf);
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrAvailableSramAddressGet (UINT32 *address,
- unsigned *sizeOfFreeSram)
- *
- * @brief Return the address of available AQM SRAM.
- *
- * This function returns the starting address in AQM SRAM not used by the
- * current queue configuration and should only be called after all queues
- * have been configured.
- * Calling this function before all queues have been configured will will return
- * the currently available SRAM. A call to configure another queue will use some
- * of the available SRAM.
- * The amount of SRAM available is specified in sizeOfFreeSram. The address is the
- * address of the bottom of available SRAM. Available SRAM extends from address
- * from address to address + sizeOfFreeSram.
- *
- * @param **address UINT32 [out] - the address of the available SRAM, NULL if
- * none available.
- * @param *sizeOfFreeSram unsigned [out]- the size in words of available SRAM
- *
- * @return @li IX_SUCCESS, there is available SRAM and is pointed to by address
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid parameter(s)
- * @return @li IX_QMGR_NO_AVAILABLE_SRAM, all AQM SRAM is consumed by the queue
- * configuration.
- *
- */
-PUBLIC IX_STATUS
-ixQMgrAvailableSramAddressGet (UINT32 *address,
- unsigned *sizeOfFreeSram);
-
-
-/* ------------------------------------------------------------
- Queue access related functions
- ---------------------------------------------------------- */
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQReadWithChecks (IxQMgrQId qId,
- UINT32 *entry)
- *
- * @brief Read an entry from a queue.
- *
- * This function reads an entire entry from a queue returning it in entry. The
- * queue configuration word is read to determine what entry size this queue is
- * configured for and then the number of words specified by the entry size is
- * read. entry must be a pointer to a previously allocated array of sufficient
- * size to hold an entry.
- *
- * @note - IX_QMGR_Q_UNDERFLOW is only returned for queues 0-31 as queues 32-63
- * do not have an underflow status maintained.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier.
- * @param *entry UINT32 [out] - pointer to the entry word(s).
- *
- * @return @li IX_SUCCESS, entry was successfully read.
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid paramter(s).
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId
- * @return @li IX_QMGR_Q_UNDERFLOW, attempt to read from an empty queue
- *
- */
-PUBLIC IX_STATUS
-ixQMgrQReadWithChecks (IxQMgrQId qId,
- UINT32 *entry);
-
-
-
-/**
- * @brief Internal structure to facilitate inlining functions in IxQMgr.h
- */
-typedef struct
-{
- /* fields related to write functions */
- UINT32 qOflowStatBitMask; /**< overflow status mask */
- UINT32 qWriteCount; /**< queue write count */
-
- /* fields related to read and write functions */
- volatile UINT32 *qAccRegAddr; /**< access register */
- volatile UINT32 *qUOStatRegAddr; /**< status register */
- volatile UINT32 *qConfigRegAddr; /**< config register */
- UINT32 qEntrySizeInWords; /**< queue entry size in words */
- UINT32 qSizeInEntries; /**< queue size in entries */
-
- /* fields related to read functions */
- UINT32 qUflowStatBitMask; /**< underflow status mask */
- UINT32 qReadCount; /**< queue read count */
-} IxQMgrQInlinedReadWriteInfo;
-
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQReadMWordsMinus1 (IxQMgrQId qId,
- UINT32 *entry)
- *
- * @brief This function reads the remaining of the q entry
- * for queues configured with many words.
- * (the first word of the entry is already read
- * in the inlined function and the entry pointer already
- * incremented
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier.
- * @param *entry UINT32 [out] - pointer to the entry word(s).
- *
- * @return @li IX_SUCCESS, entry was successfully read.
- * @return @li IX_QMGR_Q_UNDERFLOW, attempt to read from an empty queue
- *
- */
-PUBLIC IX_STATUS
-ixQMgrQReadMWordsMinus1 (IxQMgrQId qId,
- UINT32 *entry);
-
-
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQRead (IxQMgrQId qId,
- UINT32 *entry)
- *
- * @brief Fast read of an entry from a queue.
- *
- * This function is a heavily streamlined version of ixQMgrQReadWithChecks(),
- * but performs essentially the same task. It reads an entire entry from a
- * queue, returning it in entry which must be a pointer to a previously
- * allocated array of sufficient size to hold an entry.
- *
- * @note - This function is inlined, to reduce unnecessary function call
- * overhead. It does not perform any parameter checks, or update any statistics.
- * Also, it does not check that the queue specified by qId has been configured.
- * or is in range. It simply reads an entry from the queue, and checks for
- * underflow.
- *
- * @note - IX_QMGR_Q_UNDERFLOW is only returned for queues 0-31 as queues 32-63
- * do not have an underflow status maintained.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier.
- * @param *entry UINT32 [out] - pointer to the entry word(s).
- *
- * @return @li IX_SUCCESS, entry was successfully read.
- * @return @li IX_QMGR_Q_UNDERFLOW, attempt to read from an empty queue
- *
- */
-#ifdef NO_INLINE_APIS
-PUBLIC IX_STATUS
-ixQMgrQRead (IxQMgrQId qId,
- UINT32 *entryPtr);
-#else
-extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
-extern IX_STATUS ixQMgrQReadMWordsMinus1 (IxQMgrQId qId, UINT32 *entryPtr);
-
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQRead (IxQMgrQId qId,
- UINT32 *entryPtr);
-#endif
-
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQRead (IxQMgrQId qId,
- UINT32 *entryPtr)
-#ifdef NO_INLINE_APIS
- ;
-#else
-{
- IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
- UINT32 entry, entrySize;
-
- /* get a new entry */
- entrySize = infoPtr->qEntrySizeInWords;
- entry = IX_QMGR_INLINE_READ_LONG(infoPtr->qAccRegAddr);
-
- if (entrySize != IX_QMGR_Q_ENTRY_SIZE1)
- {
- *entryPtr = entry;
- /* process the remaining part of the entry */
- return ixQMgrQReadMWordsMinus1(qId, entryPtr);
- }
-
- /* underflow is available for lower queues only */
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- /* the counter of queue entries is decremented. In happy
- * day scenario there are many entries in the queue
- * and the counter does not reach zero.
- */
- if (infoPtr->qReadCount-- == 0)
- {
- /* There is maybe no entry in the queue
- * qReadCount is now negative, but will be corrected before
- * the function returns.
- */
- UINT32 qPtrs; /* queue internal pointers */
-
- /* when a queue is empty, the hw guarantees to return
- * a null value. If the value is not null, the queue is
- * not empty.
- */
- if (entry == 0)
- {
- /* get the queue status */
- UINT32 status = IX_QMGR_INLINE_READ_LONG(infoPtr->qUOStatRegAddr);
-
- /* check the underflow status */
- if (status & infoPtr->qUflowStatBitMask)
- {
- /* the queue is empty
- * clear the underflow status bit if it was set
- */
- IX_QMGR_INLINE_WRITE_LONG(infoPtr->qUOStatRegAddr,
- status & ~infoPtr->qUflowStatBitMask);
- *entryPtr = 0;
- infoPtr->qReadCount = 0;
- return IX_QMGR_Q_UNDERFLOW;
- }
- }
- /* store the result */
- *entryPtr = entry;
-
- /* No underflow occured : someone is filling the queue
- * or the queue contains null entries.
- * The current counter needs to be
- * updated from the current number of entries in the queue
- */
-
- /* get snapshot of queue pointers */
- qPtrs = IX_QMGR_INLINE_READ_LONG(infoPtr->qConfigRegAddr);
-
- /* Mod subtraction of pointers to get number of words in Q. */
- qPtrs = (qPtrs - (qPtrs >> 7)) & 0x7f;
-
- if (qPtrs == 0)
- {
- /* no entry in the queue */
- infoPtr->qReadCount = 0;
- }
- else
- {
- /* convert the number of words inside the queue
- * to a number of entries
- */
- infoPtr->qReadCount = qPtrs & (infoPtr->qSizeInEntries - 1);
- }
- return IX_SUCCESS;
- }
- }
- *entryPtr = entry;
- return IX_SUCCESS;
-}
-#endif
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQBurstRead (IxQMgrQId qId,
- UINT32 numEntries,
- UINT32 *entries)
- *
- * @brief Read a number of entries from an AQM queue.
- *
- * This function will burst read a number of entries from the specified queue.
- * The entry size of queue is auto-detected. The function will attempt to
- * read as many entries as specified by the numEntries parameter and will
- * return an UNDERFLOW if any one of the individual entry reads fail.
- *
- * @warning
- * IX_QMGR_Q_UNDERFLOW is only returned for queues 0-31 as queues 32-63
- * do not have an underflow status maintained, hence there is a potential for
- * silent failure here. This function must be used with caution.
- *
- * @note
- * This function is intended for fast draining of queues, so to make it
- * as efficient as possible, it has the following features:
- * - This function is inlined, to reduce unnecessary function call overhead.
- * - It does not perform any parameter checks, or update any statistics.
- * - It does not check that the queue specified by qId has been configured.
- * - It does not check that the queue has the number of full entries that
- * have been specified to be read. It will read until it finds a NULL entry or
- * until the number of specified entries have been read. It always checks for
- * underflow after all the reads have been performed.
- * Therefore, the client should ensure before calling this function that there
- * are enough entries in the queue to read. ixQMgrQNumEntriesGet() will
- * provide the number of full entries in a queue.
- * ixQMgrQRead() or ixQMgrQReadWithChecks(), which only reads
- * a single queue entry per call, should be used instead if the user requires
- * checks for UNDERFLOW after each entry read.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier.
- * @param numEntries unsigned [in] - the number of entries to read.
- * This number should be greater than 0
- * @param *entries UINT32 [out] - the word(s) read.
- *
- * @return @li IX_SUCCESS, entries were successfully read.
- * @return @li IX_QMGR_Q_UNDERFLOW, attempt to read from an empty queue
- *
- */
-#ifdef NO_INLINE_APIS
-PUBLIC IX_STATUS
-ixQMgrQBurstRead (IxQMgrQId qId,
- UINT32 numEntries,
- UINT32 *entries);
-#else
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQBurstRead (IxQMgrQId qId,
- UINT32 numEntries,
- UINT32 *entries);
-#endif /* endif NO_INLINE_APIS */
-
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQBurstRead (IxQMgrQId qId,
- UINT32 numEntries,
- UINT32 *entries)
-#ifdef NO_INLINE_APIS
-;
-#else
-{
- IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
- UINT32 nullCheckEntry;
-
- if (infoPtr->qEntrySizeInWords == IX_QMGR_Q_ENTRY_SIZE1)
- {
- volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
-
- /* the code is optimized to take care of data dependencies:
- * Durig a read, there are a few cycles needed to get the
- * read complete. During these cycles, it is poossible to
- * do some CPU, e.g. increment pointers and decrement
- * counters.
- */
-
- /* fetch a queue entry */
- nullCheckEntry = IX_QMGR_INLINE_READ_LONG(infoPtr->qAccRegAddr);
-
- /* iterate the specified number of queue entries */
- while (--numEntries)
- {
- /* check the result of the previous read */
- if (nullCheckEntry == 0)
- {
- /* if we read a NULL entry, stop. We have underflowed */
- break;
- }
- else
- {
- /* write the entry */
- *entries = nullCheckEntry;
- /* fetch next entry */
- nullCheckEntry = IX_QMGR_INLINE_READ_LONG(qAccRegAddr);
- /* increment the write address */
- entries++;
- }
- }
- /* write the pre-fetched entry */
- *entries = nullCheckEntry;
- }
- else
- {
- IxQMgrQEntrySizeInWords entrySizeInWords = infoPtr->qEntrySizeInWords;
- /* read the specified number of queue entries */
- nullCheckEntry = 0;
- while (numEntries--)
- {
- UINT32 i;
-
- for (i = 0; i < (UINT32)entrySizeInWords; i++)
- {
- *entries = IX_QMGR_INLINE_READ_LONG(infoPtr->qAccRegAddr + i);
- nullCheckEntry |= *entries++;
- }
-
- /* if we read a NULL entry, stop. We have underflowed */
- if (nullCheckEntry == 0)
- {
- break;
- }
- nullCheckEntry = 0;
- }
- }
-
- /* reset the current read count : next access to the read function
- * will force a underflow status check
- */
- infoPtr->qReadCount = 0;
-
- /* Check if underflow occurred on the read */
- if (nullCheckEntry == 0 && qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- /* get the queue status */
- UINT32 status = IX_QMGR_INLINE_READ_LONG(infoPtr->qUOStatRegAddr);
-
- if (status & infoPtr->qUflowStatBitMask)
- {
- /* clear the underflow status bit if it was set */
- IX_QMGR_INLINE_WRITE_LONG(infoPtr->qUOStatRegAddr,
- status & ~infoPtr->qUflowStatBitMask);
- return IX_QMGR_Q_UNDERFLOW;
- }
- }
-
- return IX_SUCCESS;
-}
-#endif
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQPeek (IxQMgrQId qId,
- unsigned int entryIndex,
- UINT32 *entry)
- *
- * @brief Read an entry from a queue without moving the read pointer.
- *
- * This function inspects an entry in a queue. The entry is inspected directly
- * in AQM SRAM and is not read from queue access registers. The entry is NOT removed
- * from the queue and the read/write pointers are unchanged.
- * N.B: The queue should not be accessed when this function is called.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier.
- * @param entryIndex unsigned int [in] - index of entry in queue in the range
- * [0].......[current number of entries in queue].
- * @param *entry UINT32 [out] - pointer to the entry word(s).
- *
- * @return @li IX_SUCCESS, entry was successfully inspected.
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid paramter(s).
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId.
- * @return @li IX_QMGR_ENTRY_INDEX_OUT_OF_BOUNDS, an entry does not exist at
- * specified index.
- * @return @li IX_FAIL, failed to inpected the queue entry.
- */
-PUBLIC IX_STATUS
-ixQMgrQPeek (IxQMgrQId qId,
- unsigned int entryIndex,
- UINT32 *entry);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQWriteWithChecks (IxQMgrQId qId,
- UINT32 *entry)
- *
- * @brief Write an entry to an AQM queue.
- *
- * This function will write the entry size number of words pointed to by entry to
- * the queue specified by qId. The queue configuration word is read to
- * determine the entry size of queue and the corresponding number of words is
- * then written to the queue.
- *
- * @note - IX_QMGR_Q_OVERFLOW is only returned for queues 0-31 as queues 32-63
- * do not have an overflow status maintained.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier.
- * @param *entry UINT32 [in] - the word(s) to write.
- *
- * @return @li IX_SUCCESS, value was successfully written.
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid paramter(s).
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId
- * @return @li IX_QMGR_Q_OVERFLOW, attempt to write to a full queue
- *
- */
-PUBLIC IX_STATUS
-ixQMgrQWriteWithChecks (IxQMgrQId qId,
- UINT32 *entry);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQWrite (IxQMgrQId qId,
- UINT32 *entry)
- *
- * @brief Fast write of an entry to a queue.
- *
- * This function is a heavily streamlined version of ixQMgrQWriteWithChecks(),
- * but performs essentially the same task. It will write the entry size number
- * of words pointed to by entry to the queue specified by qId.
- *
- * @note - This function is inlined, to reduce unnecessary function call
- * overhead. It does not perform any parameter checks, or update any
- * statistics. Also, it does not check that the queue specified by qId has
- * been configured. It simply writes an entry to the queue, and checks for
- * overflow.
- *
- * @note - IX_QMGR_Q_OVERFLOW is only returned for queues 0-31 as queues 32-63
- * do not have an overflow status maintained.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier.
- * @param *entry UINT32 [in] - pointer to the entry word(s).
- *
- * @return @li IX_SUCCESS, entry was successfully read.
- * @return @li IX_QMGR_Q_OVERFLOW, attempt to write to a full queue
- *
- */
-#ifdef NO_INLINE_APIS
-PUBLIC IX_STATUS
-ixQMgrQWrite (IxQMgrQId qId,
- UINT32 *entry);
-#else
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQWrite (IxQMgrQId qId,
- UINT32 *entry);
-#endif /* NO_INLINE_APIS */
-
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQWrite (IxQMgrQId qId,
- UINT32 *entry)
-#ifdef NO_INLINE_APIS
- ;
-#else
-{
- IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
- UINT32 entrySize;
-
- /* write the entry */
- IX_QMGR_INLINE_WRITE_LONG(infoPtr->qAccRegAddr, *entry);
- entrySize = infoPtr->qEntrySizeInWords;
-
- if (entrySize != IX_QMGR_Q_ENTRY_SIZE1)
- {
- /* process the remaining part of the entry */
- volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
- while (--entrySize)
- {
- ++entry;
- IX_QMGR_INLINE_WRITE_LONG(++qAccRegAddr, *entry);
- }
- entrySize = infoPtr->qEntrySizeInWords;
- }
-
- /* overflow is available for lower queues only */
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- UINT32 qSize = infoPtr->qSizeInEntries;
- /* increment the current number of entries in the queue
- * and check for overflow
- */
- if (infoPtr->qWriteCount++ == qSize)
- {
- /* the queue may have overflow */
- UINT32 qPtrs; /* queue internal pointers */
-
- /* get the queue status */
- UINT32 status = IX_QMGR_INLINE_READ_LONG(infoPtr->qUOStatRegAddr);
-
- /* read the status twice because the status may
- * not be immediately ready after the write operation
- */
- if ((status & infoPtr->qOflowStatBitMask) ||
- ((status = IX_QMGR_INLINE_READ_LONG(infoPtr->qUOStatRegAddr))
- & infoPtr->qOflowStatBitMask))
- {
- /* the queue is full, clear the overflow status
- * bit if it was set
- */
- IX_QMGR_INLINE_WRITE_LONG(infoPtr->qUOStatRegAddr,
- status & ~infoPtr->qOflowStatBitMask);
- infoPtr->qWriteCount = infoPtr->qSizeInEntries;
- return IX_QMGR_Q_OVERFLOW;
- }
- /* No overflow occured : someone is draining the queue
- * and the current counter needs to be
- * updated from the current number of entries in the queue
- */
-
- /* get q pointer snapshot */
- qPtrs = IX_QMGR_INLINE_READ_LONG(infoPtr->qConfigRegAddr);
-
- /* Mod subtraction of pointers to get number of words in Q. */
- qPtrs = (qPtrs - (qPtrs >> 7)) & 0x7f;
-
- if (qPtrs == 0)
- {
- /* the queue may be full at the time of the
- * snapshot. Next access will check
- * the overflow status again.
- */
- infoPtr->qWriteCount = qSize;
- }
- else
- {
- /* convert the number of words to a number of entries */
- if (entrySize == IX_QMGR_Q_ENTRY_SIZE1)
- {
- infoPtr->qWriteCount = qPtrs & (qSize - 1);
- }
- else
- {
- infoPtr->qWriteCount = (qPtrs / entrySize) & (qSize - 1);
- }
- }
- }
- }
- return IX_SUCCESS;
-}
-#endif
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQBurstWrite (IxQMgrQId qId,
- unsigned numEntries,
- UINT32 *entries)
- *
- * @brief Write a number of entries to an AQM queue.
- *
- * This function will burst write a number of entries to the specified queue.
- * The entry size of queue is auto-detected. The function will attempt to
- * write as many entries as specified by the numEntries parameter and will
- * return an OVERFLOW if any one of the individual entry writes fail.
- *
- * @warning
- * IX_QMGR_Q_OVERFLOW is only returned for queues 0-31 as queues 32-63
- * do not have an overflow status maintained, hence there is a potential for
- * silent failure here. This function must be used with caution.
- *
- * @note
- * This function is intended for fast population of queues, so to make it
- * as efficient as possible, it has the following features:
- * - This function is inlined, to reduce unnecessary function call overhead.
- * - It does not perform any parameter checks, or update any statistics.
- * - It does not check that the queue specified by qId has been configured.
- * - It does not check that the queue has enough free space to hold the entries
- * before writing, and only checks for overflow after all writes have been
- * performed. Therefore, the client should ensure before calling this function
- * that there is enough free space in the queue to hold the number of entries
- * to be written. ixQMgrQWrite() or ixQMgrQWriteWithChecks(), which only writes
- * a single queue entry per call, should be used instead if the user requires
- * checks for OVERFLOW after each entry written.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier.
- * @param numEntries unsigned [in] - the number of entries to write.
- * @param *entries UINT32 [in] - the word(s) to write.
- *
- * @return @li IX_SUCCESS, value was successfully written.
- * @return @li IX_QMGR_Q_OVERFLOW, attempt to write to a full queue
- *
- */
-#ifdef NO_INLINE_APIS
-PUBLIC IX_STATUS
-ixQMgrQBurstWrite (IxQMgrQId qId,
- unsigned numEntries,
- UINT32 *entries);
-#else
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQBurstWrite (IxQMgrQId qId,
- unsigned numEntries,
- UINT32 *entries);
-#endif /* NO_INLINE_APIS */
-
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQBurstWrite (IxQMgrQId qId,
- unsigned numEntries,
- UINT32 *entries)
-#ifdef NO_INLINE_APIS
-;
-#else
-{
- IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
- UINT32 status;
-
- /* update the current write count */
- infoPtr->qWriteCount += numEntries;
-
- if (infoPtr->qEntrySizeInWords == IX_QMGR_Q_ENTRY_SIZE1)
- {
- volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
- while (numEntries--)
- {
- IX_QMGR_INLINE_WRITE_LONG(qAccRegAddr, *entries);
- entries++;
- }
- }
- else
- {
- IxQMgrQEntrySizeInWords entrySizeInWords = infoPtr->qEntrySizeInWords;
- UINT32 i;
-
- /* write each queue entry */
- while (numEntries--)
- {
- /* write the queueEntrySize number of words for each entry */
- for (i = 0; i < (UINT32)entrySizeInWords; i++)
- {
- IX_QMGR_INLINE_WRITE_LONG((infoPtr->qAccRegAddr + i), *entries);
- entries++;
- }
- }
- }
-
- /* check if the write count overflows */
- if (infoPtr->qWriteCount > infoPtr->qSizeInEntries)
- {
- /* reset the current write count */
- infoPtr->qWriteCount = infoPtr->qSizeInEntries;
- }
-
- /* Check if overflow occurred on the write operation */
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- /* get the queue status */
- status = IX_QMGR_INLINE_READ_LONG(infoPtr->qUOStatRegAddr);
-
- /* read the status twice because the status may
- * not be ready at the time of the write
- */
- if ((status & infoPtr->qOflowStatBitMask) ||
- ((status = IX_QMGR_INLINE_READ_LONG(infoPtr->qUOStatRegAddr))
- & infoPtr->qOflowStatBitMask))
- {
- /* clear the underflow status bit if it was set */
- IX_QMGR_INLINE_WRITE_LONG(infoPtr->qUOStatRegAddr,
- status & ~infoPtr->qOflowStatBitMask);
- return IX_QMGR_Q_OVERFLOW;
- }
- }
-
- return IX_SUCCESS;
-}
-#endif
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQPoke (IxQMgrQId qId,
- unsigned int entryIndex,
- UINT32 *entry)
- *
- * @brief Write an entry to a queue without moving the write pointer.
- *
- * This function modifies an entry in a queue. The entry is modified directly
- * in AQM SRAM and not using the queue access registers. The entry is NOT added to the
- * queue and the read/write pointers are unchanged.
- * N.B: The queue should not be accessed when this function is called.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier.
- * @param entryIndex unsigned int [in] - index of entry in queue in the range
- * [0].......[current number of entries in queue].
- * @param *entry UINT32 [in] - pointer to the entry word(s).
- *
- * @return @li IX_SUCCESS, entry was successfully modified.
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid paramter(s).
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId.
- * @return @li IX_QMGR_ENTRY_INDEX_OUT_OF_BOUNDS, an entry does not exist at
- * specified index.
- * @return @li IX_FAIL, failed to modify the queue entry.
- */
-PUBLIC IX_STATUS
-ixQMgrQPoke (IxQMgrQId qId,
- unsigned int entryIndex,
- UINT32 *entry);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQNumEntriesGet (IxQMgrQId qId,
- unsigned *numEntries)
- *
- * @brief Get a snapshot of the number of entries in a queue.
- *
- * This function gets the number of entries in a queue.
- *
- * @param qId @ref IxQMgrQId [in] qId - the queue idenfifier
- * @param *numEntries unsigned [out] - the number of entries in a queue
- *
- * @return @li IX_SUCCESS, got the number of entries for the queue
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid paramter(s).
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, the specified qId has not been configured
- * @return @li IX_QMGR_WARNING, could not determine num entries at this time
- *
- */
-PUBLIC IX_STATUS
-ixQMgrQNumEntriesGet (IxQMgrQId qId,
- unsigned *numEntries);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQStatusGetWithChecks (IxQMgrQId qId,
- IxQMgrQStatus *qStatus)
- *
- * @brief Get a queues status.
- *
- * This function reads the specified queues status. A queues status is defined
- * by its status flags. For queues 0-31 these flags are E,NE,NF,F. For
- * queues 32-63 these flags are NE and F.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier.
- * @param &qStatus @ref IxQMgrQStatus [out] - the status of the specified queue.
- *
- * @return @li IX_SUCCESS, queue status was successfully read.
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, the specified qId has not been configured
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid paramter.
- *
- */
-PUBLIC IX_STATUS
-ixQMgrQStatusGetWithChecks (IxQMgrQId qId,
- IxQMgrQStatus *qStatus);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrQStatusGet (IxQMgrQId qId,
- IxQMgrQStatus *qStatus)
- *
- * @brief Fast get of a queue's status.
- *
- * This function is a streamlined version of ixQMgrQStatusGetWithChecks(), but
- * performs essentially the same task. It reads the specified queue's status.
- * A queues status is defined by its status flags. For queues 0-31 these flags
- * are E,NE,NF,F. For queues 32-63 these flags are NE and F.
- *
- * @note - This function is inlined, to reduce unnecessary function call
- * overhead. It does not perform any parameter checks, or update any
- * statistics. Also, it does not check that the queue specified by qId has
- * been configured. It simply reads the specified queue's status.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier.
- * @param *qStatus @ref IxQMgrQStatus [out] - the status of the specified queue.
- *
- * @return @li void.
- *
- */
-
-#ifdef NO_INLINE_APIS
-PUBLIC IX_STATUS
-ixQMgrQStatusGet (IxQMgrQId qId,
- IxQMgrQStatus *qStatus);
-#else
-extern UINT32 ixQMgrAqmIfQueLowStatRegAddr[];
-extern UINT32 ixQMgrAqmIfQueLowStatBitsOffset[];
-extern UINT32 ixQMgrAqmIfQueLowStatBitsMask;
-extern UINT32 ixQMgrAqmIfQueUppStat0RegAddr;
-extern UINT32 ixQMgrAqmIfQueUppStat1RegAddr;
-extern UINT32 ixQMgrAqmIfQueUppStat0BitMask[];
-extern UINT32 ixQMgrAqmIfQueUppStat1BitMask[];
-
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQStatusGet (IxQMgrQId qId,
- IxQMgrQStatus *qStatus);
-#endif /* endif NO_INLINE_APIS */
-
-IX_QMGR_INLINE PUBLIC IX_STATUS
-ixQMgrQStatusGet (IxQMgrQId qId,
- IxQMgrQStatus *qStatus)
-#ifdef NO_INLINE_APIS
- ;
-#else
-{
- /* read the status of a queue in the range 0-31 */
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- volatile UINT32 *lowStatRegAddr = (UINT32*)ixQMgrAqmIfQueLowStatRegAddr[qId];
-
- UINT32 lowStatBitsOffset = ixQMgrAqmIfQueLowStatBitsOffset[qId];
- UINT32 lowStatBitsMask = ixQMgrAqmIfQueLowStatBitsMask;
-
- /* read the status register for this queue */
- *qStatus = IX_QMGR_INLINE_READ_LONG(lowStatRegAddr);
-
- /* mask out the status bits relevant only to this queue */
- *qStatus = (*qStatus >> lowStatBitsOffset) & lowStatBitsMask;
-
- }
- else /* read status of a queue in the range 32-63 */
- {
-
- volatile UINT32 *qNearEmptyStatRegAddr = (UINT32*)ixQMgrAqmIfQueUppStat0RegAddr;
- volatile UINT32 *qFullStatRegAddr = (UINT32*)ixQMgrAqmIfQueUppStat1RegAddr;
- int maskIndex = qId - IX_QMGR_MIN_QUEUPP_QID;
- UINT32 qNearEmptyStatBitMask = ixQMgrAqmIfQueUppStat0BitMask[maskIndex];
- UINT32 qFullStatBitMask = ixQMgrAqmIfQueUppStat1BitMask[maskIndex];
-
- /* Reset the status bits */
- *qStatus = 0;
-
- /* Check if the queue is nearly empty */
- if (IX_QMGR_INLINE_READ_LONG(qNearEmptyStatRegAddr) & qNearEmptyStatBitMask)
- {
- *qStatus |= IX_QMGR_Q_STATUS_NE_BIT_MASK;
- }
-
- /* Check if the queue is full */
- if (IX_QMGR_INLINE_READ_LONG(qFullStatRegAddr) & qFullStatBitMask)
- {
- *qStatus |= IX_QMGR_Q_STATUS_F_BIT_MASK;
- }
- }
- return IX_SUCCESS;
-}
-#endif
-
-/* ------------------------------------------------------------
- Queue dispatch related functions
- ---------------------------------------------------------- */
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrDispatcherPrioritySet (IxQMgrQId qId,
- IxQMgrPriority priority)
- *
- * @brief Set the dispatch priority of a queue.
- *
- * This function is called to set the dispatch priority of queue. The effect of
- * this function is to add a priority change request to a queue. This queue is
- * serviced by @a ixQMgrDispatcherLoopRunA0, @a ixQMgrDispatcherLoopRunB0 or
- * @a ixQMgrDispatcherLoopRunB0LLP.
- *
- * This function is re-entrant. and can be used from an interrupt context
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier
- * @param priority @ref IxQMgrPriority [in] - the new queue dispatch priority
- *
- * @return @li IX_SUCCESS, priority change request is queued
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, the specified qId has not been configured
- * @return @li IX_QMGR_Q_INVALID_PRIORITY, specified priority is invalid
- *
- */
-PUBLIC IX_STATUS
-ixQMgrDispatcherPrioritySet (IxQMgrQId qId,
- IxQMgrPriority priority);
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrNotificationEnable (IxQMgrQId qId,
- IxQMgrSourceId sourceId)
- *
- * @brief Enable notification on a queue for a specified queue source flag.
- *
- * This function is called by a client of the QMgr to enable notifications on a
- * specified condition.
- * If the condition for the notification is set after the client has called this
- * function but before the function has enabled the interrupt source, then the
- * notification will not occur.
- * For queues 32-63 the notification source is fixed to the NE(Nearly Empty) flag
- * and cannot be changed so the sourceId parameter is ignored for these queues.
- * The status register is read before the notofication is enabled and is read again
- * after the notification has been enabled, if they differ then the warning status
- * is returned.
- *
- * This function is re-entrant. and can be used from an interrupt context
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier
- * @param sourceId @ref IxQMgrSourceId [in] - the interrupt src condition identifier
- *
- * @return @li IX_SUCCESS, the interrupt has been enabled for the specified source
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, the specified qId has not been configured
- * @return @li IX_QMGR_INVALID_INT_SOURCE_ID, interrupt source invalid for this queue
- * @return @li IX_QMGR_WARNING, the status register may not be constistent
- *
- */
-PUBLIC IX_STATUS
-ixQMgrNotificationEnable (IxQMgrQId qId,
- IxQMgrSourceId sourceId);
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrNotificationDisable (IxQMgrQId qId)
- *
- * @brief Disable notifications on a queue.
- *
- * This function is called to disable notifications on a specified queue.
- *
- * This function is re-entrant. and can be used from an interrupt context
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier
- *
- * @return @li IX_SUCCESS, the interrupt has been disabled
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, the specified qId has not been configured
- *
- */
-PUBLIC IX_STATUS
-ixQMgrNotificationDisable (IxQMgrQId qId);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrDispatcherLoopRunA0 (IxQMgrDispatchGroup group)
- *
- * @brief Run the callback dispatcher.
- *
- * This function runs the dispatcher for a group of queues.
- * Callbacks are made for interrupts that have occurred on queues within
- * the group that have registered callbacks. The order in which queues are
- * serviced depends on the queue priorities set by the client.
- * This function may be called from interrupt or task context.
- * For optimisations that were introduced in IXP42X B0 and supported IXP46X
- * the @a ixQMgrDispatcherLoopRunB0, or @a ixQMgrDispatcherLoopRunB0LLP
- * should be used.
- *
- * This function is not re-entrant.
- *
- * @param group @ref IxQMgrDispatchGroup [in] - the group of queues over which the
- * dispatcher will run
- *
- * @return @li void
- *
- * @note This function may be called from interrupt or task context.
- * However, for optimal performance the choice of context depends also on the
- * operating system used.
- *
- */
-PUBLIC void
-ixQMgrDispatcherLoopRunA0 (IxQMgrDispatchGroup group);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrDispatcherLoopRunB0 (IxQMgrDispatchGroup group)
- *
- * @brief Run the callback dispatcher.
- *
- * The enhanced version of @a ixQMgrDispatcherLoopRunA0 that is optimised for
- * features introduced in IXP42X B0 silicon and supported on IXP46X.
- * This is the default dispatcher for IXP42X B0 and IXP46X silicon.
- * The function runs the dispatcher for a group of queues.
- * Callbacks are made for interrupts that have occurred on queues within
- * the group that have registered callbacks. The order in which queues are
- * serviced depends on the queue priorities set by the client.
- * This function may be called from interrupt or task context.
- *
- * This function is not re-entrant.
- *
- * @param group @ref IxQMgrDispatchGroup [in] - the group of queues over which the
- * dispatcher will run
- *
- * @return @li void
- *
- *
- * @note This function may be called from interrupt or task context.
- * However, for optimal performance the choice of context depends also on the
- * operating system used.
- *
- */
-PUBLIC void
-ixQMgrDispatcherLoopRunB0 (IxQMgrDispatchGroup group);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrDispatcherLoopRunB0LLP (IxQMgrDispatchGroup group)
- *
- * @brief Run the callback dispatcher.
- *
- * This is a version of the optimised dispatcher for IXP42X B0 and IXP46X,
- * @a ixQMgrDispatcherLoopRunB0, with added support for livelock prevention.
- * This dispatcher will only be used for the IXP42X B0 or IXP46X silicon if
- * feature control indicates that IX_FEATURECTRL_ORIGB0_DISPATCHER is set to
- * IX_FEATURE_CTRL_SWCONFIG_DISABLED. Otherwise the @a ixQMgrDispatcherLoopRunB0
- * dispatcher will be used (Default).
- *
- * When this dispatcher notifies for a queue that is type
- * IX_QMGR_TYPE_REALTIME_PERIODIC, notifications for queues that are set
- * as type IX_QMGR_REALTIME_SPORADIC are not processed and disabled.
- * This helps prevent any tasks resulting from the notification of the
- * IX_QMGR_TYPE_REALTIME_PERIODIC type queue to being subject to livelock.
- * The function runs the dispatcher for a group of queues.
- * Callbacks are made for interrupts that have occurred on queues within
- * the group that have registered callbacks. The order in which queues are
- * serviced depends on their type along with the queue priorities set by the
- * client. This function may be called from interrupt or task context.
- *
- * This function is not re-entrant.
- *
- * @param group @ref IxQMgrDispatchGroup [in] - the group of queues over which
- * the dispatcher will run
- *
- * @return @li void
- *
- * @note This function may be called from interrupt or task context.
- * However, for optimal performance the choice of context depends also on the
- * operating system used.
- *
- */
-PUBLIC void
-ixQMgrDispatcherLoopRunB0LLP (IxQMgrDispatchGroup group);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrNotificationCallbackSet (IxQMgrQId qId,
- IxQMgrCallback callback,
- IxQMgrCallbackId callbackId)
- *
- * @brief Set the notification callback for a queue.
- *
- * This function sets the callback for the specified queue. This callback will
- * be called by the dispatcher, and may be called in the context of a interrupt
- * If callback has a value of NULL the previously registered callback, if one
- * exists will be unregistered.
- *
- * @param qId @ref IxQMgrQId [in] - the queue idenfifier
- * @param callback @ref IxQMgrCallback [in] - the callback registered for this queue
- * @param callbackId @ref IxQMgrCallbackId [in] - the callback identifier
- *
- * @return @li IX_SUCCESS, the callback for the specified queue has been set
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, the specified qId has not been configured
- *
- */
-PUBLIC IX_STATUS
-ixQMgrNotificationCallbackSet (IxQMgrQId qId,
- IxQMgrCallback callback,
- IxQMgrCallbackId callbackId);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrDispatcherLoopGet (IxQMgrDispatcherFuncPtr *qDispatcherFuncPtr)
- *
- * @brief Get QMgr DispatcherLoopRun for respective silicon device
- *
- * This function gets a function pointer to ixQMgrDispatcherLoopRunA0() for IXP42X A0
- * Silicon. If the IXP42X B0 or 46X Silicon, the default is the ixQMgrDispatcherLoopRunB0()
- * function, however if live lock prevention is enabled a function pointer to
- * ixQMgrDispatcherLoopRunB0LLP() is given.
- *
- * @param *qDispatchFuncPtr @ref IxQMgrDispatcherFuncPtr [out] -
- * the function pointer of QMgr Dispatcher
- *
- */
-PUBLIC void
-ixQMgrDispatcherLoopGet (IxQMgrDispatcherFuncPtr *qDispatcherFuncPtr);
-
-/**
- *
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrStickyInterruptRegEnable(void)
- *
- * @brief Enable AQM's sticky interrupt register behaviour only available
- * on B0 Silicon.
- *
- * When AQM's sticky interrupt register is enabled, interrupt register bit will
- * only be cleared when a '1' is written to interrupt register bit and the
- * interrupting condition is satisfied, i.e.queue condition does not exist.
- *
- * @note This function must be called before any queue is enabled.
- * Calling this function after queue is enabled will cause
- * undefined results.
- *
- * @return none
- *
- */
-PUBLIC void
-ixQMgrStickyInterruptRegEnable(void);
-
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrCallbackTypeSet(IxQMgrQId qId,
- IxQMgrType type)
- *
- * @brief Set the Callback Type of a queue.
- *
- * This function is only used for live lock prevention.
- * This function allows the callback type of a queue to be set. The default for
- * all queues is IX_QMGR_TYPE_REALTIME_OTHER. Setting the type to
- * IX_QMGR_TYPE_REALTIME_SPORADIC means that this queue will have it's
- * notifications disabled while there is a task associated with a
- * queue of type IX_QMGR_TYPE_REALTIME_PERIODIC running. As live lock
- * prevention operates on lower queues, this function should
- * be called for lower queues only.
- * This function is not re-entrant.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier
- * @param type @ref IxQMgrType [in] - the type of callback
- *
- * @return @li IX_SUCCESS, successfully set callback type for the queue entry
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid parameter(s).
- *
- */
-PUBLIC IX_STATUS
-ixQMgrCallbackTypeSet(IxQMgrQId qId,
- IxQMgrType type);
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrCallbackTypeGet(IxQMgrQId qId,
- IxQMgrType *type)
- *
- * @brief Get the Callback Type of a queue.
- *
- * This function allows the callback type of a queue to be got. As live lock
- * prevention operates on lower queues, this function should
- * be called for lower queues only.
- * This function is re-entrant.
- *
- * @param qId @ref IxQMgrQId [in] - the queue identifier
- * @param *type @ref IxQMgrType [out] - the type of callback
- *
- * @return @li IX_SUCCESS, successfully set callback type for the queue entry
- * @return @li IX_QMGR_Q_NOT_CONFIGURED, queue not configured for this QId
- * @return @li IX_QMGR_PARAMETER_ERROR, invalid parameter(s)
- *
- */
-PUBLIC IX_STATUS
-ixQMgrCallbackTypeGet(IxQMgrQId qId,
- IxQMgrType *type);
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrPeriodicDone(void)
- *
- * @brief Indicate that the Periodic task is completed for LLP
- *
- * This function is used as part of live lock prevention.
- * A periodic task is a task that results from a queue that
- * is set as type IX_QMGR_TYPE_REALTIME_PERIODIC. This function
- * should be called to indicate to the dispatcher that the
- * the periodic task is completed. This ensures that the notifications
- * for queues set as type sporadic queues are re-enabled.
- * This function is re-entrant.
- *
- */
-PUBLIC void
-ixQMgrPeriodicDone(void);
-
-
-/**
- * @ingroup IxQMgrAPI
- *
- * @fn ixQMgrLLPShow(int resetStats)
- *
- * @brief Print out the live lock prevention statistics when in debug mode.
- *
- * This function prints out statistics related to the livelock. These
- * statistics are only collected in debug mode.
- * This function is not re-entrant.
- *
- * @param resetStats @ref int [in] - if set the the stats are reset.
- *
- */
-PUBLIC void
-ixQMgrLLPShow(int resetStats);
-
-
-#endif /* IXQMGR_H */
-
-/**
- * @} defgroup IxQMgrAPI
- */
-
-
+++ /dev/null
-/**
- * @file IxQMgrAqmIf_p.h
- *
- * @author Intel Corporation
- * @date 30-Oct-2001
- *
- * @brief The IxQMgrAqmIf sub-component provides a number of inline
- * functions for performing I/O on the AQM.
- *
- * Because some functions contained in this module are inline and are
- * used in other modules (within the QMgr component) the definitions are
- * contained in this header file. The "normal" use of inline functions
- * is to use the inline functions in the module in which they are
- * defined. In this case these inline functions are used in external
- * modules and therefore the use of "inline extern". What this means
- * is as follows: if a function foo is declared as "inline extern"this
- * definition is only used for inlining, in no case is the function
- * compiled on its own. If the compiler cannot inline the function it
- * becomes an external reference. Therefore in IxQMgrAqmIf.c all
- * inline functions are defined without the "inline extern" specifier
- * and so define the external references. In all other modules these
- * funtions are defined as "inline extern".
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-#ifndef IXQMGRAQMIF_P_H
-#define IXQMGRAQMIF_P_H
-
-#include "IxOsalTypes.h"
-
-/*
- * inline definition
- */
-
-#ifdef IX_OSAL_INLINE_ALL
-/* If IX_OSAL_INLINE_ALL is set then each inlineable API functions will be defined as
- inline functions */
-#define IX_QMGR_AQMIF_INLINE IX_OSAL_INLINE_EXTERN
-#else
-#ifdef IXQMGRAQMIF_C
-#ifndef IX_QMGR_AQMIF_INLINE
-#define IX_QMGR_AQMIF_INLINE
-#endif
-#else
-#ifndef IX_QMGR_AQMIF_INLINE
-#define IX_QMGR_AQMIF_INLINE IX_OSAL_INLINE_EXTERN
-#endif
-#endif /* IXQMGRAQMIF_C */
-#endif /* IX_OSAL_INLINE */
-
-
-/*
- * User defined include files.
- */
-#include "IxQMgr.h"
-#include "IxQMgrLog_p.h"
-#include "IxQMgrQCfg_p.h"
-
-/* Because this file contains inline functions which will be compiled into
- * other components, we need to ensure that the IX_COMPONENT_NAME define
- * is set to ix_qmgr while this code is being compiled. This will ensure
- * that the correct implementation is provided for the memory access macros
- * IX_OSAL_READ_LONG and IX_OSAL_WRITE_LONG which are used in this file.
- * This must be done before including "IxOsalMemAccess.h"
- */
-#define IX_QMGR_AQMIF_SAVED_COMPONENT_NAME IX_COMPONENT_NAME
-#undef IX_COMPONENT_NAME
-#define IX_COMPONENT_NAME ix_qmgr
-#include "IxOsal.h"
-
-/*
- * #defines and macros used in this file.
- */
-
-/* Number of bytes per word */
-#define IX_QMGR_NUM_BYTES_PER_WORD 4
-
-/* Underflow bit mask */
-#define IX_QMGR_UNDERFLOW_BIT_OFFSET 0x0
-
-/* Overflow bit mask */
-#define IX_QMGR_OVERFLOW_BIT_OFFSET 0x1
-
-/* Queue access register, queue 0 */
-#define IX_QMGR_QUEACC0_OFFSET 0x0000
-
-/* Size of queue access register in words */
-#define IX_QMGR_QUEACC_SIZE 0x4/*words*/
-
-/* Queue status register, queues 0-7 */
-#define IX_QMGR_QUELOWSTAT0_OFFSET (IX_QMGR_QUEACC0_OFFSET +\
-(IX_QMGR_MAX_NUM_QUEUES * IX_QMGR_QUEACC_SIZE * IX_QMGR_NUM_BYTES_PER_WORD))
-
-/* Queue status register, queues 8-15 */
-#define IX_QMGR_QUELOWSTAT1_OFFSET (IX_QMGR_QUELOWSTAT0_OFFSET +\
- IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue status register, queues 16-23 */
-#define IX_QMGR_QUELOWSTAT2_OFFSET (IX_QMGR_QUELOWSTAT1_OFFSET +\
- IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue status register, queues 24-31 */
-#define IX_QMGR_QUELOWSTAT3_OFFSET (IX_QMGR_QUELOWSTAT2_OFFSET +\
- IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue status register Q status bits mask */
-#define IX_QMGR_QUELOWSTAT_QUE_STS_BITS_MASK 0xF
-
-/* Size of queue 0-31 status register */
-#define IX_QMGR_QUELOWSTAT_SIZE 0x4 /*words*/
-
-/* The number of queues' status specified per word */
-#define IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD 0x8
-
-/* Queue UF/OF status register queues 0-15 */
-#define IX_QMGR_QUEUOSTAT0_OFFSET (IX_QMGR_QUELOWSTAT3_OFFSET +\
- IX_QMGR_NUM_BYTES_PER_WORD)
-/* Queue UF/OF status register queues 16-31 */
-#define IX_QMGR_QUEUOSTAT1_OFFSET (IX_QMGR_QUEUOSTAT0_OFFSET +\
- IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* The number of queues' underflow/overflow status specified per word */
-#define IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD 0x10
-
-/* Queue NE status register, queues 32-63 */
-#define IX_QMGR_QUEUPPSTAT0_OFFSET (IX_QMGR_QUEUOSTAT1_OFFSET +\
- IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue F status register, queues 32-63 */
-#define IX_QMGR_QUEUPPSTAT1_OFFSET (IX_QMGR_QUEUPPSTAT0_OFFSET +\
- IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Size of queue 32-63 status register */
-#define IX_QMGR_QUEUPPSTAT_SIZE 0x2 /*words*/
-
-/* The number of queues' status specified per word */
-#define IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD 0x20
-
-/* Queue INT source select register, queues 0-7 */
-#define IX_QMGR_INT0SRCSELREG0_OFFSET (IX_QMGR_QUEUPPSTAT1_OFFSET +\
- IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue INT source select register, queues 8-15 */
-#define IX_QMGR_INT0SRCSELREG1_OFFSET (IX_QMGR_INT0SRCSELREG0_OFFSET+\
- IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue INT source select register, queues 16-23 */
-#define IX_QMGR_INT0SRCSELREG2_OFFSET (IX_QMGR_INT0SRCSELREG1_OFFSET+\
- IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue INT source select register, queues 24-31 */
-#define IX_QMGR_INT0SRCSELREG3_OFFSET (IX_QMGR_INT0SRCSELREG2_OFFSET+\
- IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Size of interrupt source select reegister */
-#define IX_QMGR_INT0SRCSELREG_SIZE 0x4 /*words*/
-
-/* The number of queues' interrupt source select specified per word*/
-#define IX_QMGR_INTSRC_NUM_QUE_PER_WORD 0x8
-
-/* Queue INT enable register, queues 0-31 */
-#define IX_QMGR_QUEIEREG0_OFFSET (IX_QMGR_INT0SRCSELREG3_OFFSET +\
- IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue INT enable register, queues 32-63 */
-#define IX_QMGR_QUEIEREG1_OFFSET (IX_QMGR_QUEIEREG0_OFFSET +\
- IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue INT register, queues 0-31 */
-#define IX_QMGR_QINTREG0_OFFSET (IX_QMGR_QUEIEREG1_OFFSET +\
- IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Queue INT register, queues 32-63 */
-#define IX_QMGR_QINTREG1_OFFSET (IX_QMGR_QINTREG0_OFFSET +\
- IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Size of interrupt register */
-#define IX_QMGR_QINTREG_SIZE 0x2 /*words*/
-
-/* Number of queues' status specified per word */
-#define IX_QMGR_QINTREG_NUM_QUE_PER_WORD 0x20
-
-/* Number of bits per queue interrupt status */
-#define IX_QMGR_QINTREG_BITS_PER_QUEUE 0x1
-#define IX_QMGR_QINTREG_BIT_OFFSET 0x1
-
-/* Size of address space not used by AQM */
-#define IX_QMGR_AQM_UNUSED_ADDRESS_SPACE_SIZE_IN_BYTES 0x1bC0
-
-/* Queue config register, queue 0 */
-#define IX_QMGR_QUECONFIG_BASE_OFFSET (IX_QMGR_QINTREG1_OFFSET +\
- IX_QMGR_NUM_BYTES_PER_WORD +\
- IX_QMGR_AQM_UNUSED_ADDRESS_SPACE_SIZE_IN_BYTES)
-
-/* Total size of configuration words */
-#define IX_QMGR_QUECONFIG_SIZE 0x100
-
-/* Start of SRAM queue buffer space */
-#define IX_QMGR_QUEBUFFER_SPACE_OFFSET (IX_QMGR_QUECONFIG_BASE_OFFSET +\
- IX_QMGR_MAX_NUM_QUEUES * IX_QMGR_NUM_BYTES_PER_WORD)
-
-/* Total bits in a word */
-#define BITS_PER_WORD 32
-
-/* Size of queue buffer space */
-#define IX_QMGR_QUE_BUFFER_SPACE_SIZE 0x1F00
-
-/*
- * This macro will return the address of the access register for the
- * queue specified by qId
- */
-#define IX_QMGR_Q_ACCESS_ADDR_GET(qId)\
- (((qId) * (IX_QMGR_QUEACC_SIZE * IX_QMGR_NUM_BYTES_PER_WORD))\
- + IX_QMGR_QUEACC0_OFFSET)
-
-/*
- * Bit location of bit-3 of INT0SRCSELREG0 register to enabled
- * sticky interrupt register.
- */
-#define IX_QMGR_INT0SRCSELREG0_BIT3 3
-
-/*
- * Variable declerations global to this file. Externs are followed by
- * statics.
- */
-extern UINT32 aqmBaseAddress;
-
-/*
- * Function declarations.
- */
-void
-ixQMgrAqmIfInit (void);
-
-void
-ixQMgrAqmIfUninit (void);
-
-unsigned
-ixQMgrAqmIfLog2 (unsigned number);
-
-void
-ixQMgrAqmIfQRegisterBitsWrite (IxQMgrQId qId,
- UINT32 registerBaseAddrOffset,
- unsigned queuesPerRegWord,
- UINT32 value);
-
-void
-ixQMgrAqmIfQStatusCheckValsCalc (IxQMgrQId qId,
- IxQMgrSourceId srcSel,
- unsigned int *statusWordOffset,
- UINT32 *checkValue,
- UINT32 *mask);
-/*
- * The Xscale software allways deals with logical addresses and so the
- * base address of the AQM memory space is not a hardcoded value. This
- * function must be called before any other function in this component.
- * NO CHECKING is performed to ensure that the base address has been
- * set.
- */
-void
-ixQMgrAqmIfBaseAddressSet (UINT32 address);
-
-/*
- * Get the base address of the AQM memory space.
- */
-void
-ixQMgrAqmIfBaseAddressGet (UINT32 *address);
-
-/*
- * Get the sram base address
- */
-void
-ixQMgrAqmIfSramBaseAddressGet (UINT32 *address);
-
-/*
- * Read a queue status
- */
-void
-ixQMgrAqmIfQueStatRead (IxQMgrQId qId,
- IxQMgrQStatus* status);
-
-
-/*
- * Set INT0SRCSELREG0 Bit3
- */
-void ixQMgrAqmIfIntSrcSelReg0Bit3Set (void);
-
-
-/*
- * Set the interrupt source
- */
-void
-ixQMgrAqmIfIntSrcSelWrite (IxQMgrQId qId,
- IxQMgrSourceId sourceId);
-
-/*
- * Enable interruptson a queue
- */
-void
-ixQMgrAqmIfQInterruptEnable (IxQMgrQId qId);
-
-/*
- * Disable interrupt on a quee
- */
-void
-ixQMgrAqmIfQInterruptDisable (IxQMgrQId qId);
-
-/*
- * Write the config register of the specified queue
- */
-void
-ixQMgrAqmIfQueCfgWrite (IxQMgrQId qId,
- IxQMgrQSizeInWords qSizeInWords,
- IxQMgrQEntrySizeInWords entrySizeInWords,
- UINT32 freeSRAMAddress);
-
-/*
- * read fields from the config of the specified queue.
- */
-void
-ixQMgrAqmIfQueCfgRead (IxQMgrQId qId,
- unsigned int numEntries,
- UINT32 *baseAddress,
- unsigned int *ne,
- unsigned int *nf,
- UINT32 *readPtr,
- UINT32 *writePtr);
-
-/*
- * Set the ne and nf watermark level on a queue.
- */
-void
-ixQMgrAqmIfWatermarkSet (IxQMgrQId qId,
- unsigned ne,
- unsigned nf);
-
-/* Inspect an entry without moving the read pointer */
-IX_STATUS
-ixQMgrAqmIfQPeek (IxQMgrQId qId,
- unsigned int entryIndex,
- unsigned int *entry);
-
-/* Modify an entry without moving the write pointer */
-IX_STATUS
-ixQMgrAqmIfQPoke (IxQMgrQId qId,
- unsigned int entryIndex,
- unsigned int *entry);
-
-/*
- * Function prototype for inline functions. For description refers to
- * the functions defintion below.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfWordWrite (VUINT32 *address,
- UINT32 word);
-
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfWordRead (VUINT32 *address,
- UINT32 *word);
-
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQPop (IxQMgrQId qId,
- IxQMgrQEntrySizeInWords numWords,
- UINT32 *entry);
-
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQPush (IxQMgrQId qId,
- IxQMgrQEntrySizeInWords numWords,
- UINT32 *entry);
-
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQStatusRegsRead (IxQMgrDispatchGroup group,
- UINT32 *qStatusWords);
-
-IX_QMGR_AQMIF_INLINE BOOL
-ixQMgrAqmIfQStatusCheck (UINT32 *oldQStatusWords,
- UINT32 *newQStatusWords,
- unsigned int statusWordOffset,
- UINT32 checkValue,
- UINT32 mask);
-
-IX_QMGR_AQMIF_INLINE BOOL
-ixQMgrAqmIfRegisterBitCheck (IxQMgrQId qId,
- UINT32 registerBaseAddrOffset,
- unsigned queuesPerRegWord,
- unsigned relativeBitOffset,
- BOOL reset);
-
-IX_QMGR_AQMIF_INLINE BOOL
-ixQMgrAqmIfUnderflowCheck (IxQMgrQId qId);
-
-IX_QMGR_AQMIF_INLINE BOOL
-ixQMgrAqmIfOverflowCheck (IxQMgrQId qId);
-
-IX_QMGR_AQMIF_INLINE UINT32
-ixQMgrAqmIfQRegisterBitsRead (IxQMgrQId qId,
- UINT32 registerBaseAddrOffset,
- unsigned queuesPerRegWord);
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQInterruptRegWrite (IxQMgrDispatchGroup group,
- UINT32 reg);
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQInterruptRegRead (IxQMgrDispatchGroup group,
- UINT32 *regVal);
-
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQueLowStatRead (IxQMgrQId qId,
- IxQMgrQStatus *status);
-
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQueUppStatRead (IxQMgrQId qId,
- IxQMgrQStatus *status);
-
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQueStatRead (IxQMgrQId qId,
- IxQMgrQStatus *qStatus);
-
-IX_QMGR_AQMIF_INLINE unsigned
-ixQMgrAqmIfPow2NumDivide (unsigned numerator,
- unsigned denominator);
-
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQInterruptEnableRegRead (IxQMgrDispatchGroup group,
- UINT32 *regVal);
-/*
- * Inline functions
- */
-
-/*
- * This inline function is used by other QMgr components to write one
- * word to the specified address.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfWordWrite (VUINT32 *address,
- UINT32 word)
-{
- IX_OSAL_WRITE_LONG(address, word);
-}
-
-/*
- * This inline function is used by other QMgr components to read a
- * word from the specified address.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfWordRead (VUINT32 *address,
- UINT32 *word)
-{
- *word = IX_OSAL_READ_LONG(address);
-}
-
-
-/*
- * This inline function is used by other QMgr components to pop an
- * entry off the specified queue.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQPop (IxQMgrQId qId,
- IxQMgrQEntrySizeInWords numWords,
- UINT32 *entry)
-{
- volatile UINT32 *accRegAddr;
-
- accRegAddr = (UINT32*)(aqmBaseAddress +
- IX_QMGR_Q_ACCESS_ADDR_GET(qId));
-
- switch (numWords)
- {
- case IX_QMGR_Q_ENTRY_SIZE1:
- ixQMgrAqmIfWordRead (accRegAddr, entry);
- break;
- case IX_QMGR_Q_ENTRY_SIZE2:
- ixQMgrAqmIfWordRead (accRegAddr++, entry++);
- ixQMgrAqmIfWordRead (accRegAddr, entry);
- break;
- case IX_QMGR_Q_ENTRY_SIZE4:
- ixQMgrAqmIfWordRead (accRegAddr++, entry++);
- ixQMgrAqmIfWordRead (accRegAddr++, entry++);
- ixQMgrAqmIfWordRead (accRegAddr++, entry++);
- ixQMgrAqmIfWordRead (accRegAddr, entry);
- break;
- default:
- IX_QMGR_LOG_ERROR0("Invalid Q Entry size passed to ixQMgrAqmIfQPop");
- break;
- }
-}
-
-/*
- * This inline function is used by other QMgr components to push an
- * entry to the specified queue.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQPush (IxQMgrQId qId,
- IxQMgrQEntrySizeInWords numWords,
- UINT32 *entry)
-{
- volatile UINT32 *accRegAddr;
-
- accRegAddr = (UINT32*)(aqmBaseAddress +
- IX_QMGR_Q_ACCESS_ADDR_GET(qId));
-
- switch (numWords)
- {
- case IX_QMGR_Q_ENTRY_SIZE1:
- ixQMgrAqmIfWordWrite (accRegAddr, *entry);
- break;
- case IX_QMGR_Q_ENTRY_SIZE2:
- ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);
- ixQMgrAqmIfWordWrite (accRegAddr, *entry);
- break;
- case IX_QMGR_Q_ENTRY_SIZE4:
- ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);
- ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);
- ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);
- ixQMgrAqmIfWordWrite (accRegAddr, *entry);
- break;
- default:
- IX_QMGR_LOG_ERROR0("Invalid Q Entry size passed to ixQMgrAqmIfQPush");
- break;
- }
-}
-
-/*
- * The AQM interrupt registers contains a bit for each AQM queue
- * specifying the queue (s) that cause an interrupt to fire. This
- * function is called by IxQMGrDispatcher component.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQStatusRegsRead (IxQMgrDispatchGroup group,
- UINT32 *qStatusWords)
-{
- volatile UINT32 *regAddress = NULL;
-
- if (group == IX_QMGR_QUELOW_GROUP)
- {
- regAddress = (UINT32*)(aqmBaseAddress +
- IX_QMGR_QUELOWSTAT0_OFFSET);
-
- ixQMgrAqmIfWordRead (regAddress++, qStatusWords++);
- ixQMgrAqmIfWordRead (regAddress++, qStatusWords++);
- ixQMgrAqmIfWordRead (regAddress++, qStatusWords++);
- ixQMgrAqmIfWordRead (regAddress, qStatusWords);
- }
- else /* We have the upper queues */
- {
- /* Only need to read the Nearly Empty status register for
- * queues 32-63 as for therse queues the interrtupt source
- * condition is fixed to Nearly Empty
- */
- regAddress = (UINT32*)(aqmBaseAddress +
- IX_QMGR_QUEUPPSTAT0_OFFSET);
- ixQMgrAqmIfWordRead (regAddress, qStatusWords);
- }
-}
-
-
-/*
- * This function check if the status for a queue has changed between
- * 2 snapshots and if it has, that the status matches a particular
- * value after masking.
- */
-IX_QMGR_AQMIF_INLINE BOOL
-ixQMgrAqmIfQStatusCheck (UINT32 *oldQStatusWords,
- UINT32 *newQStatusWords,
- unsigned int statusWordOffset,
- UINT32 checkValue,
- UINT32 mask)
-{
- if (((oldQStatusWords[statusWordOffset] & mask) !=
- (newQStatusWords[statusWordOffset] & mask)) &&
- ((newQStatusWords[statusWordOffset] & mask) == checkValue))
- {
- return TRUE;
- }
-
- return FALSE;
-}
-
-/*
- * The AQM interrupt register contains a bit for each AQM queue
- * specifying the queue (s) that cause an interrupt to fire. This
- * function is called by IxQMgrDispatcher component.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQInterruptRegRead (IxQMgrDispatchGroup group,
- UINT32 *regVal)
-{
- volatile UINT32 *regAddress;
-
- if (group == IX_QMGR_QUELOW_GROUP)
- {
- regAddress = (UINT32*)(aqmBaseAddress +
- IX_QMGR_QINTREG0_OFFSET);
- }
- else
- {
- regAddress = (UINT32*)(aqmBaseAddress +
- IX_QMGR_QINTREG1_OFFSET);
- }
-
- ixQMgrAqmIfWordRead (regAddress, regVal);
-}
-
-/*
- * The AQM interrupt enable register contains a bit for each AQM queue.
- * This function reads the interrupt enable register. This
- * function is called by IxQMgrDispatcher component.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQInterruptEnableRegRead (IxQMgrDispatchGroup group,
- UINT32 *regVal)
-{
- volatile UINT32 *regAddress;
-
- if (group == IX_QMGR_QUELOW_GROUP)
- {
- regAddress = (UINT32*)(aqmBaseAddress +
- IX_QMGR_QUEIEREG0_OFFSET);
- }
- else
- {
- regAddress = (UINT32*)(aqmBaseAddress +
- IX_QMGR_QUEIEREG1_OFFSET);
- }
-
- ixQMgrAqmIfWordRead (regAddress, regVal);
-}
-
-
-/*
- * This inline function will read the status bit of a queue
- * specified by qId. If reset is TRUE the bit is cleared.
- */
-IX_QMGR_AQMIF_INLINE BOOL
-ixQMgrAqmIfRegisterBitCheck (IxQMgrQId qId,
- UINT32 registerBaseAddrOffset,
- unsigned queuesPerRegWord,
- unsigned relativeBitOffset,
- BOOL reset)
-{
- UINT32 actualBitOffset;
- volatile UINT32 *registerAddress;
- UINT32 registerWord;
-
- /*
- * Calculate the registerAddress
- * multiple queues split accross registers
- */
- registerAddress = (UINT32*)(aqmBaseAddress +
- registerBaseAddrOffset +
- ((qId / queuesPerRegWord) *
- IX_QMGR_NUM_BYTES_PER_WORD));
-
- /*
- * Get the status word
- */
- ixQMgrAqmIfWordRead (registerAddress, ®isterWord);
-
- /*
- * Calculate the actualBitOffset
- * status for multiple queues stored in one register
- */
- actualBitOffset = (relativeBitOffset + 1) <<
- ((qId & (queuesPerRegWord - 1)) * (BITS_PER_WORD / queuesPerRegWord));
-
- /* Check if the status bit is set */
- if (registerWord & actualBitOffset)
- {
- /* Clear the bit if reset */
- if (reset)
- {
- ixQMgrAqmIfWordWrite (registerAddress, registerWord & (~actualBitOffset));
- }
- return TRUE;
- }
-
- /* Bit not set */
- return FALSE;
-}
-
-
-/*
- * @ingroup IxQmgrAqmIfAPI
- *
- * @brief Read the underflow status of a queue
- *
- * This inline function will read the underflow status of a queue
- * specified by qId.
- *
- */
-IX_QMGR_AQMIF_INLINE BOOL
-ixQMgrAqmIfUnderflowCheck (IxQMgrQId qId)
-{
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- return (ixQMgrAqmIfRegisterBitCheck (qId,
- IX_QMGR_QUEUOSTAT0_OFFSET,
- IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD,
- IX_QMGR_UNDERFLOW_BIT_OFFSET,
- TRUE/*reset*/));
- }
- else
- {
- /* Qs 32-63 have no underflow status */
- return FALSE;
- }
-}
-
-/*
- * This inline function will read the overflow status of a queue
- * specified by qId.
- */
-IX_QMGR_AQMIF_INLINE BOOL
-ixQMgrAqmIfOverflowCheck (IxQMgrQId qId)
-{
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- return (ixQMgrAqmIfRegisterBitCheck (qId,
- IX_QMGR_QUEUOSTAT0_OFFSET,
- IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD,
- IX_QMGR_OVERFLOW_BIT_OFFSET,
- TRUE/*reset*/));
- }
- else
- {
- /* Qs 32-63 have no overflow status */
- return FALSE;
- }
-}
-
-/*
- * This inline function will read the status bits of a queue
- * specified by qId.
- */
-IX_QMGR_AQMIF_INLINE UINT32
-ixQMgrAqmIfQRegisterBitsRead (IxQMgrQId qId,
- UINT32 registerBaseAddrOffset,
- unsigned queuesPerRegWord)
-{
- volatile UINT32 *registerAddress;
- UINT32 registerWord;
- UINT32 statusBitsMask;
- UINT32 bitsPerQueue;
-
- bitsPerQueue = BITS_PER_WORD / queuesPerRegWord;
-
- /*
- * Calculate the registerAddress
- * multiple queues split accross registers
- */
- registerAddress = (UINT32*)(aqmBaseAddress +
- registerBaseAddrOffset +
- ((qId / queuesPerRegWord) *
- IX_QMGR_NUM_BYTES_PER_WORD));
- /*
- * Read the status word
- */
- ixQMgrAqmIfWordRead (registerAddress, ®isterWord);
-
-
- /*
- * Calculate the mask for the status bits for this queue.
- */
- statusBitsMask = ((1 << bitsPerQueue) - 1);
-
- /*
- * Shift the status word so it is right justified
- */
- registerWord >>= ((qId & (queuesPerRegWord - 1)) * bitsPerQueue);
-
- /*
- * Mask out all bar the status bits for this queue
- */
- return (registerWord &= statusBitsMask);
-}
-
-/*
- * This function is called by IxQMgrDispatcher to set the contents of
- * the AQM interrupt register.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQInterruptRegWrite (IxQMgrDispatchGroup group,
- UINT32 reg)
-{
- volatile UINT32 *address;
-
- if (group == IX_QMGR_QUELOW_GROUP)
- {
- address = (UINT32*)(aqmBaseAddress +
- IX_QMGR_QINTREG0_OFFSET);
- }
- else
- {
- address = (UINT32*)(aqmBaseAddress +
- IX_QMGR_QINTREG1_OFFSET);
- }
-
- ixQMgrAqmIfWordWrite (address, reg);
-}
-
-/*
- * Read the status of a queue in the range 0-31.
- *
- * This function is used by other QMgr components to read the
- * status of the queue specified by qId.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQueLowStatRead (IxQMgrQId qId,
- IxQMgrQStatus *status)
-{
- /* Read the general status bits */
- *status = ixQMgrAqmIfQRegisterBitsRead (qId,
- IX_QMGR_QUELOWSTAT0_OFFSET,
- IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD);
-}
-
-/*
- * This function will read the status of the queue specified
- * by qId.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQueUppStatRead (IxQMgrQId qId,
- IxQMgrQStatus *status)
-{
- /* Reset the status bits */
- *status = 0;
-
- /*
- * Check if the queue is nearly empty,
- * N.b. QUPP stat register contains status for regs 32-63 at each
- * bit position so subtract 32 to get bit offset
- */
- if (ixQMgrAqmIfRegisterBitCheck ((qId - IX_QMGR_MIN_QUEUPP_QID),
- IX_QMGR_QUEUPPSTAT0_OFFSET,
- IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD,
- 0/*relativeBitOffset*/,
- FALSE/*!reset*/))
- {
- *status |= IX_QMGR_Q_STATUS_NE_BIT_MASK;
- }
-
- /*
- * Check if the queue is full,
- * N.b. QUPP stat register contains status for regs 32-63 at each
- * bit position so subtract 32 to get bit offset
- */
- if (ixQMgrAqmIfRegisterBitCheck ((qId - IX_QMGR_MIN_QUEUPP_QID),
- IX_QMGR_QUEUPPSTAT1_OFFSET,
- IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD,
- 0/*relativeBitOffset*/,
- FALSE/*!reset*/))
- {
- *status |= IX_QMGR_Q_STATUS_F_BIT_MASK;
- }
-}
-
-/*
- * This function is used by other QMgr components to read the
- * status of the queue specified by qId.
- */
-IX_QMGR_AQMIF_INLINE void
-ixQMgrAqmIfQueStatRead (IxQMgrQId qId,
- IxQMgrQStatus *qStatus)
-{
- if (qId < IX_QMGR_MIN_QUEUPP_QID)
- {
- ixQMgrAqmIfQueLowStatRead (qId, qStatus);
- }
- else
- {
- ixQMgrAqmIfQueUppStatRead (qId, qStatus);
- }
-}
-
-
-/*
- * This function performs a mod division
- */
-IX_QMGR_AQMIF_INLINE unsigned
-ixQMgrAqmIfPow2NumDivide (unsigned numerator,
- unsigned denominator)
-{
- /* Number is evenly divisable by 2 */
- return (numerator >> ixQMgrAqmIfLog2 (denominator));
-}
-
-/* Restore IX_COMPONENT_NAME */
-#undef IX_COMPONENT_NAME
-#define IX_COMPONENT_NAME IX_QMGR_AQMIF_SAVED_COMPONENT_NAME
-
-#endif/*IXQMGRAQMIF_P_H*/
+++ /dev/null
-/**
- * @file IxQMgrDefines_p.h
- *
- * @author Intel Corporation
- * @date 19-Jul-2002
- *
- * @brief IxQMgr Defines and tuneable constants
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-#ifndef IXQMGRDEFINES_P_H
-#define IXQMGRDEFINES_P_H
-
-#define IX_QMGR_PARM_CHECKS_ENABLED 1
-#define IX_QMGR_STATS_UPDATE_ENABLED 1
-
-#endif /* IXQMGRDEFINES_P_H */
+++ /dev/null
-/**
- * @file IxQMgrDispatcher_p.h
- *
- * @author Intel Corporation
- * @date 07-Feb-2002
- *
- * @brief This file contains the internal functions for dispatcher
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-#ifndef IXQMGRDISPATCHER_P_H
-#define IXQMGRDISPATCHER_P_H
-
-/*
- * User defined include files
- */
-#include "IxQMgr.h"
-
-/*
- * This structure defines the statistic data for a queue
- */
-typedef struct
-{
- unsigned callbackCnt; /* Call count of callback */
- unsigned priorityChangeCnt; /* Priority change count */
- unsigned intNoCallbackCnt; /* Interrupt fired but no callback set count */
- unsigned intLostCallbackCnt; /* Interrupt lost and detected ; SCR541 */
- BOOL notificationEnabled; /* Interrupt enabled for this queue */
- IxQMgrSourceId srcSel; /* interrupt source */
- unsigned enableCount; /* num times notif enabled by LLP */
- unsigned disableCount; /* num of times notif disabled by LLP */
-} IxQMgrDispatcherQStats;
-
-/*
- * This structure defines statistic data for the disatcher
- */
-typedef struct
- {
- unsigned loopRunCnt; /* ixQMgrDispatcherLoopRun count */
-
- IxQMgrDispatcherQStats queueStats[IX_QMGR_MAX_NUM_QUEUES];
-
-} IxQMgrDispatcherStats;
-
-/*
- * Initialise the dispatcher component
- */
-void
-ixQMgrDispatcherInit (void);
-
-/*
- * Get the dispatcher statistics
- */
-IxQMgrDispatcherStats*
-ixQMgrDispatcherStatsGet (void);
-
-/**
- * Retrieve the number of leading zero bits starting from the MSB
- * This function is implemented as an (extremely fast) asm routine
- * for XSCALE processor (see clz instruction) and as a (slower) C
- * function for other systems.
- */
-unsigned int
-ixQMgrCountLeadingZeros(unsigned int value);
-
-#endif/*IXQMGRDISPATCHER_P_H*/
-
-
+++ /dev/null
-/**
- * @file IxQMgrLog_p.h
- *
- * @author Intel Corporation
- * @date 07-Feb-2002
- *
- * @brief This file contains the internal functions for config
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-#ifndef IXQMGRLOG_P_H
-#define IXQMGRLOG_P_H
-
-/*
- * User defined header files
- */
-#include "IxOsal.h"
-
-/*
- * Macros
- */
-
-#define IX_QMGR_LOG0(string) do\
-{\
- ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, string, 0, 0, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG1(string, arg1) do\
-{\
- ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, string, (int)arg1, 0, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG2(string, arg1, arg2) do\
-{\
- ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, string, (int)arg1, (int)arg2, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG3(string, arg1, arg2, arg3) do\
-{\
- ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, string, (int)arg1, (int)arg2, (int)arg3, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG6(string, arg1, arg2, arg3, arg4, arg5, arg6) do\
-{\
- ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, string, (int)arg1, (int)arg2, (int)arg3, (int)arg4, (int)arg5, (int)arg6); \
-}while(0);
-
-#define IX_QMGR_LOG_WARNING0(string) do\
-{\
- ixOsalLog(IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, string, 0, 0, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG_WARNING1(string, arg1) do\
-{\
- ixOsalLog(IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, string, (int)arg1, 0, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG_WARNING2(string, arg1, arg2) do\
-{\
- ixOsalLog(IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, string, (int)arg1, (int)arg2, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG_ERROR0(string) do\
-{\
- ixOsalLog(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, string, 0, 0, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG_ERROR1(string, arg1) do\
-{\
- ixOsalLog(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, string, (int)arg1, 0, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG_ERROR2(string, arg1, arg2) do\
-{\
- ixOsalLog(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, string, (int)arg1, (int)arg2, 0, 0, 0, 0);\
-}while(0);
-
-#define IX_QMGR_LOG_ERROR3(string, arg1, arg2, arg3) do\
-{\
- ixOsalLog(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, string, (int)arg1, (int)arg2, (int)arg3, 0, 0, 0);\
-}while(0);
-#endif /* IX_QMGRLOG_P_H */
-
-
-
-
+++ /dev/null
-/**
- * @file IxQMgrQAccess_p.h
- *
- * @author Intel Corporation
- * @date 30-Oct-2001
- *
- * @brief QAccess private header file
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-#ifndef IXQMGRQACCESS_P_H
-#define IXQMGRQACCESS_P_H
-
-/*
- * User defined header files
- */
-#include "IxQMgr.h"
-
-/*
- * Global variables declarations.
- */
-extern volatile UINT32 * ixQMgrAqmIfQueAccRegAddr[];
-
-/*
- * Initialise the Queue Access component
- */
-void
-ixQMgrQAccessInit (void);
-
-/*
- * read the remainder of a multi-word queue entry
- * (the first word is already read)
- */
-IX_STATUS
-ixQMgrQReadMWordsMinus1 (IxQMgrQId qId,
- UINT32 *entry);
-
-/*
- * Fast access : pop a q entry from a single word queue
- */
-extern __inline__ UINT32 ixQMgrQAccessPop(IxQMgrQId qId);
-
-extern __inline__ UINT32 ixQMgrQAccessPop(IxQMgrQId qId)
-{
- return *(ixQMgrAqmIfQueAccRegAddr[qId]);
-}
-
-/*
- * Fast access : push a q entry in a single word queue
- */
-extern __inline__ void ixQMgrQAccessPush(IxQMgrQId qId, UINT32 entry);
-
-extern __inline__ void ixQMgrQAccessPush(IxQMgrQId qId, UINT32 entry)
-{
- *(ixQMgrAqmIfQueAccRegAddr[qId]) = entry;
-}
-
-#endif/*IXQMGRQACCESS_P_H*/
+++ /dev/null
-/**
- * @file IxQMgrQCfg_p.h
- *
- * @author Intel Corporation
- * @date 07-Feb-2002
- *
- * @brief This file contains the internal functions for config
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-#ifndef IXQMGRQCFG_P_H
-#define IXQMGRQCFG_P_H
-
-/*
- * User defined header files
- */
-#include "IxQMgr.h"
-
-/*
- * Typedefs
- */
-typedef struct
-{
- unsigned wmSetCnt;
-
- struct
- {
- char *qName;
- BOOL isConfigured;
- unsigned int qSizeInWords;
- unsigned int qEntrySizeInWords;
- unsigned int ne;
- unsigned int nf;
- unsigned int numEntries;
- UINT32 baseAddress;
- UINT32 readPtr;
- UINT32 writePtr;
- } qStats[IX_QMGR_MAX_NUM_QUEUES];
-
-} IxQMgrQCfgStats;
-
-/*
- * Initialize the QCfg subcomponent
- */
-void
-ixQMgrQCfgInit (void);
-
-/*
- * Uninitialize the QCfg subcomponent
- */
-void
-ixQMgrQCfgUninit (void);
-
-/*
- * Get the Q size in words
- */
-IxQMgrQSizeInWords
-ixQMgrQSizeInWordsGet (IxQMgrQId qId);
-
-/*
- * Get the Q entry size in words
- */
-IxQMgrQEntrySizeInWords
-ixQMgrQEntrySizeInWordsGet (IxQMgrQId qId);
-
-/*
- * Get the generic cfg stats
- */
-IxQMgrQCfgStats*
-ixQMgrQCfgStatsGet (void);
-
-/*
- * Get queue specific stats
- */
-IxQMgrQCfgStats*
-ixQMgrQCfgQStatsGet (IxQMgrQId qId);
-
-/*
- * Check is the queue configured
- */
-BOOL
-ixQMgrQIsConfigured(IxQMgrQId qId);
-
-#endif /* IX_QMGRQCFG_P_H */
+++ /dev/null
-/**
- * @file IxQueueAssignments.h
- *
- * @author Intel Corporation
- * @date 29-Oct-2004
- *
- * @brief Central definition for queue assignments
- *
- * Design Notes:
- * This file contains queue assignments used by Ethernet (EthAcc),
- * HSS (HssAcc), ATM (atmdAcc) and DMA (dmaAcc) access libraries.
- *
- * Note: Ethernet QoS traffic class definitions are managed separately
- * by EthDB in IxEthDBQoS.h.
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-#ifndef IxQueueAssignments_H
-#define IxQueueAssignments_H
-
-#include "IxQMgr.h"
-
-/***************************************************************************
- * Queue assignments for ATM
- ***************************************************************************/
-
-/**
- * @brief Global compiler switch to select between 3 possible NPE Modes
- * Define this macro to enable MPHY mode
- *
- * Default(No Switch) = MultiPHY Utopia2
- * IX_UTOPIAMODE = 1 for single Phy Utopia1
- * IX_MPHYSINGLEPORT = 1 for single Phy Utopia2
- */
-#define IX_NPE_MPHYMULTIPORT 1
-#if IX_UTOPIAMODE == 1
-#undef IX_NPE_MPHYMULTIPORT
-#endif
-#if IX_MPHYSINGLEPORT == 1
-#undef IX_NPE_MPHYMULTIPORT
-#endif
-
-/**
- * @def IX_NPE_A_TXDONE_QUEUE_HIGHWATERMARK
- *
- * @brief The NPE reserves the High Watermark for its operation. But it must be set by the Xscale
- */
-#define IX_NPE_A_TXDONE_QUEUE_HIGHWATERMARK 2
-
-/**
- * @def IX_NPE_A_QMQ_ATM_TX_DONE
- *
- * @brief Queue ID for ATM Transmit Done queue
- */
-#define IX_NPE_A_QMQ_ATM_TX_DONE IX_QMGR_QUEUE_1
-
-/**
- * @def IX_NPE_A_QMQ_ATM_TX0
- *
- * @brief Queue ID for ATM transmit Queue in a single phy configuration
- */
-#define IX_NPE_A_QMQ_ATM_TX0 IX_QMGR_QUEUE_2
-
-
-/**
- * @def IX_NPE_A_QMQ_ATM_TXID_MIN
- *
- * @brief Queue Manager Queue ID for ATM transmit Queue with minimum number of queue
- *
- */
-
-/**
- * @def IX_NPE_A_QMQ_ATM_TXID_MAX
- *
- * @brief Queue Manager Queue ID for ATM transmit Queue with maximum number of queue
- *
- */
-
-/**
- * @def IX_NPE_A_QMQ_ATM_RX_HI
- *
- * @brief Queue Manager Queue ID for ATM Receive high Queue
- *
- */
-
-/**
- * @def IX_NPE_A_QMQ_ATM_RX_LO
- *
- * @brief Queue Manager Queue ID for ATM Receive low Queue
- */
-
-#ifdef IX_NPE_MPHYMULTIPORT
-/**
- * @def IX_NPE_A_QMQ_ATM_TX1
- *
- * @brief Queue ID for ATM transmit Queue Multiphy from 1 to 11
- */
-#define IX_NPE_A_QMQ_ATM_TX1 IX_NPE_A_QMQ_ATM_TX0+1
-#define IX_NPE_A_QMQ_ATM_TX2 IX_NPE_A_QMQ_ATM_TX1+1
-#define IX_NPE_A_QMQ_ATM_TX3 IX_NPE_A_QMQ_ATM_TX2+1
-#define IX_NPE_A_QMQ_ATM_TX4 IX_NPE_A_QMQ_ATM_TX3+1
-#define IX_NPE_A_QMQ_ATM_TX5 IX_NPE_A_QMQ_ATM_TX4+1
-#define IX_NPE_A_QMQ_ATM_TX6 IX_NPE_A_QMQ_ATM_TX5+1
-#define IX_NPE_A_QMQ_ATM_TX7 IX_NPE_A_QMQ_ATM_TX6+1
-#define IX_NPE_A_QMQ_ATM_TX8 IX_NPE_A_QMQ_ATM_TX7+1
-#define IX_NPE_A_QMQ_ATM_TX9 IX_NPE_A_QMQ_ATM_TX8+1
-#define IX_NPE_A_QMQ_ATM_TX10 IX_NPE_A_QMQ_ATM_TX9+1
-#define IX_NPE_A_QMQ_ATM_TX11 IX_NPE_A_QMQ_ATM_TX10+1
-#define IX_NPE_A_QMQ_ATM_TXID_MIN IX_NPE_A_QMQ_ATM_TX0
-#define IX_NPE_A_QMQ_ATM_TXID_MAX IX_NPE_A_QMQ_ATM_TX11
-#define IX_NPE_A_QMQ_ATM_RX_HI IX_QMGR_QUEUE_21
-#define IX_NPE_A_QMQ_ATM_RX_LO IX_QMGR_QUEUE_22
-#else
-#define IX_NPE_A_QMQ_ATM_TXID_MIN IX_NPE_A_QMQ_ATM_TX0
-#define IX_NPE_A_QMQ_ATM_TXID_MAX IX_NPE_A_QMQ_ATM_TX0
-#define IX_NPE_A_QMQ_ATM_RX_HI IX_QMGR_QUEUE_10
-#define IX_NPE_A_QMQ_ATM_RX_LO IX_QMGR_QUEUE_11
-#endif /* MPHY */
-
-/**
- * @def IX_NPE_A_QMQ_ATM_FREE_VC0
- *
- * @brief Hardware QMgr Queue ID for ATM Free VC Queue.
- *
- * There are 32 Hardware QMgr Queue ID; from IX_NPE_A_QMQ_ATM_FREE_VC1 to
- * IX_NPE_A_QMQ_ATM_FREE_VC30
- */
-#define IX_NPE_A_QMQ_ATM_FREE_VC0 IX_QMGR_QUEUE_32
-#define IX_NPE_A_QMQ_ATM_FREE_VC1 IX_NPE_A_QMQ_ATM_FREE_VC0+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC2 IX_NPE_A_QMQ_ATM_FREE_VC1+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC3 IX_NPE_A_QMQ_ATM_FREE_VC2+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC4 IX_NPE_A_QMQ_ATM_FREE_VC3+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC5 IX_NPE_A_QMQ_ATM_FREE_VC4+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC6 IX_NPE_A_QMQ_ATM_FREE_VC5+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC7 IX_NPE_A_QMQ_ATM_FREE_VC6+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC8 IX_NPE_A_QMQ_ATM_FREE_VC7+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC9 IX_NPE_A_QMQ_ATM_FREE_VC8+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC10 IX_NPE_A_QMQ_ATM_FREE_VC9+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC11 IX_NPE_A_QMQ_ATM_FREE_VC10+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC12 IX_NPE_A_QMQ_ATM_FREE_VC11+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC13 IX_NPE_A_QMQ_ATM_FREE_VC12+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC14 IX_NPE_A_QMQ_ATM_FREE_VC13+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC15 IX_NPE_A_QMQ_ATM_FREE_VC14+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC16 IX_NPE_A_QMQ_ATM_FREE_VC15+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC17 IX_NPE_A_QMQ_ATM_FREE_VC16+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC18 IX_NPE_A_QMQ_ATM_FREE_VC17+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC19 IX_NPE_A_QMQ_ATM_FREE_VC18+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC20 IX_NPE_A_QMQ_ATM_FREE_VC19+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC21 IX_NPE_A_QMQ_ATM_FREE_VC20+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC22 IX_NPE_A_QMQ_ATM_FREE_VC21+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC23 IX_NPE_A_QMQ_ATM_FREE_VC22+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC24 IX_NPE_A_QMQ_ATM_FREE_VC23+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC25 IX_NPE_A_QMQ_ATM_FREE_VC24+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC26 IX_NPE_A_QMQ_ATM_FREE_VC25+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC27 IX_NPE_A_QMQ_ATM_FREE_VC26+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC28 IX_NPE_A_QMQ_ATM_FREE_VC27+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC29 IX_NPE_A_QMQ_ATM_FREE_VC28+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC30 IX_NPE_A_QMQ_ATM_FREE_VC29+1
-#define IX_NPE_A_QMQ_ATM_FREE_VC31 IX_NPE_A_QMQ_ATM_FREE_VC30+1
-
-/**
- * @def IX_NPE_A_QMQ_ATM_RXFREE_MIN
- *
- * @brief The minimum queue ID for FreeVC queue
- */
-#define IX_NPE_A_QMQ_ATM_RXFREE_MIN IX_NPE_A_QMQ_ATM_FREE_VC0
-
-/**
- * @def IX_NPE_A_QMQ_ATM_RXFREE_MAX
- *
- * @brief The maximum queue ID for FreeVC queue
- */
-#define IX_NPE_A_QMQ_ATM_RXFREE_MAX IX_NPE_A_QMQ_ATM_FREE_VC31
-
-/**
- * @def IX_NPE_A_QMQ_OAM_FREE_VC
- * @brief OAM Rx Free queue ID
- */
-#ifdef IX_NPE_MPHYMULTIPORT
-#define IX_NPE_A_QMQ_OAM_FREE_VC IX_QMGR_QUEUE_14
-#else
-#define IX_NPE_A_QMQ_OAM_FREE_VC IX_QMGR_QUEUE_3
-#endif /* MPHY */
-
-/****************************************************************************
- * Queue assignments for HSS
- ****************************************************************************/
-
-/**** HSS Port 0 ****/
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_CHL_RX_TRIG
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Channelized Receive trigger
- */
-#define IX_NPE_A_QMQ_HSS0_CHL_RX_TRIG IX_QMGR_QUEUE_12
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_RX
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_RX IX_QMGR_QUEUE_13
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_TX0
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 0
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_TX0 IX_QMGR_QUEUE_14
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_TX1
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 1
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_TX1 IX_QMGR_QUEUE_15
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_TX2
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 2
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_TX2 IX_QMGR_QUEUE_16
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_TX3
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 3
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_TX3 IX_QMGR_QUEUE_17
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE0
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 0
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE0 IX_QMGR_QUEUE_18
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE1
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 1
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE1 IX_QMGR_QUEUE_19
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE2
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 2
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE2 IX_QMGR_QUEUE_20
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE3
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 3
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE3 IX_QMGR_QUEUE_21
-
-/**
- * @def IX_NPE_A_QMQ_HSS0_PKT_TX_DONE
- *
- * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit Done queue
- */
-#define IX_NPE_A_QMQ_HSS0_PKT_TX_DONE IX_QMGR_QUEUE_22
-
-/**** HSS Port 1 ****/
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_CHL_RX_TRIG
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Channelized Receive trigger
- */
-#define IX_NPE_A_QMQ_HSS1_CHL_RX_TRIG IX_QMGR_QUEUE_10
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_RX
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_RX IX_QMGR_QUEUE_0
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_TX0
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 0
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_TX0 IX_QMGR_QUEUE_5
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_TX1
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 1
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_TX1 IX_QMGR_QUEUE_6
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_TX2
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 2
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_TX2 IX_QMGR_QUEUE_7
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_TX3
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 3
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_TX3 IX_QMGR_QUEUE_8
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE0
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 0
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE0 IX_QMGR_QUEUE_1
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE1
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 1
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE1 IX_QMGR_QUEUE_2
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE2
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 2
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE2 IX_QMGR_QUEUE_3
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE3
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 3
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE3 IX_QMGR_QUEUE_4
-
-/**
- * @def IX_NPE_A_QMQ_HSS1_PKT_TX_DONE
- *
- * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit Done queue
- */
-#define IX_NPE_A_QMQ_HSS1_PKT_TX_DONE IX_QMGR_QUEUE_9
-
-/*****************************************************************************************
- * Queue assignments for DMA
- *****************************************************************************************/
-
-#define IX_DMA_NPE_A_REQUEST_QID IX_QMGR_QUEUE_19 /**< Queue Id for NPE A DMA Request */
-#define IX_DMA_NPE_A_DONE_QID IX_QMGR_QUEUE_20 /**< Queue Id for NPE A DMA Done */
-#define IX_DMA_NPE_B_REQUEST_QID IX_QMGR_QUEUE_24 /**< Queue Id for NPE B DMA Request */
-#define IX_DMA_NPE_B_DONE_QID IX_QMGR_QUEUE_26 /**< Queue Id for NPE B DMA Done */
-#define IX_DMA_NPE_C_REQUEST_QID IX_QMGR_QUEUE_25 /**< Queue Id for NPE C DMA Request */
-#define IX_DMA_NPE_C_DONE_QID IX_QMGR_QUEUE_27 /**< Queue Id for NPE C DMA Done */
-
-
-/*****************************************************************************************
- * Queue assignments for Ethernet
- *
- * Note: Rx queue definitions, which include QoS traffic class definitions
- * are managed by EthDB and declared in IxEthDBQoS.h
- *****************************************************************************************/
-
-/**
-*
-* @def IX_ETH_ACC_RX_FRAME_ETH_Q
-*
-* @brief Eth0/Eth1 NPE Frame Recieve Q.
-*
-* @note THIS IS NOT USED - the Rx queues are read from EthDB QoS configuration
-*
-*/
-#define IX_ETH_ACC_RX_FRAME_ETH_Q (IX_QMGR_QUEUE_4)
-
-/**
-*
-* @def IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q
-*
-* @brief Supply Rx Buffers Ethernet Q for NPEB - Eth 0 - Port 1
-*
-*/
-#define IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q (IX_QMGR_QUEUE_27)
-
-/**
-*
-* @def IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q
-*
-* @brief Supply Rx Buffers Ethernet Q for NPEC - Eth 1 - Port 2
-*
-*/
-#define IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q (IX_QMGR_QUEUE_28)
-
-/**
-*
-* @def IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q
-*
-* @brief Supply Rx Buffers Ethernet Q for NPEA - Eth 2 - Port 3
-*
-*/
-#define IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q (IX_QMGR_QUEUE_26)
-
-
-/**
-*
-* @def IX_ETH_ACC_TX_FRAME_ENET0_Q
-*
-* @brief Submit frame Q for NPEB Eth 0 - Port 1
-*
-*/
-#define IX_ETH_ACC_TX_FRAME_ENET0_Q (IX_QMGR_QUEUE_24)
-
-
-/**
-*
-* @def IX_ETH_ACC_TX_FRAME_ENET1_Q
-*
-* @brief Submit frame Q for NPEC Eth 1 - Port 2
-*
-*/
-#define IX_ETH_ACC_TX_FRAME_ENET1_Q (IX_QMGR_QUEUE_25)
-
-/**
-*
-* @def IX_ETH_ACC_TX_FRAME_ENET2_Q
-*
-* @brief Submit frame Q for NPEA Eth 2 - Port 3
-*
-*/
-#define IX_ETH_ACC_TX_FRAME_ENET2_Q (IX_QMGR_QUEUE_23)
-
-/**
-*
-* @def IX_ETH_ACC_TX_FRAME_DONE_ETH_Q
-*
-* @brief Transmit complete Q for NPE Eth 0/1, Port 1&2
-*
-*/
-#define IX_ETH_ACC_TX_FRAME_DONE_ETH_Q (IX_QMGR_QUEUE_31)
-
-/*****************************************************************************************
- * Queue assignments for Crypto
- *****************************************************************************************/
-
-/** Crypto Service Request Queue */
-#define IX_CRYPTO_ACC_CRYPTO_REQ_Q (IX_QMGR_QUEUE_29)
-
-/** Crypto Service Done Queue */
-#define IX_CRYPTO_ACC_CRYPTO_DONE_Q (IX_QMGR_QUEUE_30)
-
-/** Crypto Req Q CB tag */
-#define IX_CRYPTO_ACC_CRYPTO_REQ_Q_CB_TAG (0)
-
-/** Crypto Done Q CB tag */
-#define IX_CRYPTO_ACC_CRYPTO_DONE_Q_CB_TAG (1)
-
-/** WEP Service Request Queue */
-#define IX_CRYPTO_ACC_WEP_REQ_Q (IX_QMGR_QUEUE_21)
-
-/** WEP Service Done Queue */
-#define IX_CRYPTO_ACC_WEP_DONE_Q (IX_QMGR_QUEUE_22)
-
-/** WEP Req Q CB tag */
-#define IX_CRYPTO_ACC_WEP_REQ_Q_CB_TAG (2)
-
-/** WEP Done Q CB tag */
-#define IX_CRYPTO_ACC_WEP_DONE_Q_CB_TAG (3)
-
-/** Number of queues allocate to crypto hardware accelerator services */
-#define IX_CRYPTO_ACC_NUM_OF_CRYPTO_Q (2)
-
-/** Number of queues allocate to WEP NPE services */
-#define IX_CRYPTO_ACC_NUM_OF_WEP_NPE_Q (2)
-
-/** Number of queues allocate to CryptoAcc component */
-#define IX_CRYPTO_ACC_NUM_OF_Q (IX_CRYPTO_ACC_NUM_OF_CRYPTO_Q + IX_CRYPTO_ACC_NUM_OF_WEP_NPE_Q)
-
-#endif /* IxQueueAssignments_H */
+++ /dev/null
-/**
- * @file IxSspAcc.h
- *
- * @brief Header file for the IXP400 SSP Serial Port Access (IxSspAcc)
- *
- * @version $Revision: 0.1 $
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxSspAcc IXP400 SSP Serial Port Access (IxSspAcc) API
- *
- * @brief IXP400 SSP Serial Port Access Public API
- *
- * @{
- */
-#ifndef IXSSPACC_H
-#define IXSSPACC_H
-
-#ifdef __ixp46X
-
-#include "IxOsal.h"
-
-/*
- * Section for enum
- */
-/**
- * @ingroup IxSspAcc
- *
- * @enum IxSspAccDataSize
- *
- * @brief The data sizes in bits that are supported by the protocol
- */
-typedef enum
-{
- DATA_SIZE_TOO_SMALL = 0x2,
- DATA_SIZE_4 = 0x3,
- DATA_SIZE_5,
- DATA_SIZE_6,
- DATA_SIZE_7,
- DATA_SIZE_8,
- DATA_SIZE_9,
- DATA_SIZE_10,
- DATA_SIZE_11,
- DATA_SIZE_12,
- DATA_SIZE_13,
- DATA_SIZE_14,
- DATA_SIZE_15,
- DATA_SIZE_16,
- DATA_SIZE_TOO_BIG
-} IxSspAccDataSize;
-
-/**
- * @ingroup IxSspAcc
- *
- * @enum IxSspAccPortStatus
- *
- * @brief The status of the SSP port to be set to enable/disable
- */
-typedef enum
-{
- SSP_PORT_DISABLE = 0x0,
- SSP_PORT_ENABLE,
- INVALID_SSP_PORT_STATUS
-} IxSspAccPortStatus;
-
-/**
- * @ingroup IxSspAcc
- *
- * @enum IxSspAccFrameFormat
- *
- * @brief The frame format that is to be used - SPI, SSP, or Microwire
- */
-typedef enum
-{
- SPI_FORMAT = 0x0,
- SSP_FORMAT,
- MICROWIRE_FORMAT,
- INVALID_FORMAT
-} IxSspAccFrameFormat;
-
-/**
- * @ingroup IxSspAcc
- *
- * @enum IxSspAccClkSource
- *
- * @brief The source to produce the SSP serial clock
- */
-typedef enum
-{
- ON_CHIP_CLK = 0x0,
- EXTERNAL_CLK,
- INVALID_CLK_SOURCE
-} IxSspAccClkSource;
-
-/**
- * @ingroup IxSspAcc
- *
- * @enum IxSspAccSpiSclkPhase
- *
- * @brief The SPI SCLK Phase:
- * 0 - SCLK is inactive one cycle at the start of a frame and 1/2 cycle at the
- * end of a frame.
- * 1 - SCLK is inactive 1/2 cycle at the start of a frame and one cycle at the
- * end of a frame.
- */
-typedef enum
-{
- START_ONE_END_HALF = 0x0,
- START_HALF_END_ONE,
- INVALID_SPI_PHASE
-} IxSspAccSpiSclkPhase;
-
-/**
- * @ingroup IxSspAcc
- *
- * @enum IxSspAccSpiSclkPolarity
- *
- * @brief The SPI SCLK Polarity can be set to either low or high.
- */
-typedef enum
-{
- SPI_POLARITY_LOW = 0x0,
- SPI_POLARITY_HIGH,
- INVALID_SPI_POLARITY
-} IxSspAccSpiSclkPolarity;
-
-/**
- * @ingroup IxSspAcc
- *
- * @enum IxSspAccMicrowireCtlWord
- *
- * @brief The Microwire control word can be either 8 or 16 bit.
- */
-typedef enum
-{
- MICROWIRE_8_BIT = 0x0,
- MICROWIRE_16_BIT,
- INVALID_MICROWIRE_CTL_WORD
-} IxSspAccMicrowireCtlWord;
-
-/**
- * @ingroup IxSspAcc
- *
- * @enum IxSspAccFifoThreshold
- *
- * @brief The threshold in frames (each frame is defined by IxSspAccDataSize)
- * that can be set for the FIFO to trigger a threshold exceed when
- * checking with the ExceedThresholdCheck functions or an interrupt
- * when it is enabled.
- */
-typedef enum
-{
- FIFO_TSHLD_1 = 0x0,
- FIFO_TSHLD_2,
- FIFO_TSHLD_3,
- FIFO_TSHLD_4,
- FIFO_TSHLD_5,
- FIFO_TSHLD_6,
- FIFO_TSHLD_7,
- FIFO_TSHLD_8,
- FIFO_TSHLD_9,
- FIFO_TSHLD_10,
- FIFO_TSHLD_11,
- FIFO_TSHLD_12,
- FIFO_TSHLD_13,
- FIFO_TSHLD_14,
- FIFO_TSHLD_15,
- FIFO_TSHLD_16,
- INVALID_FIFO_TSHLD
-} IxSspAccFifoThreshold;
-
-/**
- * @ingroup IxSspAcc
- *
- * @enum IX_SSP_STATUS
- *
- * @brief The statuses that can be returned in a SSP Serial Port Access
- */
-typedef enum
-{
- IX_SSP_SUCCESS = IX_SUCCESS, /**< Success status */
- IX_SSP_FAIL, /**< Fail status */
- IX_SSP_RX_FIFO_OVERRUN_HANDLER_MISSING, /**<
- Rx FIFO Overrun handler is NULL. */
- IX_SSP_RX_FIFO_HANDLER_MISSING, /**<
- Rx FIFO threshold hit or above handler is NULL
- */
- IX_SSP_TX_FIFO_HANDLER_MISSING, /**<
- Tx FIFO threshold hit or below handler is NULL
- */
- IX_SSP_FIFO_NOT_EMPTY_FOR_SETTING_CTL_CMD, /**<
- Tx FIFO not empty and therefore microwire
- control command size setting is not allowed. */
- IX_SSP_INVALID_FRAME_FORMAT_ENUM_VALUE, /**<
- frame format selected is invalid. */
- IX_SSP_INVALID_DATA_SIZE_ENUM_VALUE, /**<
- data size selected is invalid. */
- IX_SSP_INVALID_CLOCK_SOURCE_ENUM_VALUE, /**<
- source clock selected is invalid. */
- IX_SSP_INVALID_TX_FIFO_THRESHOLD_ENUM_VALUE, /**<
- Tx FIFO threshold selected is invalid. */
- IX_SSP_INVALID_RX_FIFO_THRESHOLD_ENUM_VALUE, /**<
- Rx FIFO threshold selected is invalid. */
- IX_SSP_INVALID_SPI_PHASE_ENUM_VALUE, /**<
- SPI phase selected is invalid. */
- IX_SSP_INVALID_SPI_POLARITY_ENUM_VALUE, /**<
- SPI polarity selected is invalid. */
- IX_SSP_INVALID_MICROWIRE_CTL_CMD_ENUM_VALUE, /**<
- Microwire control command selected is invalid
- */
- IX_SSP_INT_UNBIND_FAIL, /**< Interrupt unbind fail to unbind SSP
- interrupt */
- IX_SSP_INT_BIND_FAIL, /**< Interrupt bind fail during init */
- IX_SSP_RX_FIFO_NOT_EMPTY, /**<
- Rx FIFO not empty while trying to change data
- size. */
- IX_SSP_TX_FIFO_NOT_EMPTY, /**<
- Rx FIFO not empty while trying to change data
- size or microwire control command size. */
- IX_SSP_POLL_MODE_BLOCKING, /**<
- poll mode selected blocks interrupt mode from
- being selected. */
- IX_SSP_TX_FIFO_HIT_BELOW_THRESHOLD, /**<
- Tx FIFO level hit or below threshold. */
- IX_SSP_TX_FIFO_EXCEED_THRESHOLD, /**<
- Tx FIFO level exceeded threshold. */
- IX_SSP_RX_FIFO_HIT_ABOVE_THRESHOLD, /**<
- Rx FIFO level hit or exceeded threshold. */
- IX_SSP_RX_FIFO_BELOW_THRESHOLD, /**<
- Rx FIFO level below threshold. */
- IX_SSP_BUSY, /**< SSP is busy. */
- IX_SSP_IDLE, /**< SSP is idle. */
- IX_SSP_OVERRUN_OCCURRED, /**<
- SSP has experienced an overrun. */
- IX_SSP_NO_OVERRUN, /**<
- SSP did not experience an overrun. */
- IX_SSP_NOT_SUPORTED, /**< hardware does not support SSP */
- IX_SSP_NOT_INIT, /**< SSP Access not intialized */
- IX_SSP_NULL_POINTER /**< parameter passed in is NULL */
-} IX_SSP_STATUS;
-
-/**
- * @ingroup IxSspAcc
- *
- * @brief SSP Rx FIFO Overrun handler
- *
- * This function is called for the client to handle Rx FIFO Overrun that occurs
- * in the SSP hardware
- */
-typedef void (*RxFIFOOverrunHandler)(void);
-
-/**
- * @ingroup IxSspAcc
- *
- * @brief SSP Rx FIFO Threshold hit or above handler
- *
- * This function is called for the client to handle Rx FIFO threshold hit or
- * or above that occurs in the SSP hardware
- */
-typedef void (*RxFIFOThresholdHandler)(void);
-
-/**
- * @ingroup IxSspAcc
- *
- * @brief SSP Tx FIFO Threshold hit or below handler
- *
- * This function is called for the client to handle Tx FIFO threshold hit or
- * or below that occurs in the SSP hardware
- */
-typedef void (*TxFIFOThresholdHandler)(void);
-
-
-/*
- * Section for struct
- */
-/**
- * @ingroup IxSspAcc
- *
- * @brief contains all the variables required to initialize the SSP serial port
- * hardware.
- *
- * Structure to be filled and used for calling initialization
- */
-typedef struct
-{
- IxSspAccFrameFormat FrameFormatSelected;/**<Select between SPI, SSP and
- Microwire. */
- IxSspAccDataSize DataSizeSelected; /**<Select between 4 and 16. */
- IxSspAccClkSource ClkSourceSelected; /**<Select clock source to be
- on-chip or external. */
- IxSspAccFifoThreshold TxFIFOThresholdSelected;
- /**<Select Tx FIFO threshold
- between 1 to 16. */
- IxSspAccFifoThreshold RxFIFOThresholdSelected;
- /**<Select Rx FIFO threshold
- between 1 to 16. */
- BOOL RxFIFOIntrEnable; /**<Enable/disable Rx FIFO
- threshold interrupt. Disabling
- this interrupt will require
- the use of the polling function
- RxFIFOExceedThresholdCheck. */
- BOOL TxFIFOIntrEnable; /**<Enable/disable Tx FIFO
- threshold interrupt. Disabling
- this interrupt will require
- the use of the polling function
- TxFIFOExceedThresholdCheck. */
- RxFIFOThresholdHandler RxFIFOThsldHdlr; /**<Pointer to function to handle
- a Rx FIFO interrupt. */
- TxFIFOThresholdHandler TxFIFOThsldHdlr; /**<Pointer to function to handle
- a Tx FIFO interrupt. */
- RxFIFOOverrunHandler RxFIFOOverrunHdlr; /**<Pointer to function to handle
- a Rx FIFO overrun interrupt. */
- BOOL LoopbackEnable; /**<Select operation mode to be
- normal or loopback mode. */
- IxSspAccSpiSclkPhase SpiSclkPhaseSelected;
- /**<Select SPI SCLK phase to start
- with one inactive cycle and end
- with 1/2 inactive cycle or
- start with 1/2 inactive cycle
- and end with one inactive
- cycle. (Only used in
- SPI format). */
- IxSspAccSpiSclkPolarity SpiSclkPolaritySelected;
- /**<Select SPI SCLK idle state
- to be low or high. (Only used in
- SPI format). */
- IxSspAccMicrowireCtlWord MicrowireCtlWordSelected;
- /**<Select Microwire control
- format to be 8 or 16-bit. (Only
- used in Microwire format). */
- UINT8 SerialClkRateSelected; /**<Select between 0 (1.8432Mbps)
- and 255 (7.2Kbps). The
- formula used is Bit rate =
- 3.6864x10^6 /
- (2 x (SerialClkRateSelect + 1))
- */
-} IxSspInitVars;
-
-/**
- * @ingroup IxSspAcc
- *
- * @brief contains counters of the SSP statistics
- *
- * Structure contains all values of counters and associated overflows.
- */
-typedef struct
-{
- UINT32 ixSspRcvCounter; /**<Total frames received. */
- UINT32 ixSspXmitCounter; /**<Total frames transmitted. */
- UINT32 ixSspOverflowCounter;/**<Total occurrences of overflow. */
-} IxSspAccStatsCounters;
-
-
-/*
- * Section for prototypes interface functions
- */
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccInit (
- IxSspInitVars *initVarsSelected);
- *
- * @brief Initializes the SSP Access module.
- *
- * @param "IxSspAccInitVars [in] *initVarsSelected" - struct containing required
- * variables for initialization
- *
- * Global Data :
- * - None.
- *
- * This API will initialize the SSP Serial Port hardware to the user specified
- * configuration. Then it will enable the SSP Serial Port.
- * *NOTE*: Once interrupt or polling mode is selected, the mode cannot be
- * changed via the interrupt enable/disable function but the init needs to be
- * called again to change it.
- *
- * @return
- * - IX_SSP_SUCCESS - Successfully initialize and enable the SSP
- * serial port.
- * - IX_SSP_RX_FIFO_HANDLER_MISSING - interrupt mode is selected but RX FIFO
- * handler pointer is NULL
- * - IX_SSP_TX_FIFO_HANDLER_MISSING - interrupt mode is selected but TX FIFO
- * handler pointer is NULL
- * - IX_SSP_RX_FIFO_OVERRUN_HANDLER_MISSING - interrupt mode is selected but
- * RX FIFO Overrun handler pointer is NULL
- * - IX_SSP_RX_FIFO_NOT_EMPTY - Rx FIFO not empty, data size change is not
- * allowed.
- * - IX_SSP_TX_FIFO_NOT_EMPTY - Tx FIFO not empty, data size change is not
- * allowed.
- * - IX_SSP_INVALID_FRAME_FORMAT_ENUM_VALUE - frame format selected is invalid
- * - IX_SSP_INVALID_DATA_SIZE_ENUM_VALUE - data size selected is invalid
- * - IX_SSP_INVALID_CLOCK_SOURCE_ENUM_VALUE - clock source selected is invalid
- * - IX_SSP_INVALID_TX_FIFO_THRESHOLD_ENUM_VALUE - Tx FIFO threshold level
- * selected is invalid
- * - IX_SSP_INVALID_RX_FIFO_THRESHOLD_ENUM_VALUE - Rx FIFO threshold level
- * selected is invalid
- * - IX_SSP_INVALID_SPI_PHASE_ENUM_VALUE - SPI phase selected is invalid
- * - IX_SSP_INVALID_SPI_POLARITY_ENUM_VALUE - SPI polarity selected is invalid
- * - IX_SSP_INVALID_MICROWIRE_CTL_CMD_ENUM_VALUE - microwire control command
- * size is invalid
- * - IX_SSP_INT_UNBIND_FAIL - interrupt handler failed to unbind SSP interrupt
- * - IX_SSP_INT_BIND_FAIL - interrupt handler failed to bind to SSP interrupt
- * hardware trigger
- * - IX_SSP_NOT_SUPORTED - hardware does not support SSP
- * - IX_SSP_NULL_POINTER - parameter passed in is NULL
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccInit (IxSspInitVars *initVarsSelected);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccUninit (
- void)
- *
- * @brief Un-initializes the SSP Serial Port Access component
- *
- * @param - None
- *
- * Global Data :
- * - None.
- *
- * This API will disable the SSP Serial Port hardware. The client can call the
- * init function again if they wish to enable the SSP.
- *
- * @return
- * - IX_SSP_SUCCESS - successfully uninit SSP component
- * - IX_SSP_INT_UNBIND_FAIL - interrupt handler failed to unbind SSP interrupt
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccUninit (void);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccFIFODataSubmit (
- UINT16 *data,
- UINT32 amtOfData)
- *
- * @brief Inserts data into the SSP Serial Port's FIFO
- *
- * @param "UINT16 [in] *data" - pointer to the location to transmit the data
- * from
- * "UINT32 [in] amtOfData" - number of data to be transmitted.
- *
- * Global Data :
- * - None.
- *
- * This API will insert the amount of data specified by "amtOfData" from buffer
- * pointed to by "data" into the FIFO to be transmitted by the hardware.
- *
- * @return
- * - IX_SSP_SUCCESS - Data inserted successfully into FIFO
- * - IX_SSP_FAIL - FIFO insufficient space
- * - IX_SSP_NULL_POINTER - data pointer passed by client is NULL
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccFIFODataSubmit (
- UINT16* data,
- UINT32 amtOfData);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccFIFODataReceive (
- UINT16 *data,
- UINT32 amtOfData)
- *
- * @brief Extract data from the SSP Serial Port's FIFO
- *
- * @param "UINT16 [in] *data" - pointer to the location to receive the data into
- * "UINT32 [in] amtOfData" - number of data to be received.
- *
- * Global Data :
- * - None.
- *
- * This API will extract the amount of data specified by "amtOfData" from the
- * FIFO already received by the hardware into the buffer pointed to by "data".
- *
- * @return
- * - IX_SSP_SUCCESS - Data extracted successfully from FIFO
- * - IX_SSP_FAIL - FIFO has no data
- * - IX_SSP_NULL_POINTER - data pointer passed by client is NULL
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccFIFODataReceive (
- UINT16* data,
- UINT32 amtOfData);
-
-
-/**
- * Polling Functions
- */
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccTxFIFOHitOrBelowThresholdCheck (
- void)
- *
- * @brief Check if the Tx FIFO threshold has been hit or fallen below.
- *
- * @param - None
- *
- * Global Data :
- * - None.
- *
- * This API will return whether the Tx FIFO threshold has been exceeded or not
- *
- * @return
- * - IX_SSP_TX_FIFO_HIT_BELOW_THRESHOLD - Tx FIFO level hit or below threshold .
- * - IX_SSP_TX_FIFO_EXCEED_THRESHOLD - Tx FIFO level exceeded threshold.
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccTxFIFOHitOrBelowThresholdCheck (
- void);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccRxFIFOHitOrAboveThresholdCheck (
- void)
- *
- * @brief Check if the Rx FIFO threshold has been hit or exceeded.
- *
- * @param - None
- *
- * Global Data :
- * - None.
- *
- * This API will return whether the Rx FIFO level is below threshold or not
- *
- * @return
- * - IX_SSP_RX_FIFO_HIT_ABOVE_THRESHOLD - Rx FIFO level hit or exceeded threshold
- * - IX_SSP_RX_FIFO_BELOW_THRESHOLD - Rx FIFO level below threshold
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccRxFIFOHitOrAboveThresholdCheck (
- void);
-
-
-/**
- * Configuration functions
- *
- * NOTE: These configurations are not required to be called once init is called
- * unless configurations need to be changed on the fly.
- */
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccSSPPortStatusSet (
- IxSspAccPortStatus portStatusSelected)
- *
- * @brief Enables/disables the SSP Serial Port hardware.
- *
- * @param "IxSspAccPortStatus [in] portStatusSelected" - Set the SSP port to
- * enable or disable
- *
- * Global Data :
- * - None.
- *
- * This API will enable/disable the SSP Serial Port hardware.
- * NOTE: This function is called by init to enable the SSP after setting up the
- * configurations and by uninit to disable the SSP.
- *
- * @return
- * - IX_SSP_SUCCESS - Port status set with valid enum value
- * - IX_SSP_FAIL - invalid enum value
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccSSPPortStatusSet (
- IxSspAccPortStatus portStatusSelected);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccFrameFormatSelect (
- IxSspAccFrameFormat frameFormatSelected)
- *
- * @brief Sets the frame format for the SSP Serial Port hardware
- *
- * @param "IxSspAccFrameFormat [in] frameFormatSelected" - The frame format of
- * SPI, SSP or Microwire can be selected as the format
- *
- * Global Data :
- * - None.
- *
- * This API will set the format for the transfers via user input.
- * *NOTE*: The SSP hardware will be disabled to clear the FIFOs. Then its
- * previous state (enabled/disabled) restored after changing the format.
- *
- * @return
- * - IX_SSP_SUCCESS - frame format set with valid enum value
- * - IX_SSP_INVALID_FRAME_FORMAT_ENUM_VALUE - invalid frame format value
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccFrameFormatSelect (
- IxSspAccFrameFormat frameFormatSelected);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccDataSizeSelect (
- IxSspAccDataSize dataSizeSelected)
- *
- * @brief Sets the data size for transfers
- *
- * @param "IxSspAccDataSize [in] dataSizeSelected" - The data size between 4
- * and 16 that can be selected for data transfers
- *
- * Global Data :
- * - None.
- *
- * This API will set the data size for the transfers via user input. It will
- * disallow the change of the data size if either of the Rx/Tx FIFO is not
- * empty to prevent data loss.
- * *NOTE*: The SSP port will be disabled if the FIFOs are found to be empty and
- * if between the check and disabling of the SSP (which clears the
- * FIFOs) data is received into the FIFO, it might be lost.
- * *NOTE*: The FIFOs can be cleared by disabling the SSP Port if necessary to
- * force the data size change.
- *
- * @return
- * - IX_SSP_SUCCESS - data size set with valid enum value
- * - IX_SSP_RX_FIFO_NOT_EMPTY - Rx FIFO not empty, data size change is not
- * allowed.
- * - IX_SSP_TX_FIFO_NOT_EMPTY - Tx FIFO not empty, data size change is not
- * allowed.
- * - IX_SSP_INVALID_DATA_SIZE_ENUM_VALUE - invalid enum value
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccDataSizeSelect (
- IxSspAccDataSize dataSizeSelected);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccClockSourceSelect(
- IxSspAccClkSource clkSourceSelected)
- *
- * @brief Sets the clock source of the SSP Serial Port hardware
- *
- * @param "IxSspAccClkSource [in] clkSourceSelected" - The clock source from
- * either external source on on-chip can be selected as the source
- *
- * Global Data :
- * - None.
- *
- * This API will set the clock source for the transfers via user input.
- *
- * @return
- * - IX_SSP_SUCCESS - clock source set with valid enum value
- * - IX_SSP_INVALID_CLOCK_SOURCE_ENUM_VALUE - invalid enum value
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccClockSourceSelect (
- IxSspAccClkSource clkSourceSelected);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccSerialClockRateConfigure (
- UINT8 serialClockRateSelected)
- *
- * @brief Sets the on-chip Serial Clock Rate of the SSP Serial Port hardware.
- *
- * @param "UINT8 [in] serialClockRateSelected" - The serial clock rate that can
- * be set is between 7.2Kbps and 1.8432Mbps. The formula used is
- * Bit rate = 3.6864x10^6 / (2 x (SerialClockRateSelected + 1))
- *
- * Global Data :
- * - None.
- *
- * This API will set the serial clock rate for the transfers via user input.
- *
- * @return
- * - IX_SSP_SUCCESS - Serial clock rate configured successfully
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccSerialClockRateConfigure (
- UINT8 serialClockRateSelected);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccRxFIFOIntEnable (
- RxFIFOThresholdHandler rxFIFOIntrHandler)
- *
- * @brief Enables service request interrupt whenever the Rx FIFO hits its
- * threshold
- *
- * @param "void [in] *rxFIFOIntrHandler(UINT32)" - function pointer to the
- * interrupt handler for the Rx FIFO exceeded.
- *
- * Global Data :
- * - None.
- *
- * This API will enable the service request interrupt for the Rx FIFO
- *
- * @return
- * - IX_SSP_SUCCESS - Rx FIFO level interrupt enabled successfully
- * - IX_SSP_RX_FIFO_HANDLER_MISSING - missing handler for Rx FIFO level interrupt
- * - IX_SSP_POLL_MODE_BLOCKING - poll mode is selected at init, interrupt not
- * allowed to be enabled. Use init to enable interrupt mode.
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccRxFIFOIntEnable (
- RxFIFOThresholdHandler rxFIFOIntrHandler);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccRxFIFOIntDisable (
- void)
- *
- * @brief Disables service request interrupt of the Rx FIFO.
- *
- * @param - None
- *
- * Global Data :
- * - None.
- *
- * This API will disable the service request interrupt of the Rx FIFO.
- *
- * @return
- * - IX_SSP_SUCCESS - Rx FIFO Interrupt disabled successfully
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccRxFIFOIntDisable (
- void);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccTxFIFOIntEnable (
- TxFIFOThresholdHandler txFIFOIntrHandler)
- *
- * @brief Enables service request interrupt of the Tx FIFO.
- *
- * @param "void [in] *txFIFOIntrHandler(UINT32)" - function pointer to the
- * interrupt handler for the Tx FIFO exceeded.
- *
- * Global Data :
- * - None.
- *
- * This API will enable the service request interrupt of the Tx FIFO.
- *
- * @return
- * - IX_SSP_SUCCESS - Tx FIFO level interrupt enabled successfully
- * - IX_SSP_TX_FIFO_HANDLER_MISSING - missing handler for Tx FIFO level interrupt
- * - IX_SSP_POLL_MODE_BLOCKING - poll mode is selected at init, interrupt not
- * allowed to be enabled. Use init to enable interrupt mode.
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccTxFIFOIntEnable (
- TxFIFOThresholdHandler txFIFOIntrHandler);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccTxFIFOIntDisable (
- void)
- *
- * @brief Disables service request interrupt of the Tx FIFO
- *
- * @param - None
- *
- * Global Data :
- * - None.
- *
- * This API will disable the service request interrupt of the Tx FIFO
- *
- * @return
- * - IX_SSP_SUCCESS - Tx FIFO Interrupt disabled successfuly.
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccTxFIFOIntDisable (
- void);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccLoopbackEnable (
- BOOL loopbackEnable)
- *
- * @brief Enables/disables the loopback mode
- *
- * @param "BOOL [in] loopbackEnable" - True to enable and false to disable.
- *
- * Global Data :
- * - None.
- *
- * This API will set the mode of operation to either loopback or normal mode
- * according to the user input.
- *
- * @return
- * - IX_SSP_SUCCESS - Loopback enabled successfully
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccLoopbackEnable (
- BOOL loopbackEnable);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccSpiSclkPolaritySet (
- IxSspAccSpiSclkPolarity spiSclkPolaritySelected)
- *
- * @brief Sets the SPI SCLK Polarity to Low or High
- *
- * @param - "IxSspAccSpiSclkPolarity [in] spiSclkPolaritySelected" - SPI SCLK
- * polarity that can be selected to either high or low
- *
- * Global Data :
- * - None.
- *
- * This API is only used for the SPI frame format and will set the SPI SCLK polarity
- * to either low or high
- *
- * @return
- * - IX_SSP_SUCCESS - SPI Sclk polarity set with valid enum value
- * - IX_SSP_INVALID_SPI_POLARITY_ENUM_VALUE - invalid SPI polarity value
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccSpiSclkPolaritySet (
- IxSspAccSpiSclkPolarity spiSclkPolaritySelected);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccSpiSclkPhaseSet (
- IxSspAccSpiSclkPhase spiSclkPhaseSelected)
- *
- * @brief Sets the SPI SCLK Phase
- *
- * @param "IxSspAccSpiSclkPhase [in] spiSclkPhaseSelected" - Phase of either
- * the SCLK is inactive one cycle at the start of a frame and 1/2
- * cycle at the end of a frame, OR
- * the SCLK is inactive 1/2 cycle at the start of a frame and one
- * cycle at the end of a frame.
- *
- * Global Data :
- * - IX_SSP_SUCCESS - SPI Sclk phase set with valid enum value
- * - IX_SSP_INVALID_SPI_PHASE_ENUM_VALUE - invalid SPI phase value
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * This API is only used for the SPI frame format and will set the SPI SCLK
- * phase according to user input.
- *
- * @return
- * - None
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccSpiSclkPhaseSet (
- IxSspAccSpiSclkPhase spiSclkPhaseSelected);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccMicrowireControlWordSet (
- IxSspAccMicrowireCtlWord microwireCtlWordSelected)
- *
- * @brief Sets the Microwire control word to 8 or 16 bit format
- *
- * @param "IxSspAccMicrowireCtlWord [in] microwireCtlWordSelected" - Microwire
- * control word format can be either 8 or 16 bit format
- *
- * Global Data :
- * - None.
- *
- * This API is only used for the Microwire frame format and will set the
- * control word to 8 or 16 bit format
- *
- * @return
- * - IX_SSP_SUCCESS - Microwire Control Word set with valid enum value
- * - IX_SSP_TX_FIFO_NOT_EMPTY - Tx FIFO not empty, data size change is not
- * allowed.
- * - IX_SSP_INVALID_MICROWIRE_CTL_CMD_ENUM_VALUE - invalid enum value
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccMicrowireControlWordSet (
- IxSspAccMicrowireCtlWord microwireCtlWordSelected);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccTxFIFOThresholdSet (
- IxSspAccFifoThreshold txFIFOThresholdSelected)
- *
- * @brief Sets the Tx FIFO Threshold.
- *
- * @param "IxSspAccFifoThreshold [in] txFIFOThresholdSelected" - Threshold that
- * is set for a Tx FIFO service request to be triggered
- *
- * Global Data :
- * - None.
- *
- * This API will set the threshold for a Tx FIFO threshold to be triggered
- *
- * @return
- * - IX_SSP_SUCCESS - Tx FIFO Threshold set with valid enum value
- * - IX_SSP_INVALID_TX_FIFO_THRESHOLD_ENUM_VALUE - invalid enum value
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccTxFIFOThresholdSet (
- IxSspAccFifoThreshold txFIFOThresholdSelected);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccRxFIFOThresholdSet (
- IxSspAccFifoThreshold rxFIFOThresholdSelected)
- *
- * @brief Sets the Rx FIFO Threshold.
- *
- * @param "IxSspAccFifoThreshold [in] rxFIFOThresholdSelected" - Threshold that
- * is set for a Tx FIFO service request to be triggered
- *
- * Global Data :
- * - None.
- *
- * This API will will set the threshold for a Rx FIFO threshold to be triggered
- *
- * @return
- * - IX_SSP_SUCCESS - Rx FIFO Threshold set with valid enum value
- * - IX_SSP_INVALID_RX_FIFO_THRESHOLD_ENUM_VALUE - invalid enum value
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccRxFIFOThresholdSet (
- IxSspAccFifoThreshold rxFIFOThresholdSelected);
-
-
-/**
- * Debug functions
- */
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccStatsGet (
- IxSspAccStatsCounters *sspStats)
- *
- * @brief Returns the SSP Statistics through the pointer passed in
- *
- * @param "IxSspAccStatsCounters [in] *sspStats" - SSP statistics counter will
- * be read and written to the location pointed by this pointer.
- *
- * Global Data :
- * - None.
- *
- * This API will return the statistics counters of the SSP transfers.
- *
- * @return
- * - IX_SSP_SUCCESS - Stats obtained into the pointer provided successfully
- * - IX_SSP_FAIL - client provided pointer is NULL
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccStatsGet (
- IxSspAccStatsCounters *sspStats);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccStatsReset (
- void)
- *
- * @brief Resets the SSP Statistics
- *
- * @param - None
- *
- * Global Data :
- * - None.
- *
- * This API will reset the SSP statistics counters.
- *
- * @return
- * - None
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC void
-ixSspAccStatsReset (
- void);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccShow (
- void)
- *
- * @brief Display SSP status registers and statistics counters.
- *
- * @param - None
- *
- * Global Data :
- * - None.
- *
- * This API will display the status registers of the SSP and the statistics
- * counters.
- *
- * @return
- * - IX_SSP_SUCCESS - SSP show called successfully.
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccShow (
- void);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccSSPBusyCheck (
- void)
- *
- * @brief Determine the state of the SSP serial port hardware.
- *
- * @param - None
- *
- * Global Data :
- * - None.
- *
- * This API will return the state of the SSP serial port hardware - busy or
- * idle
- *
- * @return
- * - IX_SSP_BUSY - SSP is busy
- * - IX_SSP_IDLE - SSP is idle.
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccSSPBusyCheck (
- void);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccTxFIFOLevelGet (
- void)
- *
- * @brief Obtain the Tx FIFO's level
- *
- * @param - None
- *
- * Global Data :
- * - None.
- *
- * This API will return the level of the Tx FIFO
- *
- * @return
- * - 0..16; 0 can also mean SSP not initialized and will need to be init.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC UINT8
-ixSspAccTxFIFOLevelGet (
- void);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccRxFIFOLevelGet (
- void)
- *
- * @brief Obtain the Rx FIFO's level
- *
- * @param - None
- *
- * Global Data :
- * - None.
- *
- * This API will return the level of the Rx FIFO
- *
- * @return
- * - 0..16; 0 can also mean SSP not initialized and will need to be init.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC UINT8
-ixSspAccRxFIFOLevelGet (
- void);
-
-/**
- * @ingroup IxSspAcc
- *
- * @fn ixSspAccRxFIFOOverrunCheck (
- void)
- *
- * @brief Check if the Rx FIFO has overrun its FIFOs
- *
- * @param - None
- *
- * Global Data :
- * - None.
- *
- * This API will return whether the Rx FIFO has overrun its 16 FIFOs
- *
- * @return
- * - IX_SSP_OVERRUN_OCCURRED - Rx FIFO overrun occurred
- * - IX_SSP_NO_OVERRUN - Rx FIFO did not overrun
- * - IX_SSP_NOT_INIT - SSP not initialized. SSP init needs to be called.
- *
- * @li Reentrant : yes
- * @li ISR Callable : yes
- *
- */
-PUBLIC IX_SSP_STATUS
-ixSspAccRxFIFOOverrunCheck (
- void);
-
-#endif /* __ixp46X */
-#endif /* IXSSPACC_H */
+++ /dev/null
-/**
- * @file IxTimeSyncAcc.h
- *
- * @author Intel Corporation
- * @date 07 May 2004
- *
- * @brief Header file for IXP400 Access Layer to IEEE 1588(TM) Precision
- * Clock Synchronisation Protocol Hardware Assist
- *
- * @version 1
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxTimeSyncAcc IXP400 Time Sync Access Component API
- *
- * @brief Public API for IxTimeSyncAcc
- *
- * @{
- */
-#ifndef IXTIMESYNCACC_H
-#define IXTIMESYNCACC_H
-
-#ifdef __ixp46X
-
-#include "IxOsal.h"
-
-/**
- * Section for enum
- */
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @enum IxTimeSyncAccStatus
- *
- * @brief The status as returned from the API
- */
-typedef enum /**< IxTimeSyncAccStatus */
-{
- IX_TIMESYNCACC_SUCCESS = IX_SUCCESS, /**< Requested operation successful */
- IX_TIMESYNCACC_INVALIDPARAM, /**< An invalid parameter was passed */
- IX_TIMESYNCACC_NOTIMESTAMP, /**< While polling no time stamp available */
- IX_TIMESYNCACC_INTERRUPTMODEINUSE, /**< Polling not allowed while operating in interrupt mode */
- IX_TIMESYNCACC_FAILED /**< Internal error occurred */
-}IxTimeSyncAccStatus;
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @enum IxTimeSyncAccAuxMode
- *
- * @brief Master or Slave Auxiliary Time Stamp (Snap Shot)
- */
-typedef enum /**< IxTimeSyncAccAuxMode */
-{
- IX_TIMESYNCACC_AUXMODE_MASTER, /**< Auxiliary Master Mode */
- IX_TIMESYNCACC_AUXMODE_SLAVE, /**< Auxiliary Slave Mode */
- IX_TIMESYNCACC_AUXMODE_INVALID /**< Invalid Auxiliary Mode */
-}IxTimeSyncAccAuxMode;
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @enum IxTimeSyncAcc1588PTPPort
- *
- * @brief IEEE 1588 PTP Communication Port(Channel)
- */
-typedef enum /**< IxTimeSyncAcc1588PTPPort */
-{
- IX_TIMESYNCACC_NPE_A_1588PTP_PORT, /**< PTP Communication Port on NPE-A */
- IX_TIMESYNCACC_NPE_B_1588PTP_PORT, /**< PTP Communication Port on NPE-B */
- IX_TIMESYNCACC_NPE_C_1588PTP_PORT, /**< PTP Communication Port on NPE-C */
- IX_TIMESYNCACC_NPE_1588PORT_INVALID /**< Invalid PTP Communication Port */
-} IxTimeSyncAcc1588PTPPort;
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @enum IxTimeSyncAcc1588PTPPortMode
- *
- * @brief Master or Slave mode for IEEE 1588 PTP Communication Port
- */
-typedef enum /**< IxTimeSyncAcc1588PTPPortMode */
-{
- IX_TIMESYNCACC_1588PTP_PORT_MASTER, /**< PTP Communication Port in Master Mode */
- IX_TIMESYNCACC_1588PTP_PORT_SLAVE, /**< PTP Communication Port in Slave Mode */
- IX_TIMESYNCACC_1588PTP_PORT_ANYMODE, /**< PTP Communication Port in ANY Mode
- allows time stamping of all messages
- including non-1588 PTP */
- IX_TIMESYNCACC_1588PTP_PORT_MODE_INVALID /**< Invalid PTP Port Mode */
-}IxTimeSyncAcc1588PTPPortMode;
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @enum IxTimeSyncAcc1588PTPMsgType
- *
- * @brief 1588 PTP Messages types that can be detected on communication port
- *
- * Note that client code can determine this based on master/slave mode in which
- * it is already operating in and this information is made available for the sake
- * of convenience only.
- */
-typedef enum /**< IxTimeSyncAcc1588PTPMsgType */
-{
- IX_TIMESYNCACC_1588PTP_MSGTYPE_SYNC, /**< PTP Sync message sent by Master or received by Slave */
- IX_TIMESYNCACC_1588PTP_MSGTYPE_DELAYREQ, /**< PTP Delay_Req message sent by Slave or received by Master */
- IX_TIMESYNCACC_1588PTP_MSGTYPE_UNKNOWN /**< Other PTP and non-PTP message sent or received by both
- Master and/or Slave */
-} IxTimeSyncAcc1588PTPMsgType;
-
-/**
- * Section for struct
- */
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @struct IxTimeSyncAccTimeValue
- *
- * @brief Struct to hold 64 bit SystemTime and TimeStamp values
- */
-typedef struct /**< IxTimeSyncAccTimeValue */
-{
- UINT32 timeValueLowWord; /**< Lower 32 bits of the time value */
- UINT32 timeValueHighWord; /**< Upper 32 bits of the time value */
-} IxTimeSyncAccTimeValue;
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @struct IxTimeSyncAccUuid
- *
- * @brief Struct to hold 48 bit UUID values captured in Sync or Delay_Req messages
- */
-typedef struct /**< IxTimeSyncAccUuid */
-{
- UINT32 uuidValueLowWord; /**<The lower 32 bits of the UUID */
- UINT16 uuidValueHighHalfword; /**<The upper 16 bits of the UUID */
-} IxTimeSyncAccUuid;
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @struct IxTimeSyncAccPtpMsgData
- *
- * @brief Struct for data from the PTP message returned when TimeStamp available
- */
-typedef struct /**< IxTimeSyncAccPtpMsgData */
-{
- IxTimeSyncAcc1588PTPMsgType ptpMsgType; /**< PTP Messages type */
- IxTimeSyncAccTimeValue ptpTimeStamp; /**< 64 bit TimeStamp value from PTP Message */
- IxTimeSyncAccUuid ptpUuid; /**< 48 bit UUID value from the PTP Message */
- UINT16 ptpSequenceNumber; /**< 16 bit Sequence Number from PTP Message */
-} IxTimeSyncAccPtpMsgData;
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @struct IxTimeSyncAccStats
- *
- * @brief Statistics for the PTP messages
- */
-typedef struct /**< IxTimeSyncAccStats */
-{
- UINT32 rxMsgs; /**< Count of timestamps for received PTP Messages */
- UINT32 txMsgs; /**< Count of timestamps for transmitted PTP Messages */
-} IxTimeSyncAccStats;
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @typedef IxTimeSyncAccTargetTimeCallback
- *
- * @brief Callback for use by target time stamp interrupt
- */
-typedef void (*IxTimeSyncAccTargetTimeCallback)(IxTimeSyncAccTimeValue targetTime);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @typedef IxTimeSyncAccAuxTimeCallback
- *
- * @brief Callback for use by auxiliary time interrupts
- */
-typedef void (*IxTimeSyncAccAuxTimeCallback)(IxTimeSyncAccAuxMode auxMode,
- IxTimeSyncAccTimeValue auxTime);
-
-/*
- * Section for prototypes interface functions
- */
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccPTPPortConfigSet(
- IxTimeSyncAcc1588PTPPort ptpPort,
- IxTimeSyncAcc1588PTPPortMode ptpPortMode)
- *
- * @brief Configures the IEEE 1588 message detect on particular PTP port.
- *
- * @param ptpPort [in] - PTP port to config
- * @param ptpPortMode [in]- Port to operate in Master or Slave mode
- *
- * This API will enable the time stamping on a particular PTP port.
- *
- * @li Re-entrant : No
- * @li ISR Callable : No
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_INVALIDPARAM - Invalid parameters passed
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccPTPPortConfigSet(IxTimeSyncAcc1588PTPPort ptpPort,
- IxTimeSyncAcc1588PTPPortMode ptpPortMode);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccPTPPortConfigGet(
- IxTimeSyncAcc1588PTPPort ptpPort,
- IxTimeSyncAcc1588PTPPortMode *ptpPortMode)
- *
- * @brief Retrieves IEEE 1588 PTP operation mode on particular PTP port.
- *
- * @param ptpPort [in] - PTP port
- * @param ptpPortMode [in]- Mode of operation of PTP port (Master or Slave)
- *
- * This API will identify the time stamping capability of a PTP port by means
- * of obtaining its mode of operation.
- *
- * @li Re-entrant : No
- * @li ISR Callable : No
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_INVALIDPARAM - Invalid parameters passed
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccPTPPortConfigGet(IxTimeSyncAcc1588PTPPort ptpPort,
- IxTimeSyncAcc1588PTPPortMode *ptpPortMode);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccPTPRxPoll(
- IxTimeSyncAcc1588PTPPort ptpPort,
- IxTimeSyncAccPtpMsgData *ptpMsgData)
- *
- * @brief Polls the IEEE 1588 message/time stamp detect status on a particular
- * PTP Port on the Receive side.
- *
- * @param ptpPort [in] - PTP port to poll
- * @param ptpMsgData [out] - Current TimeStamp and other Data
- *
- * This API will poll for the availability of a time stamp on the received Sync
- * (Slave) or Delay_Req (Master) messages.
- * The client application will provide the buffer.
- *
- * @li Re-entrant : No
- * @li ISR Callable : No
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_INVALIDPARAM - Invalid parameters passed
- * @li IX_TIMESYNCACC_NOTIMESTAMP - No time stamp available
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccPTPRxPoll(IxTimeSyncAcc1588PTPPort ptpPort,
- IxTimeSyncAccPtpMsgData *ptpMsgData);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccPTPTxPoll(
- IxTimeSyncAcc1588PTPPort ptpPort,
- IxTimeSyncAccPtpMsgData *ptpMsgData)
- *
- *
- * @brief Polls the IEEE 1588 message/time stamp detect status on a particular
- * PTP Port on the Transmit side.
- *
- * @param ptpPort [in] - PTP port to poll
- * @param ptpMsgData [out] - Current TimeStamp and other Data
- *
- * This API will poll for the availability of a time stamp on the transmitted
- * Sync (Master) or Delay_Req (Slave) messages.
- * The client application will provide the buffer.
- *
- * @li Re-entrant : No
- * @li ISR Callable : No
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_INVALIDPARAM - Invalid parameters passed
- * @li IX_TIMESYNCACC_NOTIMESTAMP - No time stamp available
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccPTPTxPoll(IxTimeSyncAcc1588PTPPort ptpPort,
- IxTimeSyncAccPtpMsgData *ptpMsgData);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccSystemTimeSet(
- IxTimeSyncAccTimeValue systemTime)
- *
- * @brief Sets the System Time in the IEEE 1588 hardware assist block
- *
- * @param systemTime [in] - Value to set System Time
- *
- * This API will set the SystemTime to given value.
- *
- * @li Re-entrant : yes
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccSystemTimeSet(IxTimeSyncAccTimeValue systemTime);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccSystemTimeGet(
- IxTimeSyncAccTimeValue *systemTime)
- *
- * @brief Gets the System Time from the IEEE 1588 hardware assist block
- *
- * @param systemTime [out] - Copy the current System Time into the client
- * application provided buffer
- *
- * This API will get the SystemTime from IEEE1588 block and return to client
- *
- * @li Re-entrant : no
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_INVALIDPARAM - Invalid parameters passed
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccSystemTimeGet(IxTimeSyncAccTimeValue *systemTime);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccTickRateSet(
- UINT32 tickRate)
- *
- * @brief Sets the Tick Rate (Frequency Scaling Value) in the IEEE 1588
- * hardware assist block
- *
- * @param tickRate [in] - Value to set Tick Rate
- *
- * This API will set the Tick Rate (Frequency Scaling Value) in the IEEE
- * 1588 block to the given value. The Accumulator register (not client
- * visible) is incremented by this TickRate value every clock cycle. When
- * the Accumulator overflows, the SystemTime is incremented by one. This
- * TickValue can therefore be used to adjust the system timer.
- *
- * @li Re-entrant : yes
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccTickRateSet(UINT32 tickRate);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccTickRateGet(
- UINT32 *tickRate)
- *
- * @brief Gets the Tick Rate (Frequency Scaling Value) from the IEEE 1588
- * hardware assist block
- *
- * @param tickRate [out] - Current Tick Rate value in the IEEE 1588 block
- *
- * This API will get the TickRate on IEE15588 block. Refer to @ref
- * ixTimeSyncAccTickRateSet for notes on usage of this value.
- *
- * @li Reentrant : yes
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_INVALIDPARAM - Invalid parameters passed
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccTickRateGet(UINT32 *tickRate);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccTargetTimeInterruptEnable(
- IxTimeSyncAccTargetTimeCallback targetTimeCallback)
- *
- * @brief Enables the interrupt to verify the condition where the System Time
- * greater or equal to the Target Time in the IEEE 1588 hardware assist block.
- * If the condition is true an interrupt will be sent to XScale.
- *
- * @param targetTimeCallback [in] - Callback to be invoked when interrupt fires
- *
- * This API will enable the Target Time reached/hit condition interrupt.
- *
- * NOTE: The client application needs to ensure that the APIs
- * @ref ixTimeSyncAccTargetTimeInterruptEnable, @ref ixTimeSyncAccTargetTimeSet and
- * @ref ixTimeSyncAccTargetTimeInterruptDisable are accessed in mutual exclusive
- * manner with respect to each other.
- *
- * @li Re-entrant : no
- * @li ISR Callable : yes
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_INVALIDPARAM - Null parameter passed for callback
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccTargetTimeInterruptEnable(IxTimeSyncAccTargetTimeCallback targetTimeCallback);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccTargetTimeInterruptDisable(
- void)
- *
- * @brief Disables the interrupt for the condition explained in the function
- * description of @ref ixTimeSyncAccTargetTimeInterruptEnable.
- *
- * This API will disable the Target Time interrupt.
- *
- * NOTE: The client application needs to ensure that the APIs
- * @ref ixTimeSyncAccTargetTimeInterruptEnable, @ref ixTimeSyncAccTargetTimeSet and
- * @ref ixTimeSyncAccTargetTimeInterruptDisable are accessed in mutual exclusive
- * manner with respect to each other.
- *
- * @li Re-entrant : no
- * @li ISR Callable : yes
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccTargetTimeInterruptDisable(void);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccTargetTimePoll(
- BOOL *ttmPollFlag,
- IxTimeSyncAccTimeValue *targetTime)
- *
- * @brief Poll to verify the condition where the System Time greater or equal to
- * the Target Time in the IEEE 1588 hardware assist block. If the condition is
- * true an event flag is set in the hardware.
- *
- * @param ttmPollFlag [out] - TRUE if the target time reached/hit condition event set
- * FALSE if the target time reached/hit condition event is
- not set
- * @param targetTime [out] - Capture current targetTime into client provided buffer
- *
- * Poll the target time reached/hit condition status. Return true and the current
- * target time value, if the condition is true else return false.
- *
- * NOTE: The client application will need to clear the event flag that will be set
- * as long as the condition that the System Time greater or equal to the Target Time is
- * valid, in one of the following ways:
- * 1) Invoke the API to change the target time
- * 2) Change the system timer value
- *
- * @li Re-entrant : yes
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_INVALIDPARAM - Null parameter passed
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- * @li IX_TIMESYNCACC_INTERRUPTMODEINUSE - Interrupt mode in use
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccTargetTimePoll(BOOL *ttmPollFlag,
- IxTimeSyncAccTimeValue *targetTime);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccTargetTimeSet(
- IxTimeSyncAccTimeValue targetTime)
- *
- * @brief Sets the Target Time in the IEEE 1588 hardware assist block
- *
- * @param targetTime [in] - Value to set Target Time
- *
- * This API will set the Target Time to a given value.
- *
- * NOTE: The client application needs to ensure that the APIs
- * @ref ixTimeSyncAccTargetTimeInterruptEnable, @ref ixTimeSyncAccTargetTimeSet and
- * @ref ixTimeSyncAccTargetTimeInterruptDisable are accessed in mutual exclusive
- * manner with respect to each other.
- *
- * @li Reentrant : no
- * @li ISR Callable : yes
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccTargetTimeSet(IxTimeSyncAccTimeValue targetTime);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccTargetTimeGet(
- IxTimeSyncAccTimeValue *targetTime)
- *
- * @brief Gets the Target Time in the IEEE 1588 hardware assist block
- *
- * @param targetTime [out] - Copy current time to client provided buffer
- *
- * This API will get the Target Time from IEEE 1588 block and return to the
- * client application
- *
- * @li Re-entrant : yes
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_INVALIDPARAM - Null parameter passed
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccTargetTimeGet(IxTimeSyncAccTimeValue *targetTime);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccAuxTimeInterruptEnable(
- IxTimeSyncAccAuxMode auxMode,
- IxTimeSyncAccAuxTimeCallback auxTimeCallback)
- *
- * @brief Enables the interrupt notification for the given mode of Auxiliary Time
- * Stamp in the IEEE 1588 hardware assist block
- *
- * @param auxMode [in] - Auxiliary time stamp register (slave or master) to use
- * @param auxTimeCallback [in] - Callback to be invoked when interrupt fires
- *
- * This API will enable the Auxiliary Master/Slave Time stamp Interrupt.
- *
- * <pre>
- * NOTE: 1) An individual callback is to be registered for each Slave and Master
- * Auxiliary Time Stamp registers. Thus to register for both Master and Slave time
- * stamp interrupts either the same callback or two separate callbacks the API has
- * to be invoked twice.
- * 2) On the IXDP465 Development Platform, the Auxiliary Timestamp signal for
- * slave mode is tied to GPIO 8 pin. This signal is software routed by default to
- * PCI for backwards compatibility with the IXDP425 Development Platform. This
- * routing must be disabled for the auxiliary slave time stamp register to work
- * properly. The following commands may be used to accomplish this. However, refer
- * to the IXDP465 Development Platform Users Guide or the BSP/LSP documentation for
- * more specific information.
- *
- * For Linux (at the Redboot prompt i.e., before loading zImage):
- * mfill -b 0x54100000 -1 -l 1 -p 8
- * mfill -b 0x54100001 -1 -l 1 -p 0x7f
- * For vxWorks, at the prompt:
- * intDisable(25)
- * ixdp400FpgaIODetach(8)
- * </pre>
- *
- * @li Re-entrant : no
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_INVALIDPARAM - Null parameter passed for callback or
- invalid auxiliary snapshot mode
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccAuxTimeInterruptEnable(IxTimeSyncAccAuxMode auxMode,
- IxTimeSyncAccAuxTimeCallback auxTimeCallback);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccAuxTimeInterruptDisable(
- IxTimeSyncAccAuxMode auxMode)
- *
- * @brief Disables the interrupt for the indicated mode of Auxiliary Time Stamp
- * in the IEEE 1588 hardware assist block
- *
- * @param auxMode [in] - Auxiliary time stamp mode (slave or master) using which
- * the interrupt will be disabled.
- *
- * This API will disable the Auxiliary Time Stamp Interrupt (Master or Slave)
- *
- * @li Re-entrant : yes
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_INVALIDPARAM - Invalid parameters passed
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccAuxTimeInterruptDisable(IxTimeSyncAccAuxMode auxMode);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccAuxTimePoll(
- IxTimeSyncAccAuxMode auxMode,
- BOOL *auxPollFlag,
- IxTimeSyncAccTimeValue *auxTime)
- *
- * @brief Poll for the Auxiliary Time Stamp captured for the mode indicated
- * (Master or Slave)
- *
- * @param auxMode [in] - Auxiliary Snapshot Register (Slave or Master) to be checked
- * @param auxPollFlag [out] - TRUE if the time stamp captured in auxiliary
- snapshot register
- * FALSE if the time stamp not captured in
- auxiliary snapshot register
- * @param auxTime [out] - Copy the current Auxiliary Snapshot Register value into the
- * client provided buffer
- *
- * Polls for the Time stamp in the appropriate Auxiliary Snapshot Registers based
- * on the mode specified. Return true and the contents of the Auxiliary snapshot,
- * if it is available else return false.
- *
- * Please refer to the note #2 of the API @ref ixTimeSyncAccAuxTimeInterruptEnable
- * for more information for Auxiliary Slave mode.
- *
- * @li Re-entrant : yes
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_INVALIDPARAM - Null parameter passed for auxPollFlag,
- callback or invalid auxiliary snapshot mode
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- * @li IX_TIMESYNCACC_INTERRUPTMODEINUSE - Interrupt mode in use
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccAuxTimePoll(IxTimeSyncAccAuxMode auxMode,
- BOOL *auxPollFlag,
- IxTimeSyncAccTimeValue *auxTime);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccReset(void)
- *
- * @brief Resets the IEEE 1588 hardware assist block
- *
- * Sets the reset bit in the IEEE1588 silicon which fully resets the silicon block
- *
- * @li Reentrant : yes
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccReset(void);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccStatsGet(IxTimeSyncAccStats
- *timeSyncStats)
- *
- * @brief Returns the IxTimeSyncAcc Statistics in the client supplied buffer
- *
- * @param timeSyncStats [out] - TimeSync statistics counter values
- *
- * This API will return the statistics of the received or transmitted messages.
- *
- * NOTE: 1) These counters are updated only when the client polls for the time
- * stamps or interrupt are enabled. This is because the IxTimeSyncAcc module
- * does not either transmit or receive messages and does only run the code
- * when explicit requests received by client application.
- *
- * 2) These statistics reflect the number of valid PTP messages exchanged
- * in Master and Slave modes but includes all the messages (including valid
- * non-PTP messages) while operating in the Any mode.
- *
- * @li Reentrant : no
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_INVALIDPARAM - NULL parameter passed
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccStatsGet(IxTimeSyncAccStats *timeSyncStats);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn void ixTimeSyncAccStatsReset(void)
- *
- * @brief Reset Time Sync statistics
- *
- * This API will reset the statistics counters of the TimeSync access layer.
- *
- * @li Reentrant : yes
- * @li ISR Callable: no
- *
- * @return @li None
- */
-PUBLIC void
-ixTimeSyncAccStatsReset(void);
-
-/**
- * @ingroup IxTimeSyncAcc
- *
- * @fn IxTimeSyncAccStatus ixTimeSyncAccShow(void)
- *
- * @brief Displays the Time Sync current status
- *
- * This API will display status on the current configuration of the IEEE
- * 1588 hardware assist block, contents of the various time stamp registers,
- * outstanding interrupts and/or events.
- *
- * Note that this is intended for debug only, and in contrast to the other
- * functions, it does not clear the any of the status bits associated with
- * active timestamps and so is passive in its nature.
- *
- * @li Reentrant : yes
- * @li ISR Callable : no
- *
- * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful
- * @li IX_TIMESYNCACC_FAILED - Internal error occurred
- */
-PUBLIC IxTimeSyncAccStatus
-ixTimeSyncAccShow(void);
-
-#endif /* __ixp46X */
-#endif /* IXTIMESYNCACC_H */
-
-/**
- * @} defgroup IxTimeSyncAcc
- */
-
+++ /dev/null
-/**
- * @file IxTimerCtrl.h
- * @brief
- * This is the header file for the Timer Control component.
- *
- * The timer callback control component provides a mechanism by which different
- * client components can start a timer and have a supplied callback function
- * invoked when the timer expires.
- * The callbacks are all dispatched from one thread inside this component.
- * Any component that needs to be called periodically should use this facility
- * rather than create its own task with a sleep loop.
- *
- * @par
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxTimerCtrl IXP400 Timer Control (IxTimerCtrl) API
- *
- * @brief The public API for the IXP400 Timer Control Component.
- *
- * @{
- */
-
-#ifndef IxTimerCtrl_H
-#define IxTimerCtrl_H
-
-
-#include "IxTypes.h"
-/* #include "Ossl.h" */
-
-/*
- * #defines and macros used in this file.
- */
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @def IX_TIMERCTRL_NO_FREE_TIMERS
- *
- * @brief Timer schedule return code.
- *
- * Indicates that the request to start a timer failed because
- * all available timer resources are used.
- */
-#define IX_TIMERCTRL_NO_FREE_TIMERS 2
-
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @def IX_TIMERCTRL_PARAM_ERROR
- *
- * @brief Timer schedule return code.
- *
- * Indicates that the request to start a timer failed because
- * the client has supplied invalid parameters.
- */
-#define IX_TIMERCTRL_PARAM_ERROR 3
-
-
-/*
- * Typedefs whose scope is limited to this file.
- */
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @brief A typedef for a pointer to a timer callback function.
- * @para void * - This parameter is supplied by the client when the
- * timer is started and passed back to the client in the callback.
- * @note in general timer callback functions should not block or
- * take longer than 100ms. This constraint is required to ensure that
- * higher priority callbacks are not held up.
- * All callbacks are called from the same thread.
- * This thread is a shared resource.
- * The parameter passed is provided when the timer is scheduled.
- */
-typedef void (*IxTimerCtrlTimerCallback)(void *userParam);
-
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @brief List used to identify the users of timers.
- * @note The order in this list indicates priority. Components appearing
- * higher in the list will be given priority over components lower in the
- * list. When adding components, please insert at an appropriate position
- * for priority ( i.e values should be less than IxTimerCtrlMaxPurpose ) .
- */
-typedef enum
-{
- IxTimerCtrlAdslPurpose,
- /* Insert new purposes above this line only
- */
- IxTimerCtrlMaxPurpose
-}
-IxTimerCtrlPurpose;
-
-
-/*
- * Function definition
- */
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @fn ixTimerCtrlSchedule(IxTimerCtrlTimerCallback func,
- void *userParam,
- IxTimerCtrlPurpose purpose,
- UINT32 relativeTime,
- unsigned *timerId )
- *
- * @brief Schedules a callback function to be called after a period of "time".
- * The callback function should not block or run for more than 100ms.
- * This function
- *
- * @param func @ref IxTimerCtrlTimerCallback [in] - the callback function to be called.
- * @param userParam void [in] - a parameter to send to the callback function, can be NULL.
- * @param purpose @ref IxTimerCtrlPurpose [in] - the purpose of the callback, internally this component will
- * decide the priority of callbacks with different purpose.
- * @param relativeTime UINT32 [in] - time relative to now in milliseconds after which the callback
- * will be called. The time must be greater than the duration of one OS tick.
- * @param *timerId unsigned [out] - An id for the callback scheduled.
- * This id can be used to cancel the callback.
- * @return
- * @li IX_SUCCESS - The timer was started successfully.
- * @li IX_TIMERCTRL_NO_FREE_TIMERS - The timer was not started because the maximum number
- * of running timers has been exceeded.
- * @li IX_TIMERCTRL_PARAM_ERROR - The timer was not started because the client has supplied
- * a NULL callback func, or the requested timeout is less than one OS tick.
- * @note This function is re-entrant. The function accesses a list of running timers
- * and may suspend the calling thread if this list is being accesed by another thread.
- */
-PUBLIC IX_STATUS
-ixTimerCtrlSchedule(IxTimerCtrlTimerCallback func,
- void *userParam,
- IxTimerCtrlPurpose purpose,
- UINT32 relativeTime,
- unsigned *timerId );
-
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @fn ixTimerCtrlScheduleRepeating(IxTimerCtrlTimerCallback func,
- void *param,
- IxTimerCtrlPurpose purpose,
- UINT32 interval,
- unsigned *timerId )
- *
- * @brief Schedules a callback function to be called after a period of "time".
- * The callback function should not block or run for more than 100ms.
- *
- * @param func @ref IxTimerCtrlTimerCallback [in] - the callback function to be called.
- * @param userParam void [in] - a parameter to send to the callback function, can be NULL.
- * @param purpose @ref IxTimerCtrlPurpose [in] - the purpose of the callback, internally this component will
- * decide the priority of callbacks with different purpose.
- * @param interval UINT32 [in] - the interval in milliseconds between calls to func.
- * @param timerId unsigned [out] - An id for the callback scheduled.
- * This id can be used to cancel the callback.
- * @return
- * @li IX_SUCCESS - The timer was started successfully.
- * @li IX_TIMERCTRL_NO_FREE_TIMERS - The timer was not started because the maximum number
- * of running timers has been exceeded.
- * @li IX_TIMERCTRL_PARAM_ERROR - The timer was not started because the client has supplied
- * a NULL callback func, or the requested timeout is less than one OS tick.
- * @note This function is re-entrant. The function accesses a list of running timers
- * and may suspend the calling thread if this list is being accesed by another thread.
- */
-PUBLIC IX_STATUS
-ixTimerCtrlScheduleRepeating(IxTimerCtrlTimerCallback func,
- void *param,
- IxTimerCtrlPurpose purpose,
- UINT32 interval,
- unsigned *timerId );
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @fn ixTimerCtrlCancel (unsigned id)
- *
- * @brief Cancels a scheduled callback.
- *
- * @param id unsigned [in] - the id of the callback to be cancelled.
- * @return
- * @li IX_SUCCESS - The timer was successfully stopped.
- * @li IX_FAIL - The id parameter did not corrrespond to any running timer..
- * @note This function is re-entrant. The function accesses a list of running timers
- * and may suspend the calling thread if this list is being accesed by another thread.
- */
-PUBLIC IX_STATUS
-ixTimerCtrlCancel (unsigned id);
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @fn ixTimerCtrlInit(void)
- *
- * @brief Initialise the Timer Control Component.
- * @return
- * @li IX_SUCCESS - The timer control component initialized successfully.
- * @li IX_FAIL - The timer control component initialization failed,
- * or the component was already initialized.
- * @note This must be done before any other API function is called.
- * This function should be called once only and is not re-entrant.
- */
-PUBLIC IX_STATUS
-ixTimerCtrlInit(void);
-
-
-/**
- * @ingroup IxTimerCtrl
- *
- * @fn ixTimerCtrlShow( void )
- *
- * @brief Display the status of the Timer Control Component.
- * @return void
- * @note Displays a list of running timers.
- * This function is not re-entrant. This function does not suspend the calling thread.
- */
-PUBLIC void
-ixTimerCtrlShow( void );
-
-#endif /* IXTIMERCTRL_H */
-
+++ /dev/null
-/**
- * @file IxTypes.h (Replaced by OSAL)
- *
- * @date 28-NOV-2001
-
- * @brief This file contains basic types used by the IXP400 software
- *
- * Design Notes:
- * This file shall only include fundamental types and definitions to be
- * shared by all the IXP400 components.
- * Please DO NOT add component-specific types here.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxTypes IXP400 Types (IxTypes)
- *
- * @brief Basic data types used by the IXP400 project
- *
- * @{
- */
-
-#ifndef IxTypes_H
-
-#ifndef __doxygen_HIDE
-
-#define IxTypes_H
-
-#endif /* __doxygen_HIDE */
-
-
-/* WR51880: Undefined data types workaround for backward compatibility */
-#ifdef __linux
-#ifndef __INCvxTypesOldh
-typedef int (*FUNCPTR)(void);
-typedef int STATUS;
-#define OK (0)
-#define ERROR (-1)
-#endif
-#endif
-
-#include "IxOsalBackward.h"
-
-#endif /* IxTypes_H */
-
-/**
- * @} addtogroup IxTypes
- */
+++ /dev/null
-/**
- * @file IxUART.h
- *
- * @date 12-OCT-01
- *
- * @brief Public header for the Intel IXP400 internal UART, generic driver.
- *
- * Design Notes:
- * This driver allows you to perform the following functions:
- * Device Initialization,
- * send/receive characters.
- *
- * Perform Uart IOCTL for the following:
- * Set/Get the current baud rate,
- * set parity,
- * set the number of Stop bits,
- * set the character Length (5,6,7,8),
- * enable/disable Hardware flow control.
- *
- * Only Polled mode is supported for now.
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
-*/
-
-/**
- * @defgroup IxUARTAccAPI IXP400 UART Access (IxUARTAcc) API
- *
- * @brief IXP400 UARTAcc Driver Public API
- *
- * @{
- */
-
-
-/* Defaults */
-
-/**
- * @defgroup DefaultDefines Defines for Default Values
- *
- * @brief Default values which can be used for UART configuration
- *
- * @sa ixUARTDev
- */
-
-/**
- * @def IX_UART_DEF_OPTS
- *
- * @brief The default hardware options to set the UART to -
- * no flow control, 8 bit word, 1 stop bit, no parity
- *
- * @ingroup DefaultDefines
- */
-#define IX_UART_DEF_OPTS (CLOCAL | CS8)
-
-/**
- * @def IX_UART_DEF_XMIT
- *
- * @brief The default UART FIFO size - must be no bigger than 64
- *
- * @ingroup DefaultDefines
- */
-#define IX_UART_DEF_XMIT 64
-
-/**
- * @def IX_UART_DEF_BAUD
- *
- * @brief The default UART baud rate - 9600
- *
- * @ingroup DefaultDefines
- */
-#define IX_UART_DEF_BAUD 9600
-
-/**
- * @def IX_UART_MIN_BAUD
- *
- * @brief The minimum UART baud rate - 9600
- *
- * @ingroup DefaultDefines
- */
-#define IX_UART_MIN_BAUD 9600
-
-/**
- * @def IX_UART_MAX_BAUD
- *
- * @brief The maximum UART baud rate - 926100
- *
- * @ingroup DefaultDefines
- */
-#define IX_UART_MAX_BAUD 926100
-
-/**
- * @def IX_UART_XTAL
- *
- * @brief The UART clock speed
- *
- * @ingroup DefaultDefines
- */
-#define IX_UART_XTAL 14745600
-
-
-
-/* IOCTL commands (Request codes) */
-
-/**
- * @defgroup IoctlCommandDefines Defines for IOCTL Commands
- *
- * @brief IOCTL Commands (Request codes) which can be used
- * with @ref ixUARTIoctl
- */
-
-
-/**
- * @ingroup IoctlCommandDefines
- *
- * @def IX_BAUD_SET
- *
- * @brief Set the baud rate
- */
-#define IX_BAUD_SET 0
-
-/**
- * @ingroup IoctlCommandDefines
- *
- * @def IX_BAUD_GET
- *
- * @brief Get the baud rate
- */
-#define IX_BAUD_GET 1
-
-/**
- * @ingroup IoctlCommandDefines
- * @def IX_MODE_SET
- * @brief Set the UART mode of operation
- */
-#define IX_MODE_SET 2
-
-/**
- * @ingroup IoctlCommandDefines
- *
- * @def IX_MODE_GET
- *
- * @brief Get the current UART mode of operation
- */
-#define IX_MODE_GET 3
-
-/**
- * @ingroup IoctlCommandDefines
- *
- * @def IX_OPTS_SET
- *
- * @brief Set the UART device options
- */
-#define IX_OPTS_SET 4
-
-/**
- * @ingroup IoctlCommandDefines
- *
- * @def IX_OPTS_GET
- *
- * @brief Get the UART device options
- */
-#define IX_OPTS_GET 5
-
-/**
- * @ingroup IoctlCommandDefines
- *
- * @def IX_STATS_GET
- *
- * @brief Get the UART statistics
- */
-#define IX_STATS_GET 6
-
-
-/* POSIX style ioctl arguments */
-
-/**
- * @defgroup IoctlArgDefines Defines for IOCTL Arguments
- *
- * @brief POSIX style IOCTL arguments which can be used
- * with @ref ixUARTIoctl
- *
- * @sa ixUARTMode
- */
-
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def CLOCAL
- *
- * @brief Software flow control
- */
-#ifdef CLOCAL
-#undef CLOCAL
-#endif
-#define CLOCAL 0x1
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def CREAD
- *
- * @brief Enable interrupt receiver
- */
-#ifdef CREAD
-#undef CREAD
-#endif
-#define CREAD 0x2
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def CSIZE
- *
- * @brief Characters size
- */
-#ifdef CSIZE
-#undef CSIZE
-#endif
-#define CSIZE 0xc
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def CS5
- *
- * @brief 5 bits
- */
-#ifdef CS5
-#undef CS5
-#endif
-#define CS5 0x0
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def CS6
- *
- * @brief 6 bits
- */
-#ifdef CS6
-#undef CS6
-#endif
-#define CS6 0x4
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def CS7
- *
- * @brief 7 bits
- */
-#ifdef CS7
-#undef CS7
-#endif
-#define CS7 0x8
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def CS8
- *
- * @brief 8 bits
- */
-#ifdef CS8
-#undef CS8
-#endif
-#define CS8 0xc
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def STOPB
- *
- * @brief Send two stop bits (else one)
- */
-#define STOPB 0x20
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def PARENB
- *
- * @brief Parity detection enabled (else disabled)
- */
-#ifdef PARENB
-#undef PARENB
-#endif
-#define PARENB 0x40
-
-/**
- * @ingroup IoctlArgDefines
- *
- * @def PARODD
- *
- * @brief Odd parity (else even)
- */
-#ifdef PARODD
-#undef PARODD
-#endif
-#define PARODD 0x80
-
-/**
- * @enum ixUARTMode
- * @brief The mode to set to UART to.
- */
-typedef enum
-{
- INTERRUPT=0, /**< Interrupt mode */
- POLLED, /**< Polled mode */
- LOOPBACK /**< Loopback mode */
-} ixUARTMode;
-
-/**
- * @struct ixUARTStats
- * @brief Statistics for the UART.
- */
-typedef struct
-{
- UINT32 rxCount;
- UINT32 txCount;
- UINT32 overrunErr;
- UINT32 parityErr;
- UINT32 framingErr;
- UINT32 breakErr;
-} ixUARTStats;
-
-/**
- * @struct ixUARTDev
- * @brief Device descriptor for the UART.
- */
-typedef struct
-{
- UINT8 *addr; /**< device base address */
- ixUARTMode mode; /**< interrupt, polled or loopback */
- int baudRate; /**< baud rate */
- int freq; /**< UART clock frequency */
- int options; /**< hardware options */
- int fifoSize; /**< FIFO xmit size */
-
- ixUARTStats stats; /**< device statistics */
-} ixUARTDev;
-
-/**
- * @ingroup IxUARTAccAPI
- *
- * @fn IX_STATUS ixUARTInit(ixUARTDev* pUART)
- *
- * @param pUART @ref ixUARTDev [in] - pointer to UART structure describing our device.
- *
- * @brief Initialise the UART. This puts the chip in a quiescent state.
- *
- * @pre The base address for the UART must contain a valid value.
- * Also the baud rate and hardware options must contain sensible values
- * otherwise the defaults will be used as defined in ixUART.h
- *
- * @post UART is initialized and ready to send and receive data.
- *
- * @note This function should only be called once per device.
- *
- * @retval IX_SUCCESS - UART device successfully initialised.
- * @retval IX_FAIL - Critical error, device not initialised.
- ***************************************************************************/
-PUBLIC IX_STATUS ixUARTInit(ixUARTDev* pUART);
-
-/**
- * @ingroup IxUARTAccAPI
- *
- * @fn IX_STATUS ixUARTPollOutput(ixUARTDev* pUART, int outChar)
- *
- * @param pUART @ref ixUARTDev [out] - pointer to UART structure describing our device.
- * @param outChar int [out] - character to transmit.
- *
- * @brief Transmit a character in polled mode.
- *
- * @pre UART device must be initialised.
- *
- * @retval IX_SUCCESS - character was successfully transmitted.
- * @retval IX_FAIL - output buffer is full (try again).
- ***************************************************************************/
-PUBLIC IX_STATUS ixUARTPollOutput(ixUARTDev* pUART, int outChar);
-
-/**
- * @ingroup IxUARTAccAPI
- *
- * @fn IX_STATUS ixUARTPollInput(ixUARTDev* pUART, char *inChar)
- *
- * @param pUART @ref ixUARTDev [in] - pointer to UART structure describing our device.
- * @param *inChar char [in] - character read from the device.
- *
- * @brief Receive a character in polled mode.
- *
- * @pre UART device must be initialised.
- *
- * @retval IX_SUCCESS - character was successfully read.
- * @retval IX_FAIL - input buffer empty (try again).
- ***************************************************************************/
-PUBLIC IX_STATUS ixUARTPollInput(ixUARTDev* pUART, char *inChar);
-
-/**
- * @ingroup IxUARTAccAPI
- *
- * @fn IX_STATUS ixUARTIoctl(ixUARTDev* pUART, int cmd, void* arg)
- *
- * @param pUART @ref ixUARTDev [in] - pointer to UART structure describing our device.
- * @param cmd int [in] - an ioctl request code.
- * @param arg void* [in] - optional argument used to set the device mode,
- * baud rate, and hardware options.
- *
- * @brief Perform I/O control routines on the device.
- *
- * @retval IX_SUCCESS - requested feature was set/read successfully.
- * @retval IX_FAIL - error setting/reading the requested feature.
- *
- * @sa IoctlCommandDefines
- * @sa IoctlArgDefines
- ***************************************************************************/
-PUBLIC IX_STATUS ixUARTIoctl(ixUARTDev* pUART, int cmd, void* arg);
-
-/**
- * @} defgroup IxUARTAcc
- */
+++ /dev/null
-/**
- * @file IxVersionId.h
- *
- * @date 22-Aug-2002
- *
- * @brief This file contains the IXP400 Software version identifier
- *
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- */
-
-/**
- * @defgroup IxVersionId IXP400 Version ID (IxVersionId)
- *
- * @brief Version Identifiers
- *
- * @{
- */
-
-#ifndef IXVERSIONID_H
-#define IXVERSIONID_H
-
-/**
- * @brief Version Identifier String
- *
- * This string will be updated with each customer release of the IXP400
- * Software.
- */
-#define IX_VERSION_ID "2_0"
-
-/**
- * This string will be updated with each customer release of the IXP400
- * ADSL driver package.
- */
-#define IX_VERSION_ADSL_ID "1_12"
-
-
-/**
- * This string will be updated with each customer release of the IXP400
- * USB Client driver package.
- */
-#define IX_VERSION_USBRNDIS_ID "1_9"
-
-/**
- * This string will be updated with each customer release of the IXP400
- * I2C Linux driver package.
- */
-#define IX_VERSION_I2C_LINUX_ID "1_0"
-
-/**
- * @brief Linux Ethernet Driver Patch Version Identifier String
- *
- * This string will be updated with each release of Linux Ethernet Patch
- */
-#define LINUX_ETHERNET_DRIVER_PATCH_ID "1_4"
-
-/**
- * @brief Linux Integration Patch Version Identifier String
- *
- * This String will be updated with each release of Linux Integration Patch
- */
-#define LINUX_INTEGRATION_PATCH_ID "1_3"
-
-/**
- * @brief Linux Ethernet Readme version Identifier String
- *
- * This string will be updated with each release of Linux Ethernet Readme
- */
-#define LINUX_ETHERNET_README_ID "1_3"
-
-/**
- * @brief Linux Integration Readme version Identifier String
- *
- * This string will be updated with each release of Linux Integration Readme
- */
-
-#define LINUX_INTEGRATION_README_ID "1_3"
-
-/**
- * @brief Linux I2C driver Readme version Identifier String
- *
- * This string will be updated with each release of Linux I2C Driver Readme
- */
-#define LINUX_I2C_DRIVER_README_ID "1_0"
-
-/**
- * @brief ixp425_eth_update_nf_bridge.patch version Identifier String
- *
- * This string will be updated with each release of ixp425_eth_update_nf_bridge.
-patch
- *
- */
-
-#define IXP425_ETH_UPDATE_NF_BRIDGE_ID "1_3"
-
-/**
- * @brief Internal Release Identifier String
- *
- * This string will be updated with each internal release (SQA drop)
- * of the IXP400 Software.
- */
-#define IX_VERSION_INTERNAL_ID "SQA3_5"
-
-/**
- * @brief Compatible Tornado Version Identifier
- */
-#define IX_VERSION_COMPATIBLE_TORNADO "Tornado2_2_1-PNE2_0"
-
-/**
- * @brief Compatible Linux Version Identifier
- */
-#define IX_VERSION_COMPATIBLE_LINUX "MVL3_1"
-
-
-#endif /* IXVERSIONID_H */
-
-/**
- * @} addtogroup IxVersionId
- */
+++ /dev/null
-/**
- * ============================================================================
- * = COPYRIGHT
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- * = PRODUCT
- * Intel(r) IXP425 Software Release
- *
- * = FILENAME
- * ix_error.h (Replaced by OSAL)
- *
- * = DESCRIPTION
- * This file will describe the basic error type and support functions that
- * will be used by the IXA SDK Framework API.
- *
- * = AUTHOR
- * Intel Corporation
- *
- * = CHANGE HISTORY
- * 4/22/2002 4:19:03 PM - creation time
- * ============================================================================
- */
-
-#if !defined(__IX_ERROR_H__)
-#define __IX_ERROR_H__
-
-#include "IxOsalBackward.h"
-
-#endif /* end !defined(__IX_ERROR_H__) */
-
+++ /dev/null
-/**
- * ============================================================================
- * = COPYRIGHT
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- * = PRODUCT
- * Intel(r) IXP425 Software Release
- *
- * = FILENAME
- * ix_macros.h
- *
- * = DESCRIPTION
- * This file will define the basic preprocessor macros that are going to be used
- * the IXA SDK Framework API.
- *
- * = AUTHOR
- * Intel Corporation
- *
- * = CHANGE HISTORY
- * 4/22/2002 4:41:05 PM - creation time
- * ============================================================================
- */
-
-#if !defined(__IX_MACROS_H__)
-#define __IX_MACROS_H__
-
-
-#if defined(__cplusplus)
-extern "C"
-{
-#endif /* end defined(__cplusplus) */
-
-
-/**
- * MACRO NAME: IX_BIT_FIELD_MASK16
- *
- * DESCRIPTION: Builds the mask required to extract the bit field from a 16 bit unsigned integer value.
- *
- * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant
- * bit of the bit field.
- * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant
- * bit of the bit field.
- *
- * @Return: Returns a 16 bit mask that will extract the bit field from a 16 bit unsigned integer value.
- */
-#define IX_BIT_FIELD_MASK16( \
- arg_FieldLSBBit, \
- arg_FieldMSBBit \
- ) \
- ((ix_bit_mask16)((((ix_uint16)1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - \
- (ix_uint16)1) << arg_FieldLSBBit))
-
-
-
-/**
- * MACRO NAME: IX_GET_BIT_FIELD16
- *
- * DESCRIPTION: Extracts a bit field from 16 bit unsigned integer. The returned value is normalized in
- * in the sense that will be right aligned.
- *
- * @Param: - IN arg_PackedData16 a 16 bit unsigned integer that contains the bit field of interest.
- * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant
- * bit of the bit field.
- * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant
- * bit of the bit field.
- *
- * @Return: Returns the value of the bit field. The value can be from 0 to (1 << (arg_FieldMSBBit + 1 -
- * arg_FieldLSBBit)) - 1.
- */
-#define IX_GET_BIT_FIELD16( \
- arg_PackedData16, \
- arg_FieldLSBBit, \
- arg_FieldMSBBit \
- ) \
- (((ix_uint16)(arg_PackedData16) & IX_BIT_FIELD_MASK16(arg_FieldLSBBit, arg_FieldMSBBit)) >> \
- arg_FieldLSBBit)
-
-
-/**
- * MACRO NAME: IX_MAKE_BIT_FIELD16
- *
- * DESCRIPTION: This macro will create a temporary 16 bit value with the bit field
- * desired set to the desired value.
- *
- * @Param: - IN arg_BitFieldValue is the new value of the bit field. The value can be from 0 to
- * (1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - 1.
- * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant
- * bit of the bit field.
- * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant
- * bit of the bit field.
- *
- * @Return: Returns a temporary ix_uint16 value that has the bit field set to the appropriate value.
- */
-#define IX_MAKE_BIT_FIELD16( \
- arg_BitFieldValue, \
- arg_FieldLSBBit, \
- arg_FieldMSBBit \
- ) \
- (((ix_uint16)(arg_BitFieldValue) << arg_FieldLSBBit) & \
- IX_BIT_FIELD_MASK16(arg_FieldLSBBit, arg_FieldMSBBit))
-
-/**
- * MACRO NAME: IX_SET_BIT_FIELD16
- *
- * DESCRIPTION: Sets a new value for a bit field from a 16 bit unsigned integer.
- *
- * @Param: - IN arg_PackedData16 a 16 bit unsigned integer that contains the bit field of interest.
- * @Param: - IN arg_BitFieldValue is the new vale of the bit field. The value can be from 0 to
- * (1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - 1.
- * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant
- * bit of the bit field.
- * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant
- * bit of the bit field.
- *
- * @Return: Returns the updated value of arg_PackedData16.
- */
-#define IX_SET_BIT_FIELD16( \
- arg_PackedData16, \
- arg_BitFieldValue, \
- arg_FieldLSBBit, \
- arg_FieldMSBBit \
- ) \
- (arg_PackedData16 = (((ix_uint16)(arg_PackedData16) & \
- ~(IX_BIT_FIELD_MASK16(arg_FieldLSBBit, arg_FieldMSBBit))) | \
- IX_MAKE_BIT_FIELD16(arg_BitFieldValue, arg_FieldLSBBit, arg_FieldMSBBit)))
-
-
-/**
- * MACRO NAME: IX_BIT_FIELD_MASK32
- *
- * DESCRIPTION: Builds the mask required to extract the bit field from a 32 bit unsigned integer value.
- *
- * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant
- * bit of the bit field.
- * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant
- * bit of the bit field.
- *
- * @Return: Returns a 32 bit mask that will extract the bit field from a 32 bit unsigned integer value.
- */
-#define IX_BIT_FIELD_MASK32( \
- arg_FieldLSBBit, \
- arg_FieldMSBBit \
- ) \
- ((ix_bit_mask32)((((ix_uint32)1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - \
- (ix_uint32)1) << arg_FieldLSBBit))
-
-
-
-/**
- * MACRO NAME: IX_GET_BIT_FIELD32
- *
- * DESCRIPTION: Extracts a bit field from 32 bit unsigned integer. The returned value is normalized in
- * in the sense that will be right aligned.
- *
- * @Param: - IN arg_PackedData32 a 32 bit unsigned integer that contains the bit field of interest.
- * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant
- * bit of the bit field.
- * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant
- * bit of the bit field.
- *
- * @Return: Returns the value of the bit field. The value can be from 0 to (1 << (arg_FieldMSBBit + 1 -
- * arg_FieldLSBBit)) - 1.
- */
-#define IX_GET_BIT_FIELD32( \
- arg_PackedData32, \
- arg_FieldLSBBit, \
- arg_FieldMSBBit \
- ) \
- (((ix_uint32)(arg_PackedData32) & IX_BIT_FIELD_MASK32(arg_FieldLSBBit, arg_FieldMSBBit)) >> \
- arg_FieldLSBBit)
-
-
-
-
-/**
- * MACRO NAME: IX_MAKE_BIT_FIELD32
- *
- * DESCRIPTION: This macro will create a temporary 32 bit value with the bit field
- * desired set to the desired value.
- *
- * @Param: - IN arg_BitFieldValue is the new value of the bit field. The value can be from 0 to
- * (1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - 1.
- * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant
- * bit of the bit field.
- * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant
- * bit of the bit field.
- *
- * @Return: Returns a temporary ix_uint32 value that has the bit field set to the appropriate value.
- */
-#define IX_MAKE_BIT_FIELD32( \
- arg_BitFieldValue, \
- arg_FieldLSBBit, \
- arg_FieldMSBBit \
- ) \
- (((ix_uint32)(arg_BitFieldValue) << arg_FieldLSBBit) & \
- IX_BIT_FIELD_MASK32(arg_FieldLSBBit, arg_FieldMSBBit))
-
-
-/**
- * MACRO NAME: IX_SET_BIT_FIELD32
- *
- * DESCRIPTION: Sets a new value for a bit field from a 32 bit unsigned integer.
- *
- * @Param: - IN arg_PackedData32 a 32 bit unsigned integer that contains the bit field of interest.
- * @Param: - IN arg_BitFieldValue is the new value of the bit field. The value can be from 0 to
- * (1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - 1.
- * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant
- * bit of the bit field.
- * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant
- * bit of the bit field.
- *
- * @Return: Returns the updated value of arg_PackedData32.
- */
-#define IX_SET_BIT_FIELD32( \
- arg_PackedData32, \
- arg_BitFieldValue, \
- arg_FieldLSBBit, \
- arg_FieldMSBBit \
- ) \
- (arg_PackedData32 = (((ix_uint32)(arg_PackedData32) & \
- ~(IX_BIT_FIELD_MASK32(arg_FieldLSBBit, arg_FieldMSBBit))) | \
- IX_MAKE_BIT_FIELD32(arg_BitFieldValue, arg_FieldLSBBit, arg_FieldMSBBit)))
-
-
-
-#if defined(__cplusplus)
-}
-#endif /* end defined(__cplusplus) */
-
-#endif /* end !defined(__IX_MACROS_H__) */
+++ /dev/null
-/**
- * ============================================================================
- * = COPYRIGHT
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- * = PRODUCT
- * Intel(r) IXP425 Software Release
- *
- * = FILENAME
- * ix_os_type.h (Replaced by OSAL)
- *
- * = DESCRIPTION
- * This file provides protable symbol definitions for the current OS type.
- *
- * = AUTHOR
- * Intel Corporation
- *
- * = CHANGE HISTORY
- * 4/22/2002 4:43:30 PM - creation time
- * ============================================================================
- */
-
-#if !defined(__IX_OS_TYPE_H__)
-#define __IX_OS_TYPE_H__
-
-#include "IxOsalBackward.h"
-
-#endif /* end !defined(__IX_OS_TYPE_H__) */
-
+++ /dev/null
-/**
- * ============================================================================
- * = COPYRIGHT
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- * = PRODUCT
- * Intel(r) IXP425 Software Release
- *
- * = LIBRARY
- * OSSL - Operating System Services Library
- *
- * = MODULE
- * OSSL Abstraction layer header file
- *
- * = FILENAME
- * ix_ossl.h (Replaced by OSAL)
- *
- * = DESCRIPTION
- * This file contains the prototypes of OS-independent wrapper
- * functions which allow the programmer not to be tied to a specific
- * operating system. The OSSL functions can be divided into three classes:
- *
- * 1) synchronization-related wrapper functions around thread system calls
- * 2) thread-related wrapper functions around thread calls
- * 3) transactor/workbench osapi calls -- defined in osApi.h
- *
- * Both 1 and 2 classes of functions provide Thread Management, Thread
- * Synchronization, Mutual Exclusion and Timer primitives. Namely,
- * creation and deletion functions as well as the standard "wait" and
- * "exit". Additionally, a couple of utility functions which enable to
- * pause the execution of a thread are also provided.
- *
- * The 3rd class provides a slew of other OSAPI functions to handle
- * Transactor/WorkBench OS calls.
- *
- *
- * OSSL Thread APIs:
- * The OSSL thread functions that allow for thread creation,
- * get thread id, thread deletion and set thread priroity.
- *
- * ix_ossl_thread_create
- * ix_ossl_thread_get_id
- * ix_ossl_thread_exit
- * ix_ossl_thread_kill
- * ix_ossl_thread_set_priority
- * ix_ossl_thread__delay
- *
- * OSSL Semaphore APIs:
- * The OSSL semaphore functions that allow for initialization,
- * posting, waiting and deletion of semaphores.
- *
- * ix_ossl_sem_init
- * ix_ossl_sem_fini
- * ix_ossl_sem_take
- * ix_ossl_sem_give
- * ix_ossl_sem_flush
- *
- * OSSL Mutex APIs:
- * The OSSL wrapper functions that allow for initialization,
- * posting, waiting and deletion of mutexes.
- *
- * ix_ossl_mutex_init
- * ix_ossl_mutex_fini
- * ix_ossl_mutex_lock
- * ix_ossl_mutex_unlock
- *
- * OSSL Timer APIs:
- * The timer APIs provide sleep and get time functions.
- *
- * ix_ossl_sleep
- * ix_ossl_sleep_tick
- * ix_ossl_time_get
- *
- * OSAPIs for Transactor/WorkBench:
- * These OSAPI functions are used for transator OS calls.
- * They are defined in osApi.h.
- *
- * Sem_Init
- * Sem_Destroy
- * Sem_Wait
- * Sem_Wait
- * Thread_Create
- * Thread_Cancel
- * Thread_SetPriority
- * delayMs
- * delayTick
- *
- *
- *
- **********************************************************************
- *
- *
- * = AUTHOR
- * Intel Corporation
- *
- * = ACKNOWLEDGEMENTS
- *
- *
- * = CREATION TIME
- * 1/8/2002 1:53:42 PM
- *
- * = CHANGE HISTORY
- * 02/22/2002 : Renamed osapi.h os_api.h
- * Moved OS header file includes from OSSL.h to os_api.h
- * Moved OS specific datatypes to os_api.h
- * Modified data types, macros and functions as per
- * 'C' coding guidelines.
- *
- *
- * ============================================================================
- */
-
-#ifndef _IX_OSSL_H
-#ifndef __doxygen_hide
-#define _IX_OSSL_H
-#endif /* __doxygen_hide */
-
-#include "IxOsalBackward.h"
-
-#endif /* _IX_OSSL_H */
-
-/**
- * @} defgroup IxOSSL
- */
+++ /dev/null
-/**
- * ============================================================================
- * = COPYRIGHT
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- * = PRODUCT
- * Intel(r) IXP425 Software Release
- *
- * = FILENAME
- * ix_symbols.h
- *
- * = DESCRIPTION
- * This file declares all the global preprocessor symbols required by
- * the IXA SDK Framework API.
- *
- * = AUTHOR
- * Intel Corporation
- *
- * = CHANGE HISTORY
- * 4/23/2002 10:41:13 AM - creation time
- * ============================================================================
- */
-
-#if !defined(__IX_SYMBOLS_H__)
-#define __IX_SYMBOLS_H__
-
-
-#if defined(__cplusplus)
-extern "C"
-{
-#endif /* end defined(__cplusplus) */
-
-/**
- * The IX_EXPORT_FUNCTION symbol will be used for compilation on different platforms.
- * We are planning to provide a simulation version of the library that should work
- * with the Transactor rather than the hardware. This implementation will be done on
- * WIN32 in the form of a DLL that will need to export functions and symbols.
- */
-#if (_IX_OS_TYPE_ == _IX_OS_WIN32_)
-# if defined(_IX_LIB_INTERFACE_IMPLEMENTATION_)
-# define IX_EXPORT_FUNCTION __declspec( dllexport )
-# elif defined(_IX_LIB_INTERFACE_IMPORT_DLL_)
-# define IX_EXPORT_FUNCTION __declspec( dllimport )
-# else
-# define IX_EXPORT_FUNCTION extern
-# endif
-#elif (_IX_OS_TYPE_ == _IX_OS_WINCE_)
-# define IX_EXPORT_FUNCTION __declspec(dllexport)
-#else
-# define IX_EXPORT_FUNCTION extern
-#endif
-
-
-/**
- * This symbols should be defined when we want to build for a multithreaded environment
- */
-#define _IX_MULTI_THREADED_ 1
-
-
-/**
- * This symbol should be defined in the case we to buils for a multithreaded environment
- * but we want that our modules to work as if they are used in a single threaded environment.
- */
-/* #define _IX_RM_EXPLICIT_SINGLE_THREADED_ 1 */
-
-#if defined(__cplusplus)
-}
-#endif /* end defined(__cplusplus) */
-
-#endif /* end !defined(__IX_SYMBOLS_H__) */
+++ /dev/null
-/**
- * ============================================================================
- * = COPYRIGHT
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- * = PRODUCT
- * Intel(r) IXP425 Software Release
- *
- * = FILENAME
- * ix_types.h
- *
- * = DESCRIPTION
- * This file will define generic types that will guarantee the protability
- * between different architectures and compilers. It should be used the entire
- * IXA SDK Framework API.
- *
- * = AUTHOR
- * Intel Corporation
- *
- * = CHANGE HISTORY
- * 4/22/2002 4:44:17 PM - creation time
- * ============================================================================
- */
-
-#if !defined(__IX_TYPES_H__)
-#define __IX_TYPES_H__
-
-
-#if defined(__cplusplus)
-extern "C"
-{
-#endif /* end defined(__cplusplus) */
-
-
-/**
- * Define generic integral data types that will guarantee the size.
- */
-
-/**
- * TYPENAME: ix_int8
- *
- * DESCRIPTION: This type defines an 8 bit signed integer value.
- *
- */
-typedef signed char ix_int8;
-
-
-/**
- * TYPENAME: ix_uint8
- *
- * DESCRIPTION: This type defines an 8 bit unsigned integer value.
- *
- */
-typedef unsigned char ix_uint8;
-
-
-/**
- * TYPENAME: ix_int16
- *
- * DESCRIPTION: This type defines an 16 bit signed integer value.
- *
- */
-typedef signed short int ix_int16;
-
-
-/**
- * TYPENAME: ix_uint16
- *
- * DESCRIPTION: This type defines an 16 bit unsigned integer value.
- *
- */
-typedef unsigned short int ix_uint16;
-
-
-/**
- * TYPENAME: ix_int32
- *
- * DESCRIPTION: This type defines an 32 bit signed integer value.
- *
- */
-typedef signed int ix_int32;
-
-
-/**
- * TYPENAME: ix_uint32
- *
- * DESCRIPTION: This type defines an 32 bit unsigned integer value.
- *
- */
-#ifndef __wince
-typedef unsigned int ix_uint32;
-#else
-typedef unsigned long ix_uint32;
-#endif
-
-/**
- * TYPENAME: ix_int64
- *
- * DESCRIPTION: This type defines an 64 bit signed integer value.
- *
- */
-#ifndef __wince
-__extension__ typedef signed long long int ix_int64;
-#endif
-
-/**
- * TYPENAME: ix_uint64
- *
- * DESCRIPTION: This type defines an 64 bit unsigned integer value.
- *
- */
-#ifndef __wince
-__extension__ typedef unsigned long long int ix_uint64;
-#endif
-
-
-/**
- * TYPENAME: ix_bit_mask8
- *
- * DESCRIPTION: This is a generic type for a 8 bit mask.
- */
-typedef ix_uint8 ix_bit_mask8;
-
-
-/**
- * TYPENAME: ix_bit_mask16
- *
- * DESCRIPTION: This is a generic type for a 16 bit mask.
- */
-typedef ix_uint16 ix_bit_mask16;
-
-
-/**
- * TYPENAME: ix_bit_mask32
- *
- * DESCRIPTION: This is a generic type for a 32 bit mask.
- */
-typedef ix_uint32 ix_bit_mask32;
-
-
-/**
- * TYPENAME: ix_bit_mask64
- *
- * DESCRIPTION: This is a generic type for a 64 bit mask.
- */
-#ifndef __wince
-typedef ix_uint64 ix_bit_mask64;
-#endif
-
-
-/**
- * TYPENAME: ix_handle
- *
- * DESCRIPTION: This type defines a generic handle.
- *
- */
-typedef ix_uint32 ix_handle;
-
-
-
-/**
- * DESCRIPTION: This symbol defines a NULL handle
- *
- */
-#define IX_NULL_HANDLE ((ix_handle)0)
-
-
-#if defined(__cplusplus)
-}
-#endif /* end defined(__cplusplus) */
-
-#endif /* end !defined(__IX_TYPES_H__) */
+++ /dev/null
-/**
- * ============================================================================
- * = COPYRIGHT
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Intel Corporation nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @par
- * -- End of Copyright Notice --
- * = PRODUCT
- * Intel(r) IXP425 Software Release
- *
- * = LIBRARY
- * OSSL - Operating System Services Library
- *
- * = MODULE
- * OS Specific Data Types header file
- *
- * = FILENAME
- * OSSL.h (Replaced by OSAL)
- *
- * = DESCRIPTION
- * This file contains definitions and encapsulations for OS specific data types. These
- * encapsulated data types are used by OSSL header files and OS API functions.
- *
- *
- **********************************************************************
- *
- *
- * = AUTHOR
- * Intel Corporation
- *
- * = AKNOWLEDGEMENTS
- *
- *
- * = CREATION TIME
- * 1/8/2002 1:53:42 PM
- *
- * = CHANGE HISTORY
-
- * ============================================================================
- */
-
-#ifndef _OS_DATATYPES_H
-#define _OS_DATATYPES_H
-
-#include "IxOsalBackward.h"
-
-#endif /* _OS_DATATYPES_H */
-
+++ /dev/null
-/* Copyright Motorola, Inc. 1993, 1994
- ALL RIGHTS RESERVED
-
- You are hereby granted a copyright license to use, modify, and
- distribute the SOFTWARE so long as this entire notice is retained
- without alteration in any modified and/or redistributed versions,
- and that such modified versions are clearly identified as such.
- No licenses are granted by implication, estoppel or otherwise under
- any patents or trademarks of Motorola, Inc.
-
- The SOFTWARE is provided on an "AS IS" basis and without warranty.
- To the maximum extent permitted by applicable law, MOTOROLA DISCLAIMS
- ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING IMPLIED
- WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
- PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
- REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS
- THEREOF) AND ANY ACCOMPANYING WRITTEN MATERIALS.
-
- To the maximum extent permitted by applicable law, IN NO EVENT SHALL
- MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
- (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF
- BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS
- INFORMATION, OR OTHER PECUNIARY LOSS) ARISING OF THE USE OR
- INABILITY TO USE THE SOFTWARE. Motorola assumes no responsibility
- for the maintenance and support of the SOFTWARE.
-
-*/
-
-
-#include "config.h"
-
-/*
- 1 2 3 4 5 6 7 8
-01234567890123456789012345678901234567890123456789012345678901234567890123456789
-*/
-/* List define statements here */
-
-/* These are for all the toolboxes and functions to use. These will help
-to standardize the error handling in the current project */
-
- /* this is the "data type" for the error
- messages in the system */
-#define STATUS unsigned int
-
- /* this is a success status code */
-#define SUCCESS 1
-
- /* likewise this is failure */
-#define FAILURE 0
-
-#define NUM_ERRORS 47
-
-/* This first section of "defines" are for error codes ONLY. The called
- routine will return one of these error codes to the caller. If the final
- returned code is "VALID", then everything is a-okay. However, if one
- of the functions returns a non-valid status, that error code should be
- propogated back to all the callers. At the end, the last caller will
- call an error_processing function, and send in the status which was
- returned. It's up to the error_processing function to determine which
- error occured (as indicated by the status), and print an appropriate
- message back to the user.
-*/
-/*----------------------------------------------------------------------*/
-/* these are specifically for the parser routines */
-
-#define UNKNOWN_COMMAND 0xfb00 /* "unrecognized command " */
-#define UNKNOWN_REGISTER 0xfb01 /* "unknown register "*/
-#define ILLEGAL_RD_STAGE 0xfb02 /* cannot specify reg. family in range*/
-#define ILLEGAL_REG_FAMILY 0xfb03 /* "cannot specify a range of special
- or miscellaneous registers"*/
-#define RANGE_CROSS_FAMILY 0xfb04 /* "cannot specify a range across
- register families" */
-#define UNIMPLEMENTED_STAGE 0xfb05 /* invalid rd or rmm parameter format */
-#define REG_NOT_WRITEABLE 0xfb06 /* "unknown operator in arguements"*/
-#define INVALID_FILENAME 0xfb07 /* "invalid download filename" */
-#define INVALID_BAUD_RATE 0xfb08 /* invalid baud rate from sb command */
-#define UNSUPPORTED_REGISTER 0xfb09 /* Special register is not supported */
-#define FOR_BOARD_ONLY 0xfb0a /* "Not available for Unix." */
-
-
-/*----------------------------------------------------------------------*/
-/* these are for the error checking toolbox */
-
-#define INVALID 0xfd00 /* NOT valid */
-#define VALID 0xfd01 /* valid */
-
- /* This error is found in the fcn:
- is_right_size_input() to indicate
- that the input was not 8 characters
- long. */
-#define INVALID_SIZE 0xfd02
-
- /* This error is found in the fcn:
- is_valid_address_range() to indicate
- that the address given falls outside
- of valid memory defined by MEM_START
- to MEM_END.
- */
-#define OUT_OF_BOUNDS_ADDRESS 0xfd03
-
- /* This error is found in the fcn:
- is_valid_hex_input() to indicate that
- one of more of the characters entered
- are not valid hex characters. Valid
- hex characters are 0-9, A-F, a-f.
- */
-#define INVALID_HEX_INPUT 0xfd04
-
- /* This error is found in the fcn:
- is_valid_register_number() to indicate
- that a given register does not exist.
- */
-#define REG_NOT_READABLE 0xfd05
-
- /* This error is found in the fcn:
- is_word_aligned_address() to indicate
- that the given address is not word-
- aligned. A word-aligned address ends
- in 0x0,0x4,0x8,0xc.
- */
-#define NOT_WORD_ALIGNED 0xfd07
-
- /* This error is found in the fcn:
- is_valid_address_range() to indicate
- that the starting address is greater
- than the ending address.
- */
-#define REVERSED_ADDRESS 0xfd08
-
- /* this error tells us that the address
- specified as the destination is within
- the source addresses */
-#define RANGE_OVERLAP 0xfd09
-
-
-#define ERROR 0xfd0a /* An error occured */
-#define INVALID_PARAM 0xfd0b /* "invalid input parameter " */
-
-
-#define INVALID_FLAG 0xfd0c /* invalid flag */
-
-/*----------------------------------------------------------------------*/
-/* these are for the getarg toolbox */
-
-#define INVALID_NUMBER_ARGS 0xFE00 /* invalid number of commd arguements */
-#define UNKNOWN_PARAMETER 0xFE01 /* "unknown type of parameter "*/
-
-
-/*----------------------------------------------------------------------*/
-/* these are for the tokenizer toolbox */
-
-#define ILLEGAL_CHARACTER 0xFF00 /* unrecognized char. in input stream*/
-#define TTL_NOT_SORTED 0xFF01 /* token translation list not sorted */
-#define TTL_NOT_DEFINED 0xFF02 /* token translation list not assigned*/
-#define INVALID_STRING 0xFF03 /* unable to extract string from input */
-#define BUFFER_EMPTY 0xFF04 /* "input buffer is empty" */
-#define INVALID_MODE 0xFF05 /* input buf is in an unrecognized mode*/
-#define TOK_INTERNAL_ERROR 0xFF06 /* "internal tokenizer error" */
-#define TOO_MANY_IBS 0xFF07 /* "too many open input buffers" */
-#define NO_OPEN_IBS 0xFF08 /* "no open input buffers" */
-
-
-/* these are for the read from screen toolbox */
-
-#define RESERVED_WORD 0xFC00 /* used a reserved word as an arguement*/
-
-
-/* these are for the breakpoint routines */
-
-#define FULL_BPDS 0xFA00 /* breakpoint data structure is full */
-
-
-/* THESE are for the downloader */
-
-#define NOT_IN_S_RECORD_FORMAT 0xf900 /* "not in S-Record Format" */
-#define UNREC_RECORD_TYPE 0xf901 /* "unrecognized record type" */
-#define CONVERSION_ERROR 0xf902 /* "ascii to int conversion error" */
-#define INVALID_MEMORY 0xf903 /* "bad s-record memory address " */
-
-
-/* these are for the compression and decompression stuff */
-
-#define COMP_UNK_CHARACTER 0xf800 /* "unknown compressed character " */
-
-#define COMP_UNKNOWN_STATE 0xf801 /* "unknown binary state" */
-
-#define NOT_IN_COMPRESSED_FORMAT 0xf802 /* not in compressed S-Record format */
-
-
-/* these are for the DUART handling things */
-
- /* "unrecognized serial port configuration" */
-#define UNKNOWN_PORT_STATE 0xf700
-
-
-/* these are for the register toolbox */
-
- /* "cannot find register in special
- purpose register file " */
-#define SPR_NOT_FOUND 0xf600
-
-
-/* these are for the duart specific stuff */
-
- /* "transparent mode needs access to
- two serial ports" */
-#define TM_NEEDS_BOTH_PORTS 0xf500
-
-
-/*----------------------------------------------------------------------*/
-/* these are specifically for the flash routines */
-#define FLASH_ERROR 0xf100 /* general flash error */
+++ /dev/null
-/*
- * Freescale SerDes initialization routine
- *
- * Copyright (C) 2007 Freescale Semicondutor, Inc.
- * Copyright (C) 2008 MontaVista Software, Inc. All rights reserved.
- *
- * Author: Li Yang <leoli@freescale.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/io.h>
-#include <asm/fsl_serdes.h>
-
-/* SerDes registers */
-#define FSL_SRDSCR0_OFFS 0x0
-#define FSL_SRDSCR0_DPP_1V2 0x00008800
-#define FSL_SRDSCR1_OFFS 0x4
-#define FSL_SRDSCR1_PLLBW 0x00000040
-#define FSL_SRDSCR2_OFFS 0x8
-#define FSL_SRDSCR2_VDD_1V2 0x00800000
-#define FSL_SRDSCR2_SEIC_MASK 0x00001c1c
-#define FSL_SRDSCR2_SEIC_SATA 0x00001414
-#define FSL_SRDSCR2_SEIC_PEX 0x00001010
-#define FSL_SRDSCR2_SEIC_SGMII 0x00000101
-#define FSL_SRDSCR3_OFFS 0xc
-#define FSL_SRDSCR3_KFR_SATA 0x10100000
-#define FSL_SRDSCR3_KPH_SATA 0x04040000
-#define FSL_SRDSCR3_SDFM_SATA_PEX 0x01010000
-#define FSL_SRDSCR3_SDTXL_SATA 0x00000505
-#define FSL_SRDSCR4_OFFS 0x10
-#define FSL_SRDSCR4_PROT_SATA 0x00000808
-#define FSL_SRDSCR4_PROT_PEX 0x00000101
-#define FSL_SRDSCR4_PROT_SGMII 0x00000505
-#define FSL_SRDSCR4_PLANE_X2 0x01000000
-#define FSL_SRDSRSTCTL_OFFS 0x20
-#define FSL_SRDSRSTCTL_RST 0x80000000
-#define FSL_SRDSRSTCTL_SATA_RESET 0xf
-
-void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd)
-{
- void *regs = (void *)CONFIG_SYS_IMMR + offset;
- u32 tmp;
-
- /* 1.0V corevdd */
- if (vdd) {
- /* DPPE/DPPA = 0 */
- tmp = in_be32(regs + FSL_SRDSCR0_OFFS);
- tmp &= ~FSL_SRDSCR0_DPP_1V2;
- out_be32(regs + FSL_SRDSCR0_OFFS, tmp);
-
- /* VDD = 0 */
- tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
- tmp &= ~FSL_SRDSCR2_VDD_1V2;
- out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
- }
-
- /* protocol specific configuration */
- switch (proto) {
- case FSL_SERDES_PROTO_SATA:
- /* Set and clear reset bits */
- tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS);
- tmp |= FSL_SRDSRSTCTL_SATA_RESET;
- out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
- udelay(1000);
- tmp &= ~FSL_SRDSRSTCTL_SATA_RESET;
- out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
-
- /* Configure SRDSCR1 */
- tmp = in_be32(regs + FSL_SRDSCR1_OFFS);
- tmp &= ~FSL_SRDSCR1_PLLBW;
- out_be32(regs + FSL_SRDSCR1_OFFS, tmp);
-
- /* Configure SRDSCR2 */
- tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
- tmp &= ~FSL_SRDSCR2_SEIC_MASK;
- tmp |= FSL_SRDSCR2_SEIC_SATA;
- out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
-
- /* Configure SRDSCR3 */
- tmp = FSL_SRDSCR3_KFR_SATA | FSL_SRDSCR3_KPH_SATA |
- FSL_SRDSCR3_SDFM_SATA_PEX |
- FSL_SRDSCR3_SDTXL_SATA;
- out_be32(regs + FSL_SRDSCR3_OFFS, tmp);
-
- /* Configure SRDSCR4 */
- tmp = rfcks | FSL_SRDSCR4_PROT_SATA;
- out_be32(regs + FSL_SRDSCR4_OFFS, tmp);
- break;
- case FSL_SERDES_PROTO_PEX:
- case FSL_SERDES_PROTO_PEX_X2:
- /* Configure SRDSCR1 */
- tmp = in_be32(regs + FSL_SRDSCR1_OFFS);
- tmp |= FSL_SRDSCR1_PLLBW;
- out_be32(regs + FSL_SRDSCR1_OFFS, tmp);
-
- /* Configure SRDSCR2 */
- tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
- tmp &= ~FSL_SRDSCR2_SEIC_MASK;
- tmp |= FSL_SRDSCR2_SEIC_PEX;
- out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
-
- /* Configure SRDSCR3 */
- tmp = FSL_SRDSCR3_SDFM_SATA_PEX;
- out_be32(regs + FSL_SRDSCR3_OFFS, tmp);
-
- /* Configure SRDSCR4 */
- tmp = rfcks | FSL_SRDSCR4_PROT_PEX;
- if (proto == FSL_SERDES_PROTO_PEX_X2)
- tmp |= FSL_SRDSCR4_PLANE_X2;
- out_be32(regs + FSL_SRDSCR4_OFFS, tmp);
- break;
- case FSL_SERDES_PROTO_SGMII:
- /* Configure SRDSCR1 */
- tmp = in_be32(regs + FSL_SRDSCR1_OFFS);
- tmp &= ~FSL_SRDSCR1_PLLBW;
- out_be32(regs + FSL_SRDSCR1_OFFS, tmp);
-
- /* Configure SRDSCR2 */
- tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
- tmp &= ~FSL_SRDSCR2_SEIC_MASK;
- tmp |= FSL_SRDSCR2_SEIC_SGMII;
- out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
-
- /* Configure SRDSCR3 */
- out_be32(regs + FSL_SRDSCR3_OFFS, 0);
-
- /* Configure SRDSCR4 */
- tmp = rfcks | FSL_SRDSCR4_PROT_SGMII;
- out_be32(regs + FSL_SRDSCR4_OFFS, tmp);
- break;
- default:
- return;
- }
-
- /* Do a software reset */
- tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS);
- tmp |= FSL_SRDSRSTCTL_RST;
- out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
-}
+++ /dev/null
-/*
- * (C) Copyright 2006 - 2008
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright (c) 2005 Cisco Systems. All rights reserved.
- * Roland Dreier <rolandd@cisco.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-/* define DEBUG for debugging output (obviously ;-)) */
-#if 0
-#define DEBUG
-#endif
-
-#include <common.h>
-#include <pci.h>
-#include <ppc4xx.h>
-#include <asm/processor.h>
-#include <asm-ppc/io.h>
-
-#if (defined(CONFIG_440SPE) || defined(CONFIG_405EX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
- defined(CONFIG_PCI) && !defined(CONFIG_PCI_DISABLE_PCIE)
-
-#include <asm/4xx_pcie.h>
-
-enum {
- PTYPE_ENDPOINT = 0x0,
- PTYPE_LEGACY_ENDPOINT = 0x1,
- PTYPE_ROOT_PORT = 0x4,
-
- LNKW_X1 = 0x1,
- LNKW_X4 = 0x4,
- LNKW_X8 = 0x8
-};
-
-static int validate_endpoint(struct pci_controller *hose)
-{
- if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE0_CFGBASE)
- return (is_end_point(0));
- else if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE1_CFGBASE)
- return (is_end_point(1));
-#if CONFIG_SYS_PCIE_NR_PORTS > 2
- else if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE2_CFGBASE)
- return (is_end_point(2));
-#endif
-
- return 0;
-}
-
-static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn)
-{
- u8 *base = (u8*)hose->cfg_data;
-
- /* use local configuration space for the first bus */
- if (PCI_BUS(devfn) == 0) {
- if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE0_CFGBASE)
- base = (u8*)CONFIG_SYS_PCIE0_XCFGBASE;
- if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE1_CFGBASE)
- base = (u8*)CONFIG_SYS_PCIE1_XCFGBASE;
-#if CONFIG_SYS_PCIE_NR_PORTS > 2
- if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE2_CFGBASE)
- base = (u8*)CONFIG_SYS_PCIE2_XCFGBASE;
-#endif
- }
-
- return base;
-}
-
-static void pcie_dmer_disable(void)
-{
- mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE),
- mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA);
- mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE),
- mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA);
-#if CONFIG_SYS_PCIE_NR_PORTS > 2
- mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE),
- mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA);
-#endif
-}
-
-static void pcie_dmer_enable(void)
-{
- mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE0_BASE),
- mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA);
- mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE),
- mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA);
-#if CONFIG_SYS_PCIE_NR_PORTS > 2
- mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE),
- mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA);
-#endif
-}
-
-static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
- int offset, int len, u32 *val) {
-
- u8 *address;
- *val = 0;
-
- if (validate_endpoint(hose))
- return 0; /* No upstream config access */
-
- /*
- * Bus numbers are relative to hose->first_busno
- */
- devfn -= PCI_BDF(hose->first_busno, 0, 0);
-
- /*
- * NOTICE: configuration space ranges are currenlty mapped only for
- * the first 16 buses, so such limit must be imposed. In case more
- * buses are required the TLB settings in board/amcc/<board>/init.S
- * need to be altered accordingly (one bus takes 1 MB of memory space).
- */
- if (PCI_BUS(devfn) >= 16)
- return 0;
-
- /*
- * Only single device/single function is supported for the primary and
- * secondary buses of the 440SPe host bridge.
- */
- if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
- ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
- return 0;
-
- address = pcie_get_base(hose, devfn);
- offset += devfn << 4;
-
- /*
- * Reading from configuration space of non-existing device can
- * generate transaction errors. For the read duration we suppress
- * assertion of machine check exceptions to avoid those.
- */
- pcie_dmer_disable ();
-
- debug("%s: cfg_data=%08x offset=%08x\n", __func__, hose->cfg_data, offset);
- switch (len) {
- case 1:
- *val = in_8(hose->cfg_data + offset);
- break;
- case 2:
- *val = in_le16((u16 *)(hose->cfg_data + offset));
- break;
- default:
- *val = in_le32((u32*)(hose->cfg_data + offset));
- break;
- }
-
- pcie_dmer_enable ();
-
- return 0;
-}
-
-static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
- int offset, int len, u32 val) {
-
- u8 *address;
-
- if (validate_endpoint(hose))
- return 0; /* No upstream config access */
-
- /*
- * Bus numbers are relative to hose->first_busno
- */
- devfn -= PCI_BDF(hose->first_busno, 0, 0);
-
- /*
- * Same constraints as in pcie_read_config().
- */
- if (PCI_BUS(devfn) >= 16)
- return 0;
-
- if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
- ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
- return 0;
-
- address = pcie_get_base(hose, devfn);
- offset += devfn << 4;
-
- /*
- * Suppress MCK exceptions, similar to pcie_read_config()
- */
- pcie_dmer_disable ();
-
- switch (len) {
- case 1:
- out_8(hose->cfg_data + offset, val);
- break;
- case 2:
- out_le16((u16 *)(hose->cfg_data + offset), val);
- break;
- default:
- out_le32((u32 *)(hose->cfg_data + offset), val);
- break;
- }
-
- pcie_dmer_enable ();
-
- return 0;
-}
-
-int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 *val)
-{
- u32 v;
- int rv;
-
- rv = pcie_read_config(hose, dev, offset, 1, &v);
- *val = (u8)v;
- return rv;
-}
-
-int pcie_read_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 *val)
-{
- u32 v;
- int rv;
-
- rv = pcie_read_config(hose, dev, offset, 2, &v);
- *val = (u16)v;
- return rv;
-}
-
-int pcie_read_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 *val)
-{
- u32 v;
- int rv;
-
- rv = pcie_read_config(hose, dev, offset, 3, &v);
- *val = (u32)v;
- return rv;
-}
-
-int pcie_write_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 val)
-{
- return pcie_write_config(hose,(u32)dev,offset,1,val);
-}
-
-int pcie_write_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 val)
-{
- return pcie_write_config(hose,(u32)dev,offset,2,(u32 )val);
-}
-
-int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 val)
-{
- return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val);
-}
-
-#if defined(CONFIG_440SPE)
-static void ppc4xx_setup_utl(u32 port) {
-
- volatile void *utl_base = NULL;
-
- /*
- * Map UTL registers
- */
- switch (port) {
- case 0:
- mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
- mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000);
- mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
- mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
- break;
-
- case 1:
- mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
- mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000);
- mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
- mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
- break;
-
- case 2:
- mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
- mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000);
- mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001);
- mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
- break;
- }
- utl_base = (unsigned int *)(CONFIG_SYS_PCIE_BASE + 0x1000 * port);
-
- /*
- * Set buffer allocations and then assert VRB and TXE.
- */
- out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
- out_be32(utl_base + PEUTL_INTR, 0x02000000);
- out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000);
- out_be32(utl_base + PEUTL_PBBSZ, 0x53000000);
- out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000);
- out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000);
- out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
- out_be32(utl_base + PEUTL_PCTL, 0x80800066);
-}
-
-static int check_error(void)
-{
- u32 valPE0, valPE1, valPE2;
- int err = 0;
-
- /* SDR0_PEGPLLLCT1 reset */
- if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000))
- printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0);
-
- valPE0 = SDR_READ(PESDR0_RCSSET);
- valPE1 = SDR_READ(PESDR1_RCSSET);
- valPE2 = SDR_READ(PESDR2_RCSSET);
-
- /* SDR0_PExRCSSET rstgu */
- if (!(valPE0 & 0x01000000) ||
- !(valPE1 & 0x01000000) ||
- !(valPE2 & 0x01000000)) {
- printf("PCIE: SDR0_PExRCSSET rstgu error\n");
- err = -1;
- }
-
- /* SDR0_PExRCSSET rstdl */
- if (!(valPE0 & 0x00010000) ||
- !(valPE1 & 0x00010000) ||
- !(valPE2 & 0x00010000)) {
- printf("PCIE: SDR0_PExRCSSET rstdl error\n");
- err = -1;
- }
-
- /* SDR0_PExRCSSET rstpyn */
- if ((valPE0 & 0x00001000) ||
- (valPE1 & 0x00001000) ||
- (valPE2 & 0x00001000)) {
- printf("PCIE: SDR0_PExRCSSET rstpyn error\n");
- err = -1;
- }
-
- /* SDR0_PExRCSSET hldplb */
- if ((valPE0 & 0x10000000) ||
- (valPE1 & 0x10000000) ||
- (valPE2 & 0x10000000)) {
- printf("PCIE: SDR0_PExRCSSET hldplb error\n");
- err = -1;
- }
-
- /* SDR0_PExRCSSET rdy */
- if ((valPE0 & 0x00100000) ||
- (valPE1 & 0x00100000) ||
- (valPE2 & 0x00100000)) {
- printf("PCIE: SDR0_PExRCSSET rdy error\n");
- err = -1;
- }
-
- /* SDR0_PExRCSSET shutdown */
- if ((valPE0 & 0x00000100) ||
- (valPE1 & 0x00000100) ||
- (valPE2 & 0x00000100)) {
- printf("PCIE: SDR0_PExRCSSET shutdown error\n");
- err = -1;
- }
- return err;
-}
-
-/*
- * Initialize PCI Express core
- */
-int ppc4xx_init_pcie(void)
-{
- int time_out = 20;
-
- /* Set PLL clock receiver to LVPECL */
- SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
-
- if (check_error())
- return -1;
-
- if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000))
- {
- printf("PCIE: PESDR_PLLCT2 resistance calibration failed (0x%08x)\n",
- SDR_READ(PESDR0_PLLLCT2));
- return -1;
- }
- /* De-assert reset of PCIe PLL, wait for lock */
- SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
- udelay(3);
-
- while (time_out) {
- if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) {
- time_out--;
- udelay(1);
- } else
- break;
- }
- if (!time_out) {
- printf("PCIE: VCO output not locked\n");
- return -1;
- }
- return 0;
-}
-#endif
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-static void ppc4xx_setup_utl(u32 port)
-{
- volatile void *utl_base = NULL;
-
- /*
- * Map UTL registers at 0x0801_n000 (4K 0xfff mask) PEGPLn_REGMSK
- */
- switch (port) {
- case 0:
- mtdcr(DCRN_PEGPL_REGBAH(PCIE0), U64_TO_U32_HIGH(CONFIG_SYS_PCIE0_UTLBASE));
- mtdcr(DCRN_PEGPL_REGBAL(PCIE0), U64_TO_U32_LOW(CONFIG_SYS_PCIE0_UTLBASE));
- mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* BAM 11100000=4KB */
- mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0);
- break;
-
- case 1:
- mtdcr(DCRN_PEGPL_REGBAH(PCIE1), U64_TO_U32_HIGH(CONFIG_SYS_PCIE0_UTLBASE));
- mtdcr(DCRN_PEGPL_REGBAL(PCIE1), U64_TO_U32_LOW(CONFIG_SYS_PCIE0_UTLBASE)
- + 0x1000);
- mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* BAM 11100000=4KB */
- mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0);
- break;
- }
- utl_base = (unsigned int *)(CONFIG_SYS_PCIE_BASE + 0x1000 * port);
-
- /*
- * Set buffer allocations and then assert VRB and TXE.
- */
- out_be32(utl_base + PEUTL_PBCTL, 0x0800000c); /* PLBME, CRRE */
- out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
- out_be32(utl_base + PEUTL_INTR, 0x02000000);
- out_be32(utl_base + PEUTL_OPDBSZ, 0x04000000); /* OPD = 512 Bytes */
- out_be32(utl_base + PEUTL_PBBSZ, 0x00000000); /* Max 512 Bytes */
- out_be32(utl_base + PEUTL_IPHBSZ, 0x02000000);
- out_be32(utl_base + PEUTL_IPDBSZ, 0x04000000); /* IPD = 512 Bytes */
- out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
- out_be32(utl_base + PEUTL_PCTL, 0x80800066); /* VRB,TXE,timeout=default */
-}
-
-/*
- * TODO: double check PCI express SDR based on the latest user manual
- * Some registers specified here no longer exist.. has to be
- * updated based on the final EAS spec.
- */
-static int check_error(void)
-{
- u32 valPE0, valPE1;
- int err = 0;
-
- valPE0 = SDR_READ(SDRN_PESDR_RCSSET(0));
- valPE1 = SDR_READ(SDRN_PESDR_RCSSET(1));
-
- /* SDR0_PExRCSSET rstgu */
- if (!(valPE0 & PESDRx_RCSSET_RSTGU) || !(valPE1 & PESDRx_RCSSET_RSTGU)) {
- printf("PCIE: SDR0_PExRCSSET rstgu error\n");
- err = -1;
- }
-
- /* SDR0_PExRCSSET rstdl */
- if (!(valPE0 & PESDRx_RCSSET_RSTDL) || !(valPE1 & PESDRx_RCSSET_RSTDL)) {
- printf("PCIE: SDR0_PExRCSSET rstdl error\n");
- err = -1;
- }
-
- /* SDR0_PExRCSSET rstpyn */
- if ((valPE0 & PESDRx_RCSSET_RSTPYN) || (valPE1 & PESDRx_RCSSET_RSTPYN)) {
- printf("PCIE: SDR0_PExRCSSET rstpyn error\n");
- err = -1;
- }
-
- /* SDR0_PExRCSSET hldplb */
- if ((valPE0 & PESDRx_RCSSET_HLDPLB) || (valPE1 & PESDRx_RCSSET_HLDPLB)) {
- printf("PCIE: SDR0_PExRCSSET hldplb error\n");
- err = -1;
- }
-
- /* SDR0_PExRCSSET rdy */
- if ((valPE0 & PESDRx_RCSSET_RDY) || (valPE1 & PESDRx_RCSSET_RDY)) {
- printf("PCIE: SDR0_PExRCSSET rdy error\n");
- err = -1;
- }
-
- return err;
-}
-
-/*
- * Initialize PCI Express core as described in User Manual
- * TODO: double check PE SDR PLL Register with the updated user manual.
- */
-int ppc4xx_init_pcie(void)
-{
- if (check_error())
- return -1;
-
- return 0;
-}
-#endif /* CONFIG_460EX */
-
-#if defined(CONFIG_405EX)
-static void ppc4xx_setup_utl(u32 port)
-{
- u32 utl_base;
-
- /*
- * Map UTL registers at 0xef4f_n000 (4K 0xfff mask) PEGPLn_REGMSK
- */
- switch (port) {
- case 0:
- mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x00000000);
- mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CONFIG_SYS_PCIE0_UTLBASE);
- mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* 4k region, valid */
- mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0);
- break;
-
- case 1:
- mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x00000000);
- mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CONFIG_SYS_PCIE1_UTLBASE);
- mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* 4k region, valid */
- mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0);
-
- break;
- }
- utl_base = (port==0) ? CONFIG_SYS_PCIE0_UTLBASE : CONFIG_SYS_PCIE1_UTLBASE;
-
- /*
- * Set buffer allocations and then assert VRB and TXE.
- */
- out_be32((u32 *)(utl_base + PEUTL_OUTTR), 0x02000000);
- out_be32((u32 *)(utl_base + PEUTL_INTR), 0x02000000);
- out_be32((u32 *)(utl_base + PEUTL_OPDBSZ), 0x04000000);
- out_be32((u32 *)(utl_base + PEUTL_PBBSZ), 0x21000000);
- out_be32((u32 *)(utl_base + PEUTL_IPHBSZ), 0x02000000);
- out_be32((u32 *)(utl_base + PEUTL_IPDBSZ), 0x04000000);
- out_be32((u32 *)(utl_base + PEUTL_RCIRQEN), 0x00f00000);
- out_be32((u32 *)(utl_base + PEUTL_PCTL), 0x80800066);
-
- out_be32((u32 *)(utl_base + PEUTL_PBCTL), 0x0800000c);
- out_be32((u32 *)(utl_base + PEUTL_RCSTA),
- in_be32((u32 *)(utl_base + PEUTL_RCSTA)) | 0x000040000);
-}
-
-int ppc4xx_init_pcie(void)
-{
- /*
- * Nothing to do on 405EX
- */
- return 0;
-}
-#endif /* CONFIG_405EX */
-
-/*
- * Board-specific pcie initialization
- * Platform code can reimplement ppc4xx_init_pcie_port_hw() if needed
- */
-
-/*
- * Initialize various parts of the PCI Express core for our port:
- *
- * - Set as a root port and enable max width
- * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
- * - Set up UTL configuration.
- * - Increase SERDES drive strength to levels suggested by AMCC.
- * - De-assert RSTPYN, RSTDL and RSTGU.
- *
- * NOTICE for 440SPE revB chip: PESDRn_UTLSET2 is not set - we leave it
- * with default setting 0x11310000. The register has new fields,
- * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core
- * hang.
- */
-#if defined(CONFIG_440SPE)
-int __ppc4xx_init_pcie_port_hw(int port, int rootport)
-{
- u32 val = 1 << 24;
- u32 utlset1;
-
- if (rootport) {
- val = PTYPE_ROOT_PORT << 20;
- utlset1 = 0x21222222;
- } else {
- val = PTYPE_LEGACY_ENDPOINT << 20;
- utlset1 = 0x20222222;
- }
-
- if (port == 0)
- val |= LNKW_X8 << 12;
- else
- val |= LNKW_X4 << 12;
-
- SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
- SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1);
- if (!ppc440spe_revB())
- SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x11000000);
- SDR_WRITE(SDRN_PESDR_HSSL0SET1(port), 0x35000000);
- SDR_WRITE(SDRN_PESDR_HSSL1SET1(port), 0x35000000);
- SDR_WRITE(SDRN_PESDR_HSSL2SET1(port), 0x35000000);
- SDR_WRITE(SDRN_PESDR_HSSL3SET1(port), 0x35000000);
- if (port == 0) {
- SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
- SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
- SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
- SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
- }
- SDR_WRITE(SDRN_PESDR_RCSSET(port), (SDR_READ(SDRN_PESDR_RCSSET(port)) &
- ~(1 << 24 | 1 << 16)) | 1 << 12);
-
- return 0;
-}
-#endif /* CONFIG_440SPE */
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-int __ppc4xx_init_pcie_port_hw(int port, int rootport)
-{
- u32 val;
- u32 utlset1;
-
- if (rootport)
- val = PTYPE_ROOT_PORT << 20;
- else
- val = PTYPE_LEGACY_ENDPOINT << 20;
-
- if (port == 0) {
- val |= LNKW_X1 << 12;
- utlset1 = 0x20000000;
- } else {
- val |= LNKW_X4 << 12;
- utlset1 = 0x20101101;
- }
-
- SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
- SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1);
- SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01210000);
-
- switch (port) {
- case 0:
- SDR_WRITE(PESDR0_L0CDRCTL, 0x00003230);
- SDR_WRITE(PESDR0_L0DRV, 0x00000130);
- SDR_WRITE(PESDR0_L0CLK, 0x00000006);
-
- SDR_WRITE(PESDR0_PHY_CTL_RST,0x10000000);
- break;
-
- case 1:
- SDR_WRITE(PESDR1_L0CDRCTL, 0x00003230);
- SDR_WRITE(PESDR1_L1CDRCTL, 0x00003230);
- SDR_WRITE(PESDR1_L2CDRCTL, 0x00003230);
- SDR_WRITE(PESDR1_L3CDRCTL, 0x00003230);
- SDR_WRITE(PESDR1_L0DRV, 0x00000130);
- SDR_WRITE(PESDR1_L1DRV, 0x00000130);
- SDR_WRITE(PESDR1_L2DRV, 0x00000130);
- SDR_WRITE(PESDR1_L3DRV, 0x00000130);
- SDR_WRITE(PESDR1_L0CLK, 0x00000006);
- SDR_WRITE(PESDR1_L1CLK, 0x00000006);
- SDR_WRITE(PESDR1_L2CLK, 0x00000006);
- SDR_WRITE(PESDR1_L3CLK, 0x00000006);
-
- SDR_WRITE(PESDR1_PHY_CTL_RST,0x10000000);
- break;
- }
-
- SDR_WRITE(SDRN_PESDR_RCSSET(port), SDR_READ(SDRN_PESDR_RCSSET(port)) |
- (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
-
- /* Poll for PHY reset */
- switch (port) {
- case 0:
- while (!(SDR_READ(PESDR0_RSTSTA) & 0x1))
- udelay(10);
- break;
- case 1:
- while (!(SDR_READ(PESDR1_RSTSTA) & 0x1))
- udelay(10);
- break;
- }
-
- SDR_WRITE(SDRN_PESDR_RCSSET(port),
- (SDR_READ(SDRN_PESDR_RCSSET(port)) &
- ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
- PESDRx_RCSSET_RSTPYN);
-
- return 0;
-}
-#endif /* CONFIG_440SPE */
-
-#if defined(CONFIG_405EX)
-int __ppc4xx_init_pcie_port_hw(int port, int rootport)
-{
- u32 val;
-
- if (rootport)
- val = 0x00401000;
- else
- val = 0x00101000;
-
- SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
- SDR_WRITE(SDRN_PESDR_UTLSET1(port), 0x00000000);
- SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01010000);
- SDR_WRITE(SDRN_PESDR_PHYSET1(port), 0x720F0000);
- SDR_WRITE(SDRN_PESDR_PHYSET2(port), 0x70600003);
-
- /* Assert the PE0_PHY reset */
- SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01010000);
- udelay(1000);
-
- /* deassert the PE0_hotreset */
- if (is_end_point(port))
- SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01111000);
- else
- SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01101000);
-
- /* poll for phy !reset */
- while (!(SDR_READ(SDRN_PESDR_PHYSTA(port)) & 0x00001000))
- ;
-
- /* deassert the PE0_gpl_utl_reset */
- SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x00101000);
-
- if (port == 0)
- mtdcr(DCRN_PEGPL_CFG(PCIE0), 0x10000000); /* guarded on */
- else
- mtdcr(DCRN_PEGPL_CFG(PCIE1), 0x10000000); /* guarded on */
-
- return 0;
-}
-#endif /* CONFIG_405EX */
-
-int ppc4xx_init_pcie_port_hw(int port, int rootport)
-__attribute__((weak, alias("__ppc4xx_init_pcie_port_hw")));
-
-/*
- * We map PCI Express configuration access into the 512MB regions
- *
- * NOTICE: revB is very strict about PLB real addressess and ranges to
- * be mapped for config space; it seems to only work with d_nnnn_nnnn
- * range (hangs the core upon config transaction attempts when set
- * otherwise) while revA uses c_nnnn_nnnn.
- *
- * For 440SPe revA:
- * PCIE0: 0xc_4000_0000
- * PCIE1: 0xc_8000_0000
- * PCIE2: 0xc_c000_0000
- *
- * For 440SPe revB:
- * PCIE0: 0xd_0000_0000
- * PCIE1: 0xd_2000_0000
- * PCIE2: 0xd_4000_0000
- *
- * For 405EX:
- * PCIE0: 0xa000_0000
- * PCIE1: 0xc000_0000
- *
- * For 460EX/GT:
- * PCIE0: 0xd_0000_0000
- * PCIE1: 0xd_2000_0000
- */
-static inline u64 ppc4xx_get_cfgaddr(int port)
-{
-#if defined(CONFIG_405EX)
- if (port == 0)
- return (u64)CONFIG_SYS_PCIE0_CFGBASE;
- else
- return (u64)CONFIG_SYS_PCIE1_CFGBASE;
-#endif
-#if defined(CONFIG_440SPE)
- if (ppc440spe_revB()) {
- switch (port) {
- default: /* to satisfy compiler */
- case 0:
- return 0x0000000d00000000ULL;
- case 1:
- return 0x0000000d20000000ULL;
- case 2:
- return 0x0000000d40000000ULL;
- }
- } else {
- switch (port) {
- default: /* to satisfy compiler */
- case 0:
- return 0x0000000c40000000ULL;
- case 1:
- return 0x0000000c80000000ULL;
- case 2:
- return 0x0000000cc0000000ULL;
- }
- }
-#endif
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
- if (port == 0)
- return 0x0000000d00000000ULL;
- else
- return 0x0000000d20000000ULL;
-#endif
-}
-
-/*
- * 4xx boards as end point and root point setup
- * and
- * testing inbound and out bound windows
- *
- * 4xx boards can be plugged into another 4xx boards or you can get PCI-E
- * cable which can be used to setup loop back from one port to another port.
- * Please rememeber that unless there is a endpoint plugged in to root port it
- * will not initialize. It is the same in case of endpoint , unless there is
- * root port attached it will not initialize.
- *
- * In this release of software all the PCI-E ports are configured as either
- * endpoint or rootpoint.In future we will have support for selective ports
- * setup as endpoint and root point in single board.
- *
- * Once your board came up as root point , you can verify by reading
- * /proc/bus/pci/devices. Where you can see the configuration registers
- * of end point device attached to the port.
- *
- * Enpoint cofiguration can be verified by connecting 4xx board to any
- * host or another 4xx board. Then try to scan the device. In case of
- * linux use "lspci" or appripriate os command.
- *
- * How do I verify the inbound and out bound windows ? (4xx to 4xx)
- * in this configuration inbound and outbound windows are setup to access
- * sram memroy area. SRAM is at 0x4 0000 0000 , on PLB bus. This address
- * is mapped at 0x90000000. From u-boot prompt write data 0xb000 0000,
- * This is waere your POM(PLB out bound memory window) mapped. then
- * read the data from other 4xx board's u-boot prompt at address
- * 0x9000 0000(SRAM). Data should match.
- * In case of inbound , write data to u-boot command prompt at 0xb000 0000
- * which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check
- * data at 0x9000 0000(SRAM).Data should match.
- */
-int ppc4xx_init_pcie_port(int port, int rootport)
-{
- static int core_init;
- volatile u32 val = 0;
- int attempts;
- u64 addr;
- u32 low, high;
-
- if (!core_init) {
- if (ppc4xx_init_pcie())
- return -1;
- ++core_init;
- }
-
- /*
- * Initialize various parts of the PCI Express core for our port
- */
- ppc4xx_init_pcie_port_hw(port, rootport);
-
- /*
- * Notice: the following delay has critical impact on device
- * initialization - if too short (<50ms) the link doesn't get up.
- */
- mdelay(100);
-
- val = SDR_READ(SDRN_PESDR_RCSSTS(port));
- if (val & (1 << 20)) {
- printf("PCIE%d: PGRST failed %08x\n", port, val);
- return -1;
- }
-
- /*
- * Verify link is up
- */
- val = SDR_READ(SDRN_PESDR_LOOP(port));
- if (!(val & 0x00001000)) {
- printf("PCIE%d: link is not up.\n", port);
- return -1;
- }
-
- /*
- * Setup UTL registers - but only on revA!
- * We use default settings for revB chip.
- */
- if (!ppc440spe_revB())
- ppc4xx_setup_utl(port);
-
- /*
- * We map PCI Express configuration access into the 512MB regions
- */
- addr = ppc4xx_get_cfgaddr(port);
- low = U64_TO_U32_LOW(addr);
- high = U64_TO_U32_HIGH(addr);
-
- switch (port) {
- case 0:
- mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), high);
- mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), low);
- mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
- break;
- case 1:
- mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), high);
- mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), low);
- mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
- break;
-#if CONFIG_SYS_PCIE_NR_PORTS > 2
- case 2:
- mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), high);
- mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), low);
- mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
- break;
-#endif
- }
-
- /*
- * Check for VC0 active and assert RDY.
- */
- attempts = 10;
- while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 16))) {
- if (!(attempts--)) {
- printf("PCIE%d: VC0 not active\n", port);
- return -1;
- }
- mdelay(1000);
- }
- SDR_WRITE(SDRN_PESDR_RCSSET(port),
- SDR_READ(SDRN_PESDR_RCSSET(port)) | 1 << 20);
- mdelay(100);
-
- return 0;
-}
-
-int ppc4xx_init_pcie_rootport(int port)
-{
- return ppc4xx_init_pcie_port(port, 1);
-}
-
-int ppc4xx_init_pcie_endport(int port)
-{
- return ppc4xx_init_pcie_port(port, 0);
-}
-
-void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
-{
- volatile void *mbase = NULL;
- volatile void *rmbase = NULL;
-
- pci_set_ops(hose,
- pcie_read_config_byte,
- pcie_read_config_word,
- pcie_read_config_dword,
- pcie_write_config_byte,
- pcie_write_config_word,
- pcie_write_config_dword);
-
- switch (port) {
- case 0:
- mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE;
- rmbase = (u32 *)CONFIG_SYS_PCIE0_CFGBASE;
- hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE;
- break;
- case 1:
- mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE;
- rmbase = (u32 *)CONFIG_SYS_PCIE1_CFGBASE;
- hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE;
- break;
-#if CONFIG_SYS_PCIE_NR_PORTS > 2
- case 2:
- mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE;
- rmbase = (u32 *)CONFIG_SYS_PCIE2_CFGBASE;
- hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE;
- break;
-#endif
- }
-
- /*
- * Set bus numbers on our root port
- */
- out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
- out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
- out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
-
- /*
- * Set up outbound translation to hose->mem_space from PLB
- * addresses at an offset of 0xd_0000_0000. We set the low
- * bits of the mask to 11 to turn off splitting into 8
- * subregions and to enable the outbound translation.
- */
- out_le32(mbase + PECFG_POM0LAH, 0x00000000);
- out_le32(mbase + PECFG_POM0LAL, CONFIG_SYS_PCIE_MEMBASE +
- port * CONFIG_SYS_PCIE_MEMSIZE);
- debug("PECFG_POM0LA=%08x.%08x\n", in_le32(mbase + PECFG_POM0LAH),
- in_le32(mbase + PECFG_POM0LAL));
-
- switch (port) {
- case 0:
- mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CONFIG_SYS_PCIE_ADDR_HIGH);
- mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CONFIG_SYS_PCIE_MEMBASE +
- port * CONFIG_SYS_PCIE_MEMSIZE);
- mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
- mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
- ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
- debug("0:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
- mfdcr(DCRN_PEGPL_OMR1BAH(PCIE0)),
- mfdcr(DCRN_PEGPL_OMR1BAL(PCIE0)),
- mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE0)),
- mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE0)));
- break;
- case 1:
- mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CONFIG_SYS_PCIE_ADDR_HIGH);
- mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CONFIG_SYS_PCIE_MEMBASE +
- port * CONFIG_SYS_PCIE_MEMSIZE);
- mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
- mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
- ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
- debug("1:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
- mfdcr(DCRN_PEGPL_OMR1BAH(PCIE1)),
- mfdcr(DCRN_PEGPL_OMR1BAL(PCIE1)),
- mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE1)),
- mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE1)));
- break;
-#if CONFIG_SYS_PCIE_NR_PORTS > 2
- case 2:
- mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CONFIG_SYS_PCIE_ADDR_HIGH);
- mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CONFIG_SYS_PCIE_MEMBASE +
- port * CONFIG_SYS_PCIE_MEMSIZE);
- mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
- mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
- ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
- debug("2:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
- mfdcr(DCRN_PEGPL_OMR1BAH(PCIE2)),
- mfdcr(DCRN_PEGPL_OMR1BAL(PCIE2)),
- mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE2)),
- mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE2)));
- break;
-#endif
- }
-
- /* Set up 4GB inbound memory window at 0 */
- out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
- out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
- out_le32(mbase + PECFG_BAR0HMPA, 0x7ffffff);
- out_le32(mbase + PECFG_BAR0LMPA, 0);
-
- out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
- out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
- out_le32(mbase + PECFG_PIM0LAL, 0);
- out_le32(mbase + PECFG_PIM0LAH, 0);
- out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
- out_le32(mbase + PECFG_PIM1LAH, 0x00000004);
- out_le32(mbase + PECFG_PIMEN, 0x1);
-
- /* Enable I/O, Mem, and Busmaster cycles */
- out_le16((u16 *)(mbase + PCI_COMMAND),
- in_le16((u16 *)(mbase + PCI_COMMAND)) |
- PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-
- /* Set Device and Vendor Id */
- out_le16(mbase + 0x200, 0xaaa0 + port);
- out_le16(mbase + 0x202, 0xbed0 + port);
-
- /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
- out_le32(mbase + 0x208, 0x06040001);
-
- printf("PCIE%d: successfully set as root-complex\n", port);
-}
-
-int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port)
-{
- volatile void *mbase = NULL;
- int attempts = 0;
-
- pci_set_ops(hose,
- pcie_read_config_byte,
- pcie_read_config_word,
- pcie_read_config_dword,
- pcie_write_config_byte,
- pcie_write_config_word,
- pcie_write_config_dword);
-
- switch (port) {
- case 0:
- mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE;
- hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE;
- break;
- case 1:
- mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE;
- hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE;
- break;
-#if defined(CONFIG_SYS_PCIE2_CFGBASE)
- case 2:
- mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE;
- hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE;
- break;
-#endif
- }
-
- /*
- * Set up outbound translation to hose->mem_space from PLB
- * addresses at an offset of 0xd_0000_0000. We set the low
- * bits of the mask to 11 to turn off splitting into 8
- * subregions and to enable the outbound translation.
- */
- out_le32(mbase + PECFG_POM0LAH, 0x00001ff8);
- out_le32(mbase + PECFG_POM0LAL, 0x00001000);
-
- switch (port) {
- case 0:
- mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CONFIG_SYS_PCIE_ADDR_HIGH);
- mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CONFIG_SYS_PCIE_MEMBASE +
- port * CONFIG_SYS_PCIE_MEMSIZE);
- mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
- mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
- ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
- break;
- case 1:
- mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CONFIG_SYS_PCIE_ADDR_HIGH);
- mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CONFIG_SYS_PCIE_MEMBASE +
- port * CONFIG_SYS_PCIE_MEMSIZE);
- mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
- mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
- ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
- break;
-#if CONFIG_SYS_PCIE_NR_PORTS > 2
- case 2:
- mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CONFIG_SYS_PCIE_ADDR_HIGH);
- mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CONFIG_SYS_PCIE_MEMBASE +
- port * CONFIG_SYS_PCIE_MEMSIZE);
- mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
- mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
- ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
- break;
-#endif
- }
-
- /* Set up 64MB inbound memory window at 0 */
- out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
- out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
-
- out_le32(mbase + PECFG_PIM01SAH, 0xffffffff);
- out_le32(mbase + PECFG_PIM01SAL, 0xfc000000);
-
- /* Setup BAR0 */
- out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffff);
- out_le32(mbase + PECFG_BAR0LMPA, 0xfc000000 | PCI_BASE_ADDRESS_MEM_TYPE_64);
-
- /* Disable BAR1 & BAR2 */
- out_le32(mbase + PECFG_BAR1MPA, 0);
- out_le32(mbase + PECFG_BAR2HMPA, 0);
- out_le32(mbase + PECFG_BAR2LMPA, 0);
-
- out_le32(mbase + PECFG_PIM0LAL, U64_TO_U32_LOW(CONFIG_SYS_PCIE_INBOUND_BASE));
- out_le32(mbase + PECFG_PIM0LAH, U64_TO_U32_HIGH(CONFIG_SYS_PCIE_INBOUND_BASE));
- out_le32(mbase + PECFG_PIMEN, 0x1);
-
- /* Enable I/O, Mem, and Busmaster cycles */
- out_le16((u16 *)(mbase + PCI_COMMAND),
- in_le16((u16 *)(mbase + PCI_COMMAND)) |
- PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
- out_le16(mbase + 0x200, 0xcaad); /* Setting vendor ID */
- out_le16(mbase + 0x202, 0xfeed); /* Setting device ID */
-
- /* Set Class Code to Processor/PPC */
- out_le32(mbase + 0x208, 0x0b200001);
-
- attempts = 10;
- while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 8))) {
- if (!(attempts--)) {
- printf("PCIE%d: BME not active\n", port);
- return -1;
- }
- mdelay(1000);
- }
-
- printf("PCIE%d: successfully set as endpoint\n", port);
-
- return 0;
-}
-#endif /* CONFIG_440SPE && CONFIG_PCI */
+++ /dev/null
-/****************************************************************************
-*
-* Video BOOT Graphics Card POST Module
-*
-* ========================================================================
-* Copyright (C) 2007 Freescale Semiconductor, Inc.
-* Jason Jin <Jason.jin@freescale.com>
-*
-* Copyright (C) 1991-2004 SciTech Software, Inc. All rights reserved.
-*
-* This file may be distributed and/or modified under the terms of the
-* GNU General Public License version 2.0 as published by the Free
-* Software Foundation and appearing in the file LICENSE.GPL included
-* in the packaging of this file.
-*
-* Licensees holding a valid Commercial License for this product from
-* SciTech Software, Inc. may use this file in accordance with the
-* Commercial License Agreement provided with the Software.
-*
-* This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING
-* THE WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-* PURPOSE.
-*
-* See http://www.scitechsoft.com/license/ for information about
-* the licensing options available and how to purchase a Commercial
-* License Agreement.
-*
-* Contact license@scitechsoft.com if any conditions of this licensing
-* are not clear to you, or you have questions about licensing options.
-*
-* ========================================================================
-*
-* Language: ANSI C
-* Environment: Linux Kernel
-* Developer: Kendall Bennett
-*
-* Description: Module to implement booting PCI/AGP controllers on the
-* bus. We use the x86 real mode emulator to run the BIOS on
-* graphics controllers to bring the cards up.
-*
-* Note that at present this module does *not* support
-* multiple controllers.
-*
-* The orignal name of this file is warmboot.c.
-* Jason ported this file to u-boot to run the ATI video card
-* BIOS in u-boot.
-****************************************************************************/
-#include <common.h>
-#include "biosemui.h"
-#include <malloc.h>
-
-/* Length of the BIOS image */
-#define MAX_BIOSLEN (128 * 1024L)
-
-/* Define some useful types and macros */
-#define true 1
-#define false 0
-
-/* Place to save PCI BAR's that we change and later restore */
-static u32 saveROMBaseAddress;
-static u32 saveBaseAddress10;
-static u32 saveBaseAddress14;
-static u32 saveBaseAddress18;
-static u32 saveBaseAddress20;
-
-/****************************************************************************
-PARAMETERS:
-pcidev - PCI device info for the video card on the bus to boot
-VGAInfo - BIOS emulator VGA info structure
-
-REMARKS:
-This function executes the BIOS POST code on the controller. We assume that
-at this stage the controller has its I/O and memory space enabled and
-that all other controllers are in a disabled state.
-****************************************************************************/
-static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo * VGAInfo)
-{
- RMREGS regs;
- RMSREGS sregs;
-
- /* Determine the value to store in AX for BIOS POST. Per the PCI specs,
- AH must contain the bus and AL must contain the devfn, encoded as
- (dev << 3) | fn
- */
- memset(®s, 0, sizeof(regs));
- memset(&sregs, 0, sizeof(sregs));
- regs.x.ax = ((int)PCI_BUS(pcidev) << 8) |
- ((int)PCI_DEV(pcidev) << 3) | (int)PCI_FUNC(pcidev);
-
- /*Setup the X86 emulator for the VGA BIOS*/
- BE_setVGA(VGAInfo);
-
- /*Execute the BIOS POST code*/
- BE_callRealMode(0xC000, 0x0003, ®s, &sregs);
-
- /*Cleanup and exit*/
- BE_getVGA(VGAInfo);
-}
-
-/****************************************************************************
-PARAMETERS:
-pcidev - PCI device info for the video card on the bus
-bar - Place to return the base address register offset to use
-
-RETURNS:
-The address to use to map the secondary BIOS (AGP devices)
-
-REMARKS:
-Searches all the PCI base address registers for the device looking for a
-memory mapping that is large enough to hold our ROM BIOS. We usually end up
-finding the framebuffer mapping (usually BAR 0x10), and we use this mapping
-to map the BIOS for the device into. We use a mapping that is already
-assigned to the device to ensure the memory range will be passed through
-by any PCI->PCI or AGP->PCI bridge that may be present.
-
-NOTE: Usually this function is only used for AGP devices, but it may be
- used for PCI devices that have already been POST'ed and the BIOS
- ROM base address has been zero'ed out.
-
-NOTE: This function leaves the original memory aperture disabled by leaving
- it programmed to all 1's. It must be restored to the correct value
- later.
-****************************************************************************/
-static u32 PCI_findBIOSAddr(pci_dev_t pcidev, int *bar)
-{
- u32 base, size;
-
- for (*bar = 0x10; *bar <= 0x14; (*bar) += 4) {
- pci_read_config_dword(pcidev, *bar, &base);
- if (!(base & 0x1)) {
- pci_write_config_dword(pcidev, *bar, 0xFFFFFFFF);
- pci_read_config_dword(pcidev, *bar, &size);
- size = ~(size & ~0xFF) + 1;
- if (size >= MAX_BIOSLEN)
- return base & ~0xFF;
- }
- }
- return 0;
-}
-
-/****************************************************************************
-REMARKS:
-Some non-x86 Linux kernels map PCI relocateable I/O to values that
-are above 64K, which will not work with the BIOS image that requires
-the offset for the I/O ports to be a maximum of 16-bits. Ideally
-someone should fix the kernel to map the I/O ports for VGA compatible
-devices to a different location (or just all I/O ports since it is
-unlikely you can have enough devices in the machine to use up all
-64K of the I/O space - a total of more than 256 cards would be
-necessary).
-
-Anyway to fix this we change all I/O mapped base registers and
-chop off the top bits.
-****************************************************************************/
-static void PCI_fixupIObase(pci_dev_t pcidev, int reg, u32 * base)
-{
- if ((*base & 0x1) && (*base > 0xFFFE)) {
- *base &= 0xFFFF;
- pci_write_config_dword(pcidev, reg, *base);
-
- }
-}
-
-/****************************************************************************
-PARAMETERS:
-pcidev - PCI device info for the video card on the bus
-
-RETURNS:
-Pointers to the mapped BIOS image
-
-REMARKS:
-Maps a pointer to the BIOS image on the graphics card on the PCI bus.
-****************************************************************************/
-void *PCI_mapBIOSImage(pci_dev_t pcidev)
-{
- u32 BIOSImagePhys;
- int BIOSImageBAR;
- u8 *BIOSImage;
-
- /*Save PCI BAR registers that might get changed*/
- pci_read_config_dword(pcidev, PCI_ROM_ADDRESS, &saveROMBaseAddress);
- pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_0, &saveBaseAddress10);
- pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_1, &saveBaseAddress14);
- pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_2, &saveBaseAddress18);
- pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_4, &saveBaseAddress20);
-
- /*Fix up I/O base registers to less than 64K */
- if(saveBaseAddress14 != 0)
- PCI_fixupIObase(pcidev, PCI_BASE_ADDRESS_1, &saveBaseAddress14);
- else
- PCI_fixupIObase(pcidev, PCI_BASE_ADDRESS_4, &saveBaseAddress20);
-
- /* Some cards have problems that stop us from being able to read the
- BIOS image from the ROM BAR. To fix this we have to do some chipset
- specific programming for different cards to solve this problem.
- */
-
- if ((BIOSImagePhys = PCI_findBIOSAddr(pcidev, &BIOSImageBAR)) == 0) {
- printf("Find bios addr error\n");
- return NULL;
- }
-
- BIOSImage = (u8 *) BIOSImagePhys;
-
- /*Change the PCI BAR registers to map it onto the bus.*/
- pci_write_config_dword(pcidev, BIOSImageBAR, 0);
- pci_write_config_dword(pcidev, PCI_ROM_ADDRESS, BIOSImagePhys | 0x1);
-
- udelay(1);
-
- /*Check that the BIOS image is valid. If not fail, or return the
- compiled in BIOS image if that option was enabled
- */
- if (BIOSImage[0] != 0x55 || BIOSImage[1] != 0xAA || BIOSImage[2] == 0) {
- return NULL;
- }
-
- return BIOSImage;
-}
-
-/****************************************************************************
-PARAMETERS:
-pcidev - PCI device info for the video card on the bus
-
-REMARKS:
-Unmaps the BIOS image for the device and restores framebuffer mappings
-****************************************************************************/
-void PCI_unmapBIOSImage(pci_dev_t pcidev, void *BIOSImage)
-{
- pci_write_config_dword(pcidev, PCI_ROM_ADDRESS, saveROMBaseAddress);
- pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_0, saveBaseAddress10);
- pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_1, saveBaseAddress14);
- pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_2, saveBaseAddress18);
- pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_4, saveBaseAddress20);
-}
-
-/****************************************************************************
-PARAMETERS:
-pcidev - PCI device info for the video card on the bus to boot
-VGAInfo - BIOS emulator VGA info structure
-
-RETURNS:
-True if successfully initialised, false if not.
-
-REMARKS:
-Loads and POST's the display controllers BIOS, directly from the BIOS
-image we can extract over the PCI bus.
-****************************************************************************/
-static int PCI_postController(pci_dev_t pcidev, BE_VGAInfo * VGAInfo)
-{
- u32 BIOSImageLen;
- uchar *mappedBIOS;
- uchar *copyOfBIOS;
-
- /*Allocate memory to store copy of BIOS from display controller*/
- if ((mappedBIOS = PCI_mapBIOSImage(pcidev)) == NULL) {
- printf("videoboot: Video ROM failed to map!\n");
- return false;
- }
-
- BIOSImageLen = mappedBIOS[2] * 512;
-
- if ((copyOfBIOS = malloc(BIOSImageLen)) == NULL) {
- printf("videoboot: Out of memory!\n");
- return false;
- }
- memcpy(copyOfBIOS, mappedBIOS, BIOSImageLen);
-
- PCI_unmapBIOSImage(pcidev, mappedBIOS);
-
- /*Save information in VGAInfo structure*/
- VGAInfo->function = PCI_FUNC(pcidev);
- VGAInfo->device = PCI_DEV(pcidev);
- VGAInfo->bus = PCI_BUS(pcidev);
- VGAInfo->pcidev = pcidev;
- VGAInfo->BIOSImage = copyOfBIOS;
- VGAInfo->BIOSImageLen = BIOSImageLen;
-
- /*Now execute the BIOS POST for the device*/
- if (copyOfBIOS[0] != 0x55 || copyOfBIOS[1] != 0xAA) {
- printf("videoboot: Video ROM image is invalid!\n");
- return false;
- }
-
- PCI_doBIOSPOST(pcidev, VGAInfo);
-
- /*Reset the size of the BIOS image to the final size*/
- VGAInfo->BIOSImageLen = copyOfBIOS[2] * 512;
- return true;
-}
-
-/****************************************************************************
-PARAMETERS:
-pcidev - PCI device info for the video card on the bus to boot
-pVGAInfo - Place to return VGA info structure is requested
-cleanUp - True to clean up on exit, false to leave emulator active
-
-REMARKS:
-Boots the PCI/AGP video card on the bus using the Video ROM BIOS image
-and the X86 BIOS emulator module.
-****************************************************************************/
-int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo ** pVGAInfo, int cleanUp)
-{
- BE_VGAInfo *VGAInfo;
-
- printf("videoboot: Booting PCI video card bus %d, function %d, device %d\n",
- PCI_BUS(pcidev), PCI_FUNC(pcidev), PCI_DEV(pcidev));
-
- /*Initialise the x86 BIOS emulator*/
- if ((VGAInfo = malloc(sizeof(*VGAInfo))) == NULL) {
- printf("videoboot: Out of memory!\n");
- return false;
- }
- memset(VGAInfo, 0, sizeof(*VGAInfo));
- BE_init(0, 65536, VGAInfo, 0);
-
- /*Post all the display controller BIOS'es*/
- PCI_postController(pcidev, VGAInfo);
-
- /*Cleanup and exit the emulator if requested. If the BIOS emulator
- is needed after booting the card, we will not call BE_exit and
- leave it enabled for further use (ie: VESA driver etc).
- */
- if (cleanUp) {
- BE_exit();
- if (VGAInfo->BIOSImage)
- free(VGAInfo->BIOSImage);
- free(VGAInfo);
- VGAInfo = NULL;
- }
- /*Return VGA info pointer if the caller requested it*/
- if (pVGAInfo)
- *pVGAInfo = VGAInfo;
- return true;
-}
+++ /dev/null
-/****************************************************************************
-*
-* BIOS emulator and interface
-* to Realmode X86 Emulator Library
-*
-* ========================================================================
-*
-* Copyright (C) 2007 Freescale Semiconductor, Inc.
-* Jason Jin<Jason.jin@freescale.com>
-*
-* Copyright (C) 1991-2004 SciTech Software, Inc. All rights reserved.
-*
-* This file may be distributed and/or modified under the terms of the
-* GNU General Public License version 2.0 as published by the Free
-* Software Foundation and appearing in the file LICENSE.GPL included
-* in the packaging of this file.
-*
-* Licensees holding a valid Commercial License for this product from
-* SciTech Software, Inc. may use this file in accordance with the
-* Commercial License Agreement provided with the Software.
-*
-* This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING
-* THE WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-* PURPOSE.
-*
-* See http://www.scitechsoft.com/license/ for information about
-* the licensing options available and how to purchase a Commercial
-* License Agreement.
-*
-* Contact license@scitechsoft.com if any conditions of this licensing
-* are not clear to you, or you have questions about licensing options.
-*
-* ========================================================================
-*
-* Language: ANSI C
-* Environment: Any
-* Developer: Kendall Bennett
-*
-* Description: This file includes BIOS emulator I/O and memory access
-* functions.
-*
-* Jason ported this file to u-boot to run the ATI video card
-* BIOS in u-boot. Removed some emulate functions such as the
-* timer port access. Made all the VGA port except reading 0x3c3
-* be emulated. Seems like reading 0x3c3 should return the high
-* 16 bit of the io port.
-*
-****************************************************************************/
-
-#include <common.h>
-#include "biosemui.h"
-
-/*------------------------- Global Variables ------------------------------*/
-
-#ifndef __i386__
-static char *BE_biosDate = "08/14/99";
-static u8 BE_model = 0xFC;
-static u8 BE_submodel = 0x00;
-#endif
-
-/*----------------------------- Implementation ----------------------------*/
-
-/****************************************************************************
-PARAMETERS:
-addr - Emulator memory address to convert
-
-RETURNS:
-Actual memory address to read or write the data
-
-REMARKS:
-This function converts an emulator memory address in a 32-bit range to
-a real memory address that we wish to access. It handles splitting up the
-memory address space appropriately to access the emulator BIOS image, video
-memory and system BIOS etc.
-****************************************************************************/
-static u8 *BE_memaddr(u32 addr)
-{
- if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) {
- return (u8*)(_BE_env.biosmem_base + addr - 0xC0000);
- } else if (addr > _BE_env.biosmem_limit && addr < 0xD0000) {
- DB(printf("BE_memaddr: address %#lx may be invalid!\n", addr);)
- return M.mem_base;
- } else if (addr >= 0xA0000 && addr <= 0xBFFFF) {
- return (u8*)(_BE_env.busmem_base + addr - 0xA0000);
- }
-#ifdef __i386__
- else if (addr >= 0xD0000 && addr <= 0xFFFFF) {
- /* We map the real System BIOS directly on real PC's */
- DB(printf("BE_memaddr: System BIOS address %#lx\n", addr);)
- return _BE_env.busmem_base + addr - 0xA0000;
- }
-#else
- else if (addr >= 0xFFFF5 && addr < 0xFFFFE) {
- /* Return a faked BIOS date string for non-x86 machines */
- DB(printf("BE_memaddr - Returning BIOS date\n");)
- return (u8 *)(BE_biosDate + addr - 0xFFFF5);
- } else if (addr == 0xFFFFE) {
- /* Return system model identifier for non-x86 machines */
- DB(printf("BE_memaddr - Returning model\n");)
- return &BE_model;
- } else if (addr == 0xFFFFF) {
- /* Return system submodel identifier for non-x86 machines */
- DB(printf("BE_memaddr - Returning submodel\n");)
- return &BE_submodel;
- }
-#endif
- else if (addr > M.mem_size - 1) {
- HALT_SYS();
- return M.mem_base;
- }
-
- return M.mem_base + addr;
-}
-
-/****************************************************************************
-PARAMETERS:
-addr - Emulator memory address to read
-
-RETURNS:
-Byte value read from emulator memory.
-
-REMARKS:
-Reads a byte value from the emulator memory. We have three distinct memory
-regions that are handled differently, which this function handles.
-****************************************************************************/
-u8 X86API BE_rdb(u32 addr)
-{
- if (_BE_env.emulateVGA && addr >= 0xA0000 && addr <= 0xBFFFF)
- return 0;
- else {
- u8 val = readb_le(BE_memaddr(addr));
- return val;
- }
-}
-
-/****************************************************************************
-PARAMETERS:
-addr - Emulator memory address to read
-
-RETURNS:
-Word value read from emulator memory.
-
-REMARKS:
-Reads a word value from the emulator memory. We have three distinct memory
-regions that are handled differently, which this function handles.
-****************************************************************************/
-u16 X86API BE_rdw(u32 addr)
-{
- if (_BE_env.emulateVGA && addr >= 0xA0000 && addr <= 0xBFFFF)
- return 0;
- else {
- u8 *base = BE_memaddr(addr);
- u16 val = readw_le(base);
- return val;
- }
-}
-
-/****************************************************************************
-PARAMETERS:
-addr - Emulator memory address to read
-
-RETURNS:
-Long value read from emulator memory.
-
-REMARKS:
-Reads a 32-bit value from the emulator memory. We have three distinct memory
-regions that are handled differently, which this function handles.
-****************************************************************************/
-u32 X86API BE_rdl(u32 addr)
-{
- if (_BE_env.emulateVGA && addr >= 0xA0000 && addr <= 0xBFFFF)
- return 0;
- else {
- u8 *base = BE_memaddr(addr);
- u32 val = readl_le(base);
- return val;
- }
-}
-
-/****************************************************************************
-PARAMETERS:
-addr - Emulator memory address to read
-val - Value to store
-
-REMARKS:
-Writes a byte value to emulator memory. We have three distinct memory
-regions that are handled differently, which this function handles.
-****************************************************************************/
-void X86API BE_wrb(u32 addr, u8 val)
-{
- if (!(_BE_env.emulateVGA && addr >= 0xA0000 && addr <= 0xBFFFF)) {
- writeb_le(BE_memaddr(addr), val);
- }
-}
-
-/****************************************************************************
-PARAMETERS:
-addr - Emulator memory address to read
-val - Value to store
-
-REMARKS:
-Writes a word value to emulator memory. We have three distinct memory
-regions that are handled differently, which this function handles.
-****************************************************************************/
-void X86API BE_wrw(u32 addr, u16 val)
-{
- if (!(_BE_env.emulateVGA && addr >= 0xA0000 && addr <= 0xBFFFF)) {
- u8 *base = BE_memaddr(addr);
- writew_le(base, val);
-
- }
-}
-
-/****************************************************************************
-PARAMETERS:
-addr - Emulator memory address to read
-val - Value to store
-
-REMARKS:
-Writes a 32-bit value to emulator memory. We have three distinct memory
-regions that are handled differently, which this function handles.
-****************************************************************************/
-void X86API BE_wrl(u32 addr, u32 val)
-{
- if (!(_BE_env.emulateVGA && addr >= 0xA0000 && addr <= 0xBFFFF)) {
- u8 *base = BE_memaddr(addr);
- writel_le(base, val);
- }
-}
-
-#if defined(DEBUG) || !defined(__i386__)
-
-/* For Non-Intel machines we may need to emulate some I/O port accesses that
- * the BIOS may try to access, such as the PCI config registers.
- */
-
-#define IS_TIMER_PORT(port) (0x40 <= port && port <= 0x43)
-#define IS_CMOS_PORT(port) (0x70 <= port && port <= 0x71)
-/*#define IS_VGA_PORT(port) (_BE_env.emulateVGA && 0x3C0 <= port && port <= 0x3DA)*/
-#define IS_VGA_PORT(port) (0x3C0 <= port && port <= 0x3DA)
-#define IS_PCI_PORT(port) (0xCF8 <= port && port <= 0xCFF)
-#define IS_SPKR_PORT(port) (port == 0x61)
-
-/****************************************************************************
-PARAMETERS:
-port - Port to read from
-type - Type of access to perform
-
-REMARKS:
-Performs an emulated read from the Standard VGA I/O ports. If the target
-hardware does not support mapping the VGA I/O and memory (such as some
-PowerPC systems), we emulate the VGA so that the BIOS will still be able to
-set NonVGA display modes such as on ATI hardware.
-****************************************************************************/
-static u8 VGA_inpb (const int port)
-{
- u8 val = 0xff;
-
- switch (port) {
- case 0x3C0:
- /* 3C0 has funky characteristics because it can act as either
- a data register or index register depending on the state
- of an internal flip flop in the hardware. Hence we have
- to emulate that functionality in here. */
- if (_BE_env.flipFlop3C0 == 0) {
- /* Access 3C0 as index register */
- val = _BE_env.emu3C0;
- } else {
- /* Access 3C0 as data register */
- if (_BE_env.emu3C0 < ATT_C)
- val = _BE_env.emu3C1[_BE_env.emu3C0];
- }
- _BE_env.flipFlop3C0 ^= 1;
- break;
- case 0x3C1:
- if (_BE_env.emu3C0 < ATT_C)
- return _BE_env.emu3C1[_BE_env.emu3C0];
- break;
- case 0x3CC:
- return _BE_env.emu3C2;
- case 0x3C4:
- return _BE_env.emu3C4;
- case 0x3C5:
- if (_BE_env.emu3C4 < ATT_C)
- return _BE_env.emu3C5[_BE_env.emu3C4];
- break;
- case 0x3C6:
- return _BE_env.emu3C6;
- case 0x3C7:
- return _BE_env.emu3C7;
- case 0x3C8:
- return _BE_env.emu3C8;
- case 0x3C9:
- if (_BE_env.emu3C7 < PAL_C)
- return _BE_env.emu3C9[_BE_env.emu3C7++];
- break;
- case 0x3CE:
- return _BE_env.emu3CE;
- case 0x3CF:
- if (_BE_env.emu3CE < GRA_C)
- return _BE_env.emu3CF[_BE_env.emu3CE];
- break;
- case 0x3D4:
- if (_BE_env.emu3C2 & 0x1)
- return _BE_env.emu3D4;
- break;
- case 0x3D5:
- if ((_BE_env.emu3C2 & 0x1) && (_BE_env.emu3D4 < CRT_C))
- return _BE_env.emu3D5[_BE_env.emu3D4];
- break;
- case 0x3DA:
- _BE_env.flipFlop3C0 = 0;
- val = _BE_env.emu3DA;
- _BE_env.emu3DA ^= 0x9;
- break;
- }
- return val;
-}
-
-/****************************************************************************
-PARAMETERS:
-port - Port to write to
-type - Type of access to perform
-
-REMARKS:
-Performs an emulated write to one of the 8253 timer registers. For now
-we only emulate timer 0 which is the only timer that the BIOS code appears
-to use.
-****************************************************************************/
-static void VGA_outpb (int port, u8 val)
-{
- switch (port) {
- case 0x3C0:
- /* 3C0 has funky characteristics because it can act as either
- a data register or index register depending on the state
- of an internal flip flop in the hardware. Hence we have
- to emulate that functionality in here. */
- if (_BE_env.flipFlop3C0 == 0) {
- /* Access 3C0 as index register */
- _BE_env.emu3C0 = val;
- } else {
- /* Access 3C0 as data register */
- if (_BE_env.emu3C0 < ATT_C)
- _BE_env.emu3C1[_BE_env.emu3C0] = val;
- }
- _BE_env.flipFlop3C0 ^= 1;
- break;
- case 0x3C2:
- _BE_env.emu3C2 = val;
- break;
- case 0x3C4:
- _BE_env.emu3C4 = val;
- break;
- case 0x3C5:
- if (_BE_env.emu3C4 < ATT_C)
- _BE_env.emu3C5[_BE_env.emu3C4] = val;
- break;
- case 0x3C6:
- _BE_env.emu3C6 = val;
- break;
- case 0x3C7:
- _BE_env.emu3C7 = (int) val *3;
-
- break;
- case 0x3C8:
- _BE_env.emu3C8 = (int) val *3;
-
- break;
- case 0x3C9:
- if (_BE_env.emu3C8 < PAL_C)
- _BE_env.emu3C9[_BE_env.emu3C8++] = val;
- break;
- case 0x3CE:
- _BE_env.emu3CE = val;
- break;
- case 0x3CF:
- if (_BE_env.emu3CE < GRA_C)
- _BE_env.emu3CF[_BE_env.emu3CE] = val;
- break;
- case 0x3D4:
- if (_BE_env.emu3C2 & 0x1)
- _BE_env.emu3D4 = val;
- break;
- case 0x3D5:
- if ((_BE_env.emu3C2 & 0x1) && (_BE_env.emu3D4 < CRT_C))
- _BE_env.emu3D5[_BE_env.emu3D4] = val;
- break;
- }
-}
-
-/****************************************************************************
-PARAMETERS:
-regOffset - Offset into register space for non-DWORD accesses
-value - Value to write to register for PCI_WRITE_* operations
-func - Function to perform (PCIAccessRegFlags)
-
-RETURNS:
-Value read from configuration register for PCI_READ_* operations
-
-REMARKS:
-Accesses a PCI configuration space register by decoding the value currently
-stored in the _BE_env.configAddress variable and passing it through to the
-portable PCI_accessReg function.
-****************************************************************************/
-static u32 BE_accessReg(int regOffset, u32 value, int func)
-{
-#ifdef __KERNEL__
- int function, device, bus;
- u8 val8;
- u16 val16;
- u32 val32;
-
-
- /* Decode the configuration register values for the register we wish to
- * access
- */
- regOffset += (_BE_env.configAddress & 0xFF);
- function = (_BE_env.configAddress >> 8) & 0x7;
- device = (_BE_env.configAddress >> 11) & 0x1F;
- bus = (_BE_env.configAddress >> 16) & 0xFF;
-
- /* Ignore accesses to all devices other than the one we're POSTing */
- if ((function == _BE_env.vgaInfo.function) &&
- (device == _BE_env.vgaInfo.device) &&
- (bus == _BE_env.vgaInfo.bus)) {
- switch (func) {
- case REG_READ_BYTE:
- pci_read_config_byte(_BE_env.vgaInfo.pcidev, regOffset,
- &val8);
- return val8;
- case REG_READ_WORD:
- pci_read_config_word(_BE_env.vgaInfo.pcidev, regOffset,
- &val16);
- return val16;
- case REG_READ_DWORD:
- pci_read_config_dword(_BE_env.vgaInfo.pcidev, regOffset,
- &val32);
- return val32;
- case REG_WRITE_BYTE:
- pci_write_config_byte(_BE_env.vgaInfo.pcidev, regOffset,
- value);
-
- return 0;
- case REG_WRITE_WORD:
- pci_write_config_word(_BE_env.vgaInfo.pcidev, regOffset,
- value);
-
- return 0;
- case REG_WRITE_DWORD:
- pci_write_config_dword(_BE_env.vgaInfo.pcidev,
- regOffset, value);
-
- return 0;
- }
- }
- return 0;
-#else
- PCIDeviceInfo pciInfo;
-
- pciInfo.mech1 = 1;
- pciInfo.slot.i = 0;
- pciInfo.slot.p.Function = (_BE_env.configAddress >> 8) & 0x7;
- pciInfo.slot.p.Device = (_BE_env.configAddress >> 11) & 0x1F;
- pciInfo.slot.p.Bus = (_BE_env.configAddress >> 16) & 0xFF;
- pciInfo.slot.p.Enable = 1;
-
- /* Ignore accesses to all devices other than the one we're POSTing */
- if ((pciInfo.slot.p.Function ==
- _BE_env.vgaInfo.pciInfo->slot.p.Function)
- && (pciInfo.slot.p.Device == _BE_env.vgaInfo.pciInfo->slot.p.Device)
- && (pciInfo.slot.p.Bus == _BE_env.vgaInfo.pciInfo->slot.p.Bus))
- return PCI_accessReg((_BE_env.configAddress & 0xFF) + regOffset,
- value, func, &pciInfo);
- return 0;
-#endif
-}
-
-/****************************************************************************
-PARAMETERS:
-port - Port to read from
-type - Type of access to perform
-
-REMARKS:
-Performs an emulated read from one of the PCI configuration space registers.
-We emulate this using our PCI_accessReg function which will access the PCI
-configuration space registers in a portable fashion.
-****************************************************************************/
-static u32 PCI_inp(int port, int type)
-{
- switch (type) {
- case REG_READ_BYTE:
- if ((_BE_env.configAddress & 0x80000000) && 0xCFC <= port
- && port <= 0xCFF)
- return BE_accessReg(port - 0xCFC, 0, REG_READ_BYTE);
- break;
- case REG_READ_WORD:
- if ((_BE_env.configAddress & 0x80000000) && 0xCFC <= port
- && port <= 0xCFF)
- return BE_accessReg(port - 0xCFC, 0, REG_READ_WORD);
- break;
- case REG_READ_DWORD:
- if (port == 0xCF8)
- return _BE_env.configAddress;
- else if ((_BE_env.configAddress & 0x80000000) && port == 0xCFC)
- return BE_accessReg(0, 0, REG_READ_DWORD);
- break;
- }
- return 0;
-}
-
-/****************************************************************************
-PARAMETERS:
-port - Port to write to
-type - Type of access to perform
-
-REMARKS:
-Performs an emulated write to one of the PCI control registers.
-****************************************************************************/
-static void PCI_outp(int port, u32 val, int type)
-{
- switch (type) {
- case REG_WRITE_BYTE:
- if ((_BE_env.configAddress & 0x80000000) && 0xCFC <= port
- && port <= 0xCFF)
- BE_accessReg(port - 0xCFC, val, REG_WRITE_BYTE);
- break;
- case REG_WRITE_WORD:
- if ((_BE_env.configAddress & 0x80000000) && 0xCFC <= port
- && port <= 0xCFF)
- BE_accessReg(port - 0xCFC, val, REG_WRITE_WORD);
- break;
- case REG_WRITE_DWORD:
- if (port == 0xCF8)
- {
- _BE_env.configAddress = val & 0x80FFFFFC;
- }
- else if ((_BE_env.configAddress & 0x80000000) && port == 0xCFC)
- BE_accessReg(0, val, REG_WRITE_DWORD);
- break;
- }
-}
-
-#endif
-
-/****************************************************************************
-PARAMETERS:
-port - Port to write to
-
-RETURNS:
-Value read from the I/O port
-
-REMARKS:
-Performs an emulated 8-bit read from an I/O port. We handle special cases
-that we need to emulate in here, and fall through to reflecting the write
-through to the real hardware if we don't need to special case it.
-****************************************************************************/
-u8 X86API BE_inb(X86EMU_pioAddr port)
-{
- u8 val = 0;
-
-#if defined(DEBUG) || !defined(__i386__)
- if (IS_VGA_PORT(port)){
- /*seems reading port 0x3c3 return the high 16 bit of io port*/
- if(port == 0x3c3)
- val = LOG_inpb(port);
- else
- val = VGA_inpb(port);
- }
- else if (IS_TIMER_PORT(port))
- DB(printf("Can not interept TIMER port now!\n");)
- else if (IS_SPKR_PORT(port))
- DB(printf("Can not interept SPEAKER port now!\n");)
- else if (IS_CMOS_PORT(port))
- DB(printf("Can not interept CMOS port now!\n");)
- else if (IS_PCI_PORT(port))
- val = PCI_inp(port, REG_READ_BYTE);
- else if (port < 0x100) {
- DB(printf("WARN: INVALID inb.%04X -> %02X\n", (u16) port, val);)
- val = LOG_inpb(port);
- } else
-#endif
- val = LOG_inpb(port);
- return val;
-}
-
-/****************************************************************************
-PARAMETERS:
-port - Port to write to
-
-RETURNS:
-Value read from the I/O port
-
-REMARKS:
-Performs an emulated 16-bit read from an I/O port. We handle special cases
-that we need to emulate in here, and fall through to reflecting the write
-through to the real hardware if we don't need to special case it.
-****************************************************************************/
-u16 X86API BE_inw(X86EMU_pioAddr port)
-{
- u16 val = 0;
-
-#if defined(DEBUG) || !defined(__i386__)
- if (IS_PCI_PORT(port))
- val = PCI_inp(port, REG_READ_WORD);
- else if (port < 0x100) {
- DB(printf("WARN: Maybe INVALID inw.%04X -> %04X\n", (u16) port, val);)
- val = LOG_inpw(port);
- } else
-#endif
- val = LOG_inpw(port);
- return val;
-}
-
-/****************************************************************************
-PARAMETERS:
-port - Port to write to
-
-RETURNS:
-Value read from the I/O port
-
-REMARKS:
-Performs an emulated 32-bit read from an I/O port. We handle special cases
-that we need to emulate in here, and fall through to reflecting the write
-through to the real hardware if we don't need to special case it.
-****************************************************************************/
-u32 X86API BE_inl(X86EMU_pioAddr port)
-{
- u32 val = 0;
-
-#if defined(DEBUG) || !defined(__i386__)
- if (IS_PCI_PORT(port))
- val = PCI_inp(port, REG_READ_DWORD);
- else if (port < 0x100) {
- val = LOG_inpd(port);
- } else
-#endif
- val = LOG_inpd(port);
- return val;
-}
-
-/****************************************************************************
-PARAMETERS:
-port - Port to write to
-val - Value to write to port
-
-REMARKS:
-Performs an emulated 8-bit write to an I/O port. We handle special cases
-that we need to emulate in here, and fall through to reflecting the write
-through to the real hardware if we don't need to special case it.
-****************************************************************************/
-void X86API BE_outb(X86EMU_pioAddr port, u8 val)
-{
-#if defined(DEBUG) || !defined(__i386__)
- if (IS_VGA_PORT(port))
- VGA_outpb(port, val);
- else if (IS_TIMER_PORT(port))
- DB(printf("Can not interept TIMER port now!\n");)
- else if (IS_SPKR_PORT(port))
- DB(printf("Can not interept SPEAKER port now!\n");)
- else if (IS_CMOS_PORT(port))
- DB(printf("Can not interept CMOS port now!\n");)
- else if (IS_PCI_PORT(port))
- PCI_outp(port, val, REG_WRITE_BYTE);
- else if (port < 0x100) {
- DB(printf("WARN:Maybe INVALID outb.%04X <- %02X\n", (u16) port, val);)
- LOG_outpb(port, val);
- } else
-#endif
- LOG_outpb(port, val);
-}
-
-/****************************************************************************
-PARAMETERS:
-port - Port to write to
-val - Value to write to port
-
-REMARKS:
-Performs an emulated 16-bit write to an I/O port. We handle special cases
-that we need to emulate in here, and fall through to reflecting the write
-through to the real hardware if we don't need to special case it.
-****************************************************************************/
-void X86API BE_outw(X86EMU_pioAddr port, u16 val)
-{
-#if defined(DEBUG) || !defined(__i386__)
- if (IS_VGA_PORT(port)) {
- VGA_outpb(port, val);
- VGA_outpb(port + 1, val >> 8);
- } else if (IS_PCI_PORT(port))
- PCI_outp(port, val, REG_WRITE_WORD);
- else if (port < 0x100) {
- DB(printf("WARN: MAybe INVALID outw.%04X <- %04X\n", (u16) port,
- val);)
- LOG_outpw(port, val);
- } else
-#endif
- LOG_outpw(port, val);
-}
-
-/****************************************************************************
-PARAMETERS:
-port - Port to write to
-val - Value to write to port
-
-REMARKS:
-Performs an emulated 32-bit write to an I/O port. We handle special cases
-that we need to emulate in here, and fall through to reflecting the write
-through to the real hardware if we don't need to special case it.
-****************************************************************************/
-void X86API BE_outl(X86EMU_pioAddr port, u32 val)
-{
-#if defined(DEBUG) || !defined(__i386__)
- if (IS_PCI_PORT(port))
- PCI_outp(port, val, REG_WRITE_DWORD);
- else if (port < 0x100) {
- DB(printf("WARN: INVALID outl.%04X <- %08X\n", (u16) port,val);)
- LOG_outpd(port, val);
- } else
-#endif
- LOG_outpd(port, val);
-}
+++ /dev/null
-/*
- * Copyright (C) Procsys. All rights reserved.
- * Author: Mushtaq Khan <mushtaq_k@procsys.com>
- * <mushtaqk_921@yahoo.co.in>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * with the reference to ata_piix driver in kernel 2.4.32
- */
-
-/*
- * This file contains SATA controller and SATA drive initialization functions
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <pci.h>
-#include <command.h>
-#include <config.h>
-#include <asm/byteorder.h>
-#include <part.h>
-#include <ide.h>
-#include <ata.h>
-
-extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
-extern int sata_curr_device;
-
-#define DEBUG_SATA 0 /*For debug prints set DEBUG_SATA to 1 */
-
-#define SATA_DECL
-#define DRV_DECL /*For file specific declarations */
-#include "ata_piix.h"
-
-/*Macros realted to PCI*/
-#define PCI_SATA_BUS 0x00
-#define PCI_SATA_DEV 0x1f
-#define PCI_SATA_FUNC 0x02
-
-#define PCI_SATA_BASE1 0x10
-#define PCI_SATA_BASE2 0x14
-#define PCI_SATA_BASE3 0x18
-#define PCI_SATA_BASE4 0x1c
-#define PCI_SATA_BASE5 0x20
-#define PCI_PMR 0x90
-#define PCI_PI 0x09
-#define PCI_PCS 0x92
-#define PCI_DMA_CTL 0x48
-
-#define PORT_PRESENT (1<<0)
-#define PORT_ENABLED (1<<4)
-
-u32 bdf;
-u32 iobase1 = 0; /*Primary cmd block */
-u32 iobase2 = 0; /*Primary ctl block */
-u32 iobase3 = 0; /*Sec cmd block */
-u32 iobase4 = 0; /*sec ctl block */
-u32 iobase5 = 0; /*BMDMA*/
-int
-pci_sata_init (void)
-{
- u32 bus = PCI_SATA_BUS;
- u32 dev = PCI_SATA_DEV;
- u32 fun = PCI_SATA_FUNC;
- u16 cmd = 0;
- u8 lat = 0, pcibios_max_latency = 0xff;
- u8 pmr; /*Port mapping reg */
- u8 pi; /*Prgming Interface reg */
-
- bdf = PCI_BDF (bus, dev, fun);
- pci_read_config_dword (bdf, PCI_SATA_BASE1, &iobase1);
- pci_read_config_dword (bdf, PCI_SATA_BASE2, &iobase2);
- pci_read_config_dword (bdf, PCI_SATA_BASE3, &iobase3);
- pci_read_config_dword (bdf, PCI_SATA_BASE4, &iobase4);
- pci_read_config_dword (bdf, PCI_SATA_BASE5, &iobase5);
-
- if ((iobase1 == 0xFFFFFFFF) || (iobase2 == 0xFFFFFFFF) ||
- (iobase3 == 0xFFFFFFFF) || (iobase4 == 0xFFFFFFFF) ||
- (iobase5 == 0xFFFFFFFF)) {
- printf ("error no base addr for SATA controller\n");
- return 1;
- /*ERROR*/}
-
- iobase1 &= 0xFFFFFFFE;
- iobase2 &= 0xFFFFFFFE;
- iobase3 &= 0xFFFFFFFE;
- iobase4 &= 0xFFFFFFFE;
- iobase5 &= 0xFFFFFFFE;
-
- /*check for mode */
- pci_read_config_byte (bdf, PCI_PMR, &pmr);
- if (pmr > 1) {
- printf ("combined mode not supported\n");
- return 1;
- }
-
- pci_read_config_byte (bdf, PCI_PI, &pi);
- if ((pi & 0x05) != 0x05) {
- printf ("Sata is in Legacy mode\n");
- return 1;
- } else {
- printf ("sata is in Native mode\n");
- }
-
- /*MASTER CFG AND IO CFG */
- pci_read_config_word (bdf, PCI_COMMAND, &cmd);
- cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
- pci_write_config_word (bdf, PCI_COMMAND, cmd);
- pci_read_config_byte (dev, PCI_LATENCY_TIMER, &lat);
-
- if (lat < 16)
- lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
- else if (lat > pcibios_max_latency)
- lat = pcibios_max_latency;
- pci_write_config_byte (dev, PCI_LATENCY_TIMER, lat);
-
- return 0;
-}
-
-int
-sata_bus_probe (int port_no)
-{
- int orig_mask, mask;
- u16 pcs;
-
- mask = (PORT_PRESENT << port_no);
- pci_read_config_word (bdf, PCI_PCS, &pcs);
- orig_mask = (int) pcs & 0xff;
- if ((orig_mask & mask) != mask)
- return 0;
- else
- return 1;
-}
-
-int
-init_sata (int dev)
-{
- static int done = 0;
- u8 i, rv = 0;
-
- if (!done)
- done = 1;
- else
- return 0;
-
- rv = pci_sata_init ();
- if (rv == 1) {
- printf ("pci initialization failed\n");
- return 1;
- }
-
- port[0].port_no = 0;
- port[0].ioaddr.cmd_addr = iobase1;
- port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr =
- iobase2 | ATA_PCI_CTL_OFS;
- port[0].ioaddr.bmdma_addr = iobase5;
-
- port[1].port_no = 1;
- port[1].ioaddr.cmd_addr = iobase3;
- port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr =
- iobase4 | ATA_PCI_CTL_OFS;
- port[1].ioaddr.bmdma_addr = iobase5 + 0x8;
-
- for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++)
- sata_port (&port[i].ioaddr);
-
- for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++) {
- if (!(sata_bus_probe (i))) {
- port[i].port_state = 0;
- printf ("SATA#%d port is not present \n", i);
- } else {
- printf ("SATA#%d port is present\n", i);
- if (sata_bus_softreset (i)) {
- port[i].port_state = 0;
- } else {
- port[i].port_state = 1;
- }
- }
- }
-
- for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++) {
- u8 j, devno;
-
- if (port[i].port_state == 0)
- continue;
- for (j = 0; j < CONFIG_SYS_SATA_DEVS_PER_BUS; j++) {
- sata_identify (i, j);
- set_Feature_cmd (i, j);
- devno = i * CONFIG_SYS_SATA_DEVS_PER_BUS + j;
- if ((sata_dev_desc[devno].lba > 0) &&
- (sata_dev_desc[devno].blksz > 0)) {
- dev_print (&sata_dev_desc[devno]);
- /* initialize partition type */
- init_part (&sata_dev_desc[devno]);
- if (sata_curr_device < 0)
- sata_curr_device =
- i * CONFIG_SYS_SATA_DEVS_PER_BUS + j;
- }
- }
- }
- return 0;
-}
-
-static u8 __inline__
-sata_inb (unsigned long ioaddr)
-{
- return inb (ioaddr);
-}
-
-static void __inline__
-sata_outb (unsigned char val, unsigned long ioaddr)
-{
- outb (val, ioaddr);
-}
-
-static void
-output_data (struct sata_ioports *ioaddr, ulong * sect_buf, int words)
-{
- outsw (ioaddr->data_addr, sect_buf, words << 1);
-}
-
-static int
-input_data (struct sata_ioports *ioaddr, ulong * sect_buf, int words)
-{
- insw (ioaddr->data_addr, sect_buf, words << 1);
- return 0;
-}
-
-static void
-sata_cpy (unsigned char *dst, unsigned char *src, unsigned int len)
-{
- unsigned char *end, *last;
-
- last = dst;
- end = src + len - 1;
-
- /* reserve space for '\0' */
- if (len < 2)
- goto OUT;
-
- /* skip leading white space */
- while ((*src) && (src < end) && (*src == ' '))
- ++src;
-
- /* copy string, omitting trailing white space */
- while ((*src) && (src < end)) {
- *dst++ = *src;
- if (*src++ != ' ')
- last = dst;
- }
- OUT:
- *last = '\0';
-}
-
-int
-sata_bus_softreset (int num)
-{
- u8 dev = 0, status = 0, i;
-
- port[num].dev_mask = 0;
-
- for (i = 0; i < CONFIG_SYS_SATA_DEVS_PER_BUS; i++) {
- if (!(sata_devchk (&port[num].ioaddr, i))) {
- PRINTF ("dev_chk failed for dev#%d\n", i);
- } else {
- port[num].dev_mask |= (1 << i);
- PRINTF ("dev_chk passed for dev#%d\n", i);
- }
- }
-
- if (!(port[num].dev_mask)) {
- printf ("no devices on port%d\n", num);
- return 1;
- }
-
- dev_select (&port[num].ioaddr, dev);
-
- port[num].ctl_reg = 0x08; /*Default value of control reg */
- sata_outb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
- udelay (10);
- sata_outb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
- udelay (10);
- sata_outb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
-
- /* spec mandates ">= 2ms" before checking status.
- * We wait 150ms, because that was the magic delay used for
- * ATAPI devices in Hale Landis's ATADRVR, for the period of time
- * between when the ATA command register is written, and then
- * status is checked. Because waiting for "a while" before
- * checking status is fine, post SRST, we perform this magic
- * delay here as well.
- */
- msleep (150);
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 300);
- while ((status & ATA_BUSY)) {
- msleep (100);
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 3);
- }
-
- if (status & ATA_BUSY)
- printf ("ata%u is slow to respond,plz be patient\n", port);
-
- while ((status & ATA_BUSY)) {
- msleep (100);
- status = sata_chk_status (&port[num].ioaddr);
- }
-
- if (status & ATA_BUSY) {
- printf ("ata%u failed to respond : ", port);
- printf ("bus reset failed\n");
- return 1;
- }
- return 0;
-}
-
-void
-sata_identify (int num, int dev)
-{
- u8 cmd = 0, status = 0, devno = num * CONFIG_SYS_SATA_DEVS_PER_BUS + dev;
- u16 iobuf[ATA_SECT_SIZE];
- u64 n_sectors = 0;
- u8 mask = 0;
-
- memset (iobuf, 0, sizeof (iobuf));
- hd_driveid_t *iop = (hd_driveid_t *) iobuf;
-
- if (dev == 0)
- mask = 0x01;
- else
- mask = 0x02;
-
- if (!(port[num].dev_mask & mask)) {
- printf ("dev%d is not present on port#%d\n", dev, num);
- return;
- }
-
- printf ("port=%d dev=%d\n", num, dev);
-
- dev_select (&port[num].ioaddr, dev);
-
- status = 0;
- cmd = ATA_CMD_IDENT; /*Device Identify Command */
- sata_outb (cmd, port[num].ioaddr.command_addr);
- sata_inb (port[num].ioaddr.altstatus_addr);
- udelay (10);
-
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 1000);
- if (status & ATA_ERR) {
- printf ("\ndevice not responding\n");
- port[num].dev_mask &= ~mask;
- return;
- }
-
- input_data (&port[num].ioaddr, (ulong *) iobuf, ATA_SECTORWORDS);
-
- PRINTF ("\nata%u: dev %u cfg 49:%04x 82:%04x 83:%04x 84:%04x85:%04x"
- "86:%04x" "87:%04x 88:%04x\n", num, dev, iobuf[49],
- iobuf[82], iobuf[83], iobuf[84], iobuf[85], iobuf[86],
- iobuf[87], iobuf[88]);
-
- /* we require LBA and DMA support (bits 8 & 9 of word 49) */
- if (!ata_id_has_dma (iobuf) || !ata_id_has_lba (iobuf)) {
- PRINTF ("ata%u: no dma/lba\n", num);
- }
- ata_dump_id (iobuf);
-
- if (ata_id_has_lba48 (iobuf)) {
- n_sectors = ata_id_u64 (iobuf, 100);
- } else {
- n_sectors = ata_id_u32 (iobuf, 60);
- }
- PRINTF ("no. of sectors %u\n", ata_id_u64 (iobuf, 100));
- PRINTF ("no. of sectors %u\n", ata_id_u32 (iobuf, 60));
-
- if (n_sectors == 0) {
- port[num].dev_mask &= ~mask;
- return;
- }
-
- sata_cpy (sata_dev_desc[devno].revision, iop->fw_rev,
- sizeof (sata_dev_desc[devno].revision));
- sata_cpy (sata_dev_desc[devno].vendor, iop->model,
- sizeof (sata_dev_desc[devno].vendor));
- sata_cpy (sata_dev_desc[devno].product, iop->serial_no,
- sizeof (sata_dev_desc[devno].product));
- strswab (sata_dev_desc[devno].revision);
- strswab (sata_dev_desc[devno].vendor);
-
- if ((iop->config & 0x0080) == 0x0080) {
- sata_dev_desc[devno].removable = 1;
- } else {
- sata_dev_desc[devno].removable = 0;
- }
-
- sata_dev_desc[devno].lba = iop->lba_capacity;
- PRINTF ("lba=0x%x", sata_dev_desc[devno].lba);
-
-#ifdef CONFIG_LBA48
- if (iop->command_set_2 & 0x0400) {
- sata_dev_desc[devno].lba48 = 1;
- lba = (unsigned long long) iop->lba48_capacity[0] |
- ((unsigned long long) iop->lba48_capacity[1] << 16) |
- ((unsigned long long) iop->lba48_capacity[2] << 32) |
- ((unsigned long long) iop->lba48_capacity[3] << 48);
- } else {
- sata_dev_desc[devno].lba48 = 0;
- }
-#endif
-
- /* assuming HD */
- sata_dev_desc[devno].type = DEV_TYPE_HARDDISK;
- sata_dev_desc[devno].blksz = ATA_BLOCKSIZE;
- sata_dev_desc[devno].lun = 0; /* just to fill something in... */
-}
-
-void
-set_Feature_cmd (int num, int dev)
-{
- u8 mask = 0x00, status = 0;
-
- if (dev == 0)
- mask = 0x01;
- else
- mask = 0x02;
-
- if (!(port[num].dev_mask & mask)) {
- PRINTF ("dev%d is not present on port#%d\n", dev, num);
- return;
- }
-
- dev_select (&port[num].ioaddr, dev);
-
- sata_outb (SETFEATURES_XFER, port[num].ioaddr.feature_addr);
- sata_outb (XFER_PIO_4, port[num].ioaddr.nsect_addr);
- sata_outb (0, port[num].ioaddr.lbal_addr);
- sata_outb (0, port[num].ioaddr.lbam_addr);
- sata_outb (0, port[num].ioaddr.lbah_addr);
-
- sata_outb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
- sata_outb (ATA_CMD_SETF, port[num].ioaddr.command_addr);
-
- udelay (50);
- msleep (150);
-
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000);
- if ((status & (ATA_STAT_BUSY | ATA_STAT_ERR))) {
- printf ("Error : status 0x%02x\n", status);
- port[num].dev_mask &= ~mask;
- }
-}
-
-void
-sata_port (struct sata_ioports *ioport)
-{
- ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA;
- ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR;
- ioport->feature_addr = ioport->cmd_addr + ATA_REG_FEATURE;
- ioport->nsect_addr = ioport->cmd_addr + ATA_REG_NSECT;
- ioport->lbal_addr = ioport->cmd_addr + ATA_REG_LBAL;
- ioport->lbam_addr = ioport->cmd_addr + ATA_REG_LBAM;
- ioport->lbah_addr = ioport->cmd_addr + ATA_REG_LBAH;
- ioport->device_addr = ioport->cmd_addr + ATA_REG_DEVICE;
- ioport->status_addr = ioport->cmd_addr + ATA_REG_STATUS;
- ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD;
-}
-
-int
-sata_devchk (struct sata_ioports *ioaddr, int dev)
-{
- u8 nsect, lbal;
-
- dev_select (ioaddr, dev);
-
- sata_outb (0x55, ioaddr->nsect_addr);
- sata_outb (0xaa, ioaddr->lbal_addr);
-
- sata_outb (0xaa, ioaddr->nsect_addr);
- sata_outb (0x55, ioaddr->lbal_addr);
-
- sata_outb (0x55, ioaddr->nsect_addr);
- sata_outb (0xaa, ioaddr->lbal_addr);
-
- nsect = sata_inb (ioaddr->nsect_addr);
- lbal = sata_inb (ioaddr->lbal_addr);
-
- if ((nsect == 0x55) && (lbal == 0xaa))
- return 1; /* we found a device */
- else
- return 0; /* nothing found */
-}
-
-void
-dev_select (struct sata_ioports *ioaddr, int dev)
-{
- u8 tmp = 0;
-
- if (dev == 0)
- tmp = ATA_DEVICE_OBS;
- else
- tmp = ATA_DEVICE_OBS | ATA_DEV1;
-
- sata_outb (tmp, ioaddr->device_addr);
- sata_inb (ioaddr->altstatus_addr);
- udelay (5);
-}
-
-u8
-sata_busy_wait (struct sata_ioports *ioaddr, int bits, unsigned int max)
-{
- u8 status;
-
- do {
- udelay (1000);
- status = sata_chk_status (ioaddr);
- max--;
- } while ((status & bits) && (max > 0));
-
- return status;
-}
-
-u8
-sata_chk_status (struct sata_ioports * ioaddr)
-{
- return sata_inb (ioaddr->status_addr);
-}
-
-void
-msleep (int count)
-{
- int i;
-
- for (i = 0; i < count; i++)
- udelay (1000);
-}
-
-ulong
-sata_read (int device, ulong blknr,lbaint_t blkcnt, void * buff)
-{
- ulong n = 0, *buffer = (ulong *)buff;
- u8 dev = 0, num = 0, mask = 0, status = 0;
-
-#ifdef CONFIG_LBA48
- unsigned char lba48 = 0;
-
- if (blknr & 0x0000fffff0000000) {
- if (!sata_dev_desc[devno].lba48) {
- printf ("Drive doesn't support 48-bit addressing\n");
- return 0;
- }
- /* more than 28 bits used, use 48bit mode */
- lba48 = 1;
- }
-#endif
- /*Port Number */
- num = device / CONFIG_SYS_SATA_DEVS_PER_BUS;
- /*dev on the port */
- if (device >= CONFIG_SYS_SATA_DEVS_PER_BUS)
- dev = device - CONFIG_SYS_SATA_DEVS_PER_BUS;
- else
- dev = device;
-
- if (dev == 0)
- mask = 0x01;
- else
- mask = 0x02;
-
- if (!(port[num].dev_mask & mask)) {
- printf ("dev%d is not present on port#%d\n", dev, num);
- return 0;
- }
-
- /* Select device */
- dev_select (&port[num].ioaddr, dev);
-
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
- if (status & ATA_BUSY) {
- printf ("ata%u failed to respond\n", port[num].port_no);
- return n;
- }
- while (blkcnt-- > 0) {
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
- if (status & ATA_BUSY) {
- printf ("ata%u failed to respond\n", 0);
- return n;
- }
-#ifdef CONFIG_LBA48
- if (lba48) {
- /* write high bits */
- sata_outb (0, port[num].ioaddr.nsect_addr);
- sata_outb ((blknr >> 24) & 0xFF,
- port[num].ioaddr.lbal_addr);
- sata_outb ((blknr >> 32) & 0xFF,
- port[num].ioaddr.lbam_addr);
- sata_outb ((blknr >> 40) & 0xFF,
- port[num].ioaddr.lbah_addr);
- }
-#endif
- sata_outb (1, port[num].ioaddr.nsect_addr);
- sata_outb (((blknr) >> 0) & 0xFF,
- port[num].ioaddr.lbal_addr);
- sata_outb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
- sata_outb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
-
-#ifdef CONFIG_LBA48
- if (lba48) {
- sata_outb (ATA_LBA, port[num].ioaddr.device_addr);
- sata_outb (ATA_CMD_READ_EXT,
- port[num].ioaddr.command_addr);
- } else
-#endif
- {
- sata_outb (ATA_LBA | ((blknr >> 24) & 0xF),
- port[num].ioaddr.device_addr);
- sata_outb (ATA_CMD_READ,
- port[num].ioaddr.command_addr);
- }
-
- msleep (50);
- /*may take up to 4 sec */
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000);
-
- if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
- != ATA_STAT_DRQ) {
- u8 err = 0;
-
- printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
- device, (ulong) blknr, status);
- err = sata_inb (port[num].ioaddr.error_addr);
- printf ("Error reg = 0x%x\n", err);
- return (n);
- }
- input_data (&port[num].ioaddr, buffer, ATA_SECTORWORDS);
- sata_inb (port[num].ioaddr.altstatus_addr);
- udelay (50);
-
- ++n;
- ++blknr;
- buffer += ATA_SECTORWORDS;
- }
- return n;
-}
-
-ulong
-sata_write (int device, ulong blknr,lbaint_t blkcnt, void * buff)
-{
- ulong n = 0, *buffer = (ulong *)buff;
- unsigned char status = 0, num = 0, dev = 0, mask = 0;
-
-#ifdef CONFIG_LBA48
- unsigned char lba48 = 0;
-
- if (blknr & 0x0000fffff0000000) {
- if (!sata_dev_desc[devno].lba48) {
- printf ("Drive doesn't support 48-bit addressing\n");
- return 0;
- }
- /* more than 28 bits used, use 48bit mode */
- lba48 = 1;
- }
-#endif
- /*Port Number */
- num = device / CONFIG_SYS_SATA_DEVS_PER_BUS;
- /*dev on the Port */
- if (device >= CONFIG_SYS_SATA_DEVS_PER_BUS)
- dev = device - CONFIG_SYS_SATA_DEVS_PER_BUS;
- else
- dev = device;
-
- if (dev == 0)
- mask = 0x01;
- else
- mask = 0x02;
-
- /* Select device */
- dev_select (&port[num].ioaddr, dev);
-
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
- if (status & ATA_BUSY) {
- printf ("ata%u failed to respond\n", port[num].port_no);
- return n;
- }
-
- while (blkcnt-- > 0) {
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
- if (status & ATA_BUSY) {
- printf ("ata%u failed to respond\n",
- port[num].port_no);
- return n;
- }
-#ifdef CONFIG_LBA48
- if (lba48) {
- /* write high bits */
- sata_outb (0, port[num].ioaddr.nsect_addr);
- sata_outb ((blknr >> 24) & 0xFF,
- port[num].ioaddr.lbal_addr);
- sata_outb ((blknr >> 32) & 0xFF,
- port[num].ioaddr.lbam_addr);
- sata_outb ((blknr >> 40) & 0xFF,
- port[num].ioaddr.lbah_addr);
- }
-#endif
- sata_outb (1, port[num].ioaddr.nsect_addr);
- sata_outb ((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr);
- sata_outb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
- sata_outb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
-#ifdef CONFIG_LBA48
- if (lba48) {
- sata_outb (ATA_LBA, port[num].ioaddr.device_addr);
- sata_outb (ATA_CMD_WRITE_EXT,
- port[num].ioaddr.command_addr);
- } else
-#endif
- {
- sata_outb (ATA_LBA | ((blknr >> 24) & 0xF),
- port[num].ioaddr.device_addr);
- sata_outb (ATA_CMD_WRITE,
- port[num].ioaddr.command_addr);
- }
-
- msleep (50);
- /*may take up to 4 sec */
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000);
- if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
- != ATA_STAT_DRQ) {
- printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
- device, (ulong) blknr, status);
- return (n);
- }
-
- output_data (&port[num].ioaddr, buffer, ATA_SECTORWORDS);
- sata_inb (port[num].ioaddr.altstatus_addr);
- udelay (50);
-
- ++n;
- ++blknr;
- buffer += ATA_SECTORWORDS;
- }
- return n;
-}
-
-int scan_sata(int dev)
-{
- return 0;
-}
+++ /dev/null
-/*
- * sata_dwc.c
- *
- * Synopsys DesignWare Cores (DWC) SATA host driver
- *
- * Author: Mark Miesfeld <mmiesfeld@amcc.com>
- *
- * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
- * Copyright 2008 DENX Software Engineering
- *
- * Based on versions provided by AMCC and Synopsys which are:
- * Copyright 2006 Applied Micro Circuits Corporation
- * COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED
- *
- * This program is free software; you can redistribute
- * it and/or modify it under the terms of the GNU
- * General Public License as published by the
- * Free Software Foundation; either version 2 of the License,
- * or (at your option) any later version.
- *
- */
-/*
- * SATA support based on the chip canyonlands.
- *
- * 04-17-2009
- * The local version of this driver for the canyonlands board
- * does not use interrupts but polls the chip instead.
- */
-
-#include <common.h>
-#include <command.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/errno.h>
-#include <asm/io.h>
-#include <malloc.h>
-#include <ata.h>
-#include <linux/ctype.h>
-
-#include "sata_dwc.h"
-
-#define DMA_NUM_CHANS 1
-#define DMA_NUM_CHAN_REGS 8
-
-#define AHB_DMA_BRST_DFLT 16
-
-struct dmareg {
- u32 low;
- u32 high;
-};
-
-struct dma_chan_regs {
- struct dmareg sar;
- struct dmareg dar;
- struct dmareg llp;
- struct dmareg ctl;
- struct dmareg sstat;
- struct dmareg dstat;
- struct dmareg sstatar;
- struct dmareg dstatar;
- struct dmareg cfg;
- struct dmareg sgr;
- struct dmareg dsr;
-};
-
-struct dma_interrupt_regs {
- struct dmareg tfr;
- struct dmareg block;
- struct dmareg srctran;
- struct dmareg dsttran;
- struct dmareg error;
-};
-
-struct ahb_dma_regs {
- struct dma_chan_regs chan_regs[DMA_NUM_CHAN_REGS];
- struct dma_interrupt_regs interrupt_raw;
- struct dma_interrupt_regs interrupt_status;
- struct dma_interrupt_regs interrupt_mask;
- struct dma_interrupt_regs interrupt_clear;
- struct dmareg statusInt;
- struct dmareg rq_srcreg;
- struct dmareg rq_dstreg;
- struct dmareg rq_sgl_srcreg;
- struct dmareg rq_sgl_dstreg;
- struct dmareg rq_lst_srcreg;
- struct dmareg rq_lst_dstreg;
- struct dmareg dma_cfg;
- struct dmareg dma_chan_en;
- struct dmareg dma_id;
- struct dmareg dma_test;
- struct dmareg res1;
- struct dmareg res2;
- /* DMA Comp Params
- * Param 6 = dma_param[0], Param 5 = dma_param[1],
- * Param 4 = dma_param[2] ...
- */
- struct dmareg dma_params[6];
-};
-
-#define DMA_EN 0x00000001
-#define DMA_DI 0x00000000
-#define DMA_CHANNEL(ch) (0x00000001 << (ch))
-#define DMA_ENABLE_CHAN(ch) ((0x00000001 << (ch)) | \
- ((0x000000001 << (ch)) << 8))
-#define DMA_DISABLE_CHAN(ch) (0x00000000 | \
- ((0x000000001 << (ch)) << 8))
-
-#define SATA_DWC_MAX_PORTS 1
-#define SATA_DWC_SCR_OFFSET 0x24
-#define SATA_DWC_REG_OFFSET 0x64
-
-struct sata_dwc_regs {
- u32 fptagr;
- u32 fpbor;
- u32 fptcr;
- u32 dmacr;
- u32 dbtsr;
- u32 intpr;
- u32 intmr;
- u32 errmr;
- u32 llcr;
- u32 phycr;
- u32 physr;
- u32 rxbistpd;
- u32 rxbistpd1;
- u32 rxbistpd2;
- u32 txbistpd;
- u32 txbistpd1;
- u32 txbistpd2;
- u32 bistcr;
- u32 bistfctr;
- u32 bistsr;
- u32 bistdecr;
- u32 res[15];
- u32 testr;
- u32 versionr;
- u32 idr;
- u32 unimpl[192];
- u32 dmadr[256];
-};
-
-#define SATA_DWC_TXFIFO_DEPTH 0x01FF
-#define SATA_DWC_RXFIFO_DEPTH 0x01FF
-
-#define SATA_DWC_DBTSR_MWR(size) ((size / 4) & SATA_DWC_TXFIFO_DEPTH)
-#define SATA_DWC_DBTSR_MRD(size) (((size / 4) & \
- SATA_DWC_RXFIFO_DEPTH) << 16)
-#define SATA_DWC_INTPR_DMAT 0x00000001
-#define SATA_DWC_INTPR_NEWFP 0x00000002
-#define SATA_DWC_INTPR_PMABRT 0x00000004
-#define SATA_DWC_INTPR_ERR 0x00000008
-#define SATA_DWC_INTPR_NEWBIST 0x00000010
-#define SATA_DWC_INTPR_IPF 0x10000000
-#define SATA_DWC_INTMR_DMATM 0x00000001
-#define SATA_DWC_INTMR_NEWFPM 0x00000002
-#define SATA_DWC_INTMR_PMABRTM 0x00000004
-#define SATA_DWC_INTMR_ERRM 0x00000008
-#define SATA_DWC_INTMR_NEWBISTM 0x00000010
-
-#define SATA_DWC_DMACR_TMOD_TXCHEN 0x00000004
-#define SATA_DWC_DMACR_TXRXCH_CLEAR SATA_DWC_DMACR_TMOD_TXCHEN
-
-#define SATA_DWC_QCMD_MAX 32
-
-#define SATA_DWC_SERROR_ERR_BITS 0x0FFF0F03
-
-#define HSDEVP_FROM_AP(ap) (struct sata_dwc_device_port*) \
- (ap)->private_data
-
-struct sata_dwc_device {
- struct device *dev;
- struct ata_probe_ent *pe;
- struct ata_host *host;
- u8 *reg_base;
- struct sata_dwc_regs *sata_dwc_regs;
- int irq_dma;
-};
-
-struct sata_dwc_device_port {
- struct sata_dwc_device *hsdev;
- int cmd_issued[SATA_DWC_QCMD_MAX];
- u32 dma_chan[SATA_DWC_QCMD_MAX];
- int dma_pending[SATA_DWC_QCMD_MAX];
-};
-
-enum {
- SATA_DWC_CMD_ISSUED_NOT = 0,
- SATA_DWC_CMD_ISSUED_PEND = 1,
- SATA_DWC_CMD_ISSUED_EXEC = 2,
- SATA_DWC_CMD_ISSUED_NODATA = 3,
-
- SATA_DWC_DMA_PENDING_NONE = 0,
- SATA_DWC_DMA_PENDING_TX = 1,
- SATA_DWC_DMA_PENDING_RX = 2,
-};
-
-#define msleep(a) udelay(a * 1000)
-#define ssleep(a) msleep(a * 1000)
-
-static int ata_probe_timeout = (ATA_TMOUT_INTERNAL / 100);
-
-enum sata_dev_state {
- SATA_INIT = 0,
- SATA_READY = 1,
- SATA_NODEVICE = 2,
- SATA_ERROR = 3,
-};
-enum sata_dev_state dev_state = SATA_INIT;
-
-static struct ahb_dma_regs *sata_dma_regs = 0;
-static struct ata_host *phost;
-static struct ata_port ap;
-static struct ata_port *pap = ≈
-static struct ata_device ata_device;
-static struct sata_dwc_device_port dwc_devp;
-
-static void *scr_addr_sstatus;
-static u32 temp_n_block = 0;
-
-static unsigned ata_exec_internal(struct ata_device *dev,
- struct ata_taskfile *tf, const u8 *cdb,
- int dma_dir, unsigned int buflen,
- unsigned long timeout);
-static unsigned int ata_dev_set_feature(struct ata_device *dev,
- u8 enable,u8 feature);
-static unsigned int ata_dev_init_params(struct ata_device *dev,
- u16 heads, u16 sectors);
-static u8 ata_irq_on(struct ata_port *ap);
-static struct ata_queued_cmd *__ata_qc_from_tag(struct ata_port *ap,
- unsigned int tag);
-static int ata_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
- u8 status, int in_wq);
-static void ata_tf_to_host(struct ata_port *ap,
- const struct ata_taskfile *tf);
-static void ata_exec_command(struct ata_port *ap,
- const struct ata_taskfile *tf);
-static unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc);
-static u8 ata_check_altstatus(struct ata_port *ap);
-static u8 ata_check_status(struct ata_port *ap);
-static void ata_dev_select(struct ata_port *ap, unsigned int device,
- unsigned int wait, unsigned int can_sleep);
-static void ata_qc_issue(struct ata_queued_cmd *qc);
-static void ata_tf_load(struct ata_port *ap,
- const struct ata_taskfile *tf);
-static int ata_dev_read_sectors(unsigned char* pdata,
- unsigned long datalen, u32 block, u32 n_block);
-static int ata_dev_write_sectors(unsigned char* pdata,
- unsigned long datalen , u32 block, u32 n_block);
-static void ata_std_dev_select(struct ata_port *ap, unsigned int device);
-static void ata_qc_complete(struct ata_queued_cmd *qc);
-static void __ata_qc_complete(struct ata_queued_cmd *qc);
-static void fill_result_tf(struct ata_queued_cmd *qc);
-static void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
-static void ata_mmio_data_xfer(struct ata_device *dev,
- unsigned char *buf,
- unsigned int buflen,int do_write);
-static void ata_pio_task(struct ata_port *arg_ap);
-static void __ata_port_freeze(struct ata_port *ap);
-static int ata_port_freeze(struct ata_port *ap);
-static void ata_qc_free(struct ata_queued_cmd *qc);
-static void ata_pio_sectors(struct ata_queued_cmd *qc);
-static void ata_pio_sector(struct ata_queued_cmd *qc);
-static void ata_pio_queue_task(struct ata_port *ap,
- void *data,unsigned long delay);
-static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq);
-static int sata_dwc_softreset(struct ata_port *ap);
-static int ata_dev_read_id(struct ata_device *dev, unsigned int *p_class,
- unsigned int flags, u16 *id);
-static int check_sata_dev_state(void);
-
-extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
-
-static const struct ata_port_info sata_dwc_port_info[] = {
- {
- .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
- ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING |
- ATA_FLAG_SRST | ATA_FLAG_NCQ,
- .pio_mask = 0x1f,
- .mwdma_mask = 0x07,
- .udma_mask = 0x7f,
- },
-};
-
-int init_sata(int dev)
-{
- struct sata_dwc_device hsdev;
- struct ata_host host;
- struct ata_port_info pi = sata_dwc_port_info[0];
- struct ata_link *link;
- struct sata_dwc_device_port hsdevp = dwc_devp;
- u8 *base = 0;
- u8 *sata_dma_regs_addr = 0;
- u8 status;
- unsigned long base_addr = 0;
- int chan = 0;
- int rc;
- int i;
-
- phost = &host;
-
- base = (u8*)SATA_BASE_ADDR;
-
- hsdev.sata_dwc_regs = (void *__iomem)(base + SATA_DWC_REG_OFFSET);
-
- host.n_ports = SATA_DWC_MAX_PORTS;
-
- for (i = 0; i < SATA_DWC_MAX_PORTS; i++) {
- ap.pflags |= ATA_PFLAG_INITIALIZING;
- ap.flags = ATA_FLAG_DISABLED;
- ap.print_id = -1;
- ap.ctl = ATA_DEVCTL_OBS;
- ap.host = &host;
- ap.last_ctl = 0xFF;
-
- link = &ap.link;
- link->ap = ≈
- link->pmp = 0;
- link->active_tag = ATA_TAG_POISON;
- link->hw_sata_spd_limit = 0;
-
- ap.port_no = i;
- host.ports[i] = ≈
- }
-
- ap.pio_mask = pi.pio_mask;
- ap.mwdma_mask = pi.mwdma_mask;
- ap.udma_mask = pi.udma_mask;
- ap.flags |= pi.flags;
- ap.link.flags |= pi.link_flags;
-
- host.ports[0]->ioaddr.cmd_addr = base;
- host.ports[0]->ioaddr.scr_addr = base + SATA_DWC_SCR_OFFSET;
- scr_addr_sstatus = base + SATA_DWC_SCR_OFFSET;
-
- base_addr = (unsigned long)base;
-
- host.ports[0]->ioaddr.cmd_addr = (void *)base_addr + 0x00;
- host.ports[0]->ioaddr.data_addr = (void *)base_addr + 0x00;
-
- host.ports[0]->ioaddr.error_addr = (void *)base_addr + 0x04;
- host.ports[0]->ioaddr.feature_addr = (void *)base_addr + 0x04;
-
- host.ports[0]->ioaddr.nsect_addr = (void *)base_addr + 0x08;
-
- host.ports[0]->ioaddr.lbal_addr = (void *)base_addr + 0x0c;
- host.ports[0]->ioaddr.lbam_addr = (void *)base_addr + 0x10;
- host.ports[0]->ioaddr.lbah_addr = (void *)base_addr + 0x14;
-
- host.ports[0]->ioaddr.device_addr = (void *)base_addr + 0x18;
- host.ports[0]->ioaddr.command_addr = (void *)base_addr + 0x1c;
- host.ports[0]->ioaddr.status_addr = (void *)base_addr + 0x1c;
-
- host.ports[0]->ioaddr.altstatus_addr = (void *)base_addr + 0x20;
- host.ports[0]->ioaddr.ctl_addr = (void *)base_addr + 0x20;
-
- sata_dma_regs_addr = (u8*)SATA_DMA_REG_ADDR;
- sata_dma_regs = (void *__iomem)sata_dma_regs_addr;
-
- status = ata_check_altstatus(&ap);
-
- if (status == 0x7f) {
- printf("Hard Disk not found.\n");
- dev_state = SATA_NODEVICE;
- rc = FALSE;
- return rc;
- }
-
- printf("Waiting for device...");
- i = 0;
- while (1) {
- udelay(10000);
-
- status = ata_check_altstatus(&ap);
-
- if ((status & ATA_BUSY) == 0) {
- printf("\n");
- break;
- }
-
- i++;
- if (i > (ATA_RESET_TIME * 100)) {
- printf("** TimeOUT **\n");
-
- dev_state = SATA_NODEVICE;
- rc = FALSE;
- return rc;
- }
- if ((i >= 100) && ((i % 100) == 0))
- printf(".");
- }
-
- rc = sata_dwc_softreset(&ap);
-
- if (rc) {
- printf("sata_dwc : error. soft reset failed\n");
- return rc;
- }
-
- for (chan = 0; chan < DMA_NUM_CHANS; chan++) {
- out_le32(&(sata_dma_regs->interrupt_mask.error.low),
- DMA_DISABLE_CHAN(chan));
-
- out_le32(&(sata_dma_regs->interrupt_mask.tfr.low),
- DMA_DISABLE_CHAN(chan));
- }
-
- out_le32(&(sata_dma_regs->dma_cfg.low), DMA_DI);
-
- out_le32(&hsdev.sata_dwc_regs->intmr,
- SATA_DWC_INTMR_ERRM |
- SATA_DWC_INTMR_PMABRTM);
-
- /* Unmask the error bits that should trigger
- * an error interrupt by setting the error mask register.
- */
- out_le32(&hsdev.sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS);
-
- hsdev.host = ap.host;
- memset(&hsdevp, 0, sizeof(hsdevp));
- hsdevp.hsdev = &hsdev;
-
- for (i = 0; i < SATA_DWC_QCMD_MAX; i++)
- hsdevp.cmd_issued[i] = SATA_DWC_CMD_ISSUED_NOT;
-
- out_le32((void __iomem *)scr_addr_sstatus + 4,
- in_le32((void __iomem *)scr_addr_sstatus + 4));
-
- rc = 0;
- return rc;
-}
-
-static u8 ata_check_altstatus(struct ata_port *ap)
-{
- u8 val = 0;
- val = readb(ap->ioaddr.altstatus_addr);
- return val;
-}
-
-static int sata_dwc_softreset(struct ata_port *ap)
-{
- u8 nsect,lbal = 0;
- u8 tmp = 0;
- u32 serror = 0;
- u8 status = 0;
- struct ata_ioports *ioaddr = &ap->ioaddr;
-
- serror = in_le32((void *)ap->ioaddr.scr_addr + (SCR_ERROR * 4));
-
- writeb(0x55, ioaddr->nsect_addr);
- writeb(0xaa, ioaddr->lbal_addr);
- writeb(0xaa, ioaddr->nsect_addr);
- writeb(0x55, ioaddr->lbal_addr);
- writeb(0x55, ioaddr->nsect_addr);
- writeb(0xaa, ioaddr->lbal_addr);
-
- nsect = readb(ioaddr->nsect_addr);
- lbal = readb(ioaddr->lbal_addr);
-
- if ((nsect == 0x55) && (lbal == 0xaa)) {
- printf("Device found\n");
- } else {
- printf("No device found\n");
- dev_state = SATA_NODEVICE;
- return FALSE;
- }
-
- tmp = ATA_DEVICE_OBS;
- writeb(tmp, ioaddr->device_addr);
- writeb(ap->ctl, ioaddr->ctl_addr);
-
- udelay(200);
-
- writeb(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
-
- udelay(200);
- writeb(ap->ctl, ioaddr->ctl_addr);
-
- msleep(150);
- status = ata_check_status(ap);
-
- msleep(50);
- ata_check_status(ap);
-
- while (1) {
- u8 status = ata_check_status(ap);
-
- if (!(status & ATA_BUSY))
- break;
-
- printf("Hard Disk status is BUSY.\n");
- msleep(50);
- }
-
- tmp = ATA_DEVICE_OBS;
- writeb(tmp, ioaddr->device_addr);
-
- nsect = readb(ioaddr->nsect_addr);
- lbal = readb(ioaddr->lbal_addr);
-
- return 0;
-}
-
-static u8 ata_check_status(struct ata_port *ap)
-{
- u8 val = 0;
- val = readb(ap->ioaddr.status_addr);
- return val;
-}
-
-static int ata_id_has_hipm(const u16 *id)
-{
- u16 val = id[76];
-
- if (val == 0 || val == 0xffff)
- return -1;
-
- return val & (1 << 9);
-}
-
-static int ata_id_has_dipm(const u16 *id)
-{
- u16 val = id[78];
-
- if (val == 0 || val == 0xffff)
- return -1;
-
- return val & (1 << 3);
-}
-
-int scan_sata(int dev)
-{
- int i;
- int rc;
- u8 status;
- const u16 *id;
- struct ata_device *ata_dev = &ata_device;
- unsigned long pio_mask, mwdma_mask, udma_mask;
- unsigned long xfer_mask;
- char revbuf[7];
- u16 iobuf[ATA_SECTOR_WORDS];
-
- memset(iobuf, 0, sizeof(iobuf));
-
- if (dev_state == SATA_NODEVICE)
- return 1;
-
- printf("Waiting for device...");
- i = 0;
- while (1) {
- udelay(10000);
-
- status = ata_check_altstatus(&ap);
-
- if ((status & ATA_BUSY) == 0) {
- printf("\n");
- break;
- }
-
- i++;
- if (i > (ATA_RESET_TIME * 100)) {
- printf("** TimeOUT **\n");
-
- dev_state = SATA_NODEVICE;
- return 1;
- }
- if ((i >= 100) && ((i % 100) == 0))
- printf(".");
- }
-
- udelay(1000);
-
- rc = ata_dev_read_id(ata_dev, &ata_dev->class,
- ATA_READID_POSTRESET,ata_dev->id);
- if (rc) {
- printf("sata_dwc : error. failed sata scan\n");
- return 1;
- }
-
- /* SATA drives indicate we have a bridge. We don't know which
- * end of the link the bridge is which is a problem
- */
- if (ata_id_is_sata(ata_dev->id))
- ap.cbl = ATA_CBL_SATA;
-
- id = ata_dev->id;
-
- ata_dev->flags &= ~ATA_DFLAG_CFG_MASK;
- ata_dev->max_sectors = 0;
- ata_dev->cdb_len = 0;
- ata_dev->n_sectors = 0;
- ata_dev->cylinders = 0;
- ata_dev->heads = 0;
- ata_dev->sectors = 0;
-
- if (id[ATA_ID_FIELD_VALID] & (1 << 1)) {
- pio_mask = id[ATA_ID_PIO_MODES] & 0x03;
- pio_mask <<= 3;
- pio_mask |= 0x7;
- } else {
- /* If word 64 isn't valid then Word 51 high byte holds
- * the PIO timing number for the maximum. Turn it into
- * a mask.
- */
- u8 mode = (id[ATA_ID_OLD_PIO_MODES] >> 8) & 0xFF;
- if (mode < 5) {
- pio_mask = (2 << mode) - 1;
- } else {
- pio_mask = 1;
- }
- }
-
- mwdma_mask = id[ATA_ID_MWDMA_MODES] & 0x07;
-
- if (ata_id_is_cfa(id)) {
- int pio = id[163] & 0x7;
- int dma = (id[163] >> 3) & 7;
-
- if (pio)
- pio_mask |= (1 << 5);
- if (pio > 1)
- pio_mask |= (1 << 6);
- if (dma)
- mwdma_mask |= (1 << 3);
- if (dma > 1)
- mwdma_mask |= (1 << 4);
- }
-
- udma_mask = 0;
- if (id[ATA_ID_FIELD_VALID] & (1 << 2))
- udma_mask = id[ATA_ID_UDMA_MODES] & 0xff;
-
- xfer_mask = ((pio_mask << ATA_SHIFT_PIO) & ATA_MASK_PIO) |
- ((mwdma_mask << ATA_SHIFT_MWDMA) & ATA_MASK_MWDMA) |
- ((udma_mask << ATA_SHIFT_UDMA) & ATA_MASK_UDMA);
-
- if (ata_dev->class == ATA_DEV_ATA) {
- if (ata_id_is_cfa(id)) {
- if (id[162] & 1)
- printf("supports DRM functions and may "
- "not be fully accessable.\n");
- sprintf(revbuf, "%s", "CFA");
- } else {
- if (ata_id_has_tpm(id))
- printf("supports DRM functions and may "
- "not be fully accessable.\n");
- }
-
- ata_dev->n_sectors = ata_id_n_sectors((u16*)id);
-
- if (ata_dev->id[59] & 0x100)
- ata_dev->multi_count = ata_dev->id[59] & 0xff;
-
- if (ata_id_has_lba(id)) {
- const char *lba_desc;
- char ncq_desc[20];
-
- lba_desc = "LBA";
- ata_dev->flags |= ATA_DFLAG_LBA;
- if (ata_id_has_lba48(id)) {
- ata_dev->flags |= ATA_DFLAG_LBA48;
- lba_desc = "LBA48";
-
- if (ata_dev->n_sectors >= (1UL << 28) &&
- ata_id_has_flush_ext(id))
- ata_dev->flags |= ATA_DFLAG_FLUSH_EXT;
- }
- if (!ata_id_has_ncq(ata_dev->id))
- ncq_desc[0] = '\0';
-
- if (ata_dev->horkage & ATA_HORKAGE_NONCQ)
- sprintf(ncq_desc, "%s", "NCQ (not used)");
-
- if (ap.flags & ATA_FLAG_NCQ)
- ata_dev->flags |= ATA_DFLAG_NCQ;
- }
- ata_dev->cdb_len = 16;
- }
- ata_dev->max_sectors = ATA_MAX_SECTORS;
- if (ata_dev->flags & ATA_DFLAG_LBA48)
- ata_dev->max_sectors = ATA_MAX_SECTORS_LBA48;
-
- if (!(ata_dev->horkage & ATA_HORKAGE_IPM)) {
- if (ata_id_has_hipm(ata_dev->id))
- ata_dev->flags |= ATA_DFLAG_HIPM;
- if (ata_id_has_dipm(ata_dev->id))
- ata_dev->flags |= ATA_DFLAG_DIPM;
- }
-
- if ((ap.cbl == ATA_CBL_SATA) && (!ata_id_is_sata(ata_dev->id))) {
- ata_dev->udma_mask &= ATA_UDMA5;
- ata_dev->max_sectors = ATA_MAX_SECTORS;
- }
-
- if (ata_dev->horkage & ATA_HORKAGE_DIAGNOSTIC) {
- printf("Drive reports diagnostics failure."
- "This may indicate a drive\n");
- printf("fault or invalid emulation."
- "Contact drive vendor for information.\n");
- }
-
- rc = check_sata_dev_state();
-
- ata_id_c_string(ata_dev->id,
- (unsigned char *)sata_dev_desc[dev].revision,
- ATA_ID_FW_REV, sizeof(sata_dev_desc[dev].revision));
- ata_id_c_string(ata_dev->id,
- (unsigned char *)sata_dev_desc[dev].vendor,
- ATA_ID_PROD, sizeof(sata_dev_desc[dev].vendor));
- ata_id_c_string(ata_dev->id,
- (unsigned char *)sata_dev_desc[dev].product,
- ATA_ID_SERNO, sizeof(sata_dev_desc[dev].product));
-
- sata_dev_desc[dev].lba = (u32) ata_dev->n_sectors;
-
-#ifdef CONFIG_LBA48
- if (ata_dev->id[83] & (1 << 10)) {
- sata_dev_desc[dev].lba48 = 1;
- } else {
- sata_dev_desc[dev].lba48 = 0;
- }
-#endif
-
- return 0;
-}
-
-static u8 ata_busy_wait(struct ata_port *ap,
- unsigned int bits,unsigned int max)
-{
- u8 status;
-
- do {
- udelay(10);
- status = ata_check_status(ap);
- max--;
- } while (status != 0xff && (status & bits) && (max > 0));
-
- return status;
-}
-
-static int ata_dev_read_id(struct ata_device *dev, unsigned int *p_class,
- unsigned int flags, u16 *id)
-{
- struct ata_port *ap = pap;
- unsigned int class = *p_class;
- struct ata_taskfile tf;
- unsigned int err_mask = 0;
- const char *reason;
- int may_fallback = 1, tried_spinup = 0;
- u8 status;
- int rc;
-
- status = ata_busy_wait(ap, ATA_BUSY, 30000);
- if (status & ATA_BUSY) {
- printf("BSY = 0 check. timeout.\n");
- rc = FALSE;
- return rc;
- }
-
- ata_dev_select(ap, dev->devno, 1, 1);
-
-retry:
- memset(&tf, 0, sizeof(tf));
- ap->print_id = 1;
- ap->flags &= ~ATA_FLAG_DISABLED;
- tf.ctl = ap->ctl;
- tf.device = ATA_DEVICE_OBS;
- tf.command = ATA_CMD_ID_ATA;
- tf.protocol = ATA_PROT_PIO;
-
- /* Some devices choke if TF registers contain garbage. Make
- * sure those are properly initialized.
- */
- tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
-
- /* Device presence detection is unreliable on some
- * controllers. Always poll IDENTIFY if available.
- */
- tf.flags |= ATA_TFLAG_POLLING;
-
- temp_n_block = 1;
-
- err_mask = ata_exec_internal(dev, &tf, NULL, DMA_FROM_DEVICE,
- sizeof(id[0]) * ATA_ID_WORDS, 0);
-
- if (err_mask) {
- if (err_mask & AC_ERR_NODEV_HINT) {
- printf("NODEV after polling detection\n");
- return -ENOENT;
- }
-
- if ((err_mask == AC_ERR_DEV) && (tf.feature & ATA_ABORTED)) {
- /* Device or controller might have reported
- * the wrong device class. Give a shot at the
- * other IDENTIFY if the current one is
- * aborted by the device.
- */
- if (may_fallback) {
- may_fallback = 0;
-
- if (class == ATA_DEV_ATA) {
- class = ATA_DEV_ATAPI;
- } else {
- class = ATA_DEV_ATA;
- }
- goto retry;
- }
- /* Control reaches here iff the device aborted
- * both flavors of IDENTIFYs which happens
- * sometimes with phantom devices.
- */
- printf("both IDENTIFYs aborted, assuming NODEV\n");
- return -ENOENT;
- }
- rc = -EIO;
- reason = "I/O error";
- goto err_out;
- }
-
- /* Falling back doesn't make sense if ID data was read
- * successfully at least once.
- */
- may_fallback = 0;
-
- unsigned int id_cnt;
-
- for (id_cnt = 0; id_cnt < ATA_ID_WORDS; id_cnt++)
- id[id_cnt] = le16_to_cpu(id[id_cnt]);
-
-
- rc = -EINVAL;
- reason = "device reports invalid type";
-
- if (class == ATA_DEV_ATA) {
- if (!ata_id_is_ata(id) && !ata_id_is_cfa(id))
- goto err_out;
- } else {
- if (ata_id_is_ata(id))
- goto err_out;
- }
- if (!tried_spinup && (id[2] == 0x37c8 || id[2] == 0x738c)) {
- tried_spinup = 1;
- /*
- * Drive powered-up in standby mode, and requires a specific
- * SET_FEATURES spin-up subcommand before it will accept
- * anything other than the original IDENTIFY command.
- */
- err_mask = ata_dev_set_feature(dev, SETFEATURES_SPINUP, 0);
- if (err_mask && id[2] != 0x738c) {
- rc = -EIO;
- reason = "SPINUP failed";
- goto err_out;
- }
- /*
- * If the drive initially returned incomplete IDENTIFY info,
- * we now must reissue the IDENTIFY command.
- */
- if (id[2] == 0x37c8)
- goto retry;
- }
-
- if ((flags & ATA_READID_POSTRESET) && class == ATA_DEV_ATA) {
- /*
- * The exact sequence expected by certain pre-ATA4 drives is:
- * SRST RESET
- * IDENTIFY (optional in early ATA)
- * INITIALIZE DEVICE PARAMETERS (later IDE and ATA)
- * anything else..
- * Some drives were very specific about that exact sequence.
- *
- * Note that ATA4 says lba is mandatory so the second check
- * shoud never trigger.
- */
- if (ata_id_major_version(id) < 4 || !ata_id_has_lba(id)) {
- err_mask = ata_dev_init_params(dev, id[3], id[6]);
- if (err_mask) {
- rc = -EIO;
- reason = "INIT_DEV_PARAMS failed";
- goto err_out;
- }
-
- /* current CHS translation info (id[53-58]) might be
- * changed. reread the identify device info.
- */
- flags &= ~ATA_READID_POSTRESET;
- goto retry;
- }
- }
-
- *p_class = class;
- return 0;
-
-err_out:
- return rc;
-}
-
-static u8 ata_wait_idle(struct ata_port *ap)
-{
- u8 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
- return status;
-}
-
-static void ata_dev_select(struct ata_port *ap, unsigned int device,
- unsigned int wait, unsigned int can_sleep)
-{
- if (wait)
- ata_wait_idle(ap);
-
- ata_std_dev_select(ap, device);
-
- if (wait)
- ata_wait_idle(ap);
-}
-
-static void ata_std_dev_select(struct ata_port *ap, unsigned int device)
-{
- u8 tmp;
-
- if (device == 0) {
- tmp = ATA_DEVICE_OBS;
- } else {
- tmp = ATA_DEVICE_OBS | ATA_DEV1;
- }
-
- writeb(tmp, ap->ioaddr.device_addr);
-
- readb(ap->ioaddr.altstatus_addr);
-
- udelay(1);
-}
-
-static int waiting_for_reg_state(volatile u8 *offset,
- int timeout_msec,
- u32 sign)
-{
- int i;
- u32 status;
-
- for (i = 0; i < timeout_msec; i++) {
- status = readl(offset);
- if ((status & sign) != 0)
- break;
- msleep(1);
- }
-
- return (i < timeout_msec) ? 0 : -1;
-}
-
-static void ata_qc_reinit(struct ata_queued_cmd *qc)
-{
- qc->dma_dir = DMA_NONE;
- qc->flags = 0;
- qc->nbytes = qc->extrabytes = qc->curbytes = 0;
- qc->n_elem = 0;
- qc->err_mask = 0;
- qc->sect_size = ATA_SECT_SIZE;
- qc->nbytes = ATA_SECT_SIZE * temp_n_block;
-
- memset(&qc->tf, 0, sizeof(qc->tf));
- qc->tf.ctl = 0;
- qc->tf.device = ATA_DEVICE_OBS;
-
- qc->result_tf.command = ATA_DRDY;
- qc->result_tf.feature = 0;
-}
-
-struct ata_queued_cmd *__ata_qc_from_tag(struct ata_port *ap,
- unsigned int tag)
-{
- if (tag < ATA_MAX_QUEUE)
- return &ap->qcmd[tag];
- return NULL;
-}
-
-static void __ata_port_freeze(struct ata_port *ap)
-{
- printf("set port freeze.\n");
- ap->pflags |= ATA_PFLAG_FROZEN;
-}
-
-static int ata_port_freeze(struct ata_port *ap)
-{
- __ata_port_freeze(ap);
- return 0;
-}
-
-unsigned ata_exec_internal(struct ata_device *dev,
- struct ata_taskfile *tf, const u8 *cdb,
- int dma_dir, unsigned int buflen,
- unsigned long timeout)
-{
- struct ata_link *link = dev->link;
- struct ata_port *ap = pap;
- struct ata_queued_cmd *qc;
- unsigned int tag, preempted_tag;
- u32 preempted_sactive, preempted_qc_active;
- int preempted_nr_active_links;
- unsigned int err_mask;
- int rc = 0;
- u8 status;
-
- status = ata_busy_wait(ap, ATA_BUSY, 300000);
- if (status & ATA_BUSY) {
- printf("BSY = 0 check. timeout.\n");
- rc = FALSE;
- return rc;
- }
-
- if (ap->pflags & ATA_PFLAG_FROZEN)
- return AC_ERR_SYSTEM;
-
- tag = ATA_TAG_INTERNAL;
-
- if (test_and_set_bit(tag, &ap->qc_allocated)) {
- rc = FALSE;
- return rc;
- }
-
- qc = __ata_qc_from_tag(ap, tag);
- qc->tag = tag;
- qc->ap = ap;
- qc->dev = dev;
-
- ata_qc_reinit(qc);
-
- preempted_tag = link->active_tag;
- preempted_sactive = link->sactive;
- preempted_qc_active = ap->qc_active;
- preempted_nr_active_links = ap->nr_active_links;
- link->active_tag = ATA_TAG_POISON;
- link->sactive = 0;
- ap->qc_active = 0;
- ap->nr_active_links = 0;
-
- qc->tf = *tf;
- if (cdb)
- memcpy(qc->cdb, cdb, ATAPI_CDB_LEN);
- qc->flags |= ATA_QCFLAG_RESULT_TF;
- qc->dma_dir = dma_dir;
- qc->private_data = 0;
-
- ata_qc_issue(qc);
-
- if (!timeout)
- timeout = ata_probe_timeout * 1000 / HZ;
-
- status = ata_busy_wait(ap, ATA_BUSY, 30000);
- if (status & ATA_BUSY) {
- printf("BSY = 0 check. timeout.\n");
- printf("altstatus = 0x%x.\n", status);
- qc->err_mask |= AC_ERR_OTHER;
- return qc->err_mask;
- }
-
- if (waiting_for_reg_state(ap->ioaddr.altstatus_addr, 1000, 0x8)) {
- u8 status = 0;
- u8 errorStatus = 0;
-
- status = readb(ap->ioaddr.altstatus_addr);
- if ((status & 0x01) != 0) {
- errorStatus = readb(ap->ioaddr.feature_addr);
- if (errorStatus == 0x04 &&
- qc->tf.command == ATA_CMD_PIO_READ_EXT){
- printf("Hard Disk doesn't support LBA48\n");
- dev_state = SATA_ERROR;
- qc->err_mask |= AC_ERR_OTHER;
- return qc->err_mask;
- }
- }
- qc->err_mask |= AC_ERR_OTHER;
- return qc->err_mask;
- }
-
- status = ata_busy_wait(ap, ATA_BUSY, 10);
- if (status & ATA_BUSY) {
- printf("BSY = 0 check. timeout.\n");
- qc->err_mask |= AC_ERR_OTHER;
- return qc->err_mask;
- }
-
- ata_pio_task(ap);
-
- if (!rc) {
- if (qc->flags & ATA_QCFLAG_ACTIVE) {
- qc->err_mask |= AC_ERR_TIMEOUT;
- ata_port_freeze(ap);
- }
- }
-
- if (qc->flags & ATA_QCFLAG_FAILED) {
- if (qc->result_tf.command & (ATA_ERR | ATA_DF))
- qc->err_mask |= AC_ERR_DEV;
-
- if (!qc->err_mask)
- qc->err_mask |= AC_ERR_OTHER;
-
- if (qc->err_mask & ~AC_ERR_OTHER)
- qc->err_mask &= ~AC_ERR_OTHER;
- }
-
- *tf = qc->result_tf;
- err_mask = qc->err_mask;
- ata_qc_free(qc);
- link->active_tag = preempted_tag;
- link->sactive = preempted_sactive;
- ap->qc_active = preempted_qc_active;
- ap->nr_active_links = preempted_nr_active_links;
-
- if (ap->flags & ATA_FLAG_DISABLED) {
- err_mask |= AC_ERR_SYSTEM;
- ap->flags &= ~ATA_FLAG_DISABLED;
- }
-
- return err_mask;
-}
-
-static void ata_qc_issue(struct ata_queued_cmd *qc)
-{
- struct ata_port *ap = qc->ap;
- struct ata_link *link = qc->dev->link;
- u8 prot = qc->tf.protocol;
-
- if (ata_is_ncq(prot)) {
- if (!link->sactive)
- ap->nr_active_links++;
- link->sactive |= 1 << qc->tag;
- } else {
- ap->nr_active_links++;
- link->active_tag = qc->tag;
- }
-
- qc->flags |= ATA_QCFLAG_ACTIVE;
- ap->qc_active |= 1 << qc->tag;
-
- if (qc->dev->flags & ATA_DFLAG_SLEEPING) {
- msleep(1);
- return;
- }
-
- qc->err_mask |= ata_qc_issue_prot(qc);
- if (qc->err_mask)
- goto err;
-
- return;
-err:
- ata_qc_complete(qc);
-}
-
-static unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc)
-{
- struct ata_port *ap = qc->ap;
-
- if (ap->flags & ATA_FLAG_PIO_POLLING) {
- switch (qc->tf.protocol) {
- case ATA_PROT_PIO:
- case ATA_PROT_NODATA:
- case ATAPI_PROT_PIO:
- case ATAPI_PROT_NODATA:
- qc->tf.flags |= ATA_TFLAG_POLLING;
- break;
- default:
- break;
- }
- }
-
- ata_dev_select(ap, qc->dev->devno, 1, 0);
-
- switch (qc->tf.protocol) {
- case ATA_PROT_PIO:
- if (qc->tf.flags & ATA_TFLAG_POLLING)
- qc->tf.ctl |= ATA_NIEN;
-
- ata_tf_to_host(ap, &qc->tf);
-
- ap->hsm_task_state = HSM_ST;
-
- if (qc->tf.flags & ATA_TFLAG_POLLING)
- ata_pio_queue_task(ap, qc, 0);
-
- break;
-
- default:
- return AC_ERR_SYSTEM;
- }
-
- return 0;
-}
-
-static void ata_tf_to_host(struct ata_port *ap,
- const struct ata_taskfile *tf)
-{
- ata_tf_load(ap, tf);
- ata_exec_command(ap, tf);
-}
-
-static void ata_tf_load(struct ata_port *ap,
- const struct ata_taskfile *tf)
-{
- struct ata_ioports *ioaddr = &ap->ioaddr;
- unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
-
- if (tf->ctl != ap->last_ctl) {
- if (ioaddr->ctl_addr)
- writeb(tf->ctl, ioaddr->ctl_addr);
- ap->last_ctl = tf->ctl;
- ata_wait_idle(ap);
- }
-
- if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
- writeb(tf->hob_feature, ioaddr->feature_addr);
- writeb(tf->hob_nsect, ioaddr->nsect_addr);
- writeb(tf->hob_lbal, ioaddr->lbal_addr);
- writeb(tf->hob_lbam, ioaddr->lbam_addr);
- writeb(tf->hob_lbah, ioaddr->lbah_addr);
- }
-
- if (is_addr) {
- writeb(tf->feature, ioaddr->feature_addr);
- writeb(tf->nsect, ioaddr->nsect_addr);
- writeb(tf->lbal, ioaddr->lbal_addr);
- writeb(tf->lbam, ioaddr->lbam_addr);
- writeb(tf->lbah, ioaddr->lbah_addr);
- }
-
- if (tf->flags & ATA_TFLAG_DEVICE)
- writeb(tf->device, ioaddr->device_addr);
-
- ata_wait_idle(ap);
-}
-
-static void ata_exec_command(struct ata_port *ap,
- const struct ata_taskfile *tf)
-{
- writeb(tf->command, ap->ioaddr.command_addr);
-
- readb(ap->ioaddr.altstatus_addr);
-
- udelay(1);
-}
-
-static void ata_pio_queue_task(struct ata_port *ap,
- void *data,unsigned long delay)
-{
- ap->port_task_data = data;
-}
-
-static unsigned int ac_err_mask(u8 status)
-{
- if (status & (ATA_BUSY | ATA_DRQ))
- return AC_ERR_HSM;
- if (status & (ATA_ERR | ATA_DF))
- return AC_ERR_DEV;
- return 0;
-}
-
-static unsigned int __ac_err_mask(u8 status)
-{
- unsigned int mask = ac_err_mask(status);
- if (mask == 0)
- return AC_ERR_OTHER;
- return mask;
-}
-
-static void ata_pio_task(struct ata_port *arg_ap)
-{
- struct ata_port *ap = arg_ap;
- struct ata_queued_cmd *qc = ap->port_task_data;
- u8 status;
- int poll_next;
-
-fsm_start:
- /*
- * This is purely heuristic. This is a fast path.
- * Sometimes when we enter, BSY will be cleared in
- * a chk-status or two. If not, the drive is probably seeking
- * or something. Snooze for a couple msecs, then
- * chk-status again. If still busy, queue delayed work.
- */
- status = ata_busy_wait(ap, ATA_BUSY, 5);
- if (status & ATA_BUSY) {
- msleep(2);
- status = ata_busy_wait(ap, ATA_BUSY, 10);
- if (status & ATA_BUSY) {
- ata_pio_queue_task(ap, qc, ATA_SHORT_PAUSE);
- return;
- }
- }
-
- poll_next = ata_hsm_move(ap, qc, status, 1);
-
- /* another command or interrupt handler
- * may be running at this point.
- */
- if (poll_next)
- goto fsm_start;
-}
-
-static int ata_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
- u8 status, int in_wq)
-{
- int poll_next;
-
-fsm_start:
- switch (ap->hsm_task_state) {
- case HSM_ST_FIRST:
- poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
-
- if ((status & ATA_DRQ) == 0) {
- if (status & (ATA_ERR | ATA_DF)) {
- qc->err_mask |= AC_ERR_DEV;
- } else {
- qc->err_mask |= AC_ERR_HSM;
- }
- ap->hsm_task_state = HSM_ST_ERR;
- goto fsm_start;
- }
-
- /* Device should not ask for data transfer (DRQ=1)
- * when it finds something wrong.
- * We ignore DRQ here and stop the HSM by
- * changing hsm_task_state to HSM_ST_ERR and
- * let the EH abort the command or reset the device.
- */
- if (status & (ATA_ERR | ATA_DF)) {
- if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
- printf("DRQ=1 with device error, "
- "dev_stat 0x%X\n", status);
- qc->err_mask |= AC_ERR_HSM;
- ap->hsm_task_state = HSM_ST_ERR;
- goto fsm_start;
- }
- }
-
- if (qc->tf.protocol == ATA_PROT_PIO) {
- /* PIO data out protocol.
- * send first data block.
- */
- /* ata_pio_sectors() might change the state
- * to HSM_ST_LAST. so, the state is changed here
- * before ata_pio_sectors().
- */
- ap->hsm_task_state = HSM_ST;
- ata_pio_sectors(qc);
- } else {
- printf("protocol is not ATA_PROT_PIO \n");
- }
- break;
-
- case HSM_ST:
- if ((status & ATA_DRQ) == 0) {
- if (status & (ATA_ERR | ATA_DF)) {
- qc->err_mask |= AC_ERR_DEV;
- } else {
- /* HSM violation. Let EH handle this.
- * Phantom devices also trigger this
- * condition. Mark hint.
- */
- qc->err_mask |= AC_ERR_HSM | AC_ERR_NODEV_HINT;
- }
-
- ap->hsm_task_state = HSM_ST_ERR;
- goto fsm_start;
- }
- /* For PIO reads, some devices may ask for
- * data transfer (DRQ=1) alone with ERR=1.
- * We respect DRQ here and transfer one
- * block of junk data before changing the
- * hsm_task_state to HSM_ST_ERR.
- *
- * For PIO writes, ERR=1 DRQ=1 doesn't make
- * sense since the data block has been
- * transferred to the device.
- */
- if (status & (ATA_ERR | ATA_DF)) {
- qc->err_mask |= AC_ERR_DEV;
-
- if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
- ata_pio_sectors(qc);
- status = ata_wait_idle(ap);
- }
-
- if (status & (ATA_BUSY | ATA_DRQ))
- qc->err_mask |= AC_ERR_HSM;
-
- /* ata_pio_sectors() might change the
- * state to HSM_ST_LAST. so, the state
- * is changed after ata_pio_sectors().
- */
- ap->hsm_task_state = HSM_ST_ERR;
- goto fsm_start;
- }
-
- ata_pio_sectors(qc);
- if (ap->hsm_task_state == HSM_ST_LAST &&
- (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
- status = ata_wait_idle(ap);
- goto fsm_start;
- }
-
- poll_next = 1;
- break;
-
- case HSM_ST_LAST:
- if (!ata_ok(status)) {
- qc->err_mask |= __ac_err_mask(status);
- ap->hsm_task_state = HSM_ST_ERR;
- goto fsm_start;
- }
-
- ap->hsm_task_state = HSM_ST_IDLE;
-
- ata_hsm_qc_complete(qc, in_wq);
-
- poll_next = 0;
- break;
-
- case HSM_ST_ERR:
- /* make sure qc->err_mask is available to
- * know what's wrong and recover
- */
- ap->hsm_task_state = HSM_ST_IDLE;
-
- ata_hsm_qc_complete(qc, in_wq);
-
- poll_next = 0;
- break;
- default:
- poll_next = 0;
- }
-
- return poll_next;
-}
-
-static void ata_pio_sectors(struct ata_queued_cmd *qc)
-{
- struct ata_port *ap;
- ap = pap;
- qc->pdata = ap->pdata;
-
- ata_pio_sector(qc);
-
- readb(qc->ap->ioaddr.altstatus_addr);
- udelay(1);
-}
-
-static void ata_pio_sector(struct ata_queued_cmd *qc)
-{
- int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
- struct ata_port *ap = qc->ap;
- unsigned int offset;
- unsigned char *buf;
- char temp_data_buf[512];
-
- if (qc->curbytes == qc->nbytes - qc->sect_size)
- ap->hsm_task_state = HSM_ST_LAST;
-
- offset = qc->curbytes;
-
- switch (qc->tf.command) {
- case ATA_CMD_ID_ATA:
- buf = (unsigned char *)&ata_device.id[0];
- break;
- case ATA_CMD_PIO_READ_EXT:
- case ATA_CMD_PIO_READ:
- case ATA_CMD_PIO_WRITE_EXT:
- case ATA_CMD_PIO_WRITE:
- buf = qc->pdata + offset;
- break;
- default:
- buf = (unsigned char *)&temp_data_buf[0];
- }
-
- ata_mmio_data_xfer(qc->dev, buf, qc->sect_size, do_write);
-
- qc->curbytes += qc->sect_size;
-
-}
-
-static void ata_mmio_data_xfer(struct ata_device *dev, unsigned char *buf,
- unsigned int buflen, int do_write)
-{
- struct ata_port *ap = pap;
- void __iomem *data_addr = ap->ioaddr.data_addr;
- unsigned int words = buflen >> 1;
- u16 *buf16 = (u16 *)buf;
- unsigned int i = 0;
-
- udelay(100);
- if (do_write) {
- for (i = 0; i < words; i++)
- writew(le16_to_cpu(buf16[i]), data_addr);
- } else {
- for (i = 0; i < words; i++)
- buf16[i] = cpu_to_le16(readw(data_addr));
- }
-
- if (buflen & 0x01) {
- __le16 align_buf[1] = { 0 };
- unsigned char *trailing_buf = buf + buflen - 1;
-
- if (do_write) {
- memcpy(align_buf, trailing_buf, 1);
- writew(le16_to_cpu(align_buf[0]), data_addr);
- } else {
- align_buf[0] = cpu_to_le16(readw(data_addr));
- memcpy(trailing_buf, align_buf, 1);
- }
- }
-}
-
-static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
-{
- struct ata_port *ap = qc->ap;
-
- if (in_wq) {
- /* EH might have kicked in while host lock is
- * released.
- */
- qc = &ap->qcmd[qc->tag];
- if (qc) {
- if (!(qc->err_mask & AC_ERR_HSM)) {
- ata_irq_on(ap);
- ata_qc_complete(qc);
- } else {
- ata_port_freeze(ap);
- }
- }
- } else {
- if (!(qc->err_mask & AC_ERR_HSM)) {
- ata_qc_complete(qc);
- } else {
- ata_port_freeze(ap);
- }
- }
-}
-
-static u8 ata_irq_on(struct ata_port *ap)
-{
- struct ata_ioports *ioaddr = &ap->ioaddr;
- u8 tmp;
-
- ap->ctl &= ~ATA_NIEN;
- ap->last_ctl = ap->ctl;
-
- if (ioaddr->ctl_addr)
- writeb(ap->ctl, ioaddr->ctl_addr);
-
- tmp = ata_wait_idle(ap);
-
- return tmp;
-}
-
-static unsigned int ata_tag_internal(unsigned int tag)
-{
- return tag == ATA_MAX_QUEUE - 1;
-}
-
-static void ata_qc_complete(struct ata_queued_cmd *qc)
-{
- struct ata_device *dev = qc->dev;
- if (qc->err_mask)
- qc->flags |= ATA_QCFLAG_FAILED;
-
- if (qc->flags & ATA_QCFLAG_FAILED) {
- if (!ata_tag_internal(qc->tag)) {
- fill_result_tf(qc);
- return;
- }
- }
- if (qc->flags & ATA_QCFLAG_RESULT_TF)
- fill_result_tf(qc);
-
- /* Some commands need post-processing after successful
- * completion.
- */
- switch (qc->tf.command) {
- case ATA_CMD_SET_FEATURES:
- if (qc->tf.feature != SETFEATURES_WC_ON &&
- qc->tf.feature != SETFEATURES_WC_OFF)
- break;
- case ATA_CMD_INIT_DEV_PARAMS:
- case ATA_CMD_SET_MULTI:
- break;
-
- case ATA_CMD_SLEEP:
- dev->flags |= ATA_DFLAG_SLEEPING;
- break;
- }
-
- __ata_qc_complete(qc);
-}
-
-static void fill_result_tf(struct ata_queued_cmd *qc)
-{
- struct ata_port *ap = qc->ap;
-
- qc->result_tf.flags = qc->tf.flags;
- ata_tf_read(ap, &qc->result_tf);
-}
-
-static void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
-{
- struct ata_ioports *ioaddr = &ap->ioaddr;
-
- tf->command = ata_check_status(ap);
- tf->feature = readb(ioaddr->error_addr);
- tf->nsect = readb(ioaddr->nsect_addr);
- tf->lbal = readb(ioaddr->lbal_addr);
- tf->lbam = readb(ioaddr->lbam_addr);
- tf->lbah = readb(ioaddr->lbah_addr);
- tf->device = readb(ioaddr->device_addr);
-
- if (tf->flags & ATA_TFLAG_LBA48) {
- if (ioaddr->ctl_addr) {
- writeb(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
-
- tf->hob_feature = readb(ioaddr->error_addr);
- tf->hob_nsect = readb(ioaddr->nsect_addr);
- tf->hob_lbal = readb(ioaddr->lbal_addr);
- tf->hob_lbam = readb(ioaddr->lbam_addr);
- tf->hob_lbah = readb(ioaddr->lbah_addr);
-
- writeb(tf->ctl, ioaddr->ctl_addr);
- ap->last_ctl = tf->ctl;
- } else {
- printf("sata_dwc warnning register read.\n");
- }
- }
-}
-
-static void __ata_qc_complete(struct ata_queued_cmd *qc)
-{
- struct ata_port *ap = qc->ap;
- struct ata_link *link = qc->dev->link;
-
- link->active_tag = ATA_TAG_POISON;
- ap->nr_active_links--;
-
- if (qc->flags & ATA_QCFLAG_CLEAR_EXCL && ap->excl_link == link)
- ap->excl_link = NULL;
-
- qc->flags &= ~ATA_QCFLAG_ACTIVE;
- ap->qc_active &= ~(1 << qc->tag);
-}
-
-static void ata_qc_free(struct ata_queued_cmd *qc)
-{
- struct ata_port *ap = qc->ap;
- unsigned int tag;
- qc->flags = 0;
- tag = qc->tag;
- if (tag < ATA_MAX_QUEUE) {
- qc->tag = ATA_TAG_POISON;
- clear_bit(tag, &ap->qc_allocated);
- }
-}
-
-static int check_sata_dev_state(void)
-{
- unsigned long datalen;
- unsigned char *pdata;
- int ret = 0;
- int i = 0;
- char temp_data_buf[512];
-
- while (1) {
- udelay(10000);
-
- pdata = (unsigned char*)&temp_data_buf[0];
- datalen = 512;
-
- ret = ata_dev_read_sectors(pdata, datalen, 0, 1);
-
- if (ret == TRUE)
- break;
-
- i++;
- if (i > (ATA_RESET_TIME * 100)) {
- printf("** TimeOUT **\n");
- dev_state = SATA_NODEVICE;
- return FALSE;
- }
-
- if ((i >= 100) && ((i % 100) == 0))
- printf(".");
- }
-
- dev_state = SATA_READY;
-
- return TRUE;
-}
-
-static unsigned int ata_dev_set_feature(struct ata_device *dev,
- u8 enable, u8 feature)
-{
- struct ata_taskfile tf;
- struct ata_port *ap;
- ap = pap;
- unsigned int err_mask;
-
- memset(&tf, 0, sizeof(tf));
- tf.ctl = ap->ctl;
-
- tf.device = ATA_DEVICE_OBS;
- tf.command = ATA_CMD_SET_FEATURES;
- tf.feature = enable;
- tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
- tf.protocol = ATA_PROT_NODATA;
- tf.nsect = feature;
-
- err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, 0, 0);
-
- return err_mask;
-}
-
-static unsigned int ata_dev_init_params(struct ata_device *dev,
- u16 heads, u16 sectors)
-{
- struct ata_taskfile tf;
- struct ata_port *ap;
- ap = pap;
- unsigned int err_mask;
-
- if (sectors < 1 || sectors > 255 || heads < 1 || heads > 16)
- return AC_ERR_INVALID;
-
- memset(&tf, 0, sizeof(tf));
- tf.ctl = ap->ctl;
- tf.device = ATA_DEVICE_OBS;
- tf.command = ATA_CMD_INIT_DEV_PARAMS;
- tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
- tf.protocol = ATA_PROT_NODATA;
- tf.nsect = sectors;
- tf.device |= (heads - 1) & 0x0f;
-
- err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, 0, 0);
-
- if (err_mask == AC_ERR_DEV && (tf.feature & ATA_ABORTED))
- err_mask = 0;
-
- return err_mask;
-}
-
-#if defined(CONFIG_SATA_DWC) && !defined(CONFIG_LBA48)
-#define SATA_MAX_READ_BLK 0xFF
-#else
-#define SATA_MAX_READ_BLK 0xFFFF
-#endif
-
-ulong sata_read(int device, ulong blknr, lbaint_t blkcnt, void *buffer)
-{
- ulong start,blks, buf_addr;
- unsigned short smallblks;
- unsigned long datalen;
- unsigned char *pdata;
- device &= 0xff;
-
- u32 block = 0;
- u32 n_block = 0;
-
- if (dev_state != SATA_READY)
- return 0;
-
- buf_addr = (unsigned long)buffer;
- start = blknr;
- blks = blkcnt;
- do {
- pdata = (unsigned char *)buf_addr;
- if (blks > SATA_MAX_READ_BLK) {
- datalen = sata_dev_desc[device].blksz * SATA_MAX_READ_BLK;
- smallblks = SATA_MAX_READ_BLK;
-
- block = (u32)start;
- n_block = (u32)smallblks;
-
- start += SATA_MAX_READ_BLK;
- blks -= SATA_MAX_READ_BLK;
- } else {
- datalen = sata_dev_desc[device].blksz * SATA_MAX_READ_BLK;
- datalen = sata_dev_desc[device].blksz * blks;
- smallblks = (unsigned short)blks;
-
- block = (u32)start;
- n_block = (u32)smallblks;
-
- start += blks;
- blks = 0;
- }
-
- if (ata_dev_read_sectors(pdata, datalen, block, n_block) != TRUE) {
- printf("sata_dwc : Hard disk read error.\n");
- blkcnt -= blks;
- break;
- }
- buf_addr += datalen;
- } while (blks != 0);
-
- return (blkcnt);
-}
-
-static int ata_dev_read_sectors(unsigned char *pdata, unsigned long datalen,
- u32 block, u32 n_block)
-{
- struct ata_port *ap = pap;
- struct ata_device *dev = &ata_device;
- struct ata_taskfile tf;
- unsigned int class = ATA_DEV_ATA;
- unsigned int err_mask = 0;
- const char *reason;
- int may_fallback = 1;
- int rc;
-
- if (dev_state == SATA_ERROR)
- return FALSE;
-
- ata_dev_select(ap, dev->devno, 1, 1);
-
-retry:
- memset(&tf, 0, sizeof(tf));
- tf.ctl = ap->ctl;
- ap->print_id = 1;
- ap->flags &= ~ATA_FLAG_DISABLED;
-
- ap->pdata = pdata;
-
- tf.device = ATA_DEVICE_OBS;
-
- temp_n_block = n_block;
-
-#ifdef CONFIG_LBA48
- tf.command = ATA_CMD_PIO_READ_EXT;
- tf.flags |= ATA_TFLAG_LBA | ATA_TFLAG_LBA48;
-
- tf.hob_feature = 31;
- tf.feature = 31;
- tf.hob_nsect = (n_block >> 8) & 0xff;
- tf.nsect = n_block & 0xff;
-
- tf.hob_lbah = 0x0;
- tf.hob_lbam = 0x0;
- tf.hob_lbal = (block >> 24) & 0xff;
- tf.lbah = (block >> 16) & 0xff;
- tf.lbam = (block >> 8) & 0xff;
- tf.lbal = block & 0xff;
-
- tf.device = 1 << 6;
- if (tf.flags & ATA_TFLAG_FUA)
- tf.device |= 1 << 7;
-#else
- tf.command = ATA_CMD_PIO_READ;
- tf.flags |= ATA_TFLAG_LBA ;
-
- tf.feature = 31;
- tf.nsect = n_block & 0xff;
-
- tf.lbah = (block >> 16) & 0xff;
- tf.lbam = (block >> 8) & 0xff;
- tf.lbal = block & 0xff;
-
- tf.device = (block >> 24) & 0xf;
-
- tf.device |= 1 << 6;
- if (tf.flags & ATA_TFLAG_FUA)
- tf.device |= 1 << 7;
-
-#endif
-
- tf.protocol = ATA_PROT_PIO;
-
- /* Some devices choke if TF registers contain garbage. Make
- * sure those are properly initialized.
- */
- tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
- tf.flags |= ATA_TFLAG_POLLING;
-
- err_mask = ata_exec_internal(dev, &tf, NULL, DMA_FROM_DEVICE, 0, 0);
-
- if (err_mask) {
- if (err_mask & AC_ERR_NODEV_HINT) {
- printf("READ_SECTORS NODEV after polling detection\n");
- return -ENOENT;
- }
-
- if ((err_mask == AC_ERR_DEV) && (tf.feature & ATA_ABORTED)) {
- /* Device or controller might have reported
- * the wrong device class. Give a shot at the
- * other IDENTIFY if the current one is
- * aborted by the device.
- */
- if (may_fallback) {
- may_fallback = 0;
-
- if (class == ATA_DEV_ATA) {
- class = ATA_DEV_ATAPI;
- } else {
- class = ATA_DEV_ATA;
- }
- goto retry;
- }
- /* Control reaches here iff the device aborted
- * both flavors of IDENTIFYs which happens
- * sometimes with phantom devices.
- */
- printf("both IDENTIFYs aborted, assuming NODEV\n");
- return -ENOENT;
- }
-
- rc = -EIO;
- reason = "I/O error";
- goto err_out;
- }
-
- /* Falling back doesn't make sense if ID data was read
- * successfully at least once.
- */
- may_fallback = 0;
-
- rc = -EINVAL;
- reason = "device reports invalid type";
-
- return TRUE;
-
-err_out:
- printf("failed to READ SECTORS (%s, err_mask=0x%x)\n", reason, err_mask);
- return FALSE;
-}
-
-#if defined(CONFIG_SATA_DWC) && !defined(CONFIG_LBA48)
-#define SATA_MAX_WRITE_BLK 0xFF
-#else
-#define SATA_MAX_WRITE_BLK 0xFFFF
-#endif
-
-ulong sata_write(int device, ulong blknr, lbaint_t blkcnt, void *buffer)
-{
- ulong start,blks, buf_addr;
- unsigned short smallblks;
- unsigned long datalen;
- unsigned char *pdata;
- device &= 0xff;
-
-
- u32 block = 0;
- u32 n_block = 0;
-
- if (dev_state != SATA_READY)
- return 0;
-
- buf_addr = (unsigned long)buffer;
- start = blknr;
- blks = blkcnt;
- do {
- pdata = (unsigned char *)buf_addr;
- if (blks > SATA_MAX_WRITE_BLK) {
- datalen = sata_dev_desc[device].blksz * SATA_MAX_WRITE_BLK;
- smallblks = SATA_MAX_WRITE_BLK;
-
- block = (u32)start;
- n_block = (u32)smallblks;
-
- start += SATA_MAX_WRITE_BLK;
- blks -= SATA_MAX_WRITE_BLK;
- } else {
- datalen = sata_dev_desc[device].blksz * blks;
- smallblks = (unsigned short)blks;
-
- block = (u32)start;
- n_block = (u32)smallblks;
-
- start += blks;
- blks = 0;
- }
-
- if (ata_dev_write_sectors(pdata, datalen, block, n_block) != TRUE) {
- printf("sata_dwc : Hard disk read error.\n");
- blkcnt -= blks;
- break;
- }
- buf_addr += datalen;
- } while (blks != 0);
-
- return (blkcnt);
-}
-
-static int ata_dev_write_sectors(unsigned char* pdata, unsigned long datalen,
- u32 block, u32 n_block)
-{
- struct ata_port *ap = pap;
- struct ata_device *dev = &ata_device;
- struct ata_taskfile tf;
- unsigned int class = ATA_DEV_ATA;
- unsigned int err_mask = 0;
- const char *reason;
- int may_fallback = 1;
- int rc;
-
- if (dev_state == SATA_ERROR)
- return FALSE;
-
- ata_dev_select(ap, dev->devno, 1, 1);
-
-retry:
- memset(&tf, 0, sizeof(tf));
- tf.ctl = ap->ctl;
- ap->print_id = 1;
- ap->flags &= ~ATA_FLAG_DISABLED;
-
- ap->pdata = pdata;
-
- tf.device = ATA_DEVICE_OBS;
-
- temp_n_block = n_block;
-
-
-#ifdef CONFIG_LBA48
- tf.command = ATA_CMD_PIO_WRITE_EXT;
- tf.flags |= ATA_TFLAG_LBA | ATA_TFLAG_LBA48 | ATA_TFLAG_WRITE;
-
- tf.hob_feature = 31;
- tf.feature = 31;
- tf.hob_nsect = (n_block >> 8) & 0xff;
- tf.nsect = n_block & 0xff;
-
- tf.hob_lbah = 0x0;
- tf.hob_lbam = 0x0;
- tf.hob_lbal = (block >> 24) & 0xff;
- tf.lbah = (block >> 16) & 0xff;
- tf.lbam = (block >> 8) & 0xff;
- tf.lbal = block & 0xff;
-
- tf.device = 1 << 6;
- if (tf.flags & ATA_TFLAG_FUA)
- tf.device |= 1 << 7;
-#else
- tf.command = ATA_CMD_PIO_WRITE;
- tf.flags |= ATA_TFLAG_LBA | ATA_TFLAG_WRITE;
-
- tf.feature = 31;
- tf.nsect = n_block & 0xff;
-
- tf.lbah = (block >> 16) & 0xff;
- tf.lbam = (block >> 8) & 0xff;
- tf.lbal = block & 0xff;
-
- tf.device = (block >> 24) & 0xf;
-
- tf.device |= 1 << 6;
- if (tf.flags & ATA_TFLAG_FUA)
- tf.device |= 1 << 7;
-
-#endif
-
- tf.protocol = ATA_PROT_PIO;
-
- /* Some devices choke if TF registers contain garbage. Make
- * sure those are properly initialized.
- */
- tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
- tf.flags |= ATA_TFLAG_POLLING;
-
- err_mask = ata_exec_internal(dev, &tf, NULL, DMA_FROM_DEVICE, 0, 0);
-
- if (err_mask) {
- if (err_mask & AC_ERR_NODEV_HINT) {
- printf("READ_SECTORS NODEV after polling detection\n");
- return -ENOENT;
- }
-
- if ((err_mask == AC_ERR_DEV) && (tf.feature & ATA_ABORTED)) {
- /* Device or controller might have reported
- * the wrong device class. Give a shot at the
- * other IDENTIFY if the current one is
- * aborted by the device.
- */
- if (may_fallback) {
- may_fallback = 0;
-
- if (class == ATA_DEV_ATA) {
- class = ATA_DEV_ATAPI;
- } else {
- class = ATA_DEV_ATA;
- }
- goto retry;
- }
- /* Control reaches here iff the device aborted
- * both flavors of IDENTIFYs which happens
- * sometimes with phantom devices.
- */
- printf("both IDENTIFYs aborted, assuming NODEV\n");
- return -ENOENT;
- }
-
- rc = -EIO;
- reason = "I/O error";
- goto err_out;
- }
-
- /* Falling back doesn't make sense if ID data was read
- * successfully at least once.
- */
- may_fallback = 0;
-
- rc = -EINVAL;
- reason = "device reports invalid type";
-
- return TRUE;
-
-err_out:
- printf("failed to WRITE SECTORS (%s, err_mask=0x%x)\n", reason, err_mask);
- return FALSE;
-}
+++ /dev/null
-/*
- * sata_dwc.h
- *
- * Synopsys DesignWare Cores (DWC) SATA host driver
- *
- * Author: Mark Miesfeld <mmiesfeld@amcc.com>
- *
- * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
- * Copyright 2008 DENX Software Engineering
- *
- * Based on versions provided by AMCC and Synopsys which are:
- * Copyright 2006 Applied Micro Circuits Corporation
- * COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED
- *
- * This program is free software; you can redistribute
- * it and/or modify it under the terms of the GNU
- * General Public License as published by the
- * Free Software Foundation; either version 2 of the License,
- * or (at your option) any later version.
- *
- */
-/*
- * SATA support based on the chip canyonlands.
- *
- * 04-17-2009
- * The local version of this driver for the canyonlands board
- * does not use interrupts but polls the chip instead.
- */
-
-
-#ifndef _SATA_DWC_H_
-#define _SATA_DWC_H_
-
-#define __U_BOOT__
-
-#define HZ 100
-#define READ 0
-#define WRITE 1
-
-enum {
- ATA_READID_POSTRESET = (1 << 0),
-
- ATA_DNXFER_PIO = 0,
- ATA_DNXFER_DMA = 1,
- ATA_DNXFER_40C = 2,
- ATA_DNXFER_FORCE_PIO = 3,
- ATA_DNXFER_FORCE_PIO0 = 4,
-
- ATA_DNXFER_QUIET = (1 << 31),
-};
-
-enum hsm_task_states {
- HSM_ST_IDLE,
- HSM_ST_FIRST,
- HSM_ST,
- HSM_ST_LAST,
- HSM_ST_ERR,
-};
-
-#define ATA_SHORT_PAUSE ((HZ >> 6) + 1)
-
-struct ata_queued_cmd {
- struct ata_port *ap;
- struct ata_device *dev;
-
- struct ata_taskfile tf;
- u8 cdb[ATAPI_CDB_LEN];
- unsigned long flags;
- unsigned int tag;
- unsigned int n_elem;
-
- int dma_dir;
- unsigned int sect_size;
-
- unsigned int nbytes;
- unsigned int extrabytes;
- unsigned int curbytes;
-
- unsigned int err_mask;
- struct ata_taskfile result_tf;
-
- void *private_data;
-#ifndef __U_BOOT__
- void *lldd_task;
-#endif
- unsigned char *pdata;
-};
-
-typedef void (*ata_qc_cb_t) (struct ata_queued_cmd *qc);
-
-#define ATA_TAG_POISON 0xfafbfcfdU
-
-enum {
- LIBATA_MAX_PRD = ATA_MAX_PRD / 2,
- LIBATA_DUMB_MAX_PRD = ATA_MAX_PRD / 4,
- ATA_MAX_PORTS = 8,
- ATA_DEF_QUEUE = 1,
- ATA_MAX_QUEUE = 32,
- ATA_TAG_INTERNAL = ATA_MAX_QUEUE - 1,
- ATA_MAX_BUS = 2,
- ATA_DEF_BUSY_WAIT = 10000,
-
- ATAPI_MAX_DRAIN = 16 << 10,
-
- ATA_SHT_EMULATED = 1,
- ATA_SHT_CMD_PER_LUN = 1,
- ATA_SHT_THIS_ID = -1,
- ATA_SHT_USE_CLUSTERING = 1,
-
- ATA_DFLAG_LBA = (1 << 0),
- ATA_DFLAG_LBA48 = (1 << 1),
- ATA_DFLAG_CDB_INTR = (1 << 2),
- ATA_DFLAG_NCQ = (1 << 3),
- ATA_DFLAG_FLUSH_EXT = (1 << 4),
- ATA_DFLAG_ACPI_PENDING = (1 << 5),
- ATA_DFLAG_ACPI_FAILED = (1 << 6),
- ATA_DFLAG_AN = (1 << 7),
- ATA_DFLAG_HIPM = (1 << 8),
- ATA_DFLAG_DIPM = (1 << 9),
- ATA_DFLAG_DMADIR = (1 << 10),
- ATA_DFLAG_CFG_MASK = (1 << 12) - 1,
-
- ATA_DFLAG_PIO = (1 << 12),
- ATA_DFLAG_NCQ_OFF = (1 << 13),
- ATA_DFLAG_SPUNDOWN = (1 << 14),
- ATA_DFLAG_SLEEPING = (1 << 15),
- ATA_DFLAG_DUBIOUS_XFER = (1 << 16),
- ATA_DFLAG_INIT_MASK = (1 << 24) - 1,
-
- ATA_DFLAG_DETACH = (1 << 24),
- ATA_DFLAG_DETACHED = (1 << 25),
-
- ATA_LFLAG_HRST_TO_RESUME = (1 << 0),
- ATA_LFLAG_SKIP_D2H_BSY = (1 << 1),
- ATA_LFLAG_NO_SRST = (1 << 2),
- ATA_LFLAG_ASSUME_ATA = (1 << 3),
- ATA_LFLAG_ASSUME_SEMB = (1 << 4),
- ATA_LFLAG_ASSUME_CLASS = ATA_LFLAG_ASSUME_ATA | ATA_LFLAG_ASSUME_SEMB,
- ATA_LFLAG_NO_RETRY = (1 << 5),
- ATA_LFLAG_DISABLED = (1 << 6),
-
- ATA_FLAG_SLAVE_POSS = (1 << 0),
- ATA_FLAG_SATA = (1 << 1),
- ATA_FLAG_NO_LEGACY = (1 << 2),
- ATA_FLAG_MMIO = (1 << 3),
- ATA_FLAG_SRST = (1 << 4),
- ATA_FLAG_SATA_RESET = (1 << 5),
- ATA_FLAG_NO_ATAPI = (1 << 6),
- ATA_FLAG_PIO_DMA = (1 << 7),
- ATA_FLAG_PIO_LBA48 = (1 << 8),
- ATA_FLAG_PIO_POLLING = (1 << 9),
- ATA_FLAG_NCQ = (1 << 10),
- ATA_FLAG_DEBUGMSG = (1 << 13),
- ATA_FLAG_IGN_SIMPLEX = (1 << 15),
- ATA_FLAG_NO_IORDY = (1 << 16),
- ATA_FLAG_ACPI_SATA = (1 << 17),
- ATA_FLAG_AN = (1 << 18),
- ATA_FLAG_PMP = (1 << 19),
- ATA_FLAG_IPM = (1 << 20),
-
- ATA_FLAG_DISABLED = (1 << 23),
-
- ATA_PFLAG_EH_PENDING = (1 << 0),
- ATA_PFLAG_EH_IN_PROGRESS = (1 << 1),
- ATA_PFLAG_FROZEN = (1 << 2),
- ATA_PFLAG_RECOVERED = (1 << 3),
- ATA_PFLAG_LOADING = (1 << 4),
- ATA_PFLAG_UNLOADING = (1 << 5),
- ATA_PFLAG_SCSI_HOTPLUG = (1 << 6),
- ATA_PFLAG_INITIALIZING = (1 << 7),
- ATA_PFLAG_RESETTING = (1 << 8),
- ATA_PFLAG_SUSPENDED = (1 << 17),
- ATA_PFLAG_PM_PENDING = (1 << 18),
-
- ATA_QCFLAG_ACTIVE = (1 << 0),
- ATA_QCFLAG_DMAMAP = (1 << 1),
- ATA_QCFLAG_IO = (1 << 3),
- ATA_QCFLAG_RESULT_TF = (1 << 4),
- ATA_QCFLAG_CLEAR_EXCL = (1 << 5),
- ATA_QCFLAG_QUIET = (1 << 6),
-
- ATA_QCFLAG_FAILED = (1 << 16),
- ATA_QCFLAG_SENSE_VALID = (1 << 17),
- ATA_QCFLAG_EH_SCHEDULED = (1 << 18),
-
- ATA_HOST_SIMPLEX = (1 << 0),
- ATA_HOST_STARTED = (1 << 1),
-
- ATA_TMOUT_BOOT = 30 * 100,
- ATA_TMOUT_BOOT_QUICK = 7 * 100,
- ATA_TMOUT_INTERNAL = 30 * 100,
- ATA_TMOUT_INTERNAL_QUICK = 5 * 100,
-
- /* FIXME: GoVault needs 2s but we can't afford that without
- * parallel probing. 800ms is enough for iVDR disk
- * HHD424020F7SV00. Increase to 2secs when parallel probing
- * is in place.
- */
- ATA_TMOUT_FF_WAIT = 4 * 100 / 5,
-
- BUS_UNKNOWN = 0,
- BUS_DMA = 1,
- BUS_IDLE = 2,
- BUS_NOINTR = 3,
- BUS_NODATA = 4,
- BUS_TIMER = 5,
- BUS_PIO = 6,
- BUS_EDD = 7,
- BUS_IDENTIFY = 8,
- BUS_PACKET = 9,
-
- PORT_UNKNOWN = 0,
- PORT_ENABLED = 1,
- PORT_DISABLED = 2,
-
- /* encoding various smaller bitmaps into a single
- * unsigned long bitmap
- */
- ATA_NR_PIO_MODES = 7,
- ATA_NR_MWDMA_MODES = 5,
- ATA_NR_UDMA_MODES = 8,
-
- ATA_SHIFT_PIO = 0,
- ATA_SHIFT_MWDMA = ATA_SHIFT_PIO + ATA_NR_PIO_MODES,
- ATA_SHIFT_UDMA = ATA_SHIFT_MWDMA + ATA_NR_MWDMA_MODES,
-
- ATA_DMA_PAD_SZ = 4,
-
- ATA_ERING_SIZE = 32,
-
- ATA_DEFER_LINK = 1,
- ATA_DEFER_PORT = 2,
-
- ATA_EH_DESC_LEN = 80,
-
- ATA_EH_REVALIDATE = (1 << 0),
- ATA_EH_SOFTRESET = (1 << 1),
- ATA_EH_HARDRESET = (1 << 2),
- ATA_EH_ENABLE_LINK = (1 << 3),
- ATA_EH_LPM = (1 << 4),
-
- ATA_EH_RESET_MASK = ATA_EH_SOFTRESET | ATA_EH_HARDRESET,
- ATA_EH_PERDEV_MASK = ATA_EH_REVALIDATE,
-
- ATA_EHI_HOTPLUGGED = (1 << 0),
- ATA_EHI_RESUME_LINK = (1 << 1),
- ATA_EHI_NO_AUTOPSY = (1 << 2),
- ATA_EHI_QUIET = (1 << 3),
-
- ATA_EHI_DID_SOFTRESET = (1 << 16),
- ATA_EHI_DID_HARDRESET = (1 << 17),
- ATA_EHI_PRINTINFO = (1 << 18),
- ATA_EHI_SETMODE = (1 << 19),
- ATA_EHI_POST_SETMODE = (1 << 20),
-
- ATA_EHI_DID_RESET = ATA_EHI_DID_SOFTRESET | ATA_EHI_DID_HARDRESET,
- ATA_EHI_RESET_MODIFIER_MASK = ATA_EHI_RESUME_LINK,
-
- ATA_EH_MAX_TRIES = 5,
-
- ATA_PROBE_MAX_TRIES = 3,
- ATA_EH_DEV_TRIES = 3,
- ATA_EH_PMP_TRIES = 5,
- ATA_EH_PMP_LINK_TRIES = 3,
-
- SATA_PMP_SCR_TIMEOUT = 250,
-
- /* Horkage types. May be set by libata or controller on drives
- (some horkage may be drive/controller pair dependant */
-
- ATA_HORKAGE_DIAGNOSTIC = (1 << 0),
- ATA_HORKAGE_NODMA = (1 << 1),
- ATA_HORKAGE_NONCQ = (1 << 2),
- ATA_HORKAGE_MAX_SEC_128 = (1 << 3),
- ATA_HORKAGE_BROKEN_HPA = (1 << 4),
- ATA_HORKAGE_SKIP_PM = (1 << 5),
- ATA_HORKAGE_HPA_SIZE = (1 << 6),
- ATA_HORKAGE_IPM = (1 << 7),
- ATA_HORKAGE_IVB = (1 << 8),
- ATA_HORKAGE_STUCK_ERR = (1 << 9),
-
- ATA_DMA_MASK_ATA = (1 << 0),
- ATA_DMA_MASK_ATAPI = (1 << 1),
- ATA_DMA_MASK_CFA = (1 << 2),
-
- ATAPI_READ = 0,
- ATAPI_WRITE = 1,
- ATAPI_READ_CD = 2,
- ATAPI_PASS_THRU = 3,
- ATAPI_MISC = 4,
-};
-
-enum ata_completion_errors {
- AC_ERR_DEV = (1 << 0),
- AC_ERR_HSM = (1 << 1),
- AC_ERR_TIMEOUT = (1 << 2),
- AC_ERR_MEDIA = (1 << 3),
- AC_ERR_ATA_BUS = (1 << 4),
- AC_ERR_HOST_BUS = (1 << 5),
- AC_ERR_SYSTEM = (1 << 6),
- AC_ERR_INVALID = (1 << 7),
- AC_ERR_OTHER = (1 << 8),
- AC_ERR_NODEV_HINT = (1 << 9),
- AC_ERR_NCQ = (1 << 10),
-};
-
-enum ata_xfer_mask {
- ATA_MASK_PIO = ((1LU << ATA_NR_PIO_MODES) - 1) << ATA_SHIFT_PIO,
- ATA_MASK_MWDMA = ((1LU << ATA_NR_MWDMA_MODES) - 1) << ATA_SHIFT_MWDMA,
- ATA_MASK_UDMA = ((1LU << ATA_NR_UDMA_MODES) - 1) << ATA_SHIFT_UDMA,
-};
-
-struct ata_port_info {
-#ifndef __U_BOOT__
- struct scsi_host_template *sht;
-#endif
- unsigned long flags;
- unsigned long link_flags;
- unsigned long pio_mask;
- unsigned long mwdma_mask;
- unsigned long udma_mask;
-#ifndef __U_BOOT__
- const struct ata_port_operations *port_ops;
- void *private_data;
-#endif
-};
-
-struct ata_ioports {
- void __iomem *cmd_addr;
- void __iomem *data_addr;
- void __iomem *error_addr;
- void __iomem *feature_addr;
- void __iomem *nsect_addr;
- void __iomem *lbal_addr;
- void __iomem *lbam_addr;
- void __iomem *lbah_addr;
- void __iomem *device_addr;
- void __iomem *status_addr;
- void __iomem *command_addr;
- void __iomem *altstatus_addr;
- void __iomem *ctl_addr;
-#ifndef __U_BOOT__
- void __iomem *bmdma_addr;
-#endif
- void __iomem *scr_addr;
-};
-
-struct ata_host {
-#ifndef __U_BOOT__
- void __iomem * const *iomap;
- void *private_data;
- const struct ata_port_operations *ops;
- unsigned long flags;
- struct ata_port *simplex_claimed;
-#endif
- unsigned int n_ports;
- struct ata_port *ports[0];
-};
-
-#ifndef __U_BOOT__
-struct ata_port_stats {
- unsigned long unhandled_irq;
- unsigned long idle_irq;
- unsigned long rw_reqbuf;
-};
-#endif
-
-struct ata_device {
- struct ata_link *link;
- unsigned int devno;
- unsigned long flags;
- unsigned int horkage;
-#ifndef __U_BOOT__
- struct scsi_device *sdev;
-#ifdef CONFIG_ATA_ACPI
- acpi_handle acpi_handle;
- union acpi_object *gtf_cache;
-#endif
-#endif
- u64 n_sectors;
- unsigned int class;
-
- union {
- u16 id[ATA_ID_WORDS];
- u32 gscr[SATA_PMP_GSCR_DWORDS];
- };
-#ifndef __U_BOOT__
- u8 pio_mode;
- u8 dma_mode;
- u8 xfer_mode;
- unsigned int xfer_shift;
-#endif
- unsigned int multi_count;
- unsigned int max_sectors;
- unsigned int cdb_len;
-#ifndef __U_BOOT__
- unsigned long pio_mask;
- unsigned long mwdma_mask;
-#endif
- unsigned long udma_mask;
- u16 cylinders;
- u16 heads;
- u16 sectors;
-#ifndef __U_BOOT__
- int spdn_cnt;
-#endif
-};
-
-enum dma_data_direction {
- DMA_BIDIRECTIONAL = 0,
- DMA_TO_DEVICE = 1,
- DMA_FROM_DEVICE = 2,
- DMA_NONE = 3,
-};
-
-struct ata_link {
- struct ata_port *ap;
- int pmp;
- unsigned int active_tag;
- u32 sactive;
- unsigned int flags;
- unsigned int hw_sata_spd_limit;
-#ifndef __U_BOOT__
- unsigned int sata_spd_limit;
- unsigned int sata_spd;
- struct ata_device device[2];
-#endif
-};
-
-struct ata_port {
- unsigned long flags;
- unsigned int pflags;
- unsigned int print_id;
- unsigned int port_no;
-
- struct ata_ioports ioaddr;
-
- u8 ctl;
- u8 last_ctl;
- unsigned int pio_mask;
- unsigned int mwdma_mask;
- unsigned int udma_mask;
- unsigned int cbl;
-
- struct ata_queued_cmd qcmd[ATA_MAX_QUEUE];
- unsigned long qc_allocated;
- unsigned int qc_active;
- int nr_active_links;
-
- struct ata_link link;
-#ifndef __U_BOOT__
- int nr_pmp_links;
- struct ata_link *pmp_link;
-#endif
- struct ata_link *excl_link;
- int nr_pmp_links;
-#ifndef __U_BOOT__
- struct ata_port_stats stats;
- struct device *dev;
- u32 msg_enable;
-#endif
- struct ata_host *host;
- void *port_task_data;
-
- unsigned int hsm_task_state;
- void *private_data;
- unsigned char *pdata;
-};
-
-#ifndef TRUE
-#define TRUE 1
-#endif
-#ifndef FALSE
-#define FALSE 0
-#endif
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) Excito Elektronik i Skåne AB, All rights reserved.
- * Author: Tor Krill <tor@excito.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * This is a driver for Silicon Image sil3114 sata chip modelled on
- * the ata_piix driver
- */
-
-#include <common.h>
-#include <pci.h>
-#include <command.h>
-#include <config.h>
-#include <asm/byteorder.h>
-#include <asm/io.h>
-#include <ide.h>
-#include <libata.h>
-#include "sata_sil3114.h"
-
-/* Convert sectorsize to wordsize */
-#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
-
-/* Forwards */
-u8 sil3114_spin_up (int num);
-u8 sil3114_spin_down (int num);
-static int sata_bus_softreset (int num);
-static void sata_identify (int num, int dev);
-static u8 check_power_mode (int num);
-static void sata_port (struct sata_ioports *ioport);
-static void set_Feature_cmd (int num, int dev);
-static u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits,
- unsigned int max, u8 usealtstatus);
-static u8 sata_chk_status (struct sata_ioports *ioaddr, u8 usealtstatus);
-static void msleep (int count);
-
-static u32 iobase[6] = { 0, 0, 0, 0, 0, 0}; /* PCI BAR registers for device */
-extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
-
-static struct sata_port port[CONFIG_SYS_SATA_MAX_DEVICE];
-
-static void output_data (struct sata_ioports *ioaddr, u16 * sect_buf, int words)
-{
- while (words--) {
- __raw_writew (*sect_buf++, (void *)ioaddr->data_addr);
- }
-}
-
-static int input_data (struct sata_ioports *ioaddr, u16 * sect_buf, int words)
-{
- while (words--) {
- *sect_buf++ = __raw_readw ((void *)ioaddr->data_addr);
- }
- return 0;
-}
-
-static int sata_bus_softreset (int num)
-{
- u8 status = 0;
-
- port[num].dev_mask = 1;
-
- port[num].ctl_reg = 0x08; /*Default value of control reg */
- writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
- udelay (10);
- writeb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
- udelay (10);
- writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
-
- /* spec mandates ">= 2ms" before checking status.
- * We wait 150ms, because that was the magic delay used for
- * ATAPI devices in Hale Landis's ATADRVR, for the period of time
- * between when the ATA command register is written, and then
- * status is checked. Because waiting for "a while" before
- * checking status is fine, post SRST, we perform this magic
- * delay here as well.
- */
- msleep (150);
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 300, 0);
- while ((status & ATA_BUSY)) {
- msleep (100);
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 3, 0);
- }
-
- if (status & ATA_BUSY) {
- printf ("ata%u is slow to respond,plz be patient\n", num);
- }
-
- while ((status & ATA_BUSY)) {
- msleep (100);
- status = sata_chk_status (&port[num].ioaddr, 0);
- }
-
- if (status & ATA_BUSY) {
- printf ("ata%u failed to respond : ", num);
- printf ("bus reset failed\n");
- port[num].dev_mask = 0;
- return 1;
- }
- return 0;
-}
-
-static void sata_identify (int num, int dev)
-{
- u8 cmd = 0, status = 0, devno = num;
- u16 iobuf[ATA_SECTOR_WORDS];
- u64 n_sectors = 0;
-
- memset (iobuf, 0, sizeof (iobuf));
-
- if (!(port[num].dev_mask & 0x01)) {
- printf ("dev%d is not present on port#%d\n", dev, num);
- return;
- }
-
- debug ("port=%d dev=%d\n", num, dev);
-
- status = 0;
- cmd = ATA_CMD_ID_ATA; /*Device Identify Command */
- writeb (cmd, port[num].ioaddr.command_addr);
- readb (port[num].ioaddr.altstatus_addr);
- udelay (10);
-
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 1000, 0);
- if (status & ATA_ERR) {
- printf ("\ndevice not responding\n");
- port[num].dev_mask &= ~0x01;
- return;
- }
-
- input_data (&port[num].ioaddr, iobuf, ATA_SECTOR_WORDS);
-
- ata_swap_buf_le16 (iobuf, ATA_SECTOR_WORDS);
-
- debug ("Specific config: %x\n", iobuf[2]);
-
- /* we require LBA and DMA support (bits 8 & 9 of word 49) */
- if (!ata_id_has_dma (iobuf) || !ata_id_has_lba (iobuf)) {
- debug ("ata%u: no dma/lba\n", num);
- }
-#ifdef DEBUG
- ata_dump_id (iobuf);
-#endif
- n_sectors = ata_id_n_sectors (iobuf);
-
- if (n_sectors == 0) {
- port[num].dev_mask &= ~0x01;
- return;
- }
- ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].revision,
- ATA_ID_FW_REV, sizeof (sata_dev_desc[devno].revision));
- ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].vendor,
- ATA_ID_PROD, sizeof (sata_dev_desc[devno].vendor));
- ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].product,
- ATA_ID_SERNO, sizeof (sata_dev_desc[devno].product));
-
- /* TODO - atm we asume harddisk ie not removable */
- sata_dev_desc[devno].removable = 0;
-
- sata_dev_desc[devno].lba = (u32) n_sectors;
- debug ("lba=0x%x\n", sata_dev_desc[devno].lba);
-
-#ifdef CONFIG_LBA48
- if (iobuf[83] & (1 << 10)) {
- sata_dev_desc[devno].lba48 = 1;
- } else {
- sata_dev_desc[devno].lba48 = 0;
- }
-#endif
-
- /* assuming HD */
- sata_dev_desc[devno].type = DEV_TYPE_HARDDISK;
- sata_dev_desc[devno].blksz = ATA_SECT_SIZE;
- sata_dev_desc[devno].lun = 0; /* just to fill something in... */
-}
-
-static void set_Feature_cmd (int num, int dev)
-{
- u8 status = 0;
-
- if (!(port[num].dev_mask & 0x01)) {
- debug ("dev%d is not present on port#%d\n", dev, num);
- return;
- }
-
- writeb (SETFEATURES_XFER, port[num].ioaddr.feature_addr);
- writeb (XFER_PIO_4, port[num].ioaddr.nsect_addr);
- writeb (0, port[num].ioaddr.lbal_addr);
- writeb (0, port[num].ioaddr.lbam_addr);
- writeb (0, port[num].ioaddr.lbah_addr);
-
- writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
- writeb (ATA_CMD_SET_FEATURES, port[num].ioaddr.command_addr);
-
- udelay (50);
- msleep (150);
-
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000, 0);
- if ((status & (ATA_BUSY | ATA_ERR))) {
- printf ("Error : status 0x%02x\n", status);
- port[num].dev_mask &= ~0x01;
- }
-}
-
-u8 sil3114_spin_down (int num)
-{
- u8 status = 0;
-
- debug ("Spin down disk\n");
-
- if (!(port[num].dev_mask & 0x01)) {
- debug ("Device ata%d is not present\n", num);
- return 1;
- }
-
- if ((status = check_power_mode (num)) == 0x00) {
- debug ("Already in standby\n");
- return 0;
- }
-
- if (status == 0x01) {
- printf ("Failed to check power mode on ata%d\n", num);
- return 1;
- }
-
- if (!((status = sata_chk_status (&port[num].ioaddr, 0)) & ATA_DRDY)) {
- printf ("Device ata%d not ready\n", num);
- return 1;
- }
-
- writeb (0x00, port[num].ioaddr.feature_addr);
-
- writeb (0x00, port[num].ioaddr.nsect_addr);
- writeb (0x00, port[num].ioaddr.lbal_addr);
- writeb (0x00, port[num].ioaddr.lbam_addr);
- writeb (0x00, port[num].ioaddr.lbah_addr);
-
- writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
- writeb (ATA_CMD_STANDBY, port[num].ioaddr.command_addr);
-
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 30000, 0);
- if ((status & (ATA_BUSY | ATA_ERR))) {
- printf ("Error waiting for disk spin down: status 0x%02x\n",
- status);
- port[num].dev_mask &= ~0x01;
- return 1;
- }
- return 0;
-}
-
-u8 sil3114_spin_up (int num)
-{
- u8 status = 0;
-
- debug ("Spin up disk\n");
-
- if (!(port[num].dev_mask & 0x01)) {
- debug ("Device ata%d is not present\n", num);
- return 1;
- }
-
- if ((status = check_power_mode (num)) != 0x00) {
- if (status == 0x01) {
- printf ("Failed to check power mode on ata%d\n", num);
- return 1;
- } else {
- /* should be up and running already */
- return 0;
- }
- }
-
- if (!((status = sata_chk_status (&port[num].ioaddr, 0)) & ATA_DRDY)) {
- printf ("Device ata%d not ready\n", num);
- return 1;
- }
-
- debug ("Stautus of device check: %d\n", status);
-
- writeb (0x00, port[num].ioaddr.feature_addr);
-
- writeb (0x00, port[num].ioaddr.nsect_addr);
- writeb (0x00, port[num].ioaddr.lbal_addr);
- writeb (0x00, port[num].ioaddr.lbam_addr);
- writeb (0x00, port[num].ioaddr.lbah_addr);
-
- writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
- writeb (ATA_CMD_IDLE, port[num].ioaddr.command_addr);
-
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 30000, 0);
- if ((status & (ATA_BUSY | ATA_ERR))) {
- printf ("Error waiting for disk spin up: status 0x%02x\n",
- status);
- port[num].dev_mask &= ~0x01;
- return 1;
- }
-
- /* Wait for disk to enter Active state */
- do {
- msleep (10);
- status = check_power_mode (num);
- } while ((status == 0x00) || (status == 0x80));
-
- if (status == 0x01) {
- printf ("Falied waiting for disk to spin up\n");
- return 1;
- }
-
- return 0;
-}
-
-/* Return value is not the usual here
- * 0x00 - Device stand by
- * 0x01 - Operation failed
- * 0x80 - Device idle
- * 0xff - Device active
-*/
-static u8 check_power_mode (int num)
-{
- u8 status = 0;
- u8 res = 0;
- if (!(port[num].dev_mask & 0x01)) {
- debug ("Device ata%d is not present\n", num);
- return 1;
- }
-
- if (!(sata_chk_status (&port[num].ioaddr, 0) & ATA_DRDY)) {
- printf ("Device ata%d not ready\n", num);
- return 1;
- }
-
- writeb (0, port[num].ioaddr.feature_addr);
- writeb (0, port[num].ioaddr.nsect_addr);
- writeb (0, port[num].ioaddr.lbal_addr);
- writeb (0, port[num].ioaddr.lbam_addr);
- writeb (0, port[num].ioaddr.lbah_addr);
-
- writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
- writeb (ATA_CMD_CHK_POWER, port[num].ioaddr.command_addr);
-
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000, 0);
- if ((status & (ATA_BUSY | ATA_ERR))) {
- printf
- ("Error waiting for check power mode complete : status 0x%02x\n",
- status);
- port[num].dev_mask &= ~0x01;
- return 1;
- }
- res = readb (port[num].ioaddr.nsect_addr);
- debug ("Check powermode: %d\n", res);
- return res;
-
-}
-
-static void sata_port (struct sata_ioports *ioport)
-{
- ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA;
- ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR;
- ioport->feature_addr = ioport->cmd_addr + ATA_REG_FEATURE;
- ioport->nsect_addr = ioport->cmd_addr + ATA_REG_NSECT;
- ioport->lbal_addr = ioport->cmd_addr + ATA_REG_LBAL;
- ioport->lbam_addr = ioport->cmd_addr + ATA_REG_LBAM;
- ioport->lbah_addr = ioport->cmd_addr + ATA_REG_LBAH;
- ioport->device_addr = ioport->cmd_addr + ATA_REG_DEVICE;
- ioport->status_addr = ioport->cmd_addr + ATA_REG_STATUS;
- ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD;
-}
-
-static u8 wait_for_irq (int num, unsigned int max)
-{
-
- u32 port = iobase[5];
- switch (num) {
- case 0:
- port += VND_TF_CNST_CH0;
- break;
- case 1:
- port += VND_TF_CNST_CH1;
- break;
- case 2:
- port += VND_TF_CNST_CH2;
- break;
- case 3:
- port += VND_TF_CNST_CH3;
- break;
- default:
- return 1;
- }
-
- do {
- if (readl (port) & VND_TF_CNST_INTST) {
- break;
- }
- udelay (1000);
- max--;
- } while ((max > 0));
-
- return (max == 0);
-}
-
-static u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits,
- unsigned int max, u8 usealtstatus)
-{
- u8 status;
-
- do {
- if (!((status = sata_chk_status (ioaddr, usealtstatus)) & bits)) {
- break;
- }
- udelay (1000);
- max--;
- } while ((status & bits) && (max > 0));
-
- return status;
-}
-
-static u8 sata_chk_status (struct sata_ioports *ioaddr, u8 usealtstatus)
-{
- if (!usealtstatus) {
- return readb (ioaddr->status_addr);
- } else {
- return readb (ioaddr->altstatus_addr);
- }
-}
-
-static void msleep (int count)
-{
- int i;
-
- for (i = 0; i < count; i++)
- udelay (1000);
-}
-
-/* Read up to 255 sectors
- *
- * Returns sectors read
-*/
-static u8 do_one_read (int device, ulong block, u8 blkcnt, u16 * buff,
- uchar lba48)
-{
-
- u8 sr = 0;
- u8 status;
- u64 blknr = (u64) block;
-
- if (!(sata_chk_status (&port[device].ioaddr, 0) & ATA_DRDY)) {
- printf ("Device ata%d not ready\n", device);
- return 0;
- }
-
- /* Set up transfer */
-#ifdef CONFIG_LBA48
- if (lba48) {
- /* write high bits */
- writeb (0, port[device].ioaddr.nsect_addr);
- writeb ((blknr >> 24) & 0xFF, port[device].ioaddr.lbal_addr);
- writeb ((blknr >> 32) & 0xFF, port[device].ioaddr.lbam_addr);
- writeb ((blknr >> 40) & 0xFF, port[device].ioaddr.lbah_addr);
- }
-#endif
- writeb (blkcnt, port[device].ioaddr.nsect_addr);
- writeb (((blknr) >> 0) & 0xFF, port[device].ioaddr.lbal_addr);
- writeb ((blknr >> 8) & 0xFF, port[device].ioaddr.lbam_addr);
- writeb ((blknr >> 16) & 0xFF, port[device].ioaddr.lbah_addr);
-
-#ifdef CONFIG_LBA48
- if (lba48) {
- writeb (ATA_LBA, port[device].ioaddr.device_addr);
- writeb (ATA_CMD_PIO_READ_EXT, port[device].ioaddr.command_addr);
- } else
-#endif
- {
- writeb (ATA_LBA | ((blknr >> 24) & 0xF),
- port[device].ioaddr.device_addr);
- writeb (ATA_CMD_PIO_READ, port[device].ioaddr.command_addr);
- }
-
- status = sata_busy_wait (&port[device].ioaddr, ATA_BUSY, 10000, 1);
-
- if (status & ATA_BUSY) {
- u8 err = 0;
-
- printf ("Device %d not responding status %d\n", device, status);
- err = readb (port[device].ioaddr.error_addr);
- printf ("Error reg = 0x%x\n", err);
-
- return (sr);
- }
- while (blkcnt--) {
-
- if (wait_for_irq (device, 500)) {
- printf ("ata%u irq failed\n", device);
- return sr;
- }
-
- status = sata_chk_status (&port[device].ioaddr, 0);
- if (status & ATA_ERR) {
- printf ("ata%u error %d\n", device,
- readb (port[device].ioaddr.error_addr));
- return sr;
- }
- /* Read one sector */
- input_data (&port[device].ioaddr, buff, ATA_SECTOR_WORDS);
- buff += ATA_SECTOR_WORDS;
- sr++;
-
- }
- return sr;
-}
-
-ulong sata_read (int device, ulong block, lbaint_t blkcnt, void *buff)
-{
- ulong n = 0, sread;
- u16 *buffer = (u16 *) buff;
- u8 status = 0;
- u64 blknr = (u64) block;
- unsigned char lba48 = 0;
-
-#ifdef CONFIG_LBA48
- if (blknr > 0xfffffff) {
- if (!sata_dev_desc[device].lba48) {
- printf ("Drive doesn't support 48-bit addressing\n");
- return 0;
- }
- /* more than 28 bits used, use 48bit mode */
- lba48 = 1;
- }
-#endif
-
- while (blkcnt > 0) {
-
- if (blkcnt > 255) {
- sread = 255;
- } else {
- sread = blkcnt;
- }
-
- status = do_one_read (device, blknr, sread, buffer, lba48);
- if (status != sread) {
- printf ("Read failed\n");
- return n;
- }
-
- blkcnt -= sread;
- blknr += sread;
- n += sread;
- buffer += sread * ATA_SECTOR_WORDS;
- }
- return n;
-}
-
-ulong sata_write (int device, ulong block, lbaint_t blkcnt, const void *buff)
-{
- ulong n = 0;
- u16 *buffer = (u16 *) buff;
- unsigned char status = 0, num = 0;
- u64 blknr = (u64) block;
-#ifdef CONFIG_LBA48
- unsigned char lba48 = 0;
-
- if (blknr > 0xfffffff) {
- if (!sata_dev_desc[device].lba48) {
- printf ("Drive doesn't support 48-bit addressing\n");
- return 0;
- }
- /* more than 28 bits used, use 48bit mode */
- lba48 = 1;
- }
-#endif
- /*Port Number */
- num = device;
-
- while (blkcnt-- > 0) {
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500, 0);
- if (status & ATA_BUSY) {
- printf ("ata%u failed to respond\n", port[num].port_no);
- return n;
- }
-#ifdef CONFIG_LBA48
- if (lba48) {
- /* write high bits */
- writeb (0, port[num].ioaddr.nsect_addr);
- writeb ((blknr >> 24) & 0xFF,
- port[num].ioaddr.lbal_addr);
- writeb ((blknr >> 32) & 0xFF,
- port[num].ioaddr.lbam_addr);
- writeb ((blknr >> 40) & 0xFF,
- port[num].ioaddr.lbah_addr);
- }
-#endif
- writeb (1, port[num].ioaddr.nsect_addr);
- writeb ((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr);
- writeb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
- writeb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
-#ifdef CONFIG_LBA48
- if (lba48) {
- writeb (ATA_LBA, port[num].ioaddr.device_addr);
- writeb (ATA_CMD_PIO_WRITE_EXT, port[num].ioaddr.command_addr);
- } else
-#endif
- {
- writeb (ATA_LBA | ((blknr >> 24) & 0xF),
- port[num].ioaddr.device_addr);
- writeb (ATA_CMD_PIO_WRITE, port[num].ioaddr.command_addr);
- }
-
- msleep (50);
- /*may take up to 4 sec */
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000, 0);
- if ((status & (ATA_DRQ | ATA_BUSY | ATA_ERR)) != ATA_DRQ) {
- printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
- device, (ulong) blknr, status);
- return (n);
- }
-
- output_data (&port[num].ioaddr, buffer, ATA_SECTOR_WORDS);
- readb (port[num].ioaddr.altstatus_addr);
- udelay (50);
-
- ++n;
- ++blknr;
- buffer += ATA_SECTOR_WORDS;
- }
- return n;
-}
-
-/* Driver implementation */
-static u8 sil_get_device_cache_line (pci_dev_t pdev)
-{
- u8 cache_line = 0;
- pci_read_config_byte (pdev, PCI_CACHE_LINE_SIZE, &cache_line);
- return cache_line;
-}
-
-int init_sata (int dev)
-{
- static u8 init_done = 0;
- static int res = 1;
- pci_dev_t devno;
- u8 cls = 0;
- u16 cmd = 0;
- u32 sconf = 0;
-
- if (init_done) {
- return res;
- }
-
- init_done = 1;
-
- if ((devno = pci_find_device (SIL_VEND_ID, SIL3114_DEVICE_ID, 0)) == -1) {
- res = 1;
- return res;
- }
-
- /* Read out all BARs, even though we only use MMIO from BAR5 */
- pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase[0]);
- pci_read_config_dword (devno, PCI_BASE_ADDRESS_1, &iobase[1]);
- pci_read_config_dword (devno, PCI_BASE_ADDRESS_2, &iobase[2]);
- pci_read_config_dword (devno, PCI_BASE_ADDRESS_3, &iobase[3]);
- pci_read_config_dword (devno, PCI_BASE_ADDRESS_4, &iobase[4]);
- pci_read_config_dword (devno, PCI_BASE_ADDRESS_5, &iobase[5]);
-
- if ((iobase[0] == 0xFFFFFFFF) || (iobase[1] == 0xFFFFFFFF) ||
- (iobase[2] == 0xFFFFFFFF) || (iobase[3] == 0xFFFFFFFF) ||
- (iobase[4] == 0xFFFFFFFF) || (iobase[5] == 0xFFFFFFFF)) {
- printf ("Error no base addr for SATA controller\n");
- res = 1;
- return res;
- }
-
- /* mask off unused bits */
- iobase[0] &= 0xfffffffc;
- iobase[1] &= 0xfffffff8;
- iobase[2] &= 0xfffffffc;
- iobase[3] &= 0xfffffff8;
- iobase[4] &= 0xfffffff0;
- iobase[5] &= 0xfffffc00;
-
- /* from sata_sil in Linux kernel */
- cls = sil_get_device_cache_line (devno);
- if (cls) {
- cls >>= 3;
- cls++; /* cls = (line_size/8)+1 */
- writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH0);
- writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH1);
- writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH2);
- writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH3);
- } else {
- printf ("Cache line not set. Driver may not function\n");
- }
-
- /* Enable operation */
- pci_read_config_word (devno, PCI_COMMAND, &cmd);
- cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
- pci_write_config_word (devno, PCI_COMMAND, cmd);
-
- /* Disable interrupt usage */
- pci_read_config_dword (devno, VND_SYSCONFSTAT, &sconf);
- sconf |= (VND_SYSCONFSTAT_CHN_0_INTBLOCK | VND_SYSCONFSTAT_CHN_1_INTBLOCK);
- pci_write_config_dword (devno, VND_SYSCONFSTAT, sconf);
-
- res = 0;
- return res;
-}
-
-/* Check if device is connected to port */
-int sata_bus_probe (int portno)
-{
- u32 port = iobase[5];
- u32 val;
- switch (portno) {
- case 0:
- port += VND_SSTATUS_CH0;
- break;
- case 1:
- port += VND_SSTATUS_CH1;
- break;
- case 2:
- port += VND_SSTATUS_CH2;
- break;
- case 3:
- port += VND_SSTATUS_CH3;
- break;
- default:
- return 0;
- }
- val = readl (port);
- if ((val & SATA_DET_PRES) == SATA_DET_PRES) {
- return 1;
- } else {
- return 0;
- }
-}
-
-int sata_phy_reset (int portno)
-{
- u32 port = iobase[5];
- u32 val;
- switch (portno) {
- case 0:
- port += VND_SCONTROL_CH0;
- break;
- case 1:
- port += VND_SCONTROL_CH1;
- break;
- case 2:
- port += VND_SCONTROL_CH2;
- break;
- case 3:
- port += VND_SCONTROL_CH3;
- break;
- default:
- return 0;
- }
- val = readl (port);
- writel (val | SATA_SC_DET_RST, port);
- msleep (150);
- writel (val & ~SATA_SC_DET_RST, port);
- return 0;
-}
-
-int scan_sata (int dev)
-{
- /* A bit brain dead, but the code has a legacy */
- switch (dev) {
- case 0:
- port[0].port_no = 0;
- port[0].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH0;
- port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr =
- (iobase[5] + VND_TF2_CH0) | ATA_PCI_CTL_OFS;
- port[0].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH0;
- break;
- case 1:
- port[1].port_no = 0;
- port[1].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH1;
- port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr =
- (iobase[5] + VND_TF2_CH1) | ATA_PCI_CTL_OFS;
- port[1].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH1;
- break;
- case 2:
- port[2].port_no = 0;
- port[2].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH2;
- port[2].ioaddr.altstatus_addr = port[2].ioaddr.ctl_addr =
- (iobase[5] + VND_TF2_CH2) | ATA_PCI_CTL_OFS;
- port[2].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH2;
- break;
- case 3:
- port[3].port_no = 0;
- port[3].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH3;
- port[3].ioaddr.altstatus_addr = port[3].ioaddr.ctl_addr =
- (iobase[5] + VND_TF2_CH3) | ATA_PCI_CTL_OFS;
- port[3].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH3;
- break;
- default:
- printf ("Tried to scan unknown port: ata%d\n", dev);
- return 1;
- }
-
- /* Initialize other registers */
- sata_port (&port[dev].ioaddr);
-
- /* Check for attached device */
- if (!sata_bus_probe (dev)) {
- port[dev].port_state = 0;
- debug ("SATA#%d port is not present\n", dev);
- } else {
- debug ("SATA#%d port is present\n", dev);
- if (sata_bus_softreset (dev)) {
- /* soft reset failed, try a hard one */
- sata_phy_reset (dev);
- if (sata_bus_softreset (dev)) {
- port[dev].port_state = 0;
- } else {
- port[dev].port_state = 1;
- }
- } else {
- port[dev].port_state = 1;
- }
- }
- if (port[dev].port_state == 1) {
- /* Probe device and set xfer mode */
- sata_identify (dev, 0);
- set_Feature_cmd (dev, 0);
- }
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) Excito Elektronik i Skåne AB, All rights reserved.
- * Author: Tor Krill <tor@excito.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef SATA_SIL3114_H
-#define SATA_SIL3114_H
-
-struct sata_ioports {
- unsigned long cmd_addr;
- unsigned long data_addr;
- unsigned long error_addr;
- unsigned long feature_addr;
- unsigned long nsect_addr;
- unsigned long lbal_addr;
- unsigned long lbam_addr;
- unsigned long lbah_addr;
- unsigned long device_addr;
- unsigned long status_addr;
- unsigned long command_addr;
- unsigned long altstatus_addr;
- unsigned long ctl_addr;
- unsigned long bmdma_addr;
- unsigned long scr_addr;
-};
-
-struct sata_port {
- unsigned char port_no; /* primary=0, secondary=1 */
- struct sata_ioports ioaddr; /* ATA cmd/ctl/dma reg blks */
- unsigned char ctl_reg;
- unsigned char last_ctl;
- unsigned char port_state; /* 1-port is available and */
- /* 0-port is not available */
- unsigned char dev_mask;
-};
-
-/* Missing ata defines */
-#define ATA_CMD_STANDBY 0xE2
-#define ATA_CMD_STANDBYNOW1 0xE0
-#define ATA_CMD_IDLE 0xE3
-#define ATA_CMD_IDLEIMMEDIATE 0xE1
-
-/* Defines for SIL3114 chip */
-
-/* PCI defines */
-#define SIL_VEND_ID 0x1095
-#define SIL3114_DEVICE_ID 0x3114
-
-/* some vendor specific registers */
-#define VND_SYSCONFSTAT 0x88 /* System Configuration Status and Command */
-#define VND_SYSCONFSTAT_CHN_0_INTBLOCK (1<<22)
-#define VND_SYSCONFSTAT_CHN_1_INTBLOCK (1<<23)
-#define VND_SYSCONFSTAT_CHN_2_INTBLOCK (1<<24)
-#define VND_SYSCONFSTAT_CHN_3_INTBLOCK (1<<25)
-
-/* internal registers mapped by BAR5 */
-/* SATA Control*/
-#define VND_SCONTROL_CH0 0x100
-#define VND_SCONTROL_CH1 0x180
-#define VND_SCONTROL_CH2 0x300
-#define VND_SCONTROL_CH3 0x380
-
-#define SATA_SC_IPM_T2P (1<<16)
-#define SATA_SC_IPM_T2S (2<<16)
-#define SATA_SC_SPD_1_5 (1<<4)
-#define SATA_SC_SPD_3_0 (2<<4)
-#define SATA_SC_DET_RST (1) /* ATA Reset sequence */
-#define SATA_SC_DET_PDIS (4) /* PHY Disable */
-
-/* SATA Status */
-#define VND_SSTATUS_CH0 0x104
-#define VND_SSTATUS_CH1 0x184
-#define VND_SSTATUS_CH2 0x304
-#define VND_SSTATUS_CH3 0x384
-
-#define SATA_SS_IPM_ACTIVE (1<<8)
-#define SATA_SS_IPM_PARTIAL (2<<8)
-#define SATA_SS_IPM_SLUMBER (6<<8)
-#define SATA_SS_SPD_1_5 (1<<4)
-#define SATA_SS_SPD_3_0 (2<<4)
-#define SATA_DET_P_NOPHY (1) /* Device presence but no PHY connection established */
-#define SATA_DET_PRES (3) /* Device presence and active PHY */
-#define SATA_DET_OFFLINE (4) /* Device offline or in loopback mode */
-
-/* Task file registers in BAR5 mapping */
-#define VND_TF0_CH0 0x80
-#define VND_TF0_CH1 0xc0
-#define VND_TF0_CH2 0x280
-#define VND_TF0_CH3 0x2c0
-#define VND_TF1_CH0 0x88
-#define VND_TF1_CH1 0xc8
-#define VND_TF1_CH2 0x288
-#define VND_TF1_CH3 0x2c8
-#define VND_TF2_CH0 0x88
-#define VND_TF2_CH1 0xc8
-#define VND_TF2_CH2 0x288
-#define VND_TF2_CH3 0x2c8
-
-#define VND_BMDMA_CH0 0x00
-#define VND_BMDMA_CH1 0x08
-#define VND_BMDMA_CH2 0x200
-#define VND_BMDMA_CH3 0x208
-#define VND_BMDMA2_CH0 0x10
-#define VND_BMDMA2_CH1 0x18
-#define VND_BMDMA2_CH2 0x210
-#define VND_BMDMA2_CH3 0x218
-
-/* FIFO control */
-#define VND_FIFOCFG_CH0 0x40
-#define VND_FIFOCFG_CH1 0x44
-#define VND_FIFOCFG_CH2 0x240
-#define VND_FIFOCFG_CH3 0x244
-
-/* Task File configuration and status */
-#define VND_TF_CNST_CH0 0xa0
-#define VND_TF_CNST_CH1 0xe0
-#define VND_TF_CNST_CH2 0x2a0
-#define VND_TF_CNST_CH3 0x2e0
-
-#define VND_TF_CNST_BFCMD (1<<1)
-#define VND_TF_CNST_CHNRST (1<<2)
-#define VND_TF_CNST_VDMA (1<<10)
-#define VND_TF_CNST_INTST (1<<11)
-#define VND_TF_CNST_WDTO (1<<12)
-#define VND_TF_CNST_WDEN (1<<13)
-#define VND_TF_CNST_WDIEN (1<<14)
-
-/* for testing */
-#define VND_SSDR 0x04c /* System Software Data Register */
-#define VND_FMACS 0x050 /* Flash Memory Address control and status */
-
-#endif
+++ /dev/null
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
- * Copyright 2009 Ilya Yanok, <yanok@emcraft.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <common.h>
-#include <nand.h>
-#include <linux/err.h>
-#include <asm/io.h>
-#ifdef CONFIG_MX27
-#include <asm/arch/imx-regs.h>
-#endif
-
-#define DRIVER_NAME "mxc_nand"
-
-struct nfc_regs {
-/* NFC RAM BUFFER Main area 0 */
- uint8_t main_area0[0x200];
- uint8_t main_area1[0x200];
- uint8_t main_area2[0x200];
- uint8_t main_area3[0x200];
-/* SPARE BUFFER Spare area 0 */
- uint8_t spare_area0[0x10];
- uint8_t spare_area1[0x10];
- uint8_t spare_area2[0x10];
- uint8_t spare_area3[0x10];
- uint8_t pad[0x5c0];
-/* NFC registers */
- uint16_t nfc_buf_size;
- uint16_t reserved;
- uint16_t nfc_buf_addr;
- uint16_t nfc_flash_addr;
- uint16_t nfc_flash_cmd;
- uint16_t nfc_config;
- uint16_t nfc_ecc_status_result;
- uint16_t nfc_rsltmain_area;
- uint16_t nfc_rsltspare_area;
- uint16_t nfc_wrprot;
- uint16_t nfc_unlockstart_blkaddr;
- uint16_t nfc_unlockend_blkaddr;
- uint16_t nfc_nf_wrprst;
- uint16_t nfc_config1;
- uint16_t nfc_config2;
-};
-
-/*
- * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
- * for Command operation
- */
-#define NFC_CMD 0x1
-
-/*
- * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register
- * for Address operation
- */
-#define NFC_ADDR 0x2
-
-/*
- * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register
- * for Input operation
- */
-#define NFC_INPUT 0x4
-
-/*
- * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register
- * for Data Output operation
- */
-#define NFC_OUTPUT 0x8
-
-/*
- * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register
- * for Read ID operation
- */
-#define NFC_ID 0x10
-
-/*
- * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register
- * for Read Status operation
- */
-#define NFC_STATUS 0x20
-
-/*
- * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read
- * Status operation
- */
-#define NFC_INT 0x8000
-
-#define NFC_SP_EN (1 << 2)
-#define NFC_ECC_EN (1 << 3)
-#define NFC_BIG (1 << 5)
-#define NFC_RST (1 << 6)
-#define NFC_CE (1 << 7)
-#define NFC_ONE_CYCLE (1 << 8)
-
-typedef enum {false, true} bool;
-
-struct mxc_nand_host {
- struct mtd_info mtd;
- struct nand_chip *nand;
-
- struct nfc_regs __iomem *regs;
- int spare_only;
- int status_request;
- int pagesize_2k;
- int clk_act;
- uint16_t col_addr;
-};
-
-static struct mxc_nand_host mxc_host;
-static struct mxc_nand_host *host = &mxc_host;
-
-/* Define delays in microsec for NAND device operations */
-#define TROP_US_DELAY 2000
-/* Macros to get byte and bit positions of ECC */
-#define COLPOS(x) ((x) >> 3)
-#define BITPOS(x) ((x) & 0xf)
-
-/* Define single bit Error positions in Main & Spare area */
-#define MAIN_SINGLEBIT_ERROR 0x4
-#define SPARE_SINGLEBIT_ERROR 0x1
-
-/* OOB placement block for use with hardware ecc generation */
-#ifdef CONFIG_MXC_NAND_HWECC
-static struct nand_ecclayout nand_hw_eccoob = {
- .eccbytes = 5,
- .eccpos = {6, 7, 8, 9, 10},
- .oobfree = {{0, 5}, {11, 5}, }
-};
-#else
-static struct nand_ecclayout nand_soft_eccoob = {
- .eccbytes = 6,
- .eccpos = {6, 7, 8, 9, 10, 11},
- .oobfree = {{0, 5}, {12, 4}, }
-};
-#endif
-
-static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size)
-{
- uint32_t *d = dest;
-
- size >>= 2;
- while (size--)
- __raw_writel(__raw_readl(source++), d++);
- return dest;
-}
-
-/*
- * This function polls the NANDFC to wait for the basic operation to
- * complete by checking the INT bit of config2 register.
- */
-static void wait_op_done(struct mxc_nand_host *host, int max_retries,
- uint16_t param)
-{
- uint32_t tmp;
-
- while (max_retries-- > 0) {
- if (readw(&host->regs->nfc_config2) & NFC_INT) {
- tmp = readw(&host->regs->nfc_config2);
- tmp &= ~NFC_INT;
- writew(tmp, &host->regs->nfc_config2);
- break;
- }
- udelay(1);
- }
- if (max_retries < 0) {
- MTDDEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n",
- __func__, param);
- }
-}
-
-/*
- * This function issues the specified command to the NAND device and
- * waits for completion.
- */
-static void send_cmd(struct mxc_nand_host *host, uint16_t cmd)
-{
- MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd);
-
- writew(cmd, &host->regs->nfc_flash_cmd);
- writew(NFC_CMD, &host->regs->nfc_config2);
-
- /* Wait for operation to complete */
- wait_op_done(host, TROP_US_DELAY, cmd);
-}
-
-/*
- * This function sends an address (or partial address) to the
- * NAND device. The address is used to select the source/destination for
- * a NAND command.
- */
-static void send_addr(struct mxc_nand_host *host, uint16_t addr)
-{
- MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr);
-
- writew(addr, &host->regs->nfc_flash_addr);
- writew(NFC_ADDR, &host->regs->nfc_config2);
-
- /* Wait for operation to complete */
- wait_op_done(host, TROP_US_DELAY, addr);
-}
-
-/*
- * This function requests the NANDFC to initate the transfer
- * of data currently in the NANDFC RAM buffer to the NAND device.
- */
-static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
- int spare_only)
-{
- MTDDEBUG(MTD_DEBUG_LEVEL3, "send_prog_page (%d)\n", spare_only);
-
- writew(buf_id, &host->regs->nfc_buf_addr);
-
- /* Configure spare or page+spare access */
- if (!host->pagesize_2k) {
- uint16_t config1 = readw(&host->regs->nfc_config1);
- if (spare_only)
- config1 |= NFC_SP_EN;
- else
- config1 &= ~(NFC_SP_EN);
- writew(config1, &host->regs->nfc_config1);
- }
-
- writew(NFC_INPUT, &host->regs->nfc_config2);
-
- /* Wait for operation to complete */
- wait_op_done(host, TROP_US_DELAY, spare_only);
-}
-
-/*
- * Requests NANDFC to initated the transfer of data from the
- * NAND device into in the NANDFC ram buffer.
- */
-static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
- int spare_only)
-{
- MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
-
- writew(buf_id, &host->regs->nfc_buf_addr);
-
- /* Configure spare or page+spare access */
- if (!host->pagesize_2k) {
- uint32_t config1 = readw(&host->regs->nfc_config1);
- if (spare_only)
- config1 |= NFC_SP_EN;
- else
- config1 &= ~NFC_SP_EN;
- writew(config1, &host->regs->nfc_config1);
- }
-
- writew(NFC_OUTPUT, &host->regs->nfc_config2);
-
- /* Wait for operation to complete */
- wait_op_done(host, TROP_US_DELAY, spare_only);
-}
-
-/* Request the NANDFC to perform a read of the NAND device ID. */
-static void send_read_id(struct mxc_nand_host *host)
-{
- uint16_t tmp;
-
- /* NANDFC buffer 0 is used for device ID output */
- writew(0x0, &host->regs->nfc_buf_addr);
-
- /* Read ID into main buffer */
- tmp = readw(&host->regs->nfc_config1);
- tmp &= ~NFC_SP_EN;
- writew(tmp, &host->regs->nfc_config1);
-
- writew(NFC_ID, &host->regs->nfc_config2);
-
- /* Wait for operation to complete */
- wait_op_done(host, TROP_US_DELAY, 0);
-}
-
-/*
- * This function requests the NANDFC to perform a read of the
- * NAND device status and returns the current status.
- */
-static uint16_t get_dev_status(struct mxc_nand_host *host)
-{
- void __iomem *main_buf = host->regs->main_area1;
- uint32_t store;
- uint16_t ret, tmp;
- /* Issue status request to NAND device */
-
- /* store the main area1 first word, later do recovery */
- store = readl(main_buf);
- /* NANDFC buffer 1 is used for device status */
- writew(1, &host->regs->nfc_buf_addr);
-
- /* Read status into main buffer */
- tmp = readw(&host->regs->nfc_config1);
- tmp &= ~NFC_SP_EN;
- writew(tmp, &host->regs->nfc_config1);
-
- writew(NFC_STATUS, &host->regs->nfc_config2);
-
- /* Wait for operation to complete */
- wait_op_done(host, TROP_US_DELAY, 0);
-
- /*
- * Status is placed in first word of main buffer
- * get status, then recovery area 1 data
- */
- ret = readw(main_buf);
- writel(store, main_buf);
-
- return ret;
-}
-
-/* This function is used by upper layer to checks if device is ready */
-static int mxc_nand_dev_ready(struct mtd_info *mtd)
-{
- /*
- * NFC handles R/B internally. Therefore, this function
- * always returns status as ready.
- */
- return 1;
-}
-
-#ifdef CONFIG_MXC_NAND_HWECC
-static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
-{
- /*
- * If HW ECC is enabled, we turn it on during init. There is
- * no need to enable again here.
- */
-}
-
-static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
- u_char *read_ecc, u_char *calc_ecc)
-{
- struct nand_chip *nand_chip = mtd->priv;
- struct mxc_nand_host *host = nand_chip->priv;
-
- /*
- * 1-Bit errors are automatically corrected in HW. No need for
- * additional correction. 2-Bit errors cannot be corrected by
- * HW ECC, so we need to return failure
- */
- uint16_t ecc_status = readw(&host->regs->nfc_ecc_status_result);
-
- if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
- MTDDEBUG(MTD_DEBUG_LEVEL0,
- "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
- return -1;
- }
-
- return 0;
-}
-
-static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
- u_char *ecc_code)
-{
- return 0;
-}
-#endif
-
-static u_char mxc_nand_read_byte(struct mtd_info *mtd)
-{
- struct nand_chip *nand_chip = mtd->priv;
- struct mxc_nand_host *host = nand_chip->priv;
- uint8_t ret = 0;
- uint16_t col;
- uint16_t __iomem *main_buf =
- (uint16_t __iomem *)host->regs->main_area0;
- uint16_t __iomem *spare_buf =
- (uint16_t __iomem *)host->regs->spare_area0;
- union {
- uint16_t word;
- uint8_t bytes[2];
- } nfc_word;
-
- /* Check for status request */
- if (host->status_request)
- return get_dev_status(host) & 0xFF;
-
- /* Get column for 16-bit access */
- col = host->col_addr >> 1;
-
- /* If we are accessing the spare region */
- if (host->spare_only)
- nfc_word.word = readw(&spare_buf[col]);
- else
- nfc_word.word = readw(&main_buf[col]);
-
- /* Pick upper/lower byte of word from RAM buffer */
- ret = nfc_word.bytes[host->col_addr & 0x1];
-
- /* Update saved column address */
- if (nand_chip->options & NAND_BUSWIDTH_16)
- host->col_addr += 2;
- else
- host->col_addr++;
-
- return ret;
-}
-
-static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
-{
- struct nand_chip *nand_chip = mtd->priv;
- struct mxc_nand_host *host = nand_chip->priv;
- uint16_t col, ret;
- uint16_t __iomem *p;
-
- MTDDEBUG(MTD_DEBUG_LEVEL3,
- "mxc_nand_read_word(col = %d)\n", host->col_addr);
-
- col = host->col_addr;
- /* Adjust saved column address */
- if (col < mtd->writesize && host->spare_only)
- col += mtd->writesize;
-
- if (col < mtd->writesize) {
- p = (uint16_t __iomem *)(host->regs->main_area0 + (col >> 1));
- } else {
- p = (uint16_t __iomem *)(host->regs->spare_area0 +
- ((col - mtd->writesize) >> 1));
- }
-
- if (col & 1) {
- union {
- uint16_t word;
- uint8_t bytes[2];
- } nfc_word[3];
-
- nfc_word[0].word = readw(p);
- nfc_word[1].word = readw(p + 1);
-
- nfc_word[2].bytes[0] = nfc_word[0].bytes[1];
- nfc_word[2].bytes[1] = nfc_word[1].bytes[0];
-
- ret = nfc_word[2].word;
- } else {
- ret = readw(p);
- }
-
- /* Update saved column address */
- host->col_addr = col + 2;
-
- return ret;
-}
-
-/*
- * Write data of length len to buffer buf. The data to be
- * written on NAND Flash is first copied to RAMbuffer. After the Data Input
- * Operation by the NFC, the data is written to NAND Flash
- */
-static void mxc_nand_write_buf(struct mtd_info *mtd,
- const u_char *buf, int len)
-{
- struct nand_chip *nand_chip = mtd->priv;
- struct mxc_nand_host *host = nand_chip->priv;
- int n, col, i = 0;
-
- MTDDEBUG(MTD_DEBUG_LEVEL3,
- "mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
- len);
-
- col = host->col_addr;
-
- /* Adjust saved column address */
- if (col < mtd->writesize && host->spare_only)
- col += mtd->writesize;
-
- n = mtd->writesize + mtd->oobsize - col;
- n = min(len, n);
-
- MTDDEBUG(MTD_DEBUG_LEVEL3,
- "%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
-
- while (n > 0) {
- void __iomem *p;
-
- if (col < mtd->writesize) {
- p = host->regs->main_area0 + (col & ~3);
- } else {
- p = host->regs->spare_area0 -
- mtd->writesize + (col & ~3);
- }
-
- MTDDEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __func__,
- __LINE__, p);
-
- if (((col | (unsigned long)&buf[i]) & 3) || n < 4) {
- union {
- uint32_t word;
- uint8_t bytes[4];
- } nfc_word;
-
- nfc_word.word = readl(p);
- nfc_word.bytes[col & 3] = buf[i++];
- n--;
- col++;
-
- writel(nfc_word.word, p);
- } else {
- int m = mtd->writesize - col;
-
- if (col >= mtd->writesize)
- m += mtd->oobsize;
-
- m = min(n, m) & ~3;
-
- MTDDEBUG(MTD_DEBUG_LEVEL3,
- "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
- __func__, __LINE__, n, m, i, col);
-
- mxc_nand_memcpy32(p, (uint32_t *)&buf[i], m);
- col += m;
- i += m;
- n -= m;
- }
- }
- /* Update saved column address */
- host->col_addr = col;
-}
-
-/*
- * Read the data buffer from the NAND Flash. To read the data from NAND
- * Flash first the data output cycle is initiated by the NFC, which copies
- * the data to RAMbuffer. This data of length len is then copied to buffer buf.
- */
-static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
-{
- struct nand_chip *nand_chip = mtd->priv;
- struct mxc_nand_host *host = nand_chip->priv;
- int n, col, i = 0;
-
- MTDDEBUG(MTD_DEBUG_LEVEL3,
- "mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr, len);
-
- col = host->col_addr;
-
- /* Adjust saved column address */
- if (col < mtd->writesize && host->spare_only)
- col += mtd->writesize;
-
- n = mtd->writesize + mtd->oobsize - col;
- n = min(len, n);
-
- while (n > 0) {
- void __iomem *p;
-
- if (col < mtd->writesize) {
- p = host->regs->main_area0 + (col & ~3);
- } else {
- p = host->regs->spare_area0 -
- mtd->writesize + (col & ~3);
- }
-
- if (((col | (int)&buf[i]) & 3) || n < 4) {
- union {
- uint32_t word;
- uint8_t bytes[4];
- } nfc_word;
-
- nfc_word.word = readl(p);
- buf[i++] = nfc_word.bytes[col & 3];
- n--;
- col++;
- } else {
- int m = mtd->writesize - col;
-
- if (col >= mtd->writesize)
- m += mtd->oobsize;
-
- m = min(n, m) & ~3;
- mxc_nand_memcpy32((uint32_t *)&buf[i], p, m);
-
- col += m;
- i += m;
- n -= m;
- }
- }
- /* Update saved column address */
- host->col_addr = col;
-}
-
-/*
- * Used by the upper layer to verify the data in NAND Flash
- * with the data in the buf.
- */
-static int mxc_nand_verify_buf(struct mtd_info *mtd,
- const u_char *buf, int len)
-{
- u_char tmp[256];
- uint bsize;
-
- while (len) {
- bsize = min(len, 256);
- mxc_nand_read_buf(mtd, tmp, bsize);
-
- if (memcmp(buf, tmp, bsize))
- return 1;
-
- buf += bsize;
- len -= bsize;
- }
-
- return 0;
-}
-
-/*
- * This function is used by upper layer for select and
- * deselect of the NAND chip
- */
-static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
-{
- struct nand_chip *nand_chip = mtd->priv;
- struct mxc_nand_host *host = nand_chip->priv;
-
- switch (chip) {
- case -1:
- /* TODO: Disable the NFC clock */
- if (host->clk_act)
- host->clk_act = 0;
- break;
- case 0:
- /* TODO: Enable the NFC clock */
- if (!host->clk_act)
- host->clk_act = 1;
- break;
-
- default:
- break;
- }
-}
-
-/*
- * Used by the upper layer to write command to NAND Flash for
- * different operations to be carried out on NAND Flash
- */
-static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
- int column, int page_addr)
-{
- struct nand_chip *nand_chip = mtd->priv;
- struct mxc_nand_host *host = nand_chip->priv;
-
- MTDDEBUG(MTD_DEBUG_LEVEL3,
- "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
- command, column, page_addr);
-
- /* Reset command state information */
- host->status_request = false;
-
- /* Command pre-processing step */
- switch (command) {
-
- case NAND_CMD_STATUS:
- host->col_addr = 0;
- host->status_request = true;
- break;
-
- case NAND_CMD_READ0:
- host->col_addr = column;
- host->spare_only = false;
- break;
-
- case NAND_CMD_READOOB:
- host->col_addr = column;
- host->spare_only = true;
- if (host->pagesize_2k)
- command = NAND_CMD_READ0; /* only READ0 is valid */
- break;
-
- case NAND_CMD_SEQIN:
- if (column >= mtd->writesize) {
- /*
- * before sending SEQIN command for partial write,
- * we need read one page out. FSL NFC does not support
- * partial write. It alway send out 512+ecc+512+ecc ...
- * for large page nand flash. But for small page nand
- * flash, it does support SPARE ONLY operation.
- */
- if (host->pagesize_2k) {
- /* call ourself to read a page */
- mxc_nand_command(mtd, NAND_CMD_READ0, 0,
- page_addr);
- }
-
- host->col_addr = column - mtd->writesize;
- host->spare_only = true;
-
- /* Set program pointer to spare region */
- if (!host->pagesize_2k)
- send_cmd(host, NAND_CMD_READOOB);
- } else {
- host->spare_only = false;
- host->col_addr = column;
-
- /* Set program pointer to page start */
- if (!host->pagesize_2k)
- send_cmd(host, NAND_CMD_READ0);
- }
- break;
-
- case NAND_CMD_PAGEPROG:
- send_prog_page(host, 0, host->spare_only);
-
- if (host->pagesize_2k) {
- /* data in 4 areas datas */
- send_prog_page(host, 1, host->spare_only);
- send_prog_page(host, 2, host->spare_only);
- send_prog_page(host, 3, host->spare_only);
- }
-
- break;
- }
-
- /* Write out the command to the device. */
- send_cmd(host, command);
-
- /* Write out column address, if necessary */
- if (column != -1) {
- /*
- * MXC NANDFC can only perform full page+spare or
- * spare-only read/write. When the upper layers
- * layers perform a read/write buf operation,
- * we will used the saved column adress to index into
- * the full page.
- */
- send_addr(host, 0);
- if (host->pagesize_2k)
- /* another col addr cycle for 2k page */
- send_addr(host, 0);
- }
-
- /* Write out page address, if necessary */
- if (page_addr != -1) {
- /* paddr_0 - p_addr_7 */
- send_addr(host, (page_addr & 0xff));
-
- if (host->pagesize_2k) {
- send_addr(host, (page_addr >> 8) & 0xFF);
- if (mtd->size >= 0x10000000) {
- /* paddr_8 - paddr_15 */
- send_addr(host, (page_addr >> 8) & 0xff);
- send_addr(host, (page_addr >> 16) & 0xff);
- } else {
- /* paddr_8 - paddr_15 */
- send_addr(host, (page_addr >> 8) & 0xff);
- }
- } else {
- /* One more address cycle for higher density devices */
- if (mtd->size >= 0x4000000) {
- /* paddr_8 - paddr_15 */
- send_addr(host, (page_addr >> 8) & 0xff);
- send_addr(host, (page_addr >> 16) & 0xff);
- } else {
- /* paddr_8 - paddr_15 */
- send_addr(host, (page_addr >> 8) & 0xff);
- }
- }
- }
-
- /* Command post-processing step */
- switch (command) {
-
- case NAND_CMD_RESET:
- break;
-
- case NAND_CMD_READOOB:
- case NAND_CMD_READ0:
- if (host->pagesize_2k) {
- /* send read confirm command */
- send_cmd(host, NAND_CMD_READSTART);
- /* read for each AREA */
- send_read_page(host, 0, host->spare_only);
- send_read_page(host, 1, host->spare_only);
- send_read_page(host, 2, host->spare_only);
- send_read_page(host, 3, host->spare_only);
- } else {
- send_read_page(host, 0, host->spare_only);
- }
- break;
-
- case NAND_CMD_READID:
- host->col_addr = 0;
- send_read_id(host);
- break;
-
- case NAND_CMD_PAGEPROG:
- break;
-
- case NAND_CMD_STATUS:
- break;
-
- case NAND_CMD_ERASE2:
- break;
- }
-}
-
-int board_nand_init(struct nand_chip *this)
-{
- struct system_control_regs *sc_regs =
- (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
- struct mtd_info *mtd;
- uint16_t tmp;
- int err = 0;
-
- /* structures must be linked */
- mtd = &host->mtd;
- mtd->priv = this;
- host->nand = this;
-
- /* 5 us command delay time */
- this->chip_delay = 5;
-
- this->priv = host;
- this->dev_ready = mxc_nand_dev_ready;
- this->cmdfunc = mxc_nand_command;
- this->select_chip = mxc_nand_select_chip;
- this->read_byte = mxc_nand_read_byte;
- this->read_word = mxc_nand_read_word;
- this->write_buf = mxc_nand_write_buf;
- this->read_buf = mxc_nand_read_buf;
- this->verify_buf = mxc_nand_verify_buf;
-
- host->regs = (struct nfc_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
- host->clk_act = 1;
-
-#ifdef CONFIG_MXC_NAND_HWECC
- this->ecc.calculate = mxc_nand_calculate_ecc;
- this->ecc.hwctl = mxc_nand_enable_hwecc;
- this->ecc.correct = mxc_nand_correct_data;
- this->ecc.mode = NAND_ECC_HW;
- this->ecc.size = 512;
- this->ecc.bytes = 3;
- this->ecc.layout = &nand_hw_eccoob;
- tmp = readw(&host->regs->nfc_config1);
- tmp |= NFC_ECC_EN;
- writew(tmp, &host->regs->nfc_config1);
-#else
- this->ecc.layout = &nand_soft_eccoob;
- this->ecc.mode = NAND_ECC_SOFT;
- tmp = readw(&host->regs->nfc_config1);
- tmp &= ~NFC_ECC_EN;
- writew(tmp, &host->regs->nfc_config1);
-#endif
-
- /* Reset NAND */
- this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
-
- /*
- * preset operation
- * Unlock the internal RAM Buffer
- */
- writew(0x2, &host->regs->nfc_config);
-
- /* Blocks to be unlocked */
- writew(0x0, &host->regs->nfc_unlockstart_blkaddr);
- writew(0x4000, &host->regs->nfc_unlockend_blkaddr);
-
- /* Unlock Block Command for given address range */
- writew(0x4, &host->regs->nfc_wrprot);
-
- /* NAND bus width determines access funtions used by upper layer */
- if (readl(&sc_regs->fmcr) & NF_16BIT_SEL)
- this->options |= NAND_BUSWIDTH_16;
-
- host->pagesize_2k = 0;
-
- return err;
-}
+++ /dev/null
-/*
- * drivers/mtd/nand/nand_util.c
- *
- * Copyright (C) 2006 by Weiss-Electronic GmbH.
- * All rights reserved.
- *
- * @author: Guido Classen <clagix@gmail.com>
- * @descr: NAND Flash support
- * @references: borrowed heavily from Linux mtd-utils code:
- * flash_eraseall.c by Arcom Control System Ltd
- * nandwrite.c by Steven J. Hill (sjhill@realitydiluted.com)
- * and Thomas Gleixner (tglx@linutronix.de)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License version
- * 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#include <common.h>
-#include <command.h>
-#include <watchdog.h>
-#include <malloc.h>
-#include <div64.h>
-
-#include <asm/errno.h>
-#include <linux/mtd/mtd.h>
-#include <nand.h>
-#include <jffs2/jffs2.h>
-
-#if !defined(CONFIG_SYS_64BIT_VSPRINTF)
-#warning Please define CONFIG_SYS_64BIT_VSPRINTF for correct output!
-#endif
-
-typedef struct erase_info erase_info_t;
-typedef struct mtd_info mtd_info_t;
-
-/* support only for native endian JFFS2 */
-#define cpu_to_je16(x) (x)
-#define cpu_to_je32(x) (x)
-
-/*****************************************************************************/
-static int nand_block_bad_scrub(struct mtd_info *mtd, loff_t ofs, int getchip)
-{
- return 0;
-}
-
-/**
- * nand_erase_opts: - erase NAND flash with support for various options
- * (jffs2 formating)
- *
- * @param meminfo NAND device to erase
- * @param opts options, @see struct nand_erase_options
- * @return 0 in case of success
- *
- * This code is ported from flash_eraseall.c from Linux mtd utils by
- * Arcom Control System Ltd.
- */
-int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts)
-{
- struct jffs2_unknown_node cleanmarker;
- erase_info_t erase;
- ulong erase_length;
- int bbtest = 1;
- int result;
- int percent_complete = -1;
- int (*nand_block_bad_old)(struct mtd_info *, loff_t, int) = NULL;
- const char *mtd_device = meminfo->name;
- struct mtd_oob_ops oob_opts;
- struct nand_chip *chip = meminfo->priv;
-
- memset(&erase, 0, sizeof(erase));
- memset(&oob_opts, 0, sizeof(oob_opts));
-
- erase.mtd = meminfo;
- erase.len = meminfo->erasesize;
- erase.addr = opts->offset;
- erase_length = opts->length;
-
- cleanmarker.magic = cpu_to_je16 (JFFS2_MAGIC_BITMASK);
- cleanmarker.nodetype = cpu_to_je16 (JFFS2_NODETYPE_CLEANMARKER);
- cleanmarker.totlen = cpu_to_je32(8);
-
- /* scrub option allows to erase badblock. To prevent internal
- * check from erase() method, set block check method to dummy
- * and disable bad block table while erasing.
- */
- if (opts->scrub) {
- struct nand_chip *priv_nand = meminfo->priv;
-
- nand_block_bad_old = priv_nand->block_bad;
- priv_nand->block_bad = nand_block_bad_scrub;
- /* we don't need the bad block table anymore...
- * after scrub, there are no bad blocks left!
- */
- if (priv_nand->bbt) {
- kfree(priv_nand->bbt);
- }
- priv_nand->bbt = NULL;
- }
-
- if (erase_length < meminfo->erasesize) {
- printf("Warning: Erase size 0x%08lx smaller than one " \
- "erase block 0x%08x\n",erase_length, meminfo->erasesize);
- printf(" Erasing 0x%08x instead\n", meminfo->erasesize);
- erase_length = meminfo->erasesize;
- }
-
- for (;
- erase.addr < opts->offset + erase_length;
- erase.addr += meminfo->erasesize) {
-
- WATCHDOG_RESET ();
-
- if (!opts->scrub && bbtest) {
- int ret = meminfo->block_isbad(meminfo, erase.addr);
- if (ret > 0) {
- if (!opts->quiet)
- printf("\rSkipping bad block at "
- "0x%08llx "
- " \n",
- erase.addr);
- continue;
-
- } else if (ret < 0) {
- printf("\n%s: MTD get bad block failed: %d\n",
- mtd_device,
- ret);
- return -1;
- }
- }
-
- result = meminfo->erase(meminfo, &erase);
- if (result != 0) {
- printf("\n%s: MTD Erase failure: %d\n",
- mtd_device, result);
- continue;
- }
-
- /* format for JFFS2 ? */
- if (opts->jffs2 && chip->ecc.layout->oobavail >= 8) {
- chip->ops.ooblen = 8;
- chip->ops.datbuf = NULL;
- chip->ops.oobbuf = (uint8_t *)&cleanmarker;
- chip->ops.ooboffs = 0;
- chip->ops.mode = MTD_OOB_AUTO;
-
- result = meminfo->write_oob(meminfo,
- erase.addr,
- &chip->ops);
- if (result != 0) {
- printf("\n%s: MTD writeoob failure: %d\n",
- mtd_device, result);
- continue;
- }
- }
-
- if (!opts->quiet) {
- unsigned long long n =(unsigned long long)
- (erase.addr + meminfo->erasesize - opts->offset)
- * 100;
- int percent;
-
- do_div(n, erase_length);
- percent = (int)n;
-
- /* output progress message only at whole percent
- * steps to reduce the number of messages printed
- * on (slow) serial consoles
- */
- if (percent != percent_complete) {
- percent_complete = percent;
-
- printf("\rErasing at 0x%llx -- %3d%% complete.",
- erase.addr, percent);
-
- if (opts->jffs2 && result == 0)
- printf(" Cleanmarker written at 0x%llx.",
- erase.addr);
- }
- }
- }
- if (!opts->quiet)
- printf("\n");
-
- if (nand_block_bad_old) {
- struct nand_chip *priv_nand = meminfo->priv;
-
- priv_nand->block_bad = nand_block_bad_old;
- priv_nand->scan_bbt(meminfo);
- }
-
- return 0;
-}
-
-/* XXX U-BOOT XXX */
-#if 0
-
-#define MAX_PAGE_SIZE 2048
-#define MAX_OOB_SIZE 64
-
-/*
- * buffer array used for writing data
- */
-static unsigned char data_buf[MAX_PAGE_SIZE];
-static unsigned char oob_buf[MAX_OOB_SIZE];
-
-/* OOB layouts to pass into the kernel as default */
-static struct nand_ecclayout none_ecclayout = {
- .useecc = MTD_NANDECC_OFF,
-};
-
-static struct nand_ecclayout jffs2_ecclayout = {
- .useecc = MTD_NANDECC_PLACE,
- .eccbytes = 6,
- .eccpos = { 0, 1, 2, 3, 6, 7 }
-};
-
-static struct nand_ecclayout yaffs_ecclayout = {
- .useecc = MTD_NANDECC_PLACE,
- .eccbytes = 6,
- .eccpos = { 8, 9, 10, 13, 14, 15}
-};
-
-static struct nand_ecclayout autoplace_ecclayout = {
- .useecc = MTD_NANDECC_AUTOPLACE
-};
-#endif
-
-/* XXX U-BOOT XXX */
-#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
-
-/******************************************************************************
- * Support for locking / unlocking operations of some NAND devices
- *****************************************************************************/
-
-#define NAND_CMD_LOCK 0x2a
-#define NAND_CMD_LOCK_TIGHT 0x2c
-#define NAND_CMD_UNLOCK1 0x23
-#define NAND_CMD_UNLOCK2 0x24
-#define NAND_CMD_LOCK_STATUS 0x7a
-
-/**
- * nand_lock: Set all pages of NAND flash chip to the LOCK or LOCK-TIGHT
- * state
- *
- * @param mtd nand mtd instance
- * @param tight bring device in lock tight mode
- *
- * @return 0 on success, -1 in case of error
- *
- * The lock / lock-tight command only applies to the whole chip. To get some
- * parts of the chip lock and others unlocked use the following sequence:
- *
- * - Lock all pages of the chip using nand_lock(mtd, 0) (or the lockpre pin)
- * - Call nand_unlock() once for each consecutive area to be unlocked
- * - If desired: Bring the chip to the lock-tight state using nand_lock(mtd, 1)
- *
- * If the device is in lock-tight state software can't change the
- * current active lock/unlock state of all pages. nand_lock() / nand_unlock()
- * calls will fail. It is only posible to leave lock-tight state by
- * an hardware signal (low pulse on _WP pin) or by power down.
- */
-int nand_lock(struct mtd_info *mtd, int tight)
-{
- int ret = 0;
- int status;
- struct nand_chip *chip = mtd->priv;
-
- /* select the NAND device */
- chip->select_chip(mtd, 0);
-
- chip->cmdfunc(mtd,
- (tight ? NAND_CMD_LOCK_TIGHT : NAND_CMD_LOCK),
- -1, -1);
-
- /* call wait ready function */
- status = chip->waitfunc(mtd, chip);
-
- /* see if device thinks it succeeded */
- if (status & 0x01) {
- ret = -1;
- }
-
- /* de-select the NAND device */
- chip->select_chip(mtd, -1);
- return ret;
-}
-
-/**
- * nand_get_lock_status: - query current lock state from one page of NAND
- * flash
- *
- * @param mtd nand mtd instance
- * @param offset page address to query (muss be page aligned!)
- *
- * @return -1 in case of error
- * >0 lock status:
- * bitfield with the following combinations:
- * NAND_LOCK_STATUS_TIGHT: page in tight state
- * NAND_LOCK_STATUS_LOCK: page locked
- * NAND_LOCK_STATUS_UNLOCK: page unlocked
- *
- */
-int nand_get_lock_status(struct mtd_info *mtd, loff_t offset)
-{
- int ret = 0;
- int chipnr;
- int page;
- struct nand_chip *chip = mtd->priv;
-
- /* select the NAND device */
- chipnr = (int)(offset >> chip->chip_shift);
- chip->select_chip(mtd, chipnr);
-
-
- if ((offset & (mtd->writesize - 1)) != 0) {
- printf ("nand_get_lock_status: "
- "Start address must be beginning of "
- "nand page!\n");
- ret = -1;
- goto out;
- }
-
- /* check the Lock Status */
- page = (int)(offset >> chip->page_shift);
- chip->cmdfunc(mtd, NAND_CMD_LOCK_STATUS, -1, page & chip->pagemask);
-
- ret = chip->read_byte(mtd) & (NAND_LOCK_STATUS_TIGHT
- | NAND_LOCK_STATUS_LOCK
- | NAND_LOCK_STATUS_UNLOCK);
-
- out:
- /* de-select the NAND device */
- chip->select_chip(mtd, -1);
- return ret;
-}
-
-/**
- * nand_unlock: - Unlock area of NAND pages
- * only one consecutive area can be unlocked at one time!
- *
- * @param mtd nand mtd instance
- * @param start start byte address
- * @param length number of bytes to unlock (must be a multiple of
- * page size nand->writesize)
- *
- * @return 0 on success, -1 in case of error
- */
-int nand_unlock(struct mtd_info *mtd, ulong start, ulong length)
-{
- int ret = 0;
- int chipnr;
- int status;
- int page;
- struct nand_chip *chip = mtd->priv;
- printf ("nand_unlock: start: %08x, length: %d!\n",
- (int)start, (int)length);
-
- /* select the NAND device */
- chipnr = (int)(start >> chip->chip_shift);
- chip->select_chip(mtd, chipnr);
-
- /* check the WP bit */
- chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
- if (!(chip->read_byte(mtd) & NAND_STATUS_WP)) {
- printf ("nand_unlock: Device is write protected!\n");
- ret = -1;
- goto out;
- }
-
- if ((start & (mtd->erasesize - 1)) != 0) {
- printf ("nand_unlock: Start address must be beginning of "
- "nand block!\n");
- ret = -1;
- goto out;
- }
-
- if (length == 0 || (length & (mtd->erasesize - 1)) != 0) {
- printf ("nand_unlock: Length must be a multiple of nand block "
- "size %08x!\n", mtd->erasesize);
- ret = -1;
- goto out;
- }
-
- /*
- * Set length so that the last address is set to the
- * starting address of the last block
- */
- length -= mtd->erasesize;
-
- /* submit address of first page to unlock */
- page = (int)(start >> chip->page_shift);
- chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
-
- /* submit ADDRESS of LAST page to unlock */
- page += (int)(length >> chip->page_shift);
- chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1, page & chip->pagemask);
-
- /* call wait ready function */
- status = chip->waitfunc(mtd, chip);
- /* see if device thinks it succeeded */
- if (status & 0x01) {
- /* there was an error */
- ret = -1;
- goto out;
- }
-
- out:
- /* de-select the NAND device */
- chip->select_chip(mtd, -1);
- return ret;
-}
-#endif
-
-/**
- * get_len_incl_bad
- *
- * Check if length including bad blocks fits into device.
- *
- * @param nand NAND device
- * @param offset offset in flash
- * @param length image length
- * @return image length including bad blocks
- */
-static size_t get_len_incl_bad (nand_info_t *nand, loff_t offset,
- const size_t length)
-{
- size_t len_incl_bad = 0;
- size_t len_excl_bad = 0;
- size_t block_len;
-
- while (len_excl_bad < length) {
- block_len = nand->erasesize - (offset & (nand->erasesize - 1));
-
- if (!nand_block_isbad (nand, offset & ~(nand->erasesize - 1)))
- len_excl_bad += block_len;
-
- len_incl_bad += block_len;
- offset += block_len;
-
- if ((offset + len_incl_bad) >= nand->size)
- break;
- }
-
- return len_incl_bad;
-}
-
-/**
- * nand_write_skip_bad:
- *
- * Write image to NAND flash.
- * Blocks that are marked bad are skipped and the is written to the next
- * block instead as long as the image is short enough to fit even after
- * skipping the bad blocks.
- *
- * @param nand NAND device
- * @param offset offset in flash
- * @param length buffer length
- * @param buf buffer to read from
- * @return 0 in case of success
- */
-int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
- u_char *buffer)
-{
- int rval;
- size_t left_to_write = *length;
- size_t len_incl_bad;
- u_char *p_buffer = buffer;
-
- /* Reject writes, which are not page aligned */
- if ((offset & (nand->writesize - 1)) != 0 ||
- (*length & (nand->writesize - 1)) != 0) {
- printf ("Attempt to write non page aligned data\n");
- return -EINVAL;
- }
-
- len_incl_bad = get_len_incl_bad (nand, offset, *length);
-
- if ((offset + len_incl_bad) >= nand->size) {
- printf ("Attempt to write outside the flash area\n");
- return -EINVAL;
- }
-
- if (len_incl_bad == *length) {
- rval = nand_write (nand, offset, length, buffer);
- if (rval != 0)
- printf ("NAND write to offset %llx failed %d\n",
- offset, rval);
-
- return rval;
- }
-
- while (left_to_write > 0) {
- size_t block_offset = offset & (nand->erasesize - 1);
- size_t write_size;
-
- WATCHDOG_RESET ();
-
- if (nand_block_isbad (nand, offset & ~(nand->erasesize - 1))) {
- printf ("Skip bad block 0x%08llx\n",
- offset & ~(nand->erasesize - 1));
- offset += nand->erasesize - block_offset;
- continue;
- }
-
- if (left_to_write < (nand->erasesize - block_offset))
- write_size = left_to_write;
- else
- write_size = nand->erasesize - block_offset;
-
- rval = nand_write (nand, offset, &write_size, p_buffer);
- if (rval != 0) {
- printf ("NAND write to offset %llx failed %d\n",
- offset, rval);
- *length -= left_to_write;
- return rval;
- }
-
- left_to_write -= write_size;
- offset += write_size;
- p_buffer += write_size;
- }
-
- return 0;
-}
-
-/**
- * nand_read_skip_bad:
- *
- * Read image from NAND flash.
- * Blocks that are marked bad are skipped and the next block is readen
- * instead as long as the image is short enough to fit even after skipping the
- * bad blocks.
- *
- * @param nand NAND device
- * @param offset offset in flash
- * @param length buffer length, on return holds remaining bytes to read
- * @param buffer buffer to write to
- * @return 0 in case of success
- */
-int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
- u_char *buffer)
-{
- int rval;
- size_t left_to_read = *length;
- size_t len_incl_bad;
- u_char *p_buffer = buffer;
-
- len_incl_bad = get_len_incl_bad (nand, offset, *length);
-
- if ((offset + len_incl_bad) >= nand->size) {
- printf ("Attempt to read outside the flash area\n");
- return -EINVAL;
- }
-
- if (len_incl_bad == *length) {
- rval = nand_read (nand, offset, length, buffer);
- if (!rval || rval == -EUCLEAN)
- return 0;
- printf ("NAND read from offset %llx failed %d\n",
- offset, rval);
- return rval;
- }
-
- while (left_to_read > 0) {
- size_t block_offset = offset & (nand->erasesize - 1);
- size_t read_length;
-
- WATCHDOG_RESET ();
-
- if (nand_block_isbad (nand, offset & ~(nand->erasesize - 1))) {
- printf ("Skipping bad block 0x%08llx\n",
- offset & ~(nand->erasesize - 1));
- offset += nand->erasesize - block_offset;
- continue;
- }
-
- if (left_to_read < (nand->erasesize - block_offset))
- read_length = left_to_read;
- else
- read_length = nand->erasesize - block_offset;
-
- rval = nand_read (nand, offset, &read_length, p_buffer);
- if (rval && rval != -EUCLEAN) {
- printf ("NAND read from offset %llx failed %d\n",
- offset, rval);
- *length -= left_to_read;
- return rval;
- }
-
- left_to_read -= read_length;
- offset += read_length;
- p_buffer += read_length;
- }
-
- return 0;
-}
+++ /dev/null
-/******************************************************************************/
-/* */
-/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom */
-/* Corporation. */
-/* All rights reserved. */
-/* */
-/* This program is free software; you can redistribute it and/or modify */
-/* it under the terms of the GNU General Public License as published by */
-/* the Free Software Foundation, located in the file LICENSE. */
-/* */
-/* History: */
-/* */
-/******************************************************************************/
-
-#if INCLUDE_5701_AX_FIX
-
-#include "bcm570x_mm.h"
-#include "5701rls.h"
-
-LM_STATUS LM_LoadRlsFirmware(PLM_DEVICE_BLOCK pDevice)
-{
- T3_FWIMG_INFO FwImgInfo;
-
- FwImgInfo.StartAddress = t3FwStartAddr;
- FwImgInfo.Text.Buffer = (PLM_UINT8)t3FwText;
- FwImgInfo.Text.Offset = t3FwTextAddr;
- FwImgInfo.Text.Length = t3FwTextLen;
- FwImgInfo.ROnlyData.Buffer = (PLM_UINT8)t3FwRodata;
- FwImgInfo.ROnlyData.Offset = t3FwRodataAddr;
- FwImgInfo.ROnlyData.Length = t3FwRodataLen;
- FwImgInfo.Data.Buffer = (PLM_UINT8)t3FwData;
- FwImgInfo.Data.Offset = t3FwDataAddr;
- FwImgInfo.Data.Length = t3FwDataLen;
-
- if (LM_LoadFirmware(pDevice,
- &FwImgInfo,
- T3_RX_CPU_ID | T3_TX_CPU_ID,
- T3_RX_CPU_ID) != LM_STATUS_SUCCESS)
- {
- return LM_STATUS_FAILURE;
- }
-
- return LM_STATUS_SUCCESS;
-}
-
-#endif /* INCLUDE_5701_AX_FIX */
+++ /dev/null
-/******************************************************************************/
-/* */
-/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom */
-/* Corporation. */
-/* All rights reserved. */
-/* */
-/* This program is free software; you can redistribute it and/or modify */
-/* it under the terms of the GNU General Public License as published by */
-/* the Free Software Foundation, located in the file LICENSE. */
-/* */
-/* History: */
-/******************************************************************************/
-
-typedef unsigned long U32;
-int t3FwReleaseMajor = 0x0;
-int t3FwReleaseMinor = 0x0;
-int t3FwReleaseFix = 0x0;
-U32 t3FwStartAddr = 0x08000000;
-U32 t3FwTextAddr = 0x08000000;
-int t3FwTextLen = 0x9c0;
-U32 t3FwRodataAddr = 0x080009c0;
-int t3FwRodataLen = 0x60;
-U32 t3FwDataAddr = 0x08000a40;
-int t3FwDataLen = 0x20;
-U32 t3FwSbssAddr = 0x08000a60;
-int t3FwSbssLen = 0xc;
-U32 t3FwBssAddr = 0x08000a70;
-int t3FwBssLen = 0x10;
-U32 t3FwText[(0x9c0/4) + 1] = {
-0x0,
-0x10000003, 0x0, 0xd, 0xd,
-0x3c1d0800, 0x37bd3ffc, 0x3a0f021, 0x3c100800,
-0x26100000, 0xe000018, 0x0, 0xd,
-0x3c1d0800, 0x37bd3ffc, 0x3a0f021, 0x3c100800,
-0x26100034, 0xe00021c, 0x0, 0xd,
-0x0, 0x0, 0x0, 0x27bdffe0,
-0x3c1cc000, 0xafbf0018, 0xaf80680c, 0xe00004c,
-0x241b2105, 0x97850000, 0x97870002, 0x9782002c,
-0x9783002e, 0x3c040800, 0x248409c0, 0xafa00014,
-0x21400, 0x621825, 0x52c00, 0xafa30010,
-0x8f860010, 0xe52825, 0xe000060, 0x24070102,
-0x3c02ac00, 0x34420100, 0x3c03ac01, 0x34630100,
-0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498,
-0xaf82049c, 0x24020001, 0xaf825ce0, 0xe00003f,
-0xaf825d00, 0xe000140, 0x0, 0x8fbf0018,
-0x3e00008, 0x27bd0020, 0x2402ffff, 0xaf825404,
-0x8f835400, 0x34630400, 0xaf835400, 0xaf825404,
-0x3c020800, 0x24420034, 0xaf82541c, 0x3e00008,
-0xaf805400, 0x0, 0x0, 0x3c020800,
-0x34423000, 0x3c030800, 0x34633000, 0x3c040800,
-0x348437ff, 0x3c010800, 0xac220a64, 0x24020040,
-0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60,
-0xac600000, 0x24630004, 0x83102b, 0x5040fffd,
-0xac600000, 0x3e00008, 0x0, 0x804821,
-0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800,
-0x8c840a68, 0x8fab0014, 0x24430001, 0x44102b,
-0x3c010800, 0xac230a60, 0x14400003, 0x4021,
-0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60,
-0x3c030800, 0x8c630a64, 0x91240000, 0x21140,
-0x431021, 0x481021, 0x25080001, 0xa0440000,
-0x29020008, 0x1440fff4, 0x25290001, 0x3c020800,
-0x8c420a60, 0x3c030800, 0x8c630a64, 0x8f84680c,
-0x21140, 0x431021, 0xac440008, 0xac45000c,
-0xac460010, 0xac470014, 0xac4a0018, 0x3e00008,
-0xac4b001c, 0x0, 0x0, 0x0,
-0x0, 0x0, 0x0, 0x0,
-0x0, 0x0, 0x0, 0x0,
-0x0, 0x0, 0x0, 0x0,
-0x0, 0x0, 0x0, 0x0,
-0x0, 0x0, 0x0, 0x0,
-0x0, 0x0, 0x0, 0x0,
-0x0, 0x0, 0x0, 0x0,
-0x0, 0x0, 0x0, 0x0,
-0x0, 0x0, 0x0, 0x0,
-0x0, 0x0, 0x0, 0x0,
-0x0, 0x0, 0x0, 0x0,
-0x0, 0x0, 0x0, 0x0,
-0x0, 0x0, 0x0, 0x2000008,
-0x0, 0xa0001e3, 0x3c0a0001, 0xa0001e3,
-0x3c0a0002, 0xa0001e3, 0x0, 0xa0001e3,
-0x0, 0xa0001e3, 0x0, 0xa0001e3,
-0x0, 0xa0001e3, 0x0, 0xa0001e3,
-0x0, 0xa0001e3, 0x0, 0xa0001e3,
-0x0, 0xa0001e3, 0x0, 0xa0001e3,
-0x3c0a0007, 0xa0001e3, 0x3c0a0008, 0xa0001e3,
-0x3c0a0009, 0xa0001e3, 0x0, 0xa0001e3,
-0x0, 0xa0001e3, 0x3c0a000b, 0xa0001e3,
-0x3c0a000c, 0xa0001e3, 0x3c0a000d, 0xa0001e3,
-0x0, 0xa0001e3, 0x0, 0xa0001e3,
-0x3c0a000e, 0xa0001e3, 0x0, 0xa0001e3,
-0x0, 0xa0001e3, 0x0, 0xa0001e3,
-0x0, 0xa0001e3, 0x0, 0xa0001e3,
-0x0, 0xa0001e3, 0x0, 0xa0001e3,
-0x0, 0xa0001e3, 0x3c0a0013, 0xa0001e3,
-0x3c0a0014, 0x0, 0x0, 0x0,
-0x0, 0x0, 0x0, 0x0,
-0x0, 0x0, 0x0, 0x0,
-0x0, 0x0, 0x0, 0x0,
-0x0, 0x0, 0x0, 0x0,
-0x0, 0x0, 0x0, 0x0,
-0x0, 0x0, 0x0, 0x0,
-0x0, 0x0, 0x0, 0x0,
-0x0, 0x0, 0x0, 0x0,
-0x0, 0x0, 0x0, 0x0,
-0x0, 0x0, 0x0, 0x0,
-0x0, 0x0, 0x0, 0x0,
-0x0, 0x0, 0x0, 0x0,
-0x0, 0x0, 0x0, 0x0,
-0x0, 0x0, 0x0, 0x0,
-0x0, 0x0, 0x0, 0x27bdffe0,
-0x1821, 0x1021, 0xafbf0018, 0xafb10014,
-0xafb00010, 0x3c010800, 0x220821, 0xac200a70,
-0x3c010800, 0x220821, 0xac200a74, 0x3c010800,
-0x220821, 0xac200a78, 0x24630001, 0x1860fff5,
-0x2442000c, 0x24110001, 0x8f906810, 0x32020004,
-0x14400005, 0x24040001, 0x3c020800, 0x8c420a78,
-0x18400003, 0x2021, 0xe000182, 0x0,
-0x32020001, 0x10400003, 0x0, 0xe000169,
-0x0, 0xa000153, 0xaf915028, 0x8fbf0018,
-0x8fb10014, 0x8fb00010, 0x3e00008, 0x27bd0020,
-0x3c050800, 0x8ca50a70, 0x3c060800, 0x8cc60a80,
-0x3c070800, 0x8ce70a78, 0x27bdffe0, 0x3c040800,
-0x248409d0, 0xafbf0018, 0xafa00010, 0xe000060,
-0xafa00014, 0xe00017b, 0x2021, 0x8fbf0018,
-0x3e00008, 0x27bd0020, 0x24020001, 0x8f836810,
-0x821004, 0x21027, 0x621824, 0x3e00008,
-0xaf836810, 0x27bdffd8, 0xafbf0024, 0x1080002e,
-0xafb00020, 0x8f825cec, 0xafa20018, 0x8f825cec,
-0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000,
-0xaf825cec, 0x8e020000, 0x18400016, 0x0,
-0x3c020800, 0x94420a74, 0x8fa3001c, 0x221c0,
-0xac830004, 0x8fa2001c, 0x3c010800, 0xe000201,
-0xac220a74, 0x10400005, 0x0, 0x8e020000,
-0x24420001, 0xa0001df, 0xae020000, 0x3c020800,
-0x8c420a70, 0x21c02, 0x321c0, 0xa0001c5,
-0xafa2001c, 0xe000201, 0x0, 0x1040001f,
-0x0, 0x8e020000, 0x8fa3001c, 0x24420001,
-0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74,
-0xa0001df, 0xae020000, 0x3c100800, 0x26100a78,
-0x8e020000, 0x18400028, 0x0, 0xe000201,
-0x0, 0x14400024, 0x0, 0x8e020000,
-0x3c030800, 0x8c630a70, 0x2442ffff, 0xafa3001c,
-0x18400006, 0xae020000, 0x31402, 0x221c0,
-0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e,
-0x2442ff00, 0x2c420300, 0x1440000b, 0x24024000,
-0x3c040800, 0x248409dc, 0xafa00010, 0xafa00014,
-0x8fa6001c, 0x24050008, 0xe000060, 0x3821,
-0xa0001df, 0x0, 0xaf825cf8, 0x3c020800,
-0x8c420a40, 0x8fa3001c, 0x24420001, 0xaf835cf8,
-0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020,
-0x3e00008, 0x27bd0028, 0x27bdffe0, 0x3c040800,
-0x248409e8, 0x2821, 0x3021, 0x3821,
-0xafbf0018, 0xafa00010, 0xe000060, 0xafa00014,
-0x8fbf0018, 0x3e00008, 0x27bd0020, 0x8f82680c,
-0x8f85680c, 0x21827, 0x3182b, 0x31823,
-0x431024, 0x441021, 0xa2282b, 0x10a00006,
-0x0, 0x401821, 0x8f82680c, 0x43102b,
-0x1440fffd, 0x0, 0x3e00008, 0x0,
-0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40,
-0x64102b, 0x54400002, 0x831023, 0x641023,
-0x2c420008, 0x3e00008, 0x38420001, 0x27bdffe0,
-0x802821, 0x3c040800, 0x24840a00, 0x3021,
-0x3821, 0xafbf0018, 0xafa00010, 0xe000060,
-0xafa00014, 0xa000216, 0x0, 0x8fbf0018,
-0x3e00008, 0x27bd0020, 0x0, 0x27bdffe0,
-0x3c1cc000, 0xafbf0018, 0xe00004c, 0xaf80680c,
-0x3c040800, 0x24840a10, 0x3802821, 0x3021,
-0x3821, 0xafa00010, 0xe000060, 0xafa00014,
-0x2402ffff, 0xaf825404, 0x3c0200aa, 0xe000234,
-0xaf825434, 0x8fbf0018, 0x3e00008, 0x27bd0020,
-0x0, 0x0, 0x0, 0x27bdffe8,
-0xafb00010, 0x24100001, 0xafbf0014, 0x3c01c003,
-0xac200000, 0x8f826810, 0x30422000, 0x10400003,
-0x0, 0xe000246, 0x0, 0xa00023a,
-0xaf905428, 0x8fbf0014, 0x8fb00010, 0x3e00008,
-0x27bd0018, 0x27bdfff8, 0x8f845d0c, 0x3c0200ff,
-0x3c030800, 0x8c630a50, 0x3442fff8, 0x821024,
-0x1043001e, 0x3c0500ff, 0x34a5fff8, 0x3c06c003,
-0x3c074000, 0x851824, 0x8c620010, 0x3c010800,
-0xac230a50, 0x30420008, 0x10400005, 0x871025,
-0x8cc20000, 0x24420001, 0xacc20000, 0x871025,
-0xaf825d0c, 0x8fa20000, 0x24420001, 0xafa20000,
-0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000,
-0x8fa20000, 0x8f845d0c, 0x3c030800, 0x8c630a50,
-0x851024, 0x1443ffe8, 0x851824, 0x27bd0008,
-0x3e00008, 0x0, 0x0, 0x0 };
-U32 t3FwRodata[(0x60/4) + 1] = {
-0x35373031, 0x726c7341, 0x0,
-0x0, 0x53774576, 0x656e7430, 0x0,
-0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e,
-0x45766e74, 0x0, 0x0, 0x0,
-0x0, 0x66617461, 0x6c457272, 0x0,
-0x0, 0x4d61696e, 0x43707542, 0x0,
-0x0, 0x0 };
-U32 t3FwData[(0x20/4) + 1] = {
-0x0, 0x0, 0x0,
-0x0, 0x0, 0x0, 0x0,
-0x0, 0x0 };
+++ /dev/null
-/******************************************************************************/
-/* */
-/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2001 Broadcom */
-/* Corporation. */
-/* All rights reserved. */
-/* */
-/* This program is free software; you can redistribute it and/or modify */
-/* it under the terms of the GNU General Public License as published by */
-/* the Free Software Foundation, located in the file LICENSE. */
-/* */
-/* History: */
-/******************************************************************************/
-#if !defined(CONFIG_NET_MULTI)
-#if INCLUDE_TBI_SUPPORT
-#include "bcm570x_autoneg.h"
-#include "bcm570x_mm.h"
-
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-void
-MM_AnTxConfig(
- PAN_STATE_INFO pAnInfo)
-{
- PLM_DEVICE_BLOCK pDevice;
-
- pDevice = (PLM_DEVICE_BLOCK) pAnInfo->pContext;
-
- REG_WR(pDevice, MacCtrl.TxAutoNeg, (LM_UINT32) pAnInfo->TxConfig.AsUSHORT);
-
- pDevice->MacMode |= MAC_MODE_SEND_CONFIGS;
- REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
-}
-
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-void
-MM_AnTxIdle(
- PAN_STATE_INFO pAnInfo)
-{
- PLM_DEVICE_BLOCK pDevice;
-
- pDevice = (PLM_DEVICE_BLOCK) pAnInfo->pContext;
-
- pDevice->MacMode &= ~MAC_MODE_SEND_CONFIGS;
- REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
-}
-
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-char
-MM_AnRxConfig(
- PAN_STATE_INFO pAnInfo,
- unsigned short *pRxConfig)
-{
- PLM_DEVICE_BLOCK pDevice;
- LM_UINT32 Value32;
- char Retcode;
-
- Retcode = AN_FALSE;
-
- pDevice = (PLM_DEVICE_BLOCK) pAnInfo->pContext;
-
- Value32 = REG_RD(pDevice, MacCtrl.Status);
- if(Value32 & MAC_STATUS_RECEIVING_CFG)
- {
- Value32 = REG_RD(pDevice, MacCtrl.RxAutoNeg);
- *pRxConfig = (unsigned short) Value32;
-
- Retcode = AN_TRUE;
- }
-
- return Retcode;
-}
-
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-void
-AutonegInit(
- PAN_STATE_INFO pAnInfo)
-{
- unsigned long j;
-
- for(j = 0; j < sizeof(AN_STATE_INFO); j++)
- {
- ((unsigned char *) pAnInfo)[j] = 0;
- }
-
- /* Initialize the default advertisement register. */
- pAnInfo->mr_adv_full_duplex = 1;
- pAnInfo->mr_adv_sym_pause = 1;
- pAnInfo->mr_adv_asym_pause = 1;
- pAnInfo->mr_an_enable = 1;
-}
-
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-AUTONEG_STATUS
-Autoneg8023z(
- PAN_STATE_INFO pAnInfo)
-{
- unsigned short RxConfig;
- unsigned long Delta_us;
- AUTONEG_STATUS AnRet;
-
- /* Get the current time. */
- if(pAnInfo->State == AN_STATE_UNKNOWN)
- {
- pAnInfo->RxConfig.AsUSHORT = 0;
- pAnInfo->CurrentTime_us = 0;
- pAnInfo->LinkTime_us = 0;
- pAnInfo->AbilityMatchCfg = 0;
- pAnInfo->AbilityMatchCnt = 0;
- pAnInfo->AbilityMatch = AN_FALSE;
- pAnInfo->IdleMatch = AN_FALSE;
- pAnInfo->AckMatch = AN_FALSE;
- }
-
- /* Increment the timer tick. This function is called every microsecon. */
-/* pAnInfo->CurrentTime_us++; */
-
- /* Set the AbilityMatch, IdleMatch, and AckMatch flags if their */
- /* corresponding conditions are satisfied. */
- if(MM_AnRxConfig(pAnInfo, &RxConfig))
- {
- if(RxConfig != pAnInfo->AbilityMatchCfg)
- {
- pAnInfo->AbilityMatchCfg = RxConfig;
- pAnInfo->AbilityMatch = AN_FALSE;
- pAnInfo->AbilityMatchCnt = 0;
- }
- else
- {
- pAnInfo->AbilityMatchCnt++;
- if(pAnInfo->AbilityMatchCnt > 1)
- {
- pAnInfo->AbilityMatch = AN_TRUE;
- pAnInfo->AbilityMatchCfg = RxConfig;
- }
- }
-
- if(RxConfig & AN_CONFIG_ACK)
- {
- pAnInfo->AckMatch = AN_TRUE;
- }
- else
- {
- pAnInfo->AckMatch = AN_FALSE;
- }
-
- pAnInfo->IdleMatch = AN_FALSE;
- }
- else
- {
- pAnInfo->IdleMatch = AN_TRUE;
-
- pAnInfo->AbilityMatchCfg = 0;
- pAnInfo->AbilityMatchCnt = 0;
- pAnInfo->AbilityMatch = AN_FALSE;
- pAnInfo->AckMatch = AN_FALSE;
-
- RxConfig = 0;
- }
-
- /* Save the last Config. */
- pAnInfo->RxConfig.AsUSHORT = RxConfig;
-
- /* Default return code. */
- AnRet = AUTONEG_STATUS_OK;
-
- /* Autoneg state machine as defined in 802.3z section 37.3.1.5. */
- switch(pAnInfo->State)
- {
- case AN_STATE_UNKNOWN:
- if(pAnInfo->mr_an_enable || pAnInfo->mr_restart_an)
- {
- pAnInfo->CurrentTime_us = 0;
- pAnInfo->State = AN_STATE_AN_ENABLE;
- }
-
- /* Fall through.*/
-
- case AN_STATE_AN_ENABLE:
- pAnInfo->mr_an_complete = AN_FALSE;
- pAnInfo->mr_page_rx = AN_FALSE;
-
- if(pAnInfo->mr_an_enable)
- {
- pAnInfo->LinkTime_us = 0;
- pAnInfo->AbilityMatchCfg = 0;
- pAnInfo->AbilityMatchCnt = 0;
- pAnInfo->AbilityMatch = AN_FALSE;
- pAnInfo->IdleMatch = AN_FALSE;
- pAnInfo->AckMatch = AN_FALSE;
-
- pAnInfo->State = AN_STATE_AN_RESTART_INIT;
- }
- else
- {
- pAnInfo->State = AN_STATE_DISABLE_LINK_OK;
- }
- break;
-
- case AN_STATE_AN_RESTART_INIT:
- pAnInfo->LinkTime_us = pAnInfo->CurrentTime_us;
- pAnInfo->mr_np_loaded = AN_FALSE;
-
- pAnInfo->TxConfig.AsUSHORT = 0;
- MM_AnTxConfig(pAnInfo);
-
- AnRet = AUTONEG_STATUS_TIMER_ENABLED;
-
- pAnInfo->State = AN_STATE_AN_RESTART;
-
- /* Fall through.*/
-
- case AN_STATE_AN_RESTART:
- /* Get the current time and compute the delta with the saved */
- /* link timer. */
- Delta_us = pAnInfo->CurrentTime_us - pAnInfo->LinkTime_us;
- if(Delta_us > AN_LINK_TIMER_INTERVAL_US)
- {
- pAnInfo->State = AN_STATE_ABILITY_DETECT_INIT;
- }
- else
- {
- AnRet = AUTONEG_STATUS_TIMER_ENABLED;
- }
- break;
-
- case AN_STATE_DISABLE_LINK_OK:
- AnRet = AUTONEG_STATUS_DONE;
- break;
-
- case AN_STATE_ABILITY_DETECT_INIT:
- /* Note: in the state diagram, this variable is set to */
- /* mr_adv_ability<12>. Is this right?. */
- pAnInfo->mr_toggle_tx = AN_FALSE;
-
- /* Send the config as advertised in the advertisement register. */
- pAnInfo->TxConfig.AsUSHORT = 0;
- pAnInfo->TxConfig.D5_FD = pAnInfo->mr_adv_full_duplex;
- pAnInfo->TxConfig.D6_HD = pAnInfo->mr_adv_half_duplex;
- pAnInfo->TxConfig.D7_PS1 = pAnInfo->mr_adv_sym_pause;
- pAnInfo->TxConfig.D8_PS2 = pAnInfo->mr_adv_asym_pause;
- pAnInfo->TxConfig.D12_RF1 = pAnInfo->mr_adv_remote_fault1;
- pAnInfo->TxConfig.D13_RF2 = pAnInfo->mr_adv_remote_fault2;
- pAnInfo->TxConfig.D15_NP = pAnInfo->mr_adv_next_page;
-
- MM_AnTxConfig(pAnInfo);
-
- pAnInfo->State = AN_STATE_ABILITY_DETECT;
-
- break;
-
- case AN_STATE_ABILITY_DETECT:
- if(pAnInfo->AbilityMatch == AN_TRUE &&
- pAnInfo->RxConfig.AsUSHORT != 0)
- {
- pAnInfo->State = AN_STATE_ACK_DETECT_INIT;
- }
-
- break;
-
- case AN_STATE_ACK_DETECT_INIT:
- pAnInfo->TxConfig.D14_ACK = 1;
- MM_AnTxConfig(pAnInfo);
-
- pAnInfo->State = AN_STATE_ACK_DETECT;
-
- /* Fall through. */
-
- case AN_STATE_ACK_DETECT:
- if(pAnInfo->AckMatch == AN_TRUE)
- {
- if((pAnInfo->RxConfig.AsUSHORT & ~AN_CONFIG_ACK) ==
- (pAnInfo->AbilityMatchCfg & ~AN_CONFIG_ACK))
- {
- pAnInfo->State = AN_STATE_COMPLETE_ACK_INIT;
- }
- else
- {
- pAnInfo->State = AN_STATE_AN_ENABLE;
- }
- }
- else if(pAnInfo->AbilityMatch == AN_TRUE &&
- pAnInfo->RxConfig.AsUSHORT == 0)
- {
- pAnInfo->State = AN_STATE_AN_ENABLE;
- }
-
- break;
-
- case AN_STATE_COMPLETE_ACK_INIT:
- /* Make sure invalid bits are not set. */
- if(pAnInfo->RxConfig.bits.D0 || pAnInfo->RxConfig.bits.D1 ||
- pAnInfo->RxConfig.bits.D2 || pAnInfo->RxConfig.bits.D3 ||
- pAnInfo->RxConfig.bits.D4 || pAnInfo->RxConfig.bits.D9 ||
- pAnInfo->RxConfig.bits.D10 || pAnInfo->RxConfig.bits.D11)
- {
- AnRet = AUTONEG_STATUS_FAILED;
- break;
- }
-
- /* Set up the link partner advertisement register. */
- pAnInfo->mr_lp_adv_full_duplex = pAnInfo->RxConfig.D5_FD;
- pAnInfo->mr_lp_adv_half_duplex = pAnInfo->RxConfig.D6_HD;
- pAnInfo->mr_lp_adv_sym_pause = pAnInfo->RxConfig.D7_PS1;
- pAnInfo->mr_lp_adv_asym_pause = pAnInfo->RxConfig.D8_PS2;
- pAnInfo->mr_lp_adv_remote_fault1 = pAnInfo->RxConfig.D12_RF1;
- pAnInfo->mr_lp_adv_remote_fault2 = pAnInfo->RxConfig.D13_RF2;
- pAnInfo->mr_lp_adv_next_page = pAnInfo->RxConfig.D15_NP;
-
- pAnInfo->LinkTime_us = pAnInfo->CurrentTime_us;
-
- pAnInfo->mr_toggle_tx = !pAnInfo->mr_toggle_tx;
- pAnInfo->mr_toggle_rx = pAnInfo->RxConfig.bits.D11;
- pAnInfo->mr_np_rx = pAnInfo->RxConfig.D15_NP;
- pAnInfo->mr_page_rx = AN_TRUE;
-
- pAnInfo->State = AN_STATE_COMPLETE_ACK;
- AnRet = AUTONEG_STATUS_TIMER_ENABLED;
-
- break;
-
- case AN_STATE_COMPLETE_ACK:
- if(pAnInfo->AbilityMatch == AN_TRUE &&
- pAnInfo->RxConfig.AsUSHORT == 0)
- {
- pAnInfo->State = AN_STATE_AN_ENABLE;
- break;
- }
-
- Delta_us = pAnInfo->CurrentTime_us - pAnInfo->LinkTime_us;
-
- if(Delta_us > AN_LINK_TIMER_INTERVAL_US)
- {
- if(pAnInfo->mr_adv_next_page == 0 ||
- pAnInfo->mr_lp_adv_next_page == 0)
- {
- pAnInfo->State = AN_STATE_IDLE_DETECT_INIT;
- }
- else
- {
- if(pAnInfo->TxConfig.bits.D15 == 0 &&
- pAnInfo->mr_np_rx == 0)
- {
- pAnInfo->State = AN_STATE_IDLE_DETECT_INIT;
- }
- else
- {
- AnRet = AUTONEG_STATUS_FAILED;
- }
- }
- }
-
- break;
-
- case AN_STATE_IDLE_DETECT_INIT:
- pAnInfo->LinkTime_us = pAnInfo->CurrentTime_us;
-
- MM_AnTxIdle(pAnInfo);
-
- pAnInfo->State = AN_STATE_IDLE_DETECT;
-
- AnRet = AUTONEG_STATUS_TIMER_ENABLED;
-
- break;
-
- case AN_STATE_IDLE_DETECT:
- if(pAnInfo->AbilityMatch == AN_TRUE &&
- pAnInfo->RxConfig.AsUSHORT == 0)
- {
- pAnInfo->State = AN_STATE_AN_ENABLE;
- break;
- }
-
- Delta_us = pAnInfo->CurrentTime_us - pAnInfo->LinkTime_us;
- if(Delta_us > AN_LINK_TIMER_INTERVAL_US)
- {
-#if 0
-/* if(pAnInfo->IdleMatch == AN_TRUE) */
-/* { */
-#endif
- pAnInfo->State = AN_STATE_LINK_OK;
-#if 0
-/* } */
-/* else */
-/* { */
-/* AnRet = AUTONEG_STATUS_FAILED; */
-/* break; */
-/* } */
-#endif
- }
-
- break;
-
- case AN_STATE_LINK_OK:
- pAnInfo->mr_an_complete = AN_TRUE;
- pAnInfo->mr_link_ok = AN_TRUE;
- AnRet = AUTONEG_STATUS_DONE;
-
- break;
-
- case AN_STATE_NEXT_PAGE_WAIT_INIT:
- break;
-
- case AN_STATE_NEXT_PAGE_WAIT:
- break;
-
- default:
- AnRet = AUTONEG_STATUS_FAILED;
- break;
- }
-
- return AnRet;
-}
-#endif /* INCLUDE_TBI_SUPPORT */
-
-#endif /* !defined(CONFIG_NET_MULTI) */
+++ /dev/null
-/******************************************************************************/
-/* */
-/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2001 Broadcom */
-/* Corporation. */
-/* All rights reserved. */
-/* */
-/* This program is free software; you can redistribute it and/or modify */
-/* it under the terms of the GNU General Public License as published by */
-/* the Free Software Foundation, located in the file LICENSE. */
-/* */
-/* History: */
-/******************************************************************************/
-
-
-#ifndef AUTONEG_H
-#define AUTONEG_H
-
-
-/******************************************************************************/
-/* Constants. */
-/******************************************************************************/
-
-#define AN_LINK_TIMER_INTERVAL_US 9000 /* 10ms */
-
-/* TRUE, FALSE */
-#define AN_TRUE 1
-#define AN_FALSE 0
-
-
-/******************************************************************************/
-/* Main data structure for keeping track of 802.3z auto-negotation state */
-/* variables as shown in Figure 37-6 of the IEEE 802.3z specification. */
-/******************************************************************************/
-
-typedef struct
-{
- /* Current auto-negotiation state. */
- unsigned long State;
- #define AN_STATE_UNKNOWN 0
- #define AN_STATE_AN_ENABLE 1
- #define AN_STATE_AN_RESTART_INIT 2
- #define AN_STATE_AN_RESTART 3
- #define AN_STATE_DISABLE_LINK_OK 4
- #define AN_STATE_ABILITY_DETECT_INIT 5
- #define AN_STATE_ABILITY_DETECT 6
- #define AN_STATE_ACK_DETECT_INIT 7
- #define AN_STATE_ACK_DETECT 8
- #define AN_STATE_COMPLETE_ACK_INIT 9
- #define AN_STATE_COMPLETE_ACK 10
- #define AN_STATE_IDLE_DETECT_INIT 11
- #define AN_STATE_IDLE_DETECT 12
- #define AN_STATE_LINK_OK 13
- #define AN_STATE_NEXT_PAGE_WAIT_INIT 14
- #define AN_STATE_NEXT_PAGE_WAIT 16
-
- /* Link timer. */
- unsigned long LinkTime_us;
-
- /* Current time. */
- unsigned long CurrentTime_us;
-
- /* Need these values for consistency check. */
- unsigned short AbilityMatchCfg;
-
- /* Ability, idle, and ack match functions. */
- unsigned long AbilityMatchCnt;
- char AbilityMatch;
- char IdleMatch;
- char AckMatch;
-
- /* Tx config data */
- union
- {
- /* The TxConfig register is arranged as follows: */
- /* */
- /* MSB LSB */
- /* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */
- /* | D7| D6| D5| D4| D3| D2| D1| D0|D15|D14|D13|D12|D11|D10| D9| D8| */
- /* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */
- struct
- {
-#ifdef BIG_ENDIAN_HOST
- unsigned int D7:1; /* PS1 */
- unsigned int D6:1; /* HD */
- unsigned int D5:1; /* FD */
- unsigned int D4:1;
- unsigned int D3:1;
- unsigned int D2:1;
- unsigned int D1:1;
- unsigned int D0:1;
- unsigned int D15:1; /* NP */
- unsigned int D14:1; /* ACK */
- unsigned int D13:1; /* RF2 */
- unsigned int D12:1; /* RF1 */
- unsigned int D11:1;
- unsigned int D10:1;
- unsigned int D9:1;
- unsigned int D8:1; /* PS2 */
-#else /* BIG_ENDIAN_HOST */
- unsigned int D8:1; /* PS2 */
- unsigned int D9:1;
- unsigned int D10:1;
- unsigned int D11:1;
- unsigned int D12:1; /* RF1 */
- unsigned int D13:1; /* RF2 */
- unsigned int D14:1; /* ACK */
- unsigned int D15:1; /* NP */
- unsigned int D0:1;
- unsigned int D1:1;
- unsigned int D2:1;
- unsigned int D3:1;
- unsigned int D4:1;
- unsigned int D5:1; /* FD */
- unsigned int D6:1; /* HD */
- unsigned int D7:1; /* PS1 */
-#endif
- } bits;
-
- unsigned short AsUSHORT;
-
- #define D8_PS2 bits.D8
- #define D12_RF1 bits.D12
- #define D13_RF2 bits.D13
- #define D14_ACK bits.D14
- #define D15_NP bits.D15
- #define D5_FD bits.D5
- #define D6_HD bits.D6
- #define D7_PS1 bits.D7
- } TxConfig;
-
- /* Rx config data */
- union
- {
- /* The RxConfig register is arranged as follows: */
- /* */
- /* MSB LSB */
- /* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */
- /* | D7| D6| D5| D4| D3| D2| D1| D0|D15|D14|D13|D12|D11|D10| D9| D8| */
- /* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */
- struct
- {
-#ifdef BIG_ENDIAN_HOST
- unsigned int D7:1; /* PS1 */
- unsigned int D6:1; /* HD */
- unsigned int D5:1; /* FD */
- unsigned int D4:1;
- unsigned int D3:1;
- unsigned int D2:1;
- unsigned int D1:1;
- unsigned int D0:1;
- unsigned int D15:1; /* NP */
- unsigned int D14:1; /* ACK */
- unsigned int D13:1; /* RF2 */
- unsigned int D12:1; /* RF1 */
- unsigned int D11:1;
- unsigned int D10:1;
- unsigned int D9:1;
- unsigned int D8:1; /* PS2 */
-#else /* BIG_ENDIAN_HOST */
- unsigned int D8:1; /* PS2 */
- unsigned int D9:1;
- unsigned int D10:1;
- unsigned int D11:1;
- unsigned int D12:1; /* RF1 */
- unsigned int D13:1; /* RF2 */
- unsigned int D14:1; /* ACK */
- unsigned int D15:1; /* NP */
- unsigned int D0:1;
- unsigned int D1:1;
- unsigned int D2:1;
- unsigned int D3:1;
- unsigned int D4:1;
- unsigned int D5:1; /* FD */
- unsigned int D6:1; /* HD */
- unsigned int D7:1; /* PS1 */
-#endif
- } bits;
-
- unsigned short AsUSHORT;
- } RxConfig;
-
- #define AN_CONFIG_NP 0x0080
- #define AN_CONFIG_ACK 0x0040
- #define AN_CONFIG_RF2 0x0020
- #define AN_CONFIG_RF1 0x0010
- #define AN_CONFIG_PS2 0x0001
- #define AN_CONFIG_PS1 0x8000
- #define AN_CONFIG_HD 0x4000
- #define AN_CONFIG_FD 0x2000
-
-
- /* Management registers. */
-
- /* Control register. */
- union
- {
- struct
- {
- unsigned int an_enable:1;
- unsigned int loopback:1;
- unsigned int reset:1;
- unsigned int restart_an:1;
- } bits;
-
- unsigned short AsUSHORT;
-
- #define mr_an_enable Mr0.bits.an_enable
- #define mr_loopback Mr0.bits.loopback
- #define mr_main_reset Mr0.bits.reset
- #define mr_restart_an Mr0.bits.restart_an
- } Mr0;
-
- /* Status register. */
- union
- {
- struct
- {
- unsigned int an_complete:1;
- unsigned int link_ok:1;
- } bits;
-
- unsigned short AsUSHORT;
-
- #define mr_an_complete Mr1.bits.an_complete
- #define mr_link_ok Mr1.bits.link_ok
- } Mr1;
-
- /* Advertisement register. */
- union
- {
- struct
- {
- unsigned int reserved_4:5;
- unsigned int full_duplex:1;
- unsigned int half_duplex:1;
- unsigned int sym_pause:1;
- unsigned int asym_pause:1;
- unsigned int reserved_11:3;
- unsigned int remote_fault1:1;
- unsigned int remote_fault2:1;
- unsigned int reserved_14:1;
- unsigned int next_page:1;
- } bits;
-
- unsigned short AsUSHORT;
-
- #define mr_adv_full_duplex Mr4.bits.full_duplex
- #define mr_adv_half_duplex Mr4.bits.half_duplex
- #define mr_adv_sym_pause Mr4.bits.sym_pause
- #define mr_adv_asym_pause Mr4.bits.asym_pause
- #define mr_adv_remote_fault1 Mr4.bits.remote_fault1
- #define mr_adv_remote_fault2 Mr4.bits.remote_fault2
- #define mr_adv_next_page Mr4.bits.next_page
- } Mr4;
-
- /* Link partner advertisement register. */
- union
- {
- struct
- {
- unsigned int reserved_4:5;
- unsigned int lp_full_duplex:1;
- unsigned int lp_half_duplex:1;
- unsigned int lp_sym_pause:1;
- unsigned int lp_asym_pause:1;
- unsigned int reserved_11:3;
- unsigned int lp_remote_fault1:1;
- unsigned int lp_remote_fault2:1;
- unsigned int lp_ack:1;
- unsigned int lp_next_page:1;
- } bits;
-
- unsigned short AsUSHORT;
-
- #define mr_lp_adv_full_duplex Mr5.bits.lp_full_duplex
- #define mr_lp_adv_half_duplex Mr5.bits.lp_half_duplex
- #define mr_lp_adv_sym_pause Mr5.bits.lp_sym_pause
- #define mr_lp_adv_asym_pause Mr5.bits.lp_asym_pause
- #define mr_lp_adv_remote_fault1 Mr5.bits.lp_remote_fault1
- #define mr_lp_adv_remote_fault2 Mr5.bits.lp_remote_fault2
- #define mr_lp_adv_next_page Mr5.bits.lp_next_page
- } Mr5;
-
- /* Auto-negotiation expansion register. */
- union
- {
- struct
- {
- unsigned int reserved_0:1;
- unsigned int page_received:1;
- unsigned int next_pageable:1;
- unsigned int reserved_15:13;
- } bits;
-
- unsigned short AsUSHORT;
- } Mr6;
-
- /* Auto-negotiation next page transmit register. */
- union
- {
- struct
- {
- unsigned int code_field:11;
- unsigned int toggle:1;
- unsigned int ack2:1;
- unsigned int message_page:1;
- unsigned int reserved_14:1;
- unsigned int next_page:1;
- } bits;
-
- unsigned short AsUSHORT;
-
- #define mr_np_tx Mr7.AsUSHORT
- } Mr7;
-
- /* Auto-negotiation link partner ability register. */
- union
- {
- struct
- {
- unsigned int code_field:11;
- unsigned int toggle:1;
- unsigned int ack2:1;
- unsigned int message_page:1;
- unsigned int ack:1;
- unsigned int next_page:1;
- } bits;
-
- unsigned short AsUSHORT;
-
- #define mr_lp_np_rx Mr8.AsUSHORT
- } Mr8;
-
- /* Extended status register. */
- union
- {
- struct
- {
- unsigned int reserved_11:12;
- unsigned int base1000_t_hd:1;
- unsigned int base1000_t_fd:1;
- unsigned int base1000_x_hd:1;
- unsigned int base1000_x_fd:1;
- } bits;
-
- unsigned short AsUSHORT;
- } Mr15;
-
- /* Miscellaneous state variables. */
- union
- {
- struct
- {
- unsigned int toggle_tx:1;
- unsigned int toggle_rx:1;
- unsigned int np_rx:1;
- unsigned int page_rx:1;
- unsigned int np_loaded:1;
- } bits;
-
- unsigned short AsUSHORT;
-
- #define mr_toggle_tx MrMisc.bits.toggle_tx
- #define mr_toggle_rx MrMisc.bits.toggle_rx
- #define mr_np_rx MrMisc.bits.np_rx
- #define mr_page_rx MrMisc.bits.page_rx
- #define mr_np_loaded MrMisc.bits.np_loaded
- } MrMisc;
-
-
- /* Implement specifics */
-
- /* Pointer to the operating system specific data structure. */
- void *pContext;
-} AN_STATE_INFO, *PAN_STATE_INFO;
-
-
-/******************************************************************************/
-/* Return code of Autoneg8023z. */
-/******************************************************************************/
-
-typedef enum
-{
- AUTONEG_STATUS_OK = 0,
- AUTONEG_STATUS_DONE = 1,
- AUTONEG_STATUS_TIMER_ENABLED = 2,
- AUTONEG_STATUS_FAILED = 0xfffffff
-} AUTONEG_STATUS, *PAUTONEG_STATUS;
-
-
-/******************************************************************************/
-/* Function prototypes. */
-/******************************************************************************/
-
-AUTONEG_STATUS Autoneg8023z(PAN_STATE_INFO pAnInfo);
-void AutonegInit(PAN_STATE_INFO pAnInfo);
-
-
-/******************************************************************************/
-/* The following functions are defined in the os-dependent module. */
-/******************************************************************************/
-
-void MM_AnTxConfig(PAN_STATE_INFO pAnInfo);
-void MM_AnTxIdle(PAN_STATE_INFO pAnInfo);
-char MM_AnRxConfig(PAN_STATE_INFO pAnInfo, unsigned short *pRxConfig);
-
-
-#endif /* AUTONEG_H */
+++ /dev/null
-
-/******************************************************************************/
-/* */
-/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom */
-/* Corporation. */
-/* All rights reserved. */
-/* */
-/* This program is free software; you can redistribute it and/or modify */
-/* it under the terms of the GNU General Public License as published by */
-/* the Free Software Foundation, located in the file LICENSE. */
-/* */
-/* History: */
-/* 02/25/00 Hav Khauv Initial version. */
-/******************************************************************************/
-
-#ifndef BITS_H
-#define BITS_H
-
-
-/******************************************************************************/
-/* Bit Mask definitions */
-/******************************************************************************/
-#define BIT_NONE 0x00
-#define BIT_0 0x01
-#define BIT_1 0x02
-#define BIT_2 0x04
-#define BIT_3 0x08
-#define BIT_4 0x10
-#define BIT_5 0x20
-#define BIT_6 0x40
-#define BIT_7 0x80
-#define BIT_8 0x0100
-#define BIT_9 0x0200
-#define BIT_10 0x0400
-#define BIT_11 0x0800
-#define BIT_12 0x1000
-#define BIT_13 0x2000
-#define BIT_14 0x4000
-#define BIT_15 0x8000
-#define BIT_16 0x010000
-#define BIT_17 0x020000
-#define BIT_18 0x040000
-#define BIT_19 0x080000
-#define BIT_20 0x100000
-#define BIT_21 0x200000
-#define BIT_22 0x400000
-#define BIT_23 0x800000
-#define BIT_24 0x01000000
-#define BIT_25 0x02000000
-#define BIT_26 0x04000000
-#define BIT_27 0x08000000
-#define BIT_28 0x10000000
-#define BIT_29 0x20000000
-#define BIT_30 0x40000000
-#define BIT_31 0x80000000
-
-#endif /* BITS_H */
+++ /dev/null
-
-/******************************************************************************/
-/* */
-/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom */
-/* Corporation. */
-/* All rights reserved. */
-/* */
-/* This program is free software; you can redistribute it and/or modify */
-/* it under the terms of the GNU General Public License as published by */
-/* the Free Software Foundation, located in the file LICENSE. */
-/* */
-/* History: */
-/* 02/25/00 Hav Khauv Initial version. */
-/******************************************************************************/
-
-#ifndef DEBUG_H
-#define DEBUG_H
-
-#ifdef VXWORKS
-#include <vxWorks.h>
-#endif
-
-/******************************************************************************/
-/* Debug macros */
-/******************************************************************************/
-
-/* Code path for controlling output debug messages. */
-/* Define your code path here. */
-#define CP_INIT 0x010000
-#define CP_SEND 0x020000
-#define CP_RCV 0x040000
-#define CP_INT 0x080000
-#define CP_UINIT 0x100000
-#define CP_RESET 0x200000
-
-#define CP_ALL (CP_INIT | CP_SEND | CP_RCV | CP_INT | \
- CP_RESET | CP_UINIT)
-
-#define CP_MASK 0xffff0000
-
-
-/* Debug message levels. */
-#define LV_VERBOSE 0x03
-#define LV_INFORM 0x02
-#define LV_WARN 0x01
-#define LV_FATAL 0x00
-
-#define LV_MASK 0xffff
-
-
-/* Code path and messsage level combined. These are the first argument of */
-/* the DbgMessage macro. */
-#define INIT_V (CP_INIT | LV_VERBOSE)
-#define INIT_I (CP_INIT | LV_INFORM)
-#define INIT_W (CP_INIT | LV_WARN)
-#define SEND_V (CP_SEND | LV_VERBOSE)
-#define SEND_I (CP_SEND | LV_INFORM)
-#define SEND_W (CP_SEND | LV_WARN)
-#define RCV_V (CP_RCV | LV_VERBOSE)
-#define RCV_I (CP_RCV | LV_INFORM)
-#define RCV_W (CP_RCV | LV_WARN)
-#define INT_V (CP_INT | LV_VERBOSE)
-#define INT_I (CP_INT | LV_INFORM)
-#define INT_W (CP_INT | LV_WARN)
-#define UINIT_V (CP_UINIT | LV_VERBOSE)
-#define UINIT_I (CP_UINIT | LV_INFORM)
-#define UINIT_W (CP_UINIT | LV_WARN)
-#define RESET_V (CP_RESET | LV_VERBOSE)
-#define RESET_I (CP_RESET | LV_INFORM)
-#define RESET_W (CP_RESET | LV_WARN)
-#define CPALL_V (CP_ALL | LV_VERBOSE)
-#define CPALL_I (CP_ALL | LV_INFORM)
-#define CPALL_W (CP_ALL | LV_WARN)
-
-
-/* All code path message levels. */
-#define FATAL (CP_ALL | LV_FATAL)
-#define WARN (CP_ALL | LV_WARN)
-#define INFORM (CP_ALL | LV_INFORM)
-#define VERBOSE (CP_ALL | LV_VERBOSE)
-
-
-/* These constants control the message output. */
-/* Set your debug message output level and code path here. */
-#ifndef DBG_MSG_CP
-#define DBG_MSG_CP CP_ALL /* Where to output messages. */
-#endif
-
-#ifndef DBG_MSG_LV
-#define DBG_MSG_LV LV_VERBOSE /* Level of message output. */
-#endif
-
-/* DbgMessage macro. */
-#if DBG
-#define DbgMessage(CNTRL, MESSAGE) \
- if((CNTRL & DBG_MSG_CP) && ((CNTRL & LV_MASK) <= DBG_MSG_LV)) \
- printf MESSAGE
-#define DbgBreak() DbgBreakPoint()
-#undef STATIC
-#define STATIC
-#else
-#define DbgMessage(CNTRL, MESSAGE)
-#define DbgBreak()
-#undef STATIC
-#define STATIC static
-#endif /* DBG */
-
-
-#endif /* DEBUG_H */
+++ /dev/null
-
-/******************************************************************************/
-/* */
-/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom */
-/* Corporation. */
-/* All rights reserved. */
-/* */
-/* This program is free software; you can redistribute it and/or modify */
-/* it under the terms of the GNU General Public License as published by */
-/* the Free Software Foundation, located in the file LICENSE. */
-/* */
-/* History: */
-/* 02/25/00 Hav Khauv Initial version. */
-/******************************************************************************/
-
-#ifndef LM_H
-#define LM_H
-
-#include "bcm570x_queue.h"
-#include "bcm570x_bits.h"
-
-/******************************************************************************/
-/* Basic types. */
-/******************************************************************************/
-
-typedef char LM_CHAR, *PLM_CHAR;
-typedef unsigned int LM_UINT, *PLM_UINT;
-typedef unsigned char LM_UINT8, *PLM_UINT8;
-typedef unsigned short LM_UINT16, *PLM_UINT16;
-typedef unsigned int LM_UINT32, *PLM_UINT32;
-typedef unsigned int LM_COUNTER, *PLM_COUNTER;
-typedef void LM_VOID, *PLM_VOID;
-typedef char LM_BOOL, *PLM_BOOL;
-
-/* 64bit value. */
-typedef struct {
-#ifdef BIG_ENDIAN_HOST
- LM_UINT32 High;
- LM_UINT32 Low;
-#else /* BIG_ENDIAN_HOST */
- LM_UINT32 Low;
- LM_UINT32 High;
-#endif /* !BIG_ENDIAN_HOST */
-} LM_UINT64, *PLM_UINT64;
-
-typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS;
-
-/* void LM_INC_PHYSICAL_ADDRESS(PLM_PHYSICAL_ADDRESS pAddr,LM_UINT32 IncSize) */
-#define LM_INC_PHYSICAL_ADDRESS(pAddr, IncSize) \
- { \
- LM_UINT32 OrgLow; \
- \
- OrgLow = (pAddr)->Low; \
- (pAddr)->Low += IncSize; \
- if((pAddr)->Low < OrgLow) { \
- (pAddr)->High++; /* Wrap around. */ \
- } \
- }
-
-#ifndef NULL
-#define NULL ((void *) 0)
-#endif /* NULL */
-
-#ifndef OFFSETOF
-#define OFFSETOF(_s, _m) (MM_UINT_PTR(&(((_s *) 0)->_m)))
-#endif /* OFFSETOF */
-
-/******************************************************************************/
-/* Simple macros. */
-/******************************************************************************/
-
-#define IS_ETH_BROADCAST(_pEthAddr) \
- (((unsigned char *) (_pEthAddr))[0] == ((unsigned char) 0xff))
-
-#define IS_ETH_MULTICAST(_pEthAddr) \
- (((unsigned char *) (_pEthAddr))[0] & ((unsigned char) 0x01))
-
-#define IS_ETH_ADDRESS_EQUAL(_pEtherAddr1, _pEtherAddr2) \
- ((((unsigned char *) (_pEtherAddr1))[0] == \
- ((unsigned char *) (_pEtherAddr2))[0]) && \
- (((unsigned char *) (_pEtherAddr1))[1] == \
- ((unsigned char *) (_pEtherAddr2))[1]) && \
- (((unsigned char *) (_pEtherAddr1))[2] == \
- ((unsigned char *) (_pEtherAddr2))[2]) && \
- (((unsigned char *) (_pEtherAddr1))[3] == \
- ((unsigned char *) (_pEtherAddr2))[3]) && \
- (((unsigned char *) (_pEtherAddr1))[4] == \
- ((unsigned char *) (_pEtherAddr2))[4]) && \
- (((unsigned char *) (_pEtherAddr1))[5] == \
- ((unsigned char *) (_pEtherAddr2))[5]))
-
-#define COPY_ETH_ADDRESS(_Src, _Dst) \
- ((unsigned char *) (_Dst))[0] = ((unsigned char *) (_Src))[0]; \
- ((unsigned char *) (_Dst))[1] = ((unsigned char *) (_Src))[1]; \
- ((unsigned char *) (_Dst))[2] = ((unsigned char *) (_Src))[2]; \
- ((unsigned char *) (_Dst))[3] = ((unsigned char *) (_Src))[3]; \
- ((unsigned char *) (_Dst))[4] = ((unsigned char *) (_Src))[4]; \
- ((unsigned char *) (_Dst))[5] = ((unsigned char *) (_Src))[5];
-
-/******************************************************************************/
-/* Constants. */
-/******************************************************************************/
-
-#define ETHERNET_ADDRESS_SIZE 6
-#define ETHERNET_PACKET_HEADER_SIZE 14
-#define MIN_ETHERNET_PACKET_SIZE 64 /* with 4 byte crc. */
-#define MAX_ETHERNET_PACKET_SIZE 1518 /* with 4 byte crc. */
-#define MIN_ETHERNET_PACKET_SIZE_NO_CRC 60
-#define MAX_ETHERNET_PACKET_SIZE_NO_CRC 1514
-#define MAX_ETHERNET_PACKET_BUFFER_SIZE 1536 /* A nice even number. */
-
-#ifndef LM_MAX_MC_TABLE_SIZE
-#define LM_MAX_MC_TABLE_SIZE 32
-#endif /* LM_MAX_MC_TABLE_SIZE */
-#define LM_MC_ENTRY_SIZE (ETHERNET_ADDRESS_SIZE+1)
-#define LM_MC_INSTANCE_COUNT_INDEX (LM_MC_ENTRY_SIZE-1)
-
-/* Receive filter masks. */
-#define LM_ACCEPT_UNICAST 0x0001
-#define LM_ACCEPT_MULTICAST 0x0002
-#define LM_ACCEPT_ALL_MULTICAST 0x0004
-#define LM_ACCEPT_BROADCAST 0x0008
-#define LM_ACCEPT_ERROR_PACKET 0x0010
-
-#define LM_PROMISCUOUS_MODE 0x10000
-
-/******************************************************************************/
-/* PCI registers. */
-/******************************************************************************/
-
-#define PCI_VENDOR_ID_REG 0x00
-#define PCI_DEVICE_ID_REG 0x02
-
-#define PCI_COMMAND_REG 0x04
-#define PCI_IO_SPACE_ENABLE 0x0001
-#define PCI_MEM_SPACE_ENABLE 0x0002
-#define PCI_BUSMASTER_ENABLE 0x0004
-#define PCI_MEMORY_WRITE_INVALIDATE 0x0010
-#define PCI_PARITY_ERROR_ENABLE 0x0040
-#define PCI_SYSTEM_ERROR_ENABLE 0x0100
-#define PCI_FAST_BACK_TO_BACK_ENABLE 0x0200
-
-#define PCI_STATUS_REG 0x06
-#define PCI_REV_ID_REG 0x08
-
-#define PCI_CACHE_LINE_SIZE_REG 0x0c
-
-#define PCI_IO_BASE_ADDR_REG 0x10
-#define PCI_IO_BASE_ADDR_MASK 0xfffffff0
-
-#define PCI_MEM_BASE_ADDR_LOW 0x10
-#define PCI_MEM_BASE_ADDR_HIGH 0x14
-
-#define PCI_SUBSYSTEM_VENDOR_ID_REG 0x2c
-#define PCI_SUBSYSTEM_ID_REG 0x2e
-#define PCI_INT_LINE_REG 0x3c
-
-#define PCIX_CAP_REG 0x40
-#define PCIX_ENABLE_RELAXED_ORDERING BIT_17
-
-/******************************************************************************/
-/* Fragment structure. */
-/******************************************************************************/
-
-typedef struct {
- LM_UINT32 FragSize;
- LM_PHYSICAL_ADDRESS FragBuf;
-} LM_FRAG, *PLM_FRAG;
-
-typedef struct {
- /* FragCount is initialized for the caller to the maximum array size, on */
- /* return FragCount is the number of the actual fragments in the array. */
- LM_UINT32 FragCount;
-
- /* Total buffer size. */
- LM_UINT32 TotalSize;
-
- /* Fragment array buffer. */
- LM_FRAG Fragments[1];
-} LM_FRAG_LIST, *PLM_FRAG_LIST;
-
-#define DECLARE_FRAG_LIST_BUFFER_TYPE(_FRAG_LIST_TYPE_NAME, _MAX_FRAG_COUNT) \
- typedef struct { \
- LM_FRAG_LIST FragList; \
- LM_FRAG FragListBuffer[_MAX_FRAG_COUNT-1]; \
- } _FRAG_LIST_TYPE_NAME, *P##_FRAG_LIST_TYPE_NAME
-
-/******************************************************************************/
-/* Status codes. */
-/******************************************************************************/
-
-#define LM_STATUS_SUCCESS 0
-#define LM_STATUS_FAILURE 1
-
-#define LM_STATUS_INTERRUPT_ACTIVE 2
-#define LM_STATUS_INTERRUPT_NOT_ACTIVE 3
-
-#define LM_STATUS_LINK_ACTIVE 4
-#define LM_STATUS_LINK_DOWN 5
-#define LM_STATUS_LINK_SETTING_MISMATCH 6
-
-#define LM_STATUS_TOO_MANY_FRAGMENTS 7
-#define LM_STATUS_TRANSMIT_ABORTED 8
-#define LM_STATUS_TRANSMIT_ERROR 9
-#define LM_STATUS_RECEIVE_ABORTED 10
-#define LM_STATUS_RECEIVE_ERROR 11
-#define LM_STATUS_INVALID_PACKET_SIZE 12
-#define LM_STATUS_OUT_OF_MAP_REGISTERS 13
-#define LM_STATUS_UNKNOWN_ADAPTER 14
-
-typedef LM_UINT LM_STATUS, *PLM_STATUS;
-
-/******************************************************************************/
-/* Requested media type. */
-/******************************************************************************/
-
-#define LM_REQUESTED_MEDIA_TYPE_AUTO 0
-#define LM_REQUESTED_MEDIA_TYPE_BNC 1
-#define LM_REQUESTED_MEDIA_TYPE_UTP_AUTO 2
-#define LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS 3
-#define LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS_FULL_DUPLEX 4
-#define LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS 5
-#define LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS_FULL_DUPLEX 6
-#define LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS 7
-#define LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS_FULL_DUPLEX 8
-#define LM_REQUESTED_MEDIA_TYPE_FIBER_100MBPS 9
-#define LM_REQUESTED_MEDIA_TYPE_FIBER_100MBPS_FULL_DUPLEX 10
-#define LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS 11
-#define LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS_FULL_DUPLEX 12
-#define LM_REQUESTED_MEDIA_TYPE_MAC_LOOPBACK 0xfffe
-#define LM_REQUESTED_MEDIA_TYPE_PHY_LOOPBACK 0xffff
-
-typedef LM_UINT32 LM_REQUESTED_MEDIA_TYPE, *PLM_REQUESTED_MEDIA_TYPE;
-
-/******************************************************************************/
-/* Media type. */
-/******************************************************************************/
-
-#define LM_MEDIA_TYPE_UNKNOWN -1
-#define LM_MEDIA_TYPE_AUTO 0
-#define LM_MEDIA_TYPE_UTP 1
-#define LM_MEDIA_TYPE_BNC 2
-#define LM_MEDIA_TYPE_AUI 3
-#define LM_MEDIA_TYPE_FIBER 4
-
-typedef LM_UINT32 LM_MEDIA_TYPE, *PLM_MEDIA_TYPE;
-
-/******************************************************************************/
-/* Line speed. */
-/******************************************************************************/
-
-#define LM_LINE_SPEED_UNKNOWN 0
-#define LM_LINE_SPEED_10MBPS 1
-#define LM_LINE_SPEED_100MBPS 2
-#define LM_LINE_SPEED_1000MBPS 3
-
-typedef LM_UINT32 LM_LINE_SPEED, *PLM_LINE_SPEED;
-
-/******************************************************************************/
-/* Duplex mode. */
-/******************************************************************************/
-
-#define LM_DUPLEX_MODE_UNKNOWN 0
-#define LM_DUPLEX_MODE_HALF 1
-#define LM_DUPLEX_MODE_FULL 2
-
-typedef LM_UINT32 LM_DUPLEX_MODE, *PLM_DUPLEX_MODE;
-
-/******************************************************************************/
-/* Power state. */
-/******************************************************************************/
-
-#define LM_POWER_STATE_D0 0
-#define LM_POWER_STATE_D1 1
-#define LM_POWER_STATE_D2 2
-#define LM_POWER_STATE_D3 3
-
-typedef LM_UINT32 LM_POWER_STATE, *PLM_POWER_STATE;
-
-/******************************************************************************/
-/* Task offloading. */
-/******************************************************************************/
-
-#define LM_TASK_OFFLOAD_NONE 0x0000
-#define LM_TASK_OFFLOAD_TX_IP_CHECKSUM 0x0001
-#define LM_TASK_OFFLOAD_RX_IP_CHECKSUM 0x0002
-#define LM_TASK_OFFLOAD_TX_TCP_CHECKSUM 0x0004
-#define LM_TASK_OFFLOAD_RX_TCP_CHECKSUM 0x0008
-#define LM_TASK_OFFLOAD_TX_UDP_CHECKSUM 0x0010
-#define LM_TASK_OFFLOAD_RX_UDP_CHECKSUM 0x0020
-#define LM_TASK_OFFLOAD_TCP_SEGMENTATION 0x0040
-
-typedef LM_UINT32 LM_TASK_OFFLOAD, *PLM_TASK_OFFLOAD;
-
-/******************************************************************************/
-/* Flow control. */
-/******************************************************************************/
-
-#define LM_FLOW_CONTROL_NONE 0x00
-#define LM_FLOW_CONTROL_RECEIVE_PAUSE 0x01
-#define LM_FLOW_CONTROL_TRANSMIT_PAUSE 0x02
-#define LM_FLOW_CONTROL_RX_TX_PAUSE (LM_FLOW_CONTROL_RECEIVE_PAUSE | \
- LM_FLOW_CONTROL_TRANSMIT_PAUSE)
-
-/* This value can be or-ed with RECEIVE_PAUSE and TRANSMIT_PAUSE. If the */
-/* auto-negotiation is disabled and the RECEIVE_PAUSE and TRANSMIT_PAUSE */
-/* bits are set, then flow control is enabled regardless of link partner's */
-/* flow control capability. */
-#define LM_FLOW_CONTROL_AUTO_PAUSE 0x80000000
-
-typedef LM_UINT32 LM_FLOW_CONTROL, *PLM_FLOW_CONTROL;
-
-/******************************************************************************/
-/* Wake up mode. */
-/******************************************************************************/
-
-#define LM_WAKE_UP_MODE_NONE 0
-#define LM_WAKE_UP_MODE_MAGIC_PACKET 1
-#define LM_WAKE_UP_MODE_NWUF 2
-#define LM_WAKE_UP_MODE_LINK_CHANGE 4
-
-typedef LM_UINT32 LM_WAKE_UP_MODE, *PLM_WAKE_UP_MODE;
-
-/******************************************************************************/
-/* Counters. */
-/******************************************************************************/
-
-#define LM_COUNTER_FRAMES_XMITTED_OK 0
-#define LM_COUNTER_FRAMES_RECEIVED_OK 1
-#define LM_COUNTER_ERRORED_TRANSMIT_COUNT 2
-#define LM_COUNTER_ERRORED_RECEIVE_COUNT 3
-#define LM_COUNTER_RCV_CRC_ERROR 4
-#define LM_COUNTER_ALIGNMENT_ERROR 5
-#define LM_COUNTER_SINGLE_COLLISION_FRAMES 6
-#define LM_COUNTER_MULTIPLE_COLLISION_FRAMES 7
-#define LM_COUNTER_FRAMES_DEFERRED 8
-#define LM_COUNTER_MAX_COLLISIONS 9
-#define LM_COUNTER_RCV_OVERRUN 10
-#define LM_COUNTER_XMIT_UNDERRUN 11
-#define LM_COUNTER_UNICAST_FRAMES_XMIT 12
-#define LM_COUNTER_MULTICAST_FRAMES_XMIT 13
-#define LM_COUNTER_BROADCAST_FRAMES_XMIT 14
-#define LM_COUNTER_UNICAST_FRAMES_RCV 15
-#define LM_COUNTER_MULTICAST_FRAMES_RCV 16
-#define LM_COUNTER_BROADCAST_FRAMES_RCV 17
-
-typedef LM_UINT32 LM_COUNTER_TYPE, *PLM_COUNTER_TYPE;
-
-/******************************************************************************/
-/* Forward definition. */
-/******************************************************************************/
-
-typedef struct _LM_DEVICE_BLOCK *PLM_DEVICE_BLOCK;
-typedef struct _LM_PACKET *PLM_PACKET;
-
-/******************************************************************************/
-/* Function prototypes. */
-/******************************************************************************/
-
-LM_STATUS LM_GetAdapterInfo (PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_InitializeAdapter (PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_ResetAdapter (PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_DisableInterrupt (PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_EnableInterrupt (PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_SendPacket (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
-LM_STATUS LM_ServiceInterrupts (PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_QueueRxPackets (PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_SetReceiveMask (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Mask);
-LM_STATUS LM_Halt (PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_Abort (PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_MulticastAdd (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress);
-LM_STATUS LM_MulticastDel (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress);
-LM_STATUS LM_MulticastClear (PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_SetMacAddress (PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_LoopbackAddress (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pAddress);
-
-LM_UINT32 LM_GetCrcCounter (PLM_DEVICE_BLOCK pDevice);
-
-LM_WAKE_UP_MODE LM_PMCapabilities (PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_NwufAdd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 ByteMaskSize,
- LM_UINT8 * pByteMask, LM_UINT8 * pPattern);
-LM_STATUS LM_NwufRemove (PLM_DEVICE_BLOCK pDevice, LM_UINT32 ByteMaskSize,
- LM_UINT8 * pByteMask, LM_UINT8 * pPattern);
-LM_STATUS LM_SetPowerState (PLM_DEVICE_BLOCK pDevice,
- LM_POWER_STATE PowerLevel);
-
-LM_VOID LM_ReadPhy (PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg,
- PLM_UINT32 pData32);
-LM_VOID LM_WritePhy (PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg,
- LM_UINT32 Data32);
-
-LM_STATUS LM_ControlLoopBack (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Control);
-LM_STATUS LM_SetupPhy (PLM_DEVICE_BLOCK pDevice);
-int LM_BlinkLED (PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDuration);
-
-/******************************************************************************/
-/* These are the OS specific functions called by LMAC. */
-/******************************************************************************/
-
-LM_STATUS MM_ReadConfig16 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset,
- LM_UINT16 * pValue16);
-LM_STATUS MM_WriteConfig16 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset,
- LM_UINT16 Value16);
-LM_STATUS MM_ReadConfig32 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset,
- LM_UINT32 * pValue32);
-LM_STATUS MM_WriteConfig32 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset,
- LM_UINT32 Value32);
-LM_STATUS MM_MapMemBase (PLM_DEVICE_BLOCK pDevice);
-LM_STATUS MM_MapIoBase (PLM_DEVICE_BLOCK pDevice);
-LM_STATUS MM_IndicateRxPackets (PLM_DEVICE_BLOCK pDevice);
-LM_STATUS MM_IndicateTxPackets (PLM_DEVICE_BLOCK pDevice);
-LM_STATUS MM_StartTxDma (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
-LM_STATUS MM_CompleteTxDma (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
-LM_STATUS MM_AllocateMemory (PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize,
- PLM_VOID * pMemoryBlockVirt);
-LM_STATUS MM_AllocateSharedMemory (PLM_DEVICE_BLOCK pDevice,
- LM_UINT32 BlockSize,
- PLM_VOID * pMemoryBlockVirt,
- PLM_PHYSICAL_ADDRESS pMemoryBlockPhy,
- LM_BOOL Cached);
-LM_STATUS MM_GetConfig (PLM_DEVICE_BLOCK pDevice);
-LM_STATUS MM_IndicateStatus (PLM_DEVICE_BLOCK pDevice, LM_STATUS Status);
-LM_STATUS MM_InitializeUmPackets (PLM_DEVICE_BLOCK pDevice);
-LM_STATUS MM_FreeRxBuffer (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
-LM_STATUS MM_CoalesceTxBuffer (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
-LM_STATUS LM_MbufWorkAround (PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_SetLinkSpeed (PLM_DEVICE_BLOCK pDevice,
- LM_REQUESTED_MEDIA_TYPE RequestedMediaType);
-
-#if INCLUDE_5703_A0_FIX
-LM_STATUS LM_Load5703DmaWFirmware (PLM_DEVICE_BLOCK pDevice);
-#endif
-
-#endif /* LM_H */
+++ /dev/null
-
-/******************************************************************************/
-/* */
-/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom */
-/* Corporation. */
-/* All rights reserved. */
-/* */
-/* This program is free software; you can redistribute it and/or modify */
-/* it under the terms of the GNU General Public License as published by */
-/* the Free Software Foundation, located in the file LICENSE. */
-/* */
-/******************************************************************************/
-
-#ifndef MM_H
-#define MM_H
-
-#define __raw_readl readl
-#define __raw_writel writel
-
-#define BIG_ENDIAN_HOST 1
-#define readl(addr) (*(volatile unsigned int*)(addr))
-#define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b))
-
-/* Define memory barrier function here if needed */
-#define wmb()
-#define membar()
-#include <common.h>
-#include <asm/types.h>
-#include "bcm570x_lm.h"
-#include "bcm570x_queue.h"
-#include "tigon3.h"
-#include <pci.h>
-
-#define FALSE 0
-#define TRUE 1
-#define ERROR -1
-
-#if DBG
-#define STATIC
-#else
-#define STATIC static
-#endif
-
-extern int MM_Packet_Desc_Size;
-
-#define MM_PACKET_DESC_SIZE MM_Packet_Desc_Size
-
-DECLARE_QUEUE_TYPE (UM_RX_PACKET_Q, MAX_RX_PACKET_DESC_COUNT + 1);
-
-#define MAX_MEM 16
-
-/* Synch */
-typedef int mutex_t;
-typedef int spinlock_t;
-
-/* Embedded device control */
-typedef struct _UM_DEVICE_BLOCK {
- LM_DEVICE_BLOCK lm_dev;
- pci_dev_t pdev;
- char *name;
- void *mem_list[MAX_MEM];
- dma_addr_t dma_list[MAX_MEM];
- int mem_size_list[MAX_MEM];
- int mem_list_num;
- int mtu;
- int index;
- int opened;
- int delayed_link_ind; /* Delay link status during initial load */
- int adapter_just_inited; /* the first few seconds after init. */
- int spurious_int; /* new -- unsupported */
- int timer_interval;
- int adaptive_expiry;
- int crc_counter_expiry; /* new -- unsupported */
- int poll_tib_expiry; /* new -- unsupported */
- int tx_full;
- int tx_queued;
- int line_speed; /* in Mbps, 0 if link is down */
- UM_RX_PACKET_Q rx_out_of_buf_q;
- int rx_out_of_buf;
- int rx_low_buf_thresh; /* changed to rx_buf_repl_thresh */
- int rx_buf_repl_panic_thresh;
- int rx_buf_align; /* new -- unsupported */
- int do_global_lock;
- mutex_t global_lock;
- mutex_t undi_lock;
- long undi_flags;
- volatile int interrupt;
- int tasklet_pending;
- int tasklet_busy; /* new -- unsupported */
- int rx_pkt;
- int tx_pkt;
-#ifdef NICE_SUPPORT /* unsupported, this is a linux ioctl */
- void (*nice_rx) (void *, void *);
- void *nice_ctx;
-#endif /* NICE_SUPPORT */
- int rx_adaptive_coalesce;
- unsigned int rx_last_cnt;
- unsigned int tx_last_cnt;
- unsigned int rx_curr_coalesce_frames;
- unsigned int rx_curr_coalesce_ticks;
- unsigned int tx_curr_coalesce_frames; /* new -- unsupported */
-#if TIGON3_DEBUG /* new -- unsupported */
- uint tx_zc_count;
- uint tx_chksum_count;
- uint tx_himem_count;
- uint rx_good_chksum_count;
-#endif
- unsigned int rx_bad_chksum_count; /* new -- unsupported */
- unsigned int rx_misc_errors; /* new -- unsupported */
-} UM_DEVICE_BLOCK, *PUM_DEVICE_BLOCK;
-
-/* Physical/PCI DMA address */
-typedef union {
- dma_addr_t dma_map;
-} dma_map_t;
-
-/* Packet */
-typedef struct
- _UM_PACKET {
- LM_PACKET lm_packet;
- void *skbuff; /* Address of packet buffer */
-} UM_PACKET, *PUM_PACKET;
-
-#define MM_ACQUIRE_UNDI_LOCK(_pDevice)
-#define MM_RELEASE_UNDI_LOCK(_pDevice)
-#define MM_ACQUIRE_INT_LOCK(_pDevice)
-#define MM_RELEASE_INT_LOCK(_pDevice)
-#define MM_UINT_PTR(_ptr) ((unsigned long) (_ptr))
-
-/* Macro for setting 64bit address struct */
-#define set_64bit_addr(paddr, low, high) \
- (paddr)->Low = low; \
- (paddr)->High = high;
-
-/* Assume that PCI controller's view of host memory is same as host */
-
-#define MEM_TO_PCI_PHYS(addr) (addr)
-
-extern void MM_SetAddr (LM_PHYSICAL_ADDRESS * paddr, dma_addr_t addr);
-extern void MM_SetT3Addr (T3_64BIT_HOST_ADDR * paddr, dma_addr_t addr);
-extern void MM_MapTxDma (PLM_DEVICE_BLOCK pDevice,
- struct _LM_PACKET *pPacket, T3_64BIT_HOST_ADDR * paddr,
- LM_UINT32 * len, int frag);
-extern void MM_MapRxDma (PLM_DEVICE_BLOCK pDevice,
- struct _LM_PACKET *pPacket,
- T3_64BIT_HOST_ADDR * paddr);
-
-/* BSP needs to provide sysUsecDelay and sysSerialPrintString */
-extern void sysSerialPrintString (char *s);
-#define MM_Wait(usec) udelay(usec)
-
-/* Define memory barrier function here if needed */
-#define wmb()
-
-#if 0
-#define cpu_to_le32(val) LONGSWAP(val)
-#endif
-#endif /* MM_H */
+++ /dev/null
-
-/******************************************************************************/
-/* */
-/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom */
-/* Corporation. */
-/* All rights reserved. */
-/* */
-/* This program is free software; you can redistribute it and/or modify */
-/* it under the terms of the GNU General Public License as published by */
-/* the Free Software Foundation, located in the file LICENSE. */
-/* */
-/* Queue functions. */
-/* void QQ_InitQueue(PQQ_CONTAINER pQueue) */
-/* char QQ_Full(PQQ_CONTAINER pQueue) */
-/* char QQ_Empty(PQQ_CONTAINER pQueue) */
-/* unsigned int QQ_GetSize(PQQ_CONTAINER pQueue) */
-/* unsigned int QQ_GetEntryCnt(PQQ_CONTAINER pQueue) */
-/* char QQ_PushHead(PQQ_CONTAINER pQueue, PQQ_ENTRY pEntry) */
-/* char QQ_PushTail(PQQ_CONTAINER pQueue, PQQ_ENTRY pEntry) */
-/* PQQ_ENTRY QQ_PopHead(PQQ_CONTAINER pQueue) */
-/* PQQ_ENTRY QQ_PopTail(PQQ_CONTAINER pQueue) */
-/* PQQ_ENTRY QQ_GetHead(PQQ_CONTAINER pQueue, unsigned int Idx) */
-/* PQQ_ENTRY QQ_GetTail(PQQ_CONTAINER pQueue, unsigned int Idx) */
-/* */
-/* */
-/* History: */
-/* 02/25/00 Hav Khauv Initial version. */
-/******************************************************************************/
-
-#ifndef BCM_QUEUE_H
-#define BCM_QUEUE_H
-#ifndef EMBEDDED
-#define EMBEDDED 1
-#endif
-
-/******************************************************************************/
-/* Queue definitions. */
-/******************************************************************************/
-
-/* Entry for queueing. */
-typedef void *PQQ_ENTRY;
-
-/* Linux Atomic Ops support */
-typedef struct { int counter; } atomic_t;
-
-
-/*
- * This combination of `inline' and `extern' has almost the effect of a
- * macro. The way to use it is to put a function definition in a header
- * file with these keywords, and put another copy of the definition
- * (lacking `inline' and `extern') in a library file. The definition in
- * the header file will cause most calls to the function to be inlined.
- * If any uses of the function remain, they will refer to the single copy
- * in the library.
- */
-extern __inline void
-atomic_set(atomic_t* entry, int val)
-{
- entry->counter = val;
-}
-extern __inline int
-atomic_read(atomic_t* entry)
-{
- return entry->counter;
-}
-extern __inline void
-atomic_inc(atomic_t* entry)
-{
- if(entry)
- entry->counter++;
-}
-
-extern __inline void
-atomic_dec(atomic_t* entry)
-{
- if(entry)
- entry->counter--;
-}
-
-extern __inline void
-atomic_sub(int a, atomic_t* entry)
-{
- if(entry)
- entry->counter -= a;
-}
-extern __inline void
-atomic_add(int a, atomic_t* entry)
-{
- if(entry)
- entry->counter += a;
-}
-
-
-/* Queue header -- base type. */
-typedef struct {
- unsigned int Head;
- unsigned int Tail;
- unsigned int Size;
- atomic_t EntryCnt;
- PQQ_ENTRY Array[1];
-} QQ_CONTAINER, *PQQ_CONTAINER;
-
-
-/* Declare queue type macro. */
-#define DECLARE_QUEUE_TYPE(_QUEUE_TYPE, _QUEUE_SIZE) \
- \
- typedef struct { \
- QQ_CONTAINER Container; \
- PQQ_ENTRY EntryBuffer[_QUEUE_SIZE]; \
- } _QUEUE_TYPE, *P##_QUEUE_TYPE
-
-
-/******************************************************************************/
-/* Compilation switches. */
-/******************************************************************************/
-
-#if DBG
-#undef QQ_NO_OVERFLOW_CHECK
-#undef QQ_NO_UNDERFLOW_CHECK
-#endif /* DBG */
-
-#ifdef QQ_USE_MACROS
-/* notdone */
-#else
-
-#ifdef QQ_NO_INLINE
-#define __inline
-#endif /* QQ_NO_INLINE */
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-extern __inline void
-QQ_InitQueue(
-PQQ_CONTAINER pQueue,
-unsigned int QueueSize) {
- pQueue->Head = 0;
- pQueue->Tail = 0;
- pQueue->Size = QueueSize+1;
- atomic_set(&pQueue->EntryCnt, 0);
-} /* QQ_InitQueue */
-
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-extern __inline char
-QQ_Full(
-PQQ_CONTAINER pQueue) {
- unsigned int NewHead;
-
- NewHead = (pQueue->Head + 1) % pQueue->Size;
-
- return(NewHead == pQueue->Tail);
-} /* QQ_Full */
-
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-extern __inline char
-QQ_Empty(
-PQQ_CONTAINER pQueue) {
- return(pQueue->Head == pQueue->Tail);
-} /* QQ_Empty */
-
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-extern __inline unsigned int
-QQ_GetSize(
-PQQ_CONTAINER pQueue) {
- return pQueue->Size;
-} /* QQ_GetSize */
-
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-extern __inline unsigned int
-QQ_GetEntryCnt(
-PQQ_CONTAINER pQueue) {
- return atomic_read(&pQueue->EntryCnt);
-} /* QQ_GetEntryCnt */
-
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/* TRUE entry was added successfully. */
-/* FALSE queue is full. */
-/******************************************************************************/
-extern __inline char
-QQ_PushHead(
-PQQ_CONTAINER pQueue,
-PQQ_ENTRY pEntry) {
- unsigned int Head;
-
- Head = (pQueue->Head + 1) % pQueue->Size;
-
-#if !defined(QQ_NO_OVERFLOW_CHECK)
- if(Head == pQueue->Tail) {
- return 0;
- } /* if */
-#endif /* QQ_NO_OVERFLOW_CHECK */
-
- pQueue->Array[pQueue->Head] = pEntry;
- wmb();
- pQueue->Head = Head;
- atomic_inc(&pQueue->EntryCnt);
-
- return -1;
-} /* QQ_PushHead */
-
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/* TRUE entry was added successfully. */
-/* FALSE queue is full. */
-/******************************************************************************/
-extern __inline char
-QQ_PushTail(
-PQQ_CONTAINER pQueue,
-PQQ_ENTRY pEntry) {
- unsigned int Tail;
-
- Tail = pQueue->Tail;
- if(Tail == 0) {
- Tail = pQueue->Size;
- } /* if */
- Tail--;
-
-#if !defined(QQ_NO_OVERFLOW_CHECK)
- if(Tail == pQueue->Head) {
- return 0;
- } /* if */
-#endif /* QQ_NO_OVERFLOW_CHECK */
-
- pQueue->Array[Tail] = pEntry;
- wmb();
- pQueue->Tail = Tail;
- atomic_inc(&pQueue->EntryCnt);
-
- return -1;
-} /* QQ_PushTail */
-
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-extern __inline PQQ_ENTRY
-QQ_PopHead(
-PQQ_CONTAINER pQueue) {
- unsigned int Head;
- PQQ_ENTRY Entry;
-
- Head = pQueue->Head;
-
-#if !defined(QQ_NO_UNDERFLOW_CHECK)
- if(Head == pQueue->Tail) {
- return (PQQ_ENTRY) 0;
- } /* if */
-#endif /* QQ_NO_UNDERFLOW_CHECK */
-
- if(Head == 0) {
- Head = pQueue->Size;
- } /* if */
- Head--;
-
- Entry = pQueue->Array[Head];
-#ifdef EMBEDDED
- membar();
-#else
- mb();
-#endif
- pQueue->Head = Head;
- atomic_dec(&pQueue->EntryCnt);
-
- return Entry;
-} /* QQ_PopHead */
-
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-extern __inline PQQ_ENTRY
-QQ_PopTail(
-PQQ_CONTAINER pQueue) {
- unsigned int Tail;
- PQQ_ENTRY Entry;
-
- Tail = pQueue->Tail;
-
-#if !defined(QQ_NO_UNDERFLOW_CHECK)
- if(Tail == pQueue->Head) {
- return (PQQ_ENTRY) 0;
- } /* if */
-#endif /* QQ_NO_UNDERFLOW_CHECK */
-
- Entry = pQueue->Array[Tail];
-#ifdef EMBEDDED
- membar();
-#else
- mb();
-#endif
- pQueue->Tail = (Tail + 1) % pQueue->Size;
- atomic_dec(&pQueue->EntryCnt);
-
- return Entry;
-} /* QQ_PopTail */
-
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-extern __inline PQQ_ENTRY
-QQ_GetHead(
- PQQ_CONTAINER pQueue,
- unsigned int Idx)
-{
- if(Idx >= atomic_read(&pQueue->EntryCnt))
- {
- return (PQQ_ENTRY) 0;
- }
-
- if(pQueue->Head > Idx)
- {
- Idx = pQueue->Head - Idx;
- }
- else
- {
- Idx = pQueue->Size - (Idx - pQueue->Head);
- }
- Idx--;
-
- return pQueue->Array[Idx];
-}
-
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-extern __inline PQQ_ENTRY
-QQ_GetTail(
- PQQ_CONTAINER pQueue,
- unsigned int Idx)
-{
- if(Idx >= atomic_read(&pQueue->EntryCnt))
- {
- return (PQQ_ENTRY) 0;
- }
-
- Idx += pQueue->Tail;
- if(Idx >= pQueue->Size)
- {
- Idx = Idx - pQueue->Size;
- }
-
- return pQueue->Array[Idx];
-}
-
-#endif /* QQ_USE_MACROS */
-
-
-#endif /* QUEUE_H */
+++ /dev/null
-/*
- dm9000.c: Version 1.2 12/15/2003
-
- A Davicom DM9000 ISA NIC fast Ethernet driver for Linux.
- Copyright (C) 1997 Sten Wang
-
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License
- as published by the Free Software Foundation; either version 2
- of the License, or (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
-
-V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match
- 06/22/2001 Support DM9801 progrmming
- E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000
- E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200
- R17 = (R17 & 0xfff0) | NF + 3
- E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200
- R17 = (R17 & 0xfff0) | NF
-
-v1.00 modify by simon 2001.9.5
- change for kernel 2.4.x
-
-v1.1 11/09/2001 fix force mode bug
-
-v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>:
- Fixed phy reset.
- Added tx/rx 32 bit mode.
- Cleaned up for kernel merge.
-
---------------------------------------
-
- 12/15/2003 Initial port to u-boot by
- Sascha Hauer <saschahauer@web.de>
-
- 06/03/2008 Remy Bohmer <linux@bohmer.net>
- - Fixed the driver to work with DM9000A.
- (check on ISR receive status bit before reading the
- FIFO as described in DM9000 programming guide and
- application notes)
- - Added autodetect of databus width.
- - Made debug code compile again.
- - Adapt eth_send such that it matches the DM9000*
- application notes. Needed to make it work properly
- for DM9000A.
- - Adapted reset procedure to match DM9000 application
- notes (i.e. double reset)
- - some minor code cleanups
- These changes are tested with DM9000{A,EP,E} together
- with a 200MHz Atmel AT91SAM9261 core
-
-TODO: external MII is not functional, only internal at the moment.
-*/
-
-#include <common.h>
-#include <command.h>
-#include <net.h>
-#include <asm/io.h>
-#include <dm9000.h>
-
-#include "dm9000x.h"
-
-/* Board/System/Debug information/definition ---------------- */
-
-/* #define CONFIG_DM9000_DEBUG */
-
-#ifdef CONFIG_DM9000_DEBUG
-#define DM9000_DBG(fmt,args...) printf(fmt, ##args)
-#define DM9000_DMP_PACKET(func,packet,length) \
- do { \
- int i; \
- printf(func ": length: %d\n", length); \
- for (i = 0; i < length; i++) { \
- if (i % 8 == 0) \
- printf("\n%s: %02x: ", func, i); \
- printf("%02x ", ((unsigned char *) packet)[i]); \
- } printf("\n"); \
- } while(0)
-#else
-#define DM9000_DBG(fmt,args...)
-#define DM9000_DMP_PACKET(func,packet,length)
-#endif
-
-/* Structure/enum declaration ------------------------------- */
-typedef struct board_info {
- u32 runt_length_counter; /* counter: RX length < 64byte */
- u32 long_length_counter; /* counter: RX length > 1514byte */
- u32 reset_counter; /* counter: RESET */
- u32 reset_tx_timeout; /* RESET caused by TX Timeout */
- u32 reset_rx_status; /* RESET caused by RX Statsus wrong */
- u16 tx_pkt_cnt;
- u16 queue_start_addr;
- u16 dbug_cnt;
- u8 phy_addr;
- u8 device_wait_reset; /* device state */
- unsigned char srom[128];
- void (*outblk)(volatile void *data_ptr, int count);
- void (*inblk)(void *data_ptr, int count);
- void (*rx_status)(u16 *RxStatus, u16 *RxLen);
- struct eth_device netdev;
-} board_info_t;
-static board_info_t dm9000_info;
-
-
-/* function declaration ------------------------------------- */
-static int dm9000_probe(void);
-static u16 phy_read(int);
-static void phy_write(int, u16);
-static u8 DM9000_ior(int);
-static void DM9000_iow(int reg, u8 value);
-
-/* DM9000 network board routine ---------------------------- */
-
-#define DM9000_outb(d,r) ( *(volatile u8 *)r = d )
-#define DM9000_outw(d,r) ( *(volatile u16 *)r = d )
-#define DM9000_outl(d,r) ( *(volatile u32 *)r = d )
-#define DM9000_inb(r) (*(volatile u8 *)r)
-#define DM9000_inw(r) (*(volatile u16 *)r)
-#define DM9000_inl(r) (*(volatile u32 *)r)
-
-#ifdef CONFIG_DM9000_DEBUG
-static void
-dump_regs(void)
-{
- DM9000_DBG("\n");
- DM9000_DBG("NCR (0x00): %02x\n", DM9000_ior(0));
- DM9000_DBG("NSR (0x01): %02x\n", DM9000_ior(1));
- DM9000_DBG("TCR (0x02): %02x\n", DM9000_ior(2));
- DM9000_DBG("TSRI (0x03): %02x\n", DM9000_ior(3));
- DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4));
- DM9000_DBG("RCR (0x05): %02x\n", DM9000_ior(5));
- DM9000_DBG("RSR (0x06): %02x\n", DM9000_ior(6));
- DM9000_DBG("ISR (0xFE): %02x\n", DM9000_ior(DM9000_ISR));
- DM9000_DBG("\n");
-}
-#endif
-
-static void dm9000_outblk_8bit(volatile void *data_ptr, int count)
-{
- int i;
- for (i = 0; i < count; i++)
- DM9000_outb((((u8 *) data_ptr)[i] & 0xff), DM9000_DATA);
-}
-
-static void dm9000_outblk_16bit(volatile void *data_ptr, int count)
-{
- int i;
- u32 tmplen = (count + 1) / 2;
-
- for (i = 0; i < tmplen; i++)
- DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA);
-}
-static void dm9000_outblk_32bit(volatile void *data_ptr, int count)
-{
- int i;
- u32 tmplen = (count + 3) / 4;
-
- for (i = 0; i < tmplen; i++)
- DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA);
-}
-
-static void dm9000_inblk_8bit(void *data_ptr, int count)
-{
- int i;
- for (i = 0; i < count; i++)
- ((u8 *) data_ptr)[i] = DM9000_inb(DM9000_DATA);
-}
-
-static void dm9000_inblk_16bit(void *data_ptr, int count)
-{
- int i;
- u32 tmplen = (count + 1) / 2;
-
- for (i = 0; i < tmplen; i++)
- ((u16 *) data_ptr)[i] = DM9000_inw(DM9000_DATA);
-}
-static void dm9000_inblk_32bit(void *data_ptr, int count)
-{
- int i;
- u32 tmplen = (count + 3) / 4;
-
- for (i = 0; i < tmplen; i++)
- ((u32 *) data_ptr)[i] = DM9000_inl(DM9000_DATA);
-}
-
-static void dm9000_rx_status_32bit(u16 *RxStatus, u16 *RxLen)
-{
- u32 tmpdata;
-
- DM9000_outb(DM9000_MRCMD, DM9000_IO);
-
- tmpdata = DM9000_inl(DM9000_DATA);
- *RxStatus = __le16_to_cpu(tmpdata);
- *RxLen = __le16_to_cpu(tmpdata >> 16);
-}
-
-static void dm9000_rx_status_16bit(u16 *RxStatus, u16 *RxLen)
-{
- DM9000_outb(DM9000_MRCMD, DM9000_IO);
-
- *RxStatus = __le16_to_cpu(DM9000_inw(DM9000_DATA));
- *RxLen = __le16_to_cpu(DM9000_inw(DM9000_DATA));
-}
-
-static void dm9000_rx_status_8bit(u16 *RxStatus, u16 *RxLen)
-{
- DM9000_outb(DM9000_MRCMD, DM9000_IO);
-
- *RxStatus =
- __le16_to_cpu(DM9000_inb(DM9000_DATA) +
- (DM9000_inb(DM9000_DATA) << 8));
- *RxLen =
- __le16_to_cpu(DM9000_inb(DM9000_DATA) +
- (DM9000_inb(DM9000_DATA) << 8));
-}
-
-/*
- Search DM9000 board, allocate space and register it
-*/
-int
-dm9000_probe(void)
-{
- u32 id_val;
- id_val = DM9000_ior(DM9000_VIDL);
- id_val |= DM9000_ior(DM9000_VIDH) << 8;
- id_val |= DM9000_ior(DM9000_PIDL) << 16;
- id_val |= DM9000_ior(DM9000_PIDH) << 24;
- if (id_val == DM9000_ID) {
- printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
- id_val);
- return 0;
- } else {
- printf("dm9000 not found at 0x%08x id: 0x%08x\n",
- CONFIG_DM9000_BASE, id_val);
- return -1;
- }
-}
-
-/* General Purpose dm9000 reset routine */
-static void
-dm9000_reset(void)
-{
- DM9000_DBG("resetting DM9000\n");
-
- /* Reset DM9000,
- see DM9000 Application Notes V1.22 Jun 11, 2004 page 29 */
-
- /* DEBUG: Make all GPIO0 outputs, all others inputs */
- DM9000_iow(DM9000_GPCR, GPCR_GPIO0_OUT);
- /* Step 1: Power internal PHY by writing 0 to GPIO0 pin */
- DM9000_iow(DM9000_GPR, 0);
- /* Step 2: Software reset */
- DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST));
-
- do {
- DM9000_DBG("resetting the DM9000, 1st reset\n");
- udelay(25); /* Wait at least 20 us */
- } while (DM9000_ior(DM9000_NCR) & 1);
-
- DM9000_iow(DM9000_NCR, 0);
- DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST)); /* Issue a second reset */
-
- do {
- DM9000_DBG("resetting the DM9000, 2nd reset\n");
- udelay(25); /* Wait at least 20 us */
- } while (DM9000_ior(DM9000_NCR) & 1);
-
- /* Check whether the ethernet controller is present */
- if ((DM9000_ior(DM9000_PIDL) != 0x0) ||
- (DM9000_ior(DM9000_PIDH) != 0x90))
- printf("ERROR: resetting DM9000 -> not responding\n");
-}
-
-/* Initialize dm9000 board
-*/
-static int dm9000_init(struct eth_device *dev, bd_t *bd)
-{
- int i, oft, lnk;
- u8 io_mode;
- struct board_info *db = &dm9000_info;
- uchar enetaddr[6];
-
- DM9000_DBG("%s\n", __func__);
-
- /* RESET device */
- dm9000_reset();
-
- if (dm9000_probe() < 0)
- return -1;
-
- /* Auto-detect 8/16/32 bit mode, ISR Bit 6+7 indicate bus width */
- io_mode = DM9000_ior(DM9000_ISR) >> 6;
-
- switch (io_mode) {
- case 0x0: /* 16-bit mode */
- printf("DM9000: running in 16 bit mode\n");
- db->outblk = dm9000_outblk_16bit;
- db->inblk = dm9000_inblk_16bit;
- db->rx_status = dm9000_rx_status_16bit;
- break;
- case 0x01: /* 32-bit mode */
- printf("DM9000: running in 32 bit mode\n");
- db->outblk = dm9000_outblk_32bit;
- db->inblk = dm9000_inblk_32bit;
- db->rx_status = dm9000_rx_status_32bit;
- break;
- case 0x02: /* 8 bit mode */
- printf("DM9000: running in 8 bit mode\n");
- db->outblk = dm9000_outblk_8bit;
- db->inblk = dm9000_inblk_8bit;
- db->rx_status = dm9000_rx_status_8bit;
- break;
- default:
- /* Assume 8 bit mode, will probably not work anyway */
- printf("DM9000: Undefined IO-mode:0x%x\n", io_mode);
- db->outblk = dm9000_outblk_8bit;
- db->inblk = dm9000_inblk_8bit;
- db->rx_status = dm9000_rx_status_8bit;
- break;
- }
-
- /* Program operating register, only internal phy supported */
- DM9000_iow(DM9000_NCR, 0x0);
- /* TX Polling clear */
- DM9000_iow(DM9000_TCR, 0);
- /* Less 3Kb, 200us */
- DM9000_iow(DM9000_BPTR, BPTR_BPHW(3) | BPTR_JPT_600US);
- /* Flow Control : High/Low Water */
- DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8));
- /* SH FIXME: This looks strange! Flow Control */
- DM9000_iow(DM9000_FCR, 0x0);
- /* Special Mode */
- DM9000_iow(DM9000_SMCR, 0);
- /* clear TX status */
- DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
- /* Clear interrupt status */
- DM9000_iow(DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS);
-
- /* Set Node address */
- if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
-#if !defined(CONFIG_DM9000_NO_SROM)
- for (i = 0; i < 3; i++)
- dm9000_read_srom_word(i, enetaddr + 2 * i);
- eth_setenv_enetaddr("ethaddr", enetaddr);
-#endif
- }
-
- printf("MAC: %pM\n", enetaddr);
-
- /* fill device MAC address registers */
- for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++)
- DM9000_iow(oft, enetaddr[i]);
- for (i = 0, oft = 0x16; i < 8; i++, oft++)
- DM9000_iow(oft, 0xff);
-
- /* read back mac, just to be sure */
- for (i = 0, oft = 0x10; i < 6; i++, oft++)
- DM9000_DBG("%02x:", DM9000_ior(oft));
- DM9000_DBG("\n");
-
- /* Activate DM9000 */
- /* RX enable */
- DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);
- /* Enable TX/RX interrupt mask */
- DM9000_iow(DM9000_IMR, IMR_PAR);
-
- i = 0;
- while (!(phy_read(1) & 0x20)) { /* autonegation complete bit */
- udelay(1000);
- i++;
- if (i == 10000) {
- printf("could not establish link\n");
- return 0;
- }
- }
-
- /* see what we've got */
- lnk = phy_read(17) >> 12;
- printf("operating at ");
- switch (lnk) {
- case 1:
- printf("10M half duplex ");
- break;
- case 2:
- printf("10M full duplex ");
- break;
- case 4:
- printf("100M half duplex ");
- break;
- case 8:
- printf("100M full duplex ");
- break;
- default:
- printf("unknown: %d ", lnk);
- break;
- }
- printf("mode\n");
- return 0;
-}
-
-/*
- Hardware start transmission.
- Send a packet to media from the upper layer.
-*/
-static int dm9000_send(struct eth_device *netdev, volatile void *packet,
- int length)
-{
- int tmo;
- struct board_info *db = &dm9000_info;
-
- DM9000_DMP_PACKET(__func__ , packet, length);
-
- DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
-
- /* Move data to DM9000 TX RAM */
- DM9000_outb(DM9000_MWCMD, DM9000_IO); /* Prepare for TX-data */
-
- /* push the data to the TX-fifo */
- (db->outblk)(packet, length);
-
- /* Set TX length to DM9000 */
- DM9000_iow(DM9000_TXPLL, length & 0xff);
- DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff);
-
- /* Issue TX polling command */
- DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
-
- /* wait for end of transmission */
- tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
- while ( !(DM9000_ior(DM9000_NSR) & (NSR_TX1END | NSR_TX2END)) ||
- !(DM9000_ior(DM9000_ISR) & IMR_PTM) ) {
- if (get_timer(0) >= tmo) {
- printf("transmission timeout\n");
- break;
- }
- }
- DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
-
- DM9000_DBG("transmit done\n\n");
- return 0;
-}
-
-/*
- Stop the interface.
- The interface is stopped when it is brought.
-*/
-static void dm9000_halt(struct eth_device *netdev)
-{
- DM9000_DBG("%s\n", __func__);
-
- /* RESET devie */
- phy_write(0, 0x8000); /* PHY RESET */
- DM9000_iow(DM9000_GPR, 0x01); /* Power-Down PHY */
- DM9000_iow(DM9000_IMR, 0x80); /* Disable all interrupt */
- DM9000_iow(DM9000_RCR, 0x00); /* Disable RX */
-}
-
-/*
- Received a packet and pass to upper layer
-*/
-static int dm9000_rx(struct eth_device *netdev)
-{
- u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0];
- u16 RxStatus, RxLen = 0;
- struct board_info *db = &dm9000_info;
-
- /* Check packet ready or not, we must check
- the ISR status first for DM9000A */
- if (!(DM9000_ior(DM9000_ISR) & 0x01)) /* Rx-ISR bit must be set. */
- return 0;
-
- DM9000_iow(DM9000_ISR, 0x01); /* clear PR status latched in bit 0 */
-
- /* There is _at least_ 1 package in the fifo, read them all */
- for (;;) {
- DM9000_ior(DM9000_MRCMDX); /* Dummy read */
-
- /* Get most updated data,
- only look at bits 0:1, See application notes DM9000 */
- rxbyte = DM9000_inb(DM9000_DATA) & 0x03;
-
- /* Status check: this byte must be 0 or 1 */
- if (rxbyte > DM9000_PKT_RDY) {
- DM9000_iow(DM9000_RCR, 0x00); /* Stop Device */
- DM9000_iow(DM9000_ISR, 0x80); /* Stop INT request */
- printf("DM9000 error: status check fail: 0x%x\n",
- rxbyte);
- return 0;
- }
-
- if (rxbyte != DM9000_PKT_RDY)
- return 0; /* No packet received, ignore */
-
- DM9000_DBG("receiving packet\n");
-
- /* A packet ready now & Get status/length */
- (db->rx_status)(&RxStatus, &RxLen);
-
- DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen);
-
- /* Move data from DM9000 */
- /* Read received packet from RX SRAM */
- (db->inblk)(rdptr, RxLen);
-
- if ((RxStatus & 0xbf00) || (RxLen < 0x40)
- || (RxLen > DM9000_PKT_MAX)) {
- if (RxStatus & 0x100) {
- printf("rx fifo error\n");
- }
- if (RxStatus & 0x200) {
- printf("rx crc error\n");
- }
- if (RxStatus & 0x8000) {
- printf("rx length error\n");
- }
- if (RxLen > DM9000_PKT_MAX) {
- printf("rx length too big\n");
- dm9000_reset();
- }
- } else {
- DM9000_DMP_PACKET(__func__ , rdptr, RxLen);
-
- DM9000_DBG("passing packet to upper layer\n");
- NetReceive(NetRxPackets[0], RxLen);
- }
- }
- return 0;
-}
-
-/*
- Read a word data from SROM
-*/
-#if !defined(CONFIG_DM9000_NO_SROM)
-void dm9000_read_srom_word(int offset, u8 *to)
-{
- DM9000_iow(DM9000_EPAR, offset);
- DM9000_iow(DM9000_EPCR, 0x4);
- udelay(8000);
- DM9000_iow(DM9000_EPCR, 0x0);
- to[0] = DM9000_ior(DM9000_EPDRL);
- to[1] = DM9000_ior(DM9000_EPDRH);
-}
-
-void dm9000_write_srom_word(int offset, u16 val)
-{
- DM9000_iow(DM9000_EPAR, offset);
- DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff));
- DM9000_iow(DM9000_EPDRL, (val & 0xff));
- DM9000_iow(DM9000_EPCR, 0x12);
- udelay(8000);
- DM9000_iow(DM9000_EPCR, 0);
-}
-#endif
-
-/*
- Read a byte from I/O port
-*/
-static u8
-DM9000_ior(int reg)
-{
- DM9000_outb(reg, DM9000_IO);
- return DM9000_inb(DM9000_DATA);
-}
-
-/*
- Write a byte to I/O port
-*/
-static void
-DM9000_iow(int reg, u8 value)
-{
- DM9000_outb(reg, DM9000_IO);
- DM9000_outb(value, DM9000_DATA);
-}
-
-/*
- Read a word from phyxcer
-*/
-static u16
-phy_read(int reg)
-{
- u16 val;
-
- /* Fill the phyxcer register into REG_0C */
- DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
- DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */
- udelay(100); /* Wait read complete */
- DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */
- val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL);
-
- /* The read data keeps on REG_0D & REG_0E */
- DM9000_DBG("phy_read(0x%x): 0x%x\n", reg, val);
- return val;
-}
-
-/*
- Write a word to phyxcer
-*/
-static void
-phy_write(int reg, u16 value)
-{
-
- /* Fill the phyxcer register into REG_0C */
- DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
-
- /* Fill the written data into REG_0D & REG_0E */
- DM9000_iow(DM9000_EPDRL, (value & 0xff));
- DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff));
- DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */
- udelay(500); /* Wait write complete */
- DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */
- DM9000_DBG("phy_write(reg:0x%x, value:0x%x)\n", reg, value);
-}
-
-int dm9000_initialize(bd_t *bis)
-{
- struct eth_device *dev = &(dm9000_info.netdev);
-
- dev->init = dm9000_init;
- dev->halt = dm9000_halt;
- dev->send = dm9000_send;
- dev->recv = dm9000_rx;
- sprintf(dev->name, "dm9000");
-
- eth_register(dev);
-
- return 0;
-}
+++ /dev/null
-/**************************************************************************
-Intel Pro 1000 for ppcboot/das-u-boot
-Drivers are port from Intel's Linux driver e1000-4.3.15
-and from Etherboot pro 1000 driver by mrakes at vivato dot net
-tested on both gig copper and gig fiber boards
-***************************************************************************/
-/*******************************************************************************
-
-
- Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
-
- This program is free software; you can redistribute it and/or modify it
- under the terms of the GNU General Public License as published by the Free
- Software Foundation; either version 2 of the License, or (at your option)
- any later version.
-
- This program is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- more details.
-
- You should have received a copy of the GNU General Public License along with
- this program; if not, write to the Free Software Foundation, Inc., 59
- Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
- The full GNU General Public License is included in this distribution in the
- file called LICENSE.
-
- Contact Information:
- Linux NICS <linux.nics@intel.com>
- Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
-
-*******************************************************************************/
-/*
- * Copyright (C) Archway Digital Solutions.
- *
- * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
- * 2/9/2002
- *
- * Copyright (C) Linux Networx.
- * Massive upgrade to work with the new intel gigabit NICs.
- * <ebiederman at lnxi dot com>
- */
-
-#include "e1000.h"
-
-#define TOUT_LOOP 100000
-
-#define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
-#define bus_to_phys(devno, a) pci_mem_to_phys(devno, a)
-#define mdelay(n) udelay((n)*1000)
-
-#define E1000_DEFAULT_PBA 0x000a0026
-
-/* NIC specific static variables go here */
-
-static char tx_pool[128 + 16];
-static char rx_pool[128 + 16];
-static char packet[2096];
-
-static struct e1000_tx_desc *tx_base;
-static struct e1000_rx_desc *rx_base;
-
-static int tx_tail;
-static int rx_tail, rx_last;
-
-static struct pci_device_id supported[] = {
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF},
- /* E1000 PCIe card */
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER },
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES },
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT},
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT},
- {}
-};
-
-/* Function forward declarations */
-static int e1000_setup_link(struct eth_device *nic);
-static int e1000_setup_fiber_link(struct eth_device *nic);
-static int e1000_setup_copper_link(struct eth_device *nic);
-static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
-static void e1000_config_collision_dist(struct e1000_hw *hw);
-static int e1000_config_mac_to_phy(struct e1000_hw *hw);
-static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
-static int e1000_check_for_link(struct eth_device *nic);
-static int e1000_wait_autoneg(struct e1000_hw *hw);
-static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
- uint16_t * duplex);
-static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
- uint16_t * phy_data);
-static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
- uint16_t phy_data);
-static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
-static int e1000_phy_reset(struct e1000_hw *hw);
-static int e1000_detect_gig_phy(struct e1000_hw *hw);
-static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
-static void e1000_set_media_type(struct e1000_hw *hw);
-
-static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
-static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
-#define E1000_WRITE_REG(a, reg, value) (writel((value), ((a)->hw_addr + E1000_##reg)))
-#define E1000_READ_REG(a, reg) (readl((a)->hw_addr + E1000_##reg))
-#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) (\
- writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2))))
-#define E1000_READ_REG_ARRAY(a, reg, offset) ( \
- readl((a)->hw_addr + E1000_##reg + ((offset) << 2)))
-#define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);}
-
-#ifndef CONFIG_AP1000 /* remove for warnings */
-static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
- uint16_t words,
- uint16_t *data);
-/******************************************************************************
- * Raises the EEPROM's clock input.
- *
- * hw - Struct containing variables accessed by shared code
- * eecd - EECD's current value
- *****************************************************************************/
-static void
-e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
-{
- /* Raise the clock input to the EEPROM (by setting the SK bit), and then
- * wait 50 microseconds.
- */
- *eecd = *eecd | E1000_EECD_SK;
- E1000_WRITE_REG(hw, EECD, *eecd);
- E1000_WRITE_FLUSH(hw);
- udelay(50);
-}
-
-/******************************************************************************
- * Lowers the EEPROM's clock input.
- *
- * hw - Struct containing variables accessed by shared code
- * eecd - EECD's current value
- *****************************************************************************/
-static void
-e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
-{
- /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
- * wait 50 microseconds.
- */
- *eecd = *eecd & ~E1000_EECD_SK;
- E1000_WRITE_REG(hw, EECD, *eecd);
- E1000_WRITE_FLUSH(hw);
- udelay(50);
-}
-
-/******************************************************************************
- * Shift data bits out to the EEPROM.
- *
- * hw - Struct containing variables accessed by shared code
- * data - data to send to the EEPROM
- * count - number of bits to shift out
- *****************************************************************************/
-static void
-e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
-{
- uint32_t eecd;
- uint32_t mask;
-
- /* We need to shift "count" bits out to the EEPROM. So, value in the
- * "data" parameter will be shifted out to the EEPROM one bit at a time.
- * In order to do this, "data" must be broken down into bits.
- */
- mask = 0x01 << (count - 1);
- eecd = E1000_READ_REG(hw, EECD);
- eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
- do {
- /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
- * and then raising and then lowering the clock (the SK bit controls
- * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
- * by setting "DI" to "0" and then raising and then lowering the clock.
- */
- eecd &= ~E1000_EECD_DI;
-
- if (data & mask)
- eecd |= E1000_EECD_DI;
-
- E1000_WRITE_REG(hw, EECD, eecd);
- E1000_WRITE_FLUSH(hw);
-
- udelay(50);
-
- e1000_raise_ee_clk(hw, &eecd);
- e1000_lower_ee_clk(hw, &eecd);
-
- mask = mask >> 1;
-
- } while (mask);
-
- /* We leave the "DI" bit set to "0" when we leave this routine. */
- eecd &= ~E1000_EECD_DI;
- E1000_WRITE_REG(hw, EECD, eecd);
-}
-
-/******************************************************************************
- * Shift data bits in from the EEPROM
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static uint16_t
-e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
-{
- uint32_t eecd;
- uint32_t i;
- uint16_t data;
-
- /* In order to read a register from the EEPROM, we need to shift 'count'
- * bits in from the EEPROM. Bits are "shifted in" by raising the clock
- * input to the EEPROM (setting the SK bit), and then reading the
- * value of the "DO" bit. During this "shifting in" process the
- * "DI" bit should always be clear.
- */
-
- eecd = E1000_READ_REG(hw, EECD);
-
- eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
- data = 0;
-
- for (i = 0; i < count; i++) {
- data = data << 1;
- e1000_raise_ee_clk(hw, &eecd);
-
- eecd = E1000_READ_REG(hw, EECD);
-
- eecd &= ~(E1000_EECD_DI);
- if (eecd & E1000_EECD_DO)
- data |= 1;
-
- e1000_lower_ee_clk(hw, &eecd);
- }
-
- return data;
-}
-
-/******************************************************************************
- * Returns EEPROM to a "standby" state
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static void
-e1000_standby_eeprom(struct e1000_hw *hw)
-{
- struct e1000_eeprom_info *eeprom = &hw->eeprom;
- uint32_t eecd;
-
- eecd = E1000_READ_REG(hw, EECD);
-
- if (eeprom->type == e1000_eeprom_microwire) {
- eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
- E1000_WRITE_REG(hw, EECD, eecd);
- E1000_WRITE_FLUSH(hw);
- udelay(eeprom->delay_usec);
-
- /* Clock high */
- eecd |= E1000_EECD_SK;
- E1000_WRITE_REG(hw, EECD, eecd);
- E1000_WRITE_FLUSH(hw);
- udelay(eeprom->delay_usec);
-
- /* Select EEPROM */
- eecd |= E1000_EECD_CS;
- E1000_WRITE_REG(hw, EECD, eecd);
- E1000_WRITE_FLUSH(hw);
- udelay(eeprom->delay_usec);
-
- /* Clock low */
- eecd &= ~E1000_EECD_SK;
- E1000_WRITE_REG(hw, EECD, eecd);
- E1000_WRITE_FLUSH(hw);
- udelay(eeprom->delay_usec);
- } else if (eeprom->type == e1000_eeprom_spi) {
- /* Toggle CS to flush commands */
- eecd |= E1000_EECD_CS;
- E1000_WRITE_REG(hw, EECD, eecd);
- E1000_WRITE_FLUSH(hw);
- udelay(eeprom->delay_usec);
- eecd &= ~E1000_EECD_CS;
- E1000_WRITE_REG(hw, EECD, eecd);
- E1000_WRITE_FLUSH(hw);
- udelay(eeprom->delay_usec);
- }
-}
-
-/***************************************************************************
-* Description: Determines if the onboard NVM is FLASH or EEPROM.
-*
-* hw - Struct containing variables accessed by shared code
-****************************************************************************/
-static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
-{
- uint32_t eecd = 0;
-
- DEBUGFUNC();
-
- if (hw->mac_type == e1000_ich8lan)
- return FALSE;
-
- if (hw->mac_type == e1000_82573) {
- eecd = E1000_READ_REG(hw, EECD);
-
- /* Isolate bits 15 & 16 */
- eecd = ((eecd >> 15) & 0x03);
-
- /* If both bits are set, device is Flash type */
- if (eecd == 0x03)
- return FALSE;
- }
- return TRUE;
-}
-
-/******************************************************************************
- * Prepares EEPROM for access
- *
- * hw - Struct containing variables accessed by shared code
- *
- * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
- * function should be called before issuing a command to the EEPROM.
- *****************************************************************************/
-static int32_t
-e1000_acquire_eeprom(struct e1000_hw *hw)
-{
- struct e1000_eeprom_info *eeprom = &hw->eeprom;
- uint32_t eecd, i = 0;
-
- DEBUGFUNC();
-
- if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
- return -E1000_ERR_SWFW_SYNC;
- eecd = E1000_READ_REG(hw, EECD);
-
- if (hw->mac_type != e1000_82573) {
- /* Request EEPROM Access */
- if (hw->mac_type > e1000_82544) {
- eecd |= E1000_EECD_REQ;
- E1000_WRITE_REG(hw, EECD, eecd);
- eecd = E1000_READ_REG(hw, EECD);
- while ((!(eecd & E1000_EECD_GNT)) &&
- (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
- i++;
- udelay(5);
- eecd = E1000_READ_REG(hw, EECD);
- }
- if (!(eecd & E1000_EECD_GNT)) {
- eecd &= ~E1000_EECD_REQ;
- E1000_WRITE_REG(hw, EECD, eecd);
- DEBUGOUT("Could not acquire EEPROM grant\n");
- return -E1000_ERR_EEPROM;
- }
- }
- }
-
- /* Setup EEPROM for Read/Write */
-
- if (eeprom->type == e1000_eeprom_microwire) {
- /* Clear SK and DI */
- eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
- E1000_WRITE_REG(hw, EECD, eecd);
-
- /* Set CS */
- eecd |= E1000_EECD_CS;
- E1000_WRITE_REG(hw, EECD, eecd);
- } else if (eeprom->type == e1000_eeprom_spi) {
- /* Clear SK and CS */
- eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
- E1000_WRITE_REG(hw, EECD, eecd);
- udelay(1);
- }
-
- return E1000_SUCCESS;
-}
-
-/******************************************************************************
- * Sets up eeprom variables in the hw struct. Must be called after mac_type
- * is configured. Additionally, if this is ICH8, the flash controller GbE
- * registers must be mapped, or this will crash.
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
-{
- struct e1000_eeprom_info *eeprom = &hw->eeprom;
- uint32_t eecd = E1000_READ_REG(hw, EECD);
- int32_t ret_val = E1000_SUCCESS;
- uint16_t eeprom_size;
-
- DEBUGFUNC();
-
- switch (hw->mac_type) {
- case e1000_82542_rev2_0:
- case e1000_82542_rev2_1:
- case e1000_82543:
- case e1000_82544:
- eeprom->type = e1000_eeprom_microwire;
- eeprom->word_size = 64;
- eeprom->opcode_bits = 3;
- eeprom->address_bits = 6;
- eeprom->delay_usec = 50;
- eeprom->use_eerd = FALSE;
- eeprom->use_eewr = FALSE;
- break;
- case e1000_82540:
- case e1000_82545:
- case e1000_82545_rev_3:
- case e1000_82546:
- case e1000_82546_rev_3:
- eeprom->type = e1000_eeprom_microwire;
- eeprom->opcode_bits = 3;
- eeprom->delay_usec = 50;
- if (eecd & E1000_EECD_SIZE) {
- eeprom->word_size = 256;
- eeprom->address_bits = 8;
- } else {
- eeprom->word_size = 64;
- eeprom->address_bits = 6;
- }
- eeprom->use_eerd = FALSE;
- eeprom->use_eewr = FALSE;
- break;
- case e1000_82541:
- case e1000_82541_rev_2:
- case e1000_82547:
- case e1000_82547_rev_2:
- if (eecd & E1000_EECD_TYPE) {
- eeprom->type = e1000_eeprom_spi;
- eeprom->opcode_bits = 8;
- eeprom->delay_usec = 1;
- if (eecd & E1000_EECD_ADDR_BITS) {
- eeprom->page_size = 32;
- eeprom->address_bits = 16;
- } else {
- eeprom->page_size = 8;
- eeprom->address_bits = 8;
- }
- } else {
- eeprom->type = e1000_eeprom_microwire;
- eeprom->opcode_bits = 3;
- eeprom->delay_usec = 50;
- if (eecd & E1000_EECD_ADDR_BITS) {
- eeprom->word_size = 256;
- eeprom->address_bits = 8;
- } else {
- eeprom->word_size = 64;
- eeprom->address_bits = 6;
- }
- }
- eeprom->use_eerd = FALSE;
- eeprom->use_eewr = FALSE;
- break;
- case e1000_82571:
- case e1000_82572:
- eeprom->type = e1000_eeprom_spi;
- eeprom->opcode_bits = 8;
- eeprom->delay_usec = 1;
- if (eecd & E1000_EECD_ADDR_BITS) {
- eeprom->page_size = 32;
- eeprom->address_bits = 16;
- } else {
- eeprom->page_size = 8;
- eeprom->address_bits = 8;
- }
- eeprom->use_eerd = FALSE;
- eeprom->use_eewr = FALSE;
- break;
- case e1000_82573:
- eeprom->type = e1000_eeprom_spi;
- eeprom->opcode_bits = 8;
- eeprom->delay_usec = 1;
- if (eecd & E1000_EECD_ADDR_BITS) {
- eeprom->page_size = 32;
- eeprom->address_bits = 16;
- } else {
- eeprom->page_size = 8;
- eeprom->address_bits = 8;
- }
- eeprom->use_eerd = TRUE;
- eeprom->use_eewr = TRUE;
- if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
- eeprom->type = e1000_eeprom_flash;
- eeprom->word_size = 2048;
-
- /* Ensure that the Autonomous FLASH update bit is cleared due to
- * Flash update issue on parts which use a FLASH for NVM. */
- eecd &= ~E1000_EECD_AUPDEN;
- E1000_WRITE_REG(hw, EECD, eecd);
- }
- break;
- case e1000_80003es2lan:
- eeprom->type = e1000_eeprom_spi;
- eeprom->opcode_bits = 8;
- eeprom->delay_usec = 1;
- if (eecd & E1000_EECD_ADDR_BITS) {
- eeprom->page_size = 32;
- eeprom->address_bits = 16;
- } else {
- eeprom->page_size = 8;
- eeprom->address_bits = 8;
- }
- eeprom->use_eerd = TRUE;
- eeprom->use_eewr = FALSE;
- break;
-
- /* ich8lan does not support currently. if needed, please
- * add corresponding code and functions.
- */
-#if 0
- case e1000_ich8lan:
- {
- int32_t i = 0;
-
- eeprom->type = e1000_eeprom_ich8;
- eeprom->use_eerd = FALSE;
- eeprom->use_eewr = FALSE;
- eeprom->word_size = E1000_SHADOW_RAM_WORDS;
- uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw,
- ICH_FLASH_GFPREG);
- /* Zero the shadow RAM structure. But don't load it from NVM
- * so as to save time for driver init */
- if (hw->eeprom_shadow_ram != NULL) {
- for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
- hw->eeprom_shadow_ram[i].modified = FALSE;
- hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
- }
- }
-
- hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
- ICH_FLASH_SECTOR_SIZE;
-
- hw->flash_bank_size = ((flash_size >> 16)
- & ICH_GFPREG_BASE_MASK) + 1;
- hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
-
- hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
-
- hw->flash_bank_size /= 2 * sizeof(uint16_t);
- break;
- }
-#endif
- default:
- break;
- }
-
- if (eeprom->type == e1000_eeprom_spi) {
- /* eeprom_size will be an enum [0..8] that maps
- * to eeprom sizes 128B to
- * 32KB (incremented by powers of 2).
- */
- if (hw->mac_type <= e1000_82547_rev_2) {
- /* Set to default value for initial eeprom read. */
- eeprom->word_size = 64;
- ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
- &eeprom_size);
- if (ret_val)
- return ret_val;
- eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
- >> EEPROM_SIZE_SHIFT;
- /* 256B eeprom size was not supported in earlier
- * hardware, so we bump eeprom_size up one to
- * ensure that "1" (which maps to 256B) is never
- * the result used in the shifting logic below. */
- if (eeprom_size)
- eeprom_size++;
- } else {
- eeprom_size = (uint16_t)((eecd &
- E1000_EECD_SIZE_EX_MASK) >>
- E1000_EECD_SIZE_EX_SHIFT);
- }
-
- eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
- }
- return ret_val;
-}
-
-/******************************************************************************
- * Polls the status bit (bit 1) of the EERD to determine when the read is done.
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static int32_t
-e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
-{
- uint32_t attempts = 100000;
- uint32_t i, reg = 0;
- int32_t done = E1000_ERR_EEPROM;
-
- for (i = 0; i < attempts; i++) {
- if (eerd == E1000_EEPROM_POLL_READ)
- reg = E1000_READ_REG(hw, EERD);
- else
- reg = E1000_READ_REG(hw, EEWR);
-
- if (reg & E1000_EEPROM_RW_REG_DONE) {
- done = E1000_SUCCESS;
- break;
- }
- udelay(5);
- }
-
- return done;
-}
-
-/******************************************************************************
- * Reads a 16 bit word from the EEPROM using the EERD register.
- *
- * hw - Struct containing variables accessed by shared code
- * offset - offset of word in the EEPROM to read
- * data - word read from the EEPROM
- * words - number of words to read
- *****************************************************************************/
-static int32_t
-e1000_read_eeprom_eerd(struct e1000_hw *hw,
- uint16_t offset,
- uint16_t words,
- uint16_t *data)
-{
- uint32_t i, eerd = 0;
- int32_t error = 0;
-
- for (i = 0; i < words; i++) {
- eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
- E1000_EEPROM_RW_REG_START;
-
- E1000_WRITE_REG(hw, EERD, eerd);
- error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
-
- if (error)
- break;
- data[i] = (E1000_READ_REG(hw, EERD) >>
- E1000_EEPROM_RW_REG_DATA);
-
- }
-
- return error;
-}
-
-static void
-e1000_release_eeprom(struct e1000_hw *hw)
-{
- uint32_t eecd;
-
- DEBUGFUNC();
-
- eecd = E1000_READ_REG(hw, EECD);
-
- if (hw->eeprom.type == e1000_eeprom_spi) {
- eecd |= E1000_EECD_CS; /* Pull CS high */
- eecd &= ~E1000_EECD_SK; /* Lower SCK */
-
- E1000_WRITE_REG(hw, EECD, eecd);
-
- udelay(hw->eeprom.delay_usec);
- } else if (hw->eeprom.type == e1000_eeprom_microwire) {
- /* cleanup eeprom */
-
- /* CS on Microwire is active-high */
- eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
-
- E1000_WRITE_REG(hw, EECD, eecd);
-
- /* Rising edge of clock */
- eecd |= E1000_EECD_SK;
- E1000_WRITE_REG(hw, EECD, eecd);
- E1000_WRITE_FLUSH(hw);
- udelay(hw->eeprom.delay_usec);
-
- /* Falling edge of clock */
- eecd &= ~E1000_EECD_SK;
- E1000_WRITE_REG(hw, EECD, eecd);
- E1000_WRITE_FLUSH(hw);
- udelay(hw->eeprom.delay_usec);
- }
-
- /* Stop requesting EEPROM access */
- if (hw->mac_type > e1000_82544) {
- eecd &= ~E1000_EECD_REQ;
- E1000_WRITE_REG(hw, EECD, eecd);
- }
-}
-/******************************************************************************
- * Reads a 16 bit word from the EEPROM.
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static int32_t
-e1000_spi_eeprom_ready(struct e1000_hw *hw)
-{
- uint16_t retry_count = 0;
- uint8_t spi_stat_reg;
-
- DEBUGFUNC();
-
- /* Read "Status Register" repeatedly until the LSB is cleared. The
- * EEPROM will signal that the command has been completed by clearing
- * bit 0 of the internal status register. If it's not cleared within
- * 5 milliseconds, then error out.
- */
- retry_count = 0;
- do {
- e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
- hw->eeprom.opcode_bits);
- spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
- if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
- break;
-
- udelay(5);
- retry_count += 5;
-
- e1000_standby_eeprom(hw);
- } while (retry_count < EEPROM_MAX_RETRY_SPI);
-
- /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
- * only 0-5mSec on 5V devices)
- */
- if (retry_count >= EEPROM_MAX_RETRY_SPI) {
- DEBUGOUT("SPI EEPROM Status error\n");
- return -E1000_ERR_EEPROM;
- }
-
- return E1000_SUCCESS;
-}
-
-/******************************************************************************
- * Reads a 16 bit word from the EEPROM.
- *
- * hw - Struct containing variables accessed by shared code
- * offset - offset of word in the EEPROM to read
- * data - word read from the EEPROM
- *****************************************************************************/
-static int32_t
-e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
- uint16_t words, uint16_t *data)
-{
- struct e1000_eeprom_info *eeprom = &hw->eeprom;
- uint32_t i = 0;
-
- DEBUGFUNC();
-
- /* If eeprom is not yet detected, do so now */
- if (eeprom->word_size == 0)
- e1000_init_eeprom_params(hw);
-
- /* A check for invalid values: offset too large, too many words,
- * and not enough words.
- */
- if ((offset >= eeprom->word_size) ||
- (words > eeprom->word_size - offset) ||
- (words == 0)) {
- DEBUGOUT("\"words\" parameter out of bounds."
- "Words = %d, size = %d\n", offset, eeprom->word_size);
- return -E1000_ERR_EEPROM;
- }
-
- /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
- * directly. In this case, we need to acquire the EEPROM so that
- * FW or other port software does not interrupt.
- */
- if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
- hw->eeprom.use_eerd == FALSE) {
-
- /* Prepare the EEPROM for bit-bang reading */
- if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
- return -E1000_ERR_EEPROM;
- }
-
- /* Eerd register EEPROM access requires no eeprom aquire/release */
- if (eeprom->use_eerd == TRUE)
- return e1000_read_eeprom_eerd(hw, offset, words, data);
-
- /* ich8lan does not support currently. if needed, please
- * add corresponding code and functions.
- */
-#if 0
- /* ICH EEPROM access is done via the ICH flash controller */
- if (eeprom->type == e1000_eeprom_ich8)
- return e1000_read_eeprom_ich8(hw, offset, words, data);
-#endif
- /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
- * acquired the EEPROM at this point, so any returns should relase it */
- if (eeprom->type == e1000_eeprom_spi) {
- uint16_t word_in;
- uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
-
- if (e1000_spi_eeprom_ready(hw)) {
- e1000_release_eeprom(hw);
- return -E1000_ERR_EEPROM;
- }
-
- e1000_standby_eeprom(hw);
-
- /* Some SPI eeproms use the 8th address bit embedded in
- * the opcode */
- if ((eeprom->address_bits == 8) && (offset >= 128))
- read_opcode |= EEPROM_A8_OPCODE_SPI;
-
- /* Send the READ command (opcode + addr) */
- e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
- e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
- eeprom->address_bits);
-
- /* Read the data. The address of the eeprom internally
- * increments with each byte (spi) being read, saving on the
- * overhead of eeprom setup and tear-down. The address
- * counter will roll over if reading beyond the size of
- * the eeprom, thus allowing the entire memory to be read
- * starting from any offset. */
- for (i = 0; i < words; i++) {
- word_in = e1000_shift_in_ee_bits(hw, 16);
- data[i] = (word_in >> 8) | (word_in << 8);
- }
- } else if (eeprom->type == e1000_eeprom_microwire) {
- for (i = 0; i < words; i++) {
- /* Send the READ command (opcode + addr) */
- e1000_shift_out_ee_bits(hw,
- EEPROM_READ_OPCODE_MICROWIRE,
- eeprom->opcode_bits);
- e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
- eeprom->address_bits);
-
- /* Read the data. For microwire, each word requires
- * the overhead of eeprom setup and tear-down. */
- data[i] = e1000_shift_in_ee_bits(hw, 16);
- e1000_standby_eeprom(hw);
- }
- }
-
- /* End this read operation */
- e1000_release_eeprom(hw);
-
- return E1000_SUCCESS;
-}
-
-/******************************************************************************
- * Verifies that the EEPROM has a valid checksum
- *
- * hw - Struct containing variables accessed by shared code
- *
- * Reads the first 64 16 bit words of the EEPROM and sums the values read.
- * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
- * valid.
- *****************************************************************************/
-static int
-e1000_validate_eeprom_checksum(struct eth_device *nic)
-{
- struct e1000_hw *hw = nic->priv;
- uint16_t checksum = 0;
- uint16_t i, eeprom_data;
-
- DEBUGFUNC();
-
- for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
- if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
- DEBUGOUT("EEPROM Read Error\n");
- return -E1000_ERR_EEPROM;
- }
- checksum += eeprom_data;
- }
-
- if (checksum == (uint16_t) EEPROM_SUM) {
- return 0;
- } else {
- DEBUGOUT("EEPROM Checksum Invalid\n");
- return -E1000_ERR_EEPROM;
- }
-}
-
-/*****************************************************************************
- * Set PHY to class A mode
- * Assumes the following operations will follow to enable the new class mode.
- * 1. Do a PHY soft reset
- * 2. Restart auto-negotiation or force link.
- *
- * hw - Struct containing variables accessed by shared code
- ****************************************************************************/
-static int32_t
-e1000_set_phy_mode(struct e1000_hw *hw)
-{
- int32_t ret_val;
- uint16_t eeprom_data;
-
- DEBUGFUNC();
-
- if ((hw->mac_type == e1000_82545_rev_3) &&
- (hw->media_type == e1000_media_type_copper)) {
- ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
- 1, &eeprom_data);
- if (ret_val)
- return ret_val;
-
- if ((eeprom_data != EEPROM_RESERVED_WORD) &&
- (eeprom_data & EEPROM_PHY_CLASS_A)) {
- ret_val = e1000_write_phy_reg(hw,
- M88E1000_PHY_PAGE_SELECT, 0x000B);
- if (ret_val)
- return ret_val;
- ret_val = e1000_write_phy_reg(hw,
- M88E1000_PHY_GEN_CONTROL, 0x8104);
- if (ret_val)
- return ret_val;
-
- hw->phy_reset_disable = FALSE;
- }
- }
-
- return E1000_SUCCESS;
-}
-#endif /* #ifndef CONFIG_AP1000 */
-
-/***************************************************************************
- *
- * Obtaining software semaphore bit (SMBI) before resetting PHY.
- *
- * hw: Struct containing variables accessed by shared code
- *
- * returns: - E1000_ERR_RESET if fail to obtain semaphore.
- * E1000_SUCCESS at any other case.
- *
- ***************************************************************************/
-static int32_t
-e1000_get_software_semaphore(struct e1000_hw *hw)
-{
- int32_t timeout = hw->eeprom.word_size + 1;
- uint32_t swsm;
-
- DEBUGFUNC();
-
- if (hw->mac_type != e1000_80003es2lan)
- return E1000_SUCCESS;
-
- while (timeout) {
- swsm = E1000_READ_REG(hw, SWSM);
- /* If SMBI bit cleared, it is now set and we hold
- * the semaphore */
- if (!(swsm & E1000_SWSM_SMBI))
- break;
- mdelay(1);
- timeout--;
- }
-
- if (!timeout) {
- DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
- return -E1000_ERR_RESET;
- }
-
- return E1000_SUCCESS;
-}
-
-/***************************************************************************
- * This function clears HW semaphore bits.
- *
- * hw: Struct containing variables accessed by shared code
- *
- * returns: - None.
- *
- ***************************************************************************/
-static void
-e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
-{
- uint32_t swsm;
-
- DEBUGFUNC();
-
- if (!hw->eeprom_semaphore_present)
- return;
-
- swsm = E1000_READ_REG(hw, SWSM);
- if (hw->mac_type == e1000_80003es2lan) {
- /* Release both semaphores. */
- swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
- } else
- swsm &= ~(E1000_SWSM_SWESMBI);
- E1000_WRITE_REG(hw, SWSM, swsm);
-}
-
-/***************************************************************************
- *
- * Using the combination of SMBI and SWESMBI semaphore bits when resetting
- * adapter or Eeprom access.
- *
- * hw: Struct containing variables accessed by shared code
- *
- * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
- * E1000_SUCCESS at any other case.
- *
- ***************************************************************************/
-static int32_t
-e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
-{
- int32_t timeout;
- uint32_t swsm;
-
- DEBUGFUNC();
-
- if (!hw->eeprom_semaphore_present)
- return E1000_SUCCESS;
-
- if (hw->mac_type == e1000_80003es2lan) {
- /* Get the SW semaphore. */
- if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
- return -E1000_ERR_EEPROM;
- }
-
- /* Get the FW semaphore. */
- timeout = hw->eeprom.word_size + 1;
- while (timeout) {
- swsm = E1000_READ_REG(hw, SWSM);
- swsm |= E1000_SWSM_SWESMBI;
- E1000_WRITE_REG(hw, SWSM, swsm);
- /* if we managed to set the bit we got the semaphore. */
- swsm = E1000_READ_REG(hw, SWSM);
- if (swsm & E1000_SWSM_SWESMBI)
- break;
-
- udelay(50);
- timeout--;
- }
-
- if (!timeout) {
- /* Release semaphores */
- e1000_put_hw_eeprom_semaphore(hw);
- DEBUGOUT("Driver can't access the Eeprom - "
- "SWESMBI bit is set.\n");
- return -E1000_ERR_EEPROM;
- }
-
- return E1000_SUCCESS;
-}
-
-static int32_t
-e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
-{
- uint32_t swfw_sync = 0;
- uint32_t swmask = mask;
- uint32_t fwmask = mask << 16;
- int32_t timeout = 200;
-
- DEBUGFUNC();
- while (timeout) {
- if (e1000_get_hw_eeprom_semaphore(hw))
- return -E1000_ERR_SWFW_SYNC;
-
- swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
- if (!(swfw_sync & (fwmask | swmask)))
- break;
-
- /* firmware currently using resource (fwmask) */
- /* or other software thread currently using resource (swmask) */
- e1000_put_hw_eeprom_semaphore(hw);
- mdelay(5);
- timeout--;
- }
-
- if (!timeout) {
- DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
- return -E1000_ERR_SWFW_SYNC;
- }
-
- swfw_sync |= swmask;
- E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
-
- e1000_put_hw_eeprom_semaphore(hw);
- return E1000_SUCCESS;
-}
-
-/******************************************************************************
- * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
- * second function of dual function devices
- *
- * nic - Struct containing variables accessed by shared code
- *****************************************************************************/
-static int
-e1000_read_mac_addr(struct eth_device *nic)
-{
-#ifndef CONFIG_AP1000
- struct e1000_hw *hw = nic->priv;
- uint16_t offset;
- uint16_t eeprom_data;
- int i;
-
- DEBUGFUNC();
-
- for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
- offset = i >> 1;
- if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
- DEBUGOUT("EEPROM Read Error\n");
- return -E1000_ERR_EEPROM;
- }
- nic->enetaddr[i] = eeprom_data & 0xff;
- nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
- }
- if ((hw->mac_type == e1000_82546) &&
- (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
- /* Invert the last bit if this is the second device */
- nic->enetaddr[5] += 1;
- }
-#ifdef CONFIG_E1000_FALLBACK_MAC
- if ( *(u32*)(nic->enetaddr) == 0 || *(u32*)(nic->enetaddr) == ~0 ) {
- unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC;
-
- memcpy (nic->enetaddr, fb_mac, NODE_ADDRESS_SIZE);
- }
-#endif
-#else
- /*
- * The AP1000's e1000 has no eeprom; the MAC address is stored in the
- * environment variables. Currently this does not support the addition
- * of a PMC e1000 card, which is certainly a possibility, so this should
- * be updated to properly use the env variable only for the onboard e1000
- */
-
- int ii;
- char *s, *e;
-
- DEBUGFUNC();
-
- s = getenv ("ethaddr");
- if (s == NULL) {
- return -E1000_ERR_EEPROM;
- } else {
- for(ii = 0; ii < 6; ii++) {
- nic->enetaddr[ii] = s ? simple_strtoul (s, &e, 16) : 0;
- if (s){
- s = (*e) ? e + 1 : e;
- }
- }
- }
-#endif
- return 0;
-}
-
-/******************************************************************************
- * Initializes receive address filters.
- *
- * hw - Struct containing variables accessed by shared code
- *
- * Places the MAC address in receive address register 0 and clears the rest
- * of the receive addresss registers. Clears the multicast table. Assumes
- * the receiver is in reset when the routine is called.
- *****************************************************************************/
-static void
-e1000_init_rx_addrs(struct eth_device *nic)
-{
- struct e1000_hw *hw = nic->priv;
- uint32_t i;
- uint32_t addr_low;
- uint32_t addr_high;
-
- DEBUGFUNC();
-
- /* Setup the receive address. */
- DEBUGOUT("Programming MAC Address into RAR[0]\n");
- addr_low = (nic->enetaddr[0] |
- (nic->enetaddr[1] << 8) |
- (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24));
-
- addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV);
-
- E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
- E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
-
- /* Zero out the other 15 receive addresses. */
- DEBUGOUT("Clearing RAR[1-15]\n");
- for (i = 1; i < E1000_RAR_ENTRIES; i++) {
- E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
- E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
- }
-}
-
-/******************************************************************************
- * Clears the VLAN filer table
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static void
-e1000_clear_vfta(struct e1000_hw *hw)
-{
- uint32_t offset;
-
- for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
- E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
-}
-
-/******************************************************************************
- * Set the mac type member in the hw struct.
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-int32_t
-e1000_set_mac_type(struct e1000_hw *hw)
-{
- DEBUGFUNC();
-
- switch (hw->device_id) {
- case E1000_DEV_ID_82542:
- switch (hw->revision_id) {
- case E1000_82542_2_0_REV_ID:
- hw->mac_type = e1000_82542_rev2_0;
- break;
- case E1000_82542_2_1_REV_ID:
- hw->mac_type = e1000_82542_rev2_1;
- break;
- default:
- /* Invalid 82542 revision ID */
- return -E1000_ERR_MAC_TYPE;
- }
- break;
- case E1000_DEV_ID_82543GC_FIBER:
- case E1000_DEV_ID_82543GC_COPPER:
- hw->mac_type = e1000_82543;
- break;
- case E1000_DEV_ID_82544EI_COPPER:
- case E1000_DEV_ID_82544EI_FIBER:
- case E1000_DEV_ID_82544GC_COPPER:
- case E1000_DEV_ID_82544GC_LOM:
- hw->mac_type = e1000_82544;
- break;
- case E1000_DEV_ID_82540EM:
- case E1000_DEV_ID_82540EM_LOM:
- case E1000_DEV_ID_82540EP:
- case E1000_DEV_ID_82540EP_LOM:
- case E1000_DEV_ID_82540EP_LP:
- hw->mac_type = e1000_82540;
- break;
- case E1000_DEV_ID_82545EM_COPPER:
- case E1000_DEV_ID_82545EM_FIBER:
- hw->mac_type = e1000_82545;
- break;
- case E1000_DEV_ID_82545GM_COPPER:
- case E1000_DEV_ID_82545GM_FIBER:
- case E1000_DEV_ID_82545GM_SERDES:
- hw->mac_type = e1000_82545_rev_3;
- break;
- case E1000_DEV_ID_82546EB_COPPER:
- case E1000_DEV_ID_82546EB_FIBER:
- case E1000_DEV_ID_82546EB_QUAD_COPPER:
- hw->mac_type = e1000_82546;
- break;
- case E1000_DEV_ID_82546GB_COPPER:
- case E1000_DEV_ID_82546GB_FIBER:
- case E1000_DEV_ID_82546GB_SERDES:
- case E1000_DEV_ID_82546GB_PCIE:
- case E1000_DEV_ID_82546GB_QUAD_COPPER:
- case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
- hw->mac_type = e1000_82546_rev_3;
- break;
- case E1000_DEV_ID_82541EI:
- case E1000_DEV_ID_82541EI_MOBILE:
- case E1000_DEV_ID_82541ER_LOM:
- hw->mac_type = e1000_82541;
- break;
- case E1000_DEV_ID_82541ER:
- case E1000_DEV_ID_82541GI:
- case E1000_DEV_ID_82541GI_LF:
- case E1000_DEV_ID_82541GI_MOBILE:
- hw->mac_type = e1000_82541_rev_2;
- break;
- case E1000_DEV_ID_82547EI:
- case E1000_DEV_ID_82547EI_MOBILE:
- hw->mac_type = e1000_82547;
- break;
- case E1000_DEV_ID_82547GI:
- hw->mac_type = e1000_82547_rev_2;
- break;
- case E1000_DEV_ID_82571EB_COPPER:
- case E1000_DEV_ID_82571EB_FIBER:
- case E1000_DEV_ID_82571EB_SERDES:
- case E1000_DEV_ID_82571EB_SERDES_DUAL:
- case E1000_DEV_ID_82571EB_SERDES_QUAD:
- case E1000_DEV_ID_82571EB_QUAD_COPPER:
- case E1000_DEV_ID_82571PT_QUAD_COPPER:
- case E1000_DEV_ID_82571EB_QUAD_FIBER:
- case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
- hw->mac_type = e1000_82571;
- break;
- case E1000_DEV_ID_82572EI_COPPER:
- case E1000_DEV_ID_82572EI_FIBER:
- case E1000_DEV_ID_82572EI_SERDES:
- case E1000_DEV_ID_82572EI:
- hw->mac_type = e1000_82572;
- break;
- case E1000_DEV_ID_82573E:
- case E1000_DEV_ID_82573E_IAMT:
- case E1000_DEV_ID_82573L:
- hw->mac_type = e1000_82573;
- break;
- case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
- case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
- case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
- case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
- hw->mac_type = e1000_80003es2lan;
- break;
- case E1000_DEV_ID_ICH8_IGP_M_AMT:
- case E1000_DEV_ID_ICH8_IGP_AMT:
- case E1000_DEV_ID_ICH8_IGP_C:
- case E1000_DEV_ID_ICH8_IFE:
- case E1000_DEV_ID_ICH8_IFE_GT:
- case E1000_DEV_ID_ICH8_IFE_G:
- case E1000_DEV_ID_ICH8_IGP_M:
- hw->mac_type = e1000_ich8lan;
- break;
- default:
- /* Should never have loaded on this device */
- return -E1000_ERR_MAC_TYPE;
- }
- return E1000_SUCCESS;
-}
-
-/******************************************************************************
- * Reset the transmit and receive units; mask and clear all interrupts.
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-void
-e1000_reset_hw(struct e1000_hw *hw)
-{
- uint32_t ctrl;
- uint32_t ctrl_ext;
- uint32_t icr;
- uint32_t manc;
-
- DEBUGFUNC();
-
- /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
- if (hw->mac_type == e1000_82542_rev2_0) {
- DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
- pci_write_config_word(hw->pdev, PCI_COMMAND,
- hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
- }
-
- /* Clear interrupt mask to stop board from generating interrupts */
- DEBUGOUT("Masking off all interrupts\n");
- E1000_WRITE_REG(hw, IMC, 0xffffffff);
-
- /* Disable the Transmit and Receive units. Then delay to allow
- * any pending transactions to complete before we hit the MAC with
- * the global reset.
- */
- E1000_WRITE_REG(hw, RCTL, 0);
- E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
- E1000_WRITE_FLUSH(hw);
-
- /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
- hw->tbi_compatibility_on = FALSE;
-
- /* Delay to allow any outstanding PCI transactions to complete before
- * resetting the device
- */
- mdelay(10);
-
- /* Issue a global reset to the MAC. This will reset the chip's
- * transmit, receive, DMA, and link units. It will not effect
- * the current PCI configuration. The global reset bit is self-
- * clearing, and should clear within a microsecond.
- */
- DEBUGOUT("Issuing a global reset to MAC\n");
- ctrl = E1000_READ_REG(hw, CTRL);
-
- E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
-
- /* Force a reload from the EEPROM if necessary */
- if (hw->mac_type < e1000_82540) {
- /* Wait for reset to complete */
- udelay(10);
- ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
- ctrl_ext |= E1000_CTRL_EXT_EE_RST;
- E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
- E1000_WRITE_FLUSH(hw);
- /* Wait for EEPROM reload */
- mdelay(2);
- } else {
- /* Wait for EEPROM reload (it happens automatically) */
- mdelay(4);
- /* Dissable HW ARPs on ASF enabled adapters */
- manc = E1000_READ_REG(hw, MANC);
- manc &= ~(E1000_MANC_ARP_EN);
- E1000_WRITE_REG(hw, MANC, manc);
- }
-
- /* Clear interrupt mask to stop board from generating interrupts */
- DEBUGOUT("Masking off all interrupts\n");
- E1000_WRITE_REG(hw, IMC, 0xffffffff);
-
- /* Clear any pending interrupt events. */
- icr = E1000_READ_REG(hw, ICR);
-
- /* If MWI was previously enabled, reenable it. */
- if (hw->mac_type == e1000_82542_rev2_0) {
- pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
- }
- E1000_WRITE_REG(hw, PBA, E1000_DEFAULT_PBA);
-}
-
-/******************************************************************************
- *
- * Initialize a number of hardware-dependent bits
- *
- * hw: Struct containing variables accessed by shared code
- *
- * This function contains hardware limitation workarounds for PCI-E adapters
- *
- *****************************************************************************/
-static void
-e1000_initialize_hardware_bits(struct e1000_hw *hw)
-{
- if ((hw->mac_type >= e1000_82571) &&
- (!hw->initialize_hw_bits_disable)) {
- /* Settings common to all PCI-express silicon */
- uint32_t reg_ctrl, reg_ctrl_ext;
- uint32_t reg_tarc0, reg_tarc1;
- uint32_t reg_tctl;
- uint32_t reg_txdctl, reg_txdctl1;
-
- /* link autonegotiation/sync workarounds */
- reg_tarc0 = E1000_READ_REG(hw, TARC0);
- reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
-
- /* Enable not-done TX descriptor counting */
- reg_txdctl = E1000_READ_REG(hw, TXDCTL);
- reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
- E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
-
- reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
- reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
- E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
-
- switch (hw->mac_type) {
- case e1000_82571:
- case e1000_82572:
- /* Clear PHY TX compatible mode bits */
- reg_tarc1 = E1000_READ_REG(hw, TARC1);
- reg_tarc1 &= ~((1 << 30)|(1 << 29));
-
- /* link autonegotiation/sync workarounds */
- reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
-
- /* TX ring control fixes */
- reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
-
- /* Multiple read bit is reversed polarity */
- reg_tctl = E1000_READ_REG(hw, TCTL);
- if (reg_tctl & E1000_TCTL_MULR)
- reg_tarc1 &= ~(1 << 28);
- else
- reg_tarc1 |= (1 << 28);
-
- E1000_WRITE_REG(hw, TARC1, reg_tarc1);
- break;
- case e1000_82573:
- reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
- reg_ctrl_ext &= ~(1 << 23);
- reg_ctrl_ext |= (1 << 22);
-
- /* TX byte count fix */
- reg_ctrl = E1000_READ_REG(hw, CTRL);
- reg_ctrl &= ~(1 << 29);
-
- E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
- E1000_WRITE_REG(hw, CTRL, reg_ctrl);
- break;
- case e1000_80003es2lan:
- /* improve small packet performace for fiber/serdes */
- if ((hw->media_type == e1000_media_type_fiber)
- || (hw->media_type ==
- e1000_media_type_internal_serdes)) {
- reg_tarc0 &= ~(1 << 20);
- }
-
- /* Multiple read bit is reversed polarity */
- reg_tctl = E1000_READ_REG(hw, TCTL);
- reg_tarc1 = E1000_READ_REG(hw, TARC1);
- if (reg_tctl & E1000_TCTL_MULR)
- reg_tarc1 &= ~(1 << 28);
- else
- reg_tarc1 |= (1 << 28);
-
- E1000_WRITE_REG(hw, TARC1, reg_tarc1);
- break;
- case e1000_ich8lan:
- /* Reduce concurrent DMA requests to 3 from 4 */
- if ((hw->revision_id < 3) ||
- ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
- (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
- reg_tarc0 |= ((1 << 29)|(1 << 28));
-
- reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
- reg_ctrl_ext |= (1 << 22);
- E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
-
- /* workaround TX hang with TSO=on */
- reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
-
- /* Multiple read bit is reversed polarity */
- reg_tctl = E1000_READ_REG(hw, TCTL);
- reg_tarc1 = E1000_READ_REG(hw, TARC1);
- if (reg_tctl & E1000_TCTL_MULR)
- reg_tarc1 &= ~(1 << 28);
- else
- reg_tarc1 |= (1 << 28);
-
- /* workaround TX hang with TSO=on */
- reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
-
- E1000_WRITE_REG(hw, TARC1, reg_tarc1);
- break;
- default:
- break;
- }
-
- E1000_WRITE_REG(hw, TARC0, reg_tarc0);
- }
-}
-
-/******************************************************************************
- * Performs basic configuration of the adapter.
- *
- * hw - Struct containing variables accessed by shared code
- *
- * Assumes that the controller has previously been reset and is in a
- * post-reset uninitialized state. Initializes the receive address registers,
- * multicast table, and VLAN filter table. Calls routines to setup link
- * configuration and flow control settings. Clears all on-chip counters. Leaves
- * the transmit and receive units disabled and uninitialized.
- *****************************************************************************/
-static int
-e1000_init_hw(struct eth_device *nic)
-{
- struct e1000_hw *hw = nic->priv;
- uint32_t ctrl;
- uint32_t i;
- int32_t ret_val;
- uint16_t pcix_cmd_word;
- uint16_t pcix_stat_hi_word;
- uint16_t cmd_mmrbc;
- uint16_t stat_mmrbc;
- uint32_t mta_size;
- uint32_t reg_data;
- uint32_t ctrl_ext;
- DEBUGFUNC();
- /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
- if ((hw->mac_type == e1000_ich8lan) &&
- ((hw->revision_id < 3) ||
- ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
- (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
- reg_data = E1000_READ_REG(hw, STATUS);
- reg_data &= ~0x80000000;
- E1000_WRITE_REG(hw, STATUS, reg_data);
- }
- /* Do not need initialize Identification LED */
-
- /* Set the media type and TBI compatibility */
- e1000_set_media_type(hw);
-
- /* Must be called after e1000_set_media_type
- * because media_type is used */
- e1000_initialize_hardware_bits(hw);
-
- /* Disabling VLAN filtering. */
- DEBUGOUT("Initializing the IEEE VLAN\n");
- /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
- if (hw->mac_type != e1000_ich8lan) {
- if (hw->mac_type < e1000_82545_rev_3)
- E1000_WRITE_REG(hw, VET, 0);
- e1000_clear_vfta(hw);
- }
-
- /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
- if (hw->mac_type == e1000_82542_rev2_0) {
- DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
- pci_write_config_word(hw->pdev, PCI_COMMAND,
- hw->
- pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
- E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
- E1000_WRITE_FLUSH(hw);
- mdelay(5);
- }
-
- /* Setup the receive address. This involves initializing all of the Receive
- * Address Registers (RARs 0 - 15).
- */
- e1000_init_rx_addrs(nic);
-
- /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
- if (hw->mac_type == e1000_82542_rev2_0) {
- E1000_WRITE_REG(hw, RCTL, 0);
- E1000_WRITE_FLUSH(hw);
- mdelay(1);
- pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
- }
-
- /* Zero out the Multicast HASH table */
- DEBUGOUT("Zeroing the MTA\n");
- mta_size = E1000_MC_TBL_SIZE;
- if (hw->mac_type == e1000_ich8lan)
- mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
- for (i = 0; i < mta_size; i++) {
- E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
- /* use write flush to prevent Memory Write Block (MWB) from
- * occuring when accessing our register space */
- E1000_WRITE_FLUSH(hw);
- }
-#if 0
- /* Set the PCI priority bit correctly in the CTRL register. This
- * determines if the adapter gives priority to receives, or if it
- * gives equal priority to transmits and receives. Valid only on
- * 82542 and 82543 silicon.
- */
- if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
- ctrl = E1000_READ_REG(hw, CTRL);
- E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
- }
-#endif
- switch (hw->mac_type) {
- case e1000_82545_rev_3:
- case e1000_82546_rev_3:
- break;
- default:
- /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
- if (hw->bus_type == e1000_bus_type_pcix) {
- pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
- &pcix_cmd_word);
- pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
- &pcix_stat_hi_word);
- cmd_mmrbc =
- (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
- PCIX_COMMAND_MMRBC_SHIFT;
- stat_mmrbc =
- (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
- PCIX_STATUS_HI_MMRBC_SHIFT;
- if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
- stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
- if (cmd_mmrbc > stat_mmrbc) {
- pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
- pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
- pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
- pcix_cmd_word);
- }
- }
- break;
- }
-
- /* More time needed for PHY to initialize */
- if (hw->mac_type == e1000_ich8lan)
- mdelay(15);
-
- /* Call a subroutine to configure the link and setup flow control. */
- ret_val = e1000_setup_link(nic);
-
- /* Set the transmit descriptor write-back policy */
- if (hw->mac_type > e1000_82544) {
- ctrl = E1000_READ_REG(hw, TXDCTL);
- ctrl =
- (ctrl & ~E1000_TXDCTL_WTHRESH) |
- E1000_TXDCTL_FULL_TX_DESC_WB;
- E1000_WRITE_REG(hw, TXDCTL, ctrl);
- }
-
- switch (hw->mac_type) {
- default:
- break;
- case e1000_80003es2lan:
- /* Enable retransmit on late collisions */
- reg_data = E1000_READ_REG(hw, TCTL);
- reg_data |= E1000_TCTL_RTLC;
- E1000_WRITE_REG(hw, TCTL, reg_data);
-
- /* Configure Gigabit Carry Extend Padding */
- reg_data = E1000_READ_REG(hw, TCTL_EXT);
- reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
- reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
- E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
-
- /* Configure Transmit Inter-Packet Gap */
- reg_data = E1000_READ_REG(hw, TIPG);
- reg_data &= ~E1000_TIPG_IPGT_MASK;
- reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
- E1000_WRITE_REG(hw, TIPG, reg_data);
-
- reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
- reg_data &= ~0x00100000;
- E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
- /* Fall through */
- case e1000_82571:
- case e1000_82572:
- case e1000_ich8lan:
- ctrl = E1000_READ_REG(hw, TXDCTL1);
- ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
- | E1000_TXDCTL_FULL_TX_DESC_WB;
- E1000_WRITE_REG(hw, TXDCTL1, ctrl);
- break;
- }
-
- if (hw->mac_type == e1000_82573) {
- uint32_t gcr = E1000_READ_REG(hw, GCR);
- gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
- E1000_WRITE_REG(hw, GCR, gcr);
- }
-
-#if 0
- /* Clear all of the statistics registers (clear on read). It is
- * important that we do this after we have tried to establish link
- * because the symbol error count will increment wildly if there
- * is no link.
- */
- e1000_clear_hw_cntrs(hw);
-
- /* ICH8 No-snoop bits are opposite polarity.
- * Set to snoop by default after reset. */
- if (hw->mac_type == e1000_ich8lan)
- e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
-#endif
-
- if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
- hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
- ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
- /* Relaxed ordering must be disabled to avoid a parity
- * error crash in a PCI slot. */
- ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
- E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
- }
-
- return ret_val;
-}
-
-/******************************************************************************
- * Configures flow control and link settings.
- *
- * hw - Struct containing variables accessed by shared code
- *
- * Determines which flow control settings to use. Calls the apropriate media-
- * specific link configuration function. Configures the flow control settings.
- * Assuming the adapter has a valid link partner, a valid link should be
- * established. Assumes the hardware has previously been reset and the
- * transmitter and receiver are not enabled.
- *****************************************************************************/
-static int
-e1000_setup_link(struct eth_device *nic)
-{
- struct e1000_hw *hw = nic->priv;
- uint32_t ctrl_ext;
- int32_t ret_val;
- uint16_t eeprom_data;
-
- DEBUGFUNC();
-
- /* In the case of the phy reset being blocked, we already have a link.
- * We do not have to set it up again. */
- if (e1000_check_phy_reset_block(hw))
- return E1000_SUCCESS;
-
-#ifndef CONFIG_AP1000
- /* Read and store word 0x0F of the EEPROM. This word contains bits
- * that determine the hardware's default PAUSE (flow control) mode,
- * a bit that determines whether the HW defaults to enabling or
- * disabling auto-negotiation, and the direction of the
- * SW defined pins. If there is no SW over-ride of the flow
- * control setting, then the variable hw->fc will
- * be initialized based on a value in the EEPROM.
- */
- if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
- &eeprom_data) < 0) {
- DEBUGOUT("EEPROM Read Error\n");
- return -E1000_ERR_EEPROM;
- }
-#else
- /* we have to hardcode the proper value for our hardware. */
- /* this value is for the 82540EM pci card used for prototyping, and it works. */
- eeprom_data = 0xb220;
-#endif
-
- if (hw->fc == e1000_fc_default) {
- switch (hw->mac_type) {
- case e1000_ich8lan:
- case e1000_82573:
- hw->fc = e1000_fc_full;
- break;
- default:
-#ifndef CONFIG_AP1000
- ret_val = e1000_read_eeprom(hw,
- EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
- if (ret_val) {
- DEBUGOUT("EEPROM Read Error\n");
- return -E1000_ERR_EEPROM;
- }
-#else
- eeprom_data = 0xb220;
-#endif
- if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
- hw->fc = e1000_fc_none;
- else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
- EEPROM_WORD0F_ASM_DIR)
- hw->fc = e1000_fc_tx_pause;
- else
- hw->fc = e1000_fc_full;
- break;
- }
- }
-
- /* We want to save off the original Flow Control configuration just
- * in case we get disconnected and then reconnected into a different
- * hub or switch with different Flow Control capabilities.
- */
- if (hw->mac_type == e1000_82542_rev2_0)
- hw->fc &= (~e1000_fc_tx_pause);
-
- if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
- hw->fc &= (~e1000_fc_rx_pause);
-
- hw->original_fc = hw->fc;
-
- DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
-
- /* Take the 4 bits from EEPROM word 0x0F that determine the initial
- * polarity value for the SW controlled pins, and setup the
- * Extended Device Control reg with that info.
- * This is needed because one of the SW controlled pins is used for
- * signal detection. So this should be done before e1000_setup_pcs_link()
- * or e1000_phy_setup() is called.
- */
- if (hw->mac_type == e1000_82543) {
- ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
- SWDPIO__EXT_SHIFT);
- E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
- }
-
- /* Call the necessary subroutine to configure the link. */
- ret_val = (hw->media_type == e1000_media_type_fiber) ?
- e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic);
- if (ret_val < 0) {
- return ret_val;
- }
-
- /* Initialize the flow control address, type, and PAUSE timer
- * registers to their default values. This is done even if flow
- * control is disabled, because it does not hurt anything to
- * initialize these registers.
- */
- DEBUGOUT("Initializing the Flow Control address, type"
- "and timer regs\n");
-
- /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
- if (hw->mac_type != e1000_ich8lan) {
- E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
- E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
- E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
- }
-
- E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
-
- /* Set the flow control receive threshold registers. Normally,
- * these registers will be set to a default threshold that may be
- * adjusted later by the driver's runtime code. However, if the
- * ability to transmit pause frames in not enabled, then these
- * registers will be set to 0.
- */
- if (!(hw->fc & e1000_fc_tx_pause)) {
- E1000_WRITE_REG(hw, FCRTL, 0);
- E1000_WRITE_REG(hw, FCRTH, 0);
- } else {
- /* We need to set up the Receive Threshold high and low water marks
- * as well as (optionally) enabling the transmission of XON frames.
- */
- if (hw->fc_send_xon) {
- E1000_WRITE_REG(hw, FCRTL,
- (hw->fc_low_water | E1000_FCRTL_XONE));
- E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
- } else {
- E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
- E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
- }
- }
- return ret_val;
-}
-
-/******************************************************************************
- * Sets up link for a fiber based adapter
- *
- * hw - Struct containing variables accessed by shared code
- *
- * Manipulates Physical Coding Sublayer functions in order to configure
- * link. Assumes the hardware has been previously reset and the transmitter
- * and receiver are not enabled.
- *****************************************************************************/
-static int
-e1000_setup_fiber_link(struct eth_device *nic)
-{
- struct e1000_hw *hw = nic->priv;
- uint32_t ctrl;
- uint32_t status;
- uint32_t txcw = 0;
- uint32_t i;
- uint32_t signal;
- int32_t ret_val;
-
- DEBUGFUNC();
- /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
- * set when the optics detect a signal. On older adapters, it will be
- * cleared when there is a signal
- */
- ctrl = E1000_READ_REG(hw, CTRL);
- if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
- signal = E1000_CTRL_SWDPIN1;
- else
- signal = 0;
-
- printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal,
- ctrl);
- /* Take the link out of reset */
- ctrl &= ~(E1000_CTRL_LRST);
-
- e1000_config_collision_dist(hw);
-
- /* Check for a software override of the flow control settings, and setup
- * the device accordingly. If auto-negotiation is enabled, then software
- * will have to set the "PAUSE" bits to the correct value in the Tranmsit
- * Config Word Register (TXCW) and re-start auto-negotiation. However, if
- * auto-negotiation is disabled, then software will have to manually
- * configure the two flow control enable bits in the CTRL register.
- *
- * The possible values of the "fc" parameter are:
- * 0: Flow control is completely disabled
- * 1: Rx flow control is enabled (we can receive pause frames, but
- * not send pause frames).
- * 2: Tx flow control is enabled (we can send pause frames but we do
- * not support receiving pause frames).
- * 3: Both Rx and TX flow control (symmetric) are enabled.
- */
- switch (hw->fc) {
- case e1000_fc_none:
- /* Flow control is completely disabled by a software over-ride. */
- txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
- break;
- case e1000_fc_rx_pause:
- /* RX Flow control is enabled and TX Flow control is disabled by a
- * software over-ride. Since there really isn't a way to advertise
- * that we are capable of RX Pause ONLY, we will advertise that we
- * support both symmetric and asymmetric RX PAUSE. Later, we will
- * disable the adapter's ability to send PAUSE frames.
- */
- txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
- break;
- case e1000_fc_tx_pause:
- /* TX Flow control is enabled, and RX Flow control is disabled, by a
- * software over-ride.
- */
- txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
- break;
- case e1000_fc_full:
- /* Flow control (both RX and TX) is enabled by a software over-ride. */
- txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
- break;
- default:
- DEBUGOUT("Flow control param set incorrectly\n");
- return -E1000_ERR_CONFIG;
- break;
- }
-
- /* Since auto-negotiation is enabled, take the link out of reset (the link
- * will be in reset, because we previously reset the chip). This will
- * restart auto-negotiation. If auto-neogtiation is successful then the
- * link-up status bit will be set and the flow control enable bits (RFCE
- * and TFCE) will be set according to their negotiated value.
- */
- DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
-
- E1000_WRITE_REG(hw, TXCW, txcw);
- E1000_WRITE_REG(hw, CTRL, ctrl);
- E1000_WRITE_FLUSH(hw);
-
- hw->txcw = txcw;
- mdelay(1);
-
- /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
- * indication in the Device Status Register. Time-out if a link isn't
- * seen in 500 milliseconds seconds (Auto-negotiation should complete in
- * less than 500 milliseconds even if the other end is doing it in SW).
- */
- if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
- DEBUGOUT("Looking for Link\n");
- for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
- mdelay(10);
- status = E1000_READ_REG(hw, STATUS);
- if (status & E1000_STATUS_LU)
- break;
- }
- if (i == (LINK_UP_TIMEOUT / 10)) {
- /* AutoNeg failed to achieve a link, so we'll call
- * e1000_check_for_link. This routine will force the link up if we
- * detect a signal. This will allow us to communicate with
- * non-autonegotiating link partners.
- */
- DEBUGOUT("Never got a valid link from auto-neg!!!\n");
- hw->autoneg_failed = 1;
- ret_val = e1000_check_for_link(nic);
- if (ret_val < 0) {
- DEBUGOUT("Error while checking for link\n");
- return ret_val;
- }
- hw->autoneg_failed = 0;
- } else {
- hw->autoneg_failed = 0;
- DEBUGOUT("Valid Link Found\n");
- }
- } else {
- DEBUGOUT("No Signal Detected\n");
- return -E1000_ERR_NOLINK;
- }
- return 0;
-}
-
-/******************************************************************************
-* Make sure we have a valid PHY and change PHY mode before link setup.
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
-static int32_t
-e1000_copper_link_preconfig(struct e1000_hw *hw)
-{
- uint32_t ctrl;
- int32_t ret_val;
- uint16_t phy_data;
-
- DEBUGFUNC();
-
- ctrl = E1000_READ_REG(hw, CTRL);
- /* With 82543, we need to force speed and duplex on the MAC equal to what
- * the PHY speed and duplex configuration is. In addition, we need to
- * perform a hardware reset on the PHY to take it out of reset.
- */
- if (hw->mac_type > e1000_82543) {
- ctrl |= E1000_CTRL_SLU;
- ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
- E1000_WRITE_REG(hw, CTRL, ctrl);
- } else {
- ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
- | E1000_CTRL_SLU);
- E1000_WRITE_REG(hw, CTRL, ctrl);
- ret_val = e1000_phy_hw_reset(hw);
- if (ret_val)
- return ret_val;
- }
-
- /* Make sure we have a valid PHY */
- ret_val = e1000_detect_gig_phy(hw);
- if (ret_val) {
- DEBUGOUT("Error, did not detect valid phy.\n");
- return ret_val;
- }
- DEBUGOUT("Phy ID = %x \n", hw->phy_id);
-
-#ifndef CONFIG_AP1000
- /* Set PHY to class A mode (if necessary) */
- ret_val = e1000_set_phy_mode(hw);
- if (ret_val)
- return ret_val;
-#endif
- if ((hw->mac_type == e1000_82545_rev_3) ||
- (hw->mac_type == e1000_82546_rev_3)) {
- ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
- &phy_data);
- phy_data |= 0x00000008;
- ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
- phy_data);
- }
-
- if (hw->mac_type <= e1000_82543 ||
- hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
- hw->mac_type == e1000_82541_rev_2
- || hw->mac_type == e1000_82547_rev_2)
- hw->phy_reset_disable = FALSE;
-
- return E1000_SUCCESS;
-}
-
-/*****************************************************************************
- *
- * This function sets the lplu state according to the active flag. When
- * activating lplu this function also disables smart speed and vise versa.
- * lplu will not be activated unless the device autonegotiation advertisment
- * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
- * hw: Struct containing variables accessed by shared code
- * active - true to enable lplu false to disable lplu.
- *
- * returns: - E1000_ERR_PHY if fail to read/write the PHY
- * E1000_SUCCESS at any other case.
- *
- ****************************************************************************/
-
-static int32_t
-e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active)
-{
- uint32_t phy_ctrl = 0;
- int32_t ret_val;
- uint16_t phy_data;
- DEBUGFUNC();
-
- if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
- && hw->phy_type != e1000_phy_igp_3)
- return E1000_SUCCESS;
-
- /* During driver activity LPLU should not be used or it will attain link
- * from the lowest speeds starting from 10Mbps. The capability is used
- * for Dx transitions and states */
- if (hw->mac_type == e1000_82541_rev_2
- || hw->mac_type == e1000_82547_rev_2) {
- ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
- &phy_data);
- if (ret_val)
- return ret_val;
- } else if (hw->mac_type == e1000_ich8lan) {
- /* MAC writes into PHY register based on the state transition
- * and start auto-negotiation. SW driver can overwrite the
- * settings in CSR PHY power control E1000_PHY_CTRL register. */
- phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
- } else {
- ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
- &phy_data);
- if (ret_val)
- return ret_val;
- }
-
- if (!active) {
- if (hw->mac_type == e1000_82541_rev_2 ||
- hw->mac_type == e1000_82547_rev_2) {
- phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
- ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
- phy_data);
- if (ret_val)
- return ret_val;
- } else {
- if (hw->mac_type == e1000_ich8lan) {
- phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
- E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
- } else {
- phy_data &= ~IGP02E1000_PM_D3_LPLU;
- ret_val = e1000_write_phy_reg(hw,
- IGP02E1000_PHY_POWER_MGMT, phy_data);
- if (ret_val)
- return ret_val;
- }
- }
-
- /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
- * Dx states where the power conservation is most important. During
- * driver activity we should enable SmartSpeed, so performance is
- * maintained. */
- if (hw->smart_speed == e1000_smart_speed_on) {
- ret_val = e1000_read_phy_reg(hw,
- IGP01E1000_PHY_PORT_CONFIG, &phy_data);
- if (ret_val)
- return ret_val;
-
- phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
- ret_val = e1000_write_phy_reg(hw,
- IGP01E1000_PHY_PORT_CONFIG, phy_data);
- if (ret_val)
- return ret_val;
- } else if (hw->smart_speed == e1000_smart_speed_off) {
- ret_val = e1000_read_phy_reg(hw,
- IGP01E1000_PHY_PORT_CONFIG, &phy_data);
- if (ret_val)
- return ret_val;
-
- phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
- ret_val = e1000_write_phy_reg(hw,
- IGP01E1000_PHY_PORT_CONFIG, phy_data);
- if (ret_val)
- return ret_val;
- }
-
- } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
- || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
- (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
-
- if (hw->mac_type == e1000_82541_rev_2 ||
- hw->mac_type == e1000_82547_rev_2) {
- phy_data |= IGP01E1000_GMII_FLEX_SPD;
- ret_val = e1000_write_phy_reg(hw,
- IGP01E1000_GMII_FIFO, phy_data);
- if (ret_val)
- return ret_val;
- } else {
- if (hw->mac_type == e1000_ich8lan) {
- phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
- E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
- } else {
- phy_data |= IGP02E1000_PM_D3_LPLU;
- ret_val = e1000_write_phy_reg(hw,
- IGP02E1000_PHY_POWER_MGMT, phy_data);
- if (ret_val)
- return ret_val;
- }
- }
-
- /* When LPLU is enabled we should disable SmartSpeed */
- ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
- &phy_data);
- if (ret_val)
- return ret_val;
-
- phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
- ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
- phy_data);
- if (ret_val)
- return ret_val;
- }
- return E1000_SUCCESS;
-}
-
-/*****************************************************************************
- *
- * This function sets the lplu d0 state according to the active flag. When
- * activating lplu this function also disables smart speed and vise versa.
- * lplu will not be activated unless the device autonegotiation advertisment
- * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
- * hw: Struct containing variables accessed by shared code
- * active - true to enable lplu false to disable lplu.
- *
- * returns: - E1000_ERR_PHY if fail to read/write the PHY
- * E1000_SUCCESS at any other case.
- *
- ****************************************************************************/
-
-static int32_t
-e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active)
-{
- uint32_t phy_ctrl = 0;
- int32_t ret_val;
- uint16_t phy_data;
- DEBUGFUNC();
-
- if (hw->mac_type <= e1000_82547_rev_2)
- return E1000_SUCCESS;
-
- if (hw->mac_type == e1000_ich8lan) {
- phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
- } else {
- ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
- &phy_data);
- if (ret_val)
- return ret_val;
- }
-
- if (!active) {
- if (hw->mac_type == e1000_ich8lan) {
- phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
- E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
- } else {
- phy_data &= ~IGP02E1000_PM_D0_LPLU;
- ret_val = e1000_write_phy_reg(hw,
- IGP02E1000_PHY_POWER_MGMT, phy_data);
- if (ret_val)
- return ret_val;
- }
-
- /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
- * Dx states where the power conservation is most important. During
- * driver activity we should enable SmartSpeed, so performance is
- * maintained. */
- if (hw->smart_speed == e1000_smart_speed_on) {
- ret_val = e1000_read_phy_reg(hw,
- IGP01E1000_PHY_PORT_CONFIG, &phy_data);
- if (ret_val)
- return ret_val;
-
- phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
- ret_val = e1000_write_phy_reg(hw,
- IGP01E1000_PHY_PORT_CONFIG, phy_data);
- if (ret_val)
- return ret_val;
- } else if (hw->smart_speed == e1000_smart_speed_off) {
- ret_val = e1000_read_phy_reg(hw,
- IGP01E1000_PHY_PORT_CONFIG, &phy_data);
- if (ret_val)
- return ret_val;
-
- phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
- ret_val = e1000_write_phy_reg(hw,
- IGP01E1000_PHY_PORT_CONFIG, phy_data);
- if (ret_val)
- return ret_val;
- }
-
-
- } else {
-
- if (hw->mac_type == e1000_ich8lan) {
- phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
- E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
- } else {
- phy_data |= IGP02E1000_PM_D0_LPLU;
- ret_val = e1000_write_phy_reg(hw,
- IGP02E1000_PHY_POWER_MGMT, phy_data);
- if (ret_val)
- return ret_val;
- }
-
- /* When LPLU is enabled we should disable SmartSpeed */
- ret_val = e1000_read_phy_reg(hw,
- IGP01E1000_PHY_PORT_CONFIG, &phy_data);
- if (ret_val)
- return ret_val;
-
- phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
- ret_val = e1000_write_phy_reg(hw,
- IGP01E1000_PHY_PORT_CONFIG, phy_data);
- if (ret_val)
- return ret_val;
-
- }
- return E1000_SUCCESS;
-}
-
-/********************************************************************
-* Copper link setup for e1000_phy_igp series.
-*
-* hw - Struct containing variables accessed by shared code
-*********************************************************************/
-static int32_t
-e1000_copper_link_igp_setup(struct e1000_hw *hw)
-{
- uint32_t led_ctrl;
- int32_t ret_val;
- uint16_t phy_data;
-
- DEBUGFUNC();
-
- if (hw->phy_reset_disable)
- return E1000_SUCCESS;
-
- ret_val = e1000_phy_reset(hw);
- if (ret_val) {
- DEBUGOUT("Error Resetting the PHY\n");
- return ret_val;
- }
-
- /* Wait 15ms for MAC to configure PHY from eeprom settings */
- mdelay(15);
- if (hw->mac_type != e1000_ich8lan) {
- /* Configure activity LED after PHY reset */
- led_ctrl = E1000_READ_REG(hw, LEDCTL);
- led_ctrl &= IGP_ACTIVITY_LED_MASK;
- led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
- E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
- }
-
- /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
- if (hw->phy_type == e1000_phy_igp) {
- /* disable lplu d3 during driver init */
- ret_val = e1000_set_d3_lplu_state(hw, FALSE);
- if (ret_val) {
- DEBUGOUT("Error Disabling LPLU D3\n");
- return ret_val;
- }
- }
-
- /* disable lplu d0 during driver init */
- ret_val = e1000_set_d0_lplu_state(hw, FALSE);
- if (ret_val) {
- DEBUGOUT("Error Disabling LPLU D0\n");
- return ret_val;
- }
- /* Configure mdi-mdix settings */
- ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
- if (ret_val)
- return ret_val;
-
- if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
- hw->dsp_config_state = e1000_dsp_config_disabled;
- /* Force MDI for earlier revs of the IGP PHY */
- phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
- | IGP01E1000_PSCR_FORCE_MDI_MDIX);
- hw->mdix = 1;
-
- } else {
- hw->dsp_config_state = e1000_dsp_config_enabled;
- phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
-
- switch (hw->mdix) {
- case 1:
- phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
- break;
- case 2:
- phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
- break;
- case 0:
- default:
- phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
- break;
- }
- }
- ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
- if (ret_val)
- return ret_val;
-
- /* set auto-master slave resolution settings */
- if (hw->autoneg) {
- e1000_ms_type phy_ms_setting = hw->master_slave;
-
- if (hw->ffe_config_state == e1000_ffe_config_active)
- hw->ffe_config_state = e1000_ffe_config_enabled;
-
- if (hw->dsp_config_state == e1000_dsp_config_activated)
- hw->dsp_config_state = e1000_dsp_config_enabled;
-
- /* when autonegotiation advertisment is only 1000Mbps then we
- * should disable SmartSpeed and enable Auto MasterSlave
- * resolution as hardware default. */
- if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
- /* Disable SmartSpeed */
- ret_val = e1000_read_phy_reg(hw,
- IGP01E1000_PHY_PORT_CONFIG, &phy_data);
- if (ret_val)
- return ret_val;
- phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
- ret_val = e1000_write_phy_reg(hw,
- IGP01E1000_PHY_PORT_CONFIG, phy_data);
- if (ret_val)
- return ret_val;
- /* Set auto Master/Slave resolution process */
- ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
- &phy_data);
- if (ret_val)
- return ret_val;
- phy_data &= ~CR_1000T_MS_ENABLE;
- ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
- phy_data);
- if (ret_val)
- return ret_val;
- }
-
- ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
- if (ret_val)
- return ret_val;
-
- /* load defaults for future use */
- hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
- ((phy_data & CR_1000T_MS_VALUE) ?
- e1000_ms_force_master :
- e1000_ms_force_slave) :
- e1000_ms_auto;
-
- switch (phy_ms_setting) {
- case e1000_ms_force_master:
- phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
- break;
- case e1000_ms_force_slave:
- phy_data |= CR_1000T_MS_ENABLE;
- phy_data &= ~(CR_1000T_MS_VALUE);
- break;
- case e1000_ms_auto:
- phy_data &= ~CR_1000T_MS_ENABLE;
- default:
- break;
- }
- ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
- if (ret_val)
- return ret_val;
- }
-
- return E1000_SUCCESS;
-}
-
-/*****************************************************************************
- * This function checks the mode of the firmware.
- *
- * returns - TRUE when the mode is IAMT or FALSE.
- ****************************************************************************/
-boolean_t
-e1000_check_mng_mode(struct e1000_hw *hw)
-{
- uint32_t fwsm;
- DEBUGFUNC();
-
- fwsm = E1000_READ_REG(hw, FWSM);
-
- if (hw->mac_type == e1000_ich8lan) {
- if ((fwsm & E1000_FWSM_MODE_MASK) ==
- (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
- return TRUE;
- } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
- (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
- return TRUE;
-
- return FALSE;
-}
-
-static int32_t
-e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
-{
- uint32_t reg_val;
- uint16_t swfw;
- DEBUGFUNC();
-
- if ((hw->mac_type == e1000_80003es2lan) &&
- (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
- swfw = E1000_SWFW_PHY1_SM;
- } else {
- swfw = E1000_SWFW_PHY0_SM;
- }
- if (e1000_swfw_sync_acquire(hw, swfw))
- return -E1000_ERR_SWFW_SYNC;
-
- reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
- & E1000_KUMCTRLSTA_OFFSET) | data;
- E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
- udelay(2);
-
- return E1000_SUCCESS;
-}
-
-static int32_t
-e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
-{
- uint32_t reg_val;
- uint16_t swfw;
- DEBUGFUNC();
-
- if ((hw->mac_type == e1000_80003es2lan) &&
- (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
- swfw = E1000_SWFW_PHY1_SM;
- } else {
- swfw = E1000_SWFW_PHY0_SM;
- }
- if (e1000_swfw_sync_acquire(hw, swfw))
- return -E1000_ERR_SWFW_SYNC;
-
- /* Write register address */
- reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
- E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
- E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
- udelay(2);
-
- /* Read the data returned */
- reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
- *data = (uint16_t)reg_val;
-
- return E1000_SUCCESS;
-}
-
-/********************************************************************
-* Copper link setup for e1000_phy_gg82563 series.
-*
-* hw - Struct containing variables accessed by shared code
-*********************************************************************/
-static int32_t
-e1000_copper_link_ggp_setup(struct e1000_hw *hw)
-{
- int32_t ret_val;
- uint16_t phy_data;
- uint32_t reg_data;
-
- DEBUGFUNC();
-
- if (!hw->phy_reset_disable) {
- /* Enable CRS on TX for half-duplex operation. */
- ret_val = e1000_read_phy_reg(hw,
- GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
- if (ret_val)
- return ret_val;
-
- phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
- /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
- phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
-
- ret_val = e1000_write_phy_reg(hw,
- GG82563_PHY_MAC_SPEC_CTRL, phy_data);
- if (ret_val)
- return ret_val;
-
- /* Options:
- * MDI/MDI-X = 0 (default)
- * 0 - Auto for all speeds
- * 1 - MDI mode
- * 2 - MDI-X mode
- * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
- */
- ret_val = e1000_read_phy_reg(hw,
- GG82563_PHY_SPEC_CTRL, &phy_data);
- if (ret_val)
- return ret_val;
-
- phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
-
- switch (hw->mdix) {
- case 1:
- phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
- break;
- case 2:
- phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
- break;
- case 0:
- default:
- phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
- break;
- }
-
- /* Options:
- * disable_polarity_correction = 0 (default)
- * Automatic Correction for Reversed Cable Polarity
- * 0 - Disabled
- * 1 - Enabled
- */
- phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
- ret_val = e1000_write_phy_reg(hw,
- GG82563_PHY_SPEC_CTRL, phy_data);
-
- if (ret_val)
- return ret_val;
-
- /* SW Reset the PHY so all changes take effect */
- ret_val = e1000_phy_reset(hw);
- if (ret_val) {
- DEBUGOUT("Error Resetting the PHY\n");
- return ret_val;
- }
- } /* phy_reset_disable */
-
- if (hw->mac_type == e1000_80003es2lan) {
- /* Bypass RX and TX FIFO's */
- ret_val = e1000_write_kmrn_reg(hw,
- E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
- E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
- | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
- if (ret_val)
- return ret_val;
-
- ret_val = e1000_read_phy_reg(hw,
- GG82563_PHY_SPEC_CTRL_2, &phy_data);
- if (ret_val)
- return ret_val;
-
- phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
- ret_val = e1000_write_phy_reg(hw,
- GG82563_PHY_SPEC_CTRL_2, phy_data);
-
- if (ret_val)
- return ret_val;
-
- reg_data = E1000_READ_REG(hw, CTRL_EXT);
- reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
- E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
-
- ret_val = e1000_read_phy_reg(hw,
- GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
- if (ret_val)
- return ret_val;
-
- /* Do not init these registers when the HW is in IAMT mode, since the
- * firmware will have already initialized them. We only initialize
- * them if the HW is not in IAMT mode.
- */
- if (e1000_check_mng_mode(hw) == FALSE) {
- /* Enable Electrical Idle on the PHY */
- phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
- ret_val = e1000_write_phy_reg(hw,
- GG82563_PHY_PWR_MGMT_CTRL, phy_data);
- if (ret_val)
- return ret_val;
-
- ret_val = e1000_read_phy_reg(hw,
- GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
- if (ret_val)
- return ret_val;
-
- phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
- ret_val = e1000_write_phy_reg(hw,
- GG82563_PHY_KMRN_MODE_CTRL, phy_data);
-
- if (ret_val)
- return ret_val;
- }
-
- /* Workaround: Disable padding in Kumeran interface in the MAC
- * and in the PHY to avoid CRC errors.
- */
- ret_val = e1000_read_phy_reg(hw,
- GG82563_PHY_INBAND_CTRL, &phy_data);
- if (ret_val)
- return ret_val;
- phy_data |= GG82563_ICR_DIS_PADDING;
- ret_val = e1000_write_phy_reg(hw,
- GG82563_PHY_INBAND_CTRL, phy_data);
- if (ret_val)
- return ret_val;
- }
- return E1000_SUCCESS;
-}
-
-/********************************************************************
-* Copper link setup for e1000_phy_m88 series.
-*
-* hw - Struct containing variables accessed by shared code
-*********************************************************************/
-static int32_t
-e1000_copper_link_mgp_setup(struct e1000_hw *hw)
-{
- int32_t ret_val;
- uint16_t phy_data;
-
- DEBUGFUNC();
-
- if (hw->phy_reset_disable)
- return E1000_SUCCESS;
-
- /* Enable CRS on TX. This must be set for half-duplex operation. */
- ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
- if (ret_val)
- return ret_val;
-
- phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
-
- /* Options:
- * MDI/MDI-X = 0 (default)
- * 0 - Auto for all speeds
- * 1 - MDI mode
- * 2 - MDI-X mode
- * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
- */
- phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
-
- switch (hw->mdix) {
- case 1:
- phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
- break;
- case 2:
- phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
- break;
- case 3:
- phy_data |= M88E1000_PSCR_AUTO_X_1000T;
- break;
- case 0:
- default:
- phy_data |= M88E1000_PSCR_AUTO_X_MODE;
- break;
- }
-
- /* Options:
- * disable_polarity_correction = 0 (default)
- * Automatic Correction for Reversed Cable Polarity
- * 0 - Disabled
- * 1 - Enabled
- */
- phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
- ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
- if (ret_val)
- return ret_val;
-
- if (hw->phy_revision < M88E1011_I_REV_4) {
- /* Force TX_CLK in the Extended PHY Specific Control Register
- * to 25MHz clock.
- */
- ret_val = e1000_read_phy_reg(hw,
- M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
- if (ret_val)
- return ret_val;
-
- phy_data |= M88E1000_EPSCR_TX_CLK_25;
-
- if ((hw->phy_revision == E1000_REVISION_2) &&
- (hw->phy_id == M88E1111_I_PHY_ID)) {
- /* Vidalia Phy, set the downshift counter to 5x */
- phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
- phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
- ret_val = e1000_write_phy_reg(hw,
- M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
- if (ret_val)
- return ret_val;
- } else {
- /* Configure Master and Slave downshift values */
- phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
- | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
- phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
- | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
- ret_val = e1000_write_phy_reg(hw,
- M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
- if (ret_val)
- return ret_val;
- }
- }
-
- /* SW Reset the PHY so all changes take effect */
- ret_val = e1000_phy_reset(hw);
- if (ret_val) {
- DEBUGOUT("Error Resetting the PHY\n");
- return ret_val;
- }
-
- return E1000_SUCCESS;
-}
-
-/********************************************************************
-* Setup auto-negotiation and flow control advertisements,
-* and then perform auto-negotiation.
-*
-* hw - Struct containing variables accessed by shared code
-*********************************************************************/
-static int32_t
-e1000_copper_link_autoneg(struct e1000_hw *hw)
-{
- int32_t ret_val;
- uint16_t phy_data;
-
- DEBUGFUNC();
-
- /* Perform some bounds checking on the hw->autoneg_advertised
- * parameter. If this variable is zero, then set it to the default.
- */
- hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
-
- /* If autoneg_advertised is zero, we assume it was not defaulted
- * by the calling code so we set to advertise full capability.
- */
- if (hw->autoneg_advertised == 0)
- hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
-
- /* IFE phy only supports 10/100 */
- if (hw->phy_type == e1000_phy_ife)
- hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
-
- DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
- ret_val = e1000_phy_setup_autoneg(hw);
- if (ret_val) {
- DEBUGOUT("Error Setting up Auto-Negotiation\n");
- return ret_val;
- }
- DEBUGOUT("Restarting Auto-Neg\n");
-
- /* Restart auto-negotiation by setting the Auto Neg Enable bit and
- * the Auto Neg Restart bit in the PHY control register.
- */
- ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
- if (ret_val)
- return ret_val;
-
- phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
- ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
- if (ret_val)
- return ret_val;
-
- /* Does the user want to wait for Auto-Neg to complete here, or
- * check at a later time (for example, callback routine).
- */
- /* If we do not wait for autonegtation to complete I
- * do not see a valid link status.
- * wait_autoneg_complete = 1 .
- */
- if (hw->wait_autoneg_complete) {
- ret_val = e1000_wait_autoneg(hw);
- if (ret_val) {
- DEBUGOUT("Error while waiting for autoneg"
- "to complete\n");
- return ret_val;
- }
- }
-
- hw->get_link_status = TRUE;
-
- return E1000_SUCCESS;
-}
-
-/******************************************************************************
-* Config the MAC and the PHY after link is up.
-* 1) Set up the MAC to the current PHY speed/duplex
-* if we are on 82543. If we
-* are on newer silicon, we only need to configure
-* collision distance in the Transmit Control Register.
-* 2) Set up flow control on the MAC to that established with
-* the link partner.
-* 3) Config DSP to improve Gigabit link quality for some PHY revisions.
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
-static int32_t
-e1000_copper_link_postconfig(struct e1000_hw *hw)
-{
- int32_t ret_val;
- DEBUGFUNC();
-
- if (hw->mac_type >= e1000_82544) {
- e1000_config_collision_dist(hw);
- } else {
- ret_val = e1000_config_mac_to_phy(hw);
- if (ret_val) {
- DEBUGOUT("Error configuring MAC to PHY settings\n");
- return ret_val;
- }
- }
- ret_val = e1000_config_fc_after_link_up(hw);
- if (ret_val) {
- DEBUGOUT("Error Configuring Flow Control\n");
- return ret_val;
- }
- return E1000_SUCCESS;
-}
-
-/******************************************************************************
-* Detects which PHY is present and setup the speed and duplex
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
-static int
-e1000_setup_copper_link(struct eth_device *nic)
-{
- struct e1000_hw *hw = nic->priv;
- int32_t ret_val;
- uint16_t i;
- uint16_t phy_data;
- uint16_t reg_data;
-
- DEBUGFUNC();
-
- switch (hw->mac_type) {
- case e1000_80003es2lan:
- case e1000_ich8lan:
- /* Set the mac to wait the maximum time between each
- * iteration and increase the max iterations when
- * polling the phy; this fixes erroneous timeouts at 10Mbps. */
- ret_val = e1000_write_kmrn_reg(hw,
- GG82563_REG(0x34, 4), 0xFFFF);
- if (ret_val)
- return ret_val;
- ret_val = e1000_read_kmrn_reg(hw,
- GG82563_REG(0x34, 9), ®_data);
- if (ret_val)
- return ret_val;
- reg_data |= 0x3F;
- ret_val = e1000_write_kmrn_reg(hw,
- GG82563_REG(0x34, 9), reg_data);
- if (ret_val)
- return ret_val;
- default:
- break;
- }
-
- /* Check if it is a valid PHY and set PHY mode if necessary. */
- ret_val = e1000_copper_link_preconfig(hw);
- if (ret_val)
- return ret_val;
- switch (hw->mac_type) {
- case e1000_80003es2lan:
- /* Kumeran registers are written-only */
- reg_data =
- E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
- reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
- ret_val = e1000_write_kmrn_reg(hw,
- E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
- if (ret_val)
- return ret_val;
- break;
- default:
- break;
- }
-
- if (hw->phy_type == e1000_phy_igp ||
- hw->phy_type == e1000_phy_igp_3 ||
- hw->phy_type == e1000_phy_igp_2) {
- ret_val = e1000_copper_link_igp_setup(hw);
- if (ret_val)
- return ret_val;
- } else if (hw->phy_type == e1000_phy_m88) {
- ret_val = e1000_copper_link_mgp_setup(hw);
- if (ret_val)
- return ret_val;
- } else if (hw->phy_type == e1000_phy_gg82563) {
- ret_val = e1000_copper_link_ggp_setup(hw);
- if (ret_val)
- return ret_val;
- }
-
- /* always auto */
- /* Setup autoneg and flow control advertisement
- * and perform autonegotiation */
- ret_val = e1000_copper_link_autoneg(hw);
- if (ret_val)
- return ret_val;
-
- /* Check link status. Wait up to 100 microseconds for link to become
- * valid.
- */
- for (i = 0; i < 10; i++) {
- ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
- if (ret_val)
- return ret_val;
- ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
- if (ret_val)
- return ret_val;
-
- if (phy_data & MII_SR_LINK_STATUS) {
- /* Config the MAC and PHY after link is up */
- ret_val = e1000_copper_link_postconfig(hw);
- if (ret_val)
- return ret_val;
-
- DEBUGOUT("Valid link established!!!\n");
- return E1000_SUCCESS;
- }
- udelay(10);
- }
-
- DEBUGOUT("Unable to establish link!!!\n");
- return E1000_SUCCESS;
-}
-
-/******************************************************************************
-* Configures PHY autoneg and flow control advertisement settings
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
-int32_t
-e1000_phy_setup_autoneg(struct e1000_hw *hw)
-{
- int32_t ret_val;
- uint16_t mii_autoneg_adv_reg;
- uint16_t mii_1000t_ctrl_reg;
-
- DEBUGFUNC();
-
- /* Read the MII Auto-Neg Advertisement Register (Address 4). */
- ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
- if (ret_val)
- return ret_val;
-
- if (hw->phy_type != e1000_phy_ife) {
- /* Read the MII 1000Base-T Control Register (Address 9). */
- ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
- &mii_1000t_ctrl_reg);
- if (ret_val)
- return ret_val;
- } else
- mii_1000t_ctrl_reg = 0;
-
- /* Need to parse both autoneg_advertised and fc and set up
- * the appropriate PHY registers. First we will parse for
- * autoneg_advertised software override. Since we can advertise
- * a plethora of combinations, we need to check each bit
- * individually.
- */
-
- /* First we clear all the 10/100 mb speed bits in the Auto-Neg
- * Advertisement Register (Address 4) and the 1000 mb speed bits in
- * the 1000Base-T Control Register (Address 9).
- */
- mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
- mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
-
- DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
-
- /* Do we want to advertise 10 Mb Half Duplex? */
- if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
- DEBUGOUT("Advertise 10mb Half duplex\n");
- mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
- }
-
- /* Do we want to advertise 10 Mb Full Duplex? */
- if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
- DEBUGOUT("Advertise 10mb Full duplex\n");
- mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
- }
-
- /* Do we want to advertise 100 Mb Half Duplex? */
- if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
- DEBUGOUT("Advertise 100mb Half duplex\n");
- mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
- }
-
- /* Do we want to advertise 100 Mb Full Duplex? */
- if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
- DEBUGOUT("Advertise 100mb Full duplex\n");
- mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
- }
-
- /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
- if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
- DEBUGOUT
- ("Advertise 1000mb Half duplex requested, request denied!\n");
- }
-
- /* Do we want to advertise 1000 Mb Full Duplex? */
- if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
- DEBUGOUT("Advertise 1000mb Full duplex\n");
- mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
- }
-
- /* Check for a software override of the flow control settings, and
- * setup the PHY advertisement registers accordingly. If
- * auto-negotiation is enabled, then software will have to set the
- * "PAUSE" bits to the correct value in the Auto-Negotiation
- * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
- *
- * The possible values of the "fc" parameter are:
- * 0: Flow control is completely disabled
- * 1: Rx flow control is enabled (we can receive pause frames
- * but not send pause frames).
- * 2: Tx flow control is enabled (we can send pause frames
- * but we do not support receiving pause frames).
- * 3: Both Rx and TX flow control (symmetric) are enabled.
- * other: No software override. The flow control configuration
- * in the EEPROM is used.
- */
- switch (hw->fc) {
- case e1000_fc_none: /* 0 */
- /* Flow control (RX & TX) is completely disabled by a
- * software over-ride.
- */
- mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
- break;
- case e1000_fc_rx_pause: /* 1 */
- /* RX Flow control is enabled, and TX Flow control is
- * disabled, by a software over-ride.
- */
- /* Since there really isn't a way to advertise that we are
- * capable of RX Pause ONLY, we will advertise that we
- * support both symmetric and asymmetric RX PAUSE. Later
- * (in e1000_config_fc_after_link_up) we will disable the
- *hw's ability to send PAUSE frames.
- */
- mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
- break;
- case e1000_fc_tx_pause: /* 2 */
- /* TX Flow control is enabled, and RX Flow control is
- * disabled, by a software over-ride.
- */
- mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
- mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
- break;
- case e1000_fc_full: /* 3 */
- /* Flow control (both RX and TX) is enabled by a software
- * over-ride.
- */
- mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
- break;
- default:
- DEBUGOUT("Flow control param set incorrectly\n");
- return -E1000_ERR_CONFIG;
- }
-
- ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
- if (ret_val)
- return ret_val;
-
- DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
-
- if (hw->phy_type != e1000_phy_ife) {
- ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
- mii_1000t_ctrl_reg);
- if (ret_val)
- return ret_val;
- }
-
- return E1000_SUCCESS;
-}
-
-/******************************************************************************
-* Sets the collision distance in the Transmit Control register
-*
-* hw - Struct containing variables accessed by shared code
-*
-* Link should have been established previously. Reads the speed and duplex
-* information from the Device Status register.
-******************************************************************************/
-static void
-e1000_config_collision_dist(struct e1000_hw *hw)
-{
- uint32_t tctl, coll_dist;
-
- DEBUGFUNC();
-
- if (hw->mac_type < e1000_82543)
- coll_dist = E1000_COLLISION_DISTANCE_82542;
- else
- coll_dist = E1000_COLLISION_DISTANCE;
-
- tctl = E1000_READ_REG(hw, TCTL);
-
- tctl &= ~E1000_TCTL_COLD;
- tctl |= coll_dist << E1000_COLD_SHIFT;
-
- E1000_WRITE_REG(hw, TCTL, tctl);
- E1000_WRITE_FLUSH(hw);
-}
-
-/******************************************************************************
-* Sets MAC speed and duplex settings to reflect the those in the PHY
-*
-* hw - Struct containing variables accessed by shared code
-* mii_reg - data to write to the MII control register
-*
-* The contents of the PHY register containing the needed information need to
-* be passed in.
-******************************************************************************/
-static int
-e1000_config_mac_to_phy(struct e1000_hw *hw)
-{
- uint32_t ctrl;
- uint16_t phy_data;
-
- DEBUGFUNC();
-
- /* Read the Device Control Register and set the bits to Force Speed
- * and Duplex.
- */
- ctrl = E1000_READ_REG(hw, CTRL);
- ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
- ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
-
- /* Set up duplex in the Device Control and Transmit Control
- * registers depending on negotiated values.
- */
- if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
- if (phy_data & M88E1000_PSSR_DPLX)
- ctrl |= E1000_CTRL_FD;
- else
- ctrl &= ~E1000_CTRL_FD;
-
- e1000_config_collision_dist(hw);
-
- /* Set up speed in the Device Control register depending on
- * negotiated values.
- */
- if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
- ctrl |= E1000_CTRL_SPD_1000;
- else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
- ctrl |= E1000_CTRL_SPD_100;
- /* Write the configured values back to the Device Control Reg. */
- E1000_WRITE_REG(hw, CTRL, ctrl);
- return 0;
-}
-
-/******************************************************************************
- * Forces the MAC's flow control settings.
- *
- * hw - Struct containing variables accessed by shared code
- *
- * Sets the TFCE and RFCE bits in the device control register to reflect
- * the adapter settings. TFCE and RFCE need to be explicitly set by
- * software when a Copper PHY is used because autonegotiation is managed
- * by the PHY rather than the MAC. Software must also configure these
- * bits when link is forced on a fiber connection.
- *****************************************************************************/
-static int
-e1000_force_mac_fc(struct e1000_hw *hw)
-{
- uint32_t ctrl;
-
- DEBUGFUNC();
-
- /* Get the current configuration of the Device Control Register */
- ctrl = E1000_READ_REG(hw, CTRL);
-
- /* Because we didn't get link via the internal auto-negotiation
- * mechanism (we either forced link or we got link via PHY
- * auto-neg), we have to manually enable/disable transmit an
- * receive flow control.
- *
- * The "Case" statement below enables/disable flow control
- * according to the "hw->fc" parameter.
- *
- * The possible values of the "fc" parameter are:
- * 0: Flow control is completely disabled
- * 1: Rx flow control is enabled (we can receive pause
- * frames but not send pause frames).
- * 2: Tx flow control is enabled (we can send pause frames
- * frames but we do not receive pause frames).
- * 3: Both Rx and TX flow control (symmetric) is enabled.
- * other: No other values should be possible at this point.
- */
-
- switch (hw->fc) {
- case e1000_fc_none:
- ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
- break;
- case e1000_fc_rx_pause:
- ctrl &= (~E1000_CTRL_TFCE);
- ctrl |= E1000_CTRL_RFCE;
- break;
- case e1000_fc_tx_pause:
- ctrl &= (~E1000_CTRL_RFCE);
- ctrl |= E1000_CTRL_TFCE;
- break;
- case e1000_fc_full:
- ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
- break;
- default:
- DEBUGOUT("Flow control param set incorrectly\n");
- return -E1000_ERR_CONFIG;
- }
-
- /* Disable TX Flow Control for 82542 (rev 2.0) */
- if (hw->mac_type == e1000_82542_rev2_0)
- ctrl &= (~E1000_CTRL_TFCE);
-
- E1000_WRITE_REG(hw, CTRL, ctrl);
- return 0;
-}
-
-/******************************************************************************
- * Configures flow control settings after link is established
- *
- * hw - Struct containing variables accessed by shared code
- *
- * Should be called immediately after a valid link has been established.
- * Forces MAC flow control settings if link was forced. When in MII/GMII mode
- * and autonegotiation is enabled, the MAC flow control settings will be set
- * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
- * and RFCE bits will be automaticaly set to the negotiated flow control mode.
- *****************************************************************************/
-static int32_t
-e1000_config_fc_after_link_up(struct e1000_hw *hw)
-{
- int32_t ret_val;
- uint16_t mii_status_reg;
- uint16_t mii_nway_adv_reg;
- uint16_t mii_nway_lp_ability_reg;
- uint16_t speed;
- uint16_t duplex;
-
- DEBUGFUNC();
-
- /* Check for the case where we have fiber media and auto-neg failed
- * so we had to force link. In this case, we need to force the
- * configuration of the MAC to match the "fc" parameter.
- */
- if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
- || ((hw->media_type == e1000_media_type_internal_serdes)
- && (hw->autoneg_failed))
- || ((hw->media_type == e1000_media_type_copper)
- && (!hw->autoneg))) {
- ret_val = e1000_force_mac_fc(hw);
- if (ret_val < 0) {
- DEBUGOUT("Error forcing flow control settings\n");
- return ret_val;
- }
- }
-
- /* Check for the case where we have copper media and auto-neg is
- * enabled. In this case, we need to check and see if Auto-Neg
- * has completed, and if so, how the PHY and link partner has
- * flow control configured.
- */
- if (hw->media_type == e1000_media_type_copper) {
- /* Read the MII Status Register and check to see if AutoNeg
- * has completed. We read this twice because this reg has
- * some "sticky" (latched) bits.
- */
- if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
- DEBUGOUT("PHY Read Error \n");
- return -E1000_ERR_PHY;
- }
- if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
- DEBUGOUT("PHY Read Error \n");
- return -E1000_ERR_PHY;
- }
-
- if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
- /* The AutoNeg process has completed, so we now need to
- * read both the Auto Negotiation Advertisement Register
- * (Address 4) and the Auto_Negotiation Base Page Ability
- * Register (Address 5) to determine how flow control was
- * negotiated.
- */
- if (e1000_read_phy_reg
- (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
- if (e1000_read_phy_reg
- (hw, PHY_LP_ABILITY,
- &mii_nway_lp_ability_reg) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
-
- /* Two bits in the Auto Negotiation Advertisement Register
- * (Address 4) and two bits in the Auto Negotiation Base
- * Page Ability Register (Address 5) determine flow control
- * for both the PHY and the link partner. The following
- * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
- * 1999, describes these PAUSE resolution bits and how flow
- * control is determined based upon these settings.
- * NOTE: DC = Don't Care
- *
- * LOCAL DEVICE | LINK PARTNER
- * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
- *-------|---------|-------|---------|--------------------
- * 0 | 0 | DC | DC | e1000_fc_none
- * 0 | 1 | 0 | DC | e1000_fc_none
- * 0 | 1 | 1 | 0 | e1000_fc_none
- * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
- * 1 | 0 | 0 | DC | e1000_fc_none
- * 1 | DC | 1 | DC | e1000_fc_full
- * 1 | 1 | 0 | 0 | e1000_fc_none
- * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
- *
- */
- /* Are both PAUSE bits set to 1? If so, this implies
- * Symmetric Flow Control is enabled at both ends. The
- * ASM_DIR bits are irrelevant per the spec.
- *
- * For Symmetric Flow Control:
- *
- * LOCAL DEVICE | LINK PARTNER
- * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
- *-------|---------|-------|---------|--------------------
- * 1 | DC | 1 | DC | e1000_fc_full
- *
- */
- if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
- (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
- /* Now we need to check if the user selected RX ONLY
- * of pause frames. In this case, we had to advertise
- * FULL flow control because we could not advertise RX
- * ONLY. Hence, we must now check to see if we need to
- * turn OFF the TRANSMISSION of PAUSE frames.
- */
- if (hw->original_fc == e1000_fc_full) {
- hw->fc = e1000_fc_full;
- DEBUGOUT("Flow Control = FULL.\r\n");
- } else {
- hw->fc = e1000_fc_rx_pause;
- DEBUGOUT
- ("Flow Control = RX PAUSE frames only.\r\n");
- }
- }
- /* For receiving PAUSE frames ONLY.
- *
- * LOCAL DEVICE | LINK PARTNER
- * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
- *-------|---------|-------|---------|--------------------
- * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
- *
- */
- else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
- (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
- (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
- (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
- {
- hw->fc = e1000_fc_tx_pause;
- DEBUGOUT
- ("Flow Control = TX PAUSE frames only.\r\n");
- }
- /* For transmitting PAUSE frames ONLY.
- *
- * LOCAL DEVICE | LINK PARTNER
- * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
- *-------|---------|-------|---------|--------------------
- * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
- *
- */
- else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
- (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
- !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
- (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
- {
- hw->fc = e1000_fc_rx_pause;
- DEBUGOUT
- ("Flow Control = RX PAUSE frames only.\r\n");
- }
- /* Per the IEEE spec, at this point flow control should be
- * disabled. However, we want to consider that we could
- * be connected to a legacy switch that doesn't advertise
- * desired flow control, but can be forced on the link
- * partner. So if we advertised no flow control, that is
- * what we will resolve to. If we advertised some kind of
- * receive capability (Rx Pause Only or Full Flow Control)
- * and the link partner advertised none, we will configure
- * ourselves to enable Rx Flow Control only. We can do
- * this safely for two reasons: If the link partner really
- * didn't want flow control enabled, and we enable Rx, no
- * harm done since we won't be receiving any PAUSE frames
- * anyway. If the intent on the link partner was to have
- * flow control enabled, then by us enabling RX only, we
- * can at least receive pause frames and process them.
- * This is a good idea because in most cases, since we are
- * predominantly a server NIC, more times than not we will
- * be asked to delay transmission of packets than asking
- * our link partner to pause transmission of frames.
- */
- else if (hw->original_fc == e1000_fc_none ||
- hw->original_fc == e1000_fc_tx_pause) {
- hw->fc = e1000_fc_none;
- DEBUGOUT("Flow Control = NONE.\r\n");
- } else {
- hw->fc = e1000_fc_rx_pause;
- DEBUGOUT
- ("Flow Control = RX PAUSE frames only.\r\n");
- }
-
- /* Now we need to do one last check... If we auto-
- * negotiated to HALF DUPLEX, flow control should not be
- * enabled per IEEE 802.3 spec.
- */
- e1000_get_speed_and_duplex(hw, &speed, &duplex);
-
- if (duplex == HALF_DUPLEX)
- hw->fc = e1000_fc_none;
-
- /* Now we call a subroutine to actually force the MAC
- * controller to use the correct flow control settings.
- */
- ret_val = e1000_force_mac_fc(hw);
- if (ret_val < 0) {
- DEBUGOUT
- ("Error forcing flow control settings\n");
- return ret_val;
- }
- } else {
- DEBUGOUT
- ("Copper PHY and Auto Neg has not completed.\r\n");
- }
- }
- return E1000_SUCCESS;
-}
-
-/******************************************************************************
- * Checks to see if the link status of the hardware has changed.
- *
- * hw - Struct containing variables accessed by shared code
- *
- * Called by any function that needs to check the link status of the adapter.
- *****************************************************************************/
-static int
-e1000_check_for_link(struct eth_device *nic)
-{
- struct e1000_hw *hw = nic->priv;
- uint32_t rxcw;
- uint32_t ctrl;
- uint32_t status;
- uint32_t rctl;
- uint32_t signal;
- int32_t ret_val;
- uint16_t phy_data;
- uint16_t lp_capability;
-
- DEBUGFUNC();
-
- /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
- * set when the optics detect a signal. On older adapters, it will be
- * cleared when there is a signal
- */
- ctrl = E1000_READ_REG(hw, CTRL);
- if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
- signal = E1000_CTRL_SWDPIN1;
- else
- signal = 0;
-
- status = E1000_READ_REG(hw, STATUS);
- rxcw = E1000_READ_REG(hw, RXCW);
- DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
-
- /* If we have a copper PHY then we only want to go out to the PHY
- * registers to see if Auto-Neg has completed and/or if our link
- * status has changed. The get_link_status flag will be set if we
- * receive a Link Status Change interrupt or we have Rx Sequence
- * Errors.
- */
- if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
- /* First we want to see if the MII Status Register reports
- * link. If so, then we want to get the current speed/duplex
- * of the PHY.
- * Read the register twice since the link bit is sticky.
- */
- if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
- if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
-
- if (phy_data & MII_SR_LINK_STATUS) {
- hw->get_link_status = FALSE;
- } else {
- /* No link detected */
- return -E1000_ERR_NOLINK;
- }
-
- /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
- * have Si on board that is 82544 or newer, Auto
- * Speed Detection takes care of MAC speed/duplex
- * configuration. So we only need to configure Collision
- * Distance in the MAC. Otherwise, we need to force
- * speed/duplex on the MAC to the current PHY speed/duplex
- * settings.
- */
- if (hw->mac_type >= e1000_82544)
- e1000_config_collision_dist(hw);
- else {
- ret_val = e1000_config_mac_to_phy(hw);
- if (ret_val < 0) {
- DEBUGOUT
- ("Error configuring MAC to PHY settings\n");
- return ret_val;
- }
- }
-
- /* Configure Flow Control now that Auto-Neg has completed. First, we
- * need to restore the desired flow control settings because we may
- * have had to re-autoneg with a different link partner.
- */
- ret_val = e1000_config_fc_after_link_up(hw);
- if (ret_val < 0) {
- DEBUGOUT("Error configuring flow control\n");
- return ret_val;
- }
-
- /* At this point we know that we are on copper and we have
- * auto-negotiated link. These are conditions for checking the link
- * parter capability register. We use the link partner capability to
- * determine if TBI Compatibility needs to be turned on or off. If
- * the link partner advertises any speed in addition to Gigabit, then
- * we assume that they are GMII-based, and TBI compatibility is not
- * needed. If no other speeds are advertised, we assume the link
- * partner is TBI-based, and we turn on TBI Compatibility.
- */
- if (hw->tbi_compatibility_en) {
- if (e1000_read_phy_reg
- (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
- if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
- NWAY_LPAR_10T_FD_CAPS |
- NWAY_LPAR_100TX_HD_CAPS |
- NWAY_LPAR_100TX_FD_CAPS |
- NWAY_LPAR_100T4_CAPS)) {
- /* If our link partner advertises anything in addition to
- * gigabit, we do not need to enable TBI compatibility.
- */
- if (hw->tbi_compatibility_on) {
- /* If we previously were in the mode, turn it off. */
- rctl = E1000_READ_REG(hw, RCTL);
- rctl &= ~E1000_RCTL_SBP;
- E1000_WRITE_REG(hw, RCTL, rctl);
- hw->tbi_compatibility_on = FALSE;
- }
- } else {
- /* If TBI compatibility is was previously off, turn it on. For
- * compatibility with a TBI link partner, we will store bad
- * packets. Some frames have an additional byte on the end and
- * will look like CRC errors to to the hardware.
- */
- if (!hw->tbi_compatibility_on) {
- hw->tbi_compatibility_on = TRUE;
- rctl = E1000_READ_REG(hw, RCTL);
- rctl |= E1000_RCTL_SBP;
- E1000_WRITE_REG(hw, RCTL, rctl);
- }
- }
- }
- }
- /* If we don't have link (auto-negotiation failed or link partner cannot
- * auto-negotiate), the cable is plugged in (we have signal), and our
- * link partner is not trying to auto-negotiate with us (we are receiving
- * idles or data), we need to force link up. We also need to give
- * auto-negotiation time to complete, in case the cable was just plugged
- * in. The autoneg_failed flag does this.
- */
- else if ((hw->media_type == e1000_media_type_fiber) &&
- (!(status & E1000_STATUS_LU)) &&
- ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
- (!(rxcw & E1000_RXCW_C))) {
- if (hw->autoneg_failed == 0) {
- hw->autoneg_failed = 1;
- return 0;
- }
- DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
-
- /* Disable auto-negotiation in the TXCW register */
- E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
-
- /* Force link-up and also force full-duplex. */
- ctrl = E1000_READ_REG(hw, CTRL);
- ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
- E1000_WRITE_REG(hw, CTRL, ctrl);
-
- /* Configure Flow Control after forcing link up. */
- ret_val = e1000_config_fc_after_link_up(hw);
- if (ret_val < 0) {
- DEBUGOUT("Error configuring flow control\n");
- return ret_val;
- }
- }
- /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
- * auto-negotiation in the TXCW register and disable forced link in the
- * Device Control register in an attempt to auto-negotiate with our link
- * partner.
- */
- else if ((hw->media_type == e1000_media_type_fiber) &&
- (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
- DEBUGOUT
- ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
- E1000_WRITE_REG(hw, TXCW, hw->txcw);
- E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
- }
- return 0;
-}
-
-/******************************************************************************
-* Configure the MAC-to-PHY interface for 10/100Mbps
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
-static int32_t
-e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
-{
- int32_t ret_val = E1000_SUCCESS;
- uint32_t tipg;
- uint16_t reg_data;
-
- DEBUGFUNC();
-
- reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
- ret_val = e1000_write_kmrn_reg(hw,
- E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
- if (ret_val)
- return ret_val;
-
- /* Configure Transmit Inter-Packet Gap */
- tipg = E1000_READ_REG(hw, TIPG);
- tipg &= ~E1000_TIPG_IPGT_MASK;
- tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
- E1000_WRITE_REG(hw, TIPG, tipg);
-
- ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
-
- if (ret_val)
- return ret_val;
-
- if (duplex == HALF_DUPLEX)
- reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
- else
- reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
-
- ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
-
- return ret_val;
-}
-
-static int32_t
-e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
-{
- int32_t ret_val = E1000_SUCCESS;
- uint16_t reg_data;
- uint32_t tipg;
-
- DEBUGFUNC();
-
- reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
- ret_val = e1000_write_kmrn_reg(hw,
- E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
- if (ret_val)
- return ret_val;
-
- /* Configure Transmit Inter-Packet Gap */
- tipg = E1000_READ_REG(hw, TIPG);
- tipg &= ~E1000_TIPG_IPGT_MASK;
- tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
- E1000_WRITE_REG(hw, TIPG, tipg);
-
- ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
-
- if (ret_val)
- return ret_val;
-
- reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
- ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
-
- return ret_val;
-}
-
-/******************************************************************************
- * Detects the current speed and duplex settings of the hardware.
- *
- * hw - Struct containing variables accessed by shared code
- * speed - Speed of the connection
- * duplex - Duplex setting of the connection
- *****************************************************************************/
-static int
-e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
- uint16_t *duplex)
-{
- uint32_t status;
- int32_t ret_val;
- uint16_t phy_data;
-
- DEBUGFUNC();
-
- if (hw->mac_type >= e1000_82543) {
- status = E1000_READ_REG(hw, STATUS);
- if (status & E1000_STATUS_SPEED_1000) {
- *speed = SPEED_1000;
- DEBUGOUT("1000 Mbs, ");
- } else if (status & E1000_STATUS_SPEED_100) {
- *speed = SPEED_100;
- DEBUGOUT("100 Mbs, ");
- } else {
- *speed = SPEED_10;
- DEBUGOUT("10 Mbs, ");
- }
-
- if (status & E1000_STATUS_FD) {
- *duplex = FULL_DUPLEX;
- DEBUGOUT("Full Duplex\r\n");
- } else {
- *duplex = HALF_DUPLEX;
- DEBUGOUT(" Half Duplex\r\n");
- }
- } else {
- DEBUGOUT("1000 Mbs, Full Duplex\r\n");
- *speed = SPEED_1000;
- *duplex = FULL_DUPLEX;
- }
-
- /* IGP01 PHY may advertise full duplex operation after speed downgrade
- * even if it is operating at half duplex. Here we set the duplex
- * settings to match the duplex in the link partner's capabilities.
- */
- if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
- ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
- if (ret_val)
- return ret_val;
-
- if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
- *duplex = HALF_DUPLEX;
- else {
- ret_val = e1000_read_phy_reg(hw,
- PHY_LP_ABILITY, &phy_data);
- if (ret_val)
- return ret_val;
- if ((*speed == SPEED_100 &&
- !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
- || (*speed == SPEED_10
- && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
- *duplex = HALF_DUPLEX;
- }
- }
-
- if ((hw->mac_type == e1000_80003es2lan) &&
- (hw->media_type == e1000_media_type_copper)) {
- if (*speed == SPEED_1000)
- ret_val = e1000_configure_kmrn_for_1000(hw);
- else
- ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
- if (ret_val)
- return ret_val;
- }
- return E1000_SUCCESS;
-}
-
-/******************************************************************************
-* Blocks until autoneg completes or times out (~4.5 seconds)
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
-static int
-e1000_wait_autoneg(struct e1000_hw *hw)
-{
- uint16_t i;
- uint16_t phy_data;
-
- DEBUGFUNC();
- DEBUGOUT("Waiting for Auto-Neg to complete.\n");
-
- /* We will wait for autoneg to complete or 4.5 seconds to expire. */
- for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
- /* Read the MII Status Register and wait for Auto-Neg
- * Complete bit to be set.
- */
- if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
- if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
- DEBUGOUT("PHY Read Error\n");
- return -E1000_ERR_PHY;
- }
- if (phy_data & MII_SR_AUTONEG_COMPLETE) {
- DEBUGOUT("Auto-Neg complete.\n");
- return 0;
- }
- mdelay(100);
- }
- DEBUGOUT("Auto-Neg timedout.\n");
- return -E1000_ERR_TIMEOUT;
-}
-
-/******************************************************************************
-* Raises the Management Data Clock
-*
-* hw - Struct containing variables accessed by shared code
-* ctrl - Device control register's current value
-******************************************************************************/
-static void
-e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
-{
- /* Raise the clock input to the Management Data Clock (by setting the MDC
- * bit), and then delay 2 microseconds.
- */
- E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
- E1000_WRITE_FLUSH(hw);
- udelay(2);
-}
-
-/******************************************************************************
-* Lowers the Management Data Clock
-*
-* hw - Struct containing variables accessed by shared code
-* ctrl - Device control register's current value
-******************************************************************************/
-static void
-e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
-{
- /* Lower the clock input to the Management Data Clock (by clearing the MDC
- * bit), and then delay 2 microseconds.
- */
- E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
- E1000_WRITE_FLUSH(hw);
- udelay(2);
-}
-
-/******************************************************************************
-* Shifts data bits out to the PHY
-*
-* hw - Struct containing variables accessed by shared code
-* data - Data to send out to the PHY
-* count - Number of bits to shift out
-*
-* Bits are shifted out in MSB to LSB order.
-******************************************************************************/
-static void
-e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
-{
- uint32_t ctrl;
- uint32_t mask;
-
- /* We need to shift "count" number of bits out to the PHY. So, the value
- * in the "data" parameter will be shifted out to the PHY one bit at a
- * time. In order to do this, "data" must be broken down into bits.
- */
- mask = 0x01;
- mask <<= (count - 1);
-
- ctrl = E1000_READ_REG(hw, CTRL);
-
- /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
- ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
-
- while (mask) {
- /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
- * then raising and lowering the Management Data Clock. A "0" is
- * shifted out to the PHY by setting the MDIO bit to "0" and then
- * raising and lowering the clock.
- */
- if (data & mask)
- ctrl |= E1000_CTRL_MDIO;
- else
- ctrl &= ~E1000_CTRL_MDIO;
-
- E1000_WRITE_REG(hw, CTRL, ctrl);
- E1000_WRITE_FLUSH(hw);
-
- udelay(2);
-
- e1000_raise_mdi_clk(hw, &ctrl);
- e1000_lower_mdi_clk(hw, &ctrl);
-
- mask = mask >> 1;
- }
-}
-
-/******************************************************************************
-* Shifts data bits in from the PHY
-*
-* hw - Struct containing variables accessed by shared code
-*
-* Bits are shifted in in MSB to LSB order.
-******************************************************************************/
-static uint16_t
-e1000_shift_in_mdi_bits(struct e1000_hw *hw)
-{
- uint32_t ctrl;
- uint16_t data = 0;
- uint8_t i;
-
- /* In order to read a register from the PHY, we need to shift in a total
- * of 18 bits from the PHY. The first two bit (turnaround) times are used
- * to avoid contention on the MDIO pin when a read operation is performed.
- * These two bits are ignored by us and thrown away. Bits are "shifted in"
- * by raising the input to the Management Data Clock (setting the MDC bit),
- * and then reading the value of the MDIO bit.
- */
- ctrl = E1000_READ_REG(hw, CTRL);
-
- /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
- ctrl &= ~E1000_CTRL_MDIO_DIR;
- ctrl &= ~E1000_CTRL_MDIO;
-
- E1000_WRITE_REG(hw, CTRL, ctrl);
- E1000_WRITE_FLUSH(hw);
-
- /* Raise and Lower the clock before reading in the data. This accounts for
- * the turnaround bits. The first clock occurred when we clocked out the
- * last bit of the Register Address.
- */
- e1000_raise_mdi_clk(hw, &ctrl);
- e1000_lower_mdi_clk(hw, &ctrl);
-
- for (data = 0, i = 0; i < 16; i++) {
- data = data << 1;
- e1000_raise_mdi_clk(hw, &ctrl);
- ctrl = E1000_READ_REG(hw, CTRL);
- /* Check to see if we shifted in a "1". */
- if (ctrl & E1000_CTRL_MDIO)
- data |= 1;
- e1000_lower_mdi_clk(hw, &ctrl);
- }
-
- e1000_raise_mdi_clk(hw, &ctrl);
- e1000_lower_mdi_clk(hw, &ctrl);
-
- return data;
-}
-
-/*****************************************************************************
-* Reads the value from a PHY register
-*
-* hw - Struct containing variables accessed by shared code
-* reg_addr - address of the PHY register to read
-******************************************************************************/
-static int
-e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
-{
- uint32_t i;
- uint32_t mdic = 0;
- const uint32_t phy_addr = 1;
-
- if (reg_addr > MAX_PHY_REG_ADDRESS) {
- DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
- return -E1000_ERR_PARAM;
- }
-
- if (hw->mac_type > e1000_82543) {
- /* Set up Op-code, Phy Address, and register address in the MDI
- * Control register. The MAC will take care of interfacing with the
- * PHY to retrieve the desired data.
- */
- mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
- (phy_addr << E1000_MDIC_PHY_SHIFT) |
- (E1000_MDIC_OP_READ));
-
- E1000_WRITE_REG(hw, MDIC, mdic);
-
- /* Poll the ready bit to see if the MDI read completed */
- for (i = 0; i < 64; i++) {
- udelay(10);
- mdic = E1000_READ_REG(hw, MDIC);
- if (mdic & E1000_MDIC_READY)
- break;
- }
- if (!(mdic & E1000_MDIC_READY)) {
- DEBUGOUT("MDI Read did not complete\n");
- return -E1000_ERR_PHY;
- }
- if (mdic & E1000_MDIC_ERROR) {
- DEBUGOUT("MDI Error\n");
- return -E1000_ERR_PHY;
- }
- *phy_data = (uint16_t) mdic;
- } else {
- /* We must first send a preamble through the MDIO pin to signal the
- * beginning of an MII instruction. This is done by sending 32
- * consecutive "1" bits.
- */
- e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
-
- /* Now combine the next few fields that are required for a read
- * operation. We use this method instead of calling the
- * e1000_shift_out_mdi_bits routine five different times. The format of
- * a MII read instruction consists of a shift out of 14 bits and is
- * defined as follows:
- * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
- * followed by a shift in of 18 bits. This first two bits shifted in
- * are TurnAround bits used to avoid contention on the MDIO pin when a
- * READ operation is performed. These two bits are thrown away
- * followed by a shift in of 16 bits which contains the desired data.
- */
- mdic = ((reg_addr) | (phy_addr << 5) |
- (PHY_OP_READ << 10) | (PHY_SOF << 12));
-
- e1000_shift_out_mdi_bits(hw, mdic, 14);
-
- /* Now that we've shifted out the read command to the MII, we need to
- * "shift in" the 16-bit value (18 total bits) of the requested PHY
- * register address.
- */
- *phy_data = e1000_shift_in_mdi_bits(hw);
- }
- return 0;
-}
-
-/******************************************************************************
-* Writes a value to a PHY register
-*
-* hw - Struct containing variables accessed by shared code
-* reg_addr - address of the PHY register to write
-* data - data to write to the PHY
-******************************************************************************/
-static int
-e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
-{
- uint32_t i;
- uint32_t mdic = 0;
- const uint32_t phy_addr = 1;
-
- if (reg_addr > MAX_PHY_REG_ADDRESS) {
- DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
- return -E1000_ERR_PARAM;
- }
-
- if (hw->mac_type > e1000_82543) {
- /* Set up Op-code, Phy Address, register address, and data intended
- * for the PHY register in the MDI Control register. The MAC will take
- * care of interfacing with the PHY to send the desired data.
- */
- mdic = (((uint32_t) phy_data) |
- (reg_addr << E1000_MDIC_REG_SHIFT) |
- (phy_addr << E1000_MDIC_PHY_SHIFT) |
- (E1000_MDIC_OP_WRITE));
-
- E1000_WRITE_REG(hw, MDIC, mdic);
-
- /* Poll the ready bit to see if the MDI read completed */
- for (i = 0; i < 64; i++) {
- udelay(10);
- mdic = E1000_READ_REG(hw, MDIC);
- if (mdic & E1000_MDIC_READY)
- break;
- }
- if (!(mdic & E1000_MDIC_READY)) {
- DEBUGOUT("MDI Write did not complete\n");
- return -E1000_ERR_PHY;
- }
- } else {
- /* We'll need to use the SW defined pins to shift the write command
- * out to the PHY. We first send a preamble to the PHY to signal the
- * beginning of the MII instruction. This is done by sending 32
- * consecutive "1" bits.
- */
- e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
-
- /* Now combine the remaining required fields that will indicate a
- * write operation. We use this method instead of calling the
- * e1000_shift_out_mdi_bits routine for each field in the command. The
- * format of a MII write instruction is as follows:
- * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
- */
- mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
- (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
- mdic <<= 16;
- mdic |= (uint32_t) phy_data;
-
- e1000_shift_out_mdi_bits(hw, mdic, 32);
- }
- return 0;
-}
-
-/******************************************************************************
- * Checks if PHY reset is blocked due to SOL/IDER session, for example.
- * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
- * the caller to figure out how to deal with it.
- *
- * hw - Struct containing variables accessed by shared code
- *
- * returns: - E1000_BLK_PHY_RESET
- * E1000_SUCCESS
- *
- *****************************************************************************/
-int32_t
-e1000_check_phy_reset_block(struct e1000_hw *hw)
-{
- uint32_t manc = 0;
- uint32_t fwsm = 0;
-
- if (hw->mac_type == e1000_ich8lan) {
- fwsm = E1000_READ_REG(hw, FWSM);
- return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
- : E1000_BLK_PHY_RESET;
- }
-
- if (hw->mac_type > e1000_82547_rev_2)
- manc = E1000_READ_REG(hw, MANC);
- return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
- E1000_BLK_PHY_RESET : E1000_SUCCESS;
-}
-
-/***************************************************************************
- * Checks if the PHY configuration is done
- *
- * hw: Struct containing variables accessed by shared code
- *
- * returns: - E1000_ERR_RESET if fail to reset MAC
- * E1000_SUCCESS at any other case.
- *
- ***************************************************************************/
-static int32_t
-e1000_get_phy_cfg_done(struct e1000_hw *hw)
-{
- int32_t timeout = PHY_CFG_TIMEOUT;
- uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
-
- DEBUGFUNC();
-
- switch (hw->mac_type) {
- default:
- mdelay(10);
- break;
- case e1000_80003es2lan:
- /* Separate *_CFG_DONE_* bit for each port */
- if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
- cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
- /* Fall Through */
- case e1000_82571:
- case e1000_82572:
- while (timeout) {
- if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
- break;
- else
- mdelay(1);
- timeout--;
- }
- if (!timeout) {
- DEBUGOUT("MNG configuration cycle has not "
- "completed.\n");
- return -E1000_ERR_RESET;
- }
- break;
- }
-
- return E1000_SUCCESS;
-}
-
-/******************************************************************************
-* Returns the PHY to the power-on reset state
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
-int32_t
-e1000_phy_hw_reset(struct e1000_hw *hw)
-{
- uint32_t ctrl, ctrl_ext;
- uint32_t led_ctrl;
- int32_t ret_val;
- uint16_t swfw;
-
- DEBUGFUNC();
-
- /* In the case of the phy reset being blocked, it's not an error, we
- * simply return success without performing the reset. */
- ret_val = e1000_check_phy_reset_block(hw);
- if (ret_val)
- return E1000_SUCCESS;
-
- DEBUGOUT("Resetting Phy...\n");
-
- if (hw->mac_type > e1000_82543) {
- if ((hw->mac_type == e1000_80003es2lan) &&
- (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
- swfw = E1000_SWFW_PHY1_SM;
- } else {
- swfw = E1000_SWFW_PHY0_SM;
- }
- if (e1000_swfw_sync_acquire(hw, swfw)) {
- DEBUGOUT("Unable to acquire swfw sync\n");
- return -E1000_ERR_SWFW_SYNC;
- }
- /* Read the device control register and assert the E1000_CTRL_PHY_RST
- * bit. Then, take it out of reset.
- */
- ctrl = E1000_READ_REG(hw, CTRL);
- E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
- E1000_WRITE_FLUSH(hw);
-
- if (hw->mac_type < e1000_82571)
- udelay(10);
- else
- udelay(100);
-
- E1000_WRITE_REG(hw, CTRL, ctrl);
- E1000_WRITE_FLUSH(hw);
-
- if (hw->mac_type >= e1000_82571)
- mdelay(10);
-
- } else {
- /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
- * bit to put the PHY into reset. Then, take it out of reset.
- */
- ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
- ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
- ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
- E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
- E1000_WRITE_FLUSH(hw);
- mdelay(10);
- ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
- E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
- E1000_WRITE_FLUSH(hw);
- }
- udelay(150);
-
- if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
- /* Configure activity LED after PHY reset */
- led_ctrl = E1000_READ_REG(hw, LEDCTL);
- led_ctrl &= IGP_ACTIVITY_LED_MASK;
- led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
- E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
- }
-
- /* Wait for FW to finish PHY configuration. */
- ret_val = e1000_get_phy_cfg_done(hw);
- if (ret_val != E1000_SUCCESS)
- return ret_val;
-
- return ret_val;
-}
-
-/******************************************************************************
- * IGP phy init script - initializes the GbE PHY
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static void
-e1000_phy_init_script(struct e1000_hw *hw)
-{
- uint32_t ret_val;
- uint16_t phy_saved_data;
- DEBUGFUNC();
-
- if (hw->phy_init_script) {
- mdelay(20);
-
- /* Save off the current value of register 0x2F5B to be
- * restored at the end of this routine. */
- ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
-
- /* Disabled the PHY transmitter */
- e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
-
- mdelay(20);
-
- e1000_write_phy_reg(hw, 0x0000, 0x0140);
-
- mdelay(5);
-
- switch (hw->mac_type) {
- case e1000_82541:
- case e1000_82547:
- e1000_write_phy_reg(hw, 0x1F95, 0x0001);
-
- e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
-
- e1000_write_phy_reg(hw, 0x1F79, 0x0018);
-
- e1000_write_phy_reg(hw, 0x1F30, 0x1600);
-
- e1000_write_phy_reg(hw, 0x1F31, 0x0014);
-
- e1000_write_phy_reg(hw, 0x1F32, 0x161C);
-
- e1000_write_phy_reg(hw, 0x1F94, 0x0003);
-
- e1000_write_phy_reg(hw, 0x1F96, 0x003F);
-
- e1000_write_phy_reg(hw, 0x2010, 0x0008);
- break;
-
- case e1000_82541_rev_2:
- case e1000_82547_rev_2:
- e1000_write_phy_reg(hw, 0x1F73, 0x0099);
- break;
- default:
- break;
- }
-
- e1000_write_phy_reg(hw, 0x0000, 0x3300);
-
- mdelay(20);
-
- /* Now enable the transmitter */
- e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
-
- if (hw->mac_type == e1000_82547) {
- uint16_t fused, fine, coarse;
-
- /* Move to analog registers page */
- e1000_read_phy_reg(hw,
- IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
-
- if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
- e1000_read_phy_reg(hw,
- IGP01E1000_ANALOG_FUSE_STATUS, &fused);
-
- fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
- coarse = fused
- & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
-
- if (coarse >
- IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
- coarse -=
- IGP01E1000_ANALOG_FUSE_COARSE_10;
- fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
- } else if (coarse
- == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
- fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
-
- fused = (fused
- & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
- (fine
- & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
- (coarse
- & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
-
- e1000_write_phy_reg(hw,
- IGP01E1000_ANALOG_FUSE_CONTROL, fused);
- e1000_write_phy_reg(hw,
- IGP01E1000_ANALOG_FUSE_BYPASS,
- IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
- }
- }
- }
-}
-
-/******************************************************************************
-* Resets the PHY
-*
-* hw - Struct containing variables accessed by shared code
-*
-* Sets bit 15 of the MII Control register
-******************************************************************************/
-int32_t
-e1000_phy_reset(struct e1000_hw *hw)
-{
- int32_t ret_val;
- uint16_t phy_data;
-
- DEBUGFUNC();
-
- /* In the case of the phy reset being blocked, it's not an error, we
- * simply return success without performing the reset. */
- ret_val = e1000_check_phy_reset_block(hw);
- if (ret_val)
- return E1000_SUCCESS;
-
- switch (hw->phy_type) {
- case e1000_phy_igp:
- case e1000_phy_igp_2:
- case e1000_phy_igp_3:
- case e1000_phy_ife:
- ret_val = e1000_phy_hw_reset(hw);
- if (ret_val)
- return ret_val;
- break;
- default:
- ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
- if (ret_val)
- return ret_val;
-
- phy_data |= MII_CR_RESET;
- ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
- if (ret_val)
- return ret_val;
-
- udelay(1);
- break;
- }
-
- if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
- e1000_phy_init_script(hw);
-
- return E1000_SUCCESS;
-}
-
-static int e1000_set_phy_type (struct e1000_hw *hw)
-{
- DEBUGFUNC ();
-
- if (hw->mac_type == e1000_undefined)
- return -E1000_ERR_PHY_TYPE;
-
- switch (hw->phy_id) {
- case M88E1000_E_PHY_ID:
- case M88E1000_I_PHY_ID:
- case M88E1011_I_PHY_ID:
- case M88E1111_I_PHY_ID:
- hw->phy_type = e1000_phy_m88;
- break;
- case IGP01E1000_I_PHY_ID:
- if (hw->mac_type == e1000_82541 ||
- hw->mac_type == e1000_82541_rev_2 ||
- hw->mac_type == e1000_82547 ||
- hw->mac_type == e1000_82547_rev_2) {
- hw->phy_type = e1000_phy_igp;
- hw->phy_type = e1000_phy_igp;
- break;
- }
- case IGP03E1000_E_PHY_ID:
- hw->phy_type = e1000_phy_igp_3;
- break;
- case IFE_E_PHY_ID:
- case IFE_PLUS_E_PHY_ID:
- case IFE_C_E_PHY_ID:
- hw->phy_type = e1000_phy_ife;
- break;
- case GG82563_E_PHY_ID:
- if (hw->mac_type == e1000_80003es2lan) {
- hw->phy_type = e1000_phy_gg82563;
- break;
- }
- /* Fall Through */
- default:
- /* Should never have loaded on this device */
- hw->phy_type = e1000_phy_undefined;
- return -E1000_ERR_PHY_TYPE;
- }
-
- return E1000_SUCCESS;
-}
-
-/******************************************************************************
-* Probes the expected PHY address for known PHY IDs
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
-static int32_t
-e1000_detect_gig_phy(struct e1000_hw *hw)
-{
- int32_t phy_init_status, ret_val;
- uint16_t phy_id_high, phy_id_low;
- boolean_t match = FALSE;
-
- DEBUGFUNC();
-
- /* The 82571 firmware may still be configuring the PHY. In this
- * case, we cannot access the PHY until the configuration is done. So
- * we explicitly set the PHY values. */
- if (hw->mac_type == e1000_82571 ||
- hw->mac_type == e1000_82572) {
- hw->phy_id = IGP01E1000_I_PHY_ID;
- hw->phy_type = e1000_phy_igp_2;
- return E1000_SUCCESS;
- }
-
- /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
- * work- around that forces PHY page 0 to be set or the reads fail.
- * The rest of the code in this routine uses e1000_read_phy_reg to
- * read the PHY ID. So for ESB-2 we need to have this set so our
- * reads won't fail. If the attached PHY is not a e1000_phy_gg82563,
- * the routines below will figure this out as well. */
- if (hw->mac_type == e1000_80003es2lan)
- hw->phy_type = e1000_phy_gg82563;
-
- /* Read the PHY ID Registers to identify which PHY is onboard. */
- ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
- if (ret_val)
- return ret_val;
-
- hw->phy_id = (uint32_t) (phy_id_high << 16);
- udelay(20);
- ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
- if (ret_val)
- return ret_val;
-
- hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
- hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
-
- switch (hw->mac_type) {
- case e1000_82543:
- if (hw->phy_id == M88E1000_E_PHY_ID)
- match = TRUE;
- break;
- case e1000_82544:
- if (hw->phy_id == M88E1000_I_PHY_ID)
- match = TRUE;
- break;
- case e1000_82540:
- case e1000_82545:
- case e1000_82545_rev_3:
- case e1000_82546:
- case e1000_82546_rev_3:
- if (hw->phy_id == M88E1011_I_PHY_ID)
- match = TRUE;
- break;
- case e1000_82541:
- case e1000_82541_rev_2:
- case e1000_82547:
- case e1000_82547_rev_2:
- if(hw->phy_id == IGP01E1000_I_PHY_ID)
- match = TRUE;
-
- break;
- case e1000_82573:
- if (hw->phy_id == M88E1111_I_PHY_ID)
- match = TRUE;
- break;
- case e1000_80003es2lan:
- if (hw->phy_id == GG82563_E_PHY_ID)
- match = TRUE;
- break;
- case e1000_ich8lan:
- if (hw->phy_id == IGP03E1000_E_PHY_ID)
- match = TRUE;
- if (hw->phy_id == IFE_E_PHY_ID)
- match = TRUE;
- if (hw->phy_id == IFE_PLUS_E_PHY_ID)
- match = TRUE;
- if (hw->phy_id == IFE_C_E_PHY_ID)
- match = TRUE;
- break;
- default:
- DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
- return -E1000_ERR_CONFIG;
- }
-
- phy_init_status = e1000_set_phy_type(hw);
-
- if ((match) && (phy_init_status == E1000_SUCCESS)) {
- DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
- return 0;
- }
- DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
- return -E1000_ERR_PHY;
-}
-
-/*****************************************************************************
- * Set media type and TBI compatibility.
- *
- * hw - Struct containing variables accessed by shared code
- * **************************************************************************/
-void
-e1000_set_media_type(struct e1000_hw *hw)
-{
- uint32_t status;
-
- DEBUGFUNC();
-
- if (hw->mac_type != e1000_82543) {
- /* tbi_compatibility is only valid on 82543 */
- hw->tbi_compatibility_en = FALSE;
- }
-
- switch (hw->device_id) {
- case E1000_DEV_ID_82545GM_SERDES:
- case E1000_DEV_ID_82546GB_SERDES:
- case E1000_DEV_ID_82571EB_SERDES:
- case E1000_DEV_ID_82571EB_SERDES_DUAL:
- case E1000_DEV_ID_82571EB_SERDES_QUAD:
- case E1000_DEV_ID_82572EI_SERDES:
- case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
- hw->media_type = e1000_media_type_internal_serdes;
- break;
- default:
- switch (hw->mac_type) {
- case e1000_82542_rev2_0:
- case e1000_82542_rev2_1:
- hw->media_type = e1000_media_type_fiber;
- break;
- case e1000_ich8lan:
- case e1000_82573:
- /* The STATUS_TBIMODE bit is reserved or reused
- * for the this device.
- */
- hw->media_type = e1000_media_type_copper;
- break;
- default:
- status = E1000_READ_REG(hw, STATUS);
- if (status & E1000_STATUS_TBIMODE) {
- hw->media_type = e1000_media_type_fiber;
- /* tbi_compatibility not valid on fiber */
- hw->tbi_compatibility_en = FALSE;
- } else {
- hw->media_type = e1000_media_type_copper;
- }
- break;
- }
- }
-}
-
-/**
- * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
- *
- * e1000_sw_init initializes the Adapter private data structure.
- * Fields are initialized based on PCI device information and
- * OS network device settings (MTU size).
- **/
-
-static int
-e1000_sw_init(struct eth_device *nic, int cardnum)
-{
- struct e1000_hw *hw = (typeof(hw)) nic->priv;
- int result;
-
- /* PCI config space info */
- pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
- pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
- pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
- &hw->subsystem_vendor_id);
- pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
-
- pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
- pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
-
- /* identify the MAC */
- result = e1000_set_mac_type(hw);
- if (result) {
- E1000_ERR("Unknown MAC Type\n");
- return result;
- }
-
- switch (hw->mac_type) {
- default:
- break;
- case e1000_82541:
- case e1000_82547:
- case e1000_82541_rev_2:
- case e1000_82547_rev_2:
- hw->phy_init_script = 1;
- break;
- }
-
- /* lan a vs. lan b settings */
- if (hw->mac_type == e1000_82546)
- /*this also works w/ multiple 82546 cards */
- /*but not if they're intermingled /w other e1000s */
- hw->lan_loc = (cardnum % 2) ? e1000_lan_b : e1000_lan_a;
- else
- hw->lan_loc = e1000_lan_a;
-
- /* flow control settings */
- hw->fc_high_water = E1000_FC_HIGH_THRESH;
- hw->fc_low_water = E1000_FC_LOW_THRESH;
- hw->fc_pause_time = E1000_FC_PAUSE_TIME;
- hw->fc_send_xon = 1;
-
- /* Media type - copper or fiber */
- e1000_set_media_type(hw);
-
- if (hw->mac_type >= e1000_82543) {
- uint32_t status = E1000_READ_REG(hw, STATUS);
-
- if (status & E1000_STATUS_TBIMODE) {
- DEBUGOUT("fiber interface\n");
- hw->media_type = e1000_media_type_fiber;
- } else {
- DEBUGOUT("copper interface\n");
- hw->media_type = e1000_media_type_copper;
- }
- } else {
- hw->media_type = e1000_media_type_fiber;
- }
-
- hw->tbi_compatibility_en = TRUE;
- hw->wait_autoneg_complete = TRUE;
- if (hw->mac_type < e1000_82543)
- hw->report_tx_early = 0;
- else
- hw->report_tx_early = 1;
-
- return E1000_SUCCESS;
-}
-
-void
-fill_rx(struct e1000_hw *hw)
-{
- struct e1000_rx_desc *rd;
-
- rx_last = rx_tail;
- rd = rx_base + rx_tail;
- rx_tail = (rx_tail + 1) % 8;
- memset(rd, 0, 16);
- rd->buffer_addr = cpu_to_le64((u32) & packet);
- E1000_WRITE_REG(hw, RDT, rx_tail);
-}
-
-/**
- * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
- * @adapter: board private structure
- *
- * Configure the Tx unit of the MAC after a reset.
- **/
-
-static void
-e1000_configure_tx(struct e1000_hw *hw)
-{
- unsigned long ptr;
- unsigned long tctl;
- unsigned long tipg, tarc;
- uint32_t ipgr1, ipgr2;
-
- ptr = (u32) tx_pool;
- if (ptr & 0xf)
- ptr = (ptr + 0x10) & (~0xf);
-
- tx_base = (typeof(tx_base)) ptr;
-
- E1000_WRITE_REG(hw, TDBAL, (u32) tx_base);
- E1000_WRITE_REG(hw, TDBAH, 0);
-
- E1000_WRITE_REG(hw, TDLEN, 128);
-
- /* Setup the HW Tx Head and Tail descriptor pointers */
- E1000_WRITE_REG(hw, TDH, 0);
- E1000_WRITE_REG(hw, TDT, 0);
- tx_tail = 0;
-
- /* Set the default values for the Tx Inter Packet Gap timer */
- if (hw->mac_type <= e1000_82547_rev_2 &&
- (hw->media_type == e1000_media_type_fiber ||
- hw->media_type == e1000_media_type_internal_serdes))
- tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
- else
- tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
-
- /* Set the default values for the Tx Inter Packet Gap timer */
- switch (hw->mac_type) {
- case e1000_82542_rev2_0:
- case e1000_82542_rev2_1:
- tipg = DEFAULT_82542_TIPG_IPGT;
- ipgr1 = DEFAULT_82542_TIPG_IPGR1;
- ipgr2 = DEFAULT_82542_TIPG_IPGR2;
- break;
- case e1000_80003es2lan:
- ipgr1 = DEFAULT_82543_TIPG_IPGR1;
- ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
- break;
- default:
- ipgr1 = DEFAULT_82543_TIPG_IPGR1;
- ipgr2 = DEFAULT_82543_TIPG_IPGR2;
- break;
- }
- tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
- tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
- E1000_WRITE_REG(hw, TIPG, tipg);
- /* Program the Transmit Control Register */
- tctl = E1000_READ_REG(hw, TCTL);
- tctl &= ~E1000_TCTL_CT;
- tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
- (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
-
- if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
- tarc = E1000_READ_REG(hw, TARC0);
- /* set the speed mode bit, we'll clear it if we're not at
- * gigabit link later */
- /* git bit can be set to 1*/
- } else if (hw->mac_type == e1000_80003es2lan) {
- tarc = E1000_READ_REG(hw, TARC0);
- tarc |= 1;
- E1000_WRITE_REG(hw, TARC0, tarc);
- tarc = E1000_READ_REG(hw, TARC1);
- tarc |= 1;
- E1000_WRITE_REG(hw, TARC1, tarc);
- }
-
-
- e1000_config_collision_dist(hw);
- /* Setup Transmit Descriptor Settings for eop descriptor */
- hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
-
- /* Need to set up RS bit */
- if (hw->mac_type < e1000_82543)
- hw->txd_cmd |= E1000_TXD_CMD_RPS;
- else
- hw->txd_cmd |= E1000_TXD_CMD_RS;
- E1000_WRITE_REG(hw, TCTL, tctl);
-}
-
-/**
- * e1000_setup_rctl - configure the receive control register
- * @adapter: Board private structure
- **/
-static void
-e1000_setup_rctl(struct e1000_hw *hw)
-{
- uint32_t rctl;
-
- rctl = E1000_READ_REG(hw, RCTL);
-
- rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
-
- rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
- | E1000_RCTL_RDMTS_HALF; /* |
- (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
-
- if (hw->tbi_compatibility_on == 1)
- rctl |= E1000_RCTL_SBP;
- else
- rctl &= ~E1000_RCTL_SBP;
-
- rctl &= ~(E1000_RCTL_SZ_4096);
- rctl |= E1000_RCTL_SZ_2048;
- rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
- E1000_WRITE_REG(hw, RCTL, rctl);
-}
-
-/**
- * e1000_configure_rx - Configure 8254x Receive Unit after Reset
- * @adapter: board private structure
- *
- * Configure the Rx unit of the MAC after a reset.
- **/
-static void
-e1000_configure_rx(struct e1000_hw *hw)
-{
- unsigned long ptr;
- unsigned long rctl, ctrl_ext;
- rx_tail = 0;
- /* make sure receives are disabled while setting up the descriptors */
- rctl = E1000_READ_REG(hw, RCTL);
- E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
- if (hw->mac_type >= e1000_82540) {
- /* Set the interrupt throttling rate. Value is calculated
- * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
-#define MAX_INTS_PER_SEC 8000
-#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
- E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
- }
-
- if (hw->mac_type >= e1000_82571) {
- ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
- /* Reset delay timers after every interrupt */
- ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
- E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
- E1000_WRITE_FLUSH(hw);
- }
- /* Setup the Base and Length of the Rx Descriptor Ring */
- ptr = (u32) rx_pool;
- if (ptr & 0xf)
- ptr = (ptr + 0x10) & (~0xf);
- rx_base = (typeof(rx_base)) ptr;
- E1000_WRITE_REG(hw, RDBAL, (u32) rx_base);
- E1000_WRITE_REG(hw, RDBAH, 0);
-
- E1000_WRITE_REG(hw, RDLEN, 128);
-
- /* Setup the HW Rx Head and Tail Descriptor Pointers */
- E1000_WRITE_REG(hw, RDH, 0);
- E1000_WRITE_REG(hw, RDT, 0);
- /* Enable Receives */
-
- E1000_WRITE_REG(hw, RCTL, rctl);
- fill_rx(hw);
-}
-
-/**************************************************************************
-POLL - Wait for a frame
-***************************************************************************/
-static int
-e1000_poll(struct eth_device *nic)
-{
- struct e1000_hw *hw = nic->priv;
- struct e1000_rx_desc *rd;
- /* return true if there's an ethernet packet ready to read */
- rd = rx_base + rx_last;
- if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD)
- return 0;
- /*DEBUGOUT("recv: packet len=%d \n", rd->length); */
- NetReceive((uchar *)packet, le32_to_cpu(rd->length));
- fill_rx(hw);
- return 1;
-}
-
-/**************************************************************************
-TRANSMIT - Transmit a frame
-***************************************************************************/
-static int
-e1000_transmit(struct eth_device *nic, volatile void *packet, int length)
-{
- struct e1000_hw *hw = nic->priv;
- struct e1000_tx_desc *txp;
- int i = 0;
-
- txp = tx_base + tx_tail;
- tx_tail = (tx_tail + 1) % 8;
-
- txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, packet));
- txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
- txp->upper.data = 0;
- E1000_WRITE_REG(hw, TDT, tx_tail);
-
- E1000_WRITE_FLUSH(hw);
- while (!(le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)) {
- if (i++ > TOUT_LOOP) {
- DEBUGOUT("e1000: tx timeout\n");
- return 0;
- }
- udelay(10); /* give the nic a chance to write to the register */
- }
- return 1;
-}
-
-/*reset function*/
-static inline int
-e1000_reset(struct eth_device *nic)
-{
- struct e1000_hw *hw = nic->priv;
-
- e1000_reset_hw(hw);
- if (hw->mac_type >= e1000_82544) {
- E1000_WRITE_REG(hw, WUC, 0);
- }
- return e1000_init_hw(nic);
-}
-
-/**************************************************************************
-DISABLE - Turn off ethernet interface
-***************************************************************************/
-static void
-e1000_disable(struct eth_device *nic)
-{
- struct e1000_hw *hw = nic->priv;
-
- /* Turn off the ethernet interface */
- E1000_WRITE_REG(hw, RCTL, 0);
- E1000_WRITE_REG(hw, TCTL, 0);
-
- /* Clear the transmit ring */
- E1000_WRITE_REG(hw, TDH, 0);
- E1000_WRITE_REG(hw, TDT, 0);
-
- /* Clear the receive ring */
- E1000_WRITE_REG(hw, RDH, 0);
- E1000_WRITE_REG(hw, RDT, 0);
-
- /* put the card in its initial state */
-#if 0
- E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST);
-#endif
- mdelay(10);
-
-}
-
-/**************************************************************************
-INIT - set up ethernet interface(s)
-***************************************************************************/
-static int
-e1000_init(struct eth_device *nic, bd_t * bis)
-{
- struct e1000_hw *hw = nic->priv;
- int ret_val = 0;
-
- ret_val = e1000_reset(nic);
- if (ret_val < 0) {
- if ((ret_val == -E1000_ERR_NOLINK) ||
- (ret_val == -E1000_ERR_TIMEOUT)) {
- E1000_ERR("Valid Link not detected\n");
- } else {
- E1000_ERR("Hardware Initialization Failed\n");
- }
- return 0;
- }
- e1000_configure_tx(hw);
- e1000_setup_rctl(hw);
- e1000_configure_rx(hw);
- return 1;
-}
-
-/******************************************************************************
- * Gets the current PCI bus type of hardware
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-void e1000_get_bus_type(struct e1000_hw *hw)
-{
- uint32_t status;
-
- switch (hw->mac_type) {
- case e1000_82542_rev2_0:
- case e1000_82542_rev2_1:
- hw->bus_type = e1000_bus_type_pci;
- break;
- case e1000_82571:
- case e1000_82572:
- case e1000_82573:
- case e1000_80003es2lan:
- hw->bus_type = e1000_bus_type_pci_express;
- break;
- case e1000_ich8lan:
- hw->bus_type = e1000_bus_type_pci_express;
- break;
- default:
- status = E1000_READ_REG(hw, STATUS);
- hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
- e1000_bus_type_pcix : e1000_bus_type_pci;
- break;
- }
-}
-
-/**************************************************************************
-PROBE - Look for an adapter, this routine's visible to the outside
-You should omit the last argument struct pci_device * for a non-PCI NIC
-***************************************************************************/
-int
-e1000_initialize(bd_t * bis)
-{
- pci_dev_t devno;
- int card_number = 0;
- struct eth_device *nic = NULL;
- struct e1000_hw *hw = NULL;
- u32 iobase;
- int idx = 0;
- u32 PciCommandWord;
-
- DEBUGFUNC();
-
- while (1) { /* Find PCI device(s) */
- if ((devno = pci_find_devices(supported, idx++)) < 0) {
- break;
- }
-
- pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase);
- iobase &= ~0xf; /* Mask the bits that say "this is an io addr" */
- DEBUGOUT("e1000#%d: iobase 0x%08x\n", card_number, iobase);
-
- pci_write_config_dword(devno, PCI_COMMAND,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
- /* Check if I/O accesses and Bus Mastering are enabled. */
- pci_read_config_dword(devno, PCI_COMMAND, &PciCommandWord);
- if (!(PciCommandWord & PCI_COMMAND_MEMORY)) {
- printf("Error: Can not enable MEM access.\n");
- continue;
- } else if (!(PciCommandWord & PCI_COMMAND_MASTER)) {
- printf("Error: Can not enable Bus Mastering.\n");
- continue;
- }
-
- nic = (struct eth_device *) malloc(sizeof (*nic));
- hw = (struct e1000_hw *) malloc(sizeof (*hw));
- hw->pdev = devno;
- nic->priv = hw;
-
- sprintf(nic->name, "e1000#%d", card_number);
-
- /* Are these variables needed? */
- hw->fc = e1000_fc_default;
- hw->original_fc = e1000_fc_default;
- hw->autoneg_failed = 0;
- hw->autoneg = 1;
- hw->get_link_status = TRUE;
- hw->hw_addr =
- pci_map_bar(devno, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
- hw->mac_type = e1000_undefined;
-
- /* MAC and Phy settings */
- if (e1000_sw_init(nic, card_number) < 0) {
- free(hw);
- free(nic);
- return 0;
- }
- if (e1000_check_phy_reset_block(hw))
- printf("phy reset block error \n");
- e1000_reset_hw(hw);
-#if !(defined(CONFIG_AP1000) || defined(CONFIG_MVBC_1G))
- if (e1000_init_eeprom_params(hw)) {
- printf("The EEPROM Checksum Is Not Valid\n");
- free(hw);
- free(nic);
- return 0;
- }
- if (e1000_validate_eeprom_checksum(nic) < 0) {
- printf("The EEPROM Checksum Is Not Valid\n");
- free(hw);
- free(nic);
- return 0;
- }
-#endif
- e1000_read_mac_addr(nic);
-
- /* get the bus type information */
- e1000_get_bus_type(hw);
-
- printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n",
- nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2],
- nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]);
-
- nic->init = e1000_init;
- nic->recv = e1000_poll;
- nic->send = e1000_transmit;
- nic->halt = e1000_disable;
-
- eth_register(nic);
-
- card_number++;
- }
- return card_number;
-}
+++ /dev/null
-/*******************************************************************************
-
-
- Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
-
- This program is free software; you can redistribute it and/or modify it
- under the terms of the GNU General Public License as published by the Free
- Software Foundation; either version 2 of the License, or (at your option)
- any later version.
-
- This program is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- more details.
-
- You should have received a copy of the GNU General Public License along with
- this program; if not, write to the Free Software Foundation, Inc., 59
- Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
- The full GNU General Public License is included in this distribution in the
- file called LICENSE.
-
- Contact Information:
- Linux NICS <linux.nics@intel.com>
- Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
-
-*******************************************************************************/
-
-/* e1000_hw.h
- * Structures, enums, and macros for the MAC
- */
-
-#ifndef _E1000_HW_H_
-#define _E1000_HW_H_
-
-#include <common.h>
-#include <malloc.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <pci.h>
-
-#define E1000_ERR(args...) printf("e1000: " args)
-
-#ifdef E1000_DEBUG
-#define E1000_DBG(args...) printf("e1000: " args)
-#define DEBUGOUT(fmt,args...) printf(fmt ,##args)
-#define DEBUGFUNC() printf("%s\n", __FUNCTION__);
-#else
-#define E1000_DBG(args...)
-#define DEBUGFUNC()
-#define DEBUGOUT(fmt,args...)
-#endif
-
-/* Forward declarations of structures used by the shared code */
-struct e1000_hw;
-struct e1000_hw_stats;
-
-typedef enum {
- FALSE = 0,
- TRUE = 1
-} boolean_t;
-
-/* Enumerated types specific to the e1000 hardware */
-/* Media Access Controlers */
-typedef enum {
- e1000_undefined = 0,
- e1000_82542_rev2_0,
- e1000_82542_rev2_1,
- e1000_82543,
- e1000_82544,
- e1000_82540,
- e1000_82545,
- e1000_82545_rev_3,
- e1000_82546,
- e1000_82546_rev_3,
- e1000_82541,
- e1000_82541_rev_2,
- e1000_82547,
- e1000_82547_rev_2,
- e1000_82571,
- e1000_82572,
- e1000_82573,
- e1000_80003es2lan,
- e1000_ich8lan,
- e1000_num_macs
-} e1000_mac_type;
-
-/* Media Types */
-typedef enum {
- e1000_media_type_copper = 0,
- e1000_media_type_fiber = 1,
- e1000_media_type_internal_serdes = 2,
- e1000_num_media_types
-} e1000_media_type;
-
-typedef enum {
- e1000_eeprom_uninitialized = 0,
- e1000_eeprom_spi,
- e1000_eeprom_microwire,
- e1000_eeprom_flash,
- e1000_eeprom_ich8,
- e1000_eeprom_none, /* No NVM support */
- e1000_num_eeprom_types
-} e1000_eeprom_type;
-
-typedef enum {
- e1000_10_half = 0,
- e1000_10_full = 1,
- e1000_100_half = 2,
- e1000_100_full = 3
-} e1000_speed_duplex_type;
-
-typedef enum {
- e1000_lan_a = 0,
- e1000_lan_b = 1
-} e1000_lan_loc;
-
-/* Flow Control Settings */
-typedef enum {
- e1000_fc_none = 0,
- e1000_fc_rx_pause = 1,
- e1000_fc_tx_pause = 2,
- e1000_fc_full = 3,
- e1000_fc_default = 0xFF
-} e1000_fc_type;
-
-/* PCI bus types */
-typedef enum {
- e1000_bus_type_unknown = 0,
- e1000_bus_type_pci,
- e1000_bus_type_pcix,
- e1000_bus_type_pci_express,
- e1000_bus_type_reserved
-} e1000_bus_type;
-
-/* PCI bus speeds */
-typedef enum {
- e1000_bus_speed_unknown = 0,
- e1000_bus_speed_33,
- e1000_bus_speed_66,
- e1000_bus_speed_100,
- e1000_bus_speed_133,
- e1000_bus_speed_reserved
-} e1000_bus_speed;
-
-/* PCI bus widths */
-typedef enum {
- e1000_bus_width_unknown = 0,
- e1000_bus_width_32,
- e1000_bus_width_64
-} e1000_bus_width;
-
-/* PHY status info structure and supporting enums */
-typedef enum {
- e1000_cable_length_50 = 0,
- e1000_cable_length_50_80,
- e1000_cable_length_80_110,
- e1000_cable_length_110_140,
- e1000_cable_length_140,
- e1000_cable_length_undefined = 0xFF
-} e1000_cable_length;
-
-typedef enum {
- e1000_10bt_ext_dist_enable_normal = 0,
- e1000_10bt_ext_dist_enable_lower,
- e1000_10bt_ext_dist_enable_undefined = 0xFF
-} e1000_10bt_ext_dist_enable;
-
-typedef enum {
- e1000_rev_polarity_normal = 0,
- e1000_rev_polarity_reversed,
- e1000_rev_polarity_undefined = 0xFF
-} e1000_rev_polarity;
-
-typedef enum {
- e1000_polarity_reversal_enabled = 0,
- e1000_polarity_reversal_disabled,
- e1000_polarity_reversal_undefined = 0xFF
-} e1000_polarity_reversal;
-
-typedef enum {
- e1000_auto_x_mode_manual_mdi = 0,
- e1000_auto_x_mode_manual_mdix,
- e1000_auto_x_mode_auto1,
- e1000_auto_x_mode_auto2,
- e1000_auto_x_mode_undefined = 0xFF
-} e1000_auto_x_mode;
-
-typedef enum {
- e1000_1000t_rx_status_not_ok = 0,
- e1000_1000t_rx_status_ok,
- e1000_1000t_rx_status_undefined = 0xFF
-} e1000_1000t_rx_status;
-
-typedef enum {
- e1000_phy_m88 = 0,
- e1000_phy_igp,
- e1000_phy_igp_2,
- e1000_phy_gg82563,
- e1000_phy_igp_3,
- e1000_phy_ife,
- e1000_phy_undefined = 0xFF
-} e1000_phy_type;
-
-struct e1000_phy_info {
- e1000_cable_length cable_length;
- e1000_10bt_ext_dist_enable extended_10bt_distance;
- e1000_rev_polarity cable_polarity;
- e1000_polarity_reversal polarity_correction;
- e1000_auto_x_mode mdix_mode;
- e1000_1000t_rx_status local_rx;
- e1000_1000t_rx_status remote_rx;
-};
-
-struct e1000_phy_stats {
- uint32_t idle_errors;
- uint32_t receive_errors;
-};
-
-/* Error Codes */
-#define E1000_SUCCESS 0
-#define E1000_ERR_EEPROM 1
-#define E1000_ERR_PHY 2
-#define E1000_ERR_CONFIG 3
-#define E1000_ERR_PARAM 4
-#define E1000_ERR_MAC_TYPE 5
-#define E1000_ERR_PHY_TYPE 6
-#define E1000_ERR_NOLINK 7
-#define E1000_ERR_TIMEOUT 8
-#define E1000_ERR_RESET 9
-#define E1000_ERR_MASTER_REQUESTS_PENDING 10
-#define E1000_ERR_HOST_INTERFACE_COMMAND 11
-#define E1000_BLK_PHY_RESET 12
-#define E1000_ERR_SWFW_SYNC 13
-
-/* PCI Device IDs */
-#define E1000_DEV_ID_82542 0x1000
-#define E1000_DEV_ID_82543GC_FIBER 0x1001
-#define E1000_DEV_ID_82543GC_COPPER 0x1004
-#define E1000_DEV_ID_82544EI_COPPER 0x1008
-#define E1000_DEV_ID_82544EI_FIBER 0x1009
-#define E1000_DEV_ID_82544GC_COPPER 0x100C
-#define E1000_DEV_ID_82544GC_LOM 0x100D
-#define E1000_DEV_ID_82540EM 0x100E
-#define E1000_DEV_ID_82540EM_LOM 0x1015
-#define E1000_DEV_ID_82540EP_LOM 0x1016
-#define E1000_DEV_ID_82540EP 0x1017
-#define E1000_DEV_ID_82540EP_LP 0x101E
-#define E1000_DEV_ID_82545EM_COPPER 0x100F
-#define E1000_DEV_ID_82545EM_FIBER 0x1011
-#define E1000_DEV_ID_82545GM_COPPER 0x1026
-#define E1000_DEV_ID_82545GM_FIBER 0x1027
-#define E1000_DEV_ID_82545GM_SERDES 0x1028
-#define E1000_DEV_ID_82546EB_COPPER 0x1010
-#define E1000_DEV_ID_82546EB_FIBER 0x1012
-#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
-#define E1000_DEV_ID_82541EI 0x1013
-#define E1000_DEV_ID_82541EI_MOBILE 0x1018
-#define E1000_DEV_ID_82541ER_LOM 0x1014
-#define E1000_DEV_ID_82541ER 0x1078
-#define E1000_DEV_ID_82547GI 0x1075
-#define E1000_DEV_ID_82541GI 0x1076
-#define E1000_DEV_ID_82541GI_MOBILE 0x1077
-#define E1000_DEV_ID_82541GI_LF 0x107C
-#define E1000_DEV_ID_82546GB_COPPER 0x1079
-#define E1000_DEV_ID_82546GB_FIBER 0x107A
-#define E1000_DEV_ID_82546GB_SERDES 0x107B
-#define E1000_DEV_ID_82546GB_PCIE 0x108A
-#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
-#define E1000_DEV_ID_82547EI 0x1019
-#define E1000_DEV_ID_82547EI_MOBILE 0x101A
-#define E1000_DEV_ID_82571EB_COPPER 0x105E
-#define E1000_DEV_ID_82571EB_FIBER 0x105F
-#define E1000_DEV_ID_82571EB_SERDES 0x1060
-#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
-#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
-#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
-#define E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE 0x10BC
-#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
-#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
-#define E1000_DEV_ID_82572EI_COPPER 0x107D
-#define E1000_DEV_ID_82572EI_FIBER 0x107E
-#define E1000_DEV_ID_82572EI_SERDES 0x107F
-#define E1000_DEV_ID_82572EI 0x10B9
-#define E1000_DEV_ID_82573E 0x108B
-#define E1000_DEV_ID_82573E_IAMT 0x108C
-#define E1000_DEV_ID_82573L 0x109A
-#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
-#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
-#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
-#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
-#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
-
-#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
-#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
-#define E1000_DEV_ID_ICH8_IGP_C 0x104B
-#define E1000_DEV_ID_ICH8_IFE 0x104C
-#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
-#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
-#define E1000_DEV_ID_ICH8_IGP_M 0x104D
-
-#define IGP03E1000_E_PHY_ID 0x02A80390
-#define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */
-#define IFE_PLUS_E_PHY_ID 0x02A80320
-#define IFE_C_E_PHY_ID 0x02A80310
-
-#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status,
- Control and Address */
-#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special
- control register */
-#define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False
- Carrier Counter */
-#define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnet
- Counter */
-#define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error
- Frame Counter */
-#define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error
- Counter */
-#define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive
- Premature End Of Frame
- Error Counter */
-#define IFE_PHY_RCV_EOF_ERR 0x18 /* 10BaseT Receive End Of
- Frame Error Counter */
-#define IFE_PHY_TX_JABBER_DETECT 0x19 /* 10BaseT Transmit Jabber
- Detect Counter */
-#define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and
- Status */
-#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and
- LED configuration */
-#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */
-#define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control
- (HWI) */
-
-#define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Defaut 1 = Disable auto
- reduced power down */
-#define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power
- state of 100BASE-TX */
-#define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power
- state of 10BASE-T */
-#define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T
- polarity */
-#define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY
- address */
-#define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed
- result 1=100Mbs, 0=10Mbs */
-#define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation
- duplex result 1=Full, 0=Half */
-#define IFE_PESC_POLARITY_REVERSED_SHIFT 8
-
-#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dyanmic Power Down
- disabled */
-#define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity,
- 0=Normal */
-#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity
- Disabled, 0=Enabled */
-#define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled,
- 0=Normal Jabber Operation */
-#define IFE_PSC_FORCE_POLARITY_SHIFT 5
-#define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4
-
-#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X
- feature, default 0=disabled */
-#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X,
- 0=force MDI */
-#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
-#define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010 /* Resolution algorithm
- is completed */
-#define IFE_PMC_MDIX_MODE_SHIFT 6
-#define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */
-
-#define IFE_PHC_HWI_ENABLE 0x8000 /* Enable the HWI
- feature */
-#define IFE_PHC_ABILITY_CHECK 0x4000 /* 1= Test Passed,
- 0=failed */
-#define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses
- on the wire */
-#define IFE_PHC_HIGHZ 0x0200 /* 1 = Open Circuit */
-#define IFE_PHC_LOWZ 0x0400 /* 1 = Short Circuit */
-#define IFE_PHC_LOW_HIGH_Z_MASK 0x0600 /* Mask for indication
- type of problem on the line */
-#define IFE_PHC_DISTANCE_MASK 0x01FF /* Mask for distance to
- the cable problem, in 80cm granularity */
-#define IFE_PHC_RESET_ALL_MASK 0x0000 /* Disable HWI */
-#define IFE_PSCL_PROBE_MODE 0x0020 /* LED Probe mode */
-#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2
- off */
-#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
-
-
-#define NUM_DEV_IDS 16
-
-#define NODE_ADDRESS_SIZE 6
-#define ETH_LENGTH_OF_ADDRESS 6
-
-/* MAC decode size is 128K - This is the size of BAR0 */
-#define MAC_DECODE_SIZE (128 * 1024)
-
-#define E1000_82542_2_0_REV_ID 2
-#define E1000_82542_2_1_REV_ID 3
-#define E1000_REVISION_0 0
-#define E1000_REVISION_1 1
-#define E1000_REVISION_2 2
-#define E1000_REVISION_3 3
-
-#define SPEED_10 10
-#define SPEED_100 100
-#define SPEED_1000 1000
-#define HALF_DUPLEX 1
-#define FULL_DUPLEX 2
-
-/* The sizes (in bytes) of a ethernet packet */
-#define ENET_HEADER_SIZE 14
-#define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */
-#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
-#define ETHERNET_FCS_SIZE 4
-#define MAXIMUM_ETHERNET_PACKET_SIZE \
- (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
-#define MINIMUM_ETHERNET_PACKET_SIZE \
- (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
-#define CRC_LENGTH ETHERNET_FCS_SIZE
-#define MAX_JUMBO_FRAME_SIZE 0x3F00
-
-/* 802.1q VLAN Packet Sizes */
-#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */
-
-/* Ethertype field values */
-#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
-#define ETHERNET_IP_TYPE 0x0800 /* IP packets */
-#define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */
-
-/* Packet Header defines */
-#define IP_PROTOCOL_TCP 6
-#define IP_PROTOCOL_UDP 0x11
-
-/* This defines the bits that are set in the Interrupt Mask
- * Set/Read Register. Each bit is documented below:
- * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
- * o RXSEQ = Receive Sequence Error
- */
-#define POLL_IMS_ENABLE_MASK ( \
- E1000_IMS_RXDMT0 | \
- E1000_IMS_RXSEQ)
-
-/* This defines the bits that are set in the Interrupt Mask
- * Set/Read Register. Each bit is documented below:
- * o RXT0 = Receiver Timer Interrupt (ring 0)
- * o TXDW = Transmit Descriptor Written Back
- * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
- * o RXSEQ = Receive Sequence Error
- * o LSC = Link Status Change
- */
-#define IMS_ENABLE_MASK ( \
- E1000_IMS_RXT0 | \
- E1000_IMS_TXDW | \
- E1000_IMS_RXDMT0 | \
- E1000_IMS_RXSEQ | \
- E1000_IMS_LSC)
-
-/* The number of high/low register pairs in the RAR. The RAR (Receive Address
- * Registers) holds the directed and multicast addresses that we monitor. We
- * reserve one of these spots for our directed address, allowing us room for
- * E1000_RAR_ENTRIES - 1 multicast addresses.
- */
-#define E1000_RAR_ENTRIES 16
-
-#define MIN_NUMBER_OF_DESCRIPTORS 8
-#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
-
-/* Receive Descriptor */
-struct e1000_rx_desc {
- uint64_t buffer_addr; /* Address of the descriptor's data buffer */
- uint16_t length; /* Length of data DMAed into data buffer */
- uint16_t csum; /* Packet checksum */
- uint8_t status; /* Descriptor status */
- uint8_t errors; /* Descriptor Errors */
- uint16_t special;
-};
-
-/* Receive Decriptor bit definitions */
-#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
-#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
-#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
-#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
-#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
-#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
-#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
-#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
-#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
-#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
-#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
-#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
-#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
-#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
-#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
-#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
-#define E1000_RXD_SPC_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */
-#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
-#define E1000_RXD_SPC_CFI_SHIFT 0x000C /* CFI is bit 12 */
-
-/* mask to determine if packets should be dropped due to frame errors */
-#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
- E1000_RXD_ERR_CE | \
- E1000_RXD_ERR_SE | \
- E1000_RXD_ERR_SEQ | \
- E1000_RXD_ERR_CXE | \
- E1000_RXD_ERR_RXE)
-
-/* Transmit Descriptor */
-struct e1000_tx_desc {
- uint64_t buffer_addr; /* Address of the descriptor's data buffer */
- union {
- uint32_t data;
- struct {
- uint16_t length; /* Data buffer length */
- uint8_t cso; /* Checksum offset */
- uint8_t cmd; /* Descriptor control */
- } flags;
- } lower;
- union {
- uint32_t data;
- struct {
- uint8_t status; /* Descriptor status */
- uint8_t css; /* Checksum start */
- uint16_t special;
- } fields;
- } upper;
-};
-
-/* Transmit Descriptor bit definitions */
-#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
-#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
-#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
-#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
-#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
-#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
-#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
-#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
-#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
-#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
-#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
-#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
-#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
-#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
-#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
-#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
-#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
-#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
-#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
-#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
-
-/* Offload Context Descriptor */
-struct e1000_context_desc {
- union {
- uint32_t ip_config;
- struct {
- uint8_t ipcss; /* IP checksum start */
- uint8_t ipcso; /* IP checksum offset */
- uint16_t ipcse; /* IP checksum end */
- } ip_fields;
- } lower_setup;
- union {
- uint32_t tcp_config;
- struct {
- uint8_t tucss; /* TCP checksum start */
- uint8_t tucso; /* TCP checksum offset */
- uint16_t tucse; /* TCP checksum end */
- } tcp_fields;
- } upper_setup;
- uint32_t cmd_and_length; /* */
- union {
- uint32_t data;
- struct {
- uint8_t status; /* Descriptor status */
- uint8_t hdr_len; /* Header length */
- uint16_t mss; /* Maximum segment size */
- } fields;
- } tcp_seg_setup;
-};
-
-/* Offload data descriptor */
-struct e1000_data_desc {
- uint64_t buffer_addr; /* Address of the descriptor's buffer address */
- union {
- uint32_t data;
- struct {
- uint16_t length; /* Data buffer length */
- uint8_t typ_len_ext; /* */
- uint8_t cmd; /* */
- } flags;
- } lower;
- union {
- uint32_t data;
- struct {
- uint8_t status; /* Descriptor status */
- uint8_t popts; /* Packet Options */
- uint16_t special; /* */
- } fields;
- } upper;
-};
-
-/* Filters */
-#define E1000_NUM_UNICAST 16 /* Unicast filter entries */
-#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
-#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
-
-/* Receive Address Register */
-struct e1000_rar {
- volatile uint32_t low; /* receive address low */
- volatile uint32_t high; /* receive address high */
-};
-
-/* The number of entries in the Multicast Table Array (MTA). */
-#define E1000_NUM_MTA_REGISTERS 128
-
-/* IPv4 Address Table Entry */
-struct e1000_ipv4_at_entry {
- volatile uint32_t ipv4_addr; /* IP Address (RW) */
- volatile uint32_t reserved;
-};
-
-/* Four wakeup IP addresses are supported */
-#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
-#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
-#define E1000_IP6AT_SIZE 1
-
-/* IPv6 Address Table Entry */
-struct e1000_ipv6_at_entry {
- volatile uint8_t ipv6_addr[16];
-};
-
-/* Flexible Filter Length Table Entry */
-struct e1000_fflt_entry {
- volatile uint32_t length; /* Flexible Filter Length (RW) */
- volatile uint32_t reserved;
-};
-
-/* Flexible Filter Mask Table Entry */
-struct e1000_ffmt_entry {
- volatile uint32_t mask; /* Flexible Filter Mask (RW) */
- volatile uint32_t reserved;
-};
-
-/* Flexible Filter Value Table Entry */
-struct e1000_ffvt_entry {
- volatile uint32_t value; /* Flexible Filter Value (RW) */
- volatile uint32_t reserved;
-};
-
-/* Four Flexible Filters are supported */
-#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
-
-/* Each Flexible Filter is at most 128 (0x80) bytes in length */
-#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
-
-#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
-#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
-#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
-
-/* Register Set. (82543, 82544)
- *
- * Registers are defined to be 32 bits and should be accessed as 32 bit values.
- * These registers are physically located on the NIC, but are mapped into the
- * host memory address space.
- *
- * RW - register is both readable and writable
- * RO - register is read only
- * WO - register is write only
- * R/clr - register is read only and is cleared when read
- * A - register array
- */
-#define E1000_CTRL 0x00000 /* Device Control - RW */
-#define E1000_STATUS 0x00008 /* Device Status - RO */
-#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
-#define E1000_EERD 0x00014 /* EEPROM Read - RW */
-#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
-#define E1000_MDIC 0x00020 /* MDI Control - RW */
-#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
-#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
-#define E1000_FCT 0x00030 /* Flow Control Type - RW */
-#define E1000_VET 0x00038 /* VLAN Ether Type - RW */
-#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
-#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
-#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
-#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
-#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
-#define E1000_RCTL 0x00100 /* RX Control - RW */
-#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
-#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
-#define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
-#define E1000_TCTL 0x00400 /* TX Control - RW */
-#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */
-#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
-#define E1000_TBT 0x00448 /* TX Burst Timer - RW */
-#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
-#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
-#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
-#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
-#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
-#define FEXTNVM_SW_CONFIG 0x0001
-#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
-#define E1000_PBS 0x01008 /* Packet Buffer Size */
-#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
-#define E1000_FLASH_UPDATES 1000
-#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
-#define E1000_FLASHT 0x01028 /* FLASH Timer Register */
-#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
-#define E1000_FLSWCTL 0x01030 /* FLASH control register */
-#define E1000_FLSWDATA 0x01034 /* FLASH data register */
-#define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */
-#define E1000_FLOP 0x0103C /* FLASH Opcode Register */
-#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
-#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
-#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
-#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
-#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
-#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
-#define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
-#define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
-#define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
-#define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */
-#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
-#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
-#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
-#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
-#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
-#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
-#define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */
-#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
-#define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
-#define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */
-#define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
-#define E1000_TDH 0x03810 /* TX Descriptor Head - RW */
-#define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */
-#define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */
-#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
-#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
-#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
-#define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */
-#define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */
-#define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */
-#define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */
-#define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */
-#define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */
-#define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */
-#define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */
-#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
-#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
-#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
-#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
-#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
-#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
-#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
-#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
-#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
-#define E1000_COLC 0x04028 /* Collision Count - R/clr */
-#define E1000_DC 0x04030 /* Defer Count - R/clr */
-#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
-#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
-#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
-#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
-#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
-#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
-#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
-#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
-#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
-#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
-#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
-#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
-#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
-#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
-#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
-#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
-#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
-#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
-#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
-#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
-#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
-#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
-#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
-#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
-#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
-#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
-#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
-#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
-#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
-#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
-#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
-#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
-#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
-#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
-#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
-#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
-#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
-#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
-#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
-#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
-#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
-#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
-#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
-#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
-#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
-#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
-#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
-#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
-#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
-#define E1000_RA 0x05400 /* Receive Address - RW Array */
-#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
-#define E1000_WUC 0x05800 /* Wakeup Control - RW */
-#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
-#define E1000_WUS 0x05810 /* Wakeup Status - RO */
-#define E1000_MANC 0x05820 /* Management Control - RW */
-#define E1000_IPAV 0x05838 /* IP Address Valid - RW */
-#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
-#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
-#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
-#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
-#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
-#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
-#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
-
-/* Register Set (82542)
- *
- * Some of the 82542 registers are located at different offsets than they are
- * in more current versions of the 8254x. Despite the difference in location,
- * the registers function in the same manner.
- */
-#define E1000_82542_CTRL E1000_CTRL
-#define E1000_82542_STATUS E1000_STATUS
-#define E1000_82542_EECD E1000_EECD
-#define E1000_82542_EERD E1000_EERD
-#define E1000_82542_CTRL_EXT E1000_CTRL_EXT
-#define E1000_82542_MDIC E1000_MDIC
-#define E1000_82542_FCAL E1000_FCAL
-#define E1000_82542_FCAH E1000_FCAH
-#define E1000_82542_FCT E1000_FCT
-#define E1000_82542_VET E1000_VET
-#define E1000_82542_RA 0x00040
-#define E1000_82542_ICR E1000_ICR
-#define E1000_82542_ITR E1000_ITR
-#define E1000_82542_ICS E1000_ICS
-#define E1000_82542_IMS E1000_IMS
-#define E1000_82542_IMC E1000_IMC
-#define E1000_82542_RCTL E1000_RCTL
-#define E1000_82542_RDTR 0x00108
-#define E1000_82542_RDBAL 0x00110
-#define E1000_82542_RDBAH 0x00114
-#define E1000_82542_RDLEN 0x00118
-#define E1000_82542_RDH 0x00120
-#define E1000_82542_RDT 0x00128
-#define E1000_82542_FCRTH 0x00160
-#define E1000_82542_FCRTL 0x00168
-#define E1000_82542_FCTTV E1000_FCTTV
-#define E1000_82542_TXCW E1000_TXCW
-#define E1000_82542_RXCW E1000_RXCW
-#define E1000_82542_MTA 0x00200
-#define E1000_82542_TCTL E1000_TCTL
-#define E1000_82542_TIPG E1000_TIPG
-#define E1000_82542_TDBAL 0x00420
-#define E1000_82542_TDBAH 0x00424
-#define E1000_82542_TDLEN 0x00428
-#define E1000_82542_TDH 0x00430
-#define E1000_82542_TDT 0x00438
-#define E1000_82542_TIDV 0x00440
-#define E1000_82542_TBT E1000_TBT
-#define E1000_82542_AIT E1000_AIT
-#define E1000_82542_VFTA 0x00600
-#define E1000_82542_LEDCTL E1000_LEDCTL
-#define E1000_82542_PBA E1000_PBA
-#define E1000_82542_RXDCTL E1000_RXDCTL
-#define E1000_82542_RADV E1000_RADV
-#define E1000_82542_RSRPD E1000_RSRPD
-#define E1000_82542_TXDMAC E1000_TXDMAC
-#define E1000_82542_TXDCTL E1000_TXDCTL
-#define E1000_82542_TADV E1000_TADV
-#define E1000_82542_TSPMT E1000_TSPMT
-#define E1000_82542_CRCERRS E1000_CRCERRS
-#define E1000_82542_ALGNERRC E1000_ALGNERRC
-#define E1000_82542_SYMERRS E1000_SYMERRS
-#define E1000_82542_RXERRC E1000_RXERRC
-#define E1000_82542_MPC E1000_MPC
-#define E1000_82542_SCC E1000_SCC
-#define E1000_82542_ECOL E1000_ECOL
-#define E1000_82542_MCC E1000_MCC
-#define E1000_82542_LATECOL E1000_LATECOL
-#define E1000_82542_COLC E1000_COLC
-#define E1000_82542_DC E1000_DC
-#define E1000_82542_TNCRS E1000_TNCRS
-#define E1000_82542_SEC E1000_SEC
-#define E1000_82542_CEXTERR E1000_CEXTERR
-#define E1000_82542_RLEC E1000_RLEC
-#define E1000_82542_XONRXC E1000_XONRXC
-#define E1000_82542_XONTXC E1000_XONTXC
-#define E1000_82542_XOFFRXC E1000_XOFFRXC
-#define E1000_82542_XOFFTXC E1000_XOFFTXC
-#define E1000_82542_FCRUC E1000_FCRUC
-#define E1000_82542_PRC64 E1000_PRC64
-#define E1000_82542_PRC127 E1000_PRC127
-#define E1000_82542_PRC255 E1000_PRC255
-#define E1000_82542_PRC511 E1000_PRC511
-#define E1000_82542_PRC1023 E1000_PRC1023
-#define E1000_82542_PRC1522 E1000_PRC1522
-#define E1000_82542_GPRC E1000_GPRC
-#define E1000_82542_BPRC E1000_BPRC
-#define E1000_82542_MPRC E1000_MPRC
-#define E1000_82542_GPTC E1000_GPTC
-#define E1000_82542_GORCL E1000_GORCL
-#define E1000_82542_GORCH E1000_GORCH
-#define E1000_82542_GOTCL E1000_GOTCL
-#define E1000_82542_GOTCH E1000_GOTCH
-#define E1000_82542_RNBC E1000_RNBC
-#define E1000_82542_RUC E1000_RUC
-#define E1000_82542_RFC E1000_RFC
-#define E1000_82542_ROC E1000_ROC
-#define E1000_82542_RJC E1000_RJC
-#define E1000_82542_MGTPRC E1000_MGTPRC
-#define E1000_82542_MGTPDC E1000_MGTPDC
-#define E1000_82542_MGTPTC E1000_MGTPTC
-#define E1000_82542_TORL E1000_TORL
-#define E1000_82542_TORH E1000_TORH
-#define E1000_82542_TOTL E1000_TOTL
-#define E1000_82542_TOTH E1000_TOTH
-#define E1000_82542_TPR E1000_TPR
-#define E1000_82542_TPT E1000_TPT
-#define E1000_82542_PTC64 E1000_PTC64
-#define E1000_82542_PTC127 E1000_PTC127
-#define E1000_82542_PTC255 E1000_PTC255
-#define E1000_82542_PTC511 E1000_PTC511
-#define E1000_82542_PTC1023 E1000_PTC1023
-#define E1000_82542_PTC1522 E1000_PTC1522
-#define E1000_82542_MPTC E1000_MPTC
-#define E1000_82542_BPTC E1000_BPTC
-#define E1000_82542_TSCTC E1000_TSCTC
-#define E1000_82542_TSCTFC E1000_TSCTFC
-#define E1000_82542_RXCSUM E1000_RXCSUM
-#define E1000_82542_WUC E1000_WUC
-#define E1000_82542_WUFC E1000_WUFC
-#define E1000_82542_WUS E1000_WUS
-#define E1000_82542_MANC E1000_MANC
-#define E1000_82542_IPAV E1000_IPAV
-#define E1000_82542_IP4AT E1000_IP4AT
-#define E1000_82542_IP6AT E1000_IP6AT
-#define E1000_82542_WUPL E1000_WUPL
-#define E1000_82542_WUPM E1000_WUPM
-#define E1000_82542_FFLT E1000_FFLT
-#define E1000_82542_FFMT E1000_FFMT
-#define E1000_82542_FFVT E1000_FFVT
-
-/* Statistics counters collected by the MAC */
-struct e1000_hw_stats {
- uint64_t crcerrs;
- uint64_t algnerrc;
- uint64_t symerrs;
- uint64_t rxerrc;
- uint64_t mpc;
- uint64_t scc;
- uint64_t ecol;
- uint64_t mcc;
- uint64_t latecol;
- uint64_t colc;
- uint64_t dc;
- uint64_t tncrs;
- uint64_t sec;
- uint64_t cexterr;
- uint64_t rlec;
- uint64_t xonrxc;
- uint64_t xontxc;
- uint64_t xoffrxc;
- uint64_t xofftxc;
- uint64_t fcruc;
- uint64_t prc64;
- uint64_t prc127;
- uint64_t prc255;
- uint64_t prc511;
- uint64_t prc1023;
- uint64_t prc1522;
- uint64_t gprc;
- uint64_t bprc;
- uint64_t mprc;
- uint64_t gptc;
- uint64_t gorcl;
- uint64_t gorch;
- uint64_t gotcl;
- uint64_t gotch;
- uint64_t rnbc;
- uint64_t ruc;
- uint64_t rfc;
- uint64_t roc;
- uint64_t rjc;
- uint64_t mgprc;
- uint64_t mgpdc;
- uint64_t mgptc;
- uint64_t torl;
- uint64_t torh;
- uint64_t totl;
- uint64_t toth;
- uint64_t tpr;
- uint64_t tpt;
- uint64_t ptc64;
- uint64_t ptc127;
- uint64_t ptc255;
- uint64_t ptc511;
- uint64_t ptc1023;
- uint64_t ptc1522;
- uint64_t mptc;
- uint64_t bptc;
- uint64_t tsctc;
- uint64_t tsctfc;
-};
-
-struct e1000_eeprom_info {
- e1000_eeprom_type type;
- uint16_t word_size;
- uint16_t opcode_bits;
- uint16_t address_bits;
- uint16_t delay_usec;
- uint16_t page_size;
- boolean_t use_eerd;
- boolean_t use_eewr;
-};
-
-typedef enum {
- e1000_smart_speed_default = 0,
- e1000_smart_speed_on,
- e1000_smart_speed_off
-} e1000_smart_speed;
-
-typedef enum {
- e1000_dsp_config_disabled = 0,
- e1000_dsp_config_enabled,
- e1000_dsp_config_activated,
- e1000_dsp_config_undefined = 0xFF
-} e1000_dsp_config;
-
-typedef enum {
- e1000_ms_hw_default = 0,
- e1000_ms_force_master,
- e1000_ms_force_slave,
- e1000_ms_auto
-} e1000_ms_type;
-
-typedef enum {
- e1000_ffe_config_enabled = 0,
- e1000_ffe_config_active,
- e1000_ffe_config_blocked
-} e1000_ffe_config;
-
-
-/* Structure containing variables used by the shared code (e1000_hw.c) */
-struct e1000_hw {
- pci_dev_t pdev;
- uint8_t *hw_addr;
- e1000_mac_type mac_type;
- e1000_phy_type phy_type;
- uint32_t phy_init_script;
- uint32_t txd_cmd;
- e1000_media_type media_type;
- e1000_lan_loc lan_loc;
- e1000_fc_type fc;
- e1000_bus_type bus_type;
-#if 0
- e1000_bus_speed bus_speed;
- e1000_bus_width bus_width;
- uint32_t io_base;
-#endif
- uint32_t asf_firmware_present;
- uint32_t eeprom_semaphore_present;
- uint32_t swfw_sync_present;
- uint32_t swfwhw_semaphore_present;
- struct e1000_eeprom_info eeprom;
- e1000_ms_type master_slave;
- e1000_ms_type original_master_slave;
- e1000_ffe_config ffe_config_state;
- uint32_t phy_id;
- uint32_t phy_revision;
- uint32_t phy_addr;
- uint32_t original_fc;
- uint32_t txcw;
- uint32_t autoneg_failed;
-#if 0
- uint32_t max_frame_size;
- uint32_t min_frame_size;
- uint32_t mc_filter_type;
- uint32_t num_mc_addrs;
- uint32_t collision_delta;
- uint32_t tx_packet_delta;
- uint32_t ledctl_default;
- uint32_t ledctl_mode1;
- uint32_t ledctl_mode2;
-#endif
- uint16_t autoneg_advertised;
- uint16_t pci_cmd_word;
- uint16_t fc_high_water;
- uint16_t fc_low_water;
- uint16_t fc_pause_time;
-#if 0
- uint16_t current_ifs_val;
- uint16_t ifs_min_val;
- uint16_t ifs_max_val;
- uint16_t ifs_step_size;
- uint16_t ifs_ratio;
-#endif
- uint16_t device_id;
- uint16_t vendor_id;
- uint16_t subsystem_id;
- uint16_t subsystem_vendor_id;
- uint8_t revision_id;
- uint8_t autoneg;
- uint8_t mdix;
- uint8_t forced_speed_duplex;
- uint8_t wait_autoneg_complete;
- uint8_t dma_fairness;
-#if 0
- uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
-#endif
- boolean_t disable_polarity_correction;
- boolean_t speed_downgraded;
- boolean_t get_link_status;
- boolean_t tbi_compatibility_en;
- boolean_t tbi_compatibility_on;
- boolean_t fc_strict_ieee;
- boolean_t fc_send_xon;
- boolean_t report_tx_early;
- boolean_t phy_reset_disable;
- boolean_t initialize_hw_bits_disable;
-#if 0
- boolean_t adaptive_ifs;
- boolean_t ifs_params_forced;
- boolean_t in_ifs_mode;
-#endif
- e1000_smart_speed smart_speed;
- e1000_dsp_config dsp_config_state;
-};
-
-#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */
-#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */
-#define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM
- read/write registers */
-#define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
-#define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start
- operation */
-#define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
-#define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write
- complete */
-#define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */
-#define EEPROM_RESERVED_WORD 0xFFFF
-
-/* Register Bit Masks */
-/* Device Control */
-#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
-#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
-#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
-#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
-#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
-#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
-#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
-#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
-#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
-#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
-#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
-#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
-#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
-#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
-#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
-#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
-#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
-#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
-#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
-#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
-#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
-#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
-#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
-#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
-#define E1000_CTRL_RST 0x04000000 /* Global reset */
-#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
-#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
-#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
-#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
-#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
-
-/* Device Status */
-#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
-#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
-#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
-#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
-#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
-#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
-#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
-#define E1000_STATUS_SPEED_MASK 0x000000C0
-#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
-#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
-#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
-#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
-#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
-#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
-#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
-#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
-#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
-
-/* Constants used to intrepret the masked PCI-X bus speed. */
-#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
-#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
-#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
-
-/* EEPROM/Flash Control */
-#define E1000_EECD_SK 0x00000001 /* EEPROM Clock */
-#define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */
-#define E1000_EECD_DI 0x00000004 /* EEPROM Data In */
-#define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */
-#define E1000_EECD_FWE_MASK 0x00000030
-#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
-#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
-#define E1000_EECD_FWE_SHIFT 4
-#define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
-#define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */
-#define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */
-#define E1000_EECD_PRES 0x00000100 /* EEPROM Present */
-#define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type
- * (0-small, 1-large) */
-
-#define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
-#ifndef E1000_EEPROM_GRANT_ATTEMPTS
-#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
-#endif
-#define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */
-#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */
-#define E1000_EECD_SIZE_EX_SHIFT 11
-#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */
-#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
-#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
-#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
-#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
-#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
-#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
-#define E1000_EECD_SECVAL_SHIFT 22
-#define E1000_STM_OPCODE 0xDB00
-#define E1000_HICR_FW_RESET 0xC0
-
-#define E1000_SHADOW_RAM_WORDS 2048
-#define E1000_ICH_NVM_SIG_WORD 0x13
-#define E1000_ICH_NVM_SIG_MASK 0xC0
-
-/* EEPROM Read */
-#define E1000_EERD_START 0x00000001 /* Start Read */
-#define E1000_EERD_DONE 0x00000010 /* Read Done */
-#define E1000_EERD_ADDR_SHIFT 8
-#define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */
-#define E1000_EERD_DATA_SHIFT 16
-#define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */
-
-/* EEPROM Commands - Microwire */
-#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */
-#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */
-#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */
-#define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */
-#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */
-
-/* EEPROM Commands - SPI */
-#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
-#define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
-#define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
-#define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
-#define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */
-#define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */
-#define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */
-#define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */
-#define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
-#define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
-#define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
-
-/* EEPROM Size definitions */
-#define EEPROM_WORD_SIZE_SHIFT 6
-#define EEPROM_SIZE_SHIFT 10
-#define EEPROM_SIZE_MASK 0x1C00
-
-/* EEPROM Word Offsets */
-#define EEPROM_COMPAT 0x0003
-#define EEPROM_ID_LED_SETTINGS 0x0004
-#define EEPROM_VERSION 0x0005
-#define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude
- adjustment. */
-#define EEPROM_PHY_CLASS_WORD 0x0007
-#define EEPROM_INIT_CONTROL1_REG 0x000A
-#define EEPROM_INIT_CONTROL2_REG 0x000F
-#define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010
-#define EEPROM_INIT_CONTROL3_PORT_B 0x0014
-#define EEPROM_INIT_3GIO_3 0x001A
-#define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020
-#define EEPROM_INIT_CONTROL3_PORT_A 0x0024
-#define EEPROM_CFG 0x0012
-#define EEPROM_FLASH_VERSION 0x0032
-#define EEPROM_CHECKSUM_REG 0x003F
-
-#define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */
-#define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */
-
-/* Extended Device Control */
-#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
-#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
-#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
-#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
-#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
-#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable
- Pin 4 */
-#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable
- Pin 5 */
-#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
-#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
-#define E1000_CTRL_EXT_SWDPIN6 0x00000040 /* SWDPIN 6 value */
-#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
-#define E1000_CTRL_EXT_SWDPIN7 0x00000080 /* SWDPIN 7 value */
-#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
-#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
-#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
-#define E1000_CTRL_EXT_SWDPIO6 0x00000400 /* SWDPIN 6 Input or output */
-#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */
-#define E1000_CTRL_EXT_SWDPIO7 0x00000800 /* SWDPIN 7 Input or output */
-#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
-#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
-#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
-#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
-#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
-#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
-#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
-#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
-#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
-#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
-#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
-#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
-#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
-
-/* MDI Control */
-#define E1000_MDIC_DATA_MASK 0x0000FFFF
-#define E1000_MDIC_REG_MASK 0x001F0000
-#define E1000_MDIC_REG_SHIFT 16
-#define E1000_MDIC_PHY_MASK 0x03E00000
-#define E1000_MDIC_PHY_SHIFT 21
-#define E1000_MDIC_OP_WRITE 0x04000000
-#define E1000_MDIC_OP_READ 0x08000000
-#define E1000_MDIC_READY 0x10000000
-#define E1000_MDIC_INT_EN 0x20000000
-#define E1000_MDIC_ERROR 0x40000000
-
-#define E1000_PHY_CTRL_SPD_EN 0x00000001
-#define E1000_PHY_CTRL_D0A_LPLU 0x00000002
-#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
-#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
-#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
-#define E1000_PHY_CTRL_B2B_EN 0x00000080
-/* LED Control */
-#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
-#define E1000_LEDCTL_LED0_MODE_SHIFT 0
-#define E1000_LEDCTL_LED0_IVRT 0x00000040
-#define E1000_LEDCTL_LED0_BLINK 0x00000080
-#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
-#define E1000_LEDCTL_LED1_MODE_SHIFT 8
-#define E1000_LEDCTL_LED1_IVRT 0x00004000
-#define E1000_LEDCTL_LED1_BLINK 0x00008000
-#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
-#define E1000_LEDCTL_LED2_MODE_SHIFT 16
-#define E1000_LEDCTL_LED2_IVRT 0x00400000
-#define E1000_LEDCTL_LED2_BLINK 0x00800000
-#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
-#define E1000_LEDCTL_LED3_MODE_SHIFT 24
-#define E1000_LEDCTL_LED3_IVRT 0x40000000
-#define E1000_LEDCTL_LED3_BLINK 0x80000000
-
-#define E1000_LEDCTL_MODE_LINK_10_1000 0x0
-#define E1000_LEDCTL_MODE_LINK_100_1000 0x1
-#define E1000_LEDCTL_MODE_LINK_UP 0x2
-#define E1000_LEDCTL_MODE_ACTIVITY 0x3
-#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
-#define E1000_LEDCTL_MODE_LINK_10 0x5
-#define E1000_LEDCTL_MODE_LINK_100 0x6
-#define E1000_LEDCTL_MODE_LINK_1000 0x7
-#define E1000_LEDCTL_MODE_PCIX_MODE 0x8
-#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
-#define E1000_LEDCTL_MODE_COLLISION 0xA
-#define E1000_LEDCTL_MODE_BUS_SPEED 0xB
-#define E1000_LEDCTL_MODE_BUS_SIZE 0xC
-#define E1000_LEDCTL_MODE_PAUSED 0xD
-#define E1000_LEDCTL_MODE_LED_ON 0xE
-#define E1000_LEDCTL_MODE_LED_OFF 0xF
-
-/* Receive Address */
-#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
-
-/* Interrupt Cause Read */
-#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
-#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
-#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
-#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
-#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
-#define E1000_ICR_RXO 0x00000040 /* rx overrun */
-#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
-#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
-#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */
-#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
-#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
-#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
-#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
-#define E1000_ICR_TXD_LOW 0x00008000
-#define E1000_ICR_SRPD 0x00010000
-
-/* Interrupt Cause Set */
-#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
-#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
-#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
-#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
-#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
-#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
-#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
-#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
-#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
-#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
-#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
-#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
-#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
-#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
-#define E1000_ICS_SRPD E1000_ICR_SRPD
-
-/* Interrupt Mask Set */
-#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
-#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
-#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
-#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
-#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
-#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
-#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
-#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
-#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
-#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
-#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
-#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
-#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
-#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
-#define E1000_IMS_SRPD E1000_ICR_SRPD
-
-/* Interrupt Mask Clear */
-#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
-#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
-#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */
-#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
-#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
-#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
-#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
-#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */
-#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
-#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
-#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
-#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
-#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
-#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
-#define E1000_IMC_SRPD E1000_ICR_SRPD
-
-/* Receive Control */
-#define E1000_RCTL_RST 0x00000001 /* Software reset */
-#define E1000_RCTL_EN 0x00000002 /* enable */
-#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
-#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
-#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
-#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
-#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
-#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
-#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
-#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
-#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
-#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
-#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
-#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
-#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
-#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
-#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
-#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
-#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
-#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
-/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
-#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
-#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
-#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
-#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
-/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
-#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
-#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
-#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
-#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
-#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
-#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
-#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
-#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
-#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
-
-/* SW_W_SYNC definitions */
-#define E1000_SWFW_EEP_SM 0x0001
-#define E1000_SWFW_PHY0_SM 0x0002
-#define E1000_SWFW_PHY1_SM 0x0004
-#define E1000_SWFW_MAC_CSR_SM 0x0008
-
-/* Receive Descriptor */
-#define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */
-#define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */
-#define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */
-#define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */
-#define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */
-
-/* Flow Control */
-#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
-#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
-#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
-#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
-
-/* Receive Descriptor Control */
-#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
-#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
-#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
-#define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
-
-/* Transmit Descriptor Control */
-#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
-#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
-#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
-#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
-#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
-#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
-#define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc.
- still to be processed. */
-
-/* Transmit Configuration Word */
-#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
-#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
-#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
-#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
-#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
-#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
-#define E1000_TXCW_NP 0x00008000 /* TXCW next page */
-#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
-#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
-#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
-
-/* Receive Configuration Word */
-#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
-#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
-#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
-#define E1000_RXCW_CC 0x10000000 /* Receive config change */
-#define E1000_RXCW_C 0x20000000 /* Receive config */
-#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
-#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
-
-/* Transmit Control */
-#define E1000_TCTL_RST 0x00000001 /* software reset */
-#define E1000_TCTL_EN 0x00000002 /* enable tx */
-#define E1000_TCTL_BCE 0x00000004 /* busy check enable */
-#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
-#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
-#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
-#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
-#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
-#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
-#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
-#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
-
-/* Receive Checksum Control */
-#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
-#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
-#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
-#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
-
-/* Definitions for power management and wakeup registers */
-/* Wake Up Control */
-#define E1000_WUC_APME 0x00000001 /* APM Enable */
-#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
-#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
-#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
-
-/* Wake Up Filter Control */
-#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
-#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
-#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
-#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
-#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
-#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
-#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
-#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
-#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
-#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
-#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
-#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
-#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
-#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
-#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
-
-/* Wake Up Status */
-#define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */
-#define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */
-#define E1000_WUS_EX 0x00000004 /* Directed Exact Received */
-#define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */
-#define E1000_WUS_BC 0x00000010 /* Broadcast Received */
-#define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */
-#define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */
-#define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */
-#define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */
-#define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */
-#define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */
-#define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */
-#define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
-
-/* Management Control */
-#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
-#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
-#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
-#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
-#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
-#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
-#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
-#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
-#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
-#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery
- * Filtering */
-#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
-#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
-#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
-#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
-#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
-#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
-#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
-#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
-#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
-
-#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
-#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
-
-/* Wake Up Packet Length */
-#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
-
-#define E1000_MDALIGN 4096
-
-/* EEPROM Commands */
-#define EEPROM_READ_OPCODE 0x6 /* EERPOM read opcode */
-#define EEPROM_WRITE_OPCODE 0x5 /* EERPOM write opcode */
-#define EEPROM_ERASE_OPCODE 0x7 /* EERPOM erase opcode */
-#define EEPROM_EWEN_OPCODE 0x13 /* EERPOM erase/write enable */
-#define EEPROM_EWDS_OPCODE 0x10 /* EERPOM erast/write disable */
-
-/* EEPROM Word Offsets */
-#define EEPROM_COMPAT 0x0003
-#define EEPROM_ID_LED_SETTINGS 0x0004
-#define EEPROM_INIT_CONTROL1_REG 0x000A
-#define EEPROM_INIT_CONTROL2_REG 0x000F
-#define EEPROM_FLASH_VERSION 0x0032
-#define EEPROM_CHECKSUM_REG 0x003F
-
-/* Word definitions for ID LED Settings */
-#define ID_LED_RESERVED_0000 0x0000
-#define ID_LED_RESERVED_FFFF 0xFFFF
-#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
- (ID_LED_OFF1_OFF2 << 8) | \
- (ID_LED_DEF1_DEF2 << 4) | \
- (ID_LED_DEF1_DEF2))
-#define ID_LED_DEF1_DEF2 0x1
-#define ID_LED_DEF1_ON2 0x2
-#define ID_LED_DEF1_OFF2 0x3
-#define ID_LED_ON1_DEF2 0x4
-#define ID_LED_ON1_ON2 0x5
-#define ID_LED_ON1_OFF2 0x6
-#define ID_LED_OFF1_DEF2 0x7
-#define ID_LED_OFF1_ON2 0x8
-#define ID_LED_OFF1_OFF2 0x9
-
-/* Mask bits for fields in Word 0x03 of the EEPROM */
-#define EEPROM_COMPAT_SERVER 0x0400
-#define EEPROM_COMPAT_CLIENT 0x0200
-
-/* Mask bits for fields in Word 0x0a of the EEPROM */
-#define EEPROM_WORD0A_ILOS 0x0010
-#define EEPROM_WORD0A_SWDPIO 0x01E0
-#define EEPROM_WORD0A_LRST 0x0200
-#define EEPROM_WORD0A_FD 0x0400
-#define EEPROM_WORD0A_66MHZ 0x0800
-
-/* Mask bits for fields in Word 0x0f of the EEPROM */
-#define EEPROM_WORD0F_PAUSE_MASK 0x3000
-#define EEPROM_WORD0F_PAUSE 0x1000
-#define EEPROM_WORD0F_ASM_DIR 0x2000
-#define EEPROM_WORD0F_ANE 0x0800
-#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
-
-/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
-#define EEPROM_SUM 0xBABA
-
-/* EEPROM Map defines (WORD OFFSETS)*/
-#define EEPROM_NODE_ADDRESS_BYTE_0 0
-#define EEPROM_PBA_BYTE_1 8
-
-/* EEPROM Map Sizes (Byte Counts) */
-#define PBA_SIZE 4
-
-/* Collision related configuration parameters */
-#define E1000_COLLISION_THRESHOLD 0xF
-#define E1000_CT_SHIFT 4
-#define E1000_COLLISION_DISTANCE 63
-#define E1000_COLLISION_DISTANCE_82542 64
-#define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
-#define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
-#define E1000_GB_HDX_COLLISION_DISTANCE 512
-#define E1000_COLD_SHIFT 12
-
-/* The number of Transmit and Receive Descriptors must be a multiple of 8 */
-#define REQ_TX_DESCRIPTOR_MULTIPLE 8
-#define REQ_RX_DESCRIPTOR_MULTIPLE 8
-
-/* Default values for the transmit IPG register */
-#define DEFAULT_82542_TIPG_IPGT 10
-#define DEFAULT_82543_TIPG_IPGT_FIBER 9
-#define DEFAULT_82543_TIPG_IPGT_COPPER 8
-
-#define E1000_TIPG_IPGT_MASK 0x000003FF
-#define E1000_TIPG_IPGR1_MASK 0x000FFC00
-#define E1000_TIPG_IPGR2_MASK 0x3FF00000
-
-#define DEFAULT_82542_TIPG_IPGR1 2
-#define DEFAULT_82543_TIPG_IPGR1 8
-#define E1000_TIPG_IPGR1_SHIFT 10
-
-#define DEFAULT_82542_TIPG_IPGR2 10
-#define DEFAULT_82543_TIPG_IPGR2 6
-#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
-#define E1000_TIPG_IPGR2_SHIFT 20
-
-#define E1000_TXDMAC_DPP 0x00000001
-
-/* Adaptive IFS defines */
-#define TX_THRESHOLD_START 8
-#define TX_THRESHOLD_INCREMENT 10
-#define TX_THRESHOLD_DECREMENT 1
-#define TX_THRESHOLD_STOP 190
-#define TX_THRESHOLD_DISABLE 0
-#define TX_THRESHOLD_TIMER_MS 10000
-#define MIN_NUM_XMITS 1000
-#define IFS_MAX 80
-#define IFS_STEP 10
-#define IFS_MIN 40
-#define IFS_RATIO 4
-
-/* PBA constants */
-#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
-#define E1000_PBA_24K 0x0018
-#define E1000_PBA_38K 0x0026
-#define E1000_PBA_40K 0x0028
-#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
-
-/* Flow Control Constants */
-#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
-#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
-#define FLOW_CONTROL_TYPE 0x8808
-
-/* The historical defaults for the flow control values are given below. */
-#define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */
-#define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */
-#define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */
-
-/* Flow Control High-Watermark: 43464 bytes */
-#define E1000_FC_HIGH_THRESH 0xA9C8
-/* Flow Control Low-Watermark: 43456 bytes */
-#define E1000_FC_LOW_THRESH 0xA9C0
-/* Flow Control Pause Time: 858 usec */
-#define E1000_FC_PAUSE_TIME 0x0680
-
-/* PCIX Config space */
-#define PCIX_COMMAND_REGISTER 0xE6
-#define PCIX_STATUS_REGISTER_LO 0xE8
-#define PCIX_STATUS_REGISTER_HI 0xEA
-
-#define PCIX_COMMAND_MMRBC_MASK 0x000C
-#define PCIX_COMMAND_MMRBC_SHIFT 0x2
-#define PCIX_STATUS_HI_MMRBC_MASK 0x0060
-#define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
-#define PCIX_STATUS_HI_MMRBC_4K 0x3
-#define PCIX_STATUS_HI_MMRBC_2K 0x2
-
-/* The number of bits that we need to shift right to move the "pause"
- * bits from the EEPROM (bits 13:12) to the "pause" (bits 8:7) field
- * in the TXCW register
- */
-#define PAUSE_SHIFT 5
-
-/* The number of bits that we need to shift left to move the "SWDPIO"
- * bits from the EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field
- * in the CTRL register
- */
-#define SWDPIO_SHIFT 17
-
-/* The number of bits that we need to shift left to move the "SWDPIO_EXT"
- * bits from the EEPROM word F (bits 7:4) to the bits 11:8 of The
- * Extended CTRL register.
- * in the CTRL register
- */
-#define SWDPIO__EXT_SHIFT 4
-
-/* The number of bits that we need to shift left to move the "ILOS"
- * bit from the EEPROM (bit 4) to the "ILOS" (bit 7) field
- * in the CTRL register
- */
-#define ILOS_SHIFT 3
-
-#define RECEIVE_BUFFER_ALIGN_SIZE (256)
-
-/* The number of milliseconds we wait for auto-negotiation to complete */
-#define LINK_UP_TIMEOUT 500
-
-#define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
-
-/* The carrier extension symbol, as received by the NIC. */
-#define CARRIER_EXTENSION 0x0F
-
-/* TBI_ACCEPT macro definition:
- *
- * This macro requires:
- * adapter = a pointer to struct e1000_hw
- * status = the 8 bit status field of the RX descriptor with EOP set
- * error = the 8 bit error field of the RX descriptor with EOP set
- * length = the sum of all the length fields of the RX descriptors that
- * make up the current frame
- * last_byte = the last byte of the frame DMAed by the hardware
- * max_frame_length = the maximum frame length we want to accept.
- * min_frame_length = the minimum frame length we want to accept.
- *
- * This macro is a conditional that should be used in the interrupt
- * handler's Rx processing routine when RxErrors have been detected.
- *
- * Typical use:
- * ...
- * if (TBI_ACCEPT) {
- * accept_frame = TRUE;
- * e1000_tbi_adjust_stats(adapter, MacAddress);
- * frame_length--;
- * } else {
- * accept_frame = FALSE;
- * }
- * ...
- */
-
-#define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
- ((adapter)->tbi_compatibility_on && \
- (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
- ((last_byte) == CARRIER_EXTENSION) && \
- (((status) & E1000_RXD_STAT_VP) ? \
- (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
- ((length) <= ((adapter)->max_frame_size + 1))) : \
- (((length) > (adapter)->min_frame_size) && \
- ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
-
-/* Structures, enums, and macros for the PHY */
-
-/* Bit definitions for the Management Data IO (MDIO) and Management Data
- * Clock (MDC) pins in the Device Control Register.
- */
-#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
-#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
-#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
-#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
-#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
-#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
-#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
-#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
-
-/* PHY 1000 MII Register/Bit Definitions */
-/* PHY Registers defined by IEEE */
-#define PHY_CTRL 0x00 /* Control Register */
-#define PHY_STATUS 0x01 /* Status Regiser */
-#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
-#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
-#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
-#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
-#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
-#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
-#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
-#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
-#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
-#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
-
-/* M88E1000 Specific Registers */
-#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
-#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
-#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
-#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
-#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
-#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
-
-#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
-#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
-
-#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
-
-/* M88EC018 Rev 2 specific DownShift settings */
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00
-
-/* IGP01E1000 specifics */
-#define IGP01E1000_IEEE_REGS_PAGE 0x0000
-#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
-#define IGP01E1000_IEEE_FORCE_GIGA 0x0140
-
-/* IGP01E1000 Specific Registers */
-#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
-#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
-#define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */
-#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
-#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */
-#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */
-#define IGP02E1000_PHY_POWER_MGMT 0x19
-#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */
-
-/* IGP01E1000 AGC Registers - stores the cable length values*/
-#define IGP01E1000_PHY_AGC_A 0x1172
-#define IGP01E1000_PHY_AGC_B 0x1272
-#define IGP01E1000_PHY_AGC_C 0x1472
-#define IGP01E1000_PHY_AGC_D 0x1872
-
-/* IGP01E1000 Specific Port Config Register - R/W */
-#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
-#define IGP01E1000_PSCFR_PRE_EN 0x0020
-#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
-#define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100
-#define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400
-#define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000
-/* IGP02E1000 AGC Registers for cable length values */
-#define IGP02E1000_PHY_AGC_A 0x11B1
-#define IGP02E1000_PHY_AGC_B 0x12B1
-#define IGP02E1000_PHY_AGC_C 0x14B1
-#define IGP02E1000_PHY_AGC_D 0x18B1
-
-#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
-#define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in
- non-D0a modes */
-#define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in
- D0a mode */
-
-/* IGP01E1000 DSP Reset Register */
-#define IGP01E1000_PHY_DSP_RESET 0x1F33
-#define IGP01E1000_PHY_DSP_SET 0x1F71
-#define IGP01E1000_PHY_DSP_FFE 0x1F35
-
-#define IGP01E1000_PHY_CHANNEL_NUM 4
-#define IGP02E1000_PHY_CHANNEL_NUM 4
-
-#define IGP01E1000_PHY_AGC_PARAM_A 0x1171
-#define IGP01E1000_PHY_AGC_PARAM_B 0x1271
-#define IGP01E1000_PHY_AGC_PARAM_C 0x1471
-#define IGP01E1000_PHY_AGC_PARAM_D 0x1871
-
-#define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000
-#define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000
-
-#define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890
-#define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000
-#define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004
-#define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069
-
-#define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A
-/* IGP01E1000 PCS Initialization register - stores the polarity status when
- * speed = 1000 Mbps. */
-#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
-#define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5
-
-#define IGP01E1000_ANALOG_REGS_PAGE 0x20C0
-
-/* IGP01E1000 GMII FIFO Register */
-#define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed
- * on Link-Up */
-#define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */
-
-/* IGP01E1000 Analog Register */
-#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
-#define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0
-#define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC
-#define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE
-
-#define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000
-#define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80
-#define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070
-#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100
-#define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
-
-#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040
-#define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010
-#define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080
-#define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500
-
-/* IGP01E1000 Specific Port Control Register - R/W */
-#define IGP01E1000_PSCR_TP_LOOPBACK 0x0010
-#define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200
-#define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400
-#define IGP01E1000_PSCR_FLIP_CHIP 0x0800
-#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
-#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */
-/* GG82563 PHY Specific Status Register (Page 0, Register 16 */
-#define GG82563_PSCR_DISABLE_JABBER 0x0001 /* 1=Disable Jabber */
-#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Polarity Reversal
- Disabled */
-#define GG82563_PSCR_POWER_DOWN 0x0004 /* 1=Power Down */
-#define GG82563_PSCR_COPPER_TRANSMITER_DISABLE 0x0008 /* 1=Transmitter
- Disabled */
-#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
-#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI
- configuration */
-#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX
- configuration */
-#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Automatic
- crossover */
-#define GG82563_PSCR_ENALBE_EXTENDED_DISTANCE 0x0080 /* 1=Enable Extended
- Distance */
-#define GG82563_PSCR_ENERGY_DETECT_MASK 0x0300
-#define GG82563_PSCR_ENERGY_DETECT_OFF 0x0000 /* 00,01=Off */
-#define GG82563_PSCR_ENERGY_DETECT_RX 0x0200 /* 10=Sense on Rx only
- (Energy Detect) */
-#define GG82563_PSCR_ENERGY_DETECT_RX_TM 0x0300 /* 11=Sense and Tx NLP */
-#define GG82563_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force Link Good */
-#define GG82563_PSCR_DOWNSHIFT_ENABLE 0x0800 /* 1=Enable Downshift */
-#define GG82563_PSCR_DOWNSHIFT_COUNTER_MASK 0x7000
-#define GG82563_PSCR_DOWNSHIFT_COUNTER_SHIFT 12
-
-/* PHY Specific Status Register (Page 0, Register 17) */
-#define GG82563_PSSR_JABBER 0x0001 /* 1=Jabber */
-#define GG82563_PSSR_POLARITY 0x0002 /* 1=Polarity Reversed */
-#define GG82563_PSSR_LINK 0x0008 /* 1=Link is Up */
-#define GG82563_PSSR_ENERGY_DETECT 0x0010 /* 1=Sleep, 0=Active */
-#define GG82563_PSSR_DOWNSHIFT 0x0020 /* 1=Downshift */
-#define GG82563_PSSR_CROSSOVER_STATUS 0x0040 /* 1=MDIX, 0=MDI */
-#define GG82563_PSSR_RX_PAUSE_ENABLED 0x0100 /* 1=Receive Pause Enabled */
-#define GG82563_PSSR_TX_PAUSE_ENABLED 0x0200 /* 1=Transmit Pause Enabled */
-#define GG82563_PSSR_LINK_UP 0x0400 /* 1=Link Up */
-#define GG82563_PSSR_SPEED_DUPLEX_RESOLVED 0x0800 /* 1=Resolved */
-#define GG82563_PSSR_PAGE_RECEIVED 0x1000 /* 1=Page Received */
-#define GG82563_PSSR_DUPLEX 0x2000 /* 1-Full-Duplex */
-#define GG82563_PSSR_SPEED_MASK 0xC000
-#define GG82563_PSSR_SPEED_10MBPS 0x0000 /* 00=10Mbps */
-#define GG82563_PSSR_SPEED_100MBPS 0x4000 /* 01=100Mbps */
-#define GG82563_PSSR_SPEED_1000MBPS 0x8000 /* 10=1000Mbps */
-
-/* PHY Specific Status Register 2 (Page 0, Register 19) */
-#define GG82563_PSSR2_JABBER 0x0001 /* 1=Jabber */
-#define GG82563_PSSR2_POLARITY_CHANGED 0x0002 /* 1=Polarity Changed */
-#define GG82563_PSSR2_ENERGY_DETECT_CHANGED 0x0010 /* 1=Energy Detect Changed */
-#define GG82563_PSSR2_DOWNSHIFT_INTERRUPT 0x0020 /* 1=Downshift Detected */
-#define GG82563_PSSR2_MDI_CROSSOVER_CHANGE 0x0040 /* 1=Crossover Changed */
-#define GG82563_PSSR2_FALSE_CARRIER 0x0100 /* 1=False Carrier */
-#define GG82563_PSSR2_SYMBOL_ERROR 0x0200 /* 1=Symbol Error */
-#define GG82563_PSSR2_LINK_STATUS_CHANGED 0x0400 /* 1=Link Status Changed */
-#define GG82563_PSSR2_AUTO_NEG_COMPLETED 0x0800 /* 1=Auto-Neg Completed */
-#define GG82563_PSSR2_PAGE_RECEIVED 0x1000 /* 1=Page Received */
-#define GG82563_PSSR2_DUPLEX_CHANGED 0x2000 /* 1=Duplex Changed */
-#define GG82563_PSSR2_SPEED_CHANGED 0x4000 /* 1=Speed Changed */
-#define GG82563_PSSR2_AUTO_NEG_ERROR 0x8000 /* 1=Auto-Neg Error */
-
-/* PHY Specific Control Register 2 (Page 0, Register 26) */
-#define GG82563_PSCR2_10BT_POLARITY_FORCE 0x0002 /* 1=Force Negative
- Polarity */
-#define GG82563_PSCR2_1000MB_TEST_SELECT_MASK 0x000C
-#define GG82563_PSCR2_1000MB_TEST_SELECT_NORMAL 0x0000 /* 00,01=Normal
- Operation */
-#define GG82563_PSCR2_1000MB_TEST_SELECT_112NS 0x0008 /* 10=Select 112ns
- Sequence */
-#define GG82563_PSCR2_1000MB_TEST_SELECT_16NS 0x000C /* 11=Select 16ns
- Sequence */
-#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse
- Auto-Negotiation */
-#define GG82563_PSCR2_1000BT_DISABLE 0x4000 /* 1=Disable
- 1000BASE-T */
-#define GG82563_PSCR2_TRANSMITER_TYPE_MASK 0x8000
-#define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_B 0x0000 /* 0=Class B */
-#define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_A 0x8000 /* 1=Class A */
-
-/* MAC Specific Control Register (Page 2, Register 21) */
-/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
-#define GG82563_MSCR_TX_CLK_MASK 0x0007
-#define GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ 0x0004
-#define GG82563_MSCR_TX_CLK_100MBPS_25MHZ 0x0005
-#define GG82563_MSCR_TX_CLK_1000MBPS_2_5MHZ 0x0006
-#define GG82563_MSCR_TX_CLK_1000MBPS_25MHZ 0x0007
-
-#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
-
-/* DSP Distance Register (Page 5, Register 26) */
-#define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M;
- 1 = 50-80M;
- 2 = 80-110M;
- 3 = 110-140M;
- 4 = >140M */
-
-/* Kumeran Mode Control Register (Page 193, Register 16) */
-#define GG82563_KMCR_PHY_LEDS_EN 0x0020 /* 1=PHY LEDs,
- 0=Kumeran Inband LEDs */
-#define GG82563_KMCR_FORCE_LINK_UP 0x0040 /* 1=Force Link Up */
-#define GG82563_KMCR_SUPPRESS_SGMII_EPD_EXT 0x0080
-#define GG82563_KMCR_MDIO_BUS_SPEED_SELECT_MASK 0x0400
-#define GG82563_KMCR_MDIO_BUS_SPEED_SELECT 0x0400 /* 1=6.25MHz,
- 0=0.8MHz */
-#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
-
-/* Power Management Control Register (Page 193, Register 20) */
-#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 /* 1=Enalbe SERDES
- Electrical Idle */
-#define GG82563_PMCR_DISABLE_PORT 0x0002 /* 1=Disable Port */
-#define GG82563_PMCR_DISABLE_SERDES 0x0004 /* 1=Disable SERDES */
-#define GG82563_PMCR_REVERSE_AUTO_NEG 0x0008 /* 1=Enable Reverse
- Auto-Negotiation */
-#define GG82563_PMCR_DISABLE_1000_NON_D0 0x0010 /* 1=Disable 1000Mbps
- Auto-Neg in non D0 */
-#define GG82563_PMCR_DISABLE_1000 0x0020 /* 1=Disable 1000Mbps
- Auto-Neg Always */
-#define GG82563_PMCR_REVERSE_AUTO_NEG_D0A 0x0040 /* 1=Enable D0a
- Reverse Auto-Negotiation */
-#define GG82563_PMCR_FORCE_POWER_STATE 0x0080 /* 1=Force Power State */
-#define GG82563_PMCR_PROGRAMMED_POWER_STATE_MASK 0x0300
-#define GG82563_PMCR_PROGRAMMED_POWER_STATE_DR 0x0000 /* 00=Dr */
-#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0U 0x0100 /* 01=D0u */
-#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0A 0x0200 /* 10=D0a */
-#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D3 0x0300 /* 11=D3 */
-
-/* In-Band Control Register (Page 194, Register 18) */
-#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding Use */
-
-
-/* Bits...
- * 15-5: page
- * 4-0: register offset
- */
-#define GG82563_PAGE_SHIFT 5
-#define GG82563_REG(page, reg) \
- (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
-#define GG82563_MIN_ALT_REG 30
-
-/* GG82563 Specific Registers */
-#define GG82563_PHY_SPEC_CTRL \
- GG82563_REG(0, 16) /* PHY Specific Control */
-#define GG82563_PHY_SPEC_STATUS \
- GG82563_REG(0, 17) /* PHY Specific Status */
-#define GG82563_PHY_INT_ENABLE \
- GG82563_REG(0, 18) /* Interrupt Enable */
-#define GG82563_PHY_SPEC_STATUS_2 \
- GG82563_REG(0, 19) /* PHY Specific Status 2 */
-#define GG82563_PHY_RX_ERR_CNTR \
- GG82563_REG(0, 21) /* Receive Error Counter */
-#define GG82563_PHY_PAGE_SELECT \
- GG82563_REG(0, 22) /* Page Select */
-#define GG82563_PHY_SPEC_CTRL_2 \
- GG82563_REG(0, 26) /* PHY Specific Control 2 */
-#define GG82563_PHY_PAGE_SELECT_ALT \
- GG82563_REG(0, 29) /* Alternate Page Select */
-#define GG82563_PHY_TEST_CLK_CTRL \
- GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
-
-#define GG82563_PHY_MAC_SPEC_CTRL \
- GG82563_REG(2, 21) /* MAC Specific Control Register */
-#define GG82563_PHY_MAC_SPEC_CTRL_2 \
- GG82563_REG(2, 26) /* MAC Specific Control 2 */
-
-#define GG82563_PHY_DSP_DISTANCE \
- GG82563_REG(5, 26) /* DSP Distance */
-
-/* Page 193 - Port Control Registers */
-#define GG82563_PHY_KMRN_MODE_CTRL \
- GG82563_REG(193, 16) /* Kumeran Mode Control */
-#define GG82563_PHY_PORT_RESET \
- GG82563_REG(193, 17) /* Port Reset */
-#define GG82563_PHY_REVISION_ID \
- GG82563_REG(193, 18) /* Revision ID */
-#define GG82563_PHY_DEVICE_ID \
- GG82563_REG(193, 19) /* Device ID */
-#define GG82563_PHY_PWR_MGMT_CTRL \
- GG82563_REG(193, 20) /* Power Management Control */
-#define GG82563_PHY_RATE_ADAPT_CTRL \
- GG82563_REG(193, 25) /* Rate Adaptation Control */
-
-/* Page 194 - KMRN Registers */
-#define GG82563_PHY_KMRN_FIFO_CTRL_STAT \
- GG82563_REG(194, 16) /* FIFO's Control/Status */
-#define GG82563_PHY_KMRN_CTRL \
- GG82563_REG(194, 17) /* Control */
-#define GG82563_PHY_INBAND_CTRL \
- GG82563_REG(194, 18) /* Inband Control */
-#define GG82563_PHY_KMRN_DIAGNOSTIC \
- GG82563_REG(194, 19) /* Diagnostic */
-#define GG82563_PHY_ACK_TIMEOUTS \
- GG82563_REG(194, 20) /* Acknowledge Timeouts */
-#define GG82563_PHY_ADV_ABILITY \
- GG82563_REG(194, 21) /* Advertised Ability */
-#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \
- GG82563_REG(194, 23) /* Link Partner Advertised Ability */
-#define GG82563_PHY_ADV_NEXT_PAGE \
- GG82563_REG(194, 24) /* Advertised Next Page */
-#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \
- GG82563_REG(194, 25) /* Link Partner Advertised Next page */
-#define GG82563_PHY_KMRN_MISC \
- GG82563_REG(194, 26) /* Misc. */
-
-/* PHY Control Register */
-#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
-#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
-#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
-#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
-#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
-#define MII_CR_POWER_DOWN 0x0800 /* Power down */
-#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
-#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
-#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
-#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
-
-/* PHY Status Register */
-#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
-#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
-#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
-#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
-#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
-#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
-#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
-#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
-#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
-#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
-#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
-#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
-#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
-#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
-#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
-
-/* Autoneg Advertisement Register */
-#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
-#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
-#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
-#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
-#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
-#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
-#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
-#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
-#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
-#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
-
-/* Link Partner Ability Register (Base Page) */
-#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
-#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
-#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
-#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
-#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
-#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
-#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
-#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
-#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
-#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
-#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
-
-/* Autoneg Expansion Register */
-#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
-#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
-#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
-#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
-#define NWAY_ER_PAR_DETECT_FAULT 0x0100 /* LP is 100TX Full Duplex Capable */
-
-/* Next Page TX Register */
-#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
-#define NPTX_TOGGLE 0x0800 /* Toggles between exchanges
- * of different NP
- */
-#define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
- * 0 = cannot comply with msg
- */
-#define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
-#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
- * 0 = sending last NP
- */
-
-/* Link Partner Next Page Register */
-#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
-#define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges
- * of different NP
- */
-#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
- * 0 = cannot comply with msg
- */
-#define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
-#define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */
-#define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
- * 0 = sending last NP
- */
-
-/* 1000BASE-T Control Register */
-#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
-#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
-#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
-#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
- /* 0=DTE device */
-#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
- /* 0=Configure PHY as Slave */
-#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
- /* 0=Automatic Master/Slave config */
-#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
-#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
-#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
-#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
-#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
-
-/* 1000BASE-T Status Register */
-#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
-#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
-#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
-#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
-#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
-#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
-#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
-#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
-#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
-#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
-
-/* Extended Status Register */
-#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
-#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
-#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
-#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
-
-#define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */
-#define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */
-
-#define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */
- /* (0=enable, 1=disable) */
-
-/* M88E1000 PHY Specific Control Register */
-#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
-#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
-#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
-#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
- * 0=CLK125 toggling
- */
-#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
- /* Manual MDI configuration */
-#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
-#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
- * 100BASE-TX/10BASE-T:
- * MDI Mode
- */
-#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
- * all speeds.
- */
-#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
- /* 1=Enable Extended 10BASE-T distance
- * (Lower 10BASE-T RX Threshold)
- * 0=Normal 10BASE-T RX Threshold */
-#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
- /* 1=5-Bit interface in 100BASE-TX
- * 0=MII interface in 100BASE-TX */
-#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
-#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
-#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
-
-#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1
-#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5
-#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
-
-/* M88E1000 PHY Specific Status Register */
-#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
-#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
-#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
-#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
- * 3=110-140M;4=>140M */
-#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
-#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
-#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
-#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
-#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
-#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
-#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
-#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
-
-#define M88E1000_PSSR_REV_POLARITY_SHIFT 1
-#define M88E1000_PSSR_MDIX_SHIFT 6
-#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
-
-/* M88E1000 Extended PHY Specific Control Register */
-#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
-#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled.
- * Will assert lost lock and bring
- * link down if idle not seen
- * within 1ms in 1000BASE-T
- */
-/* Number of times we will attempt to autonegotiate before downshifting if we
- * are the master */
-#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
-#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
-#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
-#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
-#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
-/* Number of times we will attempt to autonegotiate before downshifting if we
- * are the slave */
-#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
-#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
-#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
-#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
-#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
-#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
-#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
-#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
-
-/* Bit definitions for valid PHY IDs. */
-#define M88E1000_E_PHY_ID 0x01410C50
-#define M88E1000_I_PHY_ID 0x01410C30
-#define M88E1011_I_PHY_ID 0x01410C20
-#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
-#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
-#define IGP01E1000_I_PHY_ID 0x02A80380
-#define M88E1011_I_REV_4 0x04
-#define M88E1111_I_PHY_ID 0x01410CC0
-#define L1LXT971A_PHY_ID 0x001378E0
-#define GG82563_E_PHY_ID 0x01410CA0
-
-/* Miscellaneous PHY bit definitions. */
-#define PHY_PREAMBLE 0xFFFFFFFF
-#define PHY_SOF 0x01
-#define PHY_OP_READ 0x02
-#define PHY_OP_WRITE 0x01
-#define PHY_TURNAROUND 0x02
-#define PHY_PREAMBLE_SIZE 32
-#define MII_CR_SPEED_1000 0x0040
-#define MII_CR_SPEED_100 0x2000
-#define MII_CR_SPEED_10 0x0000
-#define E1000_PHY_ADDRESS 0x01
-#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
-#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
-#define PHY_REVISION_MASK 0xFFFFFFF0
-#define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */
-#define REG4_SPEED_MASK 0x01E0
-#define REG9_SPEED_MASK 0x0300
-#define ADVERTISE_10_HALF 0x0001
-#define ADVERTISE_10_FULL 0x0002
-#define ADVERTISE_100_HALF 0x0004
-#define ADVERTISE_100_FULL 0x0008
-#define ADVERTISE_1000_HALF 0x0010
-#define ADVERTISE_1000_FULL 0x0020
-#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
-
-#define ICH_FLASH_GFPREG 0x0000
-#define ICH_FLASH_HSFSTS 0x0004
-#define ICH_FLASH_HSFCTL 0x0006
-#define ICH_FLASH_FADDR 0x0008
-#define ICH_FLASH_FDATA0 0x0010
-#define ICH_FLASH_FRACC 0x0050
-#define ICH_FLASH_FREG0 0x0054
-#define ICH_FLASH_FREG1 0x0058
-#define ICH_FLASH_FREG2 0x005C
-#define ICH_FLASH_FREG3 0x0060
-#define ICH_FLASH_FPR0 0x0074
-#define ICH_FLASH_FPR1 0x0078
-#define ICH_FLASH_SSFSTS 0x0090
-#define ICH_FLASH_SSFCTL 0x0092
-#define ICH_FLASH_PREOP 0x0094
-#define ICH_FLASH_OPTYPE 0x0096
-#define ICH_FLASH_OPMENU 0x0098
-
-#define ICH_FLASH_REG_MAPSIZE 0x00A0
-#define ICH_FLASH_SECTOR_SIZE 4096
-#define ICH_GFPREG_BASE_MASK 0x1FFF
-#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
-
-#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
-#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
-
-/* SPI EEPROM Status Register */
-#define EEPROM_STATUS_RDY_SPI 0x01
-#define EEPROM_STATUS_WEN_SPI 0x02
-#define EEPROM_STATUS_BP0_SPI 0x04
-#define EEPROM_STATUS_BP1_SPI 0x08
-#define EEPROM_STATUS_WPEN_SPI 0x80
-
-/* SW Semaphore Register */
-#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
-#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
-#define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
-#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
-
-/* FW Semaphore Register */
-#define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */
-#define E1000_FWSM_MODE_SHIFT 1
-#define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */
-
-#define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */
-#define E1000_FWSM_DISSW 0x10000000 /* FW disable SW Write Access */
-#define E1000_FWSM_SKUSEL_MASK 0x60000000 /* LAN SKU select */
-#define E1000_FWSM_SKUEL_SHIFT 29
-#define E1000_FWSM_SKUSEL_EMB 0x0 /* Embedded SKU */
-#define E1000_FWSM_SKUSEL_CONS 0x1 /* Consumer SKU */
-#define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */
-#define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */
-
-#define E1000_GCR 0x05B00 /* PCI-Ex Control */
-#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
-#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */
-#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */
-#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */
-#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
-#define E1000_SWSM 0x05B50 /* SW Semaphore */
-#define E1000_FWSM 0x05B54 /* FW Semaphore */
-#define E1000_FFLT_DBG 0x05F04 /* Debug Register */
-#define E1000_HICR 0x08F00 /* Host Inteface Control */
-
-#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
-#define IGP_ACTIVITY_LED_ENABLE 0x0300
-#define IGP_LED3_MODE 0x07000000
-
-/* Mask bit for PHY class in Word 7 of the EEPROM */
-#define EEPROM_PHY_CLASS_A 0x8000
-#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
-#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/
-#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/
-
-#define E1000_KUMCTRLSTA_MASK 0x0000FFFF
-#define E1000_KUMCTRLSTA_OFFSET 0x001F0000
-#define E1000_KUMCTRLSTA_OFFSET_SHIFT 16
-#define E1000_KUMCTRLSTA_REN 0x00200000
-
-#define E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000
-#define E1000_KUMCTRLSTA_OFFSET_CTRL 0x00000001
-#define E1000_KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002
-#define E1000_KUMCTRLSTA_OFFSET_DIAG 0x00000003
-#define E1000_KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004
-#define E1000_KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009
-#define E1000_KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010
-#define E1000_KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001E
-#define E1000_KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001F
-
-/* FIFO Control */
-#define E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x00000008
-#define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800
-
-/* In-Band Control */
-#define E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT 0x00000500
-#define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010
-
-/* Half-Duplex Control */
-#define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004
-#define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000
-
-#define E1000_KUMCTRLSTA_OFFSET_K0S_CTRL 0x0000001E
-
-#define E1000_KUMCTRLSTA_DIAG_FELPBK 0x2000
-#define E1000_KUMCTRLSTA_DIAG_NELPBK 0x1000
-
-#define E1000_KUMCTRLSTA_K0S_100_EN 0x2000
-#define E1000_KUMCTRLSTA_K0S_GBE_EN 0x1000
-#define E1000_KUMCTRLSTA_K0S_ENTRY_LATENCY_MASK 0x0003
-
-#define E1000_MNG_ICH_IAMT_MODE 0x2
-#define E1000_MNG_IAMT_MODE 0x3
-#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
-#define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */
-/* Number of milliseconds we wait for PHY configuration done after MAC reset */
-#define PHY_CFG_TIMEOUT 100
-#define DEFAULT_80003ES2LAN_TIPG_IPGT_10_100 0x00000009
-#define DEFAULT_80003ES2LAN_TIPG_IPGT_1000 0x00000008
-#define E1000_TXDMAC_DPP 0x00000001
-#define AUTO_ALL_MODES 0
-
-#ifndef E1000_MASTER_SLAVE
-/* Switch to override PHY master/slave setting */
-#define E1000_MASTER_SLAVE e1000_ms_hw_default
-#endif
-/* Extended Transmit Control */
-#define E1000_TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */
-#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
-
-#define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000
-
-#define PCI_EX_82566_SNOOP_ALL PCI_EX_NO_SNOOP_ALL
-
-#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
-#define E1000_MC_TBL_SIZE_ICH8LAN 32
-
-#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers
- after IMS clear */
-#endif /* _E1000_HW_H_ */
+++ /dev/null
-/****************************************************************************
- * Copyright(c) 2000-2001 Broadcom Corporation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation.
- *
- * Name: nicext.h
- *
- * Description: Broadcom Network Interface Card Extension (NICE) is an
- * extension to Linux NET device kernel mode drivers.
- * NICE is designed to provide additional functionalities,
- * such as receive packet intercept. To support Broadcom NICE,
- * the network device driver can be modified by adding an
- * device ioctl handler and by indicating receiving packets
- * to the NICE receive handler. Broadcom NICE will only be
- * enabled by a NICE-aware intermediate driver, such as
- * Broadcom Advanced Server Program Driver (BASP). When NICE
- * is not enabled, the modified network device drivers
- * functions exactly as other non-NICE aware drivers.
- *
- * Author: Frankie Fan
- *
- * Created: September 17, 2000
- *
- ****************************************************************************/
-#ifndef _nicext_h_
-#define _nicext_h_
-
-/*
- * ioctl for NICE
- */
-#define SIOCNICE SIOCDEVPRIVATE+7
-
-/*
- * SIOCNICE:
- *
- * The following structure needs to be less than IFNAMSIZ (16 bytes) because
- * we're overloading ifreq.ifr_ifru.
- *
- * If 16 bytes is not enough, we should consider relaxing this because
- * this is no field after ifr_ifru in the ifreq structure. But we may
- * run into future compatiability problem in case of changing struct ifreq.
- */
-struct nice_req
-{
- __u32 cmd;
-
- union
- {
-#ifdef __KERNEL__
- /* cmd = NICE_CMD_SET_RX or NICE_CMD_GET_RX */
- struct
- {
- void (*nrqus1_rx)( struct sk_buff*, void* );
- void* nrqus1_ctx;
- } nrqu_nrqus1;
-
- /* cmd = NICE_CMD_QUERY_SUPPORT */
- struct
- {
- __u32 nrqus2_magic;
- __u32 nrqus2_support_rx:1;
- __u32 nrqus2_support_vlan:1;
- __u32 nrqus2_support_get_speed:1;
- } nrqu_nrqus2;
-#endif
-
- /* cmd = NICE_CMD_GET_SPEED */
- struct
- {
- unsigned int nrqus3_speed; /* 0 if link is down, */
- /* otherwise speed in Mbps */
- } nrqu_nrqus3;
-
- /* cmd = NICE_CMD_BLINK_LED */
- struct
- {
- unsigned int nrqus4_blink_time; /* blink duration in seconds */
- } nrqu_nrqus4;
-
- } nrq_nrqu;
-};
-
-#define nrq_rx nrq_nrqu.nrqu_nrqus1.nrqus1_rx
-#define nrq_ctx nrq_nrqu.nrqu_nrqus1.nrqus1_ctx
-#define nrq_support_rx nrq_nrqu.nrqu_nrqus2.nrqus2_support_rx
-#define nrq_magic nrq_nrqu.nrqu_nrqus2.nrqus2_magic
-#define nrq_support_vlan nrq_nrqu.nrqu_nrqus2.nrqus2_support_vlan
-#define nrq_support_get_speed nrq_nrqu.nrqu_nrqus2.nrqus2_support_get_speed
-#define nrq_speed nrq_nrqu.nrqu_nrqus3.nrqus3_speed
-#define nrq_blink_time nrq_nrqu.nrqu_nrqus4.nrqus4_blink_time
-
-/*
- * magic constants
- */
-#define NICE_REQUESTOR_MAGIC 0x4543494E /* NICE in ascii */
-#define NICE_DEVICE_MAGIC 0x4E494345 /* ECIN in ascii */
-
-/*
- * command field
- */
-#define NICE_CMD_QUERY_SUPPORT 0x00000001
-#define NICE_CMD_SET_RX 0x00000002
-#define NICE_CMD_GET_RX 0x00000003
-#define NICE_CMD_GET_SPEED 0x00000004
-#define NICE_CMD_BLINK_LED 0x00000005
-
-#endif /* _nicext_h_ */
+++ /dev/null
-/***********************************************************************
- *
- * Copyright (C) 2004 by FS Forth-Systeme GmbH.
- * All rights reserved.
- *
- * $Id: ns9750_eth.c,v 1.2 2004/02/24 14:09:39 mpietrek Exp $
- * @Author: Markus Pietrek
- * @Descr: Ethernet driver for the NS9750. Uses DMA Engine with polling
- * interrupt status. But interrupts are not enabled.
- * Only one tx buffer descriptor and the RXA buffer descriptor are used
- * Currently no transmit lockup handling is included. eth_send has a 5s
- * timeout for sending frames. No retransmits are performed when an
- * error occurs.
- * @References: [1] NS9750 Hardware Reference, December 2003
- * [2] Intel LXT971 Datasheet #249414 Rev. 02
- * [3] NS7520 Linux Ethernet Driver
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- ***********************************************************************/
-
-#include <common.h>
-#include <net.h> /* NetSendPacket */
-
-#include "ns9750_eth.h" /* for Ethernet and PHY */
-
-/* some definition to make transition to linux easier */
-
-#define NS9750_DRIVER_NAME "eth"
-#define KERN_WARNING "Warning:"
-#define KERN_ERR "Error:"
-#define KERN_INFO "Info:"
-
-#if 0
-# define DEBUG
-#endif
-
-#ifdef DEBUG
-# define printk printf
-
-# define DEBUG_INIT 0x0001
-# define DEBUG_MINOR 0x0002
-# define DEBUG_RX 0x0004
-# define DEBUG_TX 0x0008
-# define DEBUG_INT 0x0010
-# define DEBUG_POLL 0x0020
-# define DEBUG_LINK 0x0040
-# define DEBUG_MII 0x0100
-# define DEBUG_MII_LOW 0x0200
-# define DEBUG_MEM 0x0400
-# define DEBUG_ERROR 0x4000
-# define DEBUG_ERROR_CRIT 0x8000
-
-static int nDebugLvl = DEBUG_ERROR_CRIT;
-
-# define DEBUG_ARGS0( FLG, a0 ) if( ( nDebugLvl & (FLG) ) == (FLG) ) \
- printf("%s: " a0, __FUNCTION__, 0, 0, 0, 0, 0, 0 )
-# define DEBUG_ARGS1( FLG, a0, a1 ) if( ( nDebugLvl & (FLG) ) == (FLG)) \
- printf("%s: " a0, __FUNCTION__, (int)(a1), 0, 0, 0, 0, 0 )
-# define DEBUG_ARGS2( FLG, a0, a1, a2 ) if( (nDebugLvl & (FLG)) ==(FLG))\
- printf("%s: " a0, __FUNCTION__, (int)(a1), (int)(a2), 0, 0,0,0 )
-# define DEBUG_ARGS3( FLG, a0, a1, a2, a3 ) if((nDebugLvl &(FLG))==(FLG))\
- printf("%s: "a0,__FUNCTION__,(int)(a1),(int)(a2),(int)(a3),0,0,0)
-# define DEBUG_FN( FLG ) if( (nDebugLvl & (FLG)) == (FLG) ) \
- printf("\r%s:line %d\n", (int)__FUNCTION__, __LINE__, 0,0,0,0);
-# define ASSERT( expr, func ) if( !( expr ) ) { \
- printf( "Assertion failed! %s:line %d %s\n", \
- (int)__FUNCTION__,__LINE__,(int)(#expr),0,0,0); \
- func }
-#else /* DEBUG */
-# define printk(...)
-# define DEBUG_ARGS0( FLG, a0 )
-# define DEBUG_ARGS1( FLG, a0, a1 )
-# define DEBUG_ARGS2( FLG, a0, a1, a2 )
-# define DEBUG_ARGS3( FLG, a0, a1, a2, a3 )
-# define DEBUG_FN( n )
-# define ASSERT(expr, func)
-#endif /* DEBUG */
-
-#define NS9750_MII_NEG_DELAY (5*CONFIG_SYS_HZ) /* in s */
-#define TX_TIMEOUT (5*CONFIG_SYS_HZ) /* in s */
-
-/* @TODO move it to eeprom.h */
-#define FS_EEPROM_AUTONEG_MASK 0x7
-#define FS_EEPROM_AUTONEG_SPEED_MASK 0x1
-#define FS_EEPROM_AUTONEG_SPEED_10 0x0
-#define FS_EEPROM_AUTONEG_SPEED_100 0x1
-#define FS_EEPROM_AUTONEG_DUPLEX_MASK 0x2
-#define FS_EEPROM_AUTONEG_DUPLEX_HALF 0x0
-#define FS_EEPROM_AUTONEG_DUPLEX_FULL 0x2
-#define FS_EEPROM_AUTONEG_ENABLE_MASK 0x4
-#define FS_EEPROM_AUTONEG_DISABLE 0x0
-#define FS_EEPROM_AUTONEG_ENABLE 0x4
-
-/* buffer descriptors taken from [1] p.306 */
-typedef struct
-{
- unsigned int* punSrc;
- unsigned int unLen; /* 11 bits */
- unsigned int* punDest; /* unused */
- union {
- unsigned int unReg;
- struct {
- unsigned uStatus : 16;
- unsigned uRes : 12;
- unsigned uFull : 1;
- unsigned uEnable : 1;
- unsigned uInt : 1;
- unsigned uWrap : 1;
- } bits;
- } s;
-} rx_buffer_desc_t;
-
-typedef struct
-{
- unsigned int* punSrc;
- unsigned int unLen; /* 10 bits */
- unsigned int* punDest; /* unused */
- union {
- unsigned int unReg; /* only 32bit accesses may done to NS9750
- * eth engine */
- struct {
- unsigned uStatus : 16;
- unsigned uRes : 12;
- unsigned uFull : 1;
- unsigned uLast : 1;
- unsigned uInt : 1;
- unsigned uWrap : 1;
- } bits;
- } s;
-} tx_buffer_desc_t;
-
-static int ns9750_eth_reset( void );
-
-static void ns9750_link_force( void );
-static void ns9750_link_auto_negotiate( void );
-static void ns9750_link_update_egcr( void );
-static void ns9750_link_print_changed( void );
-
-/* the PHY stuff */
-
-static char ns9750_mii_identify_phy( void );
-static unsigned short ns9750_mii_read( unsigned short uiRegister );
-static void ns9750_mii_write( unsigned short uiRegister, unsigned short uiData );
-static unsigned int ns9750_mii_get_clock_divisor( unsigned int unMaxMDIOClk );
-static unsigned int ns9750_mii_poll_busy( void );
-
-static unsigned int nPhyMaxMdioClock = PHY_MDIO_MAX_CLK;
-static unsigned char ucLinkMode = FS_EEPROM_AUTONEG_ENABLE;
-static unsigned int uiLastLinkStatus;
-static PhyType phyDetected = PHY_NONE;
-
-/* we use only one tx buffer descriptor */
-static tx_buffer_desc_t* pTxBufferDesc =
- (tx_buffer_desc_t*) get_eth_reg_addr( NS9750_ETH_TXBD );
-
-/* we use only one rx buffer descriptor of the 4 */
-static rx_buffer_desc_t aRxBufferDesc[ 4 ];
-
-/***********************************************************************
- * @Function: eth_init
- * @Return: -1 on failure otherwise 0
- * @Descr: Initializes the ethernet engine and uses either FS Forth's default
- * MAC addr or the one in environment
- ***********************************************************************/
-
-int eth_init (bd_t * pbis)
-{
- /* This default MAC Addr is reserved by FS Forth-Systeme for the case of
- EEPROM failures */
- unsigned char aucMACAddr[6] = { 0x00, 0x04, 0xf3, 0x00, 0x06, 0x35 };
- char *pcTmp = getenv ("ethaddr");
- char *pcEnd;
- int i;
-
- DEBUG_FN (DEBUG_INIT);
-
- /* no need to check for hardware */
-
- if (!ns9750_eth_reset ())
- return -1;
-
- if (pcTmp != NULL)
- for (i = 0; i < 6; i++) {
- aucMACAddr[i] =
- pcTmp ? simple_strtoul (pcTmp, &pcEnd,
- 16) : 0;
- pcTmp = (*pcTmp) ? pcEnd + 1 : pcEnd;
- }
-
- /* configure ethernet address */
-
- *get_eth_reg_addr (NS9750_ETH_SA1) =
- aucMACAddr[5] << 8 | aucMACAddr[4];
- *get_eth_reg_addr (NS9750_ETH_SA2) =
- aucMACAddr[3] << 8 | aucMACAddr[2];
- *get_eth_reg_addr (NS9750_ETH_SA3) =
- aucMACAddr[1] << 8 | aucMACAddr[0];
-
- /* enable hardware */
-
- *get_eth_reg_addr (NS9750_ETH_MAC1) = NS9750_ETH_MAC1_RXEN;
-
- /* the linux kernel may give packets < 60 bytes, for example arp */
- *get_eth_reg_addr (NS9750_ETH_MAC2) = NS9750_ETH_MAC2_CRCEN |
- NS9750_ETH_MAC2_PADEN | NS9750_ETH_MAC2_HUGE;
-
- /* enable receive and transmit FIFO, use 10/100 Mbps MII */
- *get_eth_reg_addr (NS9750_ETH_EGCR1) =
- NS9750_ETH_EGCR1_ETXWM |
- NS9750_ETH_EGCR1_ERX |
- NS9750_ETH_EGCR1_ERXDMA |
- NS9750_ETH_EGCR1_ETX |
- NS9750_ETH_EGCR1_ETXDMA | NS9750_ETH_EGCR1_ITXA;
-
- /* prepare DMA descriptors */
- for (i = 0; i < 4; i++) {
- aRxBufferDesc[i].punSrc = 0;
- aRxBufferDesc[i].unLen = 0;
- aRxBufferDesc[i].s.bits.uWrap = 1;
- aRxBufferDesc[i].s.bits.uInt = 1;
- aRxBufferDesc[i].s.bits.uEnable = 0;
- aRxBufferDesc[i].s.bits.uFull = 0;
- }
-
- /* NetRxPackets[ 0 ] is initialized before eth_init is called and never
- changes. NetRxPackets is 32bit aligned */
- aRxBufferDesc[0].punSrc = (unsigned int *) NetRxPackets[0];
- aRxBufferDesc[0].s.bits.uEnable = 1;
- aRxBufferDesc[0].unLen = 1522; /* as stated in [1] p.307 */
-
- *get_eth_reg_addr (NS9750_ETH_RXAPTR) =
- (unsigned int) &aRxBufferDesc[0];
-
- /* [1] Tab. 221 states less than 5us */
- *get_eth_reg_addr (NS9750_ETH_EGCR1) |= NS9750_ETH_EGCR1_ERXINIT;
- while (!
- (*get_eth_reg_addr (NS9750_ETH_EGSR) & NS9750_ETH_EGSR_RXINIT))
- /* wait for finish */
- udelay (1);
-
- /* @TODO do we need to clear RXINIT? */
- *get_eth_reg_addr (NS9750_ETH_EGCR1) &= ~NS9750_ETH_EGCR1_ERXINIT;
-
- *get_eth_reg_addr (NS9750_ETH_RXFREE) = 0x1;
-
- return 0;
-}
-
-/***********************************************************************
- * @Function: eth_send
- * @Return: -1 on timeout otherwise 1
- * @Descr: sends one frame by DMA
- ***********************************************************************/
-
-int eth_send (volatile void *pPacket, int nLen)
-{
- ulong ulTimeout;
-
- DEBUG_FN (DEBUG_TX);
-
- /* clear old status values */
- *get_eth_reg_addr (NS9750_ETH_EINTR) &=
- *get_eth_reg_addr (NS9750_ETH_EINTR) & NS9750_ETH_EINTR_TX_MA;
-
- /* prepare Tx Descriptors */
-
- pTxBufferDesc->punSrc = (unsigned int *) pPacket; /* pPacket is 32bit
- * aligned */
- pTxBufferDesc->unLen = nLen;
- /* only 32bit accesses allowed. wrap, full, interrupt and enabled to 1 */
- pTxBufferDesc->s.unReg = 0xf0000000;
- /* pTxBufferDesc is the first possible buffer descriptor */
- *get_eth_reg_addr (NS9750_ETH_TXPTR) = 0x0;
-
- /* enable processor for next frame */
-
- *get_eth_reg_addr (NS9750_ETH_EGCR2) &= ~NS9750_ETH_EGCR2_TCLER;
- *get_eth_reg_addr (NS9750_ETH_EGCR2) |= NS9750_ETH_EGCR2_TCLER;
-
- ulTimeout = get_timer (0);
-
- DEBUG_ARGS0 (DEBUG_TX | DEBUG_MINOR,
- "Waiting for transmission to finish\n");
- while (!
- (*get_eth_reg_addr (NS9750_ETH_EINTR) &
- (NS9750_ETH_EINTR_TXDONE | NS9750_ETH_EINTR_TXERR))) {
- /* do nothing, wait for completion */
- if (get_timer (0) - ulTimeout > TX_TIMEOUT) {
- DEBUG_ARGS0 (DEBUG_TX, "Transmit Timed out\n");
- return -1;
- }
- }
- DEBUG_ARGS0 (DEBUG_TX | DEBUG_MINOR, "transmitted...\n");
-
- return 0;
-}
-
-/***********************************************************************
- * @Function: eth_rx
- * @Return: size of last frame in bytes or 0 if no frame available
- * @Descr: gives one frame to U-Boot which has been copied by DMA engine already
- * to NetRxPackets[ 0 ].
- ***********************************************************************/
-
-int eth_rx (void)
-{
- int nLen = 0;
- unsigned int unStatus;
-
- unStatus =
- *get_eth_reg_addr (NS9750_ETH_EINTR) & NS9750_ETH_EINTR_RX_MA;
-
- if (!unStatus)
- /* no packet available, return immediately */
- return 0;
-
- DEBUG_FN (DEBUG_RX);
-
- /* unLen always < max(nLen) and discard checksum */
- nLen = (int) aRxBufferDesc[0].unLen - 4;
-
- /* acknowledge status register */
- *get_eth_reg_addr (NS9750_ETH_EINTR) = unStatus;
-
- aRxBufferDesc[0].unLen = 1522;
- aRxBufferDesc[0].s.bits.uFull = 0;
-
- /* Buffer A descriptor available again */
- *get_eth_reg_addr (NS9750_ETH_RXFREE) |= 0x1;
-
- /* NetReceive may call eth_send. Due to a possible bug of the NS9750 we
- * have to acknowledge the received frame before sending a new one */
- if (unStatus & NS9750_ETH_EINTR_RXDONEA)
- NetReceive (NetRxPackets[0], nLen);
-
- return nLen;
-}
-
-/***********************************************************************
- * @Function: eth_halt
- * @Return: n/a
- * @Descr: stops the ethernet engine
- ***********************************************************************/
-
-void eth_halt (void)
-{
- DEBUG_FN (DEBUG_INIT);
-
- *get_eth_reg_addr (NS9750_ETH_MAC1) &= ~NS9750_ETH_MAC1_RXEN;
- *get_eth_reg_addr (NS9750_ETH_EGCR1) &= ~(NS9750_ETH_EGCR1_ERX |
- NS9750_ETH_EGCR1_ERXDMA |
- NS9750_ETH_EGCR1_ETX |
- NS9750_ETH_EGCR1_ETXDMA);
-}
-
-/***********************************************************************
- * @Function: ns9750_eth_reset
- * @Return: 0 on failure otherwise 1
- * @Descr: resets the ethernet interface and the PHY,
- * performs auto negotiation or fixed modes
- ***********************************************************************/
-
-static int ns9750_eth_reset (void)
-{
- DEBUG_FN (DEBUG_MINOR);
-
- /* Reset MAC */
- *get_eth_reg_addr (NS9750_ETH_EGCR1) |= NS9750_ETH_EGCR1_MAC_HRST;
- udelay (5); /* according to [1], p.322 */
- *get_eth_reg_addr (NS9750_ETH_EGCR1) &= ~NS9750_ETH_EGCR1_MAC_HRST;
-
- /* reset and initialize PHY */
-
- *get_eth_reg_addr (NS9750_ETH_MAC1) &= ~NS9750_ETH_MAC1_SRST;
-
- /* we don't support hot plugging of PHY, therefore we don't reset
- phyDetected and nPhyMaxMdioClock here. The risk is if the setting is
- incorrect the first open
- may detect the PHY correctly but succeding will fail
- For reseting the PHY and identifying we have to use the standard
- MDIO CLOCK value 2.5 MHz only after hardware reset
- After having identified the PHY we will do faster */
-
- *get_eth_reg_addr (NS9750_ETH_MCFG) =
- ns9750_mii_get_clock_divisor (nPhyMaxMdioClock);
-
- /* reset PHY */
- ns9750_mii_write(PHY_BMCR, PHY_BMCR_RESET);
- ns9750_mii_write(PHY_BMCR, 0);
-
- /* @TODO check time */
- udelay (3000); /* [2] p.70 says at least 300us reset recovery time. But
- go sure, it didn't worked stable at higher timer
- frequencies under LxNETES-2.x */
-
- /* MII clock has been setup to default, ns9750_mii_identify_phy should
- work for all */
-
- if (!ns9750_mii_identify_phy ()) {
- printk (KERN_ERR NS9750_DRIVER_NAME
- ": Unsupported PHY, aborting\n");
- return 0;
- }
-
- /* now take the highest MDIO clock possible after detection */
- *get_eth_reg_addr (NS9750_ETH_MCFG) =
- ns9750_mii_get_clock_divisor (nPhyMaxMdioClock);
-
-
- /* PHY has been detected, so there can be no abort reason and we can
- finish initializing ethernet */
-
- uiLastLinkStatus = 0xff; /* undefined */
-
- if ((ucLinkMode & FS_EEPROM_AUTONEG_ENABLE_MASK) ==
- FS_EEPROM_AUTONEG_DISABLE)
- /* use parameters defined */
- ns9750_link_force ();
- else
- ns9750_link_auto_negotiate ();
-
- if (phyDetected == PHY_LXT971A)
- /* set LED2 to link mode */
- ns9750_mii_write (PHY_LXT971_LED_CFG,
- PHY_LXT971_LED_CFG_LINK_ACT <<
- PHY_LXT971_LED_CFG_SHIFT_LED2);
-
- return 1;
-}
-
-/***********************************************************************
- * @Function: ns9750_link_force
- * @Return: void
- * @Descr: configures eth and MII to use the link mode defined in
- * ucLinkMode
- ***********************************************************************/
-
-static void ns9750_link_force (void)
-{
- unsigned short uiControl;
-
- DEBUG_FN (DEBUG_LINK);
-
- uiControl = ns9750_mii_read(PHY_BMCR);
- uiControl &= ~(PHY_BMCR_SPEED_MASK |
- PHY_BMCR_AUTON | PHY_BMCR_DPLX);
-
- uiLastLinkStatus = 0;
-
- if ((ucLinkMode & FS_EEPROM_AUTONEG_SPEED_MASK) ==
- FS_EEPROM_AUTONEG_SPEED_100) {
- uiControl |= PHY_BMCR_100MB;
- uiLastLinkStatus |= PHY_LXT971_STAT2_100BTX;
- } else
- uiControl |= PHY_BMCR_10_MBPS;
-
- if ((ucLinkMode & FS_EEPROM_AUTONEG_DUPLEX_MASK) ==
- FS_EEPROM_AUTONEG_DUPLEX_FULL) {
- uiControl |= PHY_BMCR_DPLX;
- uiLastLinkStatus |= PHY_LXT971_STAT2_DUPLEX_MODE;
- }
-
- ns9750_mii_write(PHY_BMCR, uiControl);
-
- ns9750_link_print_changed ();
- ns9750_link_update_egcr ();
-}
-
-/***********************************************************************
- * @Function: ns9750_link_auto_negotiate
- * @Return: void
- * @Descr: performs auto-negotation of link.
- ***********************************************************************/
-
-static void ns9750_link_auto_negotiate (void)
-{
- unsigned long ulStartJiffies;
- unsigned short uiStatus;
-
- DEBUG_FN (DEBUG_LINK);
-
- /* run auto-negotation */
- /* define what we are capable of */
- ns9750_mii_write(PHY_ANAR,
- PHY_ANLPAR_TXFD |
- PHY_ANLPAR_TX |
- PHY_ANLPAR_10FD |
- PHY_ANLPAR_10 |
- PHY_ANLPAR_PSB_802_3);
- /* start auto-negotiation */
- ns9750_mii_write(PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
-
- /* wait for completion */
-
- ulStartJiffies = get_ticks ();
- while (get_ticks () < ulStartJiffies + NS9750_MII_NEG_DELAY) {
- uiStatus = ns9750_mii_read(PHY_BMSR);
- if ((uiStatus &
- (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)) ==
- (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)) {
- /* lucky we are, auto-negotiation succeeded */
- ns9750_link_print_changed ();
- ns9750_link_update_egcr ();
- return;
- }
- }
-
- DEBUG_ARGS0 (DEBUG_LINK, "auto-negotiation timed out\n");
- /* ignore invalid link settings */
-}
-
-/***********************************************************************
- * @Function: ns9750_link_update_egcr
- * @Return: void
- * @Descr: updates the EGCR and MAC2 link status after mode change or
- * auto-negotation
- ***********************************************************************/
-
-static void ns9750_link_update_egcr (void)
-{
- unsigned int unEGCR;
- unsigned int unMAC2;
- unsigned int unIPGT;
-
- DEBUG_FN (DEBUG_LINK);
-
- unEGCR = *get_eth_reg_addr (NS9750_ETH_EGCR1);
- unMAC2 = *get_eth_reg_addr (NS9750_ETH_MAC2);
- unIPGT = *get_eth_reg_addr (NS9750_ETH_IPGT) & ~NS9750_ETH_IPGT_MA;
-
- unMAC2 &= ~NS9750_ETH_MAC2_FULLD;
- if ((uiLastLinkStatus & PHY_LXT971_STAT2_DUPLEX_MODE)
- == PHY_LXT971_STAT2_DUPLEX_MODE) {
- unMAC2 |= NS9750_ETH_MAC2_FULLD;
- unIPGT |= 0x15; /* see [1] p. 339 */
- } else
- unIPGT |= 0x12; /* see [1] p. 339 */
-
- *get_eth_reg_addr (NS9750_ETH_MAC2) = unMAC2;
- *get_eth_reg_addr (NS9750_ETH_EGCR1) = unEGCR;
- *get_eth_reg_addr (NS9750_ETH_IPGT) = unIPGT;
-}
-
-/***********************************************************************
- * @Function: ns9750_link_print_changed
- * @Return: void
- * @Descr: checks whether the link status has changed and if so prints
- * the new mode
- ***********************************************************************/
-
-static void ns9750_link_print_changed (void)
-{
- unsigned short uiStatus;
- unsigned short uiControl;
-
- DEBUG_FN (DEBUG_LINK);
-
- uiControl = ns9750_mii_read(PHY_BMCR);
-
- if ((uiControl & PHY_BMCR_AUTON) == PHY_BMCR_AUTON) {
- /* PHY_BMSR_LS is only set on autonegotiation */
- uiStatus = ns9750_mii_read(PHY_BMSR);
-
- if (!(uiStatus & PHY_BMSR_LS)) {
- printk (KERN_WARNING NS9750_DRIVER_NAME
- ": link down\n");
- /* @TODO Linux: carrier_off */
- } else {
- /* @TODO Linux: carrier_on */
- if (phyDetected == PHY_LXT971A) {
- uiStatus = ns9750_mii_read (PHY_LXT971_STAT2);
- uiStatus &= (PHY_LXT971_STAT2_100BTX |
- PHY_LXT971_STAT2_DUPLEX_MODE |
- PHY_LXT971_STAT2_AUTO_NEG);
-
- /* mask out all uninteresting parts */
- }
- /* other PHYs must store their link information in
- uiStatus as PHY_LXT971 */
- }
- } else {
- /* mode has been forced, so uiStatus should be the same as the
- last link status, enforce printing */
- uiStatus = uiLastLinkStatus;
- uiLastLinkStatus = 0xff;
- }
-
- if (uiStatus != uiLastLinkStatus) {
- /* save current link status */
- uiLastLinkStatus = uiStatus;
-
- /* print new link status */
-
- printk (KERN_INFO NS9750_DRIVER_NAME
- ": link mode %i Mbps %s duplex %s\n",
- (uiStatus & PHY_LXT971_STAT2_100BTX) ? 100 : 10,
- (uiStatus & PHY_LXT971_STAT2_DUPLEX_MODE) ? "full" :
- "half",
- (uiStatus & PHY_LXT971_STAT2_AUTO_NEG) ? "(auto)" :
- "");
- }
-}
-
-/***********************************************************************
- * the MII low level stuff
- ***********************************************************************/
-
-/***********************************************************************
- * @Function: ns9750_mii_identify_phy
- * @Return: 1 if supported PHY has been detected otherwise 0
- * @Descr: checks for supported PHY and prints the IDs.
- ***********************************************************************/
-
-static char ns9750_mii_identify_phy (void)
-{
- unsigned short uiID1;
- unsigned short uiID2;
- unsigned char *szName;
- char cRes = 0;
-
- DEBUG_FN (DEBUG_MII);
-
- phyDetected = (PhyType) uiID1 = ns9750_mii_read(PHY_PHYIDR1);
-
- switch (phyDetected) {
- case PHY_LXT971A:
- szName = "LXT971A";
- uiID2 = ns9750_mii_read(PHY_PHYIDR2);
- nPhyMaxMdioClock = PHY_LXT971_MDIO_MAX_CLK;
- cRes = 1;
- break;
- case PHY_NONE:
- default:
- /* in case uiID1 == 0 && uiID2 == 0 we may have the wrong
- address or reset sets the wrong NS9750_ETH_MCFG_CLKS */
-
- uiID2 = 0;
- szName = "unknown";
- nPhyMaxMdioClock = PHY_MDIO_MAX_CLK;
- phyDetected = PHY_NONE;
- }
-
- printk (KERN_INFO NS9750_DRIVER_NAME
- ": PHY (0x%x, 0x%x) = %s detected\n", uiID1, uiID2, szName);
-
- return cRes;
-}
-
-/***********************************************************************
- * @Function: ns9750_mii_read
- * @Return: the data read from PHY register uiRegister
- * @Descr: the data read may be invalid if timed out. If so, a message
- * is printed but the invalid data is returned.
- * The fixed device address is being used.
- ***********************************************************************/
-
-static unsigned short ns9750_mii_read (unsigned short uiRegister)
-{
- DEBUG_FN (DEBUG_MII_LOW);
-
- /* write MII register to be read */
- *get_eth_reg_addr (NS9750_ETH_MADR) =
- NS9750_ETH_PHY_ADDRESS << 8 | uiRegister;
-
- *get_eth_reg_addr (NS9750_ETH_MCMD) = NS9750_ETH_MCMD_READ;
-
- if (!ns9750_mii_poll_busy ())
- printk (KERN_WARNING NS9750_DRIVER_NAME
- ": MII still busy in read\n");
- /* continue to read */
-
- *get_eth_reg_addr (NS9750_ETH_MCMD) = 0;
-
- return (unsigned short) (*get_eth_reg_addr (NS9750_ETH_MRDD));
-}
-
-
-/***********************************************************************
- * @Function: ns9750_mii_write
- * @Return: nothing
- * @Descr: writes the data to the PHY register. In case of a timeout,
- * no special handling is performed but a message printed
- * The fixed device address is being used.
- ***********************************************************************/
-
-static void ns9750_mii_write (unsigned short uiRegister,
- unsigned short uiData)
-{
- DEBUG_FN (DEBUG_MII_LOW);
-
- /* write MII register to be written */
- *get_eth_reg_addr (NS9750_ETH_MADR) =
- NS9750_ETH_PHY_ADDRESS << 8 | uiRegister;
-
- *get_eth_reg_addr (NS9750_ETH_MWTD) = uiData;
-
- if (!ns9750_mii_poll_busy ()) {
- printf (KERN_WARNING NS9750_DRIVER_NAME
- ": MII still busy in write\n");
- }
-}
-
-
-/***********************************************************************
- * @Function: ns9750_mii_get_clock_divisor
- * @Return: the clock divisor that should be used in NS9750_ETH_MCFG_CLKS
- * @Descr: if no clock divisor can be calculated for the
- * current SYSCLK and the maximum MDIO Clock, a warning is printed
- * and the greatest divisor is taken
- ***********************************************************************/
-
-static unsigned int ns9750_mii_get_clock_divisor (unsigned int unMaxMDIOClk)
-{
- struct {
- unsigned int unSysClkDivisor;
- unsigned int unClks; /* field for NS9750_ETH_MCFG_CLKS */
- } PHYClockDivisors[] = {
- {
- 4, NS9750_ETH_MCFG_CLKS_4}, {
- 6, NS9750_ETH_MCFG_CLKS_6}, {
- 8, NS9750_ETH_MCFG_CLKS_8}, {
- 10, NS9750_ETH_MCFG_CLKS_10}, {
- 20, NS9750_ETH_MCFG_CLKS_20}, {
- 30, NS9750_ETH_MCFG_CLKS_30}, {
- 40, NS9750_ETH_MCFG_CLKS_40}
- };
-
- int nIndexSysClkDiv;
- int nArraySize =
- sizeof (PHYClockDivisors) / sizeof (PHYClockDivisors[0]);
- unsigned int unClks = NS9750_ETH_MCFG_CLKS_40; /* defaults to
- greatest div */
-
- DEBUG_FN (DEBUG_INIT);
-
- for (nIndexSysClkDiv = 0; nIndexSysClkDiv < nArraySize;
- nIndexSysClkDiv++) {
- /* find first sysclock divisor that isn't higher than 2.5 MHz
- clock */
- if (AHB_CLK_FREQ /
- PHYClockDivisors[nIndexSysClkDiv].unSysClkDivisor <=
- unMaxMDIOClk) {
- unClks = PHYClockDivisors[nIndexSysClkDiv].unClks;
- break;
- }
- }
-
- DEBUG_ARGS2 (DEBUG_INIT,
- "Taking MDIO Clock bit mask 0x%0x for max clock %i\n",
- unClks, unMaxMDIOClk);
-
- /* return greatest divisor */
- return unClks;
-}
-
-/***********************************************************************
- * @Function: ns9750_mii_poll_busy
- * @Return: 0 if timed out otherwise the remaing timeout
- * @Descr: waits until the MII has completed a command or it times out
- * code may be interrupted by hard interrupts.
- * It is not checked what happens on multiple actions when
- * the first is still being busy and we timeout.
- ***********************************************************************/
-
-static unsigned int ns9750_mii_poll_busy (void)
-{
- unsigned int unTimeout = 10000;
-
- DEBUG_FN (DEBUG_MII_LOW);
-
- while (((*get_eth_reg_addr (NS9750_ETH_MIND) & NS9750_ETH_MIND_BUSY)
- == NS9750_ETH_MIND_BUSY) && unTimeout)
- unTimeout--;
-
- return unTimeout;
-}
+++ /dev/null
-/******************************************************************************/
-/* */
-/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom */
-/* Corporation. */
-/* All rights reserved. */
-/* */
-/* This program is free software; you can redistribute it and/or modify */
-/* it under the terms of the GNU General Public License as published by */
-/* the Free Software Foundation, located in the file LICENSE. */
-/* */
-/* History: */
-/******************************************************************************/
-#include <common.h>
-#include <asm/types.h>
-
-#ifdef CONFIG_BMW
-#include <mpc824x.h>
-#endif
-#include <malloc.h>
-#include <linux/byteorder/big_endian.h>
-#include "bcm570x_mm.h"
-
-#define EMBEDDED 1
-/******************************************************************************/
-/* Local functions. */
-/******************************************************************************/
-
-LM_STATUS LM_Abort (PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_QueueRxPackets (PLM_DEVICE_BLOCK pDevice);
-
-static LM_STATUS LM_TranslateRequestedMediaType (LM_REQUESTED_MEDIA_TYPE
- RequestedMediaType,
- PLM_MEDIA_TYPE pMediaType,
- PLM_LINE_SPEED pLineSpeed,
- PLM_DUPLEX_MODE pDuplexMode);
-
-static LM_STATUS LM_InitBcm540xPhy (PLM_DEVICE_BLOCK pDevice);
-
-__inline static LM_VOID LM_ServiceRxInterrupt (PLM_DEVICE_BLOCK pDevice);
-__inline static LM_VOID LM_ServiceTxInterrupt (PLM_DEVICE_BLOCK pDevice);
-
-static LM_STATUS LM_ForceAutoNegBcm540xPhy (PLM_DEVICE_BLOCK pDevice,
- LM_REQUESTED_MEDIA_TYPE
- RequestedMediaType);
-static LM_STATUS LM_ForceAutoNeg (PLM_DEVICE_BLOCK pDevice,
- LM_REQUESTED_MEDIA_TYPE RequestedMediaType);
-static LM_UINT32 GetPhyAdFlowCntrlSettings (PLM_DEVICE_BLOCK pDevice);
-STATIC LM_STATUS LM_SetFlowControl (PLM_DEVICE_BLOCK pDevice,
- LM_UINT32 LocalPhyAd,
- LM_UINT32 RemotePhyAd);
-#if INCLUDE_TBI_SUPPORT
-STATIC LM_STATUS LM_SetupFiberPhy (PLM_DEVICE_BLOCK pDevice);
-STATIC LM_STATUS LM_InitBcm800xPhy (PLM_DEVICE_BLOCK pDevice);
-#endif
-STATIC LM_STATUS LM_SetupCopperPhy (PLM_DEVICE_BLOCK pDevice);
-STATIC PLM_ADAPTER_INFO LM_GetAdapterInfoBySsid (LM_UINT16 Svid,
- LM_UINT16 Ssid);
-STATIC LM_STATUS LM_DmaTest (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt,
- LM_PHYSICAL_ADDRESS BufferPhy,
- LM_UINT32 BufferSize);
-STATIC LM_STATUS LM_HaltCpu (PLM_DEVICE_BLOCK pDevice, LM_UINT32 cpu_number);
-STATIC LM_STATUS LM_ResetChip (PLM_DEVICE_BLOCK pDevice);
-STATIC LM_STATUS LM_Test4GBoundary (PLM_DEVICE_BLOCK pDevice,
- PLM_PACKET pPacket, PT3_SND_BD pSendBd);
-
-/******************************************************************************/
-/* External functions. */
-/******************************************************************************/
-
-LM_STATUS LM_LoadRlsFirmware (PLM_DEVICE_BLOCK pDevice);
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-LM_UINT32 LM_RegRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register)
-{
- LM_UINT32 Value32;
-
-#if PCIX_TARGET_WORKAROUND
- MM_ACQUIRE_UNDI_LOCK (pDevice);
-#endif
- MM_WriteConfig32 (pDevice, T3_PCI_REG_ADDR_REG, Register);
- MM_ReadConfig32 (pDevice, T3_PCI_REG_DATA_REG, &Value32);
-#if PCIX_TARGET_WORKAROUND
- MM_RELEASE_UNDI_LOCK (pDevice);
-#endif
-
- return Value32;
-} /* LM_RegRdInd */
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-LM_VOID
-LM_RegWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register, LM_UINT32 Value32)
-{
-
-#if PCIX_TARGET_WORKAROUND
- MM_ACQUIRE_UNDI_LOCK (pDevice);
-#endif
- MM_WriteConfig32 (pDevice, T3_PCI_REG_ADDR_REG, Register);
- MM_WriteConfig32 (pDevice, T3_PCI_REG_DATA_REG, Value32);
-#if PCIX_TARGET_WORKAROUND
- MM_RELEASE_UNDI_LOCK (pDevice);
-#endif
-} /* LM_RegWrInd */
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-LM_UINT32 LM_MemRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr)
-{
- LM_UINT32 Value32;
-
- MM_ACQUIRE_UNDI_LOCK (pDevice);
-#ifdef BIG_ENDIAN_HOST
- MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
- Value32 = REG_RD (pDevice, PciCfg.MemWindowData);
- /* Value32 = REG_RD(pDevice,uIntMem.Mbuf[(MemAddr & 0x7fff)/4]); */
-#else
- MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
- MM_ReadConfig32 (pDevice, T3_PCI_MEM_WIN_DATA_REG, &Value32);
-#endif
- MM_RELEASE_UNDI_LOCK (pDevice);
-
- return Value32;
-} /* LM_MemRdInd */
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-LM_VOID
-LM_MemWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr, LM_UINT32 Value32)
-{
- MM_ACQUIRE_UNDI_LOCK (pDevice);
-#ifdef BIG_ENDIAN_HOST
- REG_WR (pDevice, PciCfg.MemWindowBaseAddr, MemAddr);
- REG_WR (pDevice, uIntMem.Mbuf[(MemAddr & 0x7fff) / 4], Value32);
-#else
- MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
- MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_DATA_REG, Value32);
-#endif
- MM_RELEASE_UNDI_LOCK (pDevice);
-} /* LM_MemWrInd */
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-LM_STATUS LM_QueueRxPackets (PLM_DEVICE_BLOCK pDevice)
-{
- LM_STATUS Lmstatus;
- PLM_PACKET pPacket;
- PT3_RCV_BD pRcvBd;
- LM_UINT32 StdBdAdded = 0;
-#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- LM_UINT32 JumboBdAdded = 0;
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
-
- Lmstatus = LM_STATUS_SUCCESS;
-
- pPacket = (PLM_PACKET) QQ_PopHead (&pDevice->RxPacketFreeQ.Container);
- while (pPacket) {
- switch (pPacket->u.Rx.RcvProdRing) {
-#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- case T3_JUMBO_RCV_PROD_RING: /* Jumbo Receive Ring. */
- /* Initialize the buffer descriptor. */
- pRcvBd =
- &pDevice->pRxJumboBdVirt[pDevice->RxJumboProdIdx];
- pRcvBd->Flags =
- RCV_BD_FLAG_END | RCV_BD_FLAG_JUMBO_RING;
- pRcvBd->Len = (LM_UINT16) pDevice->RxJumboBufferSize;
-
- /* Initialize the receive buffer pointer */
-#if 0 /* Jimmy, deleted in new */
- pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low;
- pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High;
-#endif
- MM_MapRxDma (pDevice, pPacket, &pRcvBd->HostAddr);
-
- /* The opaque field may point to an offset from a fix addr. */
- pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR (pPacket) -
- MM_UINT_PTR (pDevice->
- pPacketDescBase));
-
- /* Update the producer index. */
- pDevice->RxJumboProdIdx =
- (pDevice->RxJumboProdIdx +
- 1) & T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK;
-
- JumboBdAdded++;
- break;
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
-
- case T3_STD_RCV_PROD_RING: /* Standard Receive Ring. */
- /* Initialize the buffer descriptor. */
- pRcvBd = &pDevice->pRxStdBdVirt[pDevice->RxStdProdIdx];
- pRcvBd->Flags = RCV_BD_FLAG_END;
- pRcvBd->Len = MAX_STD_RCV_BUFFER_SIZE;
-
- /* Initialize the receive buffer pointer */
-#if 0 /* Jimmy, deleted in new replaced with MM_MapRxDma */
- pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low;
- pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High;
-#endif
- MM_MapRxDma (pDevice, pPacket, &pRcvBd->HostAddr);
-
- /* The opaque field may point to an offset from a fix addr. */
- pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR (pPacket) -
- MM_UINT_PTR (pDevice->
- pPacketDescBase));
-
- /* Update the producer index. */
- pDevice->RxStdProdIdx = (pDevice->RxStdProdIdx + 1) &
- T3_STD_RCV_RCB_ENTRY_COUNT_MASK;
-
- StdBdAdded++;
- break;
-
- case T3_UNKNOWN_RCV_PROD_RING:
- default:
- Lmstatus = LM_STATUS_FAILURE;
- break;
- } /* switch */
-
- /* Bail out if there is any error. */
- if (Lmstatus != LM_STATUS_SUCCESS) {
- break;
- }
-
- pPacket =
- (PLM_PACKET) QQ_PopHead (&pDevice->RxPacketFreeQ.Container);
- } /* while */
-
- wmb ();
- /* Update the procedure index. */
- if (StdBdAdded) {
- MB_REG_WR (pDevice, Mailbox.RcvStdProdIdx.Low,
- pDevice->RxStdProdIdx);
- }
-#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- if (JumboBdAdded) {
- MB_REG_WR (pDevice, Mailbox.RcvJumboProdIdx.Low,
- pDevice->RxJumboProdIdx);
- }
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
-
- return Lmstatus;
-} /* LM_QueueRxPackets */
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-STATIC LM_VOID LM_NvramInit (PLM_DEVICE_BLOCK pDevice)
-{
- LM_UINT32 Value32;
- LM_UINT32 j;
-
- /* Intialize clock period and state machine. */
- Value32 = SEEPROM_ADDR_CLK_PERD (SEEPROM_CLOCK_PERIOD) |
- SEEPROM_ADDR_FSM_RESET;
- REG_WR (pDevice, Grc.EepromAddr, Value32);
-
- for (j = 0; j < 100; j++) {
- MM_Wait (10);
- }
-
- /* Serial eeprom access using the Grc.EepromAddr/EepromData registers. */
- Value32 = REG_RD (pDevice, Grc.LocalCtrl);
- REG_WR (pDevice, Grc.LocalCtrl,
- Value32 | GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM);
-
- /* Set the 5701 compatibility mode if we are using EEPROM. */
- if (T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
- T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5701) {
- Value32 = REG_RD (pDevice, Nvram.Config1);
- if ((Value32 & FLASH_INTERFACE_ENABLE) == 0) {
- /* Use the new interface to read EEPROM. */
- Value32 &= ~FLASH_COMPAT_BYPASS;
-
- REG_WR (pDevice, Nvram.Config1, Value32);
- }
- }
-} /* LM_NvRamInit */
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-STATIC LM_STATUS
-LM_EepromRead (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, LM_UINT32 * pData)
-{
- LM_UINT32 Value32;
- LM_UINT32 Addr;
- LM_UINT32 Dev;
- LM_UINT32 j;
-
- if (Offset > SEEPROM_CHIP_SIZE) {
- return LM_STATUS_FAILURE;
- }
-
- Dev = Offset / SEEPROM_CHIP_SIZE;
- Addr = Offset % SEEPROM_CHIP_SIZE;
-
- Value32 = REG_RD (pDevice, Grc.EepromAddr);
- Value32 &= ~(SEEPROM_ADDR_ADDRESS_MASK | SEEPROM_ADDR_DEV_ID_MASK |
- SEEPROM_ADDR_RW_MASK);
- REG_WR (pDevice, Grc.EepromAddr, Value32 | SEEPROM_ADDR_DEV_ID (Dev) |
- SEEPROM_ADDR_ADDRESS (Addr) | SEEPROM_ADDR_START |
- SEEPROM_ADDR_READ);
-
- for (j = 0; j < 1000; j++) {
- Value32 = REG_RD (pDevice, Grc.EepromAddr);
- if (Value32 & SEEPROM_ADDR_COMPLETE) {
- break;
- }
- MM_Wait (10);
- }
-
- if (Value32 & SEEPROM_ADDR_COMPLETE) {
- Value32 = REG_RD (pDevice, Grc.EepromData);
- *pData = Value32;
-
- return LM_STATUS_SUCCESS;
- }
-
- return LM_STATUS_FAILURE;
-} /* LM_EepromRead */
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-STATIC LM_STATUS
-LM_NvramRead (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, LM_UINT32 * pData)
-{
- LM_UINT32 Value32;
- LM_STATUS Status;
- LM_UINT32 j;
-
- if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
- Status = LM_EepromRead (pDevice, Offset, pData);
- } else {
- /* Determine if we have flash or EEPROM. */
- Value32 = REG_RD (pDevice, Nvram.Config1);
- if (Value32 & FLASH_INTERFACE_ENABLE) {
- if (Value32 & FLASH_SSRAM_BUFFERRED_MODE) {
- Offset = ((Offset / BUFFERED_FLASH_PAGE_SIZE) <<
- BUFFERED_FLASH_PAGE_POS) +
- (Offset % BUFFERED_FLASH_PAGE_SIZE);
- }
- }
-
- REG_WR (pDevice, Nvram.SwArb, SW_ARB_REQ_SET1);
- for (j = 0; j < 1000; j++) {
- if (REG_RD (pDevice, Nvram.SwArb) & SW_ARB_GNT1) {
- break;
- }
- MM_Wait (20);
- }
- if (j == 1000) {
- return LM_STATUS_FAILURE;
- }
-
- /* Read from flash or EEPROM with the new 5703/02 interface. */
- REG_WR (pDevice, Nvram.Addr, Offset & NVRAM_ADDRESS_MASK);
-
- REG_WR (pDevice, Nvram.Cmd, NVRAM_CMD_RD | NVRAM_CMD_DO_IT |
- NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
-
- /* Wait for the done bit to clear. */
- for (j = 0; j < 500; j++) {
- MM_Wait (10);
-
- Value32 = REG_RD (pDevice, Nvram.Cmd);
- if (!(Value32 & NVRAM_CMD_DONE)) {
- break;
- }
- }
-
- /* Wait for the done bit. */
- if (!(Value32 & NVRAM_CMD_DONE)) {
- for (j = 0; j < 500; j++) {
- MM_Wait (10);
-
- Value32 = REG_RD (pDevice, Nvram.Cmd);
- if (Value32 & NVRAM_CMD_DONE) {
- MM_Wait (10);
-
- *pData =
- REG_RD (pDevice, Nvram.ReadData);
-
- /* Change the endianess. */
- *pData =
- ((*pData & 0xff) << 24) |
- ((*pData & 0xff00) << 8) |
- ((*pData & 0xff0000) >> 8) |
- ((*pData >> 24) & 0xff);
-
- break;
- }
- }
- }
-
- REG_WR (pDevice, Nvram.SwArb, SW_ARB_REQ_CLR1);
- if (Value32 & NVRAM_CMD_DONE) {
- Status = LM_STATUS_SUCCESS;
- } else {
- Status = LM_STATUS_FAILURE;
- }
- }
-
- return Status;
-} /* LM_NvramRead */
-
-STATIC void LM_ReadVPD (PLM_DEVICE_BLOCK pDevice)
-{
- LM_UINT32 Vpd_arr[256 / 4];
- LM_UINT8 *Vpd = (LM_UINT8 *) & Vpd_arr[0];
- LM_UINT32 *Vpd_dptr = &Vpd_arr[0];
- LM_UINT32 Value32;
- unsigned int j;
-
- /* Read PN from VPD */
- for (j = 0; j < 256; j += 4, Vpd_dptr++) {
- if (LM_NvramRead (pDevice, 0x100 + j, &Value32) !=
- LM_STATUS_SUCCESS) {
- printf ("BCM570x: LM_ReadVPD: VPD read failed"
- " (no EEPROM onboard)\n");
- return;
- }
- *Vpd_dptr = cpu_to_le32 (Value32);
- }
- for (j = 0; j < 256;) {
- unsigned int Vpd_r_len;
- unsigned int Vpd_r_end;
-
- if ((Vpd[j] == 0x82) || (Vpd[j] == 0x91)) {
- j = j + 3 + Vpd[j + 1] + (Vpd[j + 2] << 8);
- } else if (Vpd[j] == 0x90) {
- Vpd_r_len = Vpd[j + 1] + (Vpd[j + 2] << 8);
- j += 3;
- Vpd_r_end = Vpd_r_len + j;
- while (j < Vpd_r_end) {
- if ((Vpd[j] == 'P') && (Vpd[j + 1] == 'N')) {
- unsigned int len = Vpd[j + 2];
-
- if (len <= 24) {
- memcpy (pDevice->PartNo,
- &Vpd[j + 3], len);
- }
- break;
- } else {
- if (Vpd[j + 2] == 0) {
- break;
- }
- j = j + Vpd[j + 2];
- }
- }
- break;
- } else {
- break;
- }
- }
-}
-
-STATIC void LM_ReadBootCodeVersion (PLM_DEVICE_BLOCK pDevice)
-{
- LM_UINT32 Value32, offset, ver_offset;
- int i;
-
- if (LM_NvramRead (pDevice, 0x0, &Value32) != LM_STATUS_SUCCESS)
- return;
- if (Value32 != 0xaa559966)
- return;
- if (LM_NvramRead (pDevice, 0xc, &offset) != LM_STATUS_SUCCESS)
- return;
-
- offset = ((offset & 0xff) << 24) | ((offset & 0xff00) << 8) |
- ((offset & 0xff0000) >> 8) | ((offset >> 24) & 0xff);
- if (LM_NvramRead (pDevice, offset, &Value32) != LM_STATUS_SUCCESS)
- return;
- if ((Value32 == 0x0300000e) &&
- (LM_NvramRead (pDevice, offset + 4, &Value32) == LM_STATUS_SUCCESS)
- && (Value32 == 0)) {
-
- if (LM_NvramRead (pDevice, offset + 8, &ver_offset) !=
- LM_STATUS_SUCCESS)
- return;
- ver_offset = ((ver_offset & 0xff0000) >> 8) |
- ((ver_offset >> 24) & 0xff);
- for (i = 0; i < 16; i += 4) {
- if (LM_NvramRead
- (pDevice, offset + ver_offset + i,
- &Value32) != LM_STATUS_SUCCESS) {
- return;
- }
- *((LM_UINT32 *) & pDevice->BootCodeVer[i]) =
- cpu_to_le32 (Value32);
- }
- } else {
- char c;
-
- if (LM_NvramRead (pDevice, 0x94, &Value32) != LM_STATUS_SUCCESS)
- return;
-
- i = 0;
- c = ((Value32 & 0xff0000) >> 16);
-
- if (c < 10) {
- pDevice->BootCodeVer[i++] = c + '0';
- } else {
- pDevice->BootCodeVer[i++] = (c / 10) + '0';
- pDevice->BootCodeVer[i++] = (c % 10) + '0';
- }
- pDevice->BootCodeVer[i++] = '.';
- c = (Value32 & 0xff000000) >> 24;
- if (c < 10) {
- pDevice->BootCodeVer[i++] = c + '0';
- } else {
- pDevice->BootCodeVer[i++] = (c / 10) + '0';
- pDevice->BootCodeVer[i++] = (c % 10) + '0';
- }
- pDevice->BootCodeVer[i] = 0;
- }
-}
-
-STATIC void LM_GetBusSpeed (PLM_DEVICE_BLOCK pDevice)
-{
- LM_UINT32 PciState = pDevice->PciState;
- LM_UINT32 ClockCtrl;
- char *SpeedStr = "";
-
- if (PciState & T3_PCI_STATE_32BIT_PCI_BUS) {
- strcpy (pDevice->BusSpeedStr, "32-bit ");
- } else {
- strcpy (pDevice->BusSpeedStr, "64-bit ");
- }
- if (PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) {
- strcat (pDevice->BusSpeedStr, "PCI ");
- if (PciState & T3_PCI_STATE_HIGH_BUS_SPEED) {
- SpeedStr = "66MHz";
- } else {
- SpeedStr = "33MHz";
- }
- } else {
- strcat (pDevice->BusSpeedStr, "PCIX ");
- if (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE) {
- SpeedStr = "133MHz";
- } else {
- ClockCtrl = REG_RD (pDevice, PciCfg.ClockCtrl) & 0x1f;
- switch (ClockCtrl) {
- case 0:
- SpeedStr = "33MHz";
- break;
-
- case 2:
- SpeedStr = "50MHz";
- break;
-
- case 4:
- SpeedStr = "66MHz";
- break;
-
- case 6:
- SpeedStr = "100MHz";
- break;
-
- case 7:
- SpeedStr = "133MHz";
- break;
- }
- }
- }
- strcat (pDevice->BusSpeedStr, SpeedStr);
-}
-
-/******************************************************************************/
-/* Description: */
-/* This routine initializes default parameters and reads the PCI */
-/* configurations. */
-/* */
-/* Return: */
-/* LM_STATUS_SUCCESS */
-/******************************************************************************/
-LM_STATUS LM_GetAdapterInfo (PLM_DEVICE_BLOCK pDevice)
-{
- PLM_ADAPTER_INFO pAdapterInfo;
- LM_UINT32 Value32;
- LM_STATUS Status;
- LM_UINT32 j;
- LM_UINT32 EeSigFound;
- LM_UINT32 EePhyTypeSerdes = 0;
- LM_UINT32 EePhyLedMode = 0;
- LM_UINT32 EePhyId = 0;
-
- /* Get Device Id and Vendor Id */
- Status = MM_ReadConfig32 (pDevice, PCI_VENDOR_ID_REG, &Value32);
- if (Status != LM_STATUS_SUCCESS) {
- return Status;
- }
- pDevice->PciVendorId = (LM_UINT16) Value32;
- pDevice->PciDeviceId = (LM_UINT16) (Value32 >> 16);
-
- /* If we are not getting the write adapter, exit. */
- if ((Value32 != T3_PCI_ID_BCM5700) &&
- (Value32 != T3_PCI_ID_BCM5701) &&
- (Value32 != T3_PCI_ID_BCM5702) &&
- (Value32 != T3_PCI_ID_BCM5702x) &&
- (Value32 != T3_PCI_ID_BCM5702FE) &&
- (Value32 != T3_PCI_ID_BCM5703) &&
- (Value32 != T3_PCI_ID_BCM5703x) && (Value32 != T3_PCI_ID_BCM5704)) {
- return LM_STATUS_FAILURE;
- }
-
- Status = MM_ReadConfig32 (pDevice, PCI_REV_ID_REG, &Value32);
- if (Status != LM_STATUS_SUCCESS) {
- return Status;
- }
- pDevice->PciRevId = (LM_UINT8) Value32;
-
- /* Get IRQ. */
- Status = MM_ReadConfig32 (pDevice, PCI_INT_LINE_REG, &Value32);
- if (Status != LM_STATUS_SUCCESS) {
- return Status;
- }
- pDevice->Irq = (LM_UINT8) Value32;
-
- /* Get interrupt pin. */
- pDevice->IntPin = (LM_UINT8) (Value32 >> 8);
-
- /* Get chip revision id. */
- Status = MM_ReadConfig32 (pDevice, T3_PCI_MISC_HOST_CTRL_REG, &Value32);
- pDevice->ChipRevId = Value32 >> 16;
-
- /* Get subsystem vendor. */
- Status =
- MM_ReadConfig32 (pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, &Value32);
- if (Status != LM_STATUS_SUCCESS) {
- return Status;
- }
- pDevice->SubsystemVendorId = (LM_UINT16) Value32;
-
- /* Get PCI subsystem id. */
- pDevice->SubsystemId = (LM_UINT16) (Value32 >> 16);
-
- /* Get the cache line size. */
- MM_ReadConfig32 (pDevice, PCI_CACHE_LINE_SIZE_REG, &Value32);
- pDevice->CacheLineSize = (LM_UINT8) Value32;
- pDevice->SavedCacheLineReg = Value32;
-
- if (pDevice->ChipRevId != T3_CHIP_ID_5703_A1 &&
- pDevice->ChipRevId != T3_CHIP_ID_5703_A2 &&
- pDevice->ChipRevId != T3_CHIP_ID_5704_A0) {
- pDevice->UndiFix = FALSE;
- }
-#if !PCIX_TARGET_WORKAROUND
- pDevice->UndiFix = FALSE;
-#endif
- /* Map the memory base to system address space. */
- if (!pDevice->UndiFix) {
- Status = MM_MapMemBase (pDevice);
- if (Status != LM_STATUS_SUCCESS) {
- return Status;
- }
- /* Initialize the memory view pointer. */
- pDevice->pMemView = (PT3_STD_MEM_MAP) pDevice->pMappedMemBase;
- }
-#if PCIX_TARGET_WORKAROUND
- /* store whether we are in PCI are PCI-X mode */
- pDevice->EnablePciXFix = FALSE;
-
- MM_ReadConfig32 (pDevice, T3_PCI_STATE_REG, &Value32);
- if ((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0) {
- /* Enable PCI-X workaround only if we are running on 5700 BX. */
- if (T3_CHIP_REV (pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) {
- pDevice->EnablePciXFix = TRUE;
- }
- }
- if (pDevice->UndiFix) {
- pDevice->EnablePciXFix = TRUE;
- }
-#endif
- /* Bx bug: due to the "byte_enable bug" in PCI-X mode, the power */
- /* management register may be clobbered which may cause the */
- /* BCM5700 to go into D3 state. While in this state, we will */
- /* not have memory mapped register access. As a workaround, we */
- /* need to restore the device to D0 state. */
- MM_ReadConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, &Value32);
- Value32 |= T3_PM_PME_ASSERTED;
- Value32 &= ~T3_PM_POWER_STATE_MASK;
- Value32 |= T3_PM_POWER_STATE_D0;
- MM_WriteConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, Value32);
-
- /* read the current PCI command word */
- MM_ReadConfig32 (pDevice, PCI_COMMAND_REG, &Value32);
-
- /* Make sure bus-mastering is enabled. */
- Value32 |= PCI_BUSMASTER_ENABLE;
-
-#if PCIX_TARGET_WORKAROUND
- /* if we are in PCI-X mode, also make sure mem-mapping and SERR#/PERR#
- are enabled */
- if (pDevice->EnablePciXFix == TRUE) {
- Value32 |= (PCI_MEM_SPACE_ENABLE | PCI_SYSTEM_ERROR_ENABLE |
- PCI_PARITY_ERROR_ENABLE);
- }
- if (pDevice->UndiFix) {
- Value32 &= ~PCI_MEM_SPACE_ENABLE;
- }
-#endif
-
- if (pDevice->EnableMWI) {
- Value32 |= PCI_MEMORY_WRITE_INVALIDATE;
- } else {
- Value32 &= (~PCI_MEMORY_WRITE_INVALIDATE);
- }
-
- /* Error out if mem-mapping is NOT enabled for PCI systems */
- if (!(Value32 | PCI_MEM_SPACE_ENABLE)) {
- return LM_STATUS_FAILURE;
- }
-
- /* save the value we are going to write into the PCI command word */
- pDevice->PciCommandStatusWords = Value32;
-
- Status = MM_WriteConfig32 (pDevice, PCI_COMMAND_REG, Value32);
- if (Status != LM_STATUS_SUCCESS) {
- return Status;
- }
-
- /* Set power state to D0. */
- LM_SetPowerState (pDevice, LM_POWER_STATE_D0);
-
-#ifdef BIG_ENDIAN_PCI
- pDevice->MiscHostCtrl =
- MISC_HOST_CTRL_MASK_PCI_INT |
- MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS |
- MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP |
- MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW;
-#else /* No CPU Swap modes for PCI IO */
-
- /* Setup the mode registers. */
- pDevice->MiscHostCtrl =
- MISC_HOST_CTRL_MASK_PCI_INT |
- MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP |
-#ifdef BIG_ENDIAN_HOST
- MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP |
-#endif /* BIG_ENDIAN_HOST */
- MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS |
- MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW;
-#endif /* !BIG_ENDIAN_PCI */
-
- /* write to PCI misc host ctr first in order to enable indirect accesses */
- MM_WriteConfig32 (pDevice, T3_PCI_MISC_HOST_CTRL_REG,
- pDevice->MiscHostCtrl);
-
- REG_WR (pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl);
-
-#ifdef BIG_ENDIAN_PCI
- Value32 = GRC_MODE_WORD_SWAP_DATA | GRC_MODE_WORD_SWAP_NON_FRAME_DATA;
-#else
-/* No CPU Swap modes for PCI IO */
-#ifdef BIG_ENDIAN_HOST
- Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
- GRC_MODE_WORD_SWAP_NON_FRAME_DATA;
-#else
- Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA;
-#endif
-#endif /* !BIG_ENDIAN_PCI */
-
- REG_WR (pDevice, Grc.Mode, Value32);
-
- if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
- REG_WR (pDevice, Grc.LocalCtrl,
- GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
- GRC_MISC_LOCAL_CTRL_GPIO_OE1);
- }
- MM_Wait (40);
-
- /* Enable indirect memory access */
- REG_WR (pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE);
-
- if (REG_RD (pDevice, PciCfg.ClockCtrl) & T3_PCI_44MHZ_CORE_CLOCK) {
- REG_WR (pDevice, PciCfg.ClockCtrl, T3_PCI_44MHZ_CORE_CLOCK |
- T3_PCI_SELECT_ALTERNATE_CLOCK);
- REG_WR (pDevice, PciCfg.ClockCtrl,
- T3_PCI_SELECT_ALTERNATE_CLOCK);
- MM_Wait (40); /* required delay is 27usec */
- }
- REG_WR (pDevice, PciCfg.ClockCtrl, 0);
- REG_WR (pDevice, PciCfg.MemWindowBaseAddr, 0);
-
-#if PCIX_TARGET_WORKAROUND
- MM_ReadConfig32 (pDevice, T3_PCI_STATE_REG, &Value32);
- if ((pDevice->EnablePciXFix == FALSE) &&
- ((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0)) {
- if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
- pDevice->ChipRevId == T3_CHIP_ID_5701_B0 ||
- pDevice->ChipRevId == T3_CHIP_ID_5701_B2 ||
- pDevice->ChipRevId == T3_CHIP_ID_5701_B5) {
- __raw_writel (0,
- &(pDevice->pMemView->uIntMem.
- MemBlock32K[0x300]));
- __raw_writel (0,
- &(pDevice->pMemView->uIntMem.
- MemBlock32K[0x301]));
- __raw_writel (0xffffffff,
- &(pDevice->pMemView->uIntMem.
- MemBlock32K[0x301]));
- if (__raw_readl
- (&(pDevice->pMemView->uIntMem.MemBlock32K[0x300])))
- {
- pDevice->EnablePciXFix = TRUE;
- }
- }
- }
-#endif
-#if 1
- /*
- * This code was at the beginning of else block below, but that's
- * a bug if node address in shared memory.
- */
- MM_Wait (50);
- LM_NvramInit (pDevice);
-#endif
- /* Get the node address. First try to get in from the shared memory. */
- /* If the signature is not present, then get it from the NVRAM. */
- Value32 = MEM_RD_OFFSET (pDevice, T3_MAC_ADDR_HIGH_MAILBOX);
- if ((Value32 >> 16) == 0x484b) {
-
- pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 8);
- pDevice->NodeAddress[1] = (LM_UINT8) Value32;
-
- Value32 = MEM_RD_OFFSET (pDevice, T3_MAC_ADDR_LOW_MAILBOX);
-
- pDevice->NodeAddress[2] = (LM_UINT8) (Value32 >> 24);
- pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 16);
- pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 8);
- pDevice->NodeAddress[5] = (LM_UINT8) Value32;
-
- Status = LM_STATUS_SUCCESS;
- } else {
- Status = LM_NvramRead (pDevice, 0x7c, &Value32);
- if (Status == LM_STATUS_SUCCESS) {
- pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 16);
- pDevice->NodeAddress[1] = (LM_UINT8) (Value32 >> 24);
-
- Status = LM_NvramRead (pDevice, 0x80, &Value32);
-
- pDevice->NodeAddress[2] = (LM_UINT8) Value32;
- pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 8);
- pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 16);
- pDevice->NodeAddress[5] = (LM_UINT8) (Value32 >> 24);
- }
- }
-
- /* Assign a default address. */
- if (Status != LM_STATUS_SUCCESS) {
-#ifndef EMBEDDED
- printk (KERN_ERR
- "Cannot get MAC addr from NVRAM. Using default.\n");
-#endif
- pDevice->NodeAddress[0] = 0x00;
- pDevice->NodeAddress[1] = 0x10;
- pDevice->NodeAddress[2] = 0x18;
- pDevice->NodeAddress[3] = 0x68;
- pDevice->NodeAddress[4] = 0x61;
- pDevice->NodeAddress[5] = 0x76;
- }
-
- pDevice->PermanentNodeAddress[0] = pDevice->NodeAddress[0];
- pDevice->PermanentNodeAddress[1] = pDevice->NodeAddress[1];
- pDevice->PermanentNodeAddress[2] = pDevice->NodeAddress[2];
- pDevice->PermanentNodeAddress[3] = pDevice->NodeAddress[3];
- pDevice->PermanentNodeAddress[4] = pDevice->NodeAddress[4];
- pDevice->PermanentNodeAddress[5] = pDevice->NodeAddress[5];
-
- /* Initialize the default values. */
- pDevice->NoTxPseudoHdrChksum = FALSE;
- pDevice->NoRxPseudoHdrChksum = FALSE;
- pDevice->NicSendBd = FALSE;
- pDevice->TxPacketDescCnt = DEFAULT_TX_PACKET_DESC_COUNT;
- pDevice->RxStdDescCnt = DEFAULT_STD_RCV_DESC_COUNT;
- pDevice->RxCoalescingTicks = DEFAULT_RX_COALESCING_TICKS;
- pDevice->TxCoalescingTicks = DEFAULT_TX_COALESCING_TICKS;
- pDevice->RxMaxCoalescedFrames = DEFAULT_RX_MAX_COALESCED_FRAMES;
- pDevice->TxMaxCoalescedFrames = DEFAULT_TX_MAX_COALESCED_FRAMES;
- pDevice->RxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE;
- pDevice->TxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE;
- pDevice->RxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE;
- pDevice->TxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE;
- pDevice->StatsCoalescingTicks = DEFAULT_STATS_COALESCING_TICKS;
- pDevice->EnableMWI = FALSE;
- pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
- pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
- pDevice->DisableAutoNeg = FALSE;
- pDevice->PhyIntMode = T3_PHY_INT_MODE_AUTO;
- pDevice->LinkChngMode = T3_LINK_CHNG_MODE_AUTO;
- pDevice->LedMode = LED_MODE_AUTO;
- pDevice->ResetPhyOnInit = TRUE;
- pDevice->DelayPciGrant = TRUE;
- pDevice->UseTaggedStatus = FALSE;
- pDevice->OneDmaAtOnce = BAD_DEFAULT_VALUE;
-
- pDevice->DmaMbufLowMark = T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO;
- pDevice->RxMacMbufLowMark = T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO;
- pDevice->MbufHighMark = T3_DEF_MBUF_HIGH_WMARK_JUMBO;
-
- pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_AUTO;
- pDevice->TaskOffloadCap = LM_TASK_OFFLOAD_NONE;
- pDevice->FlowControlCap = LM_FLOW_CONTROL_AUTO_PAUSE;
- pDevice->EnableTbi = FALSE;
-#if INCLUDE_TBI_SUPPORT
- pDevice->PollTbiLink = BAD_DEFAULT_VALUE;
-#endif
-
- switch (T3_ASIC_REV (pDevice->ChipRevId)) {
- case T3_ASIC_REV_5704:
- pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR;
- pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE64;
- break;
- default:
- pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR;
- pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE96;
- break;
- }
-
- pDevice->LinkStatus = LM_STATUS_LINK_DOWN;
- pDevice->QueueRxPackets = TRUE;
-
- pDevice->EnableWireSpeed = TRUE;
-
-#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT;
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
-
- /* Make this is a known adapter. */
- pAdapterInfo = LM_GetAdapterInfoBySsid (pDevice->SubsystemVendorId,
- pDevice->SubsystemId);
-
- pDevice->BondId = REG_RD (pDevice, Grc.MiscCfg) & GRC_MISC_BD_ID_MASK;
- if (pDevice->BondId != GRC_MISC_BD_ID_5700 &&
- pDevice->BondId != GRC_MISC_BD_ID_5701 &&
- pDevice->BondId != GRC_MISC_BD_ID_5702FE &&
- pDevice->BondId != GRC_MISC_BD_ID_5703 &&
- pDevice->BondId != GRC_MISC_BD_ID_5703S &&
- pDevice->BondId != GRC_MISC_BD_ID_5704 &&
- pDevice->BondId != GRC_MISC_BD_ID_5704CIOBE) {
- return LM_STATUS_UNKNOWN_ADAPTER;
- }
-
- pDevice->SplitModeEnable = SPLIT_MODE_DISABLE;
- if ((pDevice->ChipRevId == T3_CHIP_ID_5704_A0) &&
- (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE)) {
- pDevice->SplitModeEnable = SPLIT_MODE_ENABLE;
- pDevice->SplitModeMaxReq = SPLIT_MODE_5704_MAX_REQ;
- }
-
- /* Get Eeprom info. */
- Value32 = MEM_RD_OFFSET (pDevice, T3_NIC_DATA_SIG_ADDR);
- if (Value32 == T3_NIC_DATA_SIG) {
- EeSigFound = TRUE;
- Value32 = MEM_RD_OFFSET (pDevice, T3_NIC_DATA_NIC_CFG_ADDR);
-
- /* Determine PHY type. */
- switch (Value32 & T3_NIC_CFG_PHY_TYPE_MASK) {
- case T3_NIC_CFG_PHY_TYPE_COPPER:
- EePhyTypeSerdes = FALSE;
- break;
-
- case T3_NIC_CFG_PHY_TYPE_FIBER:
- EePhyTypeSerdes = TRUE;
- break;
-
- default:
- EePhyTypeSerdes = FALSE;
- break;
- }
-
- /* Determine PHY led mode. */
- if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
- switch (Value32 & T3_NIC_CFG_LED_MODE_MASK) {
- case T3_NIC_CFG_LED_MODE_TRIPLE_SPEED:
- EePhyLedMode = LED_MODE_THREE_LINK;
- break;
-
- case T3_NIC_CFG_LED_MODE_LINK_SPEED:
- EePhyLedMode = LED_MODE_LINK10;
- break;
-
- default:
- EePhyLedMode = LED_MODE_AUTO;
- break;
- }
- } else {
- switch (Value32 & T3_NIC_CFG_LED_MODE_MASK) {
- case T3_NIC_CFG_LED_MODE_OPEN_DRAIN:
- EePhyLedMode = LED_MODE_OPEN_DRAIN;
- break;
-
- case T3_NIC_CFG_LED_MODE_OUTPUT:
- EePhyLedMode = LED_MODE_OUTPUT;
- break;
-
- default:
- EePhyLedMode = LED_MODE_AUTO;
- break;
- }
- }
- if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1 ||
- pDevice->ChipRevId == T3_CHIP_ID_5703_A2) {
- /* Enable EEPROM write protection. */
- if (Value32 & T3_NIC_EEPROM_WP) {
- pDevice->EepromWp = TRUE;
- }
- }
-
- /* Get the PHY Id. */
- Value32 = MEM_RD_OFFSET (pDevice, T3_NIC_DATA_PHY_ID_ADDR);
- if (Value32) {
- EePhyId = (((Value32 & T3_NIC_PHY_ID1_MASK) >> 16) &
- PHY_ID1_OUI_MASK) << 10;
-
- Value32 = Value32 & T3_NIC_PHY_ID2_MASK;
-
- EePhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) |
- (Value32 & PHY_ID2_MODEL_MASK) | (Value32 &
- PHY_ID2_REV_MASK);
- } else {
- EePhyId = 0;
- }
- } else {
- EeSigFound = FALSE;
- }
-
- /* Set the PHY address. */
- pDevice->PhyAddr = PHY_DEVICE_ID;
-
- /* Disable auto polling. */
- pDevice->MiMode = 0xc0000;
- REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode);
- MM_Wait (40);
-
- /* Get the PHY id. */
- LM_ReadPhy (pDevice, PHY_ID1_REG, &Value32);
- pDevice->PhyId = (Value32 & PHY_ID1_OUI_MASK) << 10;
-
- LM_ReadPhy (pDevice, PHY_ID2_REG, &Value32);
- pDevice->PhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) |
- (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK);
-
- /* Set the EnableTbi flag to false if we have a copper PHY. */
- switch (pDevice->PhyId & PHY_ID_MASK) {
- case PHY_BCM5400_PHY_ID:
- pDevice->EnableTbi = FALSE;
- break;
-
- case PHY_BCM5401_PHY_ID:
- pDevice->EnableTbi = FALSE;
- break;
-
- case PHY_BCM5411_PHY_ID:
- pDevice->EnableTbi = FALSE;
- break;
-
- case PHY_BCM5701_PHY_ID:
- pDevice->EnableTbi = FALSE;
- break;
-
- case PHY_BCM5703_PHY_ID:
- pDevice->EnableTbi = FALSE;
- break;
-
- case PHY_BCM5704_PHY_ID:
- pDevice->EnableTbi = FALSE;
- break;
-
- case PHY_BCM8002_PHY_ID:
- pDevice->EnableTbi = TRUE;
- break;
-
- default:
-
- if (pAdapterInfo) {
- pDevice->PhyId = pAdapterInfo->PhyId;
- pDevice->EnableTbi = pAdapterInfo->Serdes;
- } else if (EeSigFound) {
- pDevice->PhyId = EePhyId;
- pDevice->EnableTbi = EePhyTypeSerdes;
- }
- break;
- }
-
- /* Bail out if we don't know the copper PHY id. */
- if (UNKNOWN_PHY_ID (pDevice->PhyId) && !pDevice->EnableTbi) {
- return LM_STATUS_FAILURE;
- }
-
- if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5703) {
- if ((pDevice->SavedCacheLineReg & 0xff00) < 0x4000) {
- pDevice->SavedCacheLineReg &= 0xffff00ff;
- pDevice->SavedCacheLineReg |= 0x4000;
- }
- }
- /* Change driver parameters. */
- Status = MM_GetConfig (pDevice);
- if (Status != LM_STATUS_SUCCESS) {
- return Status;
- }
-#if INCLUDE_5701_AX_FIX
- if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
- pDevice->ChipRevId == T3_CHIP_ID_5701_B0) {
- pDevice->ResetPhyOnInit = TRUE;
- }
-#endif
-
- /* Save the current phy link status. */
- if (!pDevice->EnableTbi) {
- LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
- LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
-
- /* If we don't have link reset the PHY. */
- if (!(Value32 & PHY_STATUS_LINK_PASS)
- || pDevice->ResetPhyOnInit) {
-
- LM_WritePhy (pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET);
-
- for (j = 0; j < 100; j++) {
- MM_Wait (10);
-
- LM_ReadPhy (pDevice, PHY_CTRL_REG, &Value32);
- if (Value32 && !(Value32 & PHY_CTRL_PHY_RESET)) {
- MM_Wait (40);
- break;
- }
- }
-
-#if INCLUDE_5701_AX_FIX
- /* 5701_AX_BX bug: only advertises 10mb speed. */
- if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
- pDevice->ChipRevId == T3_CHIP_ID_5701_B0) {
-
- Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD |
- PHY_AN_AD_10BASET_HALF |
- PHY_AN_AD_10BASET_FULL |
- PHY_AN_AD_100BASETX_FULL |
- PHY_AN_AD_100BASETX_HALF;
- Value32 |= GetPhyAdFlowCntrlSettings (pDevice);
- LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32);
- pDevice->advertising = Value32;
-
- Value32 = BCM540X_AN_AD_1000BASET_HALF |
- BCM540X_AN_AD_1000BASET_FULL |
- BCM540X_CONFIG_AS_MASTER |
- BCM540X_ENABLE_CONFIG_AS_MASTER;
- LM_WritePhy (pDevice,
- BCM540X_1000BASET_CTRL_REG,
- Value32);
- pDevice->advertising1000 = Value32;
-
- LM_WritePhy (pDevice, PHY_CTRL_REG,
- PHY_CTRL_AUTO_NEG_ENABLE |
- PHY_CTRL_RESTART_AUTO_NEG);
- }
-#endif
- if (T3_ASIC_REV (pDevice->ChipRevId) ==
- T3_ASIC_REV_5703) {
- LM_WritePhy (pDevice, 0x18, 0x0c00);
- LM_WritePhy (pDevice, 0x17, 0x201f);
- LM_WritePhy (pDevice, 0x15, 0x2aaa);
- }
- if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) {
- LM_WritePhy (pDevice, 0x1c, 0x8d68);
- LM_WritePhy (pDevice, 0x1c, 0x8d68);
- }
- /* Enable Ethernet@WireSpeed. */
- if (pDevice->EnableWireSpeed) {
- LM_WritePhy (pDevice, 0x18, 0x7007);
- LM_ReadPhy (pDevice, 0x18, &Value32);
- LM_WritePhy (pDevice, 0x18,
- Value32 | BIT_15 | BIT_4);
- }
- }
- }
-
- /* Turn off tap power management. */
- if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) {
- LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x0c20);
- LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012);
- LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x1804);
- LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013);
- LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x1204);
- LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
- LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0132);
- LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
- LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0232);
- LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f);
- LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0a20);
-
- MM_Wait (40);
- }
-#if INCLUDE_TBI_SUPPORT
- pDevice->IgnoreTbiLinkChange = FALSE;
-
- if (pDevice->EnableTbi) {
- pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_NONE;
- pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY;
- if ((pDevice->PollTbiLink == BAD_DEFAULT_VALUE) ||
- pDevice->DisableAutoNeg) {
- pDevice->PollTbiLink = FALSE;
- }
- } else {
- pDevice->PollTbiLink = FALSE;
- }
-#endif /* INCLUDE_TBI_SUPPORT */
-
- /* UseTaggedStatus is only valid for 5701 and later. */
- if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
- pDevice->UseTaggedStatus = FALSE;
-
- pDevice->CoalesceMode = 0;
- } else {
- pDevice->CoalesceMode =
- HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT |
- HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT;
- }
-
- /* Set the status block size. */
- if (T3_CHIP_REV (pDevice->ChipRevId) != T3_CHIP_REV_5700_AX &&
- T3_CHIP_REV (pDevice->ChipRevId) != T3_CHIP_REV_5700_BX) {
- pDevice->CoalesceMode |= HOST_COALESCE_32_BYTE_STATUS_MODE;
- }
-
- /* Check the DURING_INT coalescing ticks parameters. */
- if (pDevice->UseTaggedStatus) {
- if (pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) {
- pDevice->RxCoalescingTicksDuringInt =
- DEFAULT_RX_COALESCING_TICKS_DURING_INT;
- }
-
- if (pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) {
- pDevice->TxCoalescingTicksDuringInt =
- DEFAULT_TX_COALESCING_TICKS_DURING_INT;
- }
-
- if (pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) {
- pDevice->RxMaxCoalescedFramesDuringInt =
- DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT;
- }
-
- if (pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) {
- pDevice->TxMaxCoalescedFramesDuringInt =
- DEFAULT_TX_MAX_COALESCED_FRAMES_DURING_INT;
- }
- } else {
- if (pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) {
- pDevice->RxCoalescingTicksDuringInt = 0;
- }
-
- if (pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) {
- pDevice->TxCoalescingTicksDuringInt = 0;
- }
-
- if (pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) {
- pDevice->RxMaxCoalescedFramesDuringInt = 0;
- }
-
- if (pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) {
- pDevice->TxMaxCoalescedFramesDuringInt = 0;
- }
- }
-
-#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- if (pDevice->RxMtu <= (MAX_STD_RCV_BUFFER_SIZE - 8 /* CRC */ )) {
- pDevice->RxJumboDescCnt = 0;
- if (pDevice->RxMtu <= MAX_ETHERNET_PACKET_SIZE_NO_CRC) {
- pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
- }
- } else {
- pDevice->RxJumboBufferSize =
- (pDevice->RxMtu + 8 /* CRC + VLAN */ +
- COMMON_CACHE_LINE_SIZE - 1) & ~COMMON_CACHE_LINE_MASK;
-
- if (pDevice->RxJumboBufferSize > MAX_JUMBO_RCV_BUFFER_SIZE) {
- pDevice->RxJumboBufferSize =
- DEFAULT_JUMBO_RCV_BUFFER_SIZE;
- pDevice->RxMtu =
- pDevice->RxJumboBufferSize - 8 /* CRC + VLAN */ ;
- }
- pDevice->TxMtu = pDevice->RxMtu;
-
- }
-#else
- pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
-
- pDevice->RxPacketDescCnt =
-#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- pDevice->RxJumboDescCnt +
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
- pDevice->RxStdDescCnt;
-
- if (pDevice->TxMtu < MAX_ETHERNET_PACKET_SIZE_NO_CRC) {
- pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
- }
-
- if (pDevice->TxMtu > MAX_JUMBO_TX_BUFFER_SIZE) {
- pDevice->TxMtu = MAX_JUMBO_TX_BUFFER_SIZE;
- }
-
- /* Configure the proper ways to get link change interrupt. */
- if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO) {
- if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
- pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
- } else {
- pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY;
- }
- } else if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) {
- /* Auto-polling does not work on 5700_AX and 5700_BX. */
- if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
- pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
- }
- }
-
- /* Determine the method to get link change status. */
- if (pDevice->LinkChngMode == T3_LINK_CHNG_MODE_AUTO) {
- /* The link status bit in the status block does not work on 5700_AX */
- /* and 5700_BX chips. */
- if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
- pDevice->LinkChngMode =
- T3_LINK_CHNG_MODE_USE_STATUS_REG;
- } else {
- pDevice->LinkChngMode =
- T3_LINK_CHNG_MODE_USE_STATUS_BLOCK;
- }
- }
-
- if (pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT ||
- T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
- pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG;
- }
-
- /* Configure PHY led mode. */
- if (pDevice->LedMode == LED_MODE_AUTO) {
- if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
- if (pDevice->SubsystemVendorId == T3_SVID_DELL) {
- pDevice->LedMode = LED_MODE_LINK10;
- } else {
- pDevice->LedMode = LED_MODE_THREE_LINK;
-
- if (EeSigFound && EePhyLedMode != LED_MODE_AUTO) {
- pDevice->LedMode = EePhyLedMode;
- }
- }
-
- /* bug? 5701 in LINK10 mode does not seem to work when */
- /* PhyIntMode is LINK_READY. */
- if (T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5700
- &&
-#if INCLUDE_TBI_SUPPORT
- pDevice->EnableTbi == FALSE &&
-#endif
- pDevice->LedMode == LED_MODE_LINK10) {
- pDevice->PhyIntMode =
- T3_PHY_INT_MODE_MI_INTERRUPT;
- pDevice->LinkChngMode =
- T3_LINK_CHNG_MODE_USE_STATUS_REG;
- }
-
- if (pDevice->EnableTbi) {
- pDevice->LedMode = LED_MODE_THREE_LINK;
- }
- } else {
- if (EeSigFound && EePhyLedMode != LED_MODE_AUTO) {
- pDevice->LedMode = EePhyLedMode;
- } else {
- pDevice->LedMode = LED_MODE_OPEN_DRAIN;
- }
- }
- }
-
- /* Enable OneDmaAtOnce. */
- if (pDevice->OneDmaAtOnce == BAD_DEFAULT_VALUE) {
- pDevice->OneDmaAtOnce = FALSE;
- }
-
- if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
- pDevice->ChipRevId == T3_CHIP_ID_5701_B0 ||
- pDevice->ChipRevId == T3_CHIP_ID_5701_B2) {
- pDevice->WolSpeed = WOL_SPEED_10MB;
- } else {
- pDevice->WolSpeed = WOL_SPEED_100MB;
- }
-
- /* Offloadings. */
- pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE;
-
- /* Turn off task offloading on Ax. */
- if (pDevice->ChipRevId == T3_CHIP_ID_5700_B0) {
- pDevice->TaskOffloadCap &= ~(LM_TASK_OFFLOAD_TX_TCP_CHECKSUM |
- LM_TASK_OFFLOAD_TX_UDP_CHECKSUM);
- }
- pDevice->PciState = REG_RD (pDevice, PciCfg.PciState);
- LM_ReadVPD (pDevice);
- LM_ReadBootCodeVersion (pDevice);
- LM_GetBusSpeed (pDevice);
-
- return LM_STATUS_SUCCESS;
-} /* LM_GetAdapterInfo */
-
-STATIC PLM_ADAPTER_INFO LM_GetAdapterInfoBySsid (LM_UINT16 Svid, LM_UINT16 Ssid)
-{
- static LM_ADAPTER_INFO AdapterArr[] = {
- {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A6,
- PHY_BCM5401_PHY_ID, 0},
- {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A5,
- PHY_BCM5701_PHY_ID, 0},
- {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700T6,
- PHY_BCM8002_PHY_ID, 1},
- {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A9, 0, 1},
- {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T1,
- PHY_BCM5701_PHY_ID, 0},
- {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T8,
- PHY_BCM5701_PHY_ID, 0},
- {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A7, 0, 1},
- {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A10,
- PHY_BCM5701_PHY_ID, 0},
- {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A12,
- PHY_BCM5701_PHY_ID, 0},
- {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax1,
- PHY_BCM5701_PHY_ID, 0},
- {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax2,
- PHY_BCM5701_PHY_ID, 0},
-
- {T3_SVID_3COM, T3_SSID_3COM_3C996T, PHY_BCM5401_PHY_ID, 0},
- {T3_SVID_3COM, T3_SSID_3COM_3C996BT, PHY_BCM5701_PHY_ID, 0},
- {T3_SVID_3COM, T3_SSID_3COM_3C996SX, 0, 1},
- {T3_SVID_3COM, T3_SSID_3COM_3C1000T, PHY_BCM5701_PHY_ID, 0},
- {T3_SVID_3COM, T3_SSID_3COM_3C940BR01, PHY_BCM5701_PHY_ID, 0},
-
- {T3_SVID_DELL, T3_SSID_DELL_VIPER, PHY_BCM5401_PHY_ID, 0},
- {T3_SVID_DELL, T3_SSID_DELL_JAGUAR, PHY_BCM5401_PHY_ID, 0},
- {T3_SVID_DELL, T3_SSID_DELL_MERLOT, PHY_BCM5411_PHY_ID, 0},
- {T3_SVID_DELL, T3_SSID_DELL_SLIM_MERLOT, PHY_BCM5411_PHY_ID, 0},
-
- {T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE, PHY_BCM5701_PHY_ID, 0},
- {T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE_2, PHY_BCM5701_PHY_ID,
- 0},
- {T3_SVID_COMPAQ, T3_SSID_COMPAQ_CHANGELING, 0, 1},
- {T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780, PHY_BCM5701_PHY_ID, 0},
- {T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780_2, PHY_BCM5701_PHY_ID,
- 0},
-
- };
- LM_UINT32 j;
-
- for (j = 0; j < sizeof (AdapterArr) / sizeof (LM_ADAPTER_INFO); j++) {
- if (AdapterArr[j].Svid == Svid && AdapterArr[j].Ssid == Ssid) {
- return &AdapterArr[j];
- }
- }
-
- return NULL;
-}
-
-/******************************************************************************/
-/* Description: */
-/* This routine sets up receive/transmit buffer descriptions queues. */
-/* */
-/* Return: */
-/* LM_STATUS_SUCCESS */
-/******************************************************************************/
-LM_STATUS LM_InitializeAdapter (PLM_DEVICE_BLOCK pDevice)
-{
- LM_PHYSICAL_ADDRESS MemPhy;
- PLM_UINT8 pMemVirt;
- PLM_PACKET pPacket;
- LM_STATUS Status;
- LM_UINT32 Size;
- LM_UINT32 j;
-
- /* Set power state to D0. */
- LM_SetPowerState (pDevice, LM_POWER_STATE_D0);
-
- /* Intialize the queues. */
- QQ_InitQueue (&pDevice->RxPacketReceivedQ.Container,
- MAX_RX_PACKET_DESC_COUNT);
- QQ_InitQueue (&pDevice->RxPacketFreeQ.Container,
- MAX_RX_PACKET_DESC_COUNT);
-
- QQ_InitQueue (&pDevice->TxPacketFreeQ.Container,
- MAX_TX_PACKET_DESC_COUNT);
- QQ_InitQueue (&pDevice->TxPacketActiveQ.Container,
- MAX_TX_PACKET_DESC_COUNT);
- QQ_InitQueue (&pDevice->TxPacketXmittedQ.Container,
- MAX_TX_PACKET_DESC_COUNT);
-
- /* Allocate shared memory for: status block, the buffers for receive */
- /* rings -- standard, mini, jumbo, and return rings. */
- Size = T3_STATUS_BLOCK_SIZE + sizeof (T3_STATS_BLOCK) +
- T3_STD_RCV_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD) +
-#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD) +
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
- T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD);
-
- /* Memory for host based Send BD. */
- if (pDevice->NicSendBd == FALSE) {
- Size += sizeof (T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT;
- }
-
- /* Allocate the memory block. */
- Status =
- MM_AllocateSharedMemory (pDevice, Size, (PLM_VOID) & pMemVirt,
- &MemPhy, FALSE);
- if (Status != LM_STATUS_SUCCESS) {
- return Status;
- }
-
- /* Program DMA Read/Write */
- if (pDevice->PciState & T3_PCI_STATE_NOT_PCI_X_BUS) {
- pDevice->DmaReadWriteCtrl = 0x763f000f;
- } else {
- if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5704) {
- pDevice->DmaReadWriteCtrl = 0x761f0000;
- } else {
- pDevice->DmaReadWriteCtrl = 0x761b000f;
- }
- if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1 ||
- pDevice->ChipRevId == T3_CHIP_ID_5703_A2) {
- pDevice->OneDmaAtOnce = TRUE;
- }
- }
- if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5703) {
- pDevice->DmaReadWriteCtrl &= 0xfffffff0;
- }
-
- if (pDevice->OneDmaAtOnce) {
- pDevice->DmaReadWriteCtrl |= DMA_CTRL_WRITE_ONE_DMA_AT_ONCE;
- }
- REG_WR (pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl);
-
- if (LM_DmaTest (pDevice, pMemVirt, MemPhy, 0x400) != LM_STATUS_SUCCESS) {
- return LM_STATUS_FAILURE;
- }
-
- /* Status block. */
- pDevice->pStatusBlkVirt = (PT3_STATUS_BLOCK) pMemVirt;
- pDevice->StatusBlkPhy = MemPhy;
- pMemVirt += T3_STATUS_BLOCK_SIZE;
- LM_INC_PHYSICAL_ADDRESS (&MemPhy, T3_STATUS_BLOCK_SIZE);
-
- /* Statistics block. */
- pDevice->pStatsBlkVirt = (PT3_STATS_BLOCK) pMemVirt;
- pDevice->StatsBlkPhy = MemPhy;
- pMemVirt += sizeof (T3_STATS_BLOCK);
- LM_INC_PHYSICAL_ADDRESS (&MemPhy, sizeof (T3_STATS_BLOCK));
-
- /* Receive standard BD buffer. */
- pDevice->pRxStdBdVirt = (PT3_RCV_BD) pMemVirt;
- pDevice->RxStdBdPhy = MemPhy;
-
- pMemVirt += T3_STD_RCV_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD);
- LM_INC_PHYSICAL_ADDRESS (&MemPhy,
- T3_STD_RCV_RCB_ENTRY_COUNT *
- sizeof (T3_RCV_BD));
-
-#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- /* Receive jumbo BD buffer. */
- pDevice->pRxJumboBdVirt = (PT3_RCV_BD) pMemVirt;
- pDevice->RxJumboBdPhy = MemPhy;
-
- pMemVirt += T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD);
- LM_INC_PHYSICAL_ADDRESS (&MemPhy,
- T3_JUMBO_RCV_RCB_ENTRY_COUNT *
- sizeof (T3_RCV_BD));
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
-
- /* Receive return BD buffer. */
- pDevice->pRcvRetBdVirt = (PT3_RCV_BD) pMemVirt;
- pDevice->RcvRetBdPhy = MemPhy;
-
- pMemVirt += T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD);
- LM_INC_PHYSICAL_ADDRESS (&MemPhy,
- T3_RCV_RETURN_RCB_ENTRY_COUNT *
- sizeof (T3_RCV_BD));
-
- /* Set up Send BD. */
- if (pDevice->NicSendBd == FALSE) {
- pDevice->pSendBdVirt = (PT3_SND_BD) pMemVirt;
- pDevice->SendBdPhy = MemPhy;
-
- pMemVirt += sizeof (T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT;
- LM_INC_PHYSICAL_ADDRESS (&MemPhy,
- sizeof (T3_SND_BD) *
- T3_SEND_RCB_ENTRY_COUNT);
- } else {
- pDevice->pSendBdVirt = (PT3_SND_BD)
- pDevice->pMemView->uIntMem.First32k.BufferDesc;
- pDevice->SendBdPhy.High = 0;
- pDevice->SendBdPhy.Low = T3_NIC_SND_BUFFER_DESC_ADDR;
- }
-
- /* Allocate memory for packet descriptors. */
- Size = (pDevice->RxPacketDescCnt +
- pDevice->TxPacketDescCnt) * MM_PACKET_DESC_SIZE;
- Status = MM_AllocateMemory (pDevice, Size, (PLM_VOID *) & pPacket);
- if (Status != LM_STATUS_SUCCESS) {
- return Status;
- }
- pDevice->pPacketDescBase = (PLM_VOID) pPacket;
-
- /* Create transmit packet descriptors from the memory block and add them */
- /* to the TxPacketFreeQ for each send ring. */
- for (j = 0; j < pDevice->TxPacketDescCnt; j++) {
- /* Ring index. */
- pPacket->Flags = 0;
-
- /* Queue the descriptor in the TxPacketFreeQ of the 'k' ring. */
- QQ_PushTail (&pDevice->TxPacketFreeQ.Container, pPacket);
-
- /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */
- /* is the total size of the packet descriptor including the */
- /* os-specific extensions in the UM_PACKET structure. */
- pPacket =
- (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
- } /* for(j.. */
-
- /* Create receive packet descriptors from the memory block and add them */
- /* to the RxPacketFreeQ. Create the Standard packet descriptors. */
- for (j = 0; j < pDevice->RxStdDescCnt; j++) {
- /* Receive producer ring. */
- pPacket->u.Rx.RcvProdRing = T3_STD_RCV_PROD_RING;
-
- /* Receive buffer size. */
- pPacket->u.Rx.RxBufferSize = MAX_STD_RCV_BUFFER_SIZE;
-
- /* Add the descriptor to RxPacketFreeQ. */
- QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
-
- /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */
- /* is the total size of the packet descriptor including the */
- /* os-specific extensions in the UM_PACKET structure. */
- pPacket =
- (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
- } /* for */
-
-#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- /* Create the Jumbo packet descriptors. */
- for (j = 0; j < pDevice->RxJumboDescCnt; j++) {
- /* Receive producer ring. */
- pPacket->u.Rx.RcvProdRing = T3_JUMBO_RCV_PROD_RING;
-
- /* Receive buffer size. */
- pPacket->u.Rx.RxBufferSize = pDevice->RxJumboBufferSize;
-
- /* Add the descriptor to RxPacketFreeQ. */
- QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
-
- /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */
- /* is the total size of the packet descriptor including the */
- /* os-specific extensions in the UM_PACKET structure. */
- pPacket =
- (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
- } /* for */
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
-
- /* Initialize the rest of the packet descriptors. */
- Status = MM_InitializeUmPackets (pDevice);
- if (Status != LM_STATUS_SUCCESS) {
- return Status;
- }
-
- /* if */
- /* Default receive mask. */
- pDevice->ReceiveMask = LM_ACCEPT_MULTICAST | LM_ACCEPT_BROADCAST |
- LM_ACCEPT_UNICAST;
-
- /* Make sure we are in the first 32k memory window or NicSendBd. */
- REG_WR (pDevice, PciCfg.MemWindowBaseAddr, 0);
-
- /* Initialize the hardware. */
- Status = LM_ResetAdapter (pDevice);
- if (Status != LM_STATUS_SUCCESS) {
- return Status;
- }
-
- /* We are done with initialization. */
- pDevice->InitDone = TRUE;
-
- return LM_STATUS_SUCCESS;
-} /* LM_InitializeAdapter */
-
-/******************************************************************************/
-/* Description: */
-/* This function Enables/Disables a given block. */
-/* */
-/* Return: */
-/* LM_STATUS_SUCCESS */
-/******************************************************************************/
-LM_STATUS
-LM_CntrlBlock (PLM_DEVICE_BLOCK pDevice, LM_UINT32 mask, LM_UINT32 cntrl)
-{
- LM_UINT32 j, i, data;
- LM_UINT32 MaxWaitCnt;
-
- MaxWaitCnt = 2;
- j = 0;
-
- for (i = 0; i < 32; i++) {
- if (!(mask & (1 << i)))
- continue;
-
- switch (1 << i) {
- case T3_BLOCK_DMA_RD:
- data = REG_RD (pDevice, DmaRead.Mode);
- if (cntrl == LM_DISABLE) {
- data &= ~DMA_READ_MODE_ENABLE;
- REG_WR (pDevice, DmaRead.Mode, data);
- for (j = 0; j < MaxWaitCnt; j++) {
- if (!
- (REG_RD (pDevice, DmaRead.Mode) &
- DMA_READ_MODE_ENABLE))
- break;
- MM_Wait (10);
- }
- } else
- REG_WR (pDevice, DmaRead.Mode,
- data | DMA_READ_MODE_ENABLE);
- break;
-
- case T3_BLOCK_DMA_COMP:
- data = REG_RD (pDevice, DmaComp.Mode);
- if (cntrl == LM_DISABLE) {
- data &= ~DMA_COMP_MODE_ENABLE;
- REG_WR (pDevice, DmaComp.Mode, data);
- for (j = 0; j < MaxWaitCnt; j++) {
- if (!
- (REG_RD (pDevice, DmaComp.Mode) &
- DMA_COMP_MODE_ENABLE))
- break;
- MM_Wait (10);
- }
- } else
- REG_WR (pDevice, DmaComp.Mode,
- data | DMA_COMP_MODE_ENABLE);
- break;
-
- case T3_BLOCK_RX_BD_INITIATOR:
- data = REG_RD (pDevice, RcvBdIn.Mode);
- if (cntrl == LM_DISABLE) {
- data &= ~RCV_BD_IN_MODE_ENABLE;
- REG_WR (pDevice, RcvBdIn.Mode, data);
- for (j = 0; j < MaxWaitCnt; j++) {
- if (!
- (REG_RD (pDevice, RcvBdIn.Mode) &
- RCV_BD_IN_MODE_ENABLE))
- break;
- MM_Wait (10);
- }
- } else
- REG_WR (pDevice, RcvBdIn.Mode,
- data | RCV_BD_IN_MODE_ENABLE);
- break;
-
- case T3_BLOCK_RX_BD_COMP:
- data = REG_RD (pDevice, RcvBdComp.Mode);
- if (cntrl == LM_DISABLE) {
- data &= ~RCV_BD_COMP_MODE_ENABLE;
- REG_WR (pDevice, RcvBdComp.Mode, data);
- for (j = 0; j < MaxWaitCnt; j++) {
- if (!
- (REG_RD (pDevice, RcvBdComp.Mode) &
- RCV_BD_COMP_MODE_ENABLE))
- break;
- MM_Wait (10);
- }
- } else
- REG_WR (pDevice, RcvBdComp.Mode,
- data | RCV_BD_COMP_MODE_ENABLE);
- break;
-
- case T3_BLOCK_DMA_WR:
- data = REG_RD (pDevice, DmaWrite.Mode);
- if (cntrl == LM_DISABLE) {
- data &= ~DMA_WRITE_MODE_ENABLE;
- REG_WR (pDevice, DmaWrite.Mode, data);
-
- for (j = 0; j < MaxWaitCnt; j++) {
- if (!
- (REG_RD (pDevice, DmaWrite.Mode) &
- DMA_WRITE_MODE_ENABLE))
- break;
- MM_Wait (10);
- }
- } else
- REG_WR (pDevice, DmaWrite.Mode,
- data | DMA_WRITE_MODE_ENABLE);
- break;
-
- case T3_BLOCK_MSI_HANDLER:
- data = REG_RD (pDevice, Msi.Mode);
- if (cntrl == LM_DISABLE) {
- data &= ~MSI_MODE_ENABLE;
- REG_WR (pDevice, Msi.Mode, data);
- for (j = 0; j < MaxWaitCnt; j++) {
- if (!
- (REG_RD (pDevice, Msi.Mode) &
- MSI_MODE_ENABLE))
- break;
- MM_Wait (10);
- }
- } else
- REG_WR (pDevice, Msi.Mode,
- data | MSI_MODE_ENABLE);
- break;
-
- case T3_BLOCK_RX_LIST_PLMT:
- data = REG_RD (pDevice, RcvListPlmt.Mode);
- if (cntrl == LM_DISABLE) {
- data &= ~RCV_LIST_PLMT_MODE_ENABLE;
- REG_WR (pDevice, RcvListPlmt.Mode, data);
- for (j = 0; j < MaxWaitCnt; j++) {
- if (!
- (REG_RD (pDevice, RcvListPlmt.Mode)
- & RCV_LIST_PLMT_MODE_ENABLE))
- break;
- MM_Wait (10);
- }
- } else
- REG_WR (pDevice, RcvListPlmt.Mode,
- data | RCV_LIST_PLMT_MODE_ENABLE);
- break;
-
- case T3_BLOCK_RX_LIST_SELECTOR:
- data = REG_RD (pDevice, RcvListSel.Mode);
- if (cntrl == LM_DISABLE) {
- data &= ~RCV_LIST_SEL_MODE_ENABLE;
- REG_WR (pDevice, RcvListSel.Mode, data);
- for (j = 0; j < MaxWaitCnt; j++) {
- if (!
- (REG_RD (pDevice, RcvListSel.Mode) &
- RCV_LIST_SEL_MODE_ENABLE))
- break;
- MM_Wait (10);
- }
- } else
- REG_WR (pDevice, RcvListSel.Mode,
- data | RCV_LIST_SEL_MODE_ENABLE);
- break;
-
- case T3_BLOCK_RX_DATA_INITIATOR:
- data = REG_RD (pDevice, RcvDataBdIn.Mode);
- if (cntrl == LM_DISABLE) {
- data &= ~RCV_DATA_BD_IN_MODE_ENABLE;
- REG_WR (pDevice, RcvDataBdIn.Mode, data);
- for (j = 0; j < MaxWaitCnt; j++) {
- if (!
- (REG_RD (pDevice, RcvDataBdIn.Mode)
- & RCV_DATA_BD_IN_MODE_ENABLE))
- break;
- MM_Wait (10);
- }
- } else
- REG_WR (pDevice, RcvDataBdIn.Mode,
- data | RCV_DATA_BD_IN_MODE_ENABLE);
- break;
-
- case T3_BLOCK_RX_DATA_COMP:
- data = REG_RD (pDevice, RcvDataComp.Mode);
- if (cntrl == LM_DISABLE) {
- data &= ~RCV_DATA_COMP_MODE_ENABLE;
- REG_WR (pDevice, RcvDataComp.Mode, data);
- for (j = 0; j < MaxWaitCnt; j++) {
- if (!
- (REG_RD (pDevice, RcvDataBdIn.Mode)
- & RCV_DATA_COMP_MODE_ENABLE))
- break;
- MM_Wait (10);
- }
- } else
- REG_WR (pDevice, RcvDataComp.Mode,
- data | RCV_DATA_COMP_MODE_ENABLE);
- break;
-
- case T3_BLOCK_HOST_COALESING:
- data = REG_RD (pDevice, HostCoalesce.Mode);
- if (cntrl == LM_DISABLE) {
- data &= ~HOST_COALESCE_ENABLE;
- REG_WR (pDevice, HostCoalesce.Mode, data);
- for (j = 0; j < MaxWaitCnt; j++) {
- if (!
- (REG_RD (pDevice, SndBdIn.Mode) &
- HOST_COALESCE_ENABLE))
- break;
- MM_Wait (10);
- }
- } else
- REG_WR (pDevice, HostCoalesce.Mode,
- data | HOST_COALESCE_ENABLE);
- break;
-
- case T3_BLOCK_MAC_RX_ENGINE:
- if (cntrl == LM_DISABLE) {
- pDevice->RxMode &= ~RX_MODE_ENABLE;
- REG_WR (pDevice, MacCtrl.RxMode,
- pDevice->RxMode);
- for (j = 0; j < MaxWaitCnt; j++) {
- if (!
- (REG_RD (pDevice, MacCtrl.RxMode) &
- RX_MODE_ENABLE)) {
- break;
- }
- MM_Wait (10);
- }
- } else {
- pDevice->RxMode |= RX_MODE_ENABLE;
- REG_WR (pDevice, MacCtrl.RxMode,
- pDevice->RxMode);
- }
- break;
-
- case T3_BLOCK_MBUF_CLUSTER_FREE:
- data = REG_RD (pDevice, MbufClusterFree.Mode);
- if (cntrl == LM_DISABLE) {
- data &= ~MBUF_CLUSTER_FREE_MODE_ENABLE;
- REG_WR (pDevice, MbufClusterFree.Mode, data);
- for (j = 0; j < MaxWaitCnt; j++) {
- if (!
- (REG_RD
- (pDevice,
- MbufClusterFree.
- Mode) &
- MBUF_CLUSTER_FREE_MODE_ENABLE))
- break;
- MM_Wait (10);
- }
- } else
- REG_WR (pDevice, MbufClusterFree.Mode,
- data | MBUF_CLUSTER_FREE_MODE_ENABLE);
- break;
-
- case T3_BLOCK_SEND_BD_INITIATOR:
- data = REG_RD (pDevice, SndBdIn.Mode);
- if (cntrl == LM_DISABLE) {
- data &= ~SND_BD_IN_MODE_ENABLE;
- REG_WR (pDevice, SndBdIn.Mode, data);
- for (j = 0; j < MaxWaitCnt; j++) {
- if (!
- (REG_RD (pDevice, SndBdIn.Mode) &
- SND_BD_IN_MODE_ENABLE))
- break;
- MM_Wait (10);
- }
- } else
- REG_WR (pDevice, SndBdIn.Mode,
- data | SND_BD_IN_MODE_ENABLE);
- break;
-
- case T3_BLOCK_SEND_BD_COMP:
- data = REG_RD (pDevice, SndBdComp.Mode);
- if (cntrl == LM_DISABLE) {
- data &= ~SND_BD_COMP_MODE_ENABLE;
- REG_WR (pDevice, SndBdComp.Mode, data);
- for (j = 0; j < MaxWaitCnt; j++) {
- if (!
- (REG_RD (pDevice, SndBdComp.Mode) &
- SND_BD_COMP_MODE_ENABLE))
- break;
- MM_Wait (10);
- }
- } else
- REG_WR (pDevice, SndBdComp.Mode,
- data | SND_BD_COMP_MODE_ENABLE);
- break;
-
- case T3_BLOCK_SEND_BD_SELECTOR:
- data = REG_RD (pDevice, SndBdSel.Mode);
- if (cntrl == LM_DISABLE) {
- data &= ~SND_BD_SEL_MODE_ENABLE;
- REG_WR (pDevice, SndBdSel.Mode, data);
- for (j = 0; j < MaxWaitCnt; j++) {
- if (!
- (REG_RD (pDevice, SndBdSel.Mode) &
- SND_BD_SEL_MODE_ENABLE))
- break;
- MM_Wait (10);
- }
- } else
- REG_WR (pDevice, SndBdSel.Mode,
- data | SND_BD_SEL_MODE_ENABLE);
- break;
-
- case T3_BLOCK_SEND_DATA_INITIATOR:
- data = REG_RD (pDevice, SndDataIn.Mode);
- if (cntrl == LM_DISABLE) {
- data &= ~T3_SND_DATA_IN_MODE_ENABLE;
- REG_WR (pDevice, SndDataIn.Mode, data);
- for (j = 0; j < MaxWaitCnt; j++) {
- if (!
- (REG_RD (pDevice, SndDataIn.Mode) &
- T3_SND_DATA_IN_MODE_ENABLE))
- break;
- MM_Wait (10);
- }
- } else
- REG_WR (pDevice, SndDataIn.Mode,
- data | T3_SND_DATA_IN_MODE_ENABLE);
- break;
-
- case T3_BLOCK_SEND_DATA_COMP:
- data = REG_RD (pDevice, SndDataComp.Mode);
- if (cntrl == LM_DISABLE) {
- data &= ~SND_DATA_COMP_MODE_ENABLE;
- REG_WR (pDevice, SndDataComp.Mode, data);
- for (j = 0; j < MaxWaitCnt; j++) {
- if (!
- (REG_RD (pDevice, SndDataComp.Mode)
- & SND_DATA_COMP_MODE_ENABLE))
- break;
- MM_Wait (10);
- }
- } else
- REG_WR (pDevice, SndDataComp.Mode,
- data | SND_DATA_COMP_MODE_ENABLE);
- break;
-
- case T3_BLOCK_MAC_TX_ENGINE:
- if (cntrl == LM_DISABLE) {
- pDevice->TxMode &= ~TX_MODE_ENABLE;
- REG_WR (pDevice, MacCtrl.TxMode,
- pDevice->TxMode);
- for (j = 0; j < MaxWaitCnt; j++) {
- if (!
- (REG_RD (pDevice, MacCtrl.TxMode) &
- TX_MODE_ENABLE))
- break;
- MM_Wait (10);
- }
- } else {
- pDevice->TxMode |= TX_MODE_ENABLE;
- REG_WR (pDevice, MacCtrl.TxMode,
- pDevice->TxMode);
- }
- break;
-
- case T3_BLOCK_MEM_ARBITOR:
- data = REG_RD (pDevice, MemArbiter.Mode);
- if (cntrl == LM_DISABLE) {
- data &= ~T3_MEM_ARBITER_MODE_ENABLE;
- REG_WR (pDevice, MemArbiter.Mode, data);
- for (j = 0; j < MaxWaitCnt; j++) {
- if (!
- (REG_RD (pDevice, MemArbiter.Mode) &
- T3_MEM_ARBITER_MODE_ENABLE))
- break;
- MM_Wait (10);
- }
- } else
- REG_WR (pDevice, MemArbiter.Mode,
- data | T3_MEM_ARBITER_MODE_ENABLE);
- break;
-
- case T3_BLOCK_MBUF_MANAGER:
- data = REG_RD (pDevice, BufMgr.Mode);
- if (cntrl == LM_DISABLE) {
- data &= ~BUFMGR_MODE_ENABLE;
- REG_WR (pDevice, BufMgr.Mode, data);
- for (j = 0; j < MaxWaitCnt; j++) {
- if (!
- (REG_RD (pDevice, BufMgr.Mode) &
- BUFMGR_MODE_ENABLE))
- break;
- MM_Wait (10);
- }
- } else
- REG_WR (pDevice, BufMgr.Mode,
- data | BUFMGR_MODE_ENABLE);
- break;
-
- case T3_BLOCK_MAC_GLOBAL:
- if (cntrl == LM_DISABLE) {
- pDevice->MacMode &= ~(MAC_MODE_ENABLE_TDE |
- MAC_MODE_ENABLE_RDE |
- MAC_MODE_ENABLE_FHDE);
- } else {
- pDevice->MacMode |= (MAC_MODE_ENABLE_TDE |
- MAC_MODE_ENABLE_RDE |
- MAC_MODE_ENABLE_FHDE);
- }
- REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode);
- break;
-
- default:
- return LM_STATUS_FAILURE;
- } /* switch */
-
- if (j >= MaxWaitCnt) {
- return LM_STATUS_FAILURE;
- }
- }
-
- return LM_STATUS_SUCCESS;
-}
-
-/******************************************************************************/
-/* Description: */
-/* This function reinitializes the adapter. */
-/* */
-/* Return: */
-/* LM_STATUS_SUCCESS */
-/******************************************************************************/
-LM_STATUS LM_ResetAdapter (PLM_DEVICE_BLOCK pDevice)
-{
- LM_UINT32 Value32;
- LM_UINT16 Value16;
- LM_UINT32 j, k;
-
- /* Disable interrupt. */
- LM_DisableInterrupt (pDevice);
-
- /* May get a spurious interrupt */
- pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED;
-
- /* Disable transmit and receive DMA engines. Abort all pending requests. */
- if (pDevice->InitDone) {
- LM_Abort (pDevice);
- }
-
- pDevice->ShuttingDown = FALSE;
-
- LM_ResetChip (pDevice);
-
- /* Bug: Athlon fix for B3 silicon only. This bit does not do anything */
- /* in other chip revisions. */
- if (pDevice->DelayPciGrant) {
- Value32 = REG_RD (pDevice, PciCfg.ClockCtrl);
- REG_WR (pDevice, PciCfg.ClockCtrl, Value32 | BIT_31);
- }
-
- if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) {
- if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) {
- Value32 = REG_RD (pDevice, PciCfg.PciState);
- Value32 |= T3_PCI_STATE_RETRY_SAME_DMA;
- REG_WR (pDevice, PciCfg.PciState, Value32);
- }
- }
-
- /* Enable TaggedStatus mode. */
- if (pDevice->UseTaggedStatus) {
- pDevice->MiscHostCtrl |=
- MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE;
- }
-
- /* Restore PCI configuration registers. */
- MM_WriteConfig32 (pDevice, PCI_CACHE_LINE_SIZE_REG,
- pDevice->SavedCacheLineReg);
- MM_WriteConfig32 (pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG,
- (pDevice->SubsystemId << 16) | pDevice->
- SubsystemVendorId);
-
- /* Clear the statistics block. */
- for (j = 0x0300; j < 0x0b00; j++) {
- MEM_WR_OFFSET (pDevice, j, 0);
- }
-
- /* Initialize the statistis Block */
- pDevice->pStatusBlkVirt->Status = 0;
- pDevice->pStatusBlkVirt->RcvStdConIdx = 0;
- pDevice->pStatusBlkVirt->RcvJumboConIdx = 0;
- pDevice->pStatusBlkVirt->RcvMiniConIdx = 0;
-
- for (j = 0; j < 16; j++) {
- pDevice->pStatusBlkVirt->Idx[j].RcvProdIdx = 0;
- pDevice->pStatusBlkVirt->Idx[j].SendConIdx = 0;
- }
-
- for (k = 0; k < T3_STD_RCV_RCB_ENTRY_COUNT; k++) {
- pDevice->pRxStdBdVirt[k].HostAddr.High = 0;
- pDevice->pRxStdBdVirt[k].HostAddr.Low = 0;
- }
-
-#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- /* Receive jumbo BD buffer. */
- for (k = 0; k < T3_JUMBO_RCV_RCB_ENTRY_COUNT; k++) {
- pDevice->pRxJumboBdVirt[k].HostAddr.High = 0;
- pDevice->pRxJumboBdVirt[k].HostAddr.Low = 0;
- }
-#endif
-
- REG_WR (pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl);
-
- /* GRC mode control register. */
-#ifdef BIG_ENDIAN_PCI /* Jimmy, this ifdef block deleted in new code! */
- Value32 =
- GRC_MODE_WORD_SWAP_DATA |
- GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
- GRC_MODE_INT_ON_MAC_ATTN | GRC_MODE_HOST_STACK_UP;
-#else
- /* No CPU Swap modes for PCI IO */
- Value32 =
-#ifdef BIG_ENDIAN_HOST
- GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
- GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
- GRC_MODE_BYTE_SWAP_DATA | GRC_MODE_WORD_SWAP_DATA |
-#else
- GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
- GRC_MODE_BYTE_SWAP_DATA | GRC_MODE_WORD_SWAP_DATA |
-#endif
- GRC_MODE_INT_ON_MAC_ATTN | GRC_MODE_HOST_STACK_UP;
-#endif /* !BIG_ENDIAN_PCI */
-
- /* Configure send BD mode. */
- if (pDevice->NicSendBd == FALSE) {
- Value32 |= GRC_MODE_HOST_SEND_BDS;
- } else {
- Value32 |= GRC_MODE_4X_NIC_BASED_SEND_RINGS;
- }
-
- /* Configure pseudo checksum mode. */
- if (pDevice->NoTxPseudoHdrChksum) {
- Value32 |= GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM;
- }
-
- if (pDevice->NoRxPseudoHdrChksum) {
- Value32 |= GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM;
- }
-
- REG_WR (pDevice, Grc.Mode, Value32);
-
- /* Setup the timer prescalar register. */
- REG_WR (pDevice, Grc.MiscCfg, 65 << 1); /* Clock is alwasy 66MHz. */
-
- /* Set up the MBUF pool base address and size. */
- REG_WR (pDevice, BufMgr.MbufPoolAddr, pDevice->MbufBase);
- REG_WR (pDevice, BufMgr.MbufPoolSize, pDevice->MbufSize);
-
- /* Set up the DMA descriptor pool base address and size. */
- REG_WR (pDevice, BufMgr.DmaDescPoolAddr, T3_NIC_DMA_DESC_POOL_ADDR);
- REG_WR (pDevice, BufMgr.DmaDescPoolSize, T3_NIC_DMA_DESC_POOL_SIZE);
-
- /* Configure MBUF and Threshold watermarks */
- /* Configure the DMA read MBUF low water mark. */
- if (pDevice->DmaMbufLowMark) {
- REG_WR (pDevice, BufMgr.MbufReadDmaLowWaterMark,
- pDevice->DmaMbufLowMark);
- } else {
- if (pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) {
- REG_WR (pDevice, BufMgr.MbufReadDmaLowWaterMark,
- T3_DEF_DMA_MBUF_LOW_WMARK);
- } else {
- REG_WR (pDevice, BufMgr.MbufReadDmaLowWaterMark,
- T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO);
- }
- }
-
- /* Configure the MAC Rx MBUF low water mark. */
- if (pDevice->RxMacMbufLowMark) {
- REG_WR (pDevice, BufMgr.MbufMacRxLowWaterMark,
- pDevice->RxMacMbufLowMark);
- } else {
- if (pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) {
- REG_WR (pDevice, BufMgr.MbufMacRxLowWaterMark,
- T3_DEF_RX_MAC_MBUF_LOW_WMARK);
- } else {
- REG_WR (pDevice, BufMgr.MbufMacRxLowWaterMark,
- T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO);
- }
- }
-
- /* Configure the MBUF high water mark. */
- if (pDevice->MbufHighMark) {
- REG_WR (pDevice, BufMgr.MbufHighWaterMark,
- pDevice->MbufHighMark);
- } else {
- if (pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) {
- REG_WR (pDevice, BufMgr.MbufHighWaterMark,
- T3_DEF_MBUF_HIGH_WMARK);
- } else {
- REG_WR (pDevice, BufMgr.MbufHighWaterMark,
- T3_DEF_MBUF_HIGH_WMARK_JUMBO);
- }
- }
-
- REG_WR (pDevice, BufMgr.DmaLowWaterMark, T3_DEF_DMA_DESC_LOW_WMARK);
- REG_WR (pDevice, BufMgr.DmaHighWaterMark, T3_DEF_DMA_DESC_HIGH_WMARK);
-
- /* Enable buffer manager. */
- REG_WR (pDevice, BufMgr.Mode,
- BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
-
- for (j = 0; j < 2000; j++) {
- if (REG_RD (pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE)
- break;
- MM_Wait (10);
- }
-
- if (j >= 2000) {
- return LM_STATUS_FAILURE;
- }
-
- /* Enable the FTQs. */
- REG_WR (pDevice, Ftq.Reset, 0xffffffff);
- REG_WR (pDevice, Ftq.Reset, 0);
-
- /* Wait until FTQ is ready */
- for (j = 0; j < 2000; j++) {
- if (REG_RD (pDevice, Ftq.Reset) == 0)
- break;
- MM_Wait (10);
- }
-
- if (j >= 2000) {
- return LM_STATUS_FAILURE;
- }
-
- /* Initialize the Standard Receive RCB. */
- REG_WR (pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.High,
- pDevice->RxStdBdPhy.High);
- REG_WR (pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.Low,
- pDevice->RxStdBdPhy.Low);
- REG_WR (pDevice, RcvDataBdIn.StdRcvRcb.u.MaxLen_Flags,
- MAX_STD_RCV_BUFFER_SIZE << 16);
-
- /* Initialize the Jumbo Receive RCB. */
- REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags,
- T3_RCB_FLAG_RING_DISABLED);
-#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.High,
- pDevice->RxJumboBdPhy.High);
- REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.Low,
- pDevice->RxJumboBdPhy.Low);
-
- REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags, 0);
-
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
-
- /* Initialize the Mini Receive RCB. */
- REG_WR (pDevice, RcvDataBdIn.MiniRcvRcb.u.MaxLen_Flags,
- T3_RCB_FLAG_RING_DISABLED);
-
- {
- REG_WR (pDevice, RcvDataBdIn.StdRcvRcb.NicRingAddr,
- (LM_UINT32) T3_NIC_STD_RCV_BUFFER_DESC_ADDR);
- REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.NicRingAddr,
- (LM_UINT32) T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR);
- }
-
- /* Receive BD Ring replenish threshold. */
- REG_WR (pDevice, RcvBdIn.StdRcvThreshold, pDevice->RxStdDescCnt / 8);
-#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- REG_WR (pDevice, RcvBdIn.JumboRcvThreshold,
- pDevice->RxJumboDescCnt / 8);
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
-
- /* Disable all the unused rings. */
- for (j = 0; j < T3_MAX_SEND_RCB_COUNT; j++) {
- MEM_WR (pDevice, SendRcb[j].u.MaxLen_Flags,
- T3_RCB_FLAG_RING_DISABLED);
- } /* for */
-
- /* Initialize the indices. */
- pDevice->SendProdIdx = 0;
- pDevice->SendConIdx = 0;
-
- MB_REG_WR (pDevice, Mailbox.SendHostProdIdx[0].Low, 0);
- MB_REG_WR (pDevice, Mailbox.SendNicProdIdx[0].Low, 0);
-
- /* Set up host or NIC based send RCB. */
- if (pDevice->NicSendBd == FALSE) {
- MEM_WR (pDevice, SendRcb[0].HostRingAddr.High,
- pDevice->SendBdPhy.High);
- MEM_WR (pDevice, SendRcb[0].HostRingAddr.Low,
- pDevice->SendBdPhy.Low);
-
- /* Set up the NIC ring address in the RCB. */
- MEM_WR (pDevice, SendRcb[0].NicRingAddr,
- T3_NIC_SND_BUFFER_DESC_ADDR);
-
- /* Setup the RCB. */
- MEM_WR (pDevice, SendRcb[0].u.MaxLen_Flags,
- T3_SEND_RCB_ENTRY_COUNT << 16);
-
- for (k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++) {
- pDevice->pSendBdVirt[k].HostAddr.High = 0;
- pDevice->pSendBdVirt[k].HostAddr.Low = 0;
- }
- } else {
- MEM_WR (pDevice, SendRcb[0].HostRingAddr.High, 0);
- MEM_WR (pDevice, SendRcb[0].HostRingAddr.Low, 0);
- MEM_WR (pDevice, SendRcb[0].NicRingAddr,
- pDevice->SendBdPhy.Low);
-
- for (k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++) {
- __raw_writel (0,
- &(pDevice->pSendBdVirt[k].HostAddr.High));
- __raw_writel (0,
- &(pDevice->pSendBdVirt[k].HostAddr.Low));
- __raw_writel (0,
- &(pDevice->pSendBdVirt[k].u1.Len_Flags));
- pDevice->ShadowSendBd[k].HostAddr.High = 0;
- pDevice->ShadowSendBd[k].u1.Len_Flags = 0;
- }
- }
- atomic_set (&pDevice->SendBdLeft, T3_SEND_RCB_ENTRY_COUNT - 1);
-
- /* Configure the receive return rings. */
- for (j = 0; j < T3_MAX_RCV_RETURN_RCB_COUNT; j++) {
- MEM_WR (pDevice, RcvRetRcb[j].u.MaxLen_Flags,
- T3_RCB_FLAG_RING_DISABLED);
- }
-
- pDevice->RcvRetConIdx = 0;
-
- MEM_WR (pDevice, RcvRetRcb[0].HostRingAddr.High,
- pDevice->RcvRetBdPhy.High);
- MEM_WR (pDevice, RcvRetRcb[0].HostRingAddr.Low,
- pDevice->RcvRetBdPhy.Low);
-
- /* Set up the NIC ring address in the RCB. */
- /* Not very clear from the spec. I am guessing that for Receive */
- /* Return Ring, NicRingAddr is not used. */
- MEM_WR (pDevice, RcvRetRcb[0].NicRingAddr, 0);
-
- /* Setup the RCB. */
- MEM_WR (pDevice, RcvRetRcb[0].u.MaxLen_Flags,
- T3_RCV_RETURN_RCB_ENTRY_COUNT << 16);
-
- /* Reinitialize RX ring producer index */
- MB_REG_WR (pDevice, Mailbox.RcvStdProdIdx.Low, 0);
- MB_REG_WR (pDevice, Mailbox.RcvJumboProdIdx.Low, 0);
- MB_REG_WR (pDevice, Mailbox.RcvMiniProdIdx.Low, 0);
-
-#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- pDevice->RxJumboProdIdx = 0;
- pDevice->RxJumboQueuedCnt = 0;
-#endif
-
- /* Reinitialize our copy of the indices. */
- pDevice->RxStdProdIdx = 0;
- pDevice->RxStdQueuedCnt = 0;
-
-#if T3_JUMBO_RCV_ENTRY_COUNT
- pDevice->RxJumboProdIdx = 0;
-#endif /* T3_JUMBO_RCV_ENTRY_COUNT */
-
- /* Configure the MAC address. */
- LM_SetMacAddress (pDevice);
-
- /* Initialize the transmit random backoff seed. */
- Value32 = (pDevice->NodeAddress[0] + pDevice->NodeAddress[1] +
- pDevice->NodeAddress[2] + pDevice->NodeAddress[3] +
- pDevice->NodeAddress[4] + pDevice->NodeAddress[5]) &
- MAC_TX_BACKOFF_SEED_MASK;
- REG_WR (pDevice, MacCtrl.TxBackoffSeed, Value32);
-
- /* Receive MTU. Frames larger than the MTU is marked as oversized. */
- REG_WR (pDevice, MacCtrl.MtuSize, pDevice->RxMtu + 8); /* CRC + VLAN. */
-
- /* Configure Time slot/IPG per 802.3 */
- REG_WR (pDevice, MacCtrl.TxLengths, 0x2620);
-
- /*
- * Configure Receive Rules so that packets don't match
- * Programmble rule will be queued to Return Ring 1
- */
- REG_WR (pDevice, MacCtrl.RcvRuleCfg, RX_RULE_DEFAULT_CLASS);
-
- /*
- * Configure to have 16 Classes of Services (COS) and one
- * queue per class. Bad frames are queued to RRR#1.
- * And frames don't match rules are also queued to COS#1.
- */
- REG_WR (pDevice, RcvListPlmt.Config, 0x181);
-
- /* Enable Receive Placement Statistics */
- REG_WR (pDevice, RcvListPlmt.StatsEnableMask, 0xffffff);
- REG_WR (pDevice, RcvListPlmt.StatsCtrl, RCV_LIST_STATS_ENABLE);
-
- /* Enable Send Data Initator Statistics */
- REG_WR (pDevice, SndDataIn.StatsEnableMask, 0xffffff);
- REG_WR (pDevice, SndDataIn.StatsCtrl,
- T3_SND_DATA_IN_STATS_CTRL_ENABLE |
- T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE);
-
- /* Disable the host coalescing state machine before configuring it's */
- /* parameters. */
- REG_WR (pDevice, HostCoalesce.Mode, 0);
- for (j = 0; j < 2000; j++) {
- Value32 = REG_RD (pDevice, HostCoalesce.Mode);
- if (!(Value32 & HOST_COALESCE_ENABLE)) {
- break;
- }
- MM_Wait (10);
- }
-
- /* Host coalescing configurations. */
- REG_WR (pDevice, HostCoalesce.RxCoalescingTicks,
- pDevice->RxCoalescingTicks);
- REG_WR (pDevice, HostCoalesce.TxCoalescingTicks,
- pDevice->TxCoalescingTicks);
- REG_WR (pDevice, HostCoalesce.RxMaxCoalescedFrames,
- pDevice->RxMaxCoalescedFrames);
- REG_WR (pDevice, HostCoalesce.TxMaxCoalescedFrames,
- pDevice->TxMaxCoalescedFrames);
- REG_WR (pDevice, HostCoalesce.RxCoalescedTickDuringInt,
- pDevice->RxCoalescingTicksDuringInt);
- REG_WR (pDevice, HostCoalesce.TxCoalescedTickDuringInt,
- pDevice->TxCoalescingTicksDuringInt);
- REG_WR (pDevice, HostCoalesce.RxMaxCoalescedFramesDuringInt,
- pDevice->RxMaxCoalescedFramesDuringInt);
- REG_WR (pDevice, HostCoalesce.TxMaxCoalescedFramesDuringInt,
- pDevice->TxMaxCoalescedFramesDuringInt);
-
- /* Initialize the address of the status block. The NIC will DMA */
- /* the status block to this memory which resides on the host. */
- REG_WR (pDevice, HostCoalesce.StatusBlkHostAddr.High,
- pDevice->StatusBlkPhy.High);
- REG_WR (pDevice, HostCoalesce.StatusBlkHostAddr.Low,
- pDevice->StatusBlkPhy.Low);
-
- /* Initialize the address of the statistics block. The NIC will DMA */
- /* the statistics to this block of memory. */
- REG_WR (pDevice, HostCoalesce.StatsBlkHostAddr.High,
- pDevice->StatsBlkPhy.High);
- REG_WR (pDevice, HostCoalesce.StatsBlkHostAddr.Low,
- pDevice->StatsBlkPhy.Low);
-
- REG_WR (pDevice, HostCoalesce.StatsCoalescingTicks,
- pDevice->StatsCoalescingTicks);
-
- REG_WR (pDevice, HostCoalesce.StatsBlkNicAddr, 0x300);
- REG_WR (pDevice, HostCoalesce.StatusBlkNicAddr, 0xb00);
-
- /* Enable Host Coalesing state machine */
- REG_WR (pDevice, HostCoalesce.Mode, HOST_COALESCE_ENABLE |
- pDevice->CoalesceMode);
-
- /* Enable the Receive BD Completion state machine. */
- REG_WR (pDevice, RcvBdComp.Mode, RCV_BD_COMP_MODE_ENABLE |
- RCV_BD_COMP_MODE_ATTN_ENABLE);
-
- /* Enable the Receive List Placement state machine. */
- REG_WR (pDevice, RcvListPlmt.Mode, RCV_LIST_PLMT_MODE_ENABLE);
-
- /* Enable the Receive List Selector state machine. */
- REG_WR (pDevice, RcvListSel.Mode, RCV_LIST_SEL_MODE_ENABLE |
- RCV_LIST_SEL_MODE_ATTN_ENABLE);
-
- /* Enable transmit DMA, clear statistics. */
- pDevice->MacMode = MAC_MODE_ENABLE_TX_STATISTICS |
- MAC_MODE_ENABLE_RX_STATISTICS | MAC_MODE_ENABLE_TDE |
- MAC_MODE_ENABLE_RDE | MAC_MODE_ENABLE_FHDE;
- REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode |
- MAC_MODE_CLEAR_RX_STATISTICS | MAC_MODE_CLEAR_TX_STATISTICS);
-
- /* GRC miscellaneous local control register. */
- pDevice->GrcLocalCtrl = GRC_MISC_LOCAL_CTRL_INT_ON_ATTN |
- GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM;
-
- if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
- pDevice->GrcLocalCtrl |= GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
- GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1;
- }
-
- REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl);
- MM_Wait (40);
-
- /* Reset RX counters. */
- for (j = 0; j < sizeof (LM_RX_COUNTERS); j++) {
- ((PLM_UINT8) & pDevice->RxCounters)[j] = 0;
- }
-
- /* Reset TX counters. */
- for (j = 0; j < sizeof (LM_TX_COUNTERS); j++) {
- ((PLM_UINT8) & pDevice->TxCounters)[j] = 0;
- }
-
- MB_REG_WR (pDevice, Mailbox.Interrupt[0].Low, 0);
-
- /* Enable the DMA Completion state machine. */
- REG_WR (pDevice, DmaComp.Mode, DMA_COMP_MODE_ENABLE);
-
- /* Enable the DMA Write state machine. */
- Value32 = DMA_WRITE_MODE_ENABLE |
- DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE |
- DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE |
- DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE |
- DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE |
- DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE |
- DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE |
- DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE |
- DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE;
- REG_WR (pDevice, DmaWrite.Mode, Value32);
-
- if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) {
- if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) {
- Value16 = REG_RD (pDevice, PciCfg.PciXCommand);
- Value16 &=
- ~(PCIX_CMD_MAX_SPLIT_MASK |
- PCIX_CMD_MAX_BURST_MASK);
- Value16 |=
- ((PCIX_CMD_MAX_BURST_CPIOB <<
- PCIX_CMD_MAX_BURST_SHL) &
- PCIX_CMD_MAX_BURST_MASK);
- if (pDevice->SplitModeEnable == SPLIT_MODE_ENABLE) {
- Value16 |=
- (pDevice->
- SplitModeMaxReq << PCIX_CMD_MAX_SPLIT_SHL)
- & PCIX_CMD_MAX_SPLIT_MASK;
- }
- REG_WR (pDevice, PciCfg.PciXCommand, Value16);
- }
- }
-
- /* Enable the Read DMA state machine. */
- Value32 = DMA_READ_MODE_ENABLE |
- DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE |
- DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE |
- DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE |
- DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE |
- DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE |
- DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE |
- DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE |
- DMA_READ_MODE_LONG_READ_ATTN_ENABLE;
-
- if (pDevice->SplitModeEnable == SPLIT_MODE_ENABLE) {
- Value32 |= DMA_READ_MODE_SPLIT_ENABLE;
- }
- REG_WR (pDevice, DmaRead.Mode, Value32);
-
- /* Enable the Receive Data Completion state machine. */
- REG_WR (pDevice, RcvDataComp.Mode, RCV_DATA_COMP_MODE_ENABLE |
- RCV_DATA_COMP_MODE_ATTN_ENABLE);
-
- /* Enable the Mbuf Cluster Free state machine. */
- REG_WR (pDevice, MbufClusterFree.Mode, MBUF_CLUSTER_FREE_MODE_ENABLE);
-
- /* Enable the Send Data Completion state machine. */
- REG_WR (pDevice, SndDataComp.Mode, SND_DATA_COMP_MODE_ENABLE);
-
- /* Enable the Send BD Completion state machine. */
- REG_WR (pDevice, SndBdComp.Mode, SND_BD_COMP_MODE_ENABLE |
- SND_BD_COMP_MODE_ATTN_ENABLE);
-
- /* Enable the Receive BD Initiator state machine. */
- REG_WR (pDevice, RcvBdIn.Mode, RCV_BD_IN_MODE_ENABLE |
- RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE);
-
- /* Enable the Receive Data and Receive BD Initiator state machine. */
- REG_WR (pDevice, RcvDataBdIn.Mode, RCV_DATA_BD_IN_MODE_ENABLE |
- RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE);
-
- /* Enable the Send Data Initiator state machine. */
- REG_WR (pDevice, SndDataIn.Mode, T3_SND_DATA_IN_MODE_ENABLE);
-
- /* Enable the Send BD Initiator state machine. */
- REG_WR (pDevice, SndBdIn.Mode, SND_BD_IN_MODE_ENABLE |
- SND_BD_IN_MODE_ATTN_ENABLE);
-
- /* Enable the Send BD Selector state machine. */
- REG_WR (pDevice, SndBdSel.Mode, SND_BD_SEL_MODE_ENABLE |
- SND_BD_SEL_MODE_ATTN_ENABLE);
-
-#if INCLUDE_5701_AX_FIX
- /* Load the firmware for the 5701_A0 workaround. */
- if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0) {
- LM_LoadRlsFirmware (pDevice);
- }
-#endif
-
- /* Enable the transmitter. */
- pDevice->TxMode = TX_MODE_ENABLE;
- REG_WR (pDevice, MacCtrl.TxMode, pDevice->TxMode);
-
- /* Enable the receiver. */
- pDevice->RxMode = RX_MODE_ENABLE;
- REG_WR (pDevice, MacCtrl.RxMode, pDevice->RxMode);
-
- if (pDevice->RestoreOnWakeUp) {
- pDevice->RestoreOnWakeUp = FALSE;
- pDevice->DisableAutoNeg = pDevice->WakeUpDisableAutoNeg;
- pDevice->RequestedMediaType = pDevice->WakeUpRequestedMediaType;
- }
-
- /* Disable auto polling. */
- pDevice->MiMode = 0xc0000;
- REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode);
-
- if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
- Value32 = LED_CTRL_PHY_MODE_1;
- } else {
- if (pDevice->LedMode == LED_MODE_OUTPUT) {
- Value32 = LED_CTRL_PHY_MODE_2;
- } else {
- Value32 = LED_CTRL_PHY_MODE_1;
- }
- }
- REG_WR (pDevice, MacCtrl.LedCtrl, Value32);
-
- /* Activate Link to enable MAC state machine */
- REG_WR (pDevice, MacCtrl.MiStatus, MI_STATUS_ENABLE_LINK_STATUS_ATTN);
-
- if (pDevice->EnableTbi) {
- REG_WR (pDevice, MacCtrl.RxMode, RX_MODE_RESET);
- MM_Wait (10);
- REG_WR (pDevice, MacCtrl.RxMode, pDevice->RxMode);
- if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1) {
- REG_WR (pDevice, MacCtrl.SerdesCfg, 0x616000);
- }
- }
- /* Setup the phy chip. */
- LM_SetupPhy (pDevice);
-
- if (!pDevice->EnableTbi) {
- /* Clear CRC stats */
- LM_ReadPhy (pDevice, 0x1e, &Value32);
- LM_WritePhy (pDevice, 0x1e, Value32 | 0x8000);
- LM_ReadPhy (pDevice, 0x14, &Value32);
- }
-
- /* Set up the receive mask. */
- LM_SetReceiveMask (pDevice, pDevice->ReceiveMask);
-
- /* Queue Rx packet buffers. */
- if (pDevice->QueueRxPackets) {
- LM_QueueRxPackets (pDevice);
- }
-
- /* Enable interrupt to the host. */
- if (pDevice->InitDone) {
- LM_EnableInterrupt (pDevice);
- }
-
- return LM_STATUS_SUCCESS;
-} /* LM_ResetAdapter */
-
-/******************************************************************************/
-/* Description: */
-/* This routine disables the adapter from generating interrupts. */
-/* */
-/* Return: */
-/* LM_STATUS_SUCCESS */
-/******************************************************************************/
-LM_STATUS LM_DisableInterrupt (PLM_DEVICE_BLOCK pDevice)
-{
- REG_WR (pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl |
- MISC_HOST_CTRL_MASK_PCI_INT);
- MB_REG_WR (pDevice, Mailbox.Interrupt[0].Low, 1);
-
- return LM_STATUS_SUCCESS;
-}
-
-/******************************************************************************/
-/* Description: */
-/* This routine enables the adapter to generate interrupts. */
-/* */
-/* Return: */
-/* LM_STATUS_SUCCESS */
-/******************************************************************************/
-LM_STATUS LM_EnableInterrupt (PLM_DEVICE_BLOCK pDevice)
-{
- REG_WR (pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl &
- ~MISC_HOST_CTRL_MASK_PCI_INT);
- MB_REG_WR (pDevice, Mailbox.Interrupt[0].Low, 0);
-
- if (pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) {
- REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
- GRC_MISC_LOCAL_CTRL_SET_INT);
- }
-
- return LM_STATUS_SUCCESS;
-}
-
-/******************************************************************************/
-/* Description: */
-/* This routine puts a packet on the wire if there is a transmit DMA */
-/* descriptor available; otherwise the packet is queued for later */
-/* transmission. If the second argue is NULL, this routine will put */
-/* the queued packet on the wire if possible. */
-/* */
-/* Return: */
-/* LM_STATUS_SUCCESS */
-/******************************************************************************/
-#if 0
-LM_STATUS LM_SendPacket (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
-{
- LM_UINT32 FragCount;
- PT3_SND_BD pSendBd;
- PT3_SND_BD pShadowSendBd;
- LM_UINT32 Value32, Len;
- LM_UINT32 Idx;
-
- if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
- return LM_5700SendPacket (pDevice, pPacket);
- }
-
- /* Update the SendBdLeft count. */
- atomic_sub (pPacket->u.Tx.FragCount, &pDevice->SendBdLeft);
-
- /* Initalize the send buffer descriptors. */
- Idx = pDevice->SendProdIdx;
-
- pSendBd = &pDevice->pSendBdVirt[Idx];
-
- /* Next producer index. */
- if (pDevice->NicSendBd == TRUE) {
- T3_64BIT_HOST_ADDR paddr;
-
- pShadowSendBd = &pDevice->ShadowSendBd[Idx];
- for (FragCount = 0;;) {
- MM_MapTxDma (pDevice, pPacket, &paddr, &Len, FragCount);
- /* Initialize the pointer to the send buffer fragment. */
- if (paddr.High != pShadowSendBd->HostAddr.High) {
- __raw_writel (paddr.High,
- &(pSendBd->HostAddr.High));
- pShadowSendBd->HostAddr.High = paddr.High;
- }
- __raw_writel (paddr.Low, &(pSendBd->HostAddr.Low));
-
- /* Setup the control flags and send buffer size. */
- Value32 = (Len << 16) | pPacket->Flags;
-
- Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
-
- FragCount++;
- if (FragCount >= pPacket->u.Tx.FragCount) {
- Value32 |= SND_BD_FLAG_END;
- if (Value32 != pShadowSendBd->u1.Len_Flags) {
- __raw_writel (Value32,
- &(pSendBd->u1.Len_Flags));
- pShadowSendBd->u1.Len_Flags = Value32;
- }
- if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) {
- __raw_writel (pPacket->VlanTag,
- &(pSendBd->u2.VlanTag));
- }
- break;
- } else {
- if (Value32 != pShadowSendBd->u1.Len_Flags) {
- __raw_writel (Value32,
- &(pSendBd->u1.Len_Flags));
- pShadowSendBd->u1.Len_Flags = Value32;
- }
- if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) {
- __raw_writel (pPacket->VlanTag,
- &(pSendBd->u2.VlanTag));
- }
- }
-
- pSendBd++;
- pShadowSendBd++;
- if (Idx == 0) {
- pSendBd = &pDevice->pSendBdVirt[0];
- pShadowSendBd = &pDevice->ShadowSendBd[0];
- }
- } /* for */
-
- /* Put the packet descriptor in the ActiveQ. */
- QQ_PushTail (&pDevice->TxPacketActiveQ.Container, pPacket);
-
- wmb ();
- MB_REG_WR (pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);
-
- } else {
- for (FragCount = 0;;) {
- /* Initialize the pointer to the send buffer fragment. */
- MM_MapTxDma (pDevice, pPacket, &pSendBd->HostAddr, &Len,
- FragCount);
-
- pSendBd->u2.VlanTag = pPacket->VlanTag;
-
- /* Setup the control flags and send buffer size. */
- Value32 = (Len << 16) | pPacket->Flags;
-
- Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
-
- FragCount++;
- if (FragCount >= pPacket->u.Tx.FragCount) {
- pSendBd->u1.Len_Flags =
- Value32 | SND_BD_FLAG_END;
- break;
- } else {
- pSendBd->u1.Len_Flags = Value32;
- }
- pSendBd++;
- if (Idx == 0) {
- pSendBd = &pDevice->pSendBdVirt[0];
- }
- } /* for */
-
- /* Put the packet descriptor in the ActiveQ. */
- QQ_PushTail (&pDevice->TxPacketActiveQ.Container, pPacket);
-
- wmb ();
- MB_REG_WR (pDevice, Mailbox.SendHostProdIdx[0].Low, Idx);
-
- }
-
- /* Update the producer index. */
- pDevice->SendProdIdx = Idx;
-
- return LM_STATUS_SUCCESS;
-}
-#endif
-
-LM_STATUS LM_SendPacket (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
-{
- LM_UINT32 FragCount;
- PT3_SND_BD pSendBd, pTmpSendBd, pShadowSendBd;
- T3_SND_BD NicSendBdArr[MAX_FRAGMENT_COUNT];
- LM_UINT32 StartIdx, Idx;
-
- while (1) {
- /* Initalize the send buffer descriptors. */
- StartIdx = Idx = pDevice->SendProdIdx;
-
- if (pDevice->NicSendBd) {
- pTmpSendBd = pSendBd = &NicSendBdArr[0];
- } else {
- pTmpSendBd = pSendBd = &pDevice->pSendBdVirt[Idx];
- }
-
- /* Next producer index. */
- for (FragCount = 0;;) {
- LM_UINT32 Value32, Len;
-
- /* Initialize the pointer to the send buffer fragment. */
- MM_MapTxDma (pDevice, pPacket, &pSendBd->HostAddr, &Len,
- FragCount);
-
- pSendBd->u2.VlanTag = pPacket->VlanTag;
-
- /* Setup the control flags and send buffer size. */
- Value32 = (Len << 16) | pPacket->Flags;
-
- Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
-
- FragCount++;
- if (FragCount >= pPacket->u.Tx.FragCount) {
- pSendBd->u1.Len_Flags =
- Value32 | SND_BD_FLAG_END;
- break;
- } else {
- pSendBd->u1.Len_Flags = Value32;
- }
- pSendBd++;
- if ((Idx == 0) && !pDevice->NicSendBd) {
- pSendBd = &pDevice->pSendBdVirt[0];
- }
- } /* for */
- if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
- if (LM_Test4GBoundary (pDevice, pPacket, pTmpSendBd) ==
- LM_STATUS_SUCCESS) {
- if (MM_CoalesceTxBuffer (pDevice, pPacket) !=
- LM_STATUS_SUCCESS) {
- QQ_PushHead (&pDevice->TxPacketFreeQ.
- Container, pPacket);
- return LM_STATUS_FAILURE;
- }
- continue;
- }
- }
- break;
- }
- /* Put the packet descriptor in the ActiveQ. */
- QQ_PushTail (&pDevice->TxPacketActiveQ.Container, pPacket);
-
- if (pDevice->NicSendBd) {
- pSendBd = &pDevice->pSendBdVirt[StartIdx];
- pShadowSendBd = &pDevice->ShadowSendBd[StartIdx];
-
- while (StartIdx != Idx) {
- LM_UINT32 Value32;
-
- if ((Value32 = pTmpSendBd->HostAddr.High) !=
- pShadowSendBd->HostAddr.High) {
- __raw_writel (Value32,
- &(pSendBd->HostAddr.High));
- pShadowSendBd->HostAddr.High = Value32;
- }
-
- __raw_writel (pTmpSendBd->HostAddr.Low,
- &(pSendBd->HostAddr.Low));
-
- if ((Value32 = pTmpSendBd->u1.Len_Flags) !=
- pShadowSendBd->u1.Len_Flags) {
- __raw_writel (Value32,
- &(pSendBd->u1.Len_Flags));
- pShadowSendBd->u1.Len_Flags = Value32;
- }
-
- if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) {
- __raw_writel (pTmpSendBd->u2.VlanTag,
- &(pSendBd->u2.VlanTag));
- }
-
- StartIdx =
- (StartIdx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
- if (StartIdx == 0)
- pSendBd = &pDevice->pSendBdVirt[0];
- else
- pSendBd++;
- pTmpSendBd++;
- }
- wmb ();
- MB_REG_WR (pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);
-
- if (T3_CHIP_REV (pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) {
- MB_REG_WR (pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);
- }
- } else {
- wmb ();
- MB_REG_WR (pDevice, Mailbox.SendHostProdIdx[0].Low, Idx);
-
- if (T3_CHIP_REV (pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) {
- MB_REG_WR (pDevice, Mailbox.SendHostProdIdx[0].Low,
- Idx);
- }
- }
-
- /* Update the SendBdLeft count. */
- atomic_sub (pPacket->u.Tx.FragCount, &pDevice->SendBdLeft);
-
- /* Update the producer index. */
- pDevice->SendProdIdx = Idx;
-
- return LM_STATUS_SUCCESS;
-}
-
-STATIC LM_STATUS
-LM_Test4GBoundary (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket,
- PT3_SND_BD pSendBd)
-{
- int FragCount;
- LM_UINT32 Idx, Base, Len;
-
- Idx = pDevice->SendProdIdx;
- for (FragCount = 0;;) {
- Len = pSendBd->u1.Len_Flags >> 16;
- if (((Base = pSendBd->HostAddr.Low) > 0xffffdcc0) &&
- (pSendBd->HostAddr.High == 0) &&
- ((Base + 8 + Len) < Base)) {
- return LM_STATUS_SUCCESS;
- }
- FragCount++;
- if (FragCount >= pPacket->u.Tx.FragCount) {
- break;
- }
- pSendBd++;
- if (!pDevice->NicSendBd) {
- Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
- if (Idx == 0) {
- pSendBd = &pDevice->pSendBdVirt[0];
- }
- }
- }
- return LM_STATUS_FAILURE;
-}
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-__inline static unsigned long
-ComputeCrc32 (unsigned char *pBuffer, unsigned long BufferSize)
-{
- unsigned long Reg;
- unsigned long Tmp;
- unsigned long j, k;
-
- Reg = 0xffffffff;
-
- for (j = 0; j < BufferSize; j++) {
- Reg ^= pBuffer[j];
-
- for (k = 0; k < 8; k++) {
- Tmp = Reg & 0x01;
-
- Reg >>= 1;
-
- if (Tmp) {
- Reg ^= 0xedb88320;
- }
- }
- }
-
- return ~Reg;
-} /* ComputeCrc32 */
-
-/******************************************************************************/
-/* Description: */
-/* This routine sets the receive control register according to ReceiveMask */
-/* */
-/* Return: */
-/* LM_STATUS_SUCCESS */
-/******************************************************************************/
-LM_STATUS LM_SetReceiveMask (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Mask)
-{
- LM_UINT32 ReceiveMask;
- LM_UINT32 RxMode;
- LM_UINT32 j, k;
-
- ReceiveMask = Mask;
-
- RxMode = pDevice->RxMode;
-
- if (Mask & LM_ACCEPT_UNICAST) {
- Mask &= ~LM_ACCEPT_UNICAST;
- }
-
- if (Mask & LM_ACCEPT_MULTICAST) {
- Mask &= ~LM_ACCEPT_MULTICAST;
- }
-
- if (Mask & LM_ACCEPT_ALL_MULTICAST) {
- Mask &= ~LM_ACCEPT_ALL_MULTICAST;
- }
-
- if (Mask & LM_ACCEPT_BROADCAST) {
- Mask &= ~LM_ACCEPT_BROADCAST;
- }
-
- RxMode &= ~RX_MODE_PROMISCUOUS_MODE;
- if (Mask & LM_PROMISCUOUS_MODE) {
- RxMode |= RX_MODE_PROMISCUOUS_MODE;
- Mask &= ~LM_PROMISCUOUS_MODE;
- }
-
- RxMode &= ~(RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED);
- if (Mask & LM_ACCEPT_ERROR_PACKET) {
- RxMode |= RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED;
- Mask &= ~LM_ACCEPT_ERROR_PACKET;
- }
-
- /* Make sure all the bits are valid before committing changes. */
- if (Mask) {
- return LM_STATUS_FAILURE;
- }
-
- /* Commit the new filter. */
- pDevice->RxMode = RxMode;
- REG_WR (pDevice, MacCtrl.RxMode, RxMode);
-
- pDevice->ReceiveMask = ReceiveMask;
-
- /* Set up the MC hash table. */
- if (ReceiveMask & LM_ACCEPT_ALL_MULTICAST) {
- for (k = 0; k < 4; k++) {
- REG_WR (pDevice, MacCtrl.HashReg[k], 0xffffffff);
- }
- } else if (ReceiveMask & LM_ACCEPT_MULTICAST) {
- LM_UINT32 HashReg[4];
-
- HashReg[0] = 0;
- HashReg[1] = 0;
- HashReg[2] = 0;
- HashReg[3] = 0;
- for (j = 0; j < pDevice->McEntryCount; j++) {
- LM_UINT32 RegIndex;
- LM_UINT32 Bitpos;
- LM_UINT32 Crc32;
-
- Crc32 =
- ComputeCrc32 (pDevice->McTable[j],
- ETHERNET_ADDRESS_SIZE);
-
- /* The most significant 7 bits of the CRC32 (no inversion), */
- /* are used to index into one of the possible 128 bit positions. */
- Bitpos = ~Crc32 & 0x7f;
-
- /* Hash register index. */
- RegIndex = (Bitpos & 0x60) >> 5;
-
- /* Bit to turn on within a hash register. */
- Bitpos &= 0x1f;
-
- /* Enable the multicast bit. */
- HashReg[RegIndex] |= (1 << Bitpos);
- }
-
- /* REV_AX has problem with multicast filtering where it uses both */
- /* DA and SA to perform hashing. */
- for (k = 0; k < 4; k++) {
- REG_WR (pDevice, MacCtrl.HashReg[k], HashReg[k]);
- }
- } else {
- /* Reject all multicast frames. */
- for (j = 0; j < 4; j++) {
- REG_WR (pDevice, MacCtrl.HashReg[j], 0);
- }
- }
-
- /* By default, Tigon3 will accept broadcast frames. We need to setup */
- if (ReceiveMask & LM_ACCEPT_BROADCAST) {
- REG_WR (pDevice,
- MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule,
- REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK);
- REG_WR (pDevice,
- MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value,
- REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK);
- REG_WR (pDevice,
- MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule,
- REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK);
- REG_WR (pDevice,
- MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value,
- REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK);
- } else {
- REG_WR (pDevice,
- MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule,
- REJECT_BROADCAST_RULE1_RULE);
- REG_WR (pDevice,
- MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value,
- REJECT_BROADCAST_RULE1_VALUE);
- REG_WR (pDevice,
- MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule,
- REJECT_BROADCAST_RULE2_RULE);
- REG_WR (pDevice,
- MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value,
- REJECT_BROADCAST_RULE2_VALUE);
- }
-
- /* disable the rest of the rules. */
- for (j = RCV_LAST_RULE_IDX; j < 16; j++) {
- REG_WR (pDevice, MacCtrl.RcvRules[j].Rule, 0);
- REG_WR (pDevice, MacCtrl.RcvRules[j].Value, 0);
- }
-
- return LM_STATUS_SUCCESS;
-} /* LM_SetReceiveMask */
-
-/******************************************************************************/
-/* Description: */
-/* Disable the interrupt and put the transmitter and receiver engines in */
-/* an idle state. Also aborts all pending send requests and receive */
-/* buffers. */
-/* */
-/* Return: */
-/* LM_STATUS_SUCCESS */
-/******************************************************************************/
-LM_STATUS LM_Abort (PLM_DEVICE_BLOCK pDevice)
-{
- PLM_PACKET pPacket;
- LM_UINT Idx;
-
- LM_DisableInterrupt (pDevice);
-
- /* Disable all the state machines. */
- LM_CntrlBlock (pDevice, T3_BLOCK_MAC_RX_ENGINE, LM_DISABLE);
- LM_CntrlBlock (pDevice, T3_BLOCK_RX_BD_INITIATOR, LM_DISABLE);
- LM_CntrlBlock (pDevice, T3_BLOCK_RX_LIST_PLMT, LM_DISABLE);
- LM_CntrlBlock (pDevice, T3_BLOCK_RX_LIST_SELECTOR, LM_DISABLE);
- LM_CntrlBlock (pDevice, T3_BLOCK_RX_DATA_INITIATOR, LM_DISABLE);
- LM_CntrlBlock (pDevice, T3_BLOCK_RX_DATA_COMP, LM_DISABLE);
- LM_CntrlBlock (pDevice, T3_BLOCK_RX_BD_COMP, LM_DISABLE);
-
- LM_CntrlBlock (pDevice, T3_BLOCK_SEND_BD_SELECTOR, LM_DISABLE);
- LM_CntrlBlock (pDevice, T3_BLOCK_SEND_BD_INITIATOR, LM_DISABLE);
- LM_CntrlBlock (pDevice, T3_BLOCK_SEND_DATA_INITIATOR, LM_DISABLE);
- LM_CntrlBlock (pDevice, T3_BLOCK_DMA_RD, LM_DISABLE);
- LM_CntrlBlock (pDevice, T3_BLOCK_SEND_DATA_COMP, LM_DISABLE);
- LM_CntrlBlock (pDevice, T3_BLOCK_DMA_COMP, LM_DISABLE);
- LM_CntrlBlock (pDevice, T3_BLOCK_SEND_BD_COMP, LM_DISABLE);
-
- /* Clear TDE bit */
- pDevice->MacMode &= ~MAC_MODE_ENABLE_TDE;
- REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode);
-
- LM_CntrlBlock (pDevice, T3_BLOCK_MAC_TX_ENGINE, LM_DISABLE);
- LM_CntrlBlock (pDevice, T3_BLOCK_HOST_COALESING, LM_DISABLE);
- LM_CntrlBlock (pDevice, T3_BLOCK_DMA_WR, LM_DISABLE);
- LM_CntrlBlock (pDevice, T3_BLOCK_MBUF_CLUSTER_FREE, LM_DISABLE);
-
- /* Reset all FTQs */
- REG_WR (pDevice, Ftq.Reset, 0xffffffff);
- REG_WR (pDevice, Ftq.Reset, 0x0);
-
- LM_CntrlBlock (pDevice, T3_BLOCK_MBUF_MANAGER, LM_DISABLE);
- LM_CntrlBlock (pDevice, T3_BLOCK_MEM_ARBITOR, LM_DISABLE);
-
- MM_ACQUIRE_INT_LOCK (pDevice);
-
- /* Abort packets that have already queued to go out. */
- pPacket = (PLM_PACKET) QQ_PopHead (&pDevice->TxPacketActiveQ.Container);
- while (pPacket) {
-
- pPacket->PacketStatus = LM_STATUS_TRANSMIT_ABORTED;
- pDevice->TxCounters.TxPacketAbortedCnt++;
-
- atomic_add (pPacket->u.Tx.FragCount, &pDevice->SendBdLeft);
-
- QQ_PushTail (&pDevice->TxPacketXmittedQ.Container, pPacket);
-
- pPacket = (PLM_PACKET)
- QQ_PopHead (&pDevice->TxPacketActiveQ.Container);
- }
-
- /* Cleanup the receive return rings. */
- LM_ServiceRxInterrupt (pDevice);
-
- /* Don't want to indicate rx packets in Ndis miniport shutdown context. */
- /* Doing so may cause system crash. */
- if (!pDevice->ShuttingDown) {
- /* Indicate packets to the protocol. */
- MM_IndicateTxPackets (pDevice);
-
- /* Indicate received packets to the protocols. */
- MM_IndicateRxPackets (pDevice);
- } else {
- /* Move the receive packet descriptors in the ReceivedQ to the */
- /* free queue. */
- for (;;) {
- pPacket =
- (PLM_PACKET) QQ_PopHead (&pDevice->
- RxPacketReceivedQ.
- Container);
- if (pPacket == NULL) {
- break;
- }
- QQ_PushTail (&pDevice->RxPacketFreeQ.Container,
- pPacket);
- }
- }
-
- /* Clean up the Std Receive Producer ring. */
- Idx = pDevice->pStatusBlkVirt->RcvStdConIdx;
-
- while (Idx != pDevice->RxStdProdIdx) {
- pPacket = (PLM_PACKET) (MM_UINT_PTR (pDevice->pPacketDescBase) +
- MM_UINT_PTR (pDevice->pRxStdBdVirt[Idx].
- Opaque));
-
- QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
-
- Idx = (Idx + 1) & T3_STD_RCV_RCB_ENTRY_COUNT_MASK;
- } /* while */
-
- /* Reinitialize our copy of the indices. */
- pDevice->RxStdProdIdx = 0;
-
-#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- /* Clean up the Jumbo Receive Producer ring. */
- Idx = pDevice->pStatusBlkVirt->RcvJumboConIdx;
-
- while (Idx != pDevice->RxJumboProdIdx) {
- pPacket = (PLM_PACKET) (MM_UINT_PTR (pDevice->pPacketDescBase) +
- MM_UINT_PTR (pDevice->
- pRxJumboBdVirt[Idx].
- Opaque));
-
- QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
-
- Idx = (Idx + 1) & T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK;
- } /* while */
-
- /* Reinitialize our copy of the indices. */
- pDevice->RxJumboProdIdx = 0;
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
-
- MM_RELEASE_INT_LOCK (pDevice);
-
- /* Initialize the statistis Block */
- pDevice->pStatusBlkVirt->Status = 0;
- pDevice->pStatusBlkVirt->RcvStdConIdx = 0;
- pDevice->pStatusBlkVirt->RcvJumboConIdx = 0;
- pDevice->pStatusBlkVirt->RcvMiniConIdx = 0;
-
- return LM_STATUS_SUCCESS;
-} /* LM_Abort */
-
-/******************************************************************************/
-/* Description: */
-/* Disable the interrupt and put the transmitter and receiver engines in */
-/* an idle state. Aborts all pending send requests and receive buffers. */
-/* Also free all the receive buffers. */
-/* */
-/* Return: */
-/* LM_STATUS_SUCCESS */
-/******************************************************************************/
-LM_STATUS LM_Halt (PLM_DEVICE_BLOCK pDevice)
-{
- PLM_PACKET pPacket;
- LM_UINT32 EntryCnt;
-
- LM_Abort (pDevice);
-
- /* Get the number of entries in the queue. */
- EntryCnt = QQ_GetEntryCnt (&pDevice->RxPacketFreeQ.Container);
-
- /* Make sure all the packets have been accounted for. */
- for (EntryCnt = 0; EntryCnt < pDevice->RxPacketDescCnt; EntryCnt++) {
- pPacket =
- (PLM_PACKET) QQ_PopHead (&pDevice->RxPacketFreeQ.Container);
- if (pPacket == 0)
- break;
-
- MM_FreeRxBuffer (pDevice, pPacket);
-
- QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
- }
-
- LM_ResetChip (pDevice);
-
- /* Restore PCI configuration registers. */
- MM_WriteConfig32 (pDevice, PCI_CACHE_LINE_SIZE_REG,
- pDevice->SavedCacheLineReg);
- LM_RegWrInd (pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG,
- (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId);
-
- /* Reprogram the MAC address. */
- LM_SetMacAddress (pDevice);
-
- return LM_STATUS_SUCCESS;
-} /* LM_Halt */
-
-STATIC LM_STATUS LM_ResetChip (PLM_DEVICE_BLOCK pDevice)
-{
- LM_UINT32 Value32;
- LM_UINT32 j;
-
- /* Wait for access to the nvram interface before resetting. This is */
- /* a workaround to prevent EEPROM corruption. */
- if (T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
- T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5701) {
- /* Request access to the flash interface. */
- REG_WR (pDevice, Nvram.SwArb, SW_ARB_REQ_SET1);
-
- for (j = 0; j < 100000; j++) {
- Value32 = REG_RD (pDevice, Nvram.SwArb);
- if (Value32 & SW_ARB_GNT1) {
- break;
- }
- MM_Wait (10);
- }
- }
-
- /* Global reset. */
- REG_WR (pDevice, Grc.MiscCfg, GRC_MISC_CFG_CORE_CLOCK_RESET);
- MM_Wait (40);
- MM_Wait (40);
- MM_Wait (40);
-
- /* make sure we re-enable indirect accesses */
- MM_WriteConfig32 (pDevice, T3_PCI_MISC_HOST_CTRL_REG,
- pDevice->MiscHostCtrl);
-
- /* Set MAX PCI retry to zero. */
- Value32 =
- T3_PCI_STATE_PCI_ROM_ENABLE | T3_PCI_STATE_PCI_ROM_RETRY_ENABLE;
- if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) {
- if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) {
- Value32 |= T3_PCI_STATE_RETRY_SAME_DMA;
- }
- }
- MM_WriteConfig32 (pDevice, T3_PCI_STATE_REG, Value32);
-
- /* Restore PCI command register. */
- MM_WriteConfig32 (pDevice, PCI_COMMAND_REG,
- pDevice->PciCommandStatusWords);
-
- /* Disable PCI-X relaxed ordering bit. */
- MM_ReadConfig32 (pDevice, PCIX_CAP_REG, &Value32);
- Value32 &= ~PCIX_ENABLE_RELAXED_ORDERING;
- MM_WriteConfig32 (pDevice, PCIX_CAP_REG, Value32);
-
- /* Enable memory arbiter. */
- REG_WR (pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE);
-
-#ifdef BIG_ENDIAN_PCI /* This from jfd */
- Value32 = GRC_MODE_WORD_SWAP_DATA | GRC_MODE_WORD_SWAP_NON_FRAME_DATA;
-#else
-#ifdef BIG_ENDIAN_HOST
- /* Reconfigure the mode register. */
- Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
- GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
- GRC_MODE_BYTE_SWAP_DATA | GRC_MODE_WORD_SWAP_DATA;
-#else
- /* Reconfigure the mode register. */
- Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA;
-#endif
-#endif
- REG_WR (pDevice, Grc.Mode, Value32);
-
- /* Prevent PXE from restarting. */
- MEM_WR_OFFSET (pDevice, 0x0b50, T3_MAGIC_NUM);
-
- if (pDevice->EnableTbi) {
- pDevice->MacMode = MAC_MODE_PORT_MODE_TBI;
- REG_WR (pDevice, MacCtrl.Mode, MAC_MODE_PORT_MODE_TBI);
- } else {
- REG_WR (pDevice, MacCtrl.Mode, 0);
- }
-
- /* Wait for the firmware to finish initialization. */
- for (j = 0; j < 100000; j++) {
- MM_Wait (10);
-
- Value32 = MEM_RD_OFFSET (pDevice, 0x0b50);
- if (Value32 == ~T3_MAGIC_NUM) {
- break;
- }
- }
- return LM_STATUS_SUCCESS;
-}
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-__inline static void LM_ServiceTxInterrupt (PLM_DEVICE_BLOCK pDevice)
-{
- PLM_PACKET pPacket;
- LM_UINT32 HwConIdx;
- LM_UINT32 SwConIdx;
-
- HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx;
-
- /* Get our copy of the consumer index. The buffer descriptors */
- /* that are in between the consumer indices are freed. */
- SwConIdx = pDevice->SendConIdx;
-
- /* Move the packets from the TxPacketActiveQ that are sent out to */
- /* the TxPacketXmittedQ. Packets that are sent use the */
- /* descriptors that are between SwConIdx and HwConIdx. */
- while (SwConIdx != HwConIdx) {
- /* Get the packet that was sent from the TxPacketActiveQ. */
- pPacket =
- (PLM_PACKET) QQ_PopHead (&pDevice->TxPacketActiveQ.
- Container);
-
- /* Set the return status. */
- pPacket->PacketStatus = LM_STATUS_SUCCESS;
-
- /* Put the packet in the TxPacketXmittedQ for indication later. */
- QQ_PushTail (&pDevice->TxPacketXmittedQ.Container, pPacket);
-
- /* Move to the next packet's BD. */
- SwConIdx = (SwConIdx + pPacket->u.Tx.FragCount) &
- T3_SEND_RCB_ENTRY_COUNT_MASK;
-
- /* Update the number of unused BDs. */
- atomic_add (pPacket->u.Tx.FragCount, &pDevice->SendBdLeft);
-
- /* Get the new updated HwConIdx. */
- HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx;
- } /* while */
-
- /* Save the new SwConIdx. */
- pDevice->SendConIdx = SwConIdx;
-
-} /* LM_ServiceTxInterrupt */
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-__inline static void LM_ServiceRxInterrupt (PLM_DEVICE_BLOCK pDevice)
-{
- PLM_PACKET pPacket;
- PT3_RCV_BD pRcvBd;
- LM_UINT32 HwRcvRetProdIdx;
- LM_UINT32 SwRcvRetConIdx;
-
- /* Loop thru the receive return rings for received packets. */
- HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx;
-
- SwRcvRetConIdx = pDevice->RcvRetConIdx;
- while (SwRcvRetConIdx != HwRcvRetProdIdx) {
- pRcvBd = &pDevice->pRcvRetBdVirt[SwRcvRetConIdx];
-
- /* Get the received packet descriptor. */
- pPacket = (PLM_PACKET) (MM_UINT_PTR (pDevice->pPacketDescBase) +
- MM_UINT_PTR (pRcvBd->Opaque));
-
- /* Check the error flag. */
- if (pRcvBd->ErrorFlag &&
- pRcvBd->ErrorFlag != RCV_BD_ERR_ODD_NIBBLED_RCVD_MII) {
- pPacket->PacketStatus = LM_STATUS_FAILURE;
-
- pDevice->RxCounters.RxPacketErrCnt++;
-
- if (pRcvBd->ErrorFlag & RCV_BD_ERR_BAD_CRC) {
- pDevice->RxCounters.RxErrCrcCnt++;
- }
-
- if (pRcvBd->ErrorFlag & RCV_BD_ERR_COLL_DETECT) {
- pDevice->RxCounters.RxErrCollCnt++;
- }
-
- if (pRcvBd->ErrorFlag & RCV_BD_ERR_LINK_LOST_DURING_PKT) {
- pDevice->RxCounters.RxErrLinkLostCnt++;
- }
-
- if (pRcvBd->ErrorFlag & RCV_BD_ERR_PHY_DECODE_ERR) {
- pDevice->RxCounters.RxErrPhyDecodeCnt++;
- }
-
- if (pRcvBd->ErrorFlag & RCV_BD_ERR_ODD_NIBBLED_RCVD_MII) {
- pDevice->RxCounters.RxErrOddNibbleCnt++;
- }
-
- if (pRcvBd->ErrorFlag & RCV_BD_ERR_MAC_ABORT) {
- pDevice->RxCounters.RxErrMacAbortCnt++;
- }
-
- if (pRcvBd->ErrorFlag & RCV_BD_ERR_LEN_LT_64) {
- pDevice->RxCounters.RxErrShortPacketCnt++;
- }
-
- if (pRcvBd->ErrorFlag & RCV_BD_ERR_TRUNC_NO_RESOURCES) {
- pDevice->RxCounters.RxErrNoResourceCnt++;
- }
-
- if (pRcvBd->ErrorFlag & RCV_BD_ERR_GIANT_FRAME_RCVD) {
- pDevice->RxCounters.RxErrLargePacketCnt++;
- }
- } else {
- pPacket->PacketStatus = LM_STATUS_SUCCESS;
- pPacket->PacketSize = pRcvBd->Len - 4;
-
- pPacket->Flags = pRcvBd->Flags;
- if (pRcvBd->Flags & RCV_BD_FLAG_VLAN_TAG) {
- pPacket->VlanTag = pRcvBd->VlanTag;
- }
-
- pPacket->u.Rx.TcpUdpChecksum = pRcvBd->TcpUdpCksum;
- }
-
- /* Put the packet descriptor containing the received packet */
- /* buffer in the RxPacketReceivedQ for indication later. */
- QQ_PushTail (&pDevice->RxPacketReceivedQ.Container, pPacket);
-
- /* Go to the next buffer descriptor. */
- SwRcvRetConIdx = (SwRcvRetConIdx + 1) &
- T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK;
-
- /* Get the updated HwRcvRetProdIdx. */
- HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx;
- } /* while */
-
- pDevice->RcvRetConIdx = SwRcvRetConIdx;
-
- /* Update the receive return ring consumer index. */
- MB_REG_WR (pDevice, Mailbox.RcvRetConIdx[0].Low, SwRcvRetConIdx);
-} /* LM_ServiceRxInterrupt */
-
-/******************************************************************************/
-/* Description: */
-/* This is the interrupt event handler routine. It acknowledges all */
-/* pending interrupts and process all pending events. */
-/* */
-/* Return: */
-/* LM_STATUS_SUCCESS */
-/******************************************************************************/
-LM_STATUS LM_ServiceInterrupts (PLM_DEVICE_BLOCK pDevice)
-{
- LM_UINT32 Value32;
- int ServicePhyInt = FALSE;
-
- /* Setup the phy chip whenever the link status changes. */
- if (pDevice->LinkChngMode == T3_LINK_CHNG_MODE_USE_STATUS_REG) {
- Value32 = REG_RD (pDevice, MacCtrl.Status);
- if (pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) {
- if (Value32 & MAC_STATUS_MI_INTERRUPT) {
- ServicePhyInt = TRUE;
- }
- } else if (Value32 & MAC_STATUS_LINK_STATE_CHANGED) {
- ServicePhyInt = TRUE;
- }
- } else {
- if (pDevice->pStatusBlkVirt->
- Status & STATUS_BLOCK_LINK_CHANGED_STATUS) {
- pDevice->pStatusBlkVirt->Status =
- STATUS_BLOCK_UPDATED | (pDevice->pStatusBlkVirt->
- Status &
- ~STATUS_BLOCK_LINK_CHANGED_STATUS);
- ServicePhyInt = TRUE;
- }
- }
-#if INCLUDE_TBI_SUPPORT
- if (pDevice->IgnoreTbiLinkChange == TRUE) {
- ServicePhyInt = FALSE;
- }
-#endif
- if (ServicePhyInt == TRUE) {
- LM_SetupPhy (pDevice);
- }
-
- /* Service receive and transmit interrupts. */
- LM_ServiceRxInterrupt (pDevice);
- LM_ServiceTxInterrupt (pDevice);
-
- /* No spinlock for this queue since this routine is serialized. */
- if (!QQ_Empty (&pDevice->RxPacketReceivedQ.Container)) {
- /* Indicate receive packets. */
- MM_IndicateRxPackets (pDevice);
- /* LM_QueueRxPackets(pDevice); */
- }
-
- /* No spinlock for this queue since this routine is serialized. */
- if (!QQ_Empty (&pDevice->TxPacketXmittedQ.Container)) {
- MM_IndicateTxPackets (pDevice);
- }
-
- return LM_STATUS_SUCCESS;
-} /* LM_ServiceInterrupts */
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-LM_STATUS LM_MulticastAdd (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress)
-{
- PLM_UINT8 pEntry;
- LM_UINT32 j;
-
- pEntry = pDevice->McTable[0];
- for (j = 0; j < pDevice->McEntryCount; j++) {
- if (IS_ETH_ADDRESS_EQUAL (pEntry, pMcAddress)) {
- /* Found a match, increment the instance count. */
- pEntry[LM_MC_INSTANCE_COUNT_INDEX] += 1;
-
- return LM_STATUS_SUCCESS;
- }
-
- pEntry += LM_MC_ENTRY_SIZE;
- }
-
- if (pDevice->McEntryCount >= LM_MAX_MC_TABLE_SIZE) {
- return LM_STATUS_FAILURE;
- }
-
- pEntry = pDevice->McTable[pDevice->McEntryCount];
-
- COPY_ETH_ADDRESS (pMcAddress, pEntry);
- pEntry[LM_MC_INSTANCE_COUNT_INDEX] = 1;
-
- pDevice->McEntryCount++;
-
- LM_SetReceiveMask (pDevice, pDevice->ReceiveMask | LM_ACCEPT_MULTICAST);
-
- return LM_STATUS_SUCCESS;
-} /* LM_MulticastAdd */
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-LM_STATUS LM_MulticastDel (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress)
-{
- PLM_UINT8 pEntry;
- LM_UINT32 j;
-
- pEntry = pDevice->McTable[0];
- for (j = 0; j < pDevice->McEntryCount; j++) {
- if (IS_ETH_ADDRESS_EQUAL (pEntry, pMcAddress)) {
- /* Found a match, decrement the instance count. */
- pEntry[LM_MC_INSTANCE_COUNT_INDEX] -= 1;
-
- /* No more instance left, remove the address from the table. */
- /* Move the last entry in the table to the delete slot. */
- if (pEntry[LM_MC_INSTANCE_COUNT_INDEX] == 0 &&
- pDevice->McEntryCount > 1) {
-
- COPY_ETH_ADDRESS (pDevice->
- McTable[pDevice->
- McEntryCount - 1],
- pEntry);
- pEntry[LM_MC_INSTANCE_COUNT_INDEX] =
- pDevice->McTable[pDevice->McEntryCount - 1]
- [LM_MC_INSTANCE_COUNT_INDEX];
- }
- pDevice->McEntryCount--;
-
- /* Update the receive mask if the table is empty. */
- if (pDevice->McEntryCount == 0) {
- LM_SetReceiveMask (pDevice,
- pDevice->
- ReceiveMask &
- ~LM_ACCEPT_MULTICAST);
- }
-
- return LM_STATUS_SUCCESS;
- }
-
- pEntry += LM_MC_ENTRY_SIZE;
- }
-
- return LM_STATUS_FAILURE;
-} /* LM_MulticastDel */
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-LM_STATUS LM_MulticastClear (PLM_DEVICE_BLOCK pDevice)
-{
- pDevice->McEntryCount = 0;
-
- LM_SetReceiveMask (pDevice,
- pDevice->ReceiveMask & ~LM_ACCEPT_MULTICAST);
-
- return LM_STATUS_SUCCESS;
-} /* LM_MulticastClear */
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-LM_STATUS LM_SetMacAddress (PLM_DEVICE_BLOCK pDevice)
-{
- LM_UINT32 j;
- PLM_UINT8 pMacAddress = pDevice->NodeAddress;
-
- for (j = 0; j < 4; j++) {
- REG_WR (pDevice, MacCtrl.MacAddr[j].High,
- (pMacAddress[0] << 8) | pMacAddress[1]);
- REG_WR (pDevice, MacCtrl.MacAddr[j].Low,
- (pMacAddress[2] << 24) | (pMacAddress[3] << 16) |
- (pMacAddress[4] << 8) | pMacAddress[5]);
- }
-
- return LM_STATUS_SUCCESS;
-}
-
-/******************************************************************************/
-/* Description: */
-/* Sets up the default line speed, and duplex modes based on the requested */
-/* media type. */
-/* */
-/* Return: */
-/* None. */
-/******************************************************************************/
-static LM_STATUS
-LM_TranslateRequestedMediaType (LM_REQUESTED_MEDIA_TYPE RequestedMediaType,
- PLM_MEDIA_TYPE pMediaType,
- PLM_LINE_SPEED pLineSpeed,
- PLM_DUPLEX_MODE pDuplexMode)
-{
- *pMediaType = LM_MEDIA_TYPE_AUTO;
- *pLineSpeed = LM_LINE_SPEED_UNKNOWN;
- *pDuplexMode = LM_DUPLEX_MODE_UNKNOWN;
-
- /* determine media type */
- switch (RequestedMediaType) {
- case LM_REQUESTED_MEDIA_TYPE_BNC:
- *pMediaType = LM_MEDIA_TYPE_BNC;
- *pLineSpeed = LM_LINE_SPEED_10MBPS;
- *pDuplexMode = LM_DUPLEX_MODE_HALF;
- break;
-
- case LM_REQUESTED_MEDIA_TYPE_UTP_AUTO:
- *pMediaType = LM_MEDIA_TYPE_UTP;
- break;
-
- case LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS:
- *pMediaType = LM_MEDIA_TYPE_UTP;
- *pLineSpeed = LM_LINE_SPEED_10MBPS;
- *pDuplexMode = LM_DUPLEX_MODE_HALF;
- break;
-
- case LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS_FULL_DUPLEX:
- *pMediaType = LM_MEDIA_TYPE_UTP;
- *pLineSpeed = LM_LINE_SPEED_10MBPS;
- *pDuplexMode = LM_DUPLEX_MODE_FULL;
- break;
-
- case LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS:
- *pMediaType = LM_MEDIA_TYPE_UTP;
- *pLineSpeed = LM_LINE_SPEED_100MBPS;
- *pDuplexMode = LM_DUPLEX_MODE_HALF;
- break;
-
- case LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS_FULL_DUPLEX:
- *pMediaType = LM_MEDIA_TYPE_UTP;
- *pLineSpeed = LM_LINE_SPEED_100MBPS;
- *pDuplexMode = LM_DUPLEX_MODE_FULL;
- break;
-
- case LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS:
- *pMediaType = LM_MEDIA_TYPE_UTP;
- *pLineSpeed = LM_LINE_SPEED_1000MBPS;
- *pDuplexMode = LM_DUPLEX_MODE_HALF;
- break;
-
- case LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS_FULL_DUPLEX:
- *pMediaType = LM_MEDIA_TYPE_UTP;
- *pLineSpeed = LM_LINE_SPEED_1000MBPS;
- *pDuplexMode = LM_DUPLEX_MODE_FULL;
- break;
-
- case LM_REQUESTED_MEDIA_TYPE_FIBER_100MBPS:
- *pMediaType = LM_MEDIA_TYPE_FIBER;
- *pLineSpeed = LM_LINE_SPEED_100MBPS;
- *pDuplexMode = LM_DUPLEX_MODE_HALF;
- break;
-
- case LM_REQUESTED_MEDIA_TYPE_FIBER_100MBPS_FULL_DUPLEX:
- *pMediaType = LM_MEDIA_TYPE_FIBER;
- *pLineSpeed = LM_LINE_SPEED_100MBPS;
- *pDuplexMode = LM_DUPLEX_MODE_FULL;
- break;
-
- case LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS:
- *pMediaType = LM_MEDIA_TYPE_FIBER;
- *pLineSpeed = LM_LINE_SPEED_1000MBPS;
- *pDuplexMode = LM_DUPLEX_MODE_HALF;
- break;
-
- case LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS_FULL_DUPLEX:
- *pMediaType = LM_MEDIA_TYPE_FIBER;
- *pLineSpeed = LM_LINE_SPEED_1000MBPS;
- *pDuplexMode = LM_DUPLEX_MODE_FULL;
- break;
-
- default:
- break;
- } /* switch */
-
- return LM_STATUS_SUCCESS;
-} /* LM_TranslateRequestedMediaType */
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/* LM_STATUS_LINK_ACTIVE */
-/* LM_STATUS_LINK_DOWN */
-/******************************************************************************/
-static LM_STATUS LM_InitBcm540xPhy (PLM_DEVICE_BLOCK pDevice)
-{
- LM_LINE_SPEED CurrentLineSpeed;
- LM_DUPLEX_MODE CurrentDuplexMode;
- LM_STATUS CurrentLinkStatus;
- LM_UINT32 Value32;
- LM_UINT32 j;
-
-#if 1 /* jmb: bugfix -- moved here, out of code that sets initial pwr state */
- LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x2);
-#endif
- if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) {
- LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
- LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
-
- if (!pDevice->InitDone) {
- Value32 = 0;
- }
-
- if (!(Value32 & PHY_STATUS_LINK_PASS)) {
- LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x0c20);
-
- LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012);
- LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x1804);
-
- LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013);
- LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x1204);
-
- LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
- LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0132);
-
- LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
- LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0232);
-
- LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f);
- LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0a20);
-
- LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
- for (j = 0; j < 1000; j++) {
- MM_Wait (10);
-
- LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
- if (Value32 & PHY_STATUS_LINK_PASS) {
- MM_Wait (40);
- break;
- }
- }
-
- if ((pDevice->PhyId & PHY_ID_REV_MASK) ==
- PHY_BCM5401_B0_REV) {
- if (!(Value32 & PHY_STATUS_LINK_PASS)
- && (pDevice->OldLineSpeed ==
- LM_LINE_SPEED_1000MBPS)) {
- LM_WritePhy (pDevice, PHY_CTRL_REG,
- PHY_CTRL_PHY_RESET);
- for (j = 0; j < 100; j++) {
- MM_Wait (10);
-
- LM_ReadPhy (pDevice,
- PHY_CTRL_REG,
- &Value32);
- if (!
- (Value32 &
- PHY_CTRL_PHY_RESET)) {
- MM_Wait (40);
- break;
- }
- }
-
- LM_WritePhy (pDevice, BCM5401_AUX_CTRL,
- 0x0c20);
-
- LM_WritePhy (pDevice,
- BCM540X_DSP_ADDRESS_REG,
- 0x0012);
- LM_WritePhy (pDevice,
- BCM540X_DSP_RW_PORT,
- 0x1804);
-
- LM_WritePhy (pDevice,
- BCM540X_DSP_ADDRESS_REG,
- 0x0013);
- LM_WritePhy (pDevice,
- BCM540X_DSP_RW_PORT,
- 0x1204);
-
- LM_WritePhy (pDevice,
- BCM540X_DSP_ADDRESS_REG,
- 0x8006);
- LM_WritePhy (pDevice,
- BCM540X_DSP_RW_PORT,
- 0x0132);
-
- LM_WritePhy (pDevice,
- BCM540X_DSP_ADDRESS_REG,
- 0x8006);
- LM_WritePhy (pDevice,
- BCM540X_DSP_RW_PORT,
- 0x0232);
-
- LM_WritePhy (pDevice,
- BCM540X_DSP_ADDRESS_REG,
- 0x201f);
- LM_WritePhy (pDevice,
- BCM540X_DSP_RW_PORT,
- 0x0a20);
- }
- }
- }
- } else if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
- pDevice->ChipRevId == T3_CHIP_ID_5701_B0) {
- /* Bug: 5701 A0, B0 TX CRC workaround. */
- LM_WritePhy (pDevice, 0x15, 0x0a75);
- LM_WritePhy (pDevice, 0x1c, 0x8c68);
- LM_WritePhy (pDevice, 0x1c, 0x8d68);
- LM_WritePhy (pDevice, 0x1c, 0x8c68);
- }
-
- /* Acknowledge interrupts. */
- LM_ReadPhy (pDevice, BCM540X_INT_STATUS_REG, &Value32);
- LM_ReadPhy (pDevice, BCM540X_INT_STATUS_REG, &Value32);
-
- /* Configure the interrupt mask. */
- if (pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) {
- LM_WritePhy (pDevice, BCM540X_INT_MASK_REG,
- ~BCM540X_INT_LINK_CHANGE);
- }
-
- /* Configure PHY led mode. */
- if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701 ||
- (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700)) {
- if (pDevice->LedMode == LED_MODE_THREE_LINK) {
- LM_WritePhy (pDevice, BCM540X_EXT_CTRL_REG,
- BCM540X_EXT_CTRL_LINK3_LED_MODE);
- } else {
- LM_WritePhy (pDevice, BCM540X_EXT_CTRL_REG, 0);
- }
- }
-
- CurrentLinkStatus = LM_STATUS_LINK_DOWN;
-
- /* Get current link and duplex mode. */
- for (j = 0; j < 100; j++) {
- LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
- LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
-
- if (Value32 & PHY_STATUS_LINK_PASS) {
- break;
- }
- MM_Wait (40);
- }
-
- if (Value32 & PHY_STATUS_LINK_PASS) {
-
- /* Determine the current line and duplex settings. */
- LM_ReadPhy (pDevice, BCM540X_AUX_STATUS_REG, &Value32);
- for (j = 0; j < 2000; j++) {
- MM_Wait (10);
-
- LM_ReadPhy (pDevice, BCM540X_AUX_STATUS_REG, &Value32);
- if (Value32) {
- break;
- }
- }
-
- switch (Value32 & BCM540X_AUX_SPEED_MASK) {
- case BCM540X_AUX_10BASET_HD:
- CurrentLineSpeed = LM_LINE_SPEED_10MBPS;
- CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
- break;
-
- case BCM540X_AUX_10BASET_FD:
- CurrentLineSpeed = LM_LINE_SPEED_10MBPS;
- CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
- break;
-
- case BCM540X_AUX_100BASETX_HD:
- CurrentLineSpeed = LM_LINE_SPEED_100MBPS;
- CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
- break;
-
- case BCM540X_AUX_100BASETX_FD:
- CurrentLineSpeed = LM_LINE_SPEED_100MBPS;
- CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
- break;
-
- case BCM540X_AUX_100BASET_HD:
- CurrentLineSpeed = LM_LINE_SPEED_1000MBPS;
- CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
- break;
-
- case BCM540X_AUX_100BASET_FD:
- CurrentLineSpeed = LM_LINE_SPEED_1000MBPS;
- CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
- break;
-
- default:
-
- CurrentLineSpeed = LM_LINE_SPEED_UNKNOWN;
- CurrentDuplexMode = LM_DUPLEX_MODE_UNKNOWN;
- break;
- }
-
- /* Make sure we are in auto-neg mode. */
- for (j = 0; j < 200; j++) {
- LM_ReadPhy (pDevice, PHY_CTRL_REG, &Value32);
- if (Value32 && Value32 != 0x7fff) {
- break;
- }
-
- if (Value32 == 0 && pDevice->RequestedMediaType ==
- LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS) {
- break;
- }
-
- MM_Wait (10);
- }
-
- /* Use the current line settings for "auto" mode. */
- if (pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO
- || pDevice->RequestedMediaType ==
- LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) {
- if (Value32 & PHY_CTRL_AUTO_NEG_ENABLE) {
- CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
-
- /* We may be exiting low power mode and the link is in */
- /* 10mb. In this case, we need to restart autoneg. */
- LM_ReadPhy (pDevice, BCM540X_1000BASET_CTRL_REG,
- &Value32);
- pDevice->advertising1000 = Value32;
- /* 5702FE supports 10/100Mb only. */
- if (T3_ASIC_REV (pDevice->ChipRevId) !=
- T3_ASIC_REV_5703
- || pDevice->BondId !=
- GRC_MISC_BD_ID_5702FE) {
- if (!
- (Value32 &
- (BCM540X_AN_AD_1000BASET_HALF |
- BCM540X_AN_AD_1000BASET_FULL))) {
- CurrentLinkStatus =
- LM_STATUS_LINK_SETTING_MISMATCH;
- }
- }
- } else {
- CurrentLinkStatus =
- LM_STATUS_LINK_SETTING_MISMATCH;
- }
- } else {
- /* Force line settings. */
- /* Use the current setting if it matches the user's requested */
- /* setting. */
- LM_ReadPhy (pDevice, PHY_CTRL_REG, &Value32);
- if ((pDevice->LineSpeed == CurrentLineSpeed) &&
- (pDevice->DuplexMode == CurrentDuplexMode)) {
- if ((pDevice->DisableAutoNeg &&
- !(Value32 & PHY_CTRL_AUTO_NEG_ENABLE)) ||
- (!pDevice->DisableAutoNeg &&
- (Value32 & PHY_CTRL_AUTO_NEG_ENABLE))) {
- CurrentLinkStatus =
- LM_STATUS_LINK_ACTIVE;
- } else {
- CurrentLinkStatus =
- LM_STATUS_LINK_SETTING_MISMATCH;
- }
- } else {
- CurrentLinkStatus =
- LM_STATUS_LINK_SETTING_MISMATCH;
- }
- }
-
- /* Save line settings. */
- pDevice->LineSpeed = CurrentLineSpeed;
- pDevice->DuplexMode = CurrentDuplexMode;
- pDevice->MediaType = LM_MEDIA_TYPE_UTP;
- }
-
- return CurrentLinkStatus;
-} /* LM_InitBcm540xPhy */
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-LM_STATUS
-LM_SetFlowControl (PLM_DEVICE_BLOCK pDevice,
- LM_UINT32 LocalPhyAd, LM_UINT32 RemotePhyAd)
-{
- LM_FLOW_CONTROL FlowCap;
-
- /* Resolve flow control. */
- FlowCap = LM_FLOW_CONTROL_NONE;
-
- /* See Table 28B-3 of 802.3ab-1999 spec. */
- if (pDevice->FlowControlCap & LM_FLOW_CONTROL_AUTO_PAUSE) {
- if (LocalPhyAd & PHY_AN_AD_PAUSE_CAPABLE) {
- if (LocalPhyAd & PHY_AN_AD_ASYM_PAUSE) {
- if (RemotePhyAd &
- PHY_LINK_PARTNER_PAUSE_CAPABLE) {
- FlowCap =
- LM_FLOW_CONTROL_TRANSMIT_PAUSE |
- LM_FLOW_CONTROL_RECEIVE_PAUSE;
- } else if (RemotePhyAd &
- PHY_LINK_PARTNER_ASYM_PAUSE) {
- FlowCap = LM_FLOW_CONTROL_RECEIVE_PAUSE;
- }
- } else {
- if (RemotePhyAd &
- PHY_LINK_PARTNER_PAUSE_CAPABLE) {
- FlowCap =
- LM_FLOW_CONTROL_TRANSMIT_PAUSE |
- LM_FLOW_CONTROL_RECEIVE_PAUSE;
- }
- }
- } else if (LocalPhyAd & PHY_AN_AD_ASYM_PAUSE) {
- if ((RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) &&
- (RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE)) {
- FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE;
- }
- }
- } else {
- FlowCap = pDevice->FlowControlCap;
- }
-
- /* Enable/disable rx PAUSE. */
- pDevice->RxMode &= ~RX_MODE_ENABLE_FLOW_CONTROL;
- if (FlowCap & LM_FLOW_CONTROL_RECEIVE_PAUSE &&
- (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE ||
- pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE)) {
- pDevice->FlowControl |= LM_FLOW_CONTROL_RECEIVE_PAUSE;
- pDevice->RxMode |= RX_MODE_ENABLE_FLOW_CONTROL;
-
- }
- REG_WR (pDevice, MacCtrl.RxMode, pDevice->RxMode);
-
- /* Enable/disable tx PAUSE. */
- pDevice->TxMode &= ~TX_MODE_ENABLE_FLOW_CONTROL;
- if (FlowCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE &&
- (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE ||
- pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)) {
- pDevice->FlowControl |= LM_FLOW_CONTROL_TRANSMIT_PAUSE;
- pDevice->TxMode |= TX_MODE_ENABLE_FLOW_CONTROL;
-
- }
- REG_WR (pDevice, MacCtrl.TxMode, pDevice->TxMode);
-
- return LM_STATUS_SUCCESS;
-}
-
-#if INCLUDE_TBI_SUPPORT
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-STATIC LM_STATUS LM_InitBcm800xPhy (PLM_DEVICE_BLOCK pDevice)
-{
- LM_UINT32 Value32;
- LM_UINT32 j;
-
- Value32 = REG_RD (pDevice, MacCtrl.Status);
-
- /* Reset the SERDES during init and when we have link. */
- if (!pDevice->InitDone || Value32 & MAC_STATUS_PCS_SYNCED) {
- /* Set PLL lock range. */
- LM_WritePhy (pDevice, 0x16, 0x8007);
-
- /* Software reset. */
- LM_WritePhy (pDevice, 0x00, 0x8000);
-
- /* Wait for reset to complete. */
- for (j = 0; j < 500; j++) {
- MM_Wait (10);
- }
-
- /* Config mode; seletct PMA/Ch 1 regs. */
- LM_WritePhy (pDevice, 0x10, 0x8411);
-
- /* Enable auto-lock and comdet, select txclk for tx. */
- LM_WritePhy (pDevice, 0x11, 0x0a10);
-
- LM_WritePhy (pDevice, 0x18, 0x00a0);
- LM_WritePhy (pDevice, 0x16, 0x41ff);
-
- /* Assert and deassert POR. */
- LM_WritePhy (pDevice, 0x13, 0x0400);
- MM_Wait (40);
- LM_WritePhy (pDevice, 0x13, 0x0000);
-
- LM_WritePhy (pDevice, 0x11, 0x0a50);
- MM_Wait (40);
- LM_WritePhy (pDevice, 0x11, 0x0a10);
-
- /* Delay for signal to stabilize. */
- for (j = 0; j < 15000; j++) {
- MM_Wait (10);
- }
-
- /* Deselect the channel register so we can read the PHY id later. */
- LM_WritePhy (pDevice, 0x10, 0x8011);
- }
-
- return LM_STATUS_SUCCESS;
-}
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-STATIC LM_STATUS LM_SetupFiberPhy (PLM_DEVICE_BLOCK pDevice)
-{
- LM_STATUS CurrentLinkStatus;
- AUTONEG_STATUS AnStatus = 0;
- LM_UINT32 Value32;
- LM_UINT32 Cnt;
- LM_UINT32 j, k;
-
- pDevice->MacMode &= ~(MAC_MODE_HALF_DUPLEX | MAC_MODE_PORT_MODE_MASK);
-
- /* Initialize the send_config register. */
- REG_WR (pDevice, MacCtrl.TxAutoNeg, 0);
-
- /* Enable TBI and full duplex mode. */
- pDevice->MacMode |= MAC_MODE_PORT_MODE_TBI;
- REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode);
-
- /* Initialize the BCM8002 SERDES PHY. */
- switch (pDevice->PhyId & PHY_ID_MASK) {
- case PHY_BCM8002_PHY_ID:
- LM_InitBcm800xPhy (pDevice);
- break;
-
- default:
- break;
- }
-
- /* Enable link change interrupt. */
- REG_WR (pDevice, MacCtrl.MacEvent,
- MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN);
-
- /* Default to link down. */
- CurrentLinkStatus = LM_STATUS_LINK_DOWN;
-
- /* Get the link status. */
- Value32 = REG_RD (pDevice, MacCtrl.Status);
- if (Value32 & MAC_STATUS_PCS_SYNCED) {
- if ((pDevice->RequestedMediaType ==
- LM_REQUESTED_MEDIA_TYPE_AUTO)
- || (pDevice->DisableAutoNeg == FALSE)) {
- /* auto-negotiation mode. */
- /* Initialize the autoneg default capaiblities. */
- AutonegInit (&pDevice->AnInfo);
-
- /* Set the context pointer to point to the main device structure. */
- pDevice->AnInfo.pContext = pDevice;
-
- /* Setup flow control advertisement register. */
- Value32 = GetPhyAdFlowCntrlSettings (pDevice);
- if (Value32 & PHY_AN_AD_PAUSE_CAPABLE) {
- pDevice->AnInfo.mr_adv_sym_pause = 1;
- } else {
- pDevice->AnInfo.mr_adv_sym_pause = 0;
- }
-
- if (Value32 & PHY_AN_AD_ASYM_PAUSE) {
- pDevice->AnInfo.mr_adv_asym_pause = 1;
- } else {
- pDevice->AnInfo.mr_adv_asym_pause = 0;
- }
-
- /* Try to autoneg up to six times. */
- if (pDevice->IgnoreTbiLinkChange) {
- Cnt = 1;
- } else {
- Cnt = 6;
- }
- for (j = 0; j < Cnt; j++) {
- REG_WR (pDevice, MacCtrl.TxAutoNeg, 0);
-
- Value32 =
- pDevice->MacMode & ~MAC_MODE_PORT_MODE_MASK;
- REG_WR (pDevice, MacCtrl.Mode, Value32);
- MM_Wait (20);
-
- REG_WR (pDevice, MacCtrl.Mode,
- pDevice->
- MacMode | MAC_MODE_SEND_CONFIGS);
-
- MM_Wait (20);
-
- pDevice->AnInfo.State = AN_STATE_UNKNOWN;
- pDevice->AnInfo.CurrentTime_us = 0;
-
- REG_WR (pDevice, Grc.Timer, 0);
- for (k = 0;
- (pDevice->AnInfo.CurrentTime_us < 75000)
- && (k < 75000); k++) {
- AnStatus =
- Autoneg8023z (&pDevice->AnInfo);
-
- if ((AnStatus == AUTONEG_STATUS_DONE) ||
- (AnStatus == AUTONEG_STATUS_FAILED))
- {
- break;
- }
-
- pDevice->AnInfo.CurrentTime_us =
- REG_RD (pDevice, Grc.Timer);
-
- }
- if ((AnStatus == AUTONEG_STATUS_DONE) ||
- (AnStatus == AUTONEG_STATUS_FAILED)) {
- break;
- }
- if (j >= 1) {
- if (!(REG_RD (pDevice, MacCtrl.Status) &
- MAC_STATUS_PCS_SYNCED)) {
- break;
- }
- }
- }
-
- /* Stop sending configs. */
- MM_AnTxIdle (&pDevice->AnInfo);
-
- /* Resolve flow control settings. */
- if ((AnStatus == AUTONEG_STATUS_DONE) &&
- pDevice->AnInfo.mr_an_complete
- && pDevice->AnInfo.mr_link_ok
- && pDevice->AnInfo.mr_lp_adv_full_duplex) {
- LM_UINT32 RemotePhyAd;
- LM_UINT32 LocalPhyAd;
-
- LocalPhyAd = 0;
- if (pDevice->AnInfo.mr_adv_sym_pause) {
- LocalPhyAd |= PHY_AN_AD_PAUSE_CAPABLE;
- }
-
- if (pDevice->AnInfo.mr_adv_asym_pause) {
- LocalPhyAd |= PHY_AN_AD_ASYM_PAUSE;
- }
-
- RemotePhyAd = 0;
- if (pDevice->AnInfo.mr_lp_adv_sym_pause) {
- RemotePhyAd |=
- PHY_LINK_PARTNER_PAUSE_CAPABLE;
- }
-
- if (pDevice->AnInfo.mr_lp_adv_asym_pause) {
- RemotePhyAd |=
- PHY_LINK_PARTNER_ASYM_PAUSE;
- }
-
- LM_SetFlowControl (pDevice, LocalPhyAd,
- RemotePhyAd);
-
- CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
- }
- for (j = 0; j < 30; j++) {
- MM_Wait (20);
- REG_WR (pDevice, MacCtrl.Status,
- MAC_STATUS_SYNC_CHANGED |
- MAC_STATUS_CFG_CHANGED);
- MM_Wait (20);
- if ((REG_RD (pDevice, MacCtrl.Status) &
- (MAC_STATUS_SYNC_CHANGED |
- MAC_STATUS_CFG_CHANGED)) == 0)
- break;
- }
- if (pDevice->PollTbiLink) {
- Value32 = REG_RD (pDevice, MacCtrl.Status);
- if (Value32 & MAC_STATUS_RECEIVING_CFG) {
- pDevice->IgnoreTbiLinkChange = TRUE;
- } else {
- pDevice->IgnoreTbiLinkChange = FALSE;
- }
- }
- Value32 = REG_RD (pDevice, MacCtrl.Status);
- if (CurrentLinkStatus == LM_STATUS_LINK_DOWN &&
- (Value32 & MAC_STATUS_PCS_SYNCED) &&
- ((Value32 & MAC_STATUS_RECEIVING_CFG) == 0)) {
- CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
- }
- } else {
- /* We are forcing line speed. */
- pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE;
- LM_SetFlowControl (pDevice, 0, 0);
-
- CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
- REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode |
- MAC_MODE_SEND_CONFIGS);
- }
- }
- /* Set the link polarity bit. */
- pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY;
- REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode);
-
- pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED |
- (pDevice->pStatusBlkVirt->
- Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS);
-
- for (j = 0; j < 100; j++) {
- REG_WR (pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
- MAC_STATUS_CFG_CHANGED);
- MM_Wait (5);
- if ((REG_RD (pDevice, MacCtrl.Status) &
- (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0)
- break;
- }
-
- Value32 = REG_RD (pDevice, MacCtrl.Status);
- if ((Value32 & MAC_STATUS_PCS_SYNCED) == 0) {
- CurrentLinkStatus = LM_STATUS_LINK_DOWN;
- if (pDevice->DisableAutoNeg == FALSE) {
- REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode |
- MAC_MODE_SEND_CONFIGS);
- MM_Wait (1);
- REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode);
- }
- }
-
- /* Initialize the current link status. */
- if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) {
- pDevice->LineSpeed = LM_LINE_SPEED_1000MBPS;
- pDevice->DuplexMode = LM_DUPLEX_MODE_FULL;
- REG_WR (pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED |
- LED_CTRL_1000MBPS_LED_ON);
- } else {
- pDevice->LineSpeed = LM_LINE_SPEED_UNKNOWN;
- pDevice->DuplexMode = LM_DUPLEX_MODE_UNKNOWN;
- REG_WR (pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED |
- LED_CTRL_OVERRIDE_TRAFFIC_LED);
- }
-
- /* Indicate link status. */
- if (pDevice->LinkStatus != CurrentLinkStatus) {
- pDevice->LinkStatus = CurrentLinkStatus;
- MM_IndicateStatus (pDevice, CurrentLinkStatus);
- }
-
- return LM_STATUS_SUCCESS;
-}
-#endif /* INCLUDE_TBI_SUPPORT */
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-LM_STATUS LM_SetupCopperPhy (PLM_DEVICE_BLOCK pDevice)
-{
- LM_STATUS CurrentLinkStatus;
- LM_UINT32 Value32;
-
- /* Assume there is not link first. */
- CurrentLinkStatus = LM_STATUS_LINK_DOWN;
-
- /* Disable phy link change attention. */
- REG_WR (pDevice, MacCtrl.MacEvent, 0);
-
- /* Clear link change attention. */
- REG_WR (pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
- MAC_STATUS_CFG_CHANGED);
-
- /* Disable auto-polling for the moment. */
- pDevice->MiMode = 0xc0000;
- REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode);
- MM_Wait (40);
-
- /* Determine the requested line speed and duplex. */
- pDevice->OldLineSpeed = pDevice->LineSpeed;
- LM_TranslateRequestedMediaType (pDevice->RequestedMediaType,
- &pDevice->MediaType,
- &pDevice->LineSpeed,
- &pDevice->DuplexMode);
-
- /* Initialize the phy chip. */
- switch (pDevice->PhyId & PHY_ID_MASK) {
- case PHY_BCM5400_PHY_ID:
- case PHY_BCM5401_PHY_ID:
- case PHY_BCM5411_PHY_ID:
- case PHY_BCM5701_PHY_ID:
- case PHY_BCM5703_PHY_ID:
- case PHY_BCM5704_PHY_ID:
- CurrentLinkStatus = LM_InitBcm540xPhy (pDevice);
- break;
-
- default:
- break;
- }
-
- if (CurrentLinkStatus == LM_STATUS_LINK_SETTING_MISMATCH) {
- CurrentLinkStatus = LM_STATUS_LINK_DOWN;
- }
-
- /* Setup flow control. */
- pDevice->FlowControl = LM_FLOW_CONTROL_NONE;
- if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) {
- LM_FLOW_CONTROL FlowCap; /* Flow control capability. */
-
- FlowCap = LM_FLOW_CONTROL_NONE;
-
- if (pDevice->DuplexMode == LM_DUPLEX_MODE_FULL) {
- if (pDevice->DisableAutoNeg == FALSE ||
- pDevice->RequestedMediaType ==
- LM_REQUESTED_MEDIA_TYPE_AUTO
- || pDevice->RequestedMediaType ==
- LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) {
- LM_UINT32 ExpectedPhyAd;
- LM_UINT32 LocalPhyAd;
- LM_UINT32 RemotePhyAd;
-
- LM_ReadPhy (pDevice, PHY_AN_AD_REG,
- &LocalPhyAd);
- pDevice->advertising = LocalPhyAd;
- LocalPhyAd &=
- (PHY_AN_AD_ASYM_PAUSE |
- PHY_AN_AD_PAUSE_CAPABLE);
-
- ExpectedPhyAd =
- GetPhyAdFlowCntrlSettings (pDevice);
-
- if (LocalPhyAd != ExpectedPhyAd) {
- CurrentLinkStatus = LM_STATUS_LINK_DOWN;
- } else {
- LM_ReadPhy (pDevice,
- PHY_LINK_PARTNER_ABILITY_REG,
- &RemotePhyAd);
-
- LM_SetFlowControl (pDevice, LocalPhyAd,
- RemotePhyAd);
- }
- } else {
- pDevice->FlowControlCap &=
- ~LM_FLOW_CONTROL_AUTO_PAUSE;
- LM_SetFlowControl (pDevice, 0, 0);
- }
- }
- }
-
- if (CurrentLinkStatus == LM_STATUS_LINK_DOWN) {
- LM_ForceAutoNeg (pDevice, pDevice->RequestedMediaType);
-
- /* If we force line speed, we make get link right away. */
- LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
- LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
- if (Value32 & PHY_STATUS_LINK_PASS) {
- CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
- }
- }
-
- /* GMII interface. */
- pDevice->MacMode &= ~MAC_MODE_PORT_MODE_MASK;
- if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) {
- if (pDevice->LineSpeed == LM_LINE_SPEED_100MBPS ||
- pDevice->LineSpeed == LM_LINE_SPEED_10MBPS) {
- pDevice->MacMode |= MAC_MODE_PORT_MODE_MII;
- } else {
- pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
- }
- } else {
- pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
- }
-
- /* Set the MAC to operate in the appropriate duplex mode. */
- pDevice->MacMode &= ~MAC_MODE_HALF_DUPLEX;
- if (pDevice->DuplexMode == LM_DUPLEX_MODE_HALF) {
- pDevice->MacMode |= MAC_MODE_HALF_DUPLEX;
- }
-
- /* Set the link polarity bit. */
- pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY;
- if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
- if ((pDevice->LedMode == LED_MODE_LINK10) ||
- (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE &&
- pDevice->LineSpeed == LM_LINE_SPEED_10MBPS)) {
- pDevice->MacMode |= MAC_MODE_LINK_POLARITY;
- }
- } else {
- if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) {
- pDevice->MacMode |= MAC_MODE_LINK_POLARITY;
- }
-
- /* Set LED mode. */
- if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
- Value32 = LED_CTRL_PHY_MODE_1;
- } else {
- if (pDevice->LedMode == LED_MODE_OUTPUT) {
- Value32 = LED_CTRL_PHY_MODE_2;
- } else {
- Value32 = LED_CTRL_PHY_MODE_1;
- }
- }
- REG_WR (pDevice, MacCtrl.LedCtrl, Value32);
- }
-
- REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode);
-
- /* Enable auto polling. */
- if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) {
- pDevice->MiMode |= MI_MODE_AUTO_POLLING_ENABLE;
- REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode);
- }
-
- /* Enable phy link change attention. */
- if (pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) {
- REG_WR (pDevice, MacCtrl.MacEvent,
- MAC_EVENT_ENABLE_MI_INTERRUPT);
- } else {
- REG_WR (pDevice, MacCtrl.MacEvent,
- MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN);
- }
- if ((T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) &&
- (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) &&
- (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) &&
- (((pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) &&
- (pDevice->PciState & T3_PCI_STATE_BUS_SPEED_HIGH)) ||
- !(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))) {
- MM_Wait (120);
- REG_WR (pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
- MAC_STATUS_CFG_CHANGED);
- MEM_WR_OFFSET (pDevice, T3_FIRMWARE_MAILBOX,
- T3_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE);
- }
-
- /* Indicate link status. */
- if (pDevice->LinkStatus != CurrentLinkStatus) {
- pDevice->LinkStatus = CurrentLinkStatus;
- MM_IndicateStatus (pDevice, CurrentLinkStatus);
- }
-
- return LM_STATUS_SUCCESS;
-} /* LM_SetupCopperPhy */
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-LM_STATUS LM_SetupPhy (PLM_DEVICE_BLOCK pDevice)
-{
- LM_STATUS LmStatus;
- LM_UINT32 Value32;
-
-#if INCLUDE_TBI_SUPPORT
- if (pDevice->EnableTbi) {
- LmStatus = LM_SetupFiberPhy (pDevice);
- } else
-#endif /* INCLUDE_TBI_SUPPORT */
- {
- LmStatus = LM_SetupCopperPhy (pDevice);
- }
- if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) {
- if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) {
- Value32 = REG_RD (pDevice, PciCfg.PciState);
- REG_WR (pDevice, PciCfg.PciState,
- Value32 | T3_PCI_STATE_RETRY_SAME_DMA);
- }
- }
- if ((pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) &&
- (pDevice->DuplexMode == LM_DUPLEX_MODE_HALF)) {
- REG_WR (pDevice, MacCtrl.TxLengths, 0x26ff);
- } else {
- REG_WR (pDevice, MacCtrl.TxLengths, 0x2620);
- }
-
- return LmStatus;
-}
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-LM_VOID
-LM_ReadPhy (PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg, PLM_UINT32 pData32)
-{
- LM_UINT32 Value32;
- LM_UINT32 j;
-
- if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) {
- REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode &
- ~MI_MODE_AUTO_POLLING_ENABLE);
- MM_Wait (40);
- }
-
- Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) |
- ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) <<
- MI_COM_FIRST_PHY_REG_ADDR_BIT) | MI_COM_CMD_READ | MI_COM_START;
-
- REG_WR (pDevice, MacCtrl.MiCom, Value32);
-
- for (j = 0; j < 20; j++) {
- MM_Wait (25);
-
- Value32 = REG_RD (pDevice, MacCtrl.MiCom);
-
- if (!(Value32 & MI_COM_BUSY)) {
- MM_Wait (5);
- Value32 = REG_RD (pDevice, MacCtrl.MiCom);
- Value32 &= MI_COM_PHY_DATA_MASK;
- break;
- }
- }
-
- if (Value32 & MI_COM_BUSY) {
- Value32 = 0;
- }
-
- *pData32 = Value32;
-
- if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) {
- REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode);
- MM_Wait (40);
- }
-} /* LM_ReadPhy */
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-LM_VOID
-LM_WritePhy (PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg, LM_UINT32 Data32)
-{
- LM_UINT32 Value32;
- LM_UINT32 j;
-
- if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) {
- REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode &
- ~MI_MODE_AUTO_POLLING_ENABLE);
- MM_Wait (40);
- }
-
- Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) |
- ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) <<
- MI_COM_FIRST_PHY_REG_ADDR_BIT) | (Data32 & MI_COM_PHY_DATA_MASK) |
- MI_COM_CMD_WRITE | MI_COM_START;
-
- REG_WR (pDevice, MacCtrl.MiCom, Value32);
-
- for (j = 0; j < 20; j++) {
- MM_Wait (25);
-
- Value32 = REG_RD (pDevice, MacCtrl.MiCom);
-
- if (!(Value32 & MI_COM_BUSY)) {
- MM_Wait (5);
- break;
- }
- }
-
- if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) {
- REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode);
- MM_Wait (40);
- }
-} /* LM_WritePhy */
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-LM_STATUS LM_SetPowerState (PLM_DEVICE_BLOCK pDevice, LM_POWER_STATE PowerLevel)
-{
- LM_UINT32 PmeSupport;
- LM_UINT32 Value32;
- LM_UINT32 PmCtrl;
-
- /* make sureindirect accesses are enabled */
- MM_WriteConfig32 (pDevice, T3_PCI_MISC_HOST_CTRL_REG,
- pDevice->MiscHostCtrl);
-
- /* Clear the PME_ASSERT bit and the power state bits. Also enable */
- /* the PME bit. */
- MM_ReadConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, &PmCtrl);
-
- PmCtrl |= T3_PM_PME_ASSERTED;
- PmCtrl &= ~T3_PM_POWER_STATE_MASK;
-
- /* Set the appropriate power state. */
- if (PowerLevel == LM_POWER_STATE_D0) {
-
- /* Bring the card out of low power mode. */
- PmCtrl |= T3_PM_POWER_STATE_D0;
- MM_WriteConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl);
-
- REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl);
- MM_Wait (40);
-#if 0 /* Bugfix by jmb...can't call WritePhy here because pDevice not fully initialized */
- LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x02);
-#endif
-
- return LM_STATUS_SUCCESS;
- } else if (PowerLevel == LM_POWER_STATE_D1) {
- PmCtrl |= T3_PM_POWER_STATE_D1;
- } else if (PowerLevel == LM_POWER_STATE_D2) {
- PmCtrl |= T3_PM_POWER_STATE_D2;
- } else if (PowerLevel == LM_POWER_STATE_D3) {
- PmCtrl |= T3_PM_POWER_STATE_D3;
- } else {
- return LM_STATUS_FAILURE;
- }
- PmCtrl |= T3_PM_PME_ENABLE;
-
- /* Mask out all interrupts so LM_SetupPhy won't be called while we are */
- /* setting new line speed. */
- Value32 = REG_RD (pDevice, PciCfg.MiscHostCtrl);
- REG_WR (pDevice, PciCfg.MiscHostCtrl,
- Value32 | MISC_HOST_CTRL_MASK_PCI_INT);
-
- if (!pDevice->RestoreOnWakeUp) {
- pDevice->RestoreOnWakeUp = TRUE;
- pDevice->WakeUpDisableAutoNeg = pDevice->DisableAutoNeg;
- pDevice->WakeUpRequestedMediaType = pDevice->RequestedMediaType;
- }
-
- /* Force auto-negotiation to 10 line speed. */
- pDevice->DisableAutoNeg = FALSE;
- pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS;
- LM_SetupPhy (pDevice);
-
- /* Put the driver in the initial state, and go through the power down */
- /* sequence. */
- LM_Halt (pDevice);
-
- MM_ReadConfig32 (pDevice, T3_PCI_PM_CAP_REG, &PmeSupport);
-
- if (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE) {
-
- /* Enable WOL. */
- LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x5a);
- MM_Wait (40);
-
- /* Set LED mode. */
- if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
- Value32 = LED_CTRL_PHY_MODE_1;
- } else {
- if (pDevice->LedMode == LED_MODE_OUTPUT) {
- Value32 = LED_CTRL_PHY_MODE_2;
- } else {
- Value32 = LED_CTRL_PHY_MODE_1;
- }
- }
-
- Value32 = MAC_MODE_PORT_MODE_MII;
- if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
- if (pDevice->LedMode == LED_MODE_LINK10 ||
- pDevice->WolSpeed == WOL_SPEED_10MB) {
- Value32 |= MAC_MODE_LINK_POLARITY;
- }
- } else {
- Value32 |= MAC_MODE_LINK_POLARITY;
- }
- REG_WR (pDevice, MacCtrl.Mode, Value32);
- MM_Wait (40);
- MM_Wait (40);
- MM_Wait (40);
-
- /* Always enable magic packet wake-up if we have vaux. */
- if ((PmeSupport & T3_PCI_PM_CAP_PME_D3COLD) &&
- (pDevice->WakeUpModeCap & LM_WAKE_UP_MODE_MAGIC_PACKET)) {
- Value32 |= MAC_MODE_DETECT_MAGIC_PACKET_ENABLE;
- }
-
- REG_WR (pDevice, MacCtrl.Mode, Value32);
-
- /* Enable the receiver. */
- REG_WR (pDevice, MacCtrl.RxMode, RX_MODE_ENABLE);
- }
-
- /* Disable tx/rx clocks, and seletect an alternate clock. */
- if (pDevice->WolSpeed == WOL_SPEED_100MB) {
- if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
- Value32 =
- T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
- T3_PCI_SELECT_ALTERNATE_CLOCK;
- } else {
- Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK;
- }
- REG_WR (pDevice, PciCfg.ClockCtrl, Value32);
-
- MM_Wait (40);
-
- if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
- Value32 =
- T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
- T3_PCI_SELECT_ALTERNATE_CLOCK |
- T3_PCI_44MHZ_CORE_CLOCK;
- } else {
- Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK |
- T3_PCI_44MHZ_CORE_CLOCK;
- }
-
- REG_WR (pDevice, PciCfg.ClockCtrl, Value32);
-
- MM_Wait (40);
-
- if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
- Value32 =
- T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
- T3_PCI_44MHZ_CORE_CLOCK;
- } else {
- Value32 = T3_PCI_44MHZ_CORE_CLOCK;
- }
-
- REG_WR (pDevice, PciCfg.ClockCtrl, Value32);
- } else {
- if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
- Value32 =
- T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
- T3_PCI_SELECT_ALTERNATE_CLOCK |
- T3_PCI_POWER_DOWN_PCI_PLL133;
- } else {
- Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK |
- T3_PCI_POWER_DOWN_PCI_PLL133;
- }
-
- REG_WR (pDevice, PciCfg.ClockCtrl, Value32);
- }
-
- MM_Wait (40);
-
- if (!pDevice->EepromWp
- && (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE)) {
- /* Switch adapter to auxilliary power. */
- if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
- /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */
- REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
- GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
- GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
- GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
- GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
- GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
- MM_Wait (40);
- } else {
- /* GPIO0 = 0, GPIO1 = 1, GPIO2 = 1. */
- REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
- GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
- GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
- GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
- GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
- GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
- MM_Wait (40);
-
- /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 1. */
- REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
- GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
- GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
- GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
- GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
- GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
- GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
- MM_Wait (40);
-
- /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */
- REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
- GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
- GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
- GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
- GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
- GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
- MM_Wait (40);
- }
- }
-
- /* Set the phy to low power mode. */
- /* Put the the hardware in low power mode. */
- MM_WriteConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl);
-
- return LM_STATUS_SUCCESS;
-} /* LM_SetPowerState */
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-static LM_UINT32 GetPhyAdFlowCntrlSettings (PLM_DEVICE_BLOCK pDevice)
-{
- LM_UINT32 Value32;
-
- Value32 = 0;
-
- /* Auto negotiation flow control only when autonegotiation is enabled. */
- if (pDevice->DisableAutoNeg == FALSE ||
- pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO ||
- pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) {
- /* Please refer to Table 28B-3 of the 802.3ab-1999 spec. */
- if ((pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE) ||
- ((pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE)
- && (pDevice->
- FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE))) {
- Value32 |= PHY_AN_AD_PAUSE_CAPABLE;
- } else if (pDevice->
- FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE) {
- Value32 |= PHY_AN_AD_ASYM_PAUSE;
- } else if (pDevice->
- FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE) {
- Value32 |=
- PHY_AN_AD_PAUSE_CAPABLE | PHY_AN_AD_ASYM_PAUSE;
- }
- }
-
- return Value32;
-}
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/* LM_STATUS_FAILURE */
-/* LM_STATUS_SUCCESS */
-/* */
-/******************************************************************************/
-static LM_STATUS
-LM_ForceAutoNegBcm540xPhy (PLM_DEVICE_BLOCK pDevice,
- LM_REQUESTED_MEDIA_TYPE RequestedMediaType)
-{
- LM_MEDIA_TYPE MediaType;
- LM_LINE_SPEED LineSpeed;
- LM_DUPLEX_MODE DuplexMode;
- LM_UINT32 NewPhyCtrl;
- LM_UINT32 Value32;
- LM_UINT32 Cnt;
-
- /* Get the interface type, line speed, and duplex mode. */
- LM_TranslateRequestedMediaType (RequestedMediaType, &MediaType,
- &LineSpeed, &DuplexMode);
-
- if (pDevice->RestoreOnWakeUp) {
- LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG, 0);
- pDevice->advertising1000 = 0;
- Value32 = PHY_AN_AD_10BASET_FULL | PHY_AN_AD_10BASET_HALF;
- if (pDevice->WolSpeed == WOL_SPEED_100MB) {
- Value32 |=
- PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF;
- }
- Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
- Value32 |= GetPhyAdFlowCntrlSettings (pDevice);
- LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32);
- pDevice->advertising = Value32;
- }
- /* Setup the auto-negotiation advertisement register. */
- else if (LineSpeed == LM_LINE_SPEED_UNKNOWN) {
- /* Setup the 10/100 Mbps auto-negotiation advertisement register. */
- Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD |
- PHY_AN_AD_10BASET_HALF | PHY_AN_AD_10BASET_FULL |
- PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF;
- Value32 |= GetPhyAdFlowCntrlSettings (pDevice);
-
- LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32);
- pDevice->advertising = Value32;
-
- /* Advertise 1000Mbps */
- Value32 =
- BCM540X_AN_AD_1000BASET_HALF | BCM540X_AN_AD_1000BASET_FULL;
-
-#if INCLUDE_5701_AX_FIX
- /* Bug: workaround for CRC error in gigabit mode when we are in */
- /* slave mode. This will force the PHY to operate in */
- /* master mode. */
- if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
- pDevice->ChipRevId == T3_CHIP_ID_5701_B0) {
- Value32 |= BCM540X_CONFIG_AS_MASTER |
- BCM540X_ENABLE_CONFIG_AS_MASTER;
- }
-#endif
-
- LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG, Value32);
- pDevice->advertising1000 = Value32;
- } else {
- if (LineSpeed == LM_LINE_SPEED_1000MBPS) {
- Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
- Value32 |= GetPhyAdFlowCntrlSettings (pDevice);
-
- LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32);
- pDevice->advertising = Value32;
-
- if (DuplexMode != LM_DUPLEX_MODE_FULL) {
- Value32 = BCM540X_AN_AD_1000BASET_HALF;
- } else {
- Value32 = BCM540X_AN_AD_1000BASET_FULL;
- }
-
- LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG,
- Value32);
- pDevice->advertising1000 = Value32;
- } else if (LineSpeed == LM_LINE_SPEED_100MBPS) {
- LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG, 0);
- pDevice->advertising1000 = 0;
-
- if (DuplexMode != LM_DUPLEX_MODE_FULL) {
- Value32 = PHY_AN_AD_100BASETX_HALF;
- } else {
- Value32 = PHY_AN_AD_100BASETX_FULL;
- }
-
- Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
- Value32 |= GetPhyAdFlowCntrlSettings (pDevice);
-
- LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32);
- pDevice->advertising = Value32;
- } else if (LineSpeed == LM_LINE_SPEED_10MBPS) {
- LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG, 0);
- pDevice->advertising1000 = 0;
-
- if (DuplexMode != LM_DUPLEX_MODE_FULL) {
- Value32 = PHY_AN_AD_10BASET_HALF;
- } else {
- Value32 = PHY_AN_AD_10BASET_FULL;
- }
-
- Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
- Value32 |= GetPhyAdFlowCntrlSettings (pDevice);
-
- LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32);
- pDevice->advertising = Value32;
- }
- }
-
- /* Force line speed if auto-negotiation is disabled. */
- if (pDevice->DisableAutoNeg && LineSpeed != LM_LINE_SPEED_UNKNOWN) {
- /* This code path is executed only when there is link. */
- pDevice->MediaType = MediaType;
- pDevice->LineSpeed = LineSpeed;
- pDevice->DuplexMode = DuplexMode;
-
- /* Force line seepd. */
- NewPhyCtrl = 0;
- switch (LineSpeed) {
- case LM_LINE_SPEED_10MBPS:
- NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_10MBPS;
- break;
- case LM_LINE_SPEED_100MBPS:
- NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_100MBPS;
- break;
- case LM_LINE_SPEED_1000MBPS:
- NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS;
- break;
- default:
- NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS;
- break;
- }
-
- if (DuplexMode == LM_DUPLEX_MODE_FULL) {
- NewPhyCtrl |= PHY_CTRL_FULL_DUPLEX_MODE;
- }
-
- /* Don't do anything if the PHY_CTRL is already what we wanted. */
- LM_ReadPhy (pDevice, PHY_CTRL_REG, &Value32);
- if (Value32 != NewPhyCtrl) {
- /* Temporary bring the link down before forcing line speed. */
- LM_WritePhy (pDevice, PHY_CTRL_REG,
- PHY_CTRL_LOOPBACK_MODE);
-
- /* Wait for link to go down. */
- for (Cnt = 0; Cnt < 15000; Cnt++) {
- MM_Wait (10);
-
- LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
- LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
-
- if (!(Value32 & PHY_STATUS_LINK_PASS)) {
- MM_Wait (40);
- break;
- }
- }
-
- LM_WritePhy (pDevice, PHY_CTRL_REG, NewPhyCtrl);
- MM_Wait (40);
- }
- } else {
- LM_WritePhy (pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE |
- PHY_CTRL_RESTART_AUTO_NEG);
- }
-
- return LM_STATUS_SUCCESS;
-} /* LM_ForceAutoNegBcm540xPhy */
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-static LM_STATUS
-LM_ForceAutoNeg (PLM_DEVICE_BLOCK pDevice,
- LM_REQUESTED_MEDIA_TYPE RequestedMediaType)
-{
- LM_STATUS LmStatus;
-
- /* Initialize the phy chip. */
- switch (pDevice->PhyId & PHY_ID_MASK) {
- case PHY_BCM5400_PHY_ID:
- case PHY_BCM5401_PHY_ID:
- case PHY_BCM5411_PHY_ID:
- case PHY_BCM5701_PHY_ID:
- case PHY_BCM5703_PHY_ID:
- case PHY_BCM5704_PHY_ID:
- LmStatus =
- LM_ForceAutoNegBcm540xPhy (pDevice, RequestedMediaType);
- break;
-
- default:
- LmStatus = LM_STATUS_FAILURE;
- break;
- }
-
- return LmStatus;
-} /* LM_ForceAutoNeg */
-
-/******************************************************************************/
-/* Description: */
-/* */
-/* Return: */
-/******************************************************************************/
-LM_STATUS LM_LoadFirmware (PLM_DEVICE_BLOCK pDevice,
- PT3_FWIMG_INFO pFwImg,
- LM_UINT32 LoadCpu, LM_UINT32 StartCpu)
-{
- LM_UINT32 i;
- LM_UINT32 address;
-
- if (LoadCpu & T3_RX_CPU_ID) {
- if (LM_HaltCpu (pDevice, T3_RX_CPU_ID) != LM_STATUS_SUCCESS) {
- return LM_STATUS_FAILURE;
- }
-
- /* First of all clear scrach pad memory */
- for (i = 0; i < T3_RX_CPU_SPAD_SIZE; i += 4) {
- LM_RegWrInd (pDevice, T3_RX_CPU_SPAD_ADDR + i, 0);
- }
-
- /* Copy code first */
- address = T3_RX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff);
- for (i = 0; i <= pFwImg->Text.Length; i += 4) {
- LM_RegWrInd (pDevice, address + i,
- ((LM_UINT32 *) pFwImg->Text.Buffer)[i /
- 4]);
- }
-
- address =
- T3_RX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff);
- for (i = 0; i <= pFwImg->ROnlyData.Length; i += 4) {
- LM_RegWrInd (pDevice, address + i,
- ((LM_UINT32 *) pFwImg->ROnlyData.
- Buffer)[i / 4]);
- }
-
- address = T3_RX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff);
- for (i = 0; i <= pFwImg->Data.Length; i += 4) {
- LM_RegWrInd (pDevice, address + i,
- ((LM_UINT32 *) pFwImg->Data.Buffer)[i /
- 4]);
- }
- }
-
- if (LoadCpu & T3_TX_CPU_ID) {
- if (LM_HaltCpu (pDevice, T3_TX_CPU_ID) != LM_STATUS_SUCCESS) {
- return LM_STATUS_FAILURE;
- }
-
- /* First of all clear scrach pad memory */
- for (i = 0; i < T3_TX_CPU_SPAD_SIZE; i += 4) {
- LM_RegWrInd (pDevice, T3_TX_CPU_SPAD_ADDR + i, 0);
- }
-
- /* Copy code first */
- address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff);
- for (i = 0; i <= pFwImg->Text.Length; i += 4) {
- LM_RegWrInd (pDevice, address + i,
- ((LM_UINT32 *) pFwImg->Text.Buffer)[i /
- 4]);
- }
-
- address =
- T3_TX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff);
- for (i = 0; i <= pFwImg->ROnlyData.Length; i += 4) {
- LM_RegWrInd (pDevice, address + i,
- ((LM_UINT32 *) pFwImg->ROnlyData.
- Buffer)[i / 4]);
- }
-
- address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff);
- for (i = 0; i <= pFwImg->Data.Length; i += 4) {
- LM_RegWrInd (pDevice, address + i,
- ((LM_UINT32 *) pFwImg->Data.Buffer)[i /
- 4]);
- }
- }
-
- if (StartCpu & T3_RX_CPU_ID) {
- /* Start Rx CPU */
- REG_WR (pDevice, rxCpu.reg.state, 0xffffffff);
- REG_WR (pDevice, rxCpu.reg.PC, pFwImg->StartAddress);
- for (i = 0; i < 5; i++) {
- if (pFwImg->StartAddress ==
- REG_RD (pDevice, rxCpu.reg.PC))
- break;
-
- REG_WR (pDevice, rxCpu.reg.state, 0xffffffff);
- REG_WR (pDevice, rxCpu.reg.mode, CPU_MODE_HALT);
- REG_WR (pDevice, rxCpu.reg.PC, pFwImg->StartAddress);
- MM_Wait (1000);
- }
-
- REG_WR (pDevice, rxCpu.reg.state, 0xffffffff);
- REG_WR (pDevice, rxCpu.reg.mode, 0);
- }
-
- if (StartCpu & T3_TX_CPU_ID) {
- /* Start Tx CPU */
- REG_WR (pDevice, txCpu.reg.state, 0xffffffff);
- REG_WR (pDevice, txCpu.reg.PC, pFwImg->StartAddress);
- for (i = 0; i < 5; i++) {
- if (pFwImg->StartAddress ==
- REG_RD (pDevice, txCpu.reg.PC))
- break;
-
- REG_WR (pDevice, txCpu.reg.state, 0xffffffff);
- REG_WR (pDevice, txCpu.reg.mode, CPU_MODE_HALT);
- REG_WR (pDevice, txCpu.reg.PC, pFwImg->StartAddress);
- MM_Wait (1000);
- }
-
- REG_WR (pDevice, txCpu.reg.state, 0xffffffff);
- REG_WR (pDevice, txCpu.reg.mode, 0);
- }
-
- return LM_STATUS_SUCCESS;
-}
-
-STATIC LM_STATUS LM_HaltCpu (PLM_DEVICE_BLOCK pDevice, LM_UINT32 cpu_number)
-{
- LM_UINT32 i;
-
- if (cpu_number == T3_RX_CPU_ID) {
- for (i = 0; i < 10000; i++) {
- REG_WR (pDevice, rxCpu.reg.state, 0xffffffff);
- REG_WR (pDevice, rxCpu.reg.mode, CPU_MODE_HALT);
-
- if (REG_RD (pDevice, rxCpu.reg.mode) & CPU_MODE_HALT)
- break;
- }
-
- REG_WR (pDevice, rxCpu.reg.state, 0xffffffff);
- REG_WR (pDevice, rxCpu.reg.mode, CPU_MODE_HALT);
- MM_Wait (10);
- } else {
- for (i = 0; i < 10000; i++) {
- REG_WR (pDevice, txCpu.reg.state, 0xffffffff);
- REG_WR (pDevice, txCpu.reg.mode, CPU_MODE_HALT);
-
- if (REG_RD (pDevice, txCpu.reg.mode) & CPU_MODE_HALT)
- break;
- }
- }
-
- return ((i == 10000) ? LM_STATUS_FAILURE : LM_STATUS_SUCCESS);
-}
-
-int LM_BlinkLED (PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDurationSec)
-{
- LM_UINT32 Oldcfg;
- int j;
- int ret = 0;
-
- if (BlinkDurationSec == 0) {
- return 0;
- }
- if (BlinkDurationSec > 120) {
- BlinkDurationSec = 120;
- }
-
- Oldcfg = REG_RD (pDevice, MacCtrl.LedCtrl);
- for (j = 0; j < BlinkDurationSec * 2; j++) {
- if (j % 2) {
- /* Turn on the LEDs. */
- REG_WR (pDevice, MacCtrl.LedCtrl,
- LED_CTRL_OVERRIDE_LINK_LED |
- LED_CTRL_1000MBPS_LED_ON |
- LED_CTRL_100MBPS_LED_ON |
- LED_CTRL_10MBPS_LED_ON |
- LED_CTRL_OVERRIDE_TRAFFIC_LED |
- LED_CTRL_BLINK_TRAFFIC_LED |
- LED_CTRL_TRAFFIC_LED);
- } else {
- /* Turn off the LEDs. */
- REG_WR (pDevice, MacCtrl.LedCtrl,
- LED_CTRL_OVERRIDE_LINK_LED |
- LED_CTRL_OVERRIDE_TRAFFIC_LED);
- }
-
-#ifndef EMBEDDED
- current->state = TASK_INTERRUPTIBLE;
- if (schedule_timeout (HZ / 2) != 0) {
- ret = -EINTR;
- break;
- }
-#else
- udelay (100000); /* 1s sleep */
-#endif
- }
- REG_WR (pDevice, MacCtrl.LedCtrl, Oldcfg);
- return ret;
-}
-
-int t3_do_dma (PLM_DEVICE_BLOCK pDevice,
- LM_PHYSICAL_ADDRESS host_addr_phy, int length, int dma_read)
-{
- T3_DMA_DESC dma_desc;
- int i;
- LM_UINT32 dma_desc_addr;
- LM_UINT32 value32;
-
- REG_WR (pDevice, BufMgr.Mode, 0);
- REG_WR (pDevice, Ftq.Reset, 0);
-
- dma_desc.host_addr.High = host_addr_phy.High;
- dma_desc.host_addr.Low = host_addr_phy.Low;
- dma_desc.nic_mbuf = 0x2100;
- dma_desc.len = length;
- dma_desc.flags = 0x00000004; /* Generate Rx-CPU event */
-
- if (dma_read) {
- dma_desc.cqid_sqid = (T3_QID_RX_BD_COMP << 8) |
- T3_QID_DMA_HIGH_PRI_READ;
- REG_WR (pDevice, DmaRead.Mode, DMA_READ_MODE_ENABLE);
- } else {
- dma_desc.cqid_sqid = (T3_QID_RX_DATA_COMP << 8) |
- T3_QID_DMA_HIGH_PRI_WRITE;
- REG_WR (pDevice, DmaWrite.Mode, DMA_WRITE_MODE_ENABLE);
- }
-
- dma_desc_addr = T3_NIC_DMA_DESC_POOL_ADDR;
-
- /* Writing this DMA descriptor to DMA memory */
- for (i = 0; i < sizeof (T3_DMA_DESC); i += 4) {
- value32 = *((PLM_UINT32) (((PLM_UINT8) & dma_desc) + i));
- MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG,
- dma_desc_addr + i);
- MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_DATA_REG,
- cpu_to_le32 (value32));
- }
- MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG, 0);
-
- if (dma_read)
- REG_WR (pDevice, Ftq.DmaHighReadFtqFifoEnqueueDequeue,
- dma_desc_addr);
- else
- REG_WR (pDevice, Ftq.DmaHighWriteFtqFifoEnqueueDequeue,
- dma_desc_addr);
-
- for (i = 0; i < 40; i++) {
- if (dma_read)
- value32 =
- REG_RD (pDevice,
- Ftq.RcvBdCompFtqFifoEnqueueDequeue);
- else
- value32 =
- REG_RD (pDevice,
- Ftq.RcvDataCompFtqFifoEnqueueDequeue);
-
- if ((value32 & 0xffff) == dma_desc_addr)
- break;
-
- MM_Wait (10);
- }
-
- return LM_STATUS_SUCCESS;
-}
-
-STATIC LM_STATUS
-LM_DmaTest (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt,
- LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize)
-{
- int j;
- LM_UINT32 *ptr;
- int dma_success = 0;
-
- if (T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
- T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5701) {
- return LM_STATUS_SUCCESS;
- }
- while (!dma_success) {
- /* Fill data with incremental patterns */
- ptr = (LM_UINT32 *) pBufferVirt;
- for (j = 0; j < BufferSize / 4; j++)
- *ptr++ = j;
-
- if (t3_do_dma (pDevice, BufferPhy, BufferSize, 1) ==
- LM_STATUS_FAILURE) {
- return LM_STATUS_FAILURE;
- }
-
- MM_Wait (40);
- ptr = (LM_UINT32 *) pBufferVirt;
- /* Fill data with zero */
- for (j = 0; j < BufferSize / 4; j++)
- *ptr++ = 0;
-
- if (t3_do_dma (pDevice, BufferPhy, BufferSize, 0) ==
- LM_STATUS_FAILURE) {
- return LM_STATUS_FAILURE;
- }
-
- MM_Wait (40);
- /* Check for data */
- ptr = (LM_UINT32 *) pBufferVirt;
- for (j = 0; j < BufferSize / 4; j++) {
- if (*ptr++ != j) {
- if ((pDevice->
- DmaReadWriteCtrl &
- DMA_CTRL_WRITE_BOUNDARY_MASK)
- == DMA_CTRL_WRITE_BOUNDARY_DISABLE) {
- pDevice->DmaReadWriteCtrl =
- (pDevice->
- DmaReadWriteCtrl &
- ~DMA_CTRL_WRITE_BOUNDARY_MASK) |
- DMA_CTRL_WRITE_BOUNDARY_16;
- REG_WR (pDevice,
- PciCfg.DmaReadWriteCtrl,
- pDevice->DmaReadWriteCtrl);
- break;
- } else {
- return LM_STATUS_FAILURE;
- }
- }
- }
- if (j == (BufferSize / 4))
- dma_success = 1;
- }
- return LM_STATUS_SUCCESS;
-}
+++ /dev/null
-
-/******************************************************************************/
-/* */
-/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom */
-/* Corporation. */
-/* All rights reserved. */
-/* */
-/* This program is free software; you can redistribute it and/or modify */
-/* it under the terms of the GNU General Public License as published by */
-/* the Free Software Foundation, located in the file LICENSE. */
-/* */
-/* History: */
-/* */
-/******************************************************************************/
-
-#ifndef TIGON3_H
-#define TIGON3_H
-
-#include "bcm570x_lm.h"
-#if INCLUDE_TBI_SUPPORT
-#include "bcm570x_autoneg.h"
-#endif
-
-/* io defines */
-#if !defined(BIG_ENDIAN_HOST)
-#define readl(addr) \
- (LONGSWAP((*(volatile unsigned int *)(addr))))
-#define writel(b,addr) \
- ((*(volatile unsigned int *)(addr)) = (LONGSWAP(b)))
-#else
-#if 0 /* !defined(PPC603) */
-#define readl(addr) (*(volatile unsigned int*)(0xa0000000 + (unsigned long)(addr)))
-#define writel(b,addr) ((*(volatile unsigned int *) ((unsigned long)(addr) + 0xa0000000)) = (b))
-#else
-#if 1
-#define readl(addr) (*(volatile unsigned int*)(addr))
-#define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b))
-#else
-extern int sprintf (char *buf, const char *f, ...);
-static __inline unsigned int readl (void *addr)
-{
- char buf[128];
- unsigned int tmp = (*(volatile unsigned int *)(addr));
- sprintf (buf, "%s:%s: read 0x%x from 0x%x\n", __FILE__, __LINE__, tmp,
- addr, 0, 0);
- sysSerialPrintString (buf);
- return tmp;
-}
-static __inline void writel (unsigned int b, unsigned int addr)
-{
- char buf[128];
- ((*(volatile unsigned int *)(addr)) = (b));
- sprintf (buf, "%s:%s: write 0x%x to 0x%x\n", __FILE__, __LINE__, b,
- addr, 0, 0);
- sysSerialPrintString (buf);
-}
-#endif
-#endif /* PPC603 */
-#endif
-
-/******************************************************************************/
-/* Constants. */
-/******************************************************************************/
-
-/* Maxim number of packet descriptors used for sending packets. */
-#define MAX_TX_PACKET_DESC_COUNT 600
-#define DEFAULT_TX_PACKET_DESC_COUNT 2
-
-/* Maximum number of packet descriptors used for receiving packets. */
-#if T3_JUMBO_RCB_ENTRY_COUNT
-#define MAX_RX_PACKET_DESC_COUNT \
- (T3_STD_RCV_RCB_ENTRY_COUNT + T3_JUMBO_RCV_RCB_ENTRY_COUNT)
-#else
-#define MAX_RX_PACKET_DESC_COUNT 800
-#endif
-#define DEFAULT_RX_PACKET_DESC_COUNT 2
-
-/* Threshhold for double copying small tx packets. 0 will disable double */
-/* copying of small Tx packets. */
-#define DEFAULT_TX_COPY_BUFFER_SIZE 0
-#define MIN_TX_COPY_BUFFER_SIZE 64
-#define MAX_TX_COPY_BUFFER_SIZE 512
-
-/* Cache line. */
-#define COMMON_CACHE_LINE_SIZE 0x20
-#define COMMON_CACHE_LINE_MASK (COMMON_CACHE_LINE_SIZE-1)
-
-/* Maximum number of fragment we can handle. */
-#ifndef MAX_FRAGMENT_COUNT
-#define MAX_FRAGMENT_COUNT 32
-#endif
-
-/* B0 bug. */
-#define BCM5700_BX_MIN_FRAG_SIZE 10
-#define BCM5700_BX_MIN_FRAG_BUF_SIZE 16 /* nice aligned size. */
-#define BCM5700_BX_MIN_FRAG_BUF_SIZE_MASK (BCM5700_BX_MIN_FRAG_BUF_SIZE-1)
-#define BCM5700_BX_TX_COPY_BUF_SIZE (BCM5700_BX_MIN_FRAG_BUF_SIZE * \
- MAX_FRAGMENT_COUNT)
-
-/* MAGIC number. */
-/* #define T3_MAGIC_NUM 'KevT' */
-#define T3_FIRMWARE_MAILBOX 0x0b50
-#define T3_MAGIC_NUM 0x4B657654
-#define T3_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE 0x4861764b
-
-#define T3_NIC_DATA_SIG_ADDR 0x0b54
-#define T3_NIC_DATA_SIG 0x4b657654
-
-#define T3_NIC_DATA_NIC_CFG_ADDR 0x0b58
-#define T3_NIC_CFG_LED_MODE_UNKNOWN BIT_NONE
-#define T3_NIC_CFG_LED_MODE_TRIPLE_SPEED BIT_2
-#define T3_NIC_CFG_LED_MODE_LINK_SPEED BIT_3
-#define T3_NIC_CFG_LED_MODE_OPEN_DRAIN BIT_2
-#define T3_NIC_CFG_LED_MODE_OUTPUT BIT_3
-#define T3_NIC_CFG_LED_MODE_MASK (BIT_2 | BIT_3)
-#define T3_NIC_CFG_PHY_TYPE_UNKNOWN BIT_NONE
-#define T3_NIC_CFG_PHY_TYPE_COPPER BIT_4
-#define T3_NIC_CFG_PHY_TYPE_FIBER BIT_5
-#define T3_NIC_CFG_PHY_TYPE_MASK (BIT_4 | BIT_5)
-#define T3_NIC_CFG_ENABLE_WOL BIT_6
-#define T3_NIC_CFG_ENABLE_ASF BIT_7
-#define T3_NIC_EEPROM_WP BIT_8
-
-#define T3_NIC_DATA_PHY_ID_ADDR 0x0b74
-#define T3_NIC_PHY_ID1_MASK 0xffff0000
-#define T3_NIC_PHY_ID2_MASK 0x0000ffff
-
-#define T3_CMD_MAILBOX 0x0b78
-#define T3_CMD_NICDRV_ALIVE 0x01
-#define T3_CMD_NICDRV_PAUSE_FW 0x02
-#define T3_CMD_NICDRV_IPV4ADDR_CHANGE 0x03
-#define T3_CMD_NICDRV_IPV6ADDR_CHANGE 0x04
-#define T3_CMD_5703A0_FIX_DMAFW_DMAR 0x05
-#define T3_CMD_5703A0_FIX_DMAFW_DMAW 0x06
-
-#define T3_CMD_LENGTH_MAILBOX 0x0b7c
-#define T3_CMD_DATA_MAILBOX 0x0b80
-
-#define T3_ASF_FW_STATUS_MAILBOX 0x0c00
-
-#define T3_DRV_STATE_MAILBOX 0x0c04
-#define T3_DRV_STATE_START 0x01
-#define T3_DRV_STATE_UNLOAD 0x02
-#define T3_DRV_STATE_WOL 0x03
-#define T3_DRV_STATE_SUSPEND 0x04
-
-#define T3_FW_RESET_TYPE_MAILBOX 0x0c08
-
-#define T3_MAC_ADDR_HIGH_MAILBOX 0x0c14
-#define T3_MAC_ADDR_LOW_MAILBOX 0x0c18
-
-/******************************************************************************/
-/* Hardware constants. */
-/******************************************************************************/
-
-/* Number of entries in the send ring: must be 512. */
-#define T3_SEND_RCB_ENTRY_COUNT 512
-#define T3_SEND_RCB_ENTRY_COUNT_MASK (T3_SEND_RCB_ENTRY_COUNT-1)
-
-/* Number of send RCBs. May be 1-16 but for now, only support one. */
-#define T3_MAX_SEND_RCB_COUNT 16
-
-/* Number of entries in the Standard Receive RCB. Must be 512 entries. */
-#define T3_STD_RCV_RCB_ENTRY_COUNT 512
-#define T3_STD_RCV_RCB_ENTRY_COUNT_MASK (T3_STD_RCV_RCB_ENTRY_COUNT-1)
-#define DEFAULT_STD_RCV_DESC_COUNT 200 /* Must be < 512. */
-#define MAX_STD_RCV_BUFFER_SIZE 0x600
-
-/* Number of entries in the Mini Receive RCB. This value can either be */
-/* 0, 1024. Currently Mini Receive RCB is disabled. */
-#ifndef T3_MINI_RCV_RCB_ENTRY_COUNT
-#define T3_MINI_RCV_RCB_ENTRY_COUNT 0
-#endif /* T3_MINI_RCV_RCB_ENTRY_COUNT */
-#define T3_MINI_RCV_RCB_ENTRY_COUNT_MASK (T3_MINI_RCV_RCB_ENTRY_COUNT-1)
-#define MAX_MINI_RCV_BUFFER_SIZE 512
-#define DEFAULT_MINI_RCV_BUFFER_SIZE 64
-#define DEFAULT_MINI_RCV_DESC_COUNT 100 /* Must be < 1024. */
-
-/* Number of entries in the Jumbo Receive RCB. This value must 256 or 0. */
-/* Currently, Jumbo Receive RCB is disabled. */
-#ifndef T3_JUMBO_RCV_RCB_ENTRY_COUNT
-#define T3_JUMBO_RCV_RCB_ENTRY_COUNT 0
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
-#define T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK (T3_JUMBO_RCV_RCB_ENTRY_COUNT-1)
-
-#define MAX_JUMBO_RCV_BUFFER_SIZE (10 * 1024) /* > 1514 */
-#define DEFAULT_JUMBO_RCV_BUFFER_SIZE (4 * 1024) /* > 1514 */
-#define DEFAULT_JUMBO_RCV_DESC_COUNT 128 /* Must be < 256. */
-
-#define MAX_JUMBO_TX_BUFFER_SIZE (8 * 1024) /* > 1514 */
-#define DEFAULT_JUMBO_TX_BUFFER_SIZE (4 * 1024) /* > 1514 */
-
-/* Number of receive return RCBs. Maybe 1-16 but for now, only support one. */
-#define T3_MAX_RCV_RETURN_RCB_COUNT 16
-
-/* Number of entries in a Receive Return ring. This value is either 1024 */
-/* or 2048. */
-#ifndef T3_RCV_RETURN_RCB_ENTRY_COUNT
-#define T3_RCV_RETURN_RCB_ENTRY_COUNT 1024
-#endif /* T3_RCV_RETURN_RCB_ENTRY_COUNT */
-#define T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK (T3_RCV_RETURN_RCB_ENTRY_COUNT-1)
-
-/* Default coalescing parameters. */
-#define DEFAULT_RX_COALESCING_TICKS 100
-#define MAX_RX_COALESCING_TICKS 500
-#define DEFAULT_TX_COALESCING_TICKS 400
-#define MAX_TX_COALESCING_TICKS 500
-#define DEFAULT_RX_MAX_COALESCED_FRAMES 10
-#define MAX_RX_MAX_COALESCED_FRAMES 100
-#define ADAPTIVE_LO_RX_MAX_COALESCED_FRAMES 5
-#define ADAPTIVE_HI_RX_MAX_COALESCED_FRAMES 42
-#define ADAPTIVE_LO_RX_COALESCING_TICKS 50
-#define ADAPTIVE_HI_RX_COALESCING_TICKS 300
-#define ADAPTIVE_LO_PKT_THRESH 30000
-#define ADAPTIVE_HI_PKT_THRESH 74000
-#define DEFAULT_TX_MAX_COALESCED_FRAMES 40
-#define ADAPTIVE_LO_TX_MAX_COALESCED_FRAMES 25
-#define ADAPTIVE_HI_TX_MAX_COALESCED_FRAMES 75
-#define MAX_TX_MAX_COALESCED_FRAMES 100
-
-#define DEFAULT_RX_COALESCING_TICKS_DURING_INT 25
-#define DEFAULT_TX_COALESCING_TICKS_DURING_INT 25
-#define DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT 5
-#define DEFAULT_TX_MAX_COALESCED_FRAMES_DURING_INT 5
-
-#define BAD_DEFAULT_VALUE 0xffffffff
-
-#define DEFAULT_STATS_COALESCING_TICKS 1000000
-#define MAX_STATS_COALESCING_TICKS 3600000000U
-
-/* Receive BD Replenish thresholds. */
-#define DEFAULT_RCV_STD_BD_REPLENISH_THRESHOLD 4
-#define DEFAULT_RCV_JUMBO_BD_REPLENISH_THRESHOLD 4
-
-#define SPLIT_MODE_DISABLE 0
-#define SPLIT_MODE_ENABLE 1
-
-#define SPLIT_MODE_5704_MAX_REQ 3
-
-/* Maximum physical fragment size. */
-#define MAX_FRAGMENT_SIZE (64 * 1024)
-
-/* Standard view. */
-#define T3_STD_VIEW_SIZE (64 * 1024)
-#define T3_FLAT_VIEW_SIZE (32 * 1024 * 1024)
-
-/* Buffer descriptor base address on the NIC's memory. */
-
-#define T3_NIC_SND_BUFFER_DESC_ADDR 0x4000
-#define T3_NIC_STD_RCV_BUFFER_DESC_ADDR 0x6000
-#define T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR 0x7000
-
-#define T3_NIC_STD_RCV_BUFFER_DESC_ADDR_EXT_MEM 0xc000
-#define T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR_EXT_MEM 0xd000
-#define T3_NIC_MINI_RCV_BUFFER_DESC_ADDR_EXT_MEM 0xe000
-
-#define T3_NIC_SND_BUFFER_DESC_SIZE (T3_SEND_RCB_ENTRY_COUNT * \
- sizeof(T3_SND_BD) / 4)
-
-#define T3_NIC_STD_RCV_BUFFER_DESC_SIZE (T3_STD_RCV_RCB_ENTRY_COUNT * \
- sizeof(T3_RCV_BD) / 4)
-
-#define T3_NIC_JUMBO_RCV_BUFFER_DESC_SIZE (T3_JUMBO_RCV_RCB_ENTRY_COUNT * \
- sizeof(T3_EXT_RCV_BD) / 4)
-
-/* MBUF pool. */
-#define T3_NIC_MBUF_POOL_ADDR 0x8000
-/* #define T3_NIC_MBUF_POOL_SIZE 0x18000 */
-#define T3_NIC_MBUF_POOL_SIZE96 0x18000
-#define T3_NIC_MBUF_POOL_SIZE64 0x10000
-
-#define T3_NIC_MBUF_POOL_ADDR_EXT_MEM 0x20000
-
-/* DMA descriptor pool */
-#define T3_NIC_DMA_DESC_POOL_ADDR 0x2000
-#define T3_NIC_DMA_DESC_POOL_SIZE 0x2000 /* 8KB. */
-
-#define T3_DEF_DMA_MBUF_LOW_WMARK 0x40
-#define T3_DEF_RX_MAC_MBUF_LOW_WMARK 0x20
-#define T3_DEF_MBUF_HIGH_WMARK 0x60
-
-#define T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO 304
-#define T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO 152
-#define T3_DEF_MBUF_HIGH_WMARK_JUMBO 380
-
-#define T3_DEF_DMA_DESC_LOW_WMARK 5
-#define T3_DEF_DMA_DESC_HIGH_WMARK 10
-
-/* Maximum size of giant TCP packet can be sent */
-#define T3_TCP_SEG_MAX_OFFLOAD_SIZE 64*1000
-#define T3_TCP_SEG_MIN_NUM_SEG 20
-
-#define T3_RX_CPU_ID 0x1
-#define T3_TX_CPU_ID 0x2
-#define T3_RX_CPU_SPAD_ADDR 0x30000
-#define T3_RX_CPU_SPAD_SIZE 0x4000
-#define T3_TX_CPU_SPAD_ADDR 0x34000
-#define T3_TX_CPU_SPAD_SIZE 0x4000
-
-typedef struct T3_DIR_ENTRY {
- PLM_UINT8 Buffer;
- LM_UINT32 Offset;
- LM_UINT32 Length;
-} T3_DIR_ENTRY, *PT3_DIR_ENTRY;
-
-typedef struct T3_FWIMG_INFO {
- LM_UINT32 StartAddress;
- T3_DIR_ENTRY Text;
- T3_DIR_ENTRY ROnlyData;
- T3_DIR_ENTRY Data;
- T3_DIR_ENTRY Sbss;
- T3_DIR_ENTRY Bss;
-} T3_FWIMG_INFO, *PT3_FWIMG_INFO;
-
-/******************************************************************************/
-/* Tigon3 PCI Registers. */
-/******************************************************************************/
-#define T3_PCI_ID_BCM5700 0x164414e4
-#define T3_PCI_ID_BCM5701 0x164514e4
-#define T3_PCI_ID_BCM5702 0x164614e4
-#define T3_PCI_ID_BCM5702x 0x16A614e4
-#define T3_PCI_ID_BCM5703 0x164714e4
-#define T3_PCI_ID_BCM5703x 0x16A714e4
-#define T3_PCI_ID_BCM5702FE 0x164D14e4
-#define T3_PCI_ID_BCM5704 0x164814e4
-
-#define T3_PCI_VENDOR_ID (T3_PCI_ID & 0xffff)
-#define T3_PCI_DEVICE_ID (T3_PCI_ID >> 16)
-
-#define T3_PCI_MISC_HOST_CTRL_REG 0x68
-
-/* The most significant 16bit of register 0x68. */
-/* ChipId:4, ChipRev:4, MetalRev:8 */
-#define T3_CHIP_ID_5700_A0 0x7000
-#define T3_CHIP_ID_5700_A1 0x7001
-#define T3_CHIP_ID_5700_B0 0x7100
-#define T3_CHIP_ID_5700_B1 0x7101
-#define T3_CHIP_ID_5700_C0 0x7200
-
-#define T3_CHIP_ID_5701_A0 0x0000
-#define T3_CHIP_ID_5701_B0 0x0100
-#define T3_CHIP_ID_5701_B2 0x0102
-#define T3_CHIP_ID_5701_B5 0x0105
-
-#define T3_CHIP_ID_5703_A0 0x1000
-#define T3_CHIP_ID_5703_A1 0x1001
-#define T3_CHIP_ID_5703_A2 0x1002
-
-#define T3_CHIP_ID_5704_A0 0x2000
-
-/* Chip Id. */
-#define T3_ASIC_REV(_ChipRevId) ((_ChipRevId) >> 12)
-#define T3_ASIC_REV_5700 0x07
-#define T3_ASIC_REV_5701 0x00
-#define T3_ASIC_REV_5703 0x01
-#define T3_ASIC_REV_5704 0x02
-
-/* Chip id and revision. */
-#define T3_CHIP_REV(_ChipRevId) ((_ChipRevId) >> 8)
-#define T3_CHIP_REV_5700_AX 0x70
-#define T3_CHIP_REV_5700_BX 0x71
-#define T3_CHIP_REV_5700_CX 0x72
-#define T3_CHIP_REV_5701_AX 0x00
-
-/* Metal revision. */
-#define T3_METAL_REV(_ChipRevId) ((_ChipRevId) & 0xff)
-#define T3_METAL_REV_A0 0x00
-#define T3_METAL_REV_A1 0x01
-#define T3_METAL_REV_B0 0x00
-#define T3_METAL_REV_B1 0x01
-#define T3_METAL_REV_B2 0x02
-
-#define T3_PCI_REG_CLOCK_CTRL 0x74
-
-#define T3_PCI_DISABLE_RX_CLOCK BIT_10
-#define T3_PCI_DISABLE_TX_CLOCK BIT_11
-#define T3_PCI_SELECT_ALTERNATE_CLOCK BIT_12
-#define T3_PCI_POWER_DOWN_PCI_PLL133 BIT_15
-#define T3_PCI_44MHZ_CORE_CLOCK BIT_18
-
-#define T3_PCI_REG_ADDR_REG 0x78
-#define T3_PCI_REG_DATA_REG 0x80
-
-#define T3_PCI_MEM_WIN_ADDR_REG 0x7c
-#define T3_PCI_MEM_WIN_DATA_REG 0x84
-
-#define T3_PCI_PM_CAP_REG 0x48
-
-#define T3_PCI_PM_CAP_PME_D3COLD BIT_31
-#define T3_PCI_PM_CAP_PME_D3HOT BIT_30
-
-#define T3_PCI_PM_STATUS_CTRL_REG 0x4c
-
-#define T3_PM_POWER_STATE_MASK (BIT_0 | BIT_1)
-#define T3_PM_POWER_STATE_D0 BIT_NONE
-#define T3_PM_POWER_STATE_D1 BIT_0
-#define T3_PM_POWER_STATE_D2 BIT_1
-#define T3_PM_POWER_STATE_D3 (BIT_0 | BIT_1)
-
-#define T3_PM_PME_ENABLE BIT_8
-#define T3_PM_PME_ASSERTED BIT_15
-
-/* PCI state register. */
-#define T3_PCI_STATE_REG 0x70
-
-#define T3_PCI_STATE_FORCE_RESET BIT_0
-#define T3_PCI_STATE_INT_NOT_ACTIVE BIT_1
-#define T3_PCI_STATE_CONVENTIONAL_PCI_MODE BIT_2
-#define T3_PCI_STATE_BUS_SPEED_HIGH BIT_3
-#define T3_PCI_STATE_32BIT_PCI_BUS BIT_4
-
-/* Broadcom subsystem/subvendor IDs. */
-#define T3_SVID_BROADCOM 0x14e4
-
-#define T3_SSID_BROADCOM_BCM95700A6 0x1644
-#define T3_SSID_BROADCOM_BCM95701A5 0x0001
-#define T3_SSID_BROADCOM_BCM95700T6 0x0002 /* BCM8002 */
-#define T3_SSID_BROADCOM_BCM95700A9 0x0003 /* Agilent */
-#define T3_SSID_BROADCOM_BCM95701T1 0x0005
-#define T3_SSID_BROADCOM_BCM95701T8 0x0006
-#define T3_SSID_BROADCOM_BCM95701A7 0x0007 /* Agilent */
-#define T3_SSID_BROADCOM_BCM95701A10 0x0008
-#define T3_SSID_BROADCOM_BCM95701A12 0x8008
-#define T3_SSID_BROADCOM_BCM95703Ax1 0x0009
-#define T3_SSID_BROADCOM_BCM95703Ax2 0x8009
-
-/* 3COM subsystem/subvendor IDs. */
-#define T3_SVID_3COM 0x10b7
-
-#define T3_SSID_3COM_3C996T 0x1000
-#define T3_SSID_3COM_3C996BT 0x1006
-#define T3_SSID_3COM_3C996CT 0x1002
-#define T3_SSID_3COM_3C997T 0x1003
-#define T3_SSID_3COM_3C1000T 0x1007
-#define T3_SSID_3COM_3C940BR01 0x1008
-
-/* Fiber boards. */
-#define T3_SSID_3COM_3C996SX 0x1004
-#define T3_SSID_3COM_3C997SX 0x1005
-
-/* Dell subsystem/subvendor IDs. */
-
-#define T3_SVID_DELL 0x1028
-
-#define T3_SSID_DELL_VIPER 0x00d1
-#define T3_SSID_DELL_JAGUAR 0x0106
-#define T3_SSID_DELL_MERLOT 0x0109
-#define T3_SSID_DELL_SLIM_MERLOT 0x010a
-
-/* Compaq subsystem/subvendor IDs */
-
-#define T3_SVID_COMPAQ 0x0e11
-
-#define T3_SSID_COMPAQ_BANSHEE 0x007c
-#define T3_SSID_COMPAQ_BANSHEE_2 0x009a
-#define T3_SSID_COMPAQ_CHANGELING 0x007d
-#define T3_SSID_COMPAQ_NC7780 0x0085
-#define T3_SSID_COMPAQ_NC7780_2 0x0099
-
-/******************************************************************************/
-/* MII registers. */
-/******************************************************************************/
-
-/* Control register. */
-#define PHY_CTRL_REG 0x00
-
-#define PHY_CTRL_SPEED_MASK (BIT_6 | BIT_13)
-#define PHY_CTRL_SPEED_SELECT_10MBPS BIT_NONE
-#define PHY_CTRL_SPEED_SELECT_100MBPS BIT_13
-#define PHY_CTRL_SPEED_SELECT_1000MBPS BIT_6
-#define PHY_CTRL_COLLISION_TEST_ENABLE BIT_7
-#define PHY_CTRL_FULL_DUPLEX_MODE BIT_8
-#define PHY_CTRL_RESTART_AUTO_NEG BIT_9
-#define PHY_CTRL_ISOLATE_PHY BIT_10
-#define PHY_CTRL_LOWER_POWER_MODE BIT_11
-#define PHY_CTRL_AUTO_NEG_ENABLE BIT_12
-#define PHY_CTRL_LOOPBACK_MODE BIT_14
-#define PHY_CTRL_PHY_RESET BIT_15
-
-/* Status register. */
-#define PHY_STATUS_REG 0x01
-
-#define PHY_STATUS_LINK_PASS BIT_2
-#define PHY_STATUS_AUTO_NEG_COMPLETE BIT_5
-
-/* Phy Id registers. */
-#define PHY_ID1_REG 0x02
-#define PHY_ID1_OUI_MASK 0xffff
-
-#define PHY_ID2_REG 0x03
-#define PHY_ID2_REV_MASK 0x000f
-#define PHY_ID2_MODEL_MASK 0x03f0
-#define PHY_ID2_OUI_MASK 0xfc00
-
-/* Auto-negotiation advertisement register. */
-#define PHY_AN_AD_REG 0x04
-
-#define PHY_AN_AD_ASYM_PAUSE BIT_11
-#define PHY_AN_AD_PAUSE_CAPABLE BIT_10
-#define PHY_AN_AD_10BASET_HALF BIT_5
-#define PHY_AN_AD_10BASET_FULL BIT_6
-#define PHY_AN_AD_100BASETX_HALF BIT_7
-#define PHY_AN_AD_100BASETX_FULL BIT_8
-#define PHY_AN_AD_PROTOCOL_802_3_CSMA_CD 0x01
-
-/* Auto-negotiation Link Partner Ability register. */
-#define PHY_LINK_PARTNER_ABILITY_REG 0x05
-
-#define PHY_LINK_PARTNER_ASYM_PAUSE BIT_11
-#define PHY_LINK_PARTNER_PAUSE_CAPABLE BIT_10
-
-/* Auto-negotiation expansion register. */
-#define PHY_AN_EXPANSION_REG 0x06
-
-/******************************************************************************/
-/* BCM5400 and BCM5401 phy info. */
-/******************************************************************************/
-
-#define PHY_DEVICE_ID 1
-
-/* OUI: bit 31-10; Model#: bit 9-4; Rev# bit 3-0. */
-#define PHY_UNKNOWN_PHY 0x00000000
-#define PHY_BCM5400_PHY_ID 0x60008040
-#define PHY_BCM5401_PHY_ID 0x60008050
-#define PHY_BCM5411_PHY_ID 0x60008070
-#define PHY_BCM5701_PHY_ID 0x60008110
-#define PHY_BCM5703_PHY_ID 0x60008160
-#define PHY_BCM5704_PHY_ID 0x60008190
-#define PHY_BCM8002_PHY_ID 0x60010140
-
-#define PHY_BCM5401_B0_REV 0x1
-#define PHY_BCM5401_B2_REV 0x3
-#define PHY_BCM5401_C0_REV 0x6
-
-#define PHY_ID_OUI_MASK 0xfffffc00
-#define PHY_ID_MODEL_MASK 0x000003f0
-#define PHY_ID_REV_MASK 0x0000000f
-#define PHY_ID_MASK (PHY_ID_OUI_MASK | \
- PHY_ID_MODEL_MASK)
-
-#define UNKNOWN_PHY_ID(x) ((((x) & PHY_ID_MASK) != PHY_BCM5400_PHY_ID) && \
- (((x) & PHY_ID_MASK) != PHY_BCM5401_PHY_ID) && \
- (((x) & PHY_ID_MASK) != PHY_BCM5411_PHY_ID) && \
- (((x) & PHY_ID_MASK) != PHY_BCM5701_PHY_ID) && \
- (((x) & PHY_ID_MASK) != PHY_BCM5703_PHY_ID) && \
- (((x) & PHY_ID_MASK) != PHY_BCM5704_PHY_ID) && \
- (((x) & PHY_ID_MASK) != PHY_BCM8002_PHY_ID))
-
-/* 1000Base-T control register. */
-#define BCM540X_1000BASET_CTRL_REG 0x09
-
-#define BCM540X_AN_AD_1000BASET_HALF BIT_8
-#define BCM540X_AN_AD_1000BASET_FULL BIT_9
-#define BCM540X_CONFIG_AS_MASTER BIT_11
-#define BCM540X_ENABLE_CONFIG_AS_MASTER BIT_12
-
-/* Extended control register. */
-#define BCM540X_EXT_CTRL_REG 0x10
-
-#define BCM540X_EXT_CTRL_LINK3_LED_MODE BIT_1
-#define BCM540X_EXT_CTRL_TBI BIT_15
-
-/* PHY extended status register. */
-#define BCM540X_EXT_STATUS_REG 0x11
-
-#define BCM540X_EXT_STATUS_LINK_PASS BIT_8
-
-/* DSP Coefficient Read/Write Port. */
-#define BCM540X_DSP_RW_PORT 0x15
-
-/* DSP Coeficient Address Register. */
-#define BCM540X_DSP_ADDRESS_REG 0x17
-
-#define BCM540X_DSP_TAP_NUMBER_MASK 0x00
-#define BCM540X_DSP_AGC_A 0x00
-#define BCM540X_DSP_AGC_B 0x01
-#define BCM540X_DSP_MSE_PAIR_STATUS 0x02
-#define BCM540X_DSP_SOFT_DECISION 0x03
-#define BCM540X_DSP_PHASE_REG 0x04
-#define BCM540X_DSP_SKEW 0x05
-#define BCM540X_DSP_POWER_SAVER_UPPER_BOUND 0x06
-#define BCM540X_DSP_POWER_SAVER_LOWER_BOUND 0x07
-#define BCM540X_DSP_LAST_ECHO 0x08
-#define BCM540X_DSP_FREQUENCY 0x09
-#define BCM540X_DSP_PLL_BANDWIDTH 0x0a
-#define BCM540X_DSP_PLL_PHASE_OFFSET 0x0b
-
-#define BCM540X_DSP_FILTER_DCOFFSET (BIT_10 | BIT_11)
-#define BCM540X_DSP_FILTER_FEXT3 (BIT_8 | BIT_9 | BIT_11)
-#define BCM540X_DSP_FILTER_FEXT2 (BIT_9 | BIT_11)
-#define BCM540X_DSP_FILTER_FEXT1 (BIT_8 | BIT_11)
-#define BCM540X_DSP_FILTER_FEXT0 BIT_11
-#define BCM540X_DSP_FILTER_NEXT3 (BIT_8 | BIT_9 | BIT_10)
-#define BCM540X_DSP_FILTER_NEXT2 (BIT_9 | BIT_10)
-#define BCM540X_DSP_FILTER_NEXT1 (BIT_8 | BIT_10)
-#define BCM540X_DSP_FILTER_NEXT0 BIT_10
-#define BCM540X_DSP_FILTER_ECHO (BIT_8 | BIT_9)
-#define BCM540X_DSP_FILTER_DFE BIT_9
-#define BCM540X_DSP_FILTER_FFE BIT_8
-
-#define BCM540X_DSP_CONTROL_ALL_FILTERS BIT_12
-
-#define BCM540X_DSP_SEL_CH_0 BIT_NONE
-#define BCM540X_DSP_SEL_CH_1 BIT_13
-#define BCM540X_DSP_SEL_CH_2 BIT_14
-#define BCM540X_DSP_SEL_CH_3 (BIT_13 | BIT_14)
-
-#define BCM540X_CONTROL_ALL_CHANNELS BIT_15
-
-/* Auxilliary Control Register (Shadow Register) */
-#define BCM5401_AUX_CTRL 0x18
-
-#define BCM5401_SHADOW_SEL_MASK 0x7
-#define BCM5401_SHADOW_SEL_NORMAL 0x00
-#define BCM5401_SHADOW_SEL_10BASET 0x01
-#define BCM5401_SHADOW_SEL_POWER_CONTROL 0x02
-#define BCM5401_SHADOW_SEL_IP_PHONE 0x03
-#define BCM5401_SHADOW_SEL_MISC_TEST1 0x04
-#define BCM5401_SHADOW_SEL_MISC_TEST2 0x05
-#define BCM5401_SHADOW_SEL_IP_PHONE_SEED 0x06
-
-/* Shadow register selector == '000' */
-#define BCM5401_SHDW_NORMAL_DIAG_MODE BIT_3
-#define BCM5401_SHDW_NORMAL_DISABLE_MBP BIT_4
-#define BCM5401_SHDW_NORMAL_DISABLE_LOW_PWR BIT_5
-#define BCM5401_SHDW_NORMAL_DISABLE_INV_PRF BIT_6
-#define BCM5401_SHDW_NORMAL_DISABLE_PRF BIT_7
-#define BCM5401_SHDW_NORMAL_RX_SLICING_NORMAL BIT_NONE
-#define BCM5401_SHDW_NORMAL_RX_SLICING_4D BIT_8
-#define BCM5401_SHDW_NORMAL_RX_SLICING_3LVL_1D BIT_9
-#define BCM5401_SHDW_NORMAL_RX_SLICING_5LVL_1D (BIT_8 | BIT_9)
-#define BCM5401_SHDW_NORMAL_TX_6DB_CODING BIT_10
-#define BCM5401_SHDW_NORMAL_ENABLE_SM_DSP_CLOCK BIT_11
-#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_4NS BIT_NONE
-#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_5NS BIT_12
-#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_3NS BIT_13
-#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_0NS (BIT_12 | BIT_13)
-#define BCM5401_SHDW_NORMAL_EXT_PACKET_LENGTH BIT_14
-#define BCM5401_SHDW_NORMAL_EXTERNAL_LOOPBACK BIT_15
-
-/* Auxilliary status summary. */
-#define BCM540X_AUX_STATUS_REG 0x19
-
-#define BCM540X_AUX_LINK_PASS BIT_2
-#define BCM540X_AUX_SPEED_MASK (BIT_8 | BIT_9 | BIT_10)
-#define BCM540X_AUX_10BASET_HD BIT_8
-#define BCM540X_AUX_10BASET_FD BIT_9
-#define BCM540X_AUX_100BASETX_HD (BIT_8 | BIT_9)
-#define BCM540X_AUX_100BASET4 BIT_10
-#define BCM540X_AUX_100BASETX_FD (BIT_8 | BIT_10)
-#define BCM540X_AUX_100BASET_HD (BIT_9 | BIT_10)
-#define BCM540X_AUX_100BASET_FD (BIT_8 | BIT_9 | BIT_10)
-
-/* Interrupt status. */
-#define BCM540X_INT_STATUS_REG 0x1a
-
-#define BCM540X_INT_LINK_CHANGE BIT_1
-#define BCM540X_INT_SPEED_CHANGE BIT_2
-#define BCM540X_INT_DUPLEX_CHANGE BIT_3
-#define BCM540X_INT_AUTO_NEG_PAGE_RX BIT_10
-
-/* Interrupt mask register. */
-#define BCM540X_INT_MASK_REG 0x1b
-
-/******************************************************************************/
-/* Register definitions. */
-/******************************************************************************/
-
-typedef volatile LM_UINT8 T3_8BIT_REGISTER, *PT3_8BIT_REGISTER;
-typedef volatile LM_UINT16 T3_16BIT_REGISTER, *PT3_16BIT_REGISTER;
-typedef volatile LM_UINT32 T3_32BIT_REGISTER, *PT3_32BIT_REGISTER;
-
-typedef struct {
- /* Big endian format. */
- T3_32BIT_REGISTER High;
- T3_32BIT_REGISTER Low;
-} T3_64BIT_REGISTER, *PT3_64BIT_REGISTER;
-
-typedef T3_64BIT_REGISTER T3_64BIT_HOST_ADDR, *PT3_64BIT_HOST_ADDR;
-
-#define T3_NUM_OF_DMA_DESC 256
-#define T3_NUM_OF_MBUF 768
-
-typedef struct {
- T3_64BIT_REGISTER host_addr;
- T3_32BIT_REGISTER nic_mbuf;
- T3_16BIT_REGISTER len;
- T3_16BIT_REGISTER cqid_sqid;
- T3_32BIT_REGISTER flags;
- T3_32BIT_REGISTER opaque1;
- T3_32BIT_REGISTER opaque2;
- T3_32BIT_REGISTER opaque3;
-} T3_DMA_DESC, *PT3_DMA_DESC;
-
-/******************************************************************************/
-/* Ring control block. */
-/******************************************************************************/
-
-typedef struct {
- T3_64BIT_REGISTER HostRingAddr;
-
- union {
- struct {
-#ifdef BIG_ENDIAN_HOST
- T3_16BIT_REGISTER MaxLen;
- T3_16BIT_REGISTER Flags;
-#else /* BIG_ENDIAN_HOST */
- T3_16BIT_REGISTER Flags;
- T3_16BIT_REGISTER MaxLen;
-#endif
- } s;
-
- T3_32BIT_REGISTER MaxLen_Flags;
- } u;
-
- T3_32BIT_REGISTER NicRingAddr;
-} T3_RCB, *PT3_RCB;
-
-#define T3_RCB_FLAG_USE_EXT_RECV_BD BIT_0
-#define T3_RCB_FLAG_RING_DISABLED BIT_1
-
-/******************************************************************************/
-/* Status block. */
-/******************************************************************************/
-
-/*
- * Size of status block is actually 0x50 bytes. Use 0x80 bytes for
- * cache line alignment.
- */
-#define T3_STATUS_BLOCK_SIZE 0x80
-
-typedef struct {
- volatile LM_UINT32 Status;
-#define STATUS_BLOCK_UPDATED BIT_0
-#define STATUS_BLOCK_LINK_CHANGED_STATUS BIT_1
-#define STATUS_BLOCK_ERROR BIT_2
-
- volatile LM_UINT32 StatusTag;
-
-#ifdef BIG_ENDIAN_HOST
- volatile LM_UINT16 RcvStdConIdx;
- volatile LM_UINT16 RcvJumboConIdx;
-
- volatile LM_UINT16 Reserved2;
- volatile LM_UINT16 RcvMiniConIdx;
-
- struct {
- volatile LM_UINT16 SendConIdx; /* Send consumer index. */
- volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */
- } Idx[16];
-#else /* BIG_ENDIAN_HOST */
- volatile LM_UINT16 RcvJumboConIdx;
- volatile LM_UINT16 RcvStdConIdx;
-
- volatile LM_UINT16 RcvMiniConIdx;
- volatile LM_UINT16 Reserved2;
-
- struct {
- volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */
- volatile LM_UINT16 SendConIdx; /* Send consumer index. */
- } Idx[16];
-#endif
-} T3_STATUS_BLOCK, *PT3_STATUS_BLOCK;
-
-/******************************************************************************/
-/* Receive buffer descriptors. */
-/******************************************************************************/
-
-typedef struct {
- T3_64BIT_HOST_ADDR HostAddr;
-
-#ifdef BIG_ENDIAN_HOST
- volatile LM_UINT16 Index;
- volatile LM_UINT16 Len;
-
- volatile LM_UINT16 Type;
- volatile LM_UINT16 Flags;
-
- volatile LM_UINT16 IpCksum;
- volatile LM_UINT16 TcpUdpCksum;
-
- volatile LM_UINT16 ErrorFlag;
- volatile LM_UINT16 VlanTag;
-#else /* BIG_ENDIAN_HOST */
- volatile LM_UINT16 Len;
- volatile LM_UINT16 Index;
-
- volatile LM_UINT16 Flags;
- volatile LM_UINT16 Type;
-
- volatile LM_UINT16 TcpUdpCksum;
- volatile LM_UINT16 IpCksum;
-
- volatile LM_UINT16 VlanTag;
- volatile LM_UINT16 ErrorFlag;
-#endif
-
- volatile LM_UINT32 Reserved;
- volatile LM_UINT32 Opaque;
-} T3_RCV_BD, *PT3_RCV_BD;
-
-typedef struct {
- T3_64BIT_HOST_ADDR HostAddr[3];
-
-#ifdef BIG_ENDIAN_HOST
- LM_UINT16 Len1;
- LM_UINT16 Len2;
-
- LM_UINT16 Len3;
- LM_UINT16 Reserved1;
-#else /* BIG_ENDIAN_HOST */
- LM_UINT16 Len2;
- LM_UINT16 Len1;
-
- LM_UINT16 Reserved1;
- LM_UINT16 Len3;
-#endif
-
- T3_RCV_BD StdRcvBd;
-} T3_EXT_RCV_BD, *PT3_EXT_RCV_BD;
-
-/* Error flags. */
-#define RCV_BD_ERR_BAD_CRC 0x0001
-#define RCV_BD_ERR_COLL_DETECT 0x0002
-#define RCV_BD_ERR_LINK_LOST_DURING_PKT 0x0004
-#define RCV_BD_ERR_PHY_DECODE_ERR 0x0008
-#define RCV_BD_ERR_ODD_NIBBLED_RCVD_MII 0x0010
-#define RCV_BD_ERR_MAC_ABORT 0x0020
-#define RCV_BD_ERR_LEN_LT_64 0x0040
-#define RCV_BD_ERR_TRUNC_NO_RESOURCES 0x0080
-#define RCV_BD_ERR_GIANT_FRAME_RCVD 0x0100
-
-/* Buffer descriptor flags. */
-#define RCV_BD_FLAG_END 0x0004
-#define RCV_BD_FLAG_JUMBO_RING 0x0020
-#define RCV_BD_FLAG_VLAN_TAG 0x0040
-#define RCV_BD_FLAG_FRAME_HAS_ERROR 0x0400
-#define RCV_BD_FLAG_MINI_RING 0x0800
-#define RCV_BD_FLAG_IP_CHKSUM_FIELD 0x1000
-#define RCV_BD_FLAG_TCP_UDP_CHKSUM_FIELD 0x2000
-#define RCV_BD_FLAG_TCP_PACKET 0x4000
-
-/******************************************************************************/
-/* Send buffer descriptor. */
-/******************************************************************************/
-
-typedef struct {
- T3_64BIT_HOST_ADDR HostAddr;
-
- union {
- struct {
-#ifdef BIG_ENDIAN_HOST
- LM_UINT16 Len;
- LM_UINT16 Flags;
-#else /* BIG_ENDIAN_HOST */
- LM_UINT16 Flags;
- LM_UINT16 Len;
-#endif
- } s1;
-
- LM_UINT32 Len_Flags;
- } u1;
-
- union {
- struct {
-#ifdef BIG_ENDIAN_HOST
- LM_UINT16 Reserved;
- LM_UINT16 VlanTag;
-#else /* BIG_ENDIAN_HOST */
- LM_UINT16 VlanTag;
- LM_UINT16 Reserved;
-#endif
- } s2;
-
- LM_UINT32 VlanTag;
- } u2;
-} T3_SND_BD, *PT3_SND_BD;
-
-/* Send buffer descriptor flags. */
-#define SND_BD_FLAG_TCP_UDP_CKSUM 0x0001
-#define SND_BD_FLAG_IP_CKSUM 0x0002
-#define SND_BD_FLAG_END 0x0004
-#define SND_BD_FLAG_IP_FRAG 0x0008
-#define SND_BD_FLAG_IP_FRAG_END 0x0010
-#define SND_BD_FLAG_VLAN_TAG 0x0040
-#define SND_BD_FLAG_COAL_NOW 0x0080
-#define SND_BD_FLAG_CPU_PRE_DMA 0x0100
-#define SND_BD_FLAG_CPU_POST_DMA 0x0200
-#define SND_BD_FLAG_INSERT_SRC_ADDR 0x1000
-#define SND_BD_FLAG_CHOOSE_SRC_ADDR 0x6000
-#define SND_BD_FLAG_DONT_GEN_CRC 0x8000
-
-/* MBUFs */
-typedef struct T3_MBUF_FRAME_DESC {
-#ifdef BIG_ENDIAN_HOST
- LM_UINT32 status_control;
- union {
- struct {
- LM_UINT8 cqid;
- LM_UINT8 reserved1;
- LM_UINT16 length;
- } s1;
- LM_UINT32 word;
- } u1;
- union {
- struct {
- LM_UINT16 ip_hdr_start;
- LM_UINT16 tcp_udp_hdr_start;
- } s2;
-
- LM_UINT32 word;
- } u2;
-
- union {
- struct {
- LM_UINT16 data_start;
- LM_UINT16 vlan_id;
- } s3;
-
- LM_UINT32 word;
- } u3;
-
- union {
- struct {
- LM_UINT16 ip_checksum;
- LM_UINT16 tcp_udp_checksum;
- } s4;
-
- LM_UINT32 word;
- } u4;
-
- union {
- struct {
- LM_UINT16 pseudo_checksum;
- LM_UINT16 checksum_status;
- } s5;
-
- LM_UINT32 word;
- } u5;
-
- union {
- struct {
- LM_UINT16 rule_match;
- LM_UINT8 class;
- LM_UINT8 rupt;
- } s6;
-
- LM_UINT32 word;
- } u6;
-
- union {
- struct {
- LM_UINT16 reserved2;
- LM_UINT16 mbuf_num;
- } s7;
-
- LM_UINT32 word;
- } u7;
-
- LM_UINT32 reserved3;
- LM_UINT32 reserved4;
-#else
- LM_UINT32 status_control;
- union {
- struct {
- LM_UINT16 length;
- LM_UINT8 reserved1;
- LM_UINT8 cqid;
- } s1;
- LM_UINT32 word;
- } u1;
- union {
- struct {
- LM_UINT16 tcp_udp_hdr_start;
- LM_UINT16 ip_hdr_start;
- } s2;
-
- LM_UINT32 word;
- } u2;
-
- union {
- struct {
- LM_UINT16 vlan_id;
- LM_UINT16 data_start;
- } s3;
-
- LM_UINT32 word;
- } u3;
-
- union {
- struct {
- LM_UINT16 tcp_udp_checksum;
- LM_UINT16 ip_checksum;
- } s4;
-
- LM_UINT32 word;
- } u4;
-
- union {
- struct {
- LM_UINT16 checksum_status;
- LM_UINT16 pseudo_checksum;
- } s5;
-
- LM_UINT32 word;
- } u5;
-
- union {
- struct {
- LM_UINT8 rupt;
- LM_UINT8 class;
- LM_UINT16 rule_match;
- } s6;
-
- LM_UINT32 word;
- } u6;
-
- union {
- struct {
- LM_UINT16 mbuf_num;
- LM_UINT16 reserved2;
- } s7;
-
- LM_UINT32 word;
- } u7;
-
- LM_UINT32 reserved3;
- LM_UINT32 reserved4;
-#endif
-} T3_MBUF_FRAME_DESC, *PT3_MBUF_FRAME_DESC;
-
-typedef struct T3_MBUF_HDR {
- union {
- struct {
- unsigned int C:1;
- unsigned int F:1;
- unsigned int reserved1:7;
- unsigned int next_mbuf:16;
- unsigned int length:7;
- } s1;
-
- LM_UINT32 word;
- } u1;
-
- LM_UINT32 next_frame_ptr;
-} T3_MBUF_HDR, *PT3_MBUF_HDR;
-
-typedef struct T3_MBUF {
- T3_MBUF_HDR hdr;
- union {
- struct {
- T3_MBUF_FRAME_DESC frame_hdr;
- LM_UINT32 data[20];
- } s1;
-
- struct {
- LM_UINT32 data[30];
- } s2;
- } body;
-} T3_MBUF, *PT3_MBUF;
-
-#define T3_MBUF_BASE (T3_NIC_MBUF_POOL_ADDR >> 7)
-#define T3_MBUF_END ((T3_NIC_MBUF_POOL_ADDR + T3_NIC_MBUF_POOL_SIZE) >> 7)
-
-/******************************************************************************/
-/* Statistics block. */
-/******************************************************************************/
-
-typedef struct {
- LM_UINT8 Reserved0[0x400 - 0x300];
-
- /* Statistics maintained by Receive MAC. */
- T3_64BIT_REGISTER ifHCInOctets;
- T3_64BIT_REGISTER Reserved1;
- T3_64BIT_REGISTER etherStatsFragments;
- T3_64BIT_REGISTER ifHCInUcastPkts;
- T3_64BIT_REGISTER ifHCInMulticastPkts;
- T3_64BIT_REGISTER ifHCInBroadcastPkts;
- T3_64BIT_REGISTER dot3StatsFCSErrors;
- T3_64BIT_REGISTER dot3StatsAlignmentErrors;
- T3_64BIT_REGISTER xonPauseFramesReceived;
- T3_64BIT_REGISTER xoffPauseFramesReceived;
- T3_64BIT_REGISTER macControlFramesReceived;
- T3_64BIT_REGISTER xoffStateEntered;
- T3_64BIT_REGISTER dot3StatsFramesTooLong;
- T3_64BIT_REGISTER etherStatsJabbers;
- T3_64BIT_REGISTER etherStatsUndersizePkts;
- T3_64BIT_REGISTER inRangeLengthError;
- T3_64BIT_REGISTER outRangeLengthError;
- T3_64BIT_REGISTER etherStatsPkts64Octets;
- T3_64BIT_REGISTER etherStatsPkts65Octetsto127Octets;
- T3_64BIT_REGISTER etherStatsPkts128Octetsto255Octets;
- T3_64BIT_REGISTER etherStatsPkts256Octetsto511Octets;
- T3_64BIT_REGISTER etherStatsPkts512Octetsto1023Octets;
- T3_64BIT_REGISTER etherStatsPkts1024Octetsto1522Octets;
- T3_64BIT_REGISTER etherStatsPkts1523Octetsto2047Octets;
- T3_64BIT_REGISTER etherStatsPkts2048Octetsto4095Octets;
- T3_64BIT_REGISTER etherStatsPkts4096Octetsto8191Octets;
- T3_64BIT_REGISTER etherStatsPkts8192Octetsto9022Octets;
-
- T3_64BIT_REGISTER Unused1[37];
-
- /* Statistics maintained by Transmit MAC. */
- T3_64BIT_REGISTER ifHCOutOctets;
- T3_64BIT_REGISTER Reserved2;
- T3_64BIT_REGISTER etherStatsCollisions;
- T3_64BIT_REGISTER outXonSent;
- T3_64BIT_REGISTER outXoffSent;
- T3_64BIT_REGISTER flowControlDone;
- T3_64BIT_REGISTER dot3StatsInternalMacTransmitErrors;
- T3_64BIT_REGISTER dot3StatsSingleCollisionFrames;
- T3_64BIT_REGISTER dot3StatsMultipleCollisionFrames;
- T3_64BIT_REGISTER dot3StatsDeferredTransmissions;
- T3_64BIT_REGISTER Reserved3;
- T3_64BIT_REGISTER dot3StatsExcessiveCollisions;
- T3_64BIT_REGISTER dot3StatsLateCollisions;
- T3_64BIT_REGISTER dot3Collided2Times;
- T3_64BIT_REGISTER dot3Collided3Times;
- T3_64BIT_REGISTER dot3Collided4Times;
- T3_64BIT_REGISTER dot3Collided5Times;
- T3_64BIT_REGISTER dot3Collided6Times;
- T3_64BIT_REGISTER dot3Collided7Times;
- T3_64BIT_REGISTER dot3Collided8Times;
- T3_64BIT_REGISTER dot3Collided9Times;
- T3_64BIT_REGISTER dot3Collided10Times;
- T3_64BIT_REGISTER dot3Collided11Times;
- T3_64BIT_REGISTER dot3Collided12Times;
- T3_64BIT_REGISTER dot3Collided13Times;
- T3_64BIT_REGISTER dot3Collided14Times;
- T3_64BIT_REGISTER dot3Collided15Times;
- T3_64BIT_REGISTER ifHCOutUcastPkts;
- T3_64BIT_REGISTER ifHCOutMulticastPkts;
- T3_64BIT_REGISTER ifHCOutBroadcastPkts;
- T3_64BIT_REGISTER dot3StatsCarrierSenseErrors;
- T3_64BIT_REGISTER ifOutDiscards;
- T3_64BIT_REGISTER ifOutErrors;
-
- T3_64BIT_REGISTER Unused2[31];
-
- /* Statistics maintained by Receive List Placement. */
- T3_64BIT_REGISTER COSIfHCInPkts[16];
- T3_64BIT_REGISTER COSFramesDroppedDueToFilters;
- T3_64BIT_REGISTER nicDmaWriteQueueFull;
- T3_64BIT_REGISTER nicDmaWriteHighPriQueueFull;
- T3_64BIT_REGISTER nicNoMoreRxBDs;
- T3_64BIT_REGISTER ifInDiscards;
- T3_64BIT_REGISTER ifInErrors;
- T3_64BIT_REGISTER nicRecvThresholdHit;
-
- T3_64BIT_REGISTER Unused3[9];
-
- /* Statistics maintained by Send Data Initiator. */
- T3_64BIT_REGISTER COSIfHCOutPkts[16];
- T3_64BIT_REGISTER nicDmaReadQueueFull;
- T3_64BIT_REGISTER nicDmaReadHighPriQueueFull;
- T3_64BIT_REGISTER nicSendDataCompQueueFull;
-
- /* Statistics maintained by Host Coalescing. */
- T3_64BIT_REGISTER nicRingSetSendProdIndex;
- T3_64BIT_REGISTER nicRingStatusUpdate;
- T3_64BIT_REGISTER nicInterrupts;
- T3_64BIT_REGISTER nicAvoidedInterrupts;
- T3_64BIT_REGISTER nicSendThresholdHit;
-
- LM_UINT8 Reserved4[0xb00 - 0x9c0];
-} T3_STATS_BLOCK, *PT3_STATS_BLOCK;
-
-/******************************************************************************/
-/* PCI configuration registers. */
-/******************************************************************************/
-
-typedef struct {
- T3_16BIT_REGISTER VendorId;
- T3_16BIT_REGISTER DeviceId;
-
- T3_16BIT_REGISTER Command;
- T3_16BIT_REGISTER Status;
-
- T3_32BIT_REGISTER ClassCodeRevId;
-
- T3_8BIT_REGISTER CacheLineSize;
- T3_8BIT_REGISTER LatencyTimer;
- T3_8BIT_REGISTER HeaderType;
- T3_8BIT_REGISTER Bist;
-
- T3_32BIT_REGISTER MemBaseAddrLow;
- T3_32BIT_REGISTER MemBaseAddrHigh;
-
- LM_UINT8 Unused1[20];
-
- T3_16BIT_REGISTER SubsystemVendorId;
- T3_16BIT_REGISTER SubsystemId;
-
- T3_32BIT_REGISTER RomBaseAddr;
-
- T3_8BIT_REGISTER PciXCapiblityPtr;
- LM_UINT8 Unused2[7];
-
- T3_8BIT_REGISTER IntLine;
- T3_8BIT_REGISTER IntPin;
- T3_8BIT_REGISTER MinGnt;
- T3_8BIT_REGISTER MaxLat;
-
- T3_8BIT_REGISTER PciXCapabilities;
- T3_8BIT_REGISTER PmCapabilityPtr;
- T3_16BIT_REGISTER PciXCommand;
-
- T3_32BIT_REGISTER PciXStatus;
-
- T3_8BIT_REGISTER PmCapabilityId;
- T3_8BIT_REGISTER VpdCapabilityPtr;
- T3_16BIT_REGISTER PmCapabilities;
-
- T3_16BIT_REGISTER PmCtrlStatus;
-#define PM_CTRL_PME_STATUS BIT_15
-#define PM_CTRL_PME_ENABLE BIT_8
-#define PM_CTRL_PME_POWER_STATE_D0 0
-#define PM_CTRL_PME_POWER_STATE_D1 1
-#define PM_CTRL_PME_POWER_STATE_D2 2
-#define PM_CTRL_PME_POWER_STATE_D3H 3
-
- T3_8BIT_REGISTER BridgeSupportExt;
- T3_8BIT_REGISTER PmData;
-
- T3_8BIT_REGISTER VpdCapabilityId;
- T3_8BIT_REGISTER MsiCapabilityPtr;
- T3_16BIT_REGISTER VpdAddrFlag;
-#define VPD_FLAG_WRITE (1 << 15)
-#define VPD_FLAG_RW_MASK (1 << 15)
-#define VPD_FLAG_READ 0
-
- T3_32BIT_REGISTER VpdData;
-
- T3_8BIT_REGISTER MsiCapabilityId;
- T3_8BIT_REGISTER NextCapabilityPtr;
- T3_16BIT_REGISTER MsiCtrl;
-#define MSI_CTRL_64BIT_CAP (1 << 7)
-#define MSI_CTRL_MSG_ENABLE(x) (x << 4)
-#define MSI_CTRL_MSG_CAP(x) (x << 1)
-#define MSI_CTRL_ENABLE (1 << 0)
-
- T3_32BIT_REGISTER MsiAddrLow;
- T3_32BIT_REGISTER MsiAddrHigh;
-
- T3_16BIT_REGISTER MsiData;
- T3_16BIT_REGISTER Unused3;
-
- T3_32BIT_REGISTER MiscHostCtrl;
-#define MISC_HOST_CTRL_CLEAR_INT BIT_0
-#define MISC_HOST_CTRL_MASK_PCI_INT BIT_1
-#define MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP BIT_2
-#define MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP BIT_3
-#define MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW BIT_4
-#define MISC_HOST_CTRL_ENABLE_CLK_REG_RW BIT_5
-#define MISC_HOST_CTRL_ENABLE_REG_WORD_SWAP BIT_6
-#define MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS BIT_7
-#define MISC_HOST_CTRL_ENABLE_INT_MASK_MODE BIT_8
-#define MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE BIT_9
-
- T3_32BIT_REGISTER DmaReadWriteCtrl;
-#define DMA_CTRL_WRITE_BOUNDARY_MASK (BIT_11 | BIT_12 | BIT_13)
-#define DMA_CTRL_WRITE_BOUNDARY_DISABLE 0
-#define DMA_CTRL_WRITE_BOUNDARY_16 BIT_11
-#define DMA_CTRL_WRITE_BOUNDARY_32 BIT_12
-#define DMA_CTRL_WRITE_BOUNDARY_64 (BIT_12 | BIT_11)
-#define DMA_CTRL_WRITE_BOUNDARY_128 BIT_13
-#define DMA_CTRL_WRITE_BOUNDARY_256 (BIT_13 | BIT_11)
-#define DMA_CTRL_WRITE_BOUNDARY_512 (BIT_13 | BIT_12)
-#define DMA_CTRL_WRITE_BOUNDARY_1024 (BIT_13 | BIT_12 | BIT_11)
-#define DMA_CTRL_WRITE_ONE_DMA_AT_ONCE BIT_14
-
- T3_32BIT_REGISTER PciState;
-#define T3_PCI_STATE_FORCE_PCI_RESET BIT_0
-#define T3_PCI_STATE_INTERRUPT_NOT_ACTIVE BIT_1
-#define T3_PCI_STATE_NOT_PCI_X_BUS BIT_2
-#define T3_PCI_STATE_HIGH_BUS_SPEED BIT_3
-#define T3_PCI_STATE_32BIT_PCI_BUS BIT_4
-#define T3_PCI_STATE_PCI_ROM_ENABLE BIT_5
-#define T3_PCI_STATE_PCI_ROM_RETRY_ENABLE BIT_6
-#define T3_PCI_STATE_FLAT_VIEW BIT_8
-#define T3_PCI_STATE_RETRY_SAME_DMA BIT_13
-
- T3_32BIT_REGISTER ClockCtrl;
-#define T3_PCI_CLKCTRL_TXCPU_CLK_DISABLE BIT_11
-#define T3_PCI_CLKCTRL_RXCPU_CLK_DISABLE BIT_10
-#define T3_PCI_CLKCTRL_CORE_CLK_DISABLE BIT_9
-
- T3_32BIT_REGISTER RegBaseAddr;
-
- T3_32BIT_REGISTER MemWindowBaseAddr;
-
-#ifdef NIC_CPU_VIEW
- /* These registers are ONLY visible to NIC CPU */
- T3_32BIT_REGISTER PowerConsumed;
- T3_32BIT_REGISTER PowerDissipated;
-#else /* NIC_CPU_VIEW */
- T3_32BIT_REGISTER RegData;
- T3_32BIT_REGISTER MemWindowData;
-#endif /* !NIC_CPU_VIEW */
-
- T3_32BIT_REGISTER ModeCtrl;
-
- T3_32BIT_REGISTER MiscCfg;
-
- T3_32BIT_REGISTER MiscLocalCtrl;
-
- T3_32BIT_REGISTER Unused4;
-
- /* NOTE: Big/Little-endian clarification needed. Are these register */
- /* in big or little endian formate. */
- T3_64BIT_REGISTER StdRingProdIdx;
- T3_64BIT_REGISTER RcvRetRingConIdx;
- T3_64BIT_REGISTER SndProdIdx;
-
- LM_UINT8 Unused5[80];
-} T3_PCI_CONFIGURATION, *PT3_PCI_CONFIGURATION;
-
-#define PCIX_CMD_MAX_SPLIT_MASK 0x0070
-#define PCIX_CMD_MAX_SPLIT_SHL 4
-#define PCIX_CMD_MAX_BURST_MASK 0x000c
-#define PCIX_CMD_MAX_BURST_SHL 2
-#define PCIX_CMD_MAX_BURST_CPIOB 2
-
-/******************************************************************************/
-/* Mac control registers. */
-/******************************************************************************/
-
-typedef struct {
- /* MAC mode control. */
- T3_32BIT_REGISTER Mode;
-#define MAC_MODE_GLOBAL_RESET BIT_0
-#define MAC_MODE_HALF_DUPLEX BIT_1
-#define MAC_MODE_PORT_MODE_MASK (BIT_2 | BIT_3)
-#define MAC_MODE_PORT_MODE_TBI (BIT_2 | BIT_3)
-#define MAC_MODE_PORT_MODE_GMII BIT_3
-#define MAC_MODE_PORT_MODE_MII BIT_2
-#define MAC_MODE_PORT_MODE_NONE BIT_NONE
-#define MAC_MODE_PORT_INTERNAL_LOOPBACK BIT_4
-#define MAC_MODE_TAGGED_MAC_CONTROL BIT_7
-#define MAC_MODE_TX_BURSTING BIT_8
-#define MAC_MODE_MAX_DEFER BIT_9
-#define MAC_MODE_LINK_POLARITY BIT_10
-#define MAC_MODE_ENABLE_RX_STATISTICS BIT_11
-#define MAC_MODE_CLEAR_RX_STATISTICS BIT_12
-#define MAC_MODE_FLUSH_RX_STATISTICS BIT_13
-#define MAC_MODE_ENABLE_TX_STATISTICS BIT_14
-#define MAC_MODE_CLEAR_TX_STATISTICS BIT_15
-#define MAC_MODE_FLUSH_TX_STATISTICS BIT_16
-#define MAC_MODE_SEND_CONFIGS BIT_17
-#define MAC_MODE_DETECT_MAGIC_PACKET_ENABLE BIT_18
-#define MAC_MODE_ACPI_POWER_ON_ENABLE BIT_19
-#define MAC_MODE_ENABLE_MIP BIT_20
-#define MAC_MODE_ENABLE_TDE BIT_21
-#define MAC_MODE_ENABLE_RDE BIT_22
-#define MAC_MODE_ENABLE_FHDE BIT_23
-
- /* MAC status */
- T3_32BIT_REGISTER Status;
-#define MAC_STATUS_PCS_SYNCED BIT_0
-#define MAC_STATUS_SIGNAL_DETECTED BIT_1
-#define MAC_STATUS_RECEIVING_CFG BIT_2
-#define MAC_STATUS_CFG_CHANGED BIT_3
-#define MAC_STATUS_SYNC_CHANGED BIT_4
-#define MAC_STATUS_PORT_DECODE_ERROR BIT_10
-#define MAC_STATUS_LINK_STATE_CHANGED BIT_12
-#define MAC_STATUS_MI_COMPLETION BIT_22
-#define MAC_STATUS_MI_INTERRUPT BIT_23
-#define MAC_STATUS_AP_ERROR BIT_24
-#define MAC_STATUS_ODI_ERROR BIT_25
-#define MAC_STATUS_RX_STATS_OVERRUN BIT_26
-#define MAC_STATUS_TX_STATS_OVERRUN BIT_27
-
- /* Event Enable */
- T3_32BIT_REGISTER MacEvent;
-#define MAC_EVENT_ENABLE_PORT_DECODE_ERR BIT_10
-#define MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN BIT_12
-#define MAC_EVENT_ENABLE_MI_COMPLETION BIT_22
-#define MAC_EVENT_ENABLE_MI_INTERRUPT BIT_23
-#define MAC_EVENT_ENABLE_AP_ERROR BIT_24
-#define MAC_EVENT_ENABLE_ODI_ERROR BIT_25
-#define MAC_EVENT_ENABLE_RX_STATS_OVERRUN BIT_26
-#define MAC_EVENT_ENABLE_TX_STATS_OVERRUN BIT_27
-
- /* Led control. */
- T3_32BIT_REGISTER LedCtrl;
-#define LED_CTRL_OVERRIDE_LINK_LED BIT_0
-#define LED_CTRL_1000MBPS_LED_ON BIT_1
-#define LED_CTRL_100MBPS_LED_ON BIT_2
-#define LED_CTRL_10MBPS_LED_ON BIT_3
-#define LED_CTRL_OVERRIDE_TRAFFIC_LED BIT_4
-#define LED_CTRL_BLINK_TRAFFIC_LED BIT_5
-#define LED_CTRL_TRAFFIC_LED BIT_6
-#define LED_CTRL_1000MBPS_LED_STATUS BIT_7
-#define LED_CTRL_100MBPS_LED_STATUS BIT_8
-#define LED_CTRL_10MBPS_LED_STATUS BIT_9
-#define LED_CTRL_TRAFFIC_LED_STATUS BIT_10
-#define LED_CTRL_MAC_MODE BIT_NONE
-#define LED_CTRL_PHY_MODE_1 BIT_11
-#define LED_CTRL_PHY_MODE_2 BIT_12
-#define LED_CTRL_BLINK_RATE_MASK 0x7ff80000
-#define LED_CTRL_OVERRIDE_BLINK_PERIOD BIT_19
-#define LED_CTRL_OVERRIDE_BLINK_RATE BIT_31
-
- /* MAC addresses. */
- struct {
- T3_32BIT_REGISTER High; /* Upper 2 bytes. */
- T3_32BIT_REGISTER Low; /* Lower 4 bytes. */
- } MacAddr[4];
-
- /* ACPI Mbuf pointer. */
- T3_32BIT_REGISTER AcpiMbufPtr;
-
- /* ACPI Length and Offset. */
- T3_32BIT_REGISTER AcpiLengthOffset;
-#define ACPI_LENGTH_MASK 0xffff
-#define ACPI_OFFSET_MASK 0x0fff0000
-#define ACPI_LENGTH(x) x
-#define ACPI_OFFSET(x) ((x) << 16)
-
- /* Transmit random backoff. */
- T3_32BIT_REGISTER TxBackoffSeed;
-#define MAC_TX_BACKOFF_SEED_MASK 0x3ff
-
- /* Receive MTU */
- T3_32BIT_REGISTER MtuSize;
-#define MAC_RX_MTU_MASK 0xffff
-
- /* Gigabit PCS Test. */
- T3_32BIT_REGISTER PcsTest;
-#define MAC_PCS_TEST_DATA_PATTERN_MASK 0x0fffff
-#define MAC_PCS_TEST_ENABLE BIT_20
-
- /* Transmit Gigabit Auto-Negotiation. */
- T3_32BIT_REGISTER TxAutoNeg;
-#define MAC_AN_TX_AN_DATA_MASK 0xffff
-
- /* Receive Gigabit Auto-Negotiation. */
- T3_32BIT_REGISTER RxAutoNeg;
-#define MAC_AN_RX_AN_DATA_MASK 0xffff
-
- /* MI Communication. */
- T3_32BIT_REGISTER MiCom;
-#define MI_COM_CMD_MASK (BIT_26 | BIT_27)
-#define MI_COM_CMD_WRITE BIT_26
-#define MI_COM_CMD_READ BIT_27
-#define MI_COM_READ_FAILED BIT_28
-#define MI_COM_START BIT_29
-#define MI_COM_BUSY BIT_29
-
-#define MI_COM_PHY_ADDR_MASK 0x1f
-#define MI_COM_FIRST_PHY_ADDR_BIT 21
-
-#define MI_COM_PHY_REG_ADDR_MASK 0x1f
-#define MI_COM_FIRST_PHY_REG_ADDR_BIT 16
-
-#define MI_COM_PHY_DATA_MASK 0xffff
-
- /* MI Status. */
- T3_32BIT_REGISTER MiStatus;
-#define MI_STATUS_ENABLE_LINK_STATUS_ATTN BIT_0
-
- /* MI Mode. */
- T3_32BIT_REGISTER MiMode;
-#define MI_MODE_CLOCK_SPEED_10MHZ BIT_0
-#define MI_MODE_USE_SHORT_PREAMBLE BIT_1
-#define MI_MODE_AUTO_POLLING_ENABLE BIT_4
-#define MI_MODE_CORE_CLOCK_SPEED_62MHZ BIT_15
-
- /* Auto-polling status. */
- T3_32BIT_REGISTER AutoPollStatus;
-#define AUTO_POLL_ERROR BIT_0
-
- /* Transmit MAC mode. */
- T3_32BIT_REGISTER TxMode;
-#define TX_MODE_RESET BIT_0
-#define TX_MODE_ENABLE BIT_1
-#define TX_MODE_ENABLE_FLOW_CONTROL BIT_4
-#define TX_MODE_ENABLE_BIG_BACKOFF BIT_5
-#define TX_MODE_ENABLE_LONG_PAUSE BIT_6
-
- /* Transmit MAC status. */
- T3_32BIT_REGISTER TxStatus;
-#define TX_STATUS_RX_CURRENTLY_XOFFED BIT_0
-#define TX_STATUS_SENT_XOFF BIT_1
-#define TX_STATUS_SENT_XON BIT_2
-#define TX_STATUS_LINK_UP BIT_3
-#define TX_STATUS_ODI_UNDERRUN BIT_4
-#define TX_STATUS_ODI_OVERRUN BIT_5
-
- /* Transmit MAC length. */
- T3_32BIT_REGISTER TxLengths;
-#define TX_LEN_SLOT_TIME_MASK 0xff
-#define TX_LEN_IPG_MASK 0x0f00
-#define TX_LEN_IPG_CRS_MASK (BIT_12 | BIT_13)
-
- /* Receive MAC mode. */
- T3_32BIT_REGISTER RxMode;
-#define RX_MODE_RESET BIT_0
-#define RX_MODE_ENABLE BIT_1
-#define RX_MODE_ENABLE_FLOW_CONTROL BIT_2
-#define RX_MODE_KEEP_MAC_CONTROL BIT_3
-#define RX_MODE_KEEP_PAUSE BIT_4
-#define RX_MODE_ACCEPT_OVERSIZED BIT_5
-#define RX_MODE_ACCEPT_RUNTS BIT_6
-#define RX_MODE_LENGTH_CHECK BIT_7
-#define RX_MODE_PROMISCUOUS_MODE BIT_8
-#define RX_MODE_NO_CRC_CHECK BIT_9
-#define RX_MODE_KEEP_VLAN_TAG BIT_10
-
- /* Receive MAC status. */
- T3_32BIT_REGISTER RxStatus;
-#define RX_STATUS_REMOTE_TRANSMITTER_XOFFED BIT_0
-#define RX_STATUS_XOFF_RECEIVED BIT_1
-#define RX_STATUS_XON_RECEIVED BIT_2
-
- /* Hash registers. */
- T3_32BIT_REGISTER HashReg[4];
-
- /* Receive placement rules registers. */
- struct {
- T3_32BIT_REGISTER Rule;
- T3_32BIT_REGISTER Value;
- } RcvRules[16];
-
-#define RCV_DISABLE_RULE_MASK 0x7fffffff
-
-#define RCV_RULE1_REJECT_BROADCAST_IDX 0x00
-#define REJECT_BROADCAST_RULE1_RULE 0xc2000000
-#define REJECT_BROADCAST_RULE1_VALUE 0xffffffff
-
-#define RCV_RULE2_REJECT_BROADCAST_IDX 0x01
-#define REJECT_BROADCAST_RULE2_RULE 0x86000004
-#define REJECT_BROADCAST_RULE2_VALUE 0xffffffff
-
-#if INCLUDE_5701_AX_FIX
-#define RCV_LAST_RULE_IDX 0x04
-#else
-#define RCV_LAST_RULE_IDX 0x02
-#endif
-
- T3_32BIT_REGISTER RcvRuleCfg;
-#define RX_RULE_DEFAULT_CLASS (1 << 3)
-
- LM_UINT8 Reserved1[140];
-
- T3_32BIT_REGISTER SerdesCfg;
- T3_32BIT_REGISTER SerdesStatus;
-
- LM_UINT8 Reserved2[104];
-
- volatile LM_UINT8 TxMacState[16];
- volatile LM_UINT8 RxMacState[20];
-
- LM_UINT8 Reserved3[476];
-
- T3_32BIT_REGISTER RxStats[26];
-
- LM_UINT8 Reserved4[24];
-
- T3_32BIT_REGISTER TxStats[28];
-
- LM_UINT8 Reserved5[784];
-} T3_MAC_CONTROL, *PT3_MAC_CONTROL;
-
-/******************************************************************************/
-/* Send data initiator control registers. */
-/******************************************************************************/
-
-typedef struct {
- T3_32BIT_REGISTER Mode;
-#define T3_SND_DATA_IN_MODE_RESET BIT_0
-#define T3_SND_DATA_IN_MODE_ENABLE BIT_1
-#define T3_SND_DATA_IN_MODE_STATS_OFLW_ATTN_ENABLE BIT_2
-
- T3_32BIT_REGISTER Status;
-#define T3_SND_DATA_IN_STATUS_STATS_OFLW_ATTN BIT_2
-
- T3_32BIT_REGISTER StatsCtrl;
-#define T3_SND_DATA_IN_STATS_CTRL_ENABLE BIT_0
-#define T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE BIT_1
-#define T3_SND_DATA_IN_STATS_CTRL_CLEAR BIT_2
-#define T3_SND_DATA_IN_STATS_CTRL_FLUSH BIT_3
-#define T3_SND_DATA_IN_STATS_CTRL_FORCE_ZERO BIT_4
-
- T3_32BIT_REGISTER StatsEnableMask;
- T3_32BIT_REGISTER StatsIncMask;
-
- LM_UINT8 Reserved[108];
-
- T3_32BIT_REGISTER ClassOfServCnt[16];
- T3_32BIT_REGISTER DmaReadQFullCnt;
- T3_32BIT_REGISTER DmaPriorityReadQFullCnt;
- T3_32BIT_REGISTER SdcQFullCnt;
-
- T3_32BIT_REGISTER NicRingSetSendProdIdxCnt;
- T3_32BIT_REGISTER StatusUpdatedCnt;
- T3_32BIT_REGISTER InterruptsCnt;
- T3_32BIT_REGISTER AvoidInterruptsCnt;
- T3_32BIT_REGISTER SendThresholdHitCnt;
-
- /* Unused space. */
- LM_UINT8 Unused[800];
-} T3_SEND_DATA_INITIATOR, *PT3_SEND_DATA_INITIATOR;
-
-/******************************************************************************/
-/* Send data completion control registers. */
-/******************************************************************************/
-
-typedef struct {
- T3_32BIT_REGISTER Mode;
-#define SND_DATA_COMP_MODE_RESET BIT_0
-#define SND_DATA_COMP_MODE_ENABLE BIT_1
-
- /* Unused space. */
- LM_UINT8 Unused[1020];
-} T3_SEND_DATA_COMPLETION, *PT3_SEND_DATA_COMPLETION;
-
-/******************************************************************************/
-/* Send BD Ring Selector Control Registers. */
-/******************************************************************************/
-
-typedef struct {
- T3_32BIT_REGISTER Mode;
-#define SND_BD_SEL_MODE_RESET BIT_0
-#define SND_BD_SEL_MODE_ENABLE BIT_1
-#define SND_BD_SEL_MODE_ATTN_ENABLE BIT_2
-
- T3_32BIT_REGISTER Status;
-#define SND_BD_SEL_STATUS_ERROR_ATTN BIT_2
-
- T3_32BIT_REGISTER HwDiag;
-
- /* Unused space. */
- LM_UINT8 Unused1[52];
-
- /* Send BD Ring Selector Local NIC Send BD Consumer Index. */
- T3_32BIT_REGISTER NicSendBdSelConIdx[16];
-
- /* Unused space. */
- LM_UINT8 Unused2[896];
-} T3_SEND_BD_SELECTOR, *PT3_SEND_BD_SELECTOR;
-
-/******************************************************************************/
-/* Send BD initiator control registers. */
-/******************************************************************************/
-
-typedef struct {
- T3_32BIT_REGISTER Mode;
-#define SND_BD_IN_MODE_RESET BIT_0
-#define SND_BD_IN_MODE_ENABLE BIT_1
-#define SND_BD_IN_MODE_ATTN_ENABLE BIT_2
-
- T3_32BIT_REGISTER Status;
-#define SND_BD_IN_STATUS_ERROR_ATTN BIT_2
-
- /* Send BD initiator local NIC send BD producer index. */
- T3_32BIT_REGISTER NicSendBdInProdIdx[16];
-
- /* Unused space. */
- LM_UINT8 Unused2[952];
-} T3_SEND_BD_INITIATOR, *PT3_SEND_BD_INITIATOR;
-
-/******************************************************************************/
-/* Send BD Completion Control. */
-/******************************************************************************/
-
-typedef struct {
- T3_32BIT_REGISTER Mode;
-#define SND_BD_COMP_MODE_RESET BIT_0
-#define SND_BD_COMP_MODE_ENABLE BIT_1
-#define SND_BD_COMP_MODE_ATTN_ENABLE BIT_2
-
- /* Unused space. */
- LM_UINT8 Unused2[1020];
-} T3_SEND_BD_COMPLETION, *PT3_SEND_BD_COMPLETION;
-
-/******************************************************************************/
-/* Receive list placement control registers. */
-/******************************************************************************/
-
-typedef struct {
- /* Mode. */
- T3_32BIT_REGISTER Mode;
-#define RCV_LIST_PLMT_MODE_RESET BIT_0
-#define RCV_LIST_PLMT_MODE_ENABLE BIT_1
-#define RCV_LIST_PLMT_MODE_CLASS0_ATTN_ENABLE BIT_2
-#define RCV_LIST_PLMT_MODE_MAPPING_OOR_ATTN_ENABLE BIT_3
-#define RCV_LIST_PLMT_MODE_STATS_OFLOW_ATTN_ENABLE BIT_4
-
- /* Status. */
- T3_32BIT_REGISTER Status;
-#define RCV_LIST_PLMT_STATUS_CLASS0_ATTN BIT_2
-#define RCV_LIST_PLMT_STATUS_MAPPING_ATTN BIT_3
-#define RCV_LIST_PLMT_STATUS_STATS_OFLOW_ATTN BIT_4
-
- /* Receive selector list lock register. */
- T3_32BIT_REGISTER Lock;
-#define RCV_LIST_SEL_LOCK_REQUEST_MASK 0xffff
-#define RCV_LIST_SEL_LOCK_GRANT_MASK 0xffff0000
-
- /* Selector non-empty bits. */
- T3_32BIT_REGISTER NonEmptyBits;
-#define RCV_LIST_SEL_NON_EMPTY_MASK 0xffff
-
- /* Receive list placement configuration register. */
- T3_32BIT_REGISTER Config;
-
- /* Receive List Placement statistics Control. */
- T3_32BIT_REGISTER StatsCtrl;
-#define RCV_LIST_STATS_ENABLE BIT_0
-#define RCV_LIST_STATS_FAST_UPDATE BIT_1
-
- /* Receive List Placement statistics Enable Mask. */
- T3_32BIT_REGISTER StatsEnableMask;
-
- /* Receive List Placement statistics Increment Mask. */
- T3_32BIT_REGISTER StatsIncMask;
-
- /* Unused space. */
- LM_UINT8 Unused1[224];
-
- struct {
- T3_32BIT_REGISTER Head;
- T3_32BIT_REGISTER Tail;
- T3_32BIT_REGISTER Count;
-
- /* Unused space. */
- LM_UINT8 Unused[4];
- } RcvSelectorList[16];
-
- /* Local statistics counter. */
- T3_32BIT_REGISTER ClassOfServCnt[16];
-
- T3_32BIT_REGISTER DropDueToFilterCnt;
- T3_32BIT_REGISTER DmaWriteQFullCnt;
- T3_32BIT_REGISTER DmaHighPriorityWriteQFullCnt;
- T3_32BIT_REGISTER NoMoreReceiveBdCnt;
- T3_32BIT_REGISTER IfInDiscardsCnt;
- T3_32BIT_REGISTER IfInErrorsCnt;
- T3_32BIT_REGISTER RcvThresholdHitCnt;
-
- /* Another unused space. */
- LM_UINT8 Unused2[420];
-} T3_RCV_LIST_PLACEMENT, *PT3_RCV_LIST_PLACEMENT;
-
-/******************************************************************************/
-/* Receive Data and Receive BD Initiator Control. */
-/******************************************************************************/
-
-typedef struct {
- /* Mode. */
- T3_32BIT_REGISTER Mode;
-#define RCV_DATA_BD_IN_MODE_RESET BIT_0
-#define RCV_DATA_BD_IN_MODE_ENABLE BIT_1
-#define RCV_DATA_BD_IN_MODE_JUMBO_BD_NEEDED BIT_2
-#define RCV_DATA_BD_IN_MODE_FRAME_TOO_BIG BIT_3
-#define RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE BIT_4
-
- /* Status. */
- T3_32BIT_REGISTER Status;
-#define RCV_DATA_BD_IN_STATUS_JUMBO_BD_NEEDED BIT_2
-#define RCV_DATA_BD_IN_STATUS_FRAME_TOO_BIG BIT_3
-#define RCV_DATA_BD_IN_STATUS_INVALID_RING_SIZE BIT_4
-
- /* Split frame minium size. */
- T3_32BIT_REGISTER SplitFrameMinSize;
-
- /* Unused space. */
- LM_UINT8 Unused1[0x2440 - 0x240c];
-
- /* Receive RCBs. */
- T3_RCB JumboRcvRcb;
- T3_RCB StdRcvRcb;
- T3_RCB MiniRcvRcb;
-
- /* Receive Data and Receive BD Ring Initiator Local NIC Receive */
- /* BD Consumber Index. */
- T3_32BIT_REGISTER NicJumboConIdx;
- T3_32BIT_REGISTER NicStdConIdx;
- T3_32BIT_REGISTER NicMiniConIdx;
-
- /* Unused space. */
- LM_UINT8 Unused2[4];
-
- /* Receive Data and Receive BD Initiator Local Receive Return ProdIdx. */
- T3_32BIT_REGISTER RcvDataBdProdIdx[16];
-
- /* Receive Data and Receive BD Initiator Hardware Diagnostic. */
- T3_32BIT_REGISTER HwDiag;
-
- /* Unused space. */
- LM_UINT8 Unused3[828];
-} T3_RCV_DATA_BD_INITIATOR, *PT3_RCV_DATA_BD_INITIATOR;
-
-/******************************************************************************/
-/* Receive Data Completion Control Registes. */
-/******************************************************************************/
-
-typedef struct {
- T3_32BIT_REGISTER Mode;
-#define RCV_DATA_COMP_MODE_RESET BIT_0
-#define RCV_DATA_COMP_MODE_ENABLE BIT_1
-#define RCV_DATA_COMP_MODE_ATTN_ENABLE BIT_2
-
- /* Unused spaced. */
- LM_UINT8 Unused[1020];
-} T3_RCV_DATA_COMPLETION, *PT3_RCV_DATA_COMPLETION;
-
-/******************************************************************************/
-/* Receive BD Initiator Control. */
-/******************************************************************************/
-
-typedef struct {
- T3_32BIT_REGISTER Mode;
-#define RCV_BD_IN_MODE_RESET BIT_0
-#define RCV_BD_IN_MODE_ENABLE BIT_1
-#define RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE BIT_2
-
- T3_32BIT_REGISTER Status;
-#define RCV_BD_IN_STATUS_BD_IN_DIABLED_RCB_ATTN BIT_2
-
- T3_32BIT_REGISTER NicJumboRcvProdIdx;
- T3_32BIT_REGISTER NicStdRcvProdIdx;
- T3_32BIT_REGISTER NicMiniRcvProdIdx;
-
- T3_32BIT_REGISTER MiniRcvThreshold;
- T3_32BIT_REGISTER StdRcvThreshold;
- T3_32BIT_REGISTER JumboRcvThreshold;
-
- /* Unused space. */
- LM_UINT8 Unused[992];
-} T3_RCV_BD_INITIATOR, *PT3_RCV_BD_INITIATOR;
-
-/******************************************************************************/
-/* Receive BD Completion Control Registers. */
-/******************************************************************************/
-
-typedef struct {
- T3_32BIT_REGISTER Mode;
-#define RCV_BD_COMP_MODE_RESET BIT_0
-#define RCV_BD_COMP_MODE_ENABLE BIT_1
-#define RCV_BD_COMP_MODE_ATTN_ENABLE BIT_2
-
- T3_32BIT_REGISTER Status;
-#define RCV_BD_COMP_STATUS_ERROR_ATTN BIT_2
-
- T3_32BIT_REGISTER NicJumboRcvBdProdIdx;
- T3_32BIT_REGISTER NicStdRcvBdProdIdx;
- T3_32BIT_REGISTER NicMiniRcvBdProdIdx;
-
- /* Unused space. */
- LM_UINT8 Unused[1004];
-} T3_RCV_BD_COMPLETION, *PT3_RCV_BD_COMPLETION;
-
-/******************************************************************************/
-/* Receive list selector control register. */
-/******************************************************************************/
-
-typedef struct {
- T3_32BIT_REGISTER Mode;
-#define RCV_LIST_SEL_MODE_RESET BIT_0
-#define RCV_LIST_SEL_MODE_ENABLE BIT_1
-#define RCV_LIST_SEL_MODE_ATTN_ENABLE BIT_2
-
- T3_32BIT_REGISTER Status;
-#define RCV_LIST_SEL_STATUS_ERROR_ATTN BIT_2
-
- /* Unused space. */
- LM_UINT8 Unused[1016];
-} T3_RCV_LIST_SELECTOR, *PT3_RCV_LIST_SELECTOR;
-
-/******************************************************************************/
-/* Mbuf cluster free registers. */
-/******************************************************************************/
-
-typedef struct {
- T3_32BIT_REGISTER Mode;
-#define MBUF_CLUSTER_FREE_MODE_RESET BIT_0
-#define MBUF_CLUSTER_FREE_MODE_ENABLE BIT_1
-
- T3_32BIT_REGISTER Status;
-
- /* Unused space. */
- LM_UINT8 Unused[1016];
-} T3_MBUF_CLUSTER_FREE, *PT3_MBUF_CLUSTER_FREE;
-
-/******************************************************************************/
-/* Host coalescing control registers. */
-/******************************************************************************/
-
-typedef struct {
- /* Mode. */
- T3_32BIT_REGISTER Mode;
-#define HOST_COALESCE_RESET BIT_0
-#define HOST_COALESCE_ENABLE BIT_1
-#define HOST_COALESCE_ATTN BIT_2
-#define HOST_COALESCE_NOW BIT_3
-#define HOST_COALESCE_FULL_STATUS_MODE BIT_NONE
-#define HOST_COALESCE_64_BYTE_STATUS_MODE BIT_7
-#define HOST_COALESCE_32_BYTE_STATUS_MODE BIT_8
-#define HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT BIT_9
-#define HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT BIT_10
-#define HOST_COALESCE_NO_INT_ON_COALESCE_NOW_MODE BIT_11
-#define HOST_COALESCE_NO_INT_ON_FORCE_DMAD_MODE BIT_12
-
- /* Status. */
- T3_32BIT_REGISTER Status;
-#define HOST_COALESCE_ERROR_ATTN BIT_2
-
- /* Receive coalescing ticks. */
- T3_32BIT_REGISTER RxCoalescingTicks;
-
- /* Send coalescing ticks. */
- T3_32BIT_REGISTER TxCoalescingTicks;
-
- /* Receive max coalesced frames. */
- T3_32BIT_REGISTER RxMaxCoalescedFrames;
-
- /* Send max coalesced frames. */
- T3_32BIT_REGISTER TxMaxCoalescedFrames;
-
- /* Receive coalescing ticks during interrupt. */
- T3_32BIT_REGISTER RxCoalescedTickDuringInt;
-
- /* Send coalescing ticks during interrupt. */
- T3_32BIT_REGISTER TxCoalescedTickDuringInt;
-
- /* Receive max coalesced frames during interrupt. */
- T3_32BIT_REGISTER RxMaxCoalescedFramesDuringInt;
-
- /* Send max coalesced frames during interrupt. */
- T3_32BIT_REGISTER TxMaxCoalescedFramesDuringInt;
-
- /* Statistics tick. */
- T3_32BIT_REGISTER StatsCoalescingTicks;
-
- /* Unused space. */
- LM_UINT8 Unused2[4];
-
- /* Statistics host address. */
- T3_64BIT_REGISTER StatsBlkHostAddr;
-
- /* Status block host address. */
- T3_64BIT_REGISTER StatusBlkHostAddr;
-
- /* Statistics NIC address. */
- T3_32BIT_REGISTER StatsBlkNicAddr;
-
- /* Statust block NIC address. */
- T3_32BIT_REGISTER StatusBlkNicAddr;
-
- /* Flow attention registers. */
- T3_32BIT_REGISTER FlowAttn;
-
- /* Unused space. */
- LM_UINT8 Unused3[4];
-
- T3_32BIT_REGISTER NicJumboRcvBdConIdx;
- T3_32BIT_REGISTER NicStdRcvBdConIdx;
- T3_32BIT_REGISTER NicMiniRcvBdConIdx;
-
- /* Unused space. */
- LM_UINT8 Unused4[36];
-
- T3_32BIT_REGISTER NicRetProdIdx[16];
- T3_32BIT_REGISTER NicSndBdConIdx[16];
-
- /* Unused space. */
- LM_UINT8 Unused5[768];
-} T3_HOST_COALESCING, *PT3_HOST_COALESCING;
-
-/******************************************************************************/
-/* Memory arbiter registers. */
-/******************************************************************************/
-
-typedef struct {
- T3_32BIT_REGISTER Mode;
-#define T3_MEM_ARBITER_MODE_RESET BIT_0
-#define T3_MEM_ARBITER_MODE_ENABLE BIT_1
-
- T3_32BIT_REGISTER Status;
-
- T3_32BIT_REGISTER ArbTrapAddrLow;
- T3_32BIT_REGISTER ArbTrapAddrHigh;
-
- /* Unused space. */
- LM_UINT8 Unused[1008];
-} T3_MEM_ARBITER, *PT3_MEM_ARBITER;
-
-/******************************************************************************/
-/* Buffer manager control register. */
-/******************************************************************************/
-
-typedef struct {
- T3_32BIT_REGISTER Mode;
-#define BUFMGR_MODE_RESET BIT_0
-#define BUFMGR_MODE_ENABLE BIT_1
-#define BUFMGR_MODE_ATTN_ENABLE BIT_2
-#define BUFMGR_MODE_BM_TEST BIT_3
-#define BUFMGR_MODE_MBUF_LOW_ATTN_ENABLE BIT_4
-
- T3_32BIT_REGISTER Status;
-#define BUFMGR_STATUS_ERROR BIT_2
-#define BUFMGR_STATUS_MBUF_LOW BIT_4
-
- T3_32BIT_REGISTER MbufPoolAddr;
- T3_32BIT_REGISTER MbufPoolSize;
- T3_32BIT_REGISTER MbufReadDmaLowWaterMark;
- T3_32BIT_REGISTER MbufMacRxLowWaterMark;
- T3_32BIT_REGISTER MbufHighWaterMark;
-
- T3_32BIT_REGISTER RxCpuMbufAllocReq;
-#define BUFMGR_MBUF_ALLOC_BIT BIT_31
- T3_32BIT_REGISTER RxCpuMbufAllocResp;
- T3_32BIT_REGISTER TxCpuMbufAllocReq;
- T3_32BIT_REGISTER TxCpuMbufAllocResp;
-
- T3_32BIT_REGISTER DmaDescPoolAddr;
- T3_32BIT_REGISTER DmaDescPoolSize;
- T3_32BIT_REGISTER DmaLowWaterMark;
- T3_32BIT_REGISTER DmaHighWaterMark;
-
- T3_32BIT_REGISTER RxCpuDmaAllocReq;
- T3_32BIT_REGISTER RxCpuDmaAllocResp;
- T3_32BIT_REGISTER TxCpuDmaAllocReq;
- T3_32BIT_REGISTER TxCpuDmaAllocResp;
-
- T3_32BIT_REGISTER Hwdiag[3];
-
- /* Unused space. */
- LM_UINT8 Unused[936];
-} T3_BUFFER_MANAGER, *PT3_BUFFER_MANAGER;
-
-/******************************************************************************/
-/* Read DMA control registers. */
-/******************************************************************************/
-
-typedef struct {
- T3_32BIT_REGISTER Mode;
-#define DMA_READ_MODE_RESET BIT_0
-#define DMA_READ_MODE_ENABLE BIT_1
-#define DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2
-#define DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3
-#define DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4
-#define DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5
-#define DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6
-#define DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7
-#define DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8
-#define DMA_READ_MODE_LONG_READ_ATTN_ENABLE BIT_9
-#define DMA_READ_MODE_SPLIT_ENABLE BIT_11
-#define DMA_READ_MODE_SPLIT_RESET BIT_12
-
- T3_32BIT_REGISTER Status;
-#define DMA_READ_STATUS_TARGET_ABORT_ATTN BIT_2
-#define DMA_READ_STATUS_MASTER_ABORT_ATTN BIT_3
-#define DMA_READ_STATUS_PARITY_ERROR_ATTN BIT_4
-#define DMA_READ_STATUS_ADDR_OVERFLOW_ATTN BIT_5
-#define DMA_READ_STATUS_FIFO_OVERRUN_ATTN BIT_6
-#define DMA_READ_STATUS_FIFO_UNDERRUN_ATTN BIT_7
-#define DMA_READ_STATUS_FIFO_OVERREAD_ATTN BIT_8
-#define DMA_READ_STATUS_LONG_READ_ATTN BIT_9
-
- /* Unused space. */
- LM_UINT8 Unused[1016];
-} T3_DMA_READ, *PT3_DMA_READ;
-
-typedef union T3_CPU {
- struct {
- T3_32BIT_REGISTER mode;
-#define CPU_MODE_HALT BIT_10
-#define CPU_MODE_RESET BIT_0
- T3_32BIT_REGISTER state;
- T3_32BIT_REGISTER EventMask;
- T3_32BIT_REGISTER reserved1[4];
- T3_32BIT_REGISTER PC;
- T3_32BIT_REGISTER Instruction;
- T3_32BIT_REGISTER SpadUnderflow;
- T3_32BIT_REGISTER WatchdogClear;
- T3_32BIT_REGISTER WatchdogVector;
- T3_32BIT_REGISTER WatchdogSavedPC;
- T3_32BIT_REGISTER HardwareBp;
- T3_32BIT_REGISTER reserved2[3];
- T3_32BIT_REGISTER WatchdogSavedState;
- T3_32BIT_REGISTER LastBrchAddr;
- T3_32BIT_REGISTER SpadUnderflowSet;
- T3_32BIT_REGISTER reserved3[(0x200 - 0x50) / 4];
- T3_32BIT_REGISTER Regs[32];
- T3_32BIT_REGISTER reserved4[(0x400 - 0x280) / 4];
- } reg;
-} T3_CPU, *PT3_CPU;
-
-/******************************************************************************/
-/* Write DMA control registers. */
-/******************************************************************************/
-
-typedef struct {
- T3_32BIT_REGISTER Mode;
-#define DMA_WRITE_MODE_RESET BIT_0
-#define DMA_WRITE_MODE_ENABLE BIT_1
-#define DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2
-#define DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3
-#define DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4
-#define DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5
-#define DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6
-#define DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7
-#define DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8
-#define DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE BIT_9
-
- T3_32BIT_REGISTER Status;
-#define DMA_WRITE_STATUS_TARGET_ABORT_ATTN BIT_2
-#define DMA_WRITE_STATUS_MASTER_ABORT_ATTN BIT_3
-#define DMA_WRITE_STATUS_PARITY_ERROR_ATTN BIT_4
-#define DMA_WRITE_STATUS_ADDR_OVERFLOW_ATTN BIT_5
-#define DMA_WRITE_STATUS_FIFO_OVERRUN_ATTN BIT_6
-#define DMA_WRITE_STATUS_FIFO_UNDERRUN_ATTN BIT_7
-#define DMA_WRITE_STATUS_FIFO_OVERREAD_ATTN BIT_8
-#define DMA_WRITE_STATUS_LONG_READ_ATTN BIT_9
-
- /* Unused space. */
- LM_UINT8 Unused[1016];
-} T3_DMA_WRITE, *PT3_DMA_WRITE;
-
-/******************************************************************************/
-/* Mailbox registers. */
-/******************************************************************************/
-
-typedef struct {
- /* Interrupt mailbox registers. */
- T3_64BIT_REGISTER Interrupt[4];
-
- /* General mailbox registers. */
- T3_64BIT_REGISTER General[8];
-
- /* Reload statistics mailbox. */
- T3_64BIT_REGISTER ReloadStat;
-
- /* Receive BD ring producer index registers. */
- T3_64BIT_REGISTER RcvStdProdIdx;
- T3_64BIT_REGISTER RcvJumboProdIdx;
- T3_64BIT_REGISTER RcvMiniProdIdx;
-
- /* Receive return ring consumer index registers. */
- T3_64BIT_REGISTER RcvRetConIdx[16];
-
- /* Send BD ring host producer index registers. */
- T3_64BIT_REGISTER SendHostProdIdx[16];
-
- /* Send BD ring nic producer index registers. */
- T3_64BIT_REGISTER SendNicProdIdx[16];
-} T3_MAILBOX, *PT3_MAILBOX;
-
-typedef struct {
- T3_MAILBOX Mailbox;
-
- /* Priority mailbox registers. */
- T3_32BIT_REGISTER HighPriorityEventVector;
- T3_32BIT_REGISTER HighPriorityEventMask;
- T3_32BIT_REGISTER LowPriorityEventVector;
- T3_32BIT_REGISTER LowPriorityEventMask;
-
- /* Unused space. */
- LM_UINT8 Unused[496];
-} T3_GRC_MAILBOX, *PT3_GRC_MAILBOX;
-
-/******************************************************************************/
-/* Flow through queues. */
-/******************************************************************************/
-
-typedef struct {
- T3_32BIT_REGISTER Reset;
-
- LM_UINT8 Unused[12];
-
- T3_32BIT_REGISTER DmaNormalReadFtqCtrl;
- T3_32BIT_REGISTER DmaNormalReadFtqFullCnt;
- T3_32BIT_REGISTER DmaNormalReadFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER DmaNormalReadFtqFifoWritePeek;
-
- T3_32BIT_REGISTER DmaHighReadFtqCtrl;
- T3_32BIT_REGISTER DmaHighReadFtqFullCnt;
- T3_32BIT_REGISTER DmaHighReadFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER DmaHighReadFtqFifoWritePeek;
-
- T3_32BIT_REGISTER DmaCompDiscardFtqCtrl;
- T3_32BIT_REGISTER DmaCompDiscardFtqFullCnt;
- T3_32BIT_REGISTER DmaCompDiscardFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER DmaCompDiscardFtqFifoWritePeek;
-
- T3_32BIT_REGISTER SendBdCompFtqCtrl;
- T3_32BIT_REGISTER SendBdCompFtqFullCnt;
- T3_32BIT_REGISTER SendBdCompFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER SendBdCompFtqFifoWritePeek;
-
- T3_32BIT_REGISTER SendDataInitiatorFtqCtrl;
- T3_32BIT_REGISTER SendDataInitiatorFtqFullCnt;
- T3_32BIT_REGISTER SendDataInitiatorFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER SendDataInitiatorFtqFifoWritePeek;
-
- T3_32BIT_REGISTER DmaNormalWriteFtqCtrl;
- T3_32BIT_REGISTER DmaNormalWriteFtqFullCnt;
- T3_32BIT_REGISTER DmaNormalWriteFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER DmaNormalWriteFtqFifoWritePeek;
-
- T3_32BIT_REGISTER DmaHighWriteFtqCtrl;
- T3_32BIT_REGISTER DmaHighWriteFtqFullCnt;
- T3_32BIT_REGISTER DmaHighWriteFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER DmaHighWriteFtqFifoWritePeek;
-
- T3_32BIT_REGISTER SwType1FtqCtrl;
- T3_32BIT_REGISTER SwType1FtqFullCnt;
- T3_32BIT_REGISTER SwType1FtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER SwType1FtqFifoWritePeek;
-
- T3_32BIT_REGISTER SendDataCompFtqCtrl;
- T3_32BIT_REGISTER SendDataCompFtqFullCnt;
- T3_32BIT_REGISTER SendDataCompFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER SendDataCompFtqFifoWritePeek;
-
- T3_32BIT_REGISTER HostCoalesceFtqCtrl;
- T3_32BIT_REGISTER HostCoalesceFtqFullCnt;
- T3_32BIT_REGISTER HostCoalesceFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER HostCoalesceFtqFifoWritePeek;
-
- T3_32BIT_REGISTER MacTxFtqCtrl;
- T3_32BIT_REGISTER MacTxFtqFullCnt;
- T3_32BIT_REGISTER MacTxFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER MacTxFtqFifoWritePeek;
-
- T3_32BIT_REGISTER MbufClustFreeFtqCtrl;
- T3_32BIT_REGISTER MbufClustFreeFtqFullCnt;
- T3_32BIT_REGISTER MbufClustFreeFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER MbufClustFreeFtqFifoWritePeek;
-
- T3_32BIT_REGISTER RcvBdCompFtqCtrl;
- T3_32BIT_REGISTER RcvBdCompFtqFullCnt;
- T3_32BIT_REGISTER RcvBdCompFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER RcvBdCompFtqFifoWritePeek;
-
- T3_32BIT_REGISTER RcvListPlmtFtqCtrl;
- T3_32BIT_REGISTER RcvListPlmtFtqFullCnt;
- T3_32BIT_REGISTER RcvListPlmtFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER RcvListPlmtFtqFifoWritePeek;
-
- T3_32BIT_REGISTER RcvDataBdInitiatorFtqCtrl;
- T3_32BIT_REGISTER RcvDataBdInitiatorFtqFullCnt;
- T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoWritePeek;
-
- T3_32BIT_REGISTER RcvDataCompFtqCtrl;
- T3_32BIT_REGISTER RcvDataCompFtqFullCnt;
- T3_32BIT_REGISTER RcvDataCompFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER RcvDataCompFtqFifoWritePeek;
-
- T3_32BIT_REGISTER SwType2FtqCtrl;
- T3_32BIT_REGISTER SwType2FtqFullCnt;
- T3_32BIT_REGISTER SwType2FtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER SwType2FtqFifoWritePeek;
-
- /* Unused space. */
- LM_UINT8 Unused2[736];
-} T3_FTQ, *PT3_FTQ;
-
-/******************************************************************************/
-/* Message signaled interrupt registers. */
-/******************************************************************************/
-
-typedef struct {
- T3_32BIT_REGISTER Mode;
-#define MSI_MODE_RESET BIT_0
-#define MSI_MODE_ENABLE BIT_1
- T3_32BIT_REGISTER Status;
-
- T3_32BIT_REGISTER MsiFifoAccess;
-
- /* Unused space. */
- LM_UINT8 Unused[1012];
-} T3_MSG_SIGNALED_INT, *PT3_MSG_SIGNALED_INT;
-
-/******************************************************************************/
-/* DMA Completion registes. */
-/******************************************************************************/
-
-typedef struct {
- T3_32BIT_REGISTER Mode;
-#define DMA_COMP_MODE_RESET BIT_0
-#define DMA_COMP_MODE_ENABLE BIT_1
-
- /* Unused space. */
- LM_UINT8 Unused[1020];
-} T3_DMA_COMPLETION, *PT3_DMA_COMPLETION;
-
-/******************************************************************************/
-/* GRC registers. */
-/******************************************************************************/
-
-typedef struct {
- /* Mode control register. */
- T3_32BIT_REGISTER Mode;
-#define GRC_MODE_UPDATE_ON_COALESCING BIT_0
-#define GRC_MODE_BYTE_SWAP_NON_FRAME_DATA BIT_1
-#define GRC_MODE_WORD_SWAP_NON_FRAME_DATA BIT_2
-#define GRC_MODE_BYTE_SWAP_DATA BIT_4
-#define GRC_MODE_WORD_SWAP_DATA BIT_5
-#define GRC_MODE_SPLIT_HEADER_MODE BIT_8
-#define GRC_MODE_NO_FRAME_CRACKING BIT_9
-#define GRC_MODE_INCLUDE_CRC BIT_10
-#define GRC_MODE_ALLOW_BAD_FRAMES BIT_11
-#define GRC_MODE_NO_INTERRUPT_ON_SENDS BIT_13
-#define GRC_MODE_NO_INTERRUPT_ON_RECEIVE BIT_14
-#define GRC_MODE_FORCE_32BIT_PCI_BUS_MODE BIT_15
-#define GRC_MODE_HOST_STACK_UP BIT_16
-#define GRC_MODE_HOST_SEND_BDS BIT_17
-#define GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM BIT_20
-#define GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM BIT_23
-#define GRC_MODE_INT_ON_TX_CPU_ATTN BIT_24
-#define GRC_MODE_INT_ON_RX_CPU_ATTN BIT_25
-#define GRC_MODE_INT_ON_MAC_ATTN BIT_26
-#define GRC_MODE_INT_ON_DMA_ATTN BIT_27
-#define GRC_MODE_INT_ON_FLOW_ATTN BIT_28
-#define GRC_MODE_4X_NIC_BASED_SEND_RINGS BIT_29
-#define GRC_MODE_MULTICAST_FRAME_ENABLE BIT_30
-
- /* Misc configuration register. */
- T3_32BIT_REGISTER MiscCfg;
-#define GRC_MISC_CFG_CORE_CLOCK_RESET BIT_0
-#define GRC_MISC_PRESCALAR_TIMER_MASK 0xfe
-#define GRC_MISC_BD_ID_MASK 0x0001e000
-#define GRC_MISC_BD_ID_5700 0x0001e000
-#define GRC_MISC_BD_ID_5701 0x00000000
-#define GRC_MISC_BD_ID_5703 0x00000000
-#define GRC_MISC_BD_ID_5703S 0x00002000
-#define GRC_MISC_BD_ID_5702FE 0x00004000
-#define GRC_MISC_BD_ID_5704 0x00000000
-#define GRC_MISC_BD_ID_5704CIOBE 0x00004000
-
- /* Miscellaneous local control register. */
- T3_32BIT_REGISTER LocalCtrl;
-#define GRC_MISC_LOCAL_CTRL_INT_ACTIVE BIT_0
-#define GRC_MISC_LOCAL_CTRL_CLEAR_INT BIT_1
-#define GRC_MISC_LOCAL_CTRL_SET_INT BIT_2
-#define GRC_MISC_LOCAL_CTRL_INT_ON_ATTN BIT_3
-#define GRC_MISC_LOCAL_CTRL_GPIO_INPUT0 BIT_8
-#define GRC_MISC_LOCAL_CTRL_GPIO_INPUT1 BIT_9
-#define GRC_MISC_LOCAL_CTRL_GPIO_INPUT2 BIT_10
-#define GRC_MISC_LOCAL_CTRL_GPIO_OE0 BIT_11
-#define GRC_MISC_LOCAL_CTRL_GPIO_OE1 BIT_12
-#define GRC_MISC_LOCAL_CTRL_GPIO_OE2 BIT_13
-#define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 BIT_14
-#define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 BIT_15
-#define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2 BIT_16
-#define GRC_MISC_LOCAL_CTRL_ENABLE_EXT_MEMORY BIT_17
-#define GRC_MISC_LOCAL_CTRL_BANK_SELECT BIT_21
-#define GRC_MISC_LOCAL_CTRL_SSRAM_TYPE BIT_22
-
-#define GRC_MISC_MEMSIZE_256K 0
-#define GRC_MISC_MEMSIZE_512K (1 << 18)
-#define GRC_MISC_MEMSIZE_1024K (2 << 18)
-#define GRC_MISC_MEMSIZE_2048K (3 << 18)
-#define GRC_MISC_MEMSIZE_4096K (4 << 18)
-#define GRC_MISC_MEMSIZE_8192K (5 << 18)
-#define GRC_MISC_MEMSIZE_16M (6 << 18)
-#define GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM BIT_24
-
- T3_32BIT_REGISTER Timer;
-
- T3_32BIT_REGISTER RxCpuEvent;
- T3_32BIT_REGISTER RxTimerRef;
- T3_32BIT_REGISTER RxCpuSemaphore;
- T3_32BIT_REGISTER RemoteRxCpuAttn;
-
- T3_32BIT_REGISTER TxCpuEvent;
- T3_32BIT_REGISTER TxTimerRef;
- T3_32BIT_REGISTER TxCpuSemaphore;
- T3_32BIT_REGISTER RemoteTxCpuAttn;
-
- T3_64BIT_REGISTER MemoryPowerUp;
-
- T3_32BIT_REGISTER EepromAddr;
-#define SEEPROM_ADDR_WRITE 0
-#define SEEPROM_ADDR_READ (1 << 31)
-#define SEEPROM_ADDR_RW_MASK 0x80000000
-#define SEEPROM_ADDR_COMPLETE (1 << 30)
-#define SEEPROM_ADDR_FSM_RESET (1 << 29)
-#define SEEPROM_ADDR_DEV_ID(x) (x << 26)
-#define SEEPROM_ADDR_DEV_ID_MASK 0x1c000000
-#define SEEPROM_ADDR_START (1 << 25)
-#define SEEPROM_ADDR_CLK_PERD(x) (x << 16)
-#define SEEPROM_ADDR_ADDRESS(x) (x & 0xfffc)
-#define SEEPROM_ADDR_ADDRESS_MASK 0x0000ffff
-
-#define SEEPROM_CLOCK_PERIOD 60
-#define SEEPROM_CHIP_SIZE (64 * 1024)
-
- T3_32BIT_REGISTER EepromData;
- T3_32BIT_REGISTER EepromCtrl;
-
- T3_32BIT_REGISTER MdiCtrl;
- T3_32BIT_REGISTER SepromDelay;
-
- /* Unused space. */
- LM_UINT8 Unused[948];
-} T3_GRC, *PT3_GRC;
-
-/******************************************************************************/
-/* NVRAM control registers. */
-/******************************************************************************/
-
-typedef struct {
- T3_32BIT_REGISTER Cmd;
-#define NVRAM_CMD_RESET BIT_0
-#define NVRAM_CMD_DONE BIT_3
-#define NVRAM_CMD_DO_IT BIT_4
-#define NVRAM_CMD_WR BIT_5
-#define NVRAM_CMD_RD BIT_NONE
-#define NVRAM_CMD_ERASE BIT_6
-#define NVRAM_CMD_FIRST BIT_7
-#define NVRAM_CMD_LAST BIT_8
-
- T3_32BIT_REGISTER Status;
- T3_32BIT_REGISTER WriteData;
-
- T3_32BIT_REGISTER Addr;
-#define NVRAM_ADDRESS_MASK 0xffffff
-
- T3_32BIT_REGISTER ReadData;
-
- /* Flash config 1 register. */
- T3_32BIT_REGISTER Config1;
-#define FLASH_INTERFACE_ENABLE BIT_0
-#define FLASH_SSRAM_BUFFERRED_MODE BIT_1
-#define FLASH_PASS_THRU_MODE BIT_2
-#define FLASH_BIT_BANG_MODE BIT_3
-#define FLASH_COMPAT_BYPASS BIT_31
-
- /* Buffered flash (Atmel: AT45DB011B) specific information */
-#define BUFFERED_FLASH_PAGE_POS 9
-#define BUFFERED_FLASH_BYTE_ADDR_MASK ((1<<BUFFERED_FLASH_PAGE_POS) - 1)
-#define BUFFERED_FLASH_PAGE_SIZE 264
-#define BUFFERED_FLASH_PHY_PAGE_SIZE 512
-
- T3_32BIT_REGISTER Config2;
- T3_32BIT_REGISTER Config3;
- T3_32BIT_REGISTER SwArb;
-#define SW_ARB_REQ_SET0 BIT_0
-#define SW_ARB_REQ_SET1 BIT_1
-#define SW_ARB_REQ_SET2 BIT_2
-#define SW_ARB_REQ_SET3 BIT_3
-#define SW_ARB_REQ_CLR0 BIT_4
-#define SW_ARB_REQ_CLR1 BIT_5
-#define SW_ARB_REQ_CLR2 BIT_6
-#define SW_ARB_REQ_CLR3 BIT_7
-#define SW_ARB_GNT0 BIT_8
-#define SW_ARB_GNT1 BIT_9
-#define SW_ARB_GNT2 BIT_10
-#define SW_ARB_GNT3 BIT_11
-#define SW_ARB_REQ0 BIT_12
-#define SW_ARB_REQ1 BIT_13
-#define SW_ARB_REQ2 BIT_14
-#define SW_ARB_REQ3 BIT_15
-
- /* Unused space. */
- LM_UINT8 Unused[988];
-} T3_NVRAM, *PT3_NVRAM;
-
-/******************************************************************************/
-/* NIC's internal memory. */
-/******************************************************************************/
-
-typedef struct {
- /* Page zero for the internal CPUs. */
- LM_UINT8 PageZero[0x100]; /* 0x0000 */
-
- /* Send RCBs. */
- T3_RCB SendRcb[16]; /* 0x0100 */
-
- /* Receive Return RCBs. */
- T3_RCB RcvRetRcb[16]; /* 0x0200 */
-
- /* Statistics block. */
- T3_STATS_BLOCK StatsBlk; /* 0x0300 */
-
- /* Status block. */
- T3_STATUS_BLOCK StatusBlk; /* 0x0b00 */
-
- /* Reserved for software. */
- LM_UINT8 Reserved[1200]; /* 0x0b50 */
-
- /* Unmapped region. */
- LM_UINT8 Unmapped[4096]; /* 0x1000 */
-
- /* DMA descriptors. */
- LM_UINT8 DmaDesc[8192]; /* 0x2000 */
-
- /* Buffer descriptors. */
- LM_UINT8 BufferDesc[16384]; /* 0x4000 */
-} T3_FIRST_32K_SRAM, *PT3_FIRST_32K_SRAM;
-
-/******************************************************************************/
-/* Memory layout. */
-/******************************************************************************/
-
-typedef struct {
- /* PCI configuration registers. */
- T3_PCI_CONFIGURATION PciCfg;
-
- /* Unused. */
- LM_UINT8 Unused1[0x100]; /* 0x0100 */
-
- /* Mailbox . */
- T3_MAILBOX Mailbox; /* 0x0200 */
-
- /* MAC control registers. */
- T3_MAC_CONTROL MacCtrl; /* 0x0400 */
-
- /* Send data initiator control registers. */
- T3_SEND_DATA_INITIATOR SndDataIn; /* 0x0c00 */
-
- /* Send data completion Control registers. */
- T3_SEND_DATA_COMPLETION SndDataComp; /* 0x1000 */
-
- /* Send BD ring selector. */
- T3_SEND_BD_SELECTOR SndBdSel; /* 0x1400 */
-
- /* Send BD initiator control registers. */
- T3_SEND_BD_INITIATOR SndBdIn; /* 0x1800 */
-
- /* Send BD completion control registers. */
- T3_SEND_BD_COMPLETION SndBdComp; /* 0x1c00 */
-
- /* Receive list placement control registers. */
- T3_RCV_LIST_PLACEMENT RcvListPlmt; /* 0x2000 */
-
- /* Receive Data and Receive BD Initiator Control. */
- T3_RCV_DATA_BD_INITIATOR RcvDataBdIn; /* 0x2400 */
-
- /* Receive Data Completion Control */
- T3_RCV_DATA_COMPLETION RcvDataComp; /* 0x2800 */
-
- /* Receive BD Initiator Control Registers. */
- T3_RCV_BD_INITIATOR RcvBdIn; /* 0x2c00 */
-
- /* Receive BD Completion Control Registers. */
- T3_RCV_BD_COMPLETION RcvBdComp; /* 0x3000 */
-
- /* Receive list selector control registers. */
- T3_RCV_LIST_SELECTOR RcvListSel; /* 0x3400 */
-
- /* Mbuf cluster free registers. */
- T3_MBUF_CLUSTER_FREE MbufClusterFree; /* 0x3800 */
-
- /* Host coalescing control registers. */
- T3_HOST_COALESCING HostCoalesce; /* 0x3c00 */
-
- /* Memory arbiter control registers. */
- T3_MEM_ARBITER MemArbiter; /* 0x4000 */
-
- /* Buffer manger control registers. */
- T3_BUFFER_MANAGER BufMgr; /* 0x4400 */
-
- /* Read DMA control registers. */
- T3_DMA_READ DmaRead; /* 0x4800 */
-
- /* Write DMA control registers. */
- T3_DMA_WRITE DmaWrite; /* 0x4c00 */
-
- T3_CPU rxCpu; /* 0x5000 */
- T3_CPU txCpu; /* 0x5400 */
-
- /* Mailboxes. */
- T3_GRC_MAILBOX GrcMailbox; /* 0x5800 */
-
- /* Flow Through queues. */
- T3_FTQ Ftq; /* 0x5c00 */
-
- /* Message signaled interrupt registes. */
- T3_MSG_SIGNALED_INT Msi; /* 0x6000 */
-
- /* DMA completion registers. */
- T3_DMA_COMPLETION DmaComp; /* 0x6400 */
-
- /* GRC registers. */
- T3_GRC Grc; /* 0x6800 */
-
- /* Unused space. */
- LM_UINT8 Unused2[1024]; /* 0x6c00 */
-
- /* NVRAM registers. */
- T3_NVRAM Nvram; /* 0x7000 */
-
- /* Unused space. */
- LM_UINT8 Unused3[3072]; /* 0x7400 */
-
- /* The 32k memory window into the NIC's */
- /* internal memory. The memory window is */
- /* controlled by the Memory Window Base */
- /* Address register. This register is located */
- /* in the PCI configuration space. */
- union { /* 0x8000 */
- T3_FIRST_32K_SRAM First32k;
-
- /* Use the memory window base address register to determine the */
- /* MBUF segment. */
- LM_UINT32 Mbuf[32768 / 4];
- LM_UINT32 MemBlock32K[32768 / 4];
- } uIntMem;
-} T3_STD_MEM_MAP, *PT3_STD_MEM_MAP;
-
-/******************************************************************************/
-/* Adapter info. */
-/******************************************************************************/
-
-typedef struct {
- LM_UINT16 Svid;
- LM_UINT16 Ssid;
- LM_UINT32 PhyId;
- LM_UINT32 Serdes; /* 0 = copper PHY, 1 = Serdes */
-} LM_ADAPTER_INFO, *PLM_ADAPTER_INFO;
-
-/******************************************************************************/
-/* Packet queues. */
-/******************************************************************************/
-
-DECLARE_QUEUE_TYPE (LM_RX_PACKET_Q, MAX_RX_PACKET_DESC_COUNT);
-DECLARE_QUEUE_TYPE (LM_TX_PACKET_Q, MAX_TX_PACKET_DESC_COUNT);
-
-/******************************************************************************/
-/* Tx counters. */
-/******************************************************************************/
-
-typedef struct {
- LM_COUNTER TxPacketGoodCnt;
- LM_COUNTER TxBytesGoodCnt;
- LM_COUNTER TxPacketAbortedCnt;
- LM_COUNTER NoSendBdLeftCnt;
- LM_COUNTER NoMapRegisterLeftCnt;
- LM_COUNTER TooManyFragmentsCnt;
- LM_COUNTER NoTxPacketDescCnt;
-} LM_TX_COUNTERS, *PLM_TX_COUNTERS;
-
-/******************************************************************************/
-/* Rx counters. */
-/******************************************************************************/
-
-typedef struct {
- LM_COUNTER RxPacketGoodCnt;
- LM_COUNTER RxBytesGoodCnt;
- LM_COUNTER RxPacketErrCnt;
- LM_COUNTER RxErrCrcCnt;
- LM_COUNTER RxErrCollCnt;
- LM_COUNTER RxErrLinkLostCnt;
- LM_COUNTER RxErrPhyDecodeCnt;
- LM_COUNTER RxErrOddNibbleCnt;
- LM_COUNTER RxErrMacAbortCnt;
- LM_COUNTER RxErrShortPacketCnt;
- LM_COUNTER RxErrNoResourceCnt;
- LM_COUNTER RxErrLargePacketCnt;
-} LM_RX_COUNTERS, *PLM_RX_COUNTERS;
-
-/******************************************************************************/
-/* Receive producer rings. */
-/******************************************************************************/
-
-typedef enum {
- T3_UNKNOWN_RCV_PROD_RING = 0,
- T3_STD_RCV_PROD_RING = 1,
- T3_MINI_RCV_PROD_RING = 2,
- T3_JUMBO_RCV_PROD_RING = 3
-} T3_RCV_PROD_RING, *PT3_RCV_PROD_RING;
-
-/******************************************************************************/
-/* Packet descriptor. */
-/******************************************************************************/
-
-#define LM_PACKET_SIGNATURE_TX 0x6861766b
-#define LM_PACKET_SIGNATURE_RX 0x6b766168
-
-typedef struct _LM_PACKET {
- /* Set in LM. */
- LM_STATUS PacketStatus;
-
- /* Set in LM for Rx, in UM for Tx. */
- LM_UINT32 PacketSize;
-
- LM_UINT16 Flags;
-
- LM_UINT16 VlanTag;
-
- union {
- /* Send info. */
- struct {
- /* Set up by UM. */
- LM_UINT32 FragCount;
-
- } Tx;
-
- /* Receive info. */
- struct {
- /* This descriptor belongs to either Std, Mini, or Jumbo ring. */
- T3_RCV_PROD_RING RcvProdRing;
-
- /* Receive buffer size */
- LM_UINT32 RxBufferSize;
-
- /* Checksum information. */
- LM_UINT16 IpChecksum;
- LM_UINT16 TcpUdpChecksum;
-
- } Rx;
- } u;
-} LM_PACKET;
-
-/******************************************************************************/
-/* Tigon3 device block. */
-/******************************************************************************/
-
-typedef struct _LM_DEVICE_BLOCK {
- int index; /* Device ID */
- /* Memory view. */
- PT3_STD_MEM_MAP pMemView;
-
- /* Base address of the block of memory in which the LM_PACKET descriptors */
- /* are allocated from. */
- PLM_VOID pPacketDescBase;
-
- LM_UINT32 MiscHostCtrl;
- LM_UINT32 GrcLocalCtrl;
- LM_UINT32 DmaReadWriteCtrl;
- LM_UINT32 PciState;
-
- /* Rx info */
- LM_UINT32 RxStdDescCnt;
- LM_UINT32 RxStdQueuedCnt;
- LM_UINT32 RxStdProdIdx;
-
- PT3_RCV_BD pRxStdBdVirt;
- LM_PHYSICAL_ADDRESS RxStdBdPhy;
-
- LM_UINT32 RxPacketDescCnt;
- LM_RX_PACKET_Q RxPacketFreeQ;
- LM_RX_PACKET_Q RxPacketReceivedQ;
-
- /* Receive info. */
- PT3_RCV_BD pRcvRetBdVirt;
- LM_PHYSICAL_ADDRESS RcvRetBdPhy;
- LM_UINT32 RcvRetConIdx;
-
-#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- LM_UINT32 RxJumboDescCnt;
- LM_UINT32 RxJumboBufferSize;
- LM_UINT32 RxJumboQueuedCnt;
-
- LM_UINT32 RxJumboProdIdx;
-
- PT3_RCV_BD pRxJumboBdVirt;
- LM_PHYSICAL_ADDRESS RxJumboBdPhy;
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
-
- /* These values are used by the upper module to inform the protocol */
- /* of the maximum transmit/receive packet size. */
- LM_UINT32 TxMtu; /* Does not include CRC. */
- LM_UINT32 RxMtu; /* Does not include CRC. */
-
- /* We need to shadow the EMAC, Rx, Tx mode registers. With B0 silicon, */
- /* we may have problems reading any MAC registers in 10mb mode. */
- LM_UINT32 MacMode;
- LM_UINT32 RxMode;
- LM_UINT32 TxMode;
-
- /* MiMode register. */
- LM_UINT32 MiMode;
-
- /* Host coalesce mode register. */
- LM_UINT32 CoalesceMode;
-
- /* Send info. */
- LM_UINT32 TxPacketDescCnt;
-
- /* Tx info. */
- LM_TX_PACKET_Q TxPacketFreeQ;
- LM_TX_PACKET_Q TxPacketActiveQ;
- LM_TX_PACKET_Q TxPacketXmittedQ;
-
- /* Pointers to SendBd. */
- PT3_SND_BD pSendBdVirt;
- LM_PHYSICAL_ADDRESS SendBdPhy; /* Only valid for Host based Send BD. */
-
- /* Send producer and consumer indices. */
- LM_UINT32 SendProdIdx;
- LM_UINT32 SendConIdx;
-
- /* Number of BD left. */
- atomic_t SendBdLeft;
-
- T3_SND_BD ShadowSendBd[T3_SEND_RCB_ENTRY_COUNT];
-
- /* Counters. */
- LM_RX_COUNTERS RxCounters;
- LM_TX_COUNTERS TxCounters;
-
- /* Host coalescing parameters. */
- LM_UINT32 RxCoalescingTicks;
- LM_UINT32 TxCoalescingTicks;
- LM_UINT32 RxMaxCoalescedFrames;
- LM_UINT32 TxMaxCoalescedFrames;
- LM_UINT32 StatsCoalescingTicks;
- LM_UINT32 RxCoalescingTicksDuringInt;
- LM_UINT32 TxCoalescingTicksDuringInt;
- LM_UINT32 RxMaxCoalescedFramesDuringInt;
- LM_UINT32 TxMaxCoalescedFramesDuringInt;
-
- /* DMA water marks. */
- LM_UINT32 DmaMbufLowMark;
- LM_UINT32 RxMacMbufLowMark;
- LM_UINT32 MbufHighMark;
-
- /* Status block. */
- PT3_STATUS_BLOCK pStatusBlkVirt;
- LM_PHYSICAL_ADDRESS StatusBlkPhy;
-
- /* Statistics block. */
- PT3_STATS_BLOCK pStatsBlkVirt;
- LM_PHYSICAL_ADDRESS StatsBlkPhy;
-
- /* Current receive mask. */
- LM_UINT32 ReceiveMask;
-
- /* Task offload capabilities. */
- LM_TASK_OFFLOAD TaskOffloadCap;
-
- /* Task offload selected. */
- LM_TASK_OFFLOAD TaskToOffload;
-
- /* Wake up capability. */
- LM_WAKE_UP_MODE WakeUpModeCap;
-
- /* Wake up capability. */
- LM_WAKE_UP_MODE WakeUpMode;
-
- /* Flow control. */
- LM_FLOW_CONTROL FlowControlCap;
- LM_FLOW_CONTROL FlowControl;
-
- /* Enable or disable PCI MWI. */
- LM_UINT32 EnableMWI;
-
- /* Enable 5701 tagged status mode. */
- LM_UINT32 UseTaggedStatus;
-
- /* NIC will not compute the pseudo header checksum. The driver or OS */
- /* must seed the checksum field with the pseudo checksum. */
- LM_UINT32 NoTxPseudoHdrChksum;
-
- /* The receive checksum in the BD does not include the pseudo checksum. */
- /* The OS or the driver must calculate the pseudo checksum and add it to */
- /* the checksum in the BD. */
- LM_UINT32 NoRxPseudoHdrChksum;
-
- /* Current node address. */
- LM_UINT8 NodeAddress[8];
-
- /* The adapter's node address. */
- LM_UINT8 PermanentNodeAddress[8];
-
- /* Adapter info. */
- LM_UINT16 BusNum;
- LM_UINT8 DevNum;
- LM_UINT8 FunctNum;
- LM_UINT16 PciVendorId;
- LM_UINT16 PciDeviceId;
- LM_UINT32 BondId;
- LM_UINT8 Irq;
- LM_UINT8 IntPin;
- LM_UINT8 CacheLineSize;
- LM_UINT8 PciRevId;
-#if PCIX_TARGET_WORKAROUND
- LM_UINT32 EnablePciXFix;
-#endif
- LM_UINT32 UndiFix; /* new, jimmy */
- LM_UINT32 PciCommandStatusWords;
- LM_UINT32 ChipRevId;
- LM_UINT16 SubsystemVendorId;
- LM_UINT16 SubsystemId;
-#if 0 /* Jimmy, deleted in new driver */
- LM_UINT32 MemBaseLow;
- LM_UINT32 MemBaseHigh;
- LM_UINT32 MemBaseSize;
-#endif
- PLM_UINT8 pMappedMemBase;
-
- /* Saved PCI configuration registers for restoring after a reset. */
- LM_UINT32 SavedCacheLineReg;
-
- /* Phy info. */
- LM_UINT32 PhyAddr;
- LM_UINT32 PhyId;
-
- /* Requested phy settings. */
- LM_REQUESTED_MEDIA_TYPE RequestedMediaType;
-
- /* Disable auto-negotiation. */
- LM_UINT32 DisableAutoNeg;
-
- /* Ways for the MAC to get link change interrupt. */
- LM_UINT32 PhyIntMode;
-#define T3_PHY_INT_MODE_AUTO 0
-#define T3_PHY_INT_MODE_MI_INTERRUPT 1
-#define T3_PHY_INT_MODE_LINK_READY 2
-#define T3_PHY_INT_MODE_AUTO_POLLING 3
-
- /* Ways to determine link change status. */
- LM_UINT32 LinkChngMode;
-#define T3_LINK_CHNG_MODE_AUTO 0
-#define T3_LINK_CHNG_MODE_USE_STATUS_REG 1
-#define T3_LINK_CHNG_MODE_USE_STATUS_BLOCK 2
-
- /* LED mode. */
- LM_UINT32 LedMode;
-
-#define LED_MODE_AUTO 0
-
- /* 5700/01 LED mode. */
-#define LED_MODE_THREE_LINK 1
-#define LED_MODE_LINK10 2
-
- /* 5703/02/04 LED mode. */
-#define LED_MODE_OPEN_DRAIN 1
-#define LED_MODE_OUTPUT 2
-
- /* WOL Speed */
- LM_UINT32 WolSpeed;
-#define WOL_SPEED_10MB 1
-#define WOL_SPEED_100MB 2
-
- /* Reset the PHY on initialization. */
- LM_UINT32 ResetPhyOnInit;
-
- LM_UINT32 RestoreOnWakeUp;
- LM_REQUESTED_MEDIA_TYPE WakeUpRequestedMediaType;
- LM_UINT32 WakeUpDisableAutoNeg;
-
- /* Current phy settings. */
- LM_MEDIA_TYPE MediaType;
- LM_LINE_SPEED LineSpeed;
- LM_LINE_SPEED OldLineSpeed;
- LM_DUPLEX_MODE DuplexMode;
- LM_STATUS LinkStatus;
- LM_UINT32 advertising; /* Jimmy, new! */
- LM_UINT32 advertising1000; /* Jimmy, new! */
-
- /* Multicast address list. */
- LM_UINT32 McEntryCount;
- LM_UINT8 McTable[LM_MAX_MC_TABLE_SIZE][LM_MC_ENTRY_SIZE];
-
- /* Use NIC or Host based send BD. */
- LM_UINT32 NicSendBd;
-
- /* Athlon fix. */
- LM_UINT32 DelayPciGrant;
-
- /* Enable OneDmaAtOnce */
- LM_UINT32 OneDmaAtOnce;
-
- /* Split Mode flags, Jimmy new */
- LM_UINT32 SplitModeEnable;
- LM_UINT32 SplitModeMaxReq;
-
- /* Init flag. */
- LM_BOOL InitDone;
-
- /* Shutdown flag. Set by the upper module. */
- LM_BOOL ShuttingDown;
-
- /* Flag to determine whether to call LM_QueueRxPackets or not in */
- /* LM_ResetAdapter routine. */
- LM_BOOL QueueRxPackets;
-
- LM_UINT32 MbufBase;
- LM_UINT32 MbufSize;
-
- /* TRUE if we have a SERDES PHY. */
- LM_UINT32 EnableTbi;
-
- /* Ethernet@WireSpeed. */
- LM_UINT32 EnableWireSpeed;
-
- LM_UINT32 EepromWp;
-
-#if INCLUDE_TBI_SUPPORT
- /* Autoneg state info. */
- AN_STATE_INFO AnInfo;
- LM_UINT32 PollTbiLink;
- LM_UINT32 IgnoreTbiLinkChange;
-#endif
- char PartNo[24];
- char BootCodeVer[16];
- char BusSpeedStr[24]; /* Jimmy, new! */
- LM_UINT32 PhyCrcCount;
-} LM_DEVICE_BLOCK;
-
-#define T3_REG_CPU_VIEW 0xc0000000
-
-#define T3_BLOCK_DMA_RD (1 << 0)
-#define T3_BLOCK_DMA_COMP (1 << 1)
-#define T3_BLOCK_RX_BD_INITIATOR (1 << 2)
-#define T3_BLOCK_RX_BD_COMP (1 << 3)
-#define T3_BLOCK_DMA_WR (1 << 4)
-#define T3_BLOCK_MSI_HANDLER (1 << 5)
-#define T3_BLOCK_RX_LIST_PLMT (1 << 6)
-#define T3_BLOCK_RX_LIST_SELECTOR (1 << 7)
-#define T3_BLOCK_RX_DATA_INITIATOR (1 << 8)
-#define T3_BLOCK_RX_DATA_COMP (1 << 9)
-#define T3_BLOCK_HOST_COALESING (1 << 10)
-#define T3_BLOCK_MAC_RX_ENGINE (1 << 11)
-#define T3_BLOCK_MBUF_CLUSTER_FREE (1 << 12)
-#define T3_BLOCK_SEND_BD_INITIATOR (1 << 13)
-#define T3_BLOCK_SEND_BD_COMP (1 << 14)
-#define T3_BLOCK_SEND_BD_SELECTOR (1 << 15)
-#define T3_BLOCK_SEND_DATA_INITIATOR (1 << 16)
-#define T3_BLOCK_SEND_DATA_COMP (1 << 17)
-#define T3_BLOCK_MAC_TX_ENGINE (1 << 18)
-#define T3_BLOCK_MEM_ARBITOR (1 << 19)
-#define T3_BLOCK_MBUF_MANAGER (1 << 20)
-#define T3_BLOCK_MAC_GLOBAL (1 << 21)
-
-#define LM_ENABLE 1
-#define LM_DISABLE 2
-
-#define RX_CPU_EVT_SW0 0
-#define RX_CPU_EVT_SW1 1
-#define RX_CPU_EVT_RLP 2
-#define RX_CPU_EVT_SW3 3
-#define RX_CPU_EVT_RLS 4
-#define RX_CPU_EVT_SW4 5
-#define RX_CPU_EVT_RX_BD_COMP 6
-#define RX_CPU_EVT_SW5 7
-#define RX_CPU_EVT_RDI 8
-#define RX_CPU_EVT_DMA_WR 9
-#define RX_CPU_EVT_DMA_RD 10
-#define RX_CPU_EVT_SWQ 11
-#define RX_CPU_EVT_SW6 12
-#define RX_CPU_EVT_RDC 13
-#define RX_CPU_EVT_SW7 14
-#define RX_CPU_EVT_HOST_COALES 15
-#define RX_CPU_EVT_SW8 16
-#define RX_CPU_EVT_HIGH_DMA_WR 17
-#define RX_CPU_EVT_HIGH_DMA_RD 18
-#define RX_CPU_EVT_SW9 19
-#define RX_CPU_EVT_DMA_ATTN 20
-#define RX_CPU_EVT_LOW_P_MBOX 21
-#define RX_CPU_EVT_HIGH_P_MBOX 22
-#define RX_CPU_EVT_SW10 23
-#define RX_CPU_EVT_TX_CPU_ATTN 24
-#define RX_CPU_EVT_MAC_ATTN 25
-#define RX_CPU_EVT_RX_CPU_ATTN 26
-#define RX_CPU_EVT_FLOW_ATTN 27
-#define RX_CPU_EVT_SW11 28
-#define RX_CPU_EVT_TIMER 29
-#define RX_CPU_EVT_SW12 30
-#define RX_CPU_EVT_SW13 31
-
-/* RX-CPU event */
-#define RX_CPU_EVENT_SW_EVENT0 (1 << RX_CPU_EVT_SW0)
-#define RX_CPU_EVENT_SW_EVENT1 (1 << RX_CPU_EVT_SW1)
-#define RX_CPU_EVENT_RLP (1 << RX_CPU_EVT_RLP)
-#define RX_CPU_EVENT_SW_EVENT3 (1 << RX_CPU_EVT_SW3)
-#define RX_CPU_EVENT_RLS (1 << RX_CPU_EVT_RLS)
-#define RX_CPU_EVENT_SW_EVENT4 (1 << RX_CPU_EVT_SW4)
-#define RX_CPU_EVENT_RX_BD_COMP (1 << RX_CPU_EVT_RX_BD_COMP)
-#define RX_CPU_EVENT_SW_EVENT5 (1 << RX_CPU_EVT_SW5)
-#define RX_CPU_EVENT_RDI (1 << RX_CPU_EVT_RDI)
-#define RX_CPU_EVENT_DMA_WR (1 << RX_CPU_EVT_DMA_WR)
-#define RX_CPU_EVENT_DMA_RD (1 << RX_CPU_EVT_DMA_RD)
-#define RX_CPU_EVENT_SWQ (1 << RX_CPU_EVT_SWQ)
-#define RX_CPU_EVENT_SW_EVENT6 (1 << RX_CPU_EVT_SW6)
-#define RX_CPU_EVENT_RDC (1 << RX_CPU_EVT_RDC)
-#define RX_CPU_EVENT_SW_EVENT7 (1 << RX_CPU_EVT_SW7)
-#define RX_CPU_EVENT_HOST_COALES (1 << RX_CPU_EVT_HOST_COALES)
-#define RX_CPU_EVENT_SW_EVENT8 (1 << RX_CPU_EVT_SW8)
-#define RX_CPU_EVENT_HIGH_DMA_WR (1 << RX_CPU_EVT_HIGH_DMA_WR)
-#define RX_CPU_EVENT_HIGH_DMA_RD (1 << RX_CPU_EVT_HIGH_DMA_RD)
-#define RX_CPU_EVENT_SW_EVENT9 (1 << RX_CPU_EVT_SW9)
-#define RX_CPU_EVENT_DMA_ATTN (1 << RX_CPU_EVT_DMA_ATTN)
-#define RX_CPU_EVENT_LOW_P_MBOX (1 << RX_CPU_EVT_LOW_P_MBOX)
-#define RX_CPU_EVENT_HIGH_P_MBOX (1 << RX_CPU_EVT_HIGH_P_MBOX)
-#define RX_CPU_EVENT_SW_EVENT10 (1 << RX_CPU_EVT_SW10)
-#define RX_CPU_EVENT_TX_CPU_ATTN (1 << RX_CPU_EVT_TX_CPU_ATTN)
-#define RX_CPU_EVENT_MAC_ATTN (1 << RX_CPU_EVT_MAC_ATTN)
-#define RX_CPU_EVENT_RX_CPU_ATTN (1 << RX_CPU_EVT_RX_CPU_ATTN)
-#define RX_CPU_EVENT_FLOW_ATTN (1 << RX_CPU_EVT_FLOW_ATTN)
-#define RX_CPU_EVENT_SW_EVENT11 (1 << RX_CPU_EVT_SW11)
-#define RX_CPU_EVENT_TIMER (1 << RX_CPU_EVT_TIMER)
-#define RX_CPU_EVENT_SW_EVENT12 (1 << RX_CPU_EVT_SW12)
-#define RX_CPU_EVENT_SW_EVENT13 (1 << RX_CPU_EVT_SW13)
-
-#define RX_CPU_MASK (RX_CPU_EVENT_SW_EVENT0 | \
- RX_CPU_EVENT_RLP | \
- RX_CPU_EVENT_RDI | \
- RX_CPU_EVENT_RDC)
-
-#define TX_CPU_EVT_SW0 0
-#define TX_CPU_EVT_SW1 1
-#define TX_CPU_EVT_SW2 2
-#define TX_CPU_EVT_SW3 3
-#define TX_CPU_EVT_TX_MAC 4
-#define TX_CPU_EVT_SW4 5
-#define TX_CPU_EVT_SBDC 6
-#define TX_CPU_EVT_SW5 7
-#define TX_CPU_EVT_SDI 8
-#define TX_CPU_EVT_DMA_WR 9
-#define TX_CPU_EVT_DMA_RD 10
-#define TX_CPU_EVT_SWQ 11
-#define TX_CPU_EVT_SW6 12
-#define TX_CPU_EVT_SDC 13
-#define TX_CPU_EVT_SW7 14
-#define TX_CPU_EVT_HOST_COALES 15
-#define TX_CPU_EVT_SW8 16
-#define TX_CPU_EVT_HIGH_DMA_WR 17
-#define TX_CPU_EVT_HIGH_DMA_RD 18
-#define TX_CPU_EVT_SW9 19
-#define TX_CPU_EVT_DMA_ATTN 20
-#define TX_CPU_EVT_LOW_P_MBOX 21
-#define TX_CPU_EVT_HIGH_P_MBOX 22
-#define TX_CPU_EVT_SW10 23
-#define TX_CPU_EVT_RX_CPU_ATTN 24
-#define TX_CPU_EVT_MAC_ATTN 25
-#define TX_CPU_EVT_TX_CPU_ATTN 26
-#define TX_CPU_EVT_FLOW_ATTN 27
-#define TX_CPU_EVT_SW11 28
-#define TX_CPU_EVT_TIMER 29
-#define TX_CPU_EVT_SW12 30
-#define TX_CPU_EVT_SW13 31
-
-/* TX-CPU event */
-#define TX_CPU_EVENT_SW_EVENT0 (1 << TX_CPU_EVT_SW0)
-#define TX_CPU_EVENT_SW_EVENT1 (1 << TX_CPU_EVT_SW1)
-#define TX_CPU_EVENT_SW_EVENT2 (1 << TX_CPU_EVT_SW2)
-#define TX_CPU_EVENT_SW_EVENT3 (1 << TX_CPU_EVT_SW3)
-#define TX_CPU_EVENT_TX_MAC (1 << TX_CPU_EVT_TX_MAC)
-#define TX_CPU_EVENT_SW_EVENT4 (1 << TX_CPU_EVT_SW4)
-#define TX_CPU_EVENT_SBDC (1 << TX_CPU_EVT_SBDC)
-#define TX_CPU_EVENT_SW_EVENT5 (1 << TX_CPU_EVT_SW5)
-#define TX_CPU_EVENT_SDI (1 << TX_CPU_EVT_SDI)
-#define TX_CPU_EVENT_DMA_WR (1 << TX_CPU_EVT_DMA_WR)
-#define TX_CPU_EVENT_DMA_RD (1 << TX_CPU_EVT_DMA_RD)
-#define TX_CPU_EVENT_SWQ (1 << TX_CPU_EVT_SWQ)
-#define TX_CPU_EVENT_SW_EVENT6 (1 << TX_CPU_EVT_SW6)
-#define TX_CPU_EVENT_SDC (1 << TX_CPU_EVT_SDC)
-#define TX_CPU_EVENT_SW_EVENT7 (1 << TX_CPU_EVT_SW7)
-#define TX_CPU_EVENT_HOST_COALES (1 << TX_CPU_EVT_HOST_COALES)
-#define TX_CPU_EVENT_SW_EVENT8 (1 << TX_CPU_EVT_SW8)
-#define TX_CPU_EVENT_HIGH_DMA_WR (1 << TX_CPU_EVT_HIGH_DMA_WR)
-#define TX_CPU_EVENT_HIGH_DMA_RD (1 << TX_CPU_EVT_HIGH_DMA_RD)
-#define TX_CPU_EVENT_SW_EVENT9 (1 << TX_CPU_EVT_SW9)
-#define TX_CPU_EVENT_DMA_ATTN (1 << TX_CPU_EVT_DMA_ATTN)
-#define TX_CPU_EVENT_LOW_P_MBOX (1 << TX_CPU_EVT_LOW_P_MBOX)
-#define TX_CPU_EVENT_HIGH_P_MBOX (1 << TX_CPU_EVT_HIGH_P_MBOX)
-#define TX_CPU_EVENT_SW_EVENT10 (1 << TX_CPU_EVT_SW10)
-#define TX_CPU_EVENT_RX_CPU_ATTN (1 << TX_CPU_EVT_RX_CPU_ATTN)
-#define TX_CPU_EVENT_MAC_ATTN (1 << TX_CPU_EVT_MAC_ATTN)
-#define TX_CPU_EVENT_TX_CPU_ATTN (1 << TX_CPU_EVT_TX_CPU_ATTN)
-#define TX_CPU_EVENT_FLOW_ATTN (1 << TX_CPU_EVT_FLOW_ATTN)
-#define TX_CPU_EVENT_SW_EVENT11 (1 << TX_CPU_EVT_SW11)
-#define TX_CPU_EVENT_TIMER (1 << TX_CPU_EVT_TIMER)
-#define TX_CPU_EVENT_SW_EVENT12 (1 << TX_CPU_EVT_SW12)
-#define TX_CPU_EVENT_SW_EVENT13 (1 << TX_CPU_EVT_SW13)
-
-#define TX_CPU_MASK (TX_CPU_EVENT_SW_EVENT0 | \
- TX_CPU_EVENT_SDI | \
- TX_CPU_EVENT_SDC)
-
-#define T3_FTQ_TYPE1_UNDERFLOW_BIT (1 << 29)
-#define T3_FTQ_TYPE1_PASS_BIT (1 << 30)
-#define T3_FTQ_TYPE1_SKIP_BIT (1 << 31)
-
-#define T3_FTQ_TYPE2_UNDERFLOW_BIT (1 << 13)
-#define T3_FTQ_TYPE2_PASS_BIT (1 << 14)
-#define T3_FTQ_TYPE2_SKIP_BIT (1 << 15)
-
-#define T3_QID_DMA_READ 1
-#define T3_QID_DMA_HIGH_PRI_READ 2
-#define T3_QID_DMA_COMP_DX 3
-#define T3_QID_SEND_BD_COMP 4
-#define T3_QID_SEND_DATA_INITIATOR 5
-#define T3_QID_DMA_WRITE 6
-#define T3_QID_DMA_HIGH_PRI_WRITE 7
-#define T3_QID_SW_TYPE_1 8
-#define T3_QID_SEND_DATA_COMP 9
-#define T3_QID_HOST_COALESCING 10
-#define T3_QID_MAC_TX 11
-#define T3_QID_MBUF_CLUSTER_FREE 12
-#define T3_QID_RX_BD_COMP 13
-#define T3_QID_RX_LIST_PLM 14
-#define T3_QID_RX_DATA_BD_INITIATOR 15
-#define T3_QID_RX_DATA_COMP 16
-#define T3_QID_SW_TYPE2 17
-
-LM_STATUS LM_LoadFirmware (PLM_DEVICE_BLOCK pDevice,
- PT3_FWIMG_INFO pFwImg,
- LM_UINT32 LoadCpu, LM_UINT32 StartCpu);
-
-/******************************************************************************/
-/* NIC register read/write macros. */
-/******************************************************************************/
-
-#if 0 /* Jimmy */
-/* MAC register access. */
-LM_UINT32 LM_RegRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register);
-LM_VOID LM_RegWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register,
- LM_UINT32 Value32);
-
-/* MAC memory access. */
-LM_UINT32 LM_MemRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr);
-LM_VOID LM_MemWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr,
- LM_UINT32 Value32);
-
-#if PCIX_TARGET_WORKAROUND
-
-/* use memory-mapped accesses for mailboxes and reads, UNDI accesses
- for writes to all other registers */
-#define REG_RD(pDevice, OffsetName) \
- readl(&((pDevice)->pMemView->OffsetName))
-
-#define REG_WR(pDevice, OffsetName, Value32) \
- (((OFFSETOF(T3_STD_MEM_MAP, OffsetName) >=0x200 ) && \
- (OFFSETOF(T3_STD_MEM_MAP, OffsetName) <0x400)) || \
- ((pDevice)->EnablePciXFix == FALSE)) ? \
- (void) writel(Value32, &((pDevice)->pMemView->OffsetName)) : \
- LM_RegWrInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName), Value32)
-
-#define MB_REG_RD(pDevice, OffsetName) \
- readl(&((pDevice)->pMemView->OffsetName))
-
-#define MB_REG_WR(pDevice, OffsetName, Value32) \
- writel(Value32, &((pDevice)->pMemView->OffsetName))
-
-#define REG_RD_OFFSET(pDevice, Offset) \
- readl(&((LM_UINT8 *) (pDevice)->pMemView + Offset))
-
-#define REG_WR_OFFSET(pDevice, Offset, Value32) \
- (((Offset >=0x200 ) && (Offset < 0x400)) || \
- ((pDevice)->EnablePciXFix == FALSE)) ? \
- (void) writel(Value32, ((LM_UINT8 *) (pDevice)->pMemView + Offset)) : \
- LM_RegWrInd(pDevice, Offset, Value32)
-
-#define MEM_RD(pDevice, AddrName) \
- LM_MemRdInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName))
-#define MEM_WR(pDevice, AddrName, Value32) \
- LM_MemWrInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName), Value32)
-
-#define MEM_RD_OFFSET(pDevice, Offset) \
- LM_MemRdInd(pDevice, Offset)
-#define MEM_WR_OFFSET(pDevice, Offset, Value32) \
- LM_MemWrInd(pDevice, Offset, Value32)
-
-#else /* normal target access path below */
-
-/* Register access. */
-#define REG_RD(pDevice, OffsetName) \
- readl(&((pDevice)->pMemView->OffsetName))
-#define REG_WR(pDevice, OffsetName, Value32) \
- writel(Value32, &((pDevice)->pMemView->OffsetName))
-
-#define REG_RD_OFFSET(pDevice, Offset) \
- readl(((LM_UINT8 *) (pDevice)->pMemView + Offset))
-#define REG_WR_OFFSET(pDevice, Offset, Value32) \
- writel(Value32, ((LM_UINT8 *) (pDevice)->pMemView + Offset))
-
-/* There could be problem access the memory window directly. For now, */
-/* we have to go through the PCI configuration register. */
-#define MEM_RD(pDevice, AddrName) \
- LM_MemRdInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName))
-#define MEM_WR(pDevice, AddrName, Value32) \
- LM_MemWrInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName), Value32)
-
-#define MEM_RD_OFFSET(pDevice, Offset) \
- LM_MemRdInd(pDevice, Offset)
-#define MEM_WR_OFFSET(pDevice, Offset, Value32) \
- LM_MemWrInd(pDevice, Offset, Value32)
-
-#endif /* PCIX_TARGET_WORKAROUND */
-
-#endif /* Jimmy, merging */
-
- /* Jimmy...rest of file is new stuff! */
-/******************************************************************************/
-/* NIC register read/write macros. */
-/******************************************************************************/
-
-/* MAC register access. */
-LM_UINT32 LM_RegRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register);
-LM_VOID LM_RegWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register,
- LM_UINT32 Value32);
-
-/* MAC memory access. */
-LM_UINT32 LM_MemRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr);
-LM_VOID LM_MemWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr,
- LM_UINT32 Value32);
-
-#define MB_REG_WR(pDevice, OffsetName, Value32) \
- ((pDevice)->UndiFix) ? \
- LM_RegWrInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)+0x5600, \
- Value32) : \
- (void) __raw_writel(Value32, &((pDevice)->pMemView->OffsetName))
-
-#define MB_REG_RD(pDevice, OffsetName) \
- (((pDevice)->UndiFix) ? \
- LM_RegRdInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)+0x5600) : \
- __raw_readl(&((pDevice)->pMemView->OffsetName)))
-
-#define REG_RD(pDevice, OffsetName) \
- (((pDevice)->UndiFix) ? \
- LM_RegRdInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)) : \
- __raw_readl(&((pDevice)->pMemView->OffsetName)))
-
-#if PCIX_TARGET_WORKAROUND
-
-#define REG_WR(pDevice, OffsetName, Value32) \
- ((pDevice)->EnablePciXFix == FALSE) ? \
- (void) __raw_writel(Value32, &((pDevice)->pMemView->OffsetName)) : \
- LM_RegWrInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName), Value32)
-
-#else
-
-#define REG_WR(pDevice, OffsetName, Value32) \
- __raw_writel(Value32, &((pDevice)->pMemView->OffsetName))
-
-#endif
-
-#define MEM_RD(pDevice, AddrName) \
- LM_MemRdInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName))
-#define MEM_WR(pDevice, AddrName, Value32) \
- LM_MemWrInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName), Value32)
-
-#define MEM_RD_OFFSET(pDevice, Offset) \
- LM_MemRdInd(pDevice, Offset)
-#define MEM_WR_OFFSET(pDevice, Offset, Value32) \
- LM_MemWrInd(pDevice, Offset, Value32)
-
-#endif /* TIGON3_H */
+++ /dev/null
-/******************************************************************************
- *
- * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
- * AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
- * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
- * OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
- * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
- * THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
- * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
- * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
- * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
- * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
- * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
- * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE.
- *
- * (C) Copyright 2007-2008 Michal Simek
- * Michal SIMEK <monstr@monstr.eu>
- *
- * (c) Copyright 2003 Xilinx Inc.
- * All rights reserved.
- *
- ******************************************************************************/
-
-#include <config.h>
-#include <common.h>
-#include <net.h>
-#include <asm/io.h>
-
-#include <asm/asm.h>
-
-#undef DEBUG
-
-typedef struct {
- u32 regbaseaddress; /* Base address of registers */
- u32 databaseaddress; /* Base address of data for FIFOs */
-} xpacketfifov100b;
-
-typedef struct {
- u32 baseaddress; /* Base address (of IPIF) */
- u32 isstarted; /* Device is currently started 0-no, 1-yes */
- xpacketfifov100b recvfifo; /* FIFO used to receive frames */
- xpacketfifov100b sendfifo; /* FIFO used to send frames */
-} xemac;
-
-#define XIIF_V123B_IISR_OFFSET 32UL /* IP interrupt status register */
-#define XIIF_V123B_RESET_MASK 0xAUL
-#define XIIF_V123B_RESETR_OFFSET 64UL /* reset register */
-
-/* This constant is used with the Reset Register */
-#define XPF_RESET_FIFO_MASK 0x0000000A
-#define XPF_COUNT_STATUS_REG_OFFSET 4UL
-
-/* These constants are used with the Occupancy/Vacancy Count Register. This
- * register also contains FIFO status */
-#define XPF_COUNT_MASK 0x0000FFFF
-#define XPF_DEADLOCK_MASK 0x20000000
-
-/* Offset of the MAC registers from the IPIF base address */
-#define XEM_REG_OFFSET 0x1100UL
-
-/*
- * Register offsets for the Ethernet MAC. Each register is 32 bits.
- */
-#define XEM_ECR_OFFSET (XEM_REG_OFFSET + 0x4) /* MAC Control */
-#define XEM_SAH_OFFSET (XEM_REG_OFFSET + 0xC) /* Station addr, high */
-#define XEM_SAL_OFFSET (XEM_REG_OFFSET + 0x10) /* Station addr, low */
-#define XEM_RPLR_OFFSET (XEM_REG_OFFSET + 0x1C) /* Rx packet length */
-#define XEM_TPLR_OFFSET (XEM_REG_OFFSET + 0x20) /* Tx packet length */
-#define XEM_TSR_OFFSET (XEM_REG_OFFSET + 0x24) /* Tx status */
-
-#define XEM_PFIFO_OFFSET 0x2000UL
-/* Tx registers */
-#define XEM_PFIFO_TXREG_OFFSET (XEM_PFIFO_OFFSET + 0x0)
-/* Rx registers */
-#define XEM_PFIFO_RXREG_OFFSET (XEM_PFIFO_OFFSET + 0x10)
-/* Tx keyhole */
-#define XEM_PFIFO_TXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x100)
-/* Rx keyhole */
-#define XEM_PFIFO_RXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x200)
-
-/*
- * EMAC Interrupt Registers (Status and Enable) masks. These registers are
- * part of the IPIF IP Interrupt registers
- */
-/* A mask for all transmit interrupts, used in polled mode */
-#define XEM_EIR_XMIT_ALL_MASK (XEM_EIR_XMIT_DONE_MASK |\
- XEM_EIR_XMIT_ERROR_MASK | \
- XEM_EIR_XMIT_SFIFO_EMPTY_MASK |\
- XEM_EIR_XMIT_LFIFO_FULL_MASK)
-
-/* Xmit complete */
-#define XEM_EIR_XMIT_DONE_MASK 0x00000001UL
-/* Recv complete */
-#define XEM_EIR_RECV_DONE_MASK 0x00000002UL
-/* Xmit error */
-#define XEM_EIR_XMIT_ERROR_MASK 0x00000004UL
-/* Recv error */
-#define XEM_EIR_RECV_ERROR_MASK 0x00000008UL
-/* Xmit status fifo empty */
-#define XEM_EIR_XMIT_SFIFO_EMPTY_MASK 0x00000010UL
-/* Recv length fifo empty */
-#define XEM_EIR_RECV_LFIFO_EMPTY_MASK 0x00000020UL
-/* Xmit length fifo full */
-#define XEM_EIR_XMIT_LFIFO_FULL_MASK 0x00000040UL
-/* Recv length fifo overrun */
-#define XEM_EIR_RECV_LFIFO_OVER_MASK 0x00000080UL
-/* Recv length fifo underrun */
-#define XEM_EIR_RECV_LFIFO_UNDER_MASK 0x00000100UL
-/* Xmit status fifo overrun */
-#define XEM_EIR_XMIT_SFIFO_OVER_MASK 0x00000200UL
-/* Transmit status fifo underrun */
-#define XEM_EIR_XMIT_SFIFO_UNDER_MASK 0x00000400UL
-/* Transmit length fifo overrun */
-#define XEM_EIR_XMIT_LFIFO_OVER_MASK 0x00000800UL
-/* Transmit length fifo underrun */
-#define XEM_EIR_XMIT_LFIFO_UNDER_MASK 0x00001000UL
-/* Transmit pause pkt received */
-#define XEM_EIR_XMIT_PAUSE_MASK 0x00002000UL
-
-/*
- * EMAC Control Register (ECR)
- */
-/* Full duplex mode */
-#define XEM_ECR_FULL_DUPLEX_MASK 0x80000000UL
-/* Reset transmitter */
-#define XEM_ECR_XMIT_RESET_MASK 0x40000000UL
-/* Enable transmitter */
-#define XEM_ECR_XMIT_ENABLE_MASK 0x20000000UL
-/* Reset receiver */
-#define XEM_ECR_RECV_RESET_MASK 0x10000000UL
-/* Enable receiver */
-#define XEM_ECR_RECV_ENABLE_MASK 0x08000000UL
-/* Enable PHY */
-#define XEM_ECR_PHY_ENABLE_MASK 0x04000000UL
-/* Enable xmit pad insert */
-#define XEM_ECR_XMIT_PAD_ENABLE_MASK 0x02000000UL
-/* Enable xmit FCS insert */
-#define XEM_ECR_XMIT_FCS_ENABLE_MASK 0x01000000UL
-/* Enable unicast addr */
-#define XEM_ECR_UNICAST_ENABLE_MASK 0x00020000UL
-/* Enable broadcast addr */
-#define XEM_ECR_BROAD_ENABLE_MASK 0x00008000UL
-
-/*
- * Transmit Status Register (TSR)
- */
-/* Transmit excess deferral */
-#define XEM_TSR_EXCESS_DEFERRAL_MASK 0x80000000UL
-/* Transmit late collision */
-#define XEM_TSR_LATE_COLLISION_MASK 0x01000000UL
-
-#define ENET_MAX_MTU PKTSIZE
-#define ENET_ADDR_LENGTH 6
-
-static unsigned int etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
-
-static u8 emacaddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 };
-
-static xemac emac;
-
-void eth_halt(void)
-{
- debug ("eth_halt\n");
-}
-
-int eth_init(bd_t * bis)
-{
- uchar enetaddr[6];
- u32 helpreg;
- debug ("EMAC Initialization Started\n\r");
-
- if (emac.isstarted) {
- puts("Emac is started\n");
- return 0;
- }
-
- memset (&emac, 0, sizeof (xemac));
-
- emac.baseaddress = XILINX_EMAC_BASEADDR;
-
- /* Setting up FIFOs */
- emac.recvfifo.regbaseaddress = emac.baseaddress +
- XEM_PFIFO_RXREG_OFFSET;
- emac.recvfifo.databaseaddress = emac.baseaddress +
- XEM_PFIFO_RXDATA_OFFSET;
- out_be32 (emac.recvfifo.regbaseaddress, XPF_RESET_FIFO_MASK);
-
- emac.sendfifo.regbaseaddress = emac.baseaddress +
- XEM_PFIFO_TXREG_OFFSET;
- emac.sendfifo.databaseaddress = emac.baseaddress +
- XEM_PFIFO_TXDATA_OFFSET;
- out_be32 (emac.sendfifo.regbaseaddress, XPF_RESET_FIFO_MASK);
-
- /* Reset the entire IPIF */
- out_be32 (emac.baseaddress + XIIF_V123B_RESETR_OFFSET,
- XIIF_V123B_RESET_MASK);
-
- /* Stopping EMAC for setting up MAC */
- helpreg = in_be32 (emac.baseaddress + XEM_ECR_OFFSET);
- helpreg &= ~(XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK);
- out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg);
-
- if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
- memcpy(enetaddr, emacaddr, ENET_ADDR_LENGTH);
- eth_setenv_enetaddr("ethaddr", enetaddr);
- }
-
- /* Set the device station address high and low registers */
- helpreg = (enetaddr[0] << 8) | enetaddr[1];
- out_be32 (emac.baseaddress + XEM_SAH_OFFSET, helpreg);
- helpreg = (enetaddr[2] << 24) | (enetaddr[3] << 16) |
- (enetaddr[4] << 8) | enetaddr[5];
- out_be32 (emac.baseaddress + XEM_SAL_OFFSET, helpreg);
-
- helpreg = XEM_ECR_UNICAST_ENABLE_MASK | XEM_ECR_BROAD_ENABLE_MASK |
- XEM_ECR_FULL_DUPLEX_MASK | XEM_ECR_XMIT_FCS_ENABLE_MASK |
- XEM_ECR_XMIT_PAD_ENABLE_MASK | XEM_ECR_PHY_ENABLE_MASK;
- out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg);
-
- emac.isstarted = 1;
-
- /* Enable the transmitter, and receiver */
- helpreg = in_be32 (emac.baseaddress + XEM_ECR_OFFSET);
- helpreg &= ~(XEM_ECR_XMIT_RESET_MASK | XEM_ECR_RECV_RESET_MASK);
- helpreg |= (XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK);
- out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg);
-
- printf("EMAC Initialization complete\n\r");
- return 0;
-}
-
-int eth_send(volatile void *ptr, int len)
-{
- u32 intrstatus;
- u32 xmitstatus;
- u32 fifocount;
- u32 wordcount;
- u32 extrabytecount;
- u32 *wordbuffer = (u32 *) ptr;
-
- if (len > ENET_MAX_MTU)
- len = ENET_MAX_MTU;
-
- /*
- * Check for overruns and underruns for the transmit status and length
- * FIFOs and make sure the send packet FIFO is not deadlocked.
- * Any of these conditions is bad enough that we do not want to
- * continue. The upper layer software should reset the device to resolve
- * the error.
- */
- intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET);
- if (intrstatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
- XEM_EIR_XMIT_LFIFO_OVER_MASK)) {
- debug ("Transmitting overrun error\n");
- return 0;
- } else if (intrstatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
- XEM_EIR_XMIT_LFIFO_UNDER_MASK)) {
- debug ("Transmitting underrun error\n");
- return 0;
- } else if (in_be32 (emac.sendfifo.regbaseaddress +
- XPF_COUNT_STATUS_REG_OFFSET) & XPF_DEADLOCK_MASK) {
- debug ("Transmitting fifo error\n");
- return 0;
- }
-
- /*
- * Before writing to the data FIFO, make sure the length FIFO is not
- * full. The data FIFO might not be full yet even though the length FIFO
- * is. This avoids an overrun condition on the length FIFO and keeps the
- * FIFOs in sync.
- *
- * Clear the latched LFIFO_FULL bit so next time around the most
- * current status is represented
- */
- if (intrstatus & XEM_EIR_XMIT_LFIFO_FULL_MASK) {
- out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
- intrstatus & XEM_EIR_XMIT_LFIFO_FULL_MASK);
- debug ("Fifo is full\n");
- return 0;
- }
-
- /* get the count of how many words may be inserted into the FIFO */
- fifocount = in_be32 (emac.sendfifo.regbaseaddress +
- XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK;
- wordcount = len >> 2;
- extrabytecount = len & 0x3;
-
- if (fifocount < wordcount) {
- debug ("Sending packet is larger then size of FIFO\n");
- return 0;
- }
-
- for (fifocount = 0; fifocount < wordcount; fifocount++) {
- out_be32 (emac.sendfifo.databaseaddress, wordbuffer[fifocount]);
- }
- if (extrabytecount > 0) {
- u32 lastword = 0;
- u8 *extrabytesbuffer = (u8 *) (wordbuffer + wordcount);
-
- if (extrabytecount == 1) {
- lastword = extrabytesbuffer[0] << 24;
- } else if (extrabytecount == 2) {
- lastword = extrabytesbuffer[0] << 24 |
- extrabytesbuffer[1] << 16;
- } else if (extrabytecount == 3) {
- lastword = extrabytesbuffer[0] << 24 |
- extrabytesbuffer[1] << 16 |
- extrabytesbuffer[2] << 8;
- }
- out_be32 (emac.sendfifo.databaseaddress, lastword);
- }
-
- /* Loop on the MAC's status to wait for any pause to complete */
- intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET);
- while ((intrstatus & XEM_EIR_XMIT_PAUSE_MASK) != 0) {
- intrstatus = in_be32 ((emac.baseaddress) +
- XIIF_V123B_IISR_OFFSET);
- /* Clear the pause status from the transmit status register */
- out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
- intrstatus & XEM_EIR_XMIT_PAUSE_MASK);
- }
-
- /*
- * Set the MAC's transmit packet length register to tell it to transmit
- */
- out_be32 (emac.baseaddress + XEM_TPLR_OFFSET, len);
-
- /*
- * Loop on the MAC's status to wait for the transmit to complete.
- * The transmit status is in the FIFO when the XMIT_DONE bit is set.
- */
- do {
- intrstatus = in_be32 ((emac.baseaddress) +
- XIIF_V123B_IISR_OFFSET);
- }
- while ((intrstatus & XEM_EIR_XMIT_DONE_MASK) == 0);
-
- xmitstatus = in_be32 (emac.baseaddress + XEM_TSR_OFFSET);
-
- if (intrstatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
- XEM_EIR_XMIT_LFIFO_OVER_MASK)) {
- debug ("Transmitting overrun error\n");
- return 0;
- } else if (intrstatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
- XEM_EIR_XMIT_LFIFO_UNDER_MASK)) {
- debug ("Transmitting underrun error\n");
- return 0;
- }
-
- /* Clear the interrupt status register of transmit statuses */
- out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
- intrstatus & XEM_EIR_XMIT_ALL_MASK);
-
- /*
- * Collision errors are stored in the transmit status register
- * instead of the interrupt status register
- */
- if ((xmitstatus & XEM_TSR_EXCESS_DEFERRAL_MASK) ||
- (xmitstatus & XEM_TSR_LATE_COLLISION_MASK)) {
- debug ("Transmitting collision error\n");
- return 0;
- }
- return 1;
-}
-
-int eth_rx(void)
-{
- u32 pktlength;
- u32 intrstatus;
- u32 fifocount;
- u32 wordcount;
- u32 extrabytecount;
- u32 lastword;
- u8 *extrabytesbuffer;
-
- if (in_be32 (emac.recvfifo.regbaseaddress + XPF_COUNT_STATUS_REG_OFFSET)
- & XPF_DEADLOCK_MASK) {
- out_be32 (emac.recvfifo.regbaseaddress, XPF_RESET_FIFO_MASK);
- debug ("Receiving FIFO deadlock\n");
- return 0;
- }
-
- /*
- * Get the interrupt status to know what happened (whether an error
- * occurred and/or whether frames have been received successfully).
- * When clearing the intr status register, clear only statuses that
- * pertain to receive.
- */
- intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET);
- /*
- * Before reading from the length FIFO, make sure the length FIFO is not
- * empty. We could cause an underrun error if we try to read from an
- * empty FIFO.
- */
- if (!(intrstatus & XEM_EIR_RECV_DONE_MASK)) {
- /* debug ("Receiving FIFO is empty\n"); */
- return 0;
- }
-
- /*
- * Determine, from the MAC, the length of the next packet available
- * in the data FIFO (there should be a non-zero length here)
- */
- pktlength = in_be32 (emac.baseaddress + XEM_RPLR_OFFSET);
- if (!pktlength) {
- return 0;
- }
-
- /*
- * Write the RECV_DONE bit in the status register to clear it. This bit
- * indicates the RPLR is non-empty, and we know it's set at this point.
- * We clear it so that subsequent entry into this routine will reflect
- * the current status. This is done because the non-empty bit is latched
- * in the IPIF, which means it may indicate a non-empty condition even
- * though there is something in the FIFO.
- */
- out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
- XEM_EIR_RECV_DONE_MASK);
-
- fifocount = in_be32 (emac.recvfifo.regbaseaddress +
- XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK;
-
- if ((fifocount * 4) < pktlength) {
- debug ("Receiving FIFO is smaller than packet size.\n");
- return 0;
- }
-
- wordcount = pktlength >> 2;
- extrabytecount = pktlength & 0x3;
-
- for (fifocount = 0; fifocount < wordcount; fifocount++) {
- etherrxbuff[fifocount] =
- in_be32 (emac.recvfifo.databaseaddress);
- }
-
- /*
- * if there are extra bytes to handle, read the last word from the FIFO
- * and insert the extra bytes into the buffer
- */
- if (extrabytecount > 0) {
- extrabytesbuffer = (u8 *) (etherrxbuff + wordcount);
-
- lastword = in_be32 (emac.recvfifo.databaseaddress);
-
- /*
- * one extra byte in the last word, put the byte into the next
- * location of the buffer, bytes in a word of the FIFO are
- * ordered from most significant byte to least
- */
- if (extrabytecount == 1) {
- extrabytesbuffer[0] = (u8) (lastword >> 24);
- } else if (extrabytecount == 2) {
- extrabytesbuffer[0] = (u8) (lastword >> 24);
- extrabytesbuffer[1] = (u8) (lastword >> 16);
- } else if (extrabytecount == 3) {
- extrabytesbuffer[0] = (u8) (lastword >> 24);
- extrabytesbuffer[1] = (u8) (lastword >> 16);
- extrabytesbuffer[2] = (u8) (lastword >> 8);
- }
- }
- NetReceive((uchar *)etherrxbuff, pktlength);
- return 1;
-}
+++ /dev/null
-/******************************************************************************
- *
- * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
- * AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
- * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
- * OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
- * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
- * THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
- * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
- * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
- * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
- * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
- * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
- * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE.
- *
- * (C) Copyright 2007-2008 Michal Simek
- * Michal SIMEK <monstr@monstr.eu>
- *
- * (c) Copyright 2003 Xilinx Inc.
- * All rights reserved.
- *
- ******************************************************************************/
-
-#include <common.h>
-#include <net.h>
-#include <config.h>
-#include <asm/io.h>
-
-#undef DEBUG
-
-#define ENET_MAX_MTU PKTSIZE
-#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
-#define ENET_ADDR_LENGTH 6
-
-/* EmacLite constants */
-#define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */
-#define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */
-#define XEL_TSR_OFFSET 0x07FC /* Tx status */
-#define XEL_RSR_OFFSET 0x17FC /* Rx status */
-#define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */
-
-/* Xmit complete */
-#define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
-/* Xmit interrupt enable bit */
-#define XEL_TSR_XMIT_IE_MASK 0x00000008UL
-/* Buffer is active, SW bit only */
-#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000UL
-/* Program the MAC address */
-#define XEL_TSR_PROGRAM_MASK 0x00000002UL
-/* define for programming the MAC address into the EMAC Lite */
-#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
-
-/* Transmit packet length upper byte */
-#define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
-/* Transmit packet length lower byte */
-#define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
-
-/* Recv complete */
-#define XEL_RSR_RECV_DONE_MASK 0x00000001UL
-/* Recv interrupt enable bit */
-#define XEL_RSR_RECV_IE_MASK 0x00000008UL
-
-typedef struct {
- unsigned int baseaddress; /* Base address for device (IPIF) */
- unsigned int nexttxbuffertouse; /* Next TX buffer to write to */
- unsigned int nextrxbuffertouse; /* Next RX buffer to read from */
- unsigned char deviceid; /* Unique ID of device - for future */
-} xemaclite;
-
-static xemaclite emaclite;
-
-static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
-
-/* hardcoded MAC address for the Xilinx EMAC Core when env is nowhere*/
-#ifdef CONFIG_ENV_IS_NOWHERE
-static u8 emacaddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 };
-#else
-static u8 emacaddr[ENET_ADDR_LENGTH];
-#endif
-
-void xemaclite_alignedread (u32 * srcptr, void *destptr, unsigned bytecount)
-{
- unsigned int i;
- u32 alignbuffer;
- u32 *to32ptr;
- u32 *from32ptr;
- u8 *to8ptr;
- u8 *from8ptr;
-
- from32ptr = (u32 *) srcptr;
-
- /* Word aligned buffer, no correction needed. */
- to32ptr = (u32 *) destptr;
- while (bytecount > 3) {
- *to32ptr++ = *from32ptr++;
- bytecount -= 4;
- }
- to8ptr = (u8 *) to32ptr;
-
- alignbuffer = *from32ptr++;
- from8ptr = (u8 *) & alignbuffer;
-
- for (i = 0; i < bytecount; i++) {
- *to8ptr++ = *from8ptr++;
- }
-}
-
-void xemaclite_alignedwrite (void *srcptr, u32 destptr, unsigned bytecount)
-{
- unsigned i;
- u32 alignbuffer;
- u32 *to32ptr = (u32 *) destptr;
- u32 *from32ptr;
- u8 *to8ptr;
- u8 *from8ptr;
-
- from32ptr = (u32 *) srcptr;
- while (bytecount > 3) {
-
- *to32ptr++ = *from32ptr++;
- bytecount -= 4;
- }
-
- alignbuffer = 0;
- to8ptr = (u8 *) & alignbuffer;
- from8ptr = (u8 *) from32ptr;
-
- for (i = 0; i < bytecount; i++) {
- *to8ptr++ = *from8ptr++;
- }
-
- *to32ptr++ = alignbuffer;
-}
-
-void eth_halt (void)
-{
- debug ("eth_halt\n");
-}
-
-int eth_init (bd_t * bis)
-{
- uchar enetaddr[6];
-
- debug ("EmacLite Initialization Started\n");
- memset (&emaclite, 0, sizeof (xemaclite));
- emaclite.baseaddress = XILINX_EMACLITE_BASEADDR;
-
- if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
- memcpy(enetaddr, emacaddr, ENET_ADDR_LENGTH);
- eth_setenv_enetaddr("ethaddr", enetaddr);
- }
-
-/*
- * TX - TX_PING & TX_PONG initialization
- */
- /* Restart PING TX */
- out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, 0);
- /* Copy MAC address */
- xemaclite_alignedwrite (enetaddr,
- emaclite.baseaddress, ENET_ADDR_LENGTH);
- /* Set the length */
- out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
- /* Update the MAC address in the EMAC Lite */
- out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR);
- /* Wait for EMAC Lite to finish with the MAC address update */
- while ((in_be32 (emaclite.baseaddress + XEL_TSR_OFFSET) &
- XEL_TSR_PROG_MAC_ADDR) != 0) ;
-
-#ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
- /* The same operation with PONG TX */
- out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
- xemaclite_alignedwrite (enetaddr, emaclite.baseaddress +
- XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH);
- out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
- out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
- XEL_TSR_PROG_MAC_ADDR);
- while ((in_be32 (emaclite.baseaddress + XEL_TSR_OFFSET +
- XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0) ;
-#endif
-
-/*
- * RX - RX_PING & RX_PONG initialization
- */
- /* Write out the value to flush the RX buffer */
- out_be32 (emaclite.baseaddress + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK);
-#ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
- out_be32 (emaclite.baseaddress + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET,
- XEL_RSR_RECV_IE_MASK);
-#endif
-
- debug ("EmacLite Initialization complete\n");
- return 0;
-}
-
-int xemaclite_txbufferavailable (xemaclite * instanceptr)
-{
- u32 reg;
- u32 txpingbusy;
- u32 txpongbusy;
- /*
- * Read the other buffer register
- * and determine if the other buffer is available
- */
- reg = in_be32 (instanceptr->baseaddress +
- instanceptr->nexttxbuffertouse + 0);
- txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
- XEL_TSR_XMIT_BUSY_MASK);
-
- reg = in_be32 (instanceptr->baseaddress +
- (instanceptr->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0);
- txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
- XEL_TSR_XMIT_BUSY_MASK);
-
- return (!(txpingbusy && txpongbusy));
-}
-
-int eth_send (volatile void *ptr, int len) {
-
- unsigned int reg;
- unsigned int baseaddress;
-
- unsigned maxtry = 1000;
-
- if (len > ENET_MAX_MTU)
- len = ENET_MAX_MTU;
-
- while (!xemaclite_txbufferavailable (&emaclite) && maxtry) {
- udelay (10);
- maxtry--;
- }
-
- if (!maxtry) {
- printf ("Error: Timeout waiting for ethernet TX buffer\n");
- /* Restart PING TX */
- out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, 0);
-#ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
- out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET +
- XEL_BUFFER_OFFSET, 0);
-#endif
- return 0;
- }
-
- /* Determine the expected TX buffer address */
- baseaddress = (emaclite.baseaddress + emaclite.nexttxbuffertouse);
-
- /* Determine if the expected buffer address is empty */
- reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
- if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
- && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
- & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
-
-#ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
- emaclite.nexttxbuffertouse ^= XEL_BUFFER_OFFSET;
-#endif
- debug ("Send packet from 0x%x\n", baseaddress);
- /* Write the frame to the buffer */
- xemaclite_alignedwrite ((void *) ptr, baseaddress, len);
- out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
- (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)));
- reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
- reg |= XEL_TSR_XMIT_BUSY_MASK;
- if ((reg & XEL_TSR_XMIT_IE_MASK) != 0) {
- reg |= XEL_TSR_XMIT_ACTIVE_MASK;
- }
- out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
- return 1;
- }
-#ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
- /* Switch to second buffer */
- baseaddress ^= XEL_BUFFER_OFFSET;
- /* Determine if the expected buffer address is empty */
- reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
- if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
- && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
- & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
- debug ("Send packet from 0x%x\n", baseaddress);
- /* Write the frame to the buffer */
- xemaclite_alignedwrite ((void *) ptr, baseaddress, len);
- out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
- (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)));
- reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
- reg |= XEL_TSR_XMIT_BUSY_MASK;
- if ((reg & XEL_TSR_XMIT_IE_MASK) != 0) {
- reg |= XEL_TSR_XMIT_ACTIVE_MASK;
- }
- out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
- return 1;
- }
-#endif
- puts ("Error while sending frame\n");
- return 0;
-}
-
-int eth_rx (void)
-{
- unsigned int length;
- unsigned int reg;
- unsigned int baseaddress;
-
- baseaddress = emaclite.baseaddress + emaclite.nextrxbuffertouse;
- reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
- debug ("Testing data at address 0x%x\n", baseaddress);
- if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
-#ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
- emaclite.nextrxbuffertouse ^= XEL_BUFFER_OFFSET;
-#endif
- } else {
-#ifndef CONFIG_XILINX_EMACLITE_RX_PING_PONG
- debug ("No data was available - address 0x%x\n", baseaddress);
- return 0;
-#else
- baseaddress ^= XEL_BUFFER_OFFSET;
- reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
- if ((reg & XEL_RSR_RECV_DONE_MASK) !=
- XEL_RSR_RECV_DONE_MASK) {
- debug ("No data was available - address 0x%x\n",
- baseaddress);
- return 0;
- }
-#endif
- }
- /* Get the length of the frame that arrived */
- switch(((in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC)) &
- 0xFFFF0000 ) >> 16) {
- case 0x806:
- length = 42 + 20; /* FIXME size of ARP */
- debug ("ARP Packet\n");
- break;
- case 0x800:
- length = 14 + 14 +
- (((in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0x10)) &
- 0xFFFF0000) >> 16); /* FIXME size of IP packet */
- debug ("IP Packet\n");
- break;
- default:
- debug ("Other Packet\n");
- length = ENET_MAX_MTU;
- break;
- }
-
- xemaclite_alignedread ((u32 *) (baseaddress + XEL_RXBUFF_OFFSET),
- etherrxbuff, length);
-
- /* Acknowledge the frame */
- reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
- reg &= ~XEL_RSR_RECV_DONE_MASK;
- out_be32 (baseaddress + XEL_RSR_OFFSET, reg);
-
- debug ("Packet receive from 0x%x, length %dB\n", baseaddress, length);
- NetReceive ((uchar *) etherrxbuff, length);
- return 1;
-
-}
+++ /dev/null
-/***********************************************************************
- *
- * Copyright (C) 2004 by FS Forth-Systeme GmbH.
- * All rights reserved.
- *
- * $Id: ns9750_serial.c,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
- * @Author: Markus Pietrek
- * @Descr: Serial driver for the NS9750. Only one UART is supported yet.
- * @References: [1] NS9750 Hardware Reference/December 2003
- * @TODO: Implement Character GAP Timer when chip is fixed for PLL bypass
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- ***********************************************************************/
-
-#include <common.h>
-
-#include "ns9750_bbus.h" /* for GPIOs */
-#include "ns9750_ser.h" /* for serial configuration */
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if !defined(CONFIG_CONS_INDEX)
-#error "No console index specified."
-#endif
-
-#define CONSOLE CONFIG_CONS_INDEX
-
-static unsigned int calcBitrateRegister( void );
-static unsigned int calcRxCharGapRegister( void );
-
-static char cCharsAvailable; /* Numbers of chars in unCharCache */
-static unsigned int unCharCache; /* unCharCache is only valid if
- * cCharsAvailable > 0 */
-
-/***********************************************************************
- * @Function: serial_init
- * @Return: 0
- * @Descr: configures GPIOs and UART. Requires BBUS Master Reset turned off
- ***********************************************************************/
-
-int serial_init( void )
-{
- unsigned int aunGPIOTxD[] = { 0, 8, 40, 44 };
- unsigned int aunGPIORxD[] = { 1, 9, 41, 45 };
-
- cCharsAvailable = 0;
-
- /* configure TxD and RxD pins for their special function */
- set_gpio_cfg_reg_val( aunGPIOTxD[ CONSOLE ],
- NS9750_GPIO_CFG_FUNC_0 | NS9750_GPIO_CFG_OUTPUT );
- set_gpio_cfg_reg_val( aunGPIORxD[ CONSOLE ],
- NS9750_GPIO_CFG_FUNC_0 | NS9750_GPIO_CFG_INPUT );
-
- /* configure serial engine */
- *get_ser_reg_addr_channel( NS9750_SER_CTRL_A, CONSOLE ) =
- NS9750_SER_CTRL_A_CE |
- NS9750_SER_CTRL_A_STOP |
- NS9750_SER_CTRL_A_WLS_8;
-
- serial_setbrg();
-
- *get_ser_reg_addr_channel( NS9750_SER_CTRL_B, CONSOLE ) =
- NS9750_SER_CTRL_B_RCGT;
-
- return 0;
-}
-
-/***********************************************************************
- * @Function: serial_putc
- * @Return: n/a
- * @Descr: writes one character to the FIFO. Blocks until FIFO is not full
- ***********************************************************************/
-
-void serial_putc( const char c )
-{
- if (c == '\n')
- serial_putc( '\r' );
-
- while (!(*get_ser_reg_addr_channel( NS9750_SER_STAT_A, CONSOLE) &
- NS9750_SER_STAT_A_TRDY ) ) {
- /* do nothing, wait for characters in FIFO sent */
- }
-
- *(volatile char*) get_ser_reg_addr_channel( NS9750_SER_FIFO,
- CONSOLE) = c;
-}
-
-/***********************************************************************
- * @Function: serial_puts
- * @Return: n/a
- * @Descr: writes non-zero string to the FIFO.
- ***********************************************************************/
-
-void serial_puts( const char *s )
-{
- while (*s) {
- serial_putc( *s++ );
- }
-}
-
-/***********************************************************************
- * @Function: serial_getc
- * @Return: the character read
- * @Descr: performs only 8bit accesses to the FIFO. No error handling
- ***********************************************************************/
-
-int serial_getc( void )
-{
- int i;
-
- while (!serial_tstc() ) {
- /* do nothing, wait for incoming characters */
- }
-
- /* at least one character in unCharCache */
- i = (int) (unCharCache & 0xff);
-
- unCharCache >>= 8;
- cCharsAvailable--;
-
- return i;
-}
-
-/***********************************************************************
- * @Function: serial_tstc
- * @Return: 0 if no input available, otherwise != 0
- * @Descr: checks for incoming FIFO not empty. Stores the incoming chars in
- * unCharCache and the numbers of characters in cCharsAvailable
- ***********************************************************************/
-
-int serial_tstc( void )
-{
- unsigned int unRegCache;
-
- if ( cCharsAvailable )
- return 1;
-
- unRegCache = *get_ser_reg_addr_channel( NS9750_SER_STAT_A,CONSOLE );
- if( unRegCache & NS9750_SER_STAT_A_RBC ) {
- *get_ser_reg_addr_channel( NS9750_SER_STAT_A, CONSOLE ) =
- NS9750_SER_STAT_A_RBC;
- unRegCache = *get_ser_reg_addr_channel( NS9750_SER_STAT_A,
- CONSOLE );
- }
-
- if ( unRegCache & NS9750_SER_STAT_A_RRDY ) {
- cCharsAvailable = (unRegCache & NS9750_SER_STAT_A_RXFDB_MA)>>20;
- if ( !cCharsAvailable )
- cCharsAvailable = 4;
-
- unCharCache = *get_ser_reg_addr_channel( NS9750_SER_FIFO,
- CONSOLE );
- return 1;
- }
-
- /* no chars available */
- return 0;
-}
-
-void serial_setbrg( void )
-{
- *get_ser_reg_addr_channel( NS9750_SER_BITRATE, CONSOLE ) =
- calcBitrateRegister();
- *get_ser_reg_addr_channel( NS9750_SER_RX_CHAR_TIMER, CONSOLE ) =
- calcRxCharGapRegister();
-}
-
-/***********************************************************************
- * @Function: calcBitrateRegister
- * @Return: value for the serial bitrate register
- * @Descr: register value depends on clock frequency and baudrate
- ***********************************************************************/
-
-static unsigned int calcBitrateRegister( void )
-{
- return ( NS9750_SER_BITRATE_EBIT |
- NS9750_SER_BITRATE_CLKMUX_BCLK |
- NS9750_SER_BITRATE_TMODE |
- NS9750_SER_BITRATE_TCDR_16 |
- NS9750_SER_BITRATE_RCDR_16 |
- ( ( ( ( CONFIG_SYS_CLK_FREQ / 8 ) / /* BBUS clock,[1] Fig. 38 */
- ( gd->baudrate * 16 ) ) - 1 ) &
- NS9750_SER_BITRATE_N_MA ) );
-}
-
-/***********************************************************************
- * @Function: calcRxCharGapRegister
- * @Return: value for the character gap timer register
- * @Descr: register value depends on clock frequency and baudrate. Currently 0
- * is used as there is a bug with the gap timer in PLL bypass mode.
- ***********************************************************************/
-
-static unsigned int calcRxCharGapRegister( void )
-{
- return NS9750_SER_RX_CHAR_TIMER_TRUN;
-}
+++ /dev/null
-/*-
- * Copyright (c) 2007-2008, Juniper Networks, Inc.
- * Copyright (c) 2008, Excito Elektronik i Skåne AB
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef USB_EHCI_CORE_H
-#define USB_EHCI_CORE_H
-
-extern int rootdev;
-extern struct ehci_hccr *hccr;
-extern volatile struct ehci_hcor *hcor;
-
-#endif
+++ /dev/null
-/*-
- * Copyright (c) 2007-2008, Juniper Networks, Inc.
- * Copyright (c) 2008, Excito Elektronik i Skåne AB
- * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
- *
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <asm/byteorder.h>
-#include <usb.h>
-#include <asm/io.h>
-#include <malloc.h>
-
-#include "ehci.h"
-
-int rootdev;
-struct ehci_hccr *hccr; /* R/O registers, not need for volatile */
-volatile struct ehci_hcor *hcor;
-
-static uint16_t portreset;
-static struct QH qh_list __attribute__((aligned(32)));
-
-static struct descriptor {
- struct usb_hub_descriptor hub;
- struct usb_device_descriptor device;
- struct usb_linux_config_descriptor config;
- struct usb_linux_interface_descriptor interface;
- struct usb_endpoint_descriptor endpoint;
-} __attribute__ ((packed)) descriptor = {
- {
- 0x8, /* bDescLength */
- 0x29, /* bDescriptorType: hub descriptor */
- 2, /* bNrPorts -- runtime modified */
- 0, /* wHubCharacteristics */
- 0xff, /* bPwrOn2PwrGood */
- 0, /* bHubCntrCurrent */
- {}, /* Device removable */
- {} /* at most 7 ports! XXX */
- },
- {
- 0x12, /* bLength */
- 1, /* bDescriptorType: UDESC_DEVICE */
- 0x0002, /* bcdUSB: v2.0 */
- 9, /* bDeviceClass: UDCLASS_HUB */
- 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
- 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */
- 64, /* bMaxPacketSize: 64 bytes */
- 0x0000, /* idVendor */
- 0x0000, /* idProduct */
- 0x0001, /* bcdDevice */
- 1, /* iManufacturer */
- 2, /* iProduct */
- 0, /* iSerialNumber */
- 1 /* bNumConfigurations: 1 */
- },
- {
- 0x9,
- 2, /* bDescriptorType: UDESC_CONFIG */
- cpu_to_le16(0x19),
- 1, /* bNumInterface */
- 1, /* bConfigurationValue */
- 0, /* iConfiguration */
- 0x40, /* bmAttributes: UC_SELF_POWER */
- 0 /* bMaxPower */
- },
- {
- 0x9, /* bLength */
- 4, /* bDescriptorType: UDESC_INTERFACE */
- 0, /* bInterfaceNumber */
- 0, /* bAlternateSetting */
- 1, /* bNumEndpoints */
- 9, /* bInterfaceClass: UICLASS_HUB */
- 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
- 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
- 0 /* iInterface */
- },
- {
- 0x7, /* bLength */
- 5, /* bDescriptorType: UDESC_ENDPOINT */
- 0x81, /* bEndpointAddress:
- * UE_DIR_IN | EHCI_INTR_ENDPT
- */
- 3, /* bmAttributes: UE_INTERRUPT */
- 8, 0, /* wMaxPacketSize */
- 255 /* bInterval */
- },
-};
-
-#if defined(CONFIG_EHCI_IS_TDI)
-#define ehci_is_TDI() (1)
-#else
-#define ehci_is_TDI() (0)
-#endif
-
-#if defined(CONFIG_EHCI_DCACHE)
-/*
- * Routines to handle (flush/invalidate) the dcache for the QH and qTD
- * structures and data buffers. This is needed on platforms using this
- * EHCI support with dcache enabled.
- */
-static void flush_invalidate(u32 addr, int size, int flush)
-{
- if (flush)
- flush_dcache_range(addr, addr + size);
- else
- invalidate_dcache_range(addr, addr + size);
-}
-
-static void cache_qtd(struct qTD *qtd, int flush)
-{
- u32 *ptr = (u32 *)qtd->qt_buffer[0];
- int len = (qtd->qt_token & 0x7fff0000) >> 16;
-
- flush_invalidate((u32)qtd, sizeof(struct qTD), flush);
- if (ptr && len)
- flush_invalidate((u32)ptr, len, flush);
-}
-
-
-static inline struct QH *qh_addr(struct QH *qh)
-{
- return (struct QH *)((u32)qh & 0xffffffe0);
-}
-
-static void cache_qh(struct QH *qh, int flush)
-{
- struct qTD *qtd;
- struct qTD *next;
- static struct qTD *first_qtd;
-
- /*
- * Walk the QH list and flush/invalidate all entries
- */
- while (1) {
- flush_invalidate((u32)qh_addr(qh), sizeof(struct QH), flush);
- if ((u32)qh & QH_LINK_TYPE_QH)
- break;
- qh = qh_addr(qh);
- qh = (struct QH *)qh->qh_link;
- }
- qh = qh_addr(qh);
-
- /*
- * Save first qTD pointer, needed for invalidating pass on this QH
- */
- if (flush)
- first_qtd = qtd = (struct qTD *)(*(u32 *)&qh->qh_overlay &
- 0xffffffe0);
- else
- qtd = first_qtd;
-
- /*
- * Walk the qTD list and flush/invalidate all entries
- */
- while (1) {
- if (qtd == NULL)
- break;
- cache_qtd(qtd, flush);
- next = (struct qTD *)((u32)qtd->qt_next & 0xffffffe0);
- if (next == qtd)
- break;
- qtd = next;
- }
-}
-
-static inline void ehci_flush_dcache(struct QH *qh)
-{
- cache_qh(qh, 1);
-}
-
-static inline void ehci_invalidate_dcache(struct QH *qh)
-{
- cache_qh(qh, 0);
-}
-#else /* CONFIG_EHCI_DCACHE */
-/*
- *
- */
-static inline void ehci_flush_dcache(struct QH *qh)
-{
-}
-
-static inline void ehci_invalidate_dcache(struct QH *qh)
-{
-}
-#endif /* CONFIG_EHCI_DCACHE */
-
-static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
-{
- uint32_t result;
- do {
- result = ehci_readl(ptr);
- if (result == ~(uint32_t)0)
- return -1;
- result &= mask;
- if (result == done)
- return 0;
- udelay(1);
- usec--;
- } while (usec > 0);
- return -1;
-}
-
-static void ehci_free(void *p, size_t sz)
-{
-
-}
-
-static int ehci_reset(void)
-{
- uint32_t cmd;
- uint32_t tmp;
- uint32_t *reg_ptr;
- int ret = 0;
-
- cmd = ehci_readl(&hcor->or_usbcmd);
- cmd |= CMD_RESET;
- ehci_writel(&hcor->or_usbcmd, cmd);
- ret = handshake((uint32_t *)&hcor->or_usbcmd, CMD_RESET, 0, 250 * 1000);
- if (ret < 0) {
- printf("EHCI fail to reset\n");
- goto out;
- }
-
- if (ehci_is_TDI()) {
- reg_ptr = (uint32_t *)((u8 *)hcor + USBMODE);
- tmp = ehci_readl(reg_ptr);
- tmp |= USBMODE_CM_HC;
-#if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
- tmp |= USBMODE_BE;
-#endif
- ehci_writel(reg_ptr, tmp);
- }
-out:
- return ret;
-}
-
-static void *ehci_alloc(size_t sz, size_t align)
-{
- static struct QH qh __attribute__((aligned(32)));
- static struct qTD td[3] __attribute__((aligned (32)));
- static int ntds;
- void *p;
-
- switch (sz) {
- case sizeof(struct QH):
- p = &qh;
- ntds = 0;
- break;
- case sizeof(struct qTD):
- if (ntds == 3) {
- debug("out of TDs\n");
- return NULL;
- }
- p = &td[ntds];
- ntds++;
- break;
- default:
- debug("unknown allocation size\n");
- return NULL;
- }
-
- memset(p, sz, 0);
- return p;
-}
-
-static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
-{
- uint32_t addr, delta, next;
- int idx;
-
- addr = (uint32_t) buf;
- idx = 0;
- while (idx < 5) {
- td->qt_buffer[idx] = cpu_to_hc32(addr);
- next = (addr + 4096) & ~4095;
- delta = next - addr;
- if (delta >= sz)
- break;
- sz -= delta;
- addr = next;
- idx++;
- }
-
- if (idx == 5) {
- debug("out of buffer pointers (%u bytes left)\n", sz);
- return -1;
- }
-
- return 0;
-}
-
-static int
-ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
- int length, struct devrequest *req)
-{
- struct QH *qh;
- struct qTD *td;
- volatile struct qTD *vtd;
- unsigned long ts;
- uint32_t *tdp;
- uint32_t endpt, token, usbsts;
- uint32_t c, toggle;
- uint32_t cmd;
- int ret = 0;
-
- debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
- buffer, length, req);
- if (req != NULL)
- debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
- req->request, req->request,
- req->requesttype, req->requesttype,
- le16_to_cpu(req->value), le16_to_cpu(req->value),
- le16_to_cpu(req->index));
-
- qh = ehci_alloc(sizeof(struct QH), 32);
- if (qh == NULL) {
- debug("unable to allocate QH\n");
- return -1;
- }
- qh->qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH);
- c = (usb_pipespeed(pipe) != USB_SPEED_HIGH &&
- usb_pipeendpoint(pipe) == 0) ? 1 : 0;
- endpt = (8 << 28) |
- (c << 27) |
- (usb_maxpacket(dev, pipe) << 16) |
- (0 << 15) |
- (1 << 14) |
- (usb_pipespeed(pipe) << 12) |
- (usb_pipeendpoint(pipe) << 8) |
- (0 << 7) | (usb_pipedevice(pipe) << 0);
- qh->qh_endpt1 = cpu_to_hc32(endpt);
- endpt = (1 << 30) |
- (dev->portnr << 23) |
- (dev->parent->devnum << 16) | (0 << 8) | (0 << 0);
- qh->qh_endpt2 = cpu_to_hc32(endpt);
- qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
- qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
-
- td = NULL;
- tdp = &qh->qh_overlay.qt_next;
-
- toggle =
- usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
-
- if (req != NULL) {
- td = ehci_alloc(sizeof(struct qTD), 32);
- if (td == NULL) {
- debug("unable to allocate SETUP td\n");
- goto fail;
- }
- td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
- td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
- token = (0 << 31) |
- (sizeof(*req) << 16) |
- (0 << 15) | (0 << 12) | (3 << 10) | (2 << 8) | (0x80 << 0);
- td->qt_token = cpu_to_hc32(token);
- if (ehci_td_buffer(td, req, sizeof(*req)) != 0) {
- debug("unable construct SETUP td\n");
- ehci_free(td, sizeof(*td));
- goto fail;
- }
- *tdp = cpu_to_hc32((uint32_t) td);
- tdp = &td->qt_next;
- toggle = 1;
- }
-
- if (length > 0 || req == NULL) {
- td = ehci_alloc(sizeof(struct qTD), 32);
- if (td == NULL) {
- debug("unable to allocate DATA td\n");
- goto fail;
- }
- td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
- td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
- token = (toggle << 31) |
- (length << 16) |
- ((req == NULL ? 1 : 0) << 15) |
- (0 << 12) |
- (3 << 10) |
- ((usb_pipein(pipe) ? 1 : 0) << 8) | (0x80 << 0);
- td->qt_token = cpu_to_hc32(token);
- if (ehci_td_buffer(td, buffer, length) != 0) {
- debug("unable construct DATA td\n");
- ehci_free(td, sizeof(*td));
- goto fail;
- }
- *tdp = cpu_to_hc32((uint32_t) td);
- tdp = &td->qt_next;
- }
-
- if (req != NULL) {
- td = ehci_alloc(sizeof(struct qTD), 32);
- if (td == NULL) {
- debug("unable to allocate ACK td\n");
- goto fail;
- }
- td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
- td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
- token = (toggle << 31) |
- (0 << 16) |
- (1 << 15) |
- (0 << 12) |
- (3 << 10) |
- ((usb_pipein(pipe) ? 0 : 1) << 8) | (0x80 << 0);
- td->qt_token = cpu_to_hc32(token);
- *tdp = cpu_to_hc32((uint32_t) td);
- tdp = &td->qt_next;
- }
-
- qh_list.qh_link = cpu_to_hc32((uint32_t) qh | QH_LINK_TYPE_QH);
-
- /* Flush dcache */
- ehci_flush_dcache(&qh_list);
-
- usbsts = ehci_readl(&hcor->or_usbsts);
- ehci_writel(&hcor->or_usbsts, (usbsts & 0x3f));
-
- /* Enable async. schedule. */
- cmd = ehci_readl(&hcor->or_usbcmd);
- cmd |= CMD_ASE;
- ehci_writel(&hcor->or_usbcmd, cmd);
-
- ret = handshake((uint32_t *)&hcor->or_usbsts, STD_ASS, STD_ASS,
- 100 * 1000);
- if (ret < 0) {
- printf("EHCI fail timeout STD_ASS set\n");
- goto fail;
- }
-
- /* Wait for TDs to be processed. */
- ts = get_timer(0);
- vtd = td;
- do {
- /* Invalidate dcache */
- ehci_invalidate_dcache(&qh_list);
- token = hc32_to_cpu(vtd->qt_token);
- if (!(token & 0x80))
- break;
- } while (get_timer(ts) < CONFIG_SYS_HZ);
-
- /* Disable async schedule. */
- cmd = ehci_readl(&hcor->or_usbcmd);
- cmd &= ~CMD_ASE;
- ehci_writel(&hcor->or_usbcmd, cmd);
-
- ret = handshake((uint32_t *)&hcor->or_usbsts, STD_ASS, 0,
- 100 * 1000);
- if (ret < 0) {
- printf("EHCI fail timeout STD_ASS reset\n");
- goto fail;
- }
-
- qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH);
-
- token = hc32_to_cpu(qh->qh_overlay.qt_token);
- if (!(token & 0x80)) {
- debug("TOKEN=%#x\n", token);
- switch (token & 0xfc) {
- case 0:
- toggle = token >> 31;
- usb_settoggle(dev, usb_pipeendpoint(pipe),
- usb_pipeout(pipe), toggle);
- dev->status = 0;
- break;
- case 0x40:
- dev->status = USB_ST_STALLED;
- break;
- case 0xa0:
- case 0x20:
- dev->status = USB_ST_BUF_ERR;
- break;
- case 0x50:
- case 0x10:
- dev->status = USB_ST_BABBLE_DET;
- break;
- default:
- dev->status = USB_ST_CRC_ERR;
- break;
- }
- dev->act_len = length - ((token >> 16) & 0x7fff);
- } else {
- dev->act_len = 0;
- debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
- dev->devnum, ehci_readl(&hcor->or_usbsts),
- ehci_readl(&hcor->or_portsc[0]),
- ehci_readl(&hcor->or_portsc[1]));
- }
-
- return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
-
-fail:
- td = (void *)hc32_to_cpu(qh->qh_overlay.qt_next);
- while (td != (void *)QT_NEXT_TERMINATE) {
- qh->qh_overlay.qt_next = td->qt_next;
- ehci_free(td, sizeof(*td));
- td = (void *)hc32_to_cpu(qh->qh_overlay.qt_next);
- }
- ehci_free(qh, sizeof(*qh));
- return -1;
-}
-
-static inline int min3(int a, int b, int c)
-{
-
- if (b < a)
- a = b;
- if (c < a)
- a = c;
- return a;
-}
-
-int
-ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
- int length, struct devrequest *req)
-{
- uint8_t tmpbuf[4];
- u16 typeReq;
- void *srcptr = NULL;
- int len, srclen;
- uint32_t reg;
- uint32_t *status_reg;
-
- if (le16_to_cpu(req->index) >= CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
- printf("The request port(%d) is not configured\n",
- le16_to_cpu(req->index) - 1);
- return -1;
- }
- status_reg = (uint32_t *)&hcor->or_portsc[
- le16_to_cpu(req->index) - 1];
- srclen = 0;
-
- debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
- req->request, req->request,
- req->requesttype, req->requesttype,
- le16_to_cpu(req->value), le16_to_cpu(req->index));
-
- typeReq = req->request | req->requesttype << 8;
-
- switch (typeReq) {
- case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
- switch (le16_to_cpu(req->value) >> 8) {
- case USB_DT_DEVICE:
- debug("USB_DT_DEVICE request\n");
- srcptr = &descriptor.device;
- srclen = 0x12;
- break;
- case USB_DT_CONFIG:
- debug("USB_DT_CONFIG config\n");
- srcptr = &descriptor.config;
- srclen = 0x19;
- break;
- case USB_DT_STRING:
- debug("USB_DT_STRING config\n");
- switch (le16_to_cpu(req->value) & 0xff) {
- case 0: /* Language */
- srcptr = "\4\3\1\0";
- srclen = 4;
- break;
- case 1: /* Vendor */
- srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
- srclen = 14;
- break;
- case 2: /* Product */
- srcptr = "\52\3E\0H\0C\0I\0 "
- "\0H\0o\0s\0t\0 "
- "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
- srclen = 42;
- break;
- default:
- debug("unknown value DT_STRING %x\n",
- le16_to_cpu(req->value));
- goto unknown;
- }
- break;
- default:
- debug("unknown value %x\n", le16_to_cpu(req->value));
- goto unknown;
- }
- break;
- case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
- switch (le16_to_cpu(req->value) >> 8) {
- case USB_DT_HUB:
- debug("USB_DT_HUB config\n");
- srcptr = &descriptor.hub;
- srclen = 0x8;
- break;
- default:
- debug("unknown value %x\n", le16_to_cpu(req->value));
- goto unknown;
- }
- break;
- case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
- debug("USB_REQ_SET_ADDRESS\n");
- rootdev = le16_to_cpu(req->value);
- break;
- case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
- debug("USB_REQ_SET_CONFIGURATION\n");
- /* Nothing to do */
- break;
- case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
- tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
- tmpbuf[1] = 0;
- srcptr = tmpbuf;
- srclen = 2;
- break;
- case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
- memset(tmpbuf, 0, 4);
- reg = ehci_readl(status_reg);
- if (reg & EHCI_PS_CS)
- tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
- if (reg & EHCI_PS_PE)
- tmpbuf[0] |= USB_PORT_STAT_ENABLE;
- if (reg & EHCI_PS_SUSP)
- tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
- if (reg & EHCI_PS_OCA)
- tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
- if (reg & EHCI_PS_PR &&
- (portreset & (1 << le16_to_cpu(req->index)))) {
- int ret;
- /* force reset to complete */
- reg = reg & ~(EHCI_PS_PR | EHCI_PS_CLEAR);
- ehci_writel(status_reg, reg);
- ret = handshake(status_reg, EHCI_PS_PR, 0, 2 * 1000);
- if (!ret)
- tmpbuf[0] |= USB_PORT_STAT_RESET;
- else
- printf("port(%d) reset error\n",
- le16_to_cpu(req->index) - 1);
- }
- if (reg & EHCI_PS_PP)
- tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
-
- if (ehci_is_TDI()) {
- switch ((reg >> 26) & 3) {
- case 0:
- break;
- case 1:
- tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
- break;
- case 2:
- default:
- tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
- break;
- }
- } else {
- tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
- }
-
- if (reg & EHCI_PS_CSC)
- tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
- if (reg & EHCI_PS_PEC)
- tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
- if (reg & EHCI_PS_OCC)
- tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
- if (portreset & (1 << le16_to_cpu(req->index)))
- tmpbuf[2] |= USB_PORT_STAT_C_RESET;
-
- srcptr = tmpbuf;
- srclen = 4;
- break;
- case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
- reg = ehci_readl(status_reg);
- reg &= ~EHCI_PS_CLEAR;
- switch (le16_to_cpu(req->value)) {
- case USB_PORT_FEAT_ENABLE:
- reg |= EHCI_PS_PE;
- ehci_writel(status_reg, reg);
- break;
- case USB_PORT_FEAT_POWER:
- if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams))) {
- reg |= EHCI_PS_PP;
- ehci_writel(status_reg, reg);
- }
- break;
- case USB_PORT_FEAT_RESET:
- if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
- !ehci_is_TDI() &&
- EHCI_PS_IS_LOWSPEED(reg)) {
- /* Low speed device, give up ownership. */
- debug("port %d low speed --> companion\n",
- req->index - 1);
- reg |= EHCI_PS_PO;
- ehci_writel(status_reg, reg);
- break;
- } else {
- reg |= EHCI_PS_PR;
- reg &= ~EHCI_PS_PE;
- ehci_writel(status_reg, reg);
- /*
- * caller must wait, then call GetPortStatus
- * usb 2.0 specification say 50 ms resets on
- * root
- */
- wait_ms(50);
- portreset |= 1 << le16_to_cpu(req->index);
- }
- break;
- default:
- debug("unknown feature %x\n", le16_to_cpu(req->value));
- goto unknown;
- }
- /* unblock posted writes */
- (void) ehci_readl(&hcor->or_usbcmd);
- break;
- case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
- reg = ehci_readl(status_reg);
- switch (le16_to_cpu(req->value)) {
- case USB_PORT_FEAT_ENABLE:
- reg &= ~EHCI_PS_PE;
- break;
- case USB_PORT_FEAT_C_ENABLE:
- reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_PE;
- break;
- case USB_PORT_FEAT_POWER:
- if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams)))
- reg = reg & ~(EHCI_PS_CLEAR | EHCI_PS_PP);
- case USB_PORT_FEAT_C_CONNECTION:
- reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_CSC;
- break;
- case USB_PORT_FEAT_OVER_CURRENT:
- reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_OCC;
- break;
- case USB_PORT_FEAT_C_RESET:
- portreset &= ~(1 << le16_to_cpu(req->index));
- break;
- default:
- debug("unknown feature %x\n", le16_to_cpu(req->value));
- goto unknown;
- }
- ehci_writel(status_reg, reg);
- /* unblock posted write */
- (void) ehci_readl(&hcor->or_usbcmd);
- break;
- default:
- debug("Unknown request\n");
- goto unknown;
- }
-
- wait_ms(1);
- len = min3(srclen, le16_to_cpu(req->length), length);
- if (srcptr != NULL && len > 0)
- memcpy(buffer, srcptr, len);
- else
- debug("Len is 0\n");
-
- dev->act_len = len;
- dev->status = 0;
- return 0;
-
-unknown:
- debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
- req->requesttype, req->request, le16_to_cpu(req->value),
- le16_to_cpu(req->index), le16_to_cpu(req->length));
-
- dev->act_len = 0;
- dev->status = USB_ST_STALLED;
- return -1;
-}
-
-int usb_lowlevel_stop(void)
-{
- return ehci_hcd_stop();
-}
-
-int usb_lowlevel_init(void)
-{
- uint32_t reg;
- uint32_t cmd;
-
- if (ehci_hcd_init() != 0)
- return -1;
-
- /* EHCI spec section 4.1 */
- if (ehci_reset() != 0)
- return -1;
-
-#if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
- if (ehci_hcd_init() != 0)
- return -1;
-#endif
-
- /* Set head of reclaim list */
- memset(&qh_list, 0, sizeof(qh_list));
- qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH);
- qh_list.qh_endpt1 = cpu_to_hc32((1 << 15) | (USB_SPEED_HIGH << 12));
- qh_list.qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE);
- qh_list.qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
- qh_list.qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
- qh_list.qh_overlay.qt_token = cpu_to_hc32(0x40);
-
- /* Set async. queue head pointer. */
- ehci_writel(&hcor->or_asynclistaddr, (uint32_t)&qh_list);
-
- reg = ehci_readl(&hccr->cr_hcsparams);
- descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
- printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
- /* Port Indicators */
- if (HCS_INDICATOR(reg))
- descriptor.hub.wHubCharacteristics |= 0x80;
- /* Port Power Control */
- if (HCS_PPC(reg))
- descriptor.hub.wHubCharacteristics |= 0x01;
-
- /* Start the host controller. */
- cmd = ehci_readl(&hcor->or_usbcmd);
- /*
- * Philips, Intel, and maybe others need CMD_RUN before the
- * root hub will detect new devices (why?); NEC doesn't
- */
- cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
- cmd |= CMD_RUN;
- ehci_writel(&hcor->or_usbcmd, cmd);
-
- /* take control over the ports */
- cmd = ehci_readl(&hcor->or_configflag);
- cmd |= FLAG_CF;
- ehci_writel(&hcor->or_configflag, cmd);
- /* unblock posted write */
- cmd = ehci_readl(&hcor->or_usbcmd);
- wait_ms(5);
- reg = HC_VERSION(ehci_readl(&hccr->cr_capbase));
- printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
-
- rootdev = 0;
-
- return 0;
-}
-
-int
-submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int length)
-{
-
- if (usb_pipetype(pipe) != PIPE_BULK) {
- debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
- return -1;
- }
- return ehci_submit_async(dev, pipe, buffer, length, NULL);
-}
-
-int
-submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int length, struct devrequest *setup)
-{
-
- if (usb_pipetype(pipe) != PIPE_CONTROL) {
- debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
- return -1;
- }
-
- if (usb_pipedevice(pipe) == rootdev) {
- if (rootdev == 0)
- dev->speed = USB_SPEED_HIGH;
- return ehci_submit_root(dev, pipe, buffer, length, setup);
- }
- return ehci_submit_async(dev, pipe, buffer, length, setup);
-}
-
-int
-submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int length, int interval)
-{
-
- debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
- dev, pipe, buffer, length, interval);
- return -1;
-}
+++ /dev/null
-/*-
- * Copyright (c) 2007-2008, Juniper Networks, Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <pci.h>
-#include <usb.h>
-
-#include "ehci.h"
-#include "ehci-core.h"
-
-#ifdef CONFIG_PCI_EHCI_DEVICE
-static struct pci_device_id ehci_pci_ids[] = {
- /* Please add supported PCI EHCI controller ids here */
- {0, 0}
-};
-#endif
-
-/*
- * Create the appropriate control structures to manage
- * a new EHCI host controller.
- */
-int ehci_hcd_init(void)
-{
- pci_dev_t pdev;
- uint32_t addr;
-
- pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVICE);
- if (pdev == -1) {
- printf("EHCI host controller not found\n");
- return -1;
- }
-
- pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &addr);
- hccr = (struct ehci_hccr *)addr;
- hcor = (struct ehci_hcor *)((uint32_t) hccr +
- HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
-
- return 0;
-}
-
-/*
- * Destroy the appropriate control structures corresponding
- * the the EHCI host controller.
- */
-int ehci_hcd_stop(void)
-{
- return 0;
-}
+++ /dev/null
-/*-
- * Copyright (c) 2007-2008, Juniper Networks, Inc.
- * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef USB_EHCI_H
-#define USB_EHCI_H
-
-#if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS)
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
-#endif
-
-/* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */
-#define DeviceRequest \
- ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
-
-#define DeviceOutRequest \
- ((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
-
-#define InterfaceRequest \
- ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
-
-#define EndpointRequest \
- ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
-
-#define EndpointOutRequest \
- ((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
-
-/*
- * Register Space.
- */
-struct ehci_hccr {
- uint32_t cr_capbase;
-#define HC_LENGTH(p) (((p) >> 0) & 0x00ff)
-#define HC_VERSION(p) (((p) >> 16) & 0xffff)
- uint32_t cr_hcsparams;
-#define HCS_PPC(p) ((p) & (1 << 4))
-#define HCS_INDICATOR(p) ((p) & (1 << 16)) /* Port indicators */
-#define HCS_N_PORTS(p) (((p) >> 0) & 0xf)
- uint32_t cr_hccparams;
- uint8_t cr_hcsp_portrt[8];
-} __attribute__ ((packed));
-
-struct ehci_hcor {
- uint32_t or_usbcmd;
-#define CMD_PARK (1 << 11) /* enable "park" */
-#define CMD_PARK_CNT(c) (((c) >> 8) & 3) /* how many transfers to park */
-#define CMD_ASE (1 << 5) /* async schedule enable */
-#define CMD_LRESET (1 << 7) /* partial reset */
-#define CMD_IAAD (1 << 5) /* "doorbell" interrupt */
-#define CMD_PSE (1 << 4) /* periodic schedule enable */
-#define CMD_RESET (1 << 1) /* reset HC not bus */
-#define CMD_RUN (1 << 0) /* start/stop HC */
- uint32_t or_usbsts;
-#define STD_ASS (1 << 15)
-#define STS_HALT (1 << 12)
- uint32_t or_usbintr;
- uint32_t or_frindex;
- uint32_t or_ctrldssegment;
- uint32_t or_periodiclistbase;
- uint32_t or_asynclistaddr;
- uint32_t _reserved_[9];
- uint32_t or_configflag;
-#define FLAG_CF (1 << 0) /* true: we'll support "high speed" */
- uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
- uint32_t or_systune;
-} __attribute__ ((packed));
-
-#define USBMODE 0x68 /* USB Device mode */
-#define USBMODE_SDIS (1 << 3) /* Stream disable */
-#define USBMODE_BE (1 << 2) /* BE/LE endiannes select */
-#define USBMODE_CM_HC (3 << 0) /* host controller mode */
-#define USBMODE_CM_IDLE (0 << 0) /* idle state */
-
-/* Interface descriptor */
-struct usb_linux_interface_descriptor {
- unsigned char bLength;
- unsigned char bDescriptorType;
- unsigned char bInterfaceNumber;
- unsigned char bAlternateSetting;
- unsigned char bNumEndpoints;
- unsigned char bInterfaceClass;
- unsigned char bInterfaceSubClass;
- unsigned char bInterfaceProtocol;
- unsigned char iInterface;
-} __attribute__ ((packed));
-
-/* Configuration descriptor information.. */
-struct usb_linux_config_descriptor {
- unsigned char bLength;
- unsigned char bDescriptorType;
- unsigned short wTotalLength;
- unsigned char bNumInterfaces;
- unsigned char bConfigurationValue;
- unsigned char iConfiguration;
- unsigned char bmAttributes;
- unsigned char MaxPower;
-} __attribute__ ((packed));
-
-#if defined CONFIG_EHCI_DESC_BIG_ENDIAN
-#define ehci_readl(x) (*((volatile u32 *)(x)))
-#define ehci_writel(a, b) (*((volatile u32 *)(a)) = ((volatile u32)b))
-#else
-#define ehci_readl(x) cpu_to_le32((*((volatile u32 *)(x))))
-#define ehci_writel(a, b) (*((volatile u32 *)(a)) = \
- cpu_to_le32(((volatile u32)b)))
-#endif
-
-#if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
-#define hc32_to_cpu(x) be32_to_cpu((x))
-#define cpu_to_hc32(x) cpu_to_be32((x))
-#else
-#define hc32_to_cpu(x) le32_to_cpu((x))
-#define cpu_to_hc32(x) cpu_to_le32((x))
-#endif
-
-#define EHCI_PS_WKOC_E (1 << 22) /* RW wake on over current */
-#define EHCI_PS_WKDSCNNT_E (1 << 21) /* RW wake on disconnect */
-#define EHCI_PS_WKCNNT_E (1 << 20) /* RW wake on connect */
-#define EHCI_PS_PO (1 << 13) /* RW port owner */
-#define EHCI_PS_PP (1 << 12) /* RW,RO port power */
-#define EHCI_PS_LS (3 << 10) /* RO line status */
-#define EHCI_PS_PR (1 << 8) /* RW port reset */
-#define EHCI_PS_SUSP (1 << 7) /* RW suspend */
-#define EHCI_PS_FPR (1 << 6) /* RW force port resume */
-#define EHCI_PS_OCC (1 << 5) /* RWC over current change */
-#define EHCI_PS_OCA (1 << 4) /* RO over current active */
-#define EHCI_PS_PEC (1 << 3) /* RWC port enable change */
-#define EHCI_PS_PE (1 << 2) /* RW port enable */
-#define EHCI_PS_CSC (1 << 1) /* RWC connect status change */
-#define EHCI_PS_CS (1 << 0) /* RO connect status */
-#define EHCI_PS_CLEAR (EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
-
-#define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == (1 << 10))
-
-/*
- * Schedule Interface Space.
- *
- * IMPORTANT: Software must ensure that no interface data structure
- * reachable by the EHCI host controller spans a 4K page boundary!
- *
- * Periodic transfers (i.e. isochronous and interrupt transfers) are
- * not supported.
- */
-
-/* Queue Element Transfer Descriptor (qTD). */
-struct qTD {
- uint32_t qt_next;
-#define QT_NEXT_TERMINATE 1
- uint32_t qt_altnext;
- uint32_t qt_token;
- uint32_t qt_buffer[5];
-};
-
-/* Queue Head (QH). */
-struct QH {
- uint32_t qh_link;
-#define QH_LINK_TERMINATE 1
-#define QH_LINK_TYPE_ITD 0
-#define QH_LINK_TYPE_QH 2
-#define QH_LINK_TYPE_SITD 4
-#define QH_LINK_TYPE_FSTN 6
- uint32_t qh_endpt1;
- uint32_t qh_endpt2;
- uint32_t qh_curtd;
- struct qTD qh_overlay;
- /*
- * Add dummy fill value to make the size of this struct
- * aligned to 32 bytes
- */
- uint8_t fill[16];
-};
-
-/* Low level init functions */
-int ehci_hcd_init(void);
-int ehci_hcd_stop(void);
-
-#endif /* USB_EHCI_H */
+++ /dev/null
-/*
- * JFFS2 -- Journalling Flash File System, Version 2.
- *
- * Copyright (C) 2004 Patrik Kluba,
- * University of Szeged, Hungary
- *
- * For licensing information, see the file 'LICENCE' in the
- * jffs2 directory.
- *
- * $Id: compr_lzari.c,v 1.3 2004/06/23 16:34:39 havasi Exp $
- *
- */
-
-/*
- Lempel-Ziv-Arithmetic coding compression module for jffs2
- Based on the LZARI source included in LDS (lossless datacompression sources)
-*/
-
-/* -*- Mode: C; indent-tabs-mode: t; c-basic-offset: 4; tab-width: 4 -*- */
-
-/*
-Original copyright follows:
-
-**************************************************************
- LZARI.C -- A Data Compression Program
- (tab = 4 spaces)
-**************************************************************
- 4/7/1989 Haruhiko Okumura
- Use, distribute, and modify this program freely.
- Please send me your improved versions.
- PC-VAN SCIENCE
- NIFTY-Serve PAF01022
- CompuServe 74050,1022
-**************************************************************
-
-LZARI.C (c)1989 by Haruyasu Yoshizaki, Haruhiko Okumura, and Kenji Rikitake.
-All rights reserved. Permission granted for non-commercial use.
-
-*/
-
-/*
-
- 2004-02-18 pajko <pajko(AT)halom(DOT)u-szeged(DOT)hu>
- Removed unused variables and fixed no return value
-
- 2004-02-16 pajko <pajko(AT)halom(DOT)u-szeged(DOT)hu>
- Initial release
-
-*/
-
-
-#include <config.h>
-#include <linux/stddef.h>
-#include <jffs2/jffs2.h>
-
-
-#define N 4096 /* size of ring buffer */
-#define F 60 /* upper limit for match_length */
-#define THRESHOLD 2 /* encode string into position and length
- if match_length is greater than this */
-#define NIL N /* index for root of binary search trees */
-
-static unsigned char
- text_buf[N + F - 1]; /* ring buffer of size N,
- with extra F-1 bytes to facilitate string comparison */
-
-/********** Arithmetic Compression **********/
-
-/* If you are not familiar with arithmetic compression, you should read
- I. E. Witten, R. M. Neal, and J. G. Cleary,
- Communications of the ACM, Vol. 30, pp. 520-540 (1987),
- from which much have been borrowed. */
-
-#define M 15
-
-/* Q1 (= 2 to the M) must be sufficiently large, but not so
- large as the unsigned long 4 * Q1 * (Q1 - 1) overflows. */
-
-#define Q1 (1UL << M)
-#define Q2 (2 * Q1)
-#define Q3 (3 * Q1)
-#define Q4 (4 * Q1)
-#define MAX_CUM (Q1 - 1)
-
-#define N_CHAR (256 - THRESHOLD + F)
- /* character code = 0, 1, ..., N_CHAR - 1 */
-
-static unsigned long char_to_sym[N_CHAR], sym_to_char[N_CHAR + 1];
-static unsigned long
- sym_freq[N_CHAR + 1], /* frequency for symbols */
- sym_cum[N_CHAR + 1], /* cumulative freq for symbols */
- position_cum[N + 1]; /* cumulative freq for positions */
-
-static void StartModel(void) /* Initialize model */
-{
- unsigned long ch, sym, i;
-
- sym_cum[N_CHAR] = 0;
- for (sym = N_CHAR; sym >= 1; sym--) {
- ch = sym - 1;
- char_to_sym[ch] = sym; sym_to_char[sym] = ch;
- sym_freq[sym] = 1;
- sym_cum[sym - 1] = sym_cum[sym] + sym_freq[sym];
- }
- sym_freq[0] = 0; /* sentinel (!= sym_freq[1]) */
- position_cum[N] = 0;
- for (i = N; i >= 1; i--)
- position_cum[i - 1] = position_cum[i] + 10000 / (i + 200);
- /* empirical distribution function (quite tentative) */
- /* Please devise a better mechanism! */
-}
-
-static void UpdateModel(unsigned long sym)
-{
- unsigned long c, ch_i, ch_sym;
- unsigned long i;
- if (sym_cum[0] >= MAX_CUM) {
- c = 0;
- for (i = N_CHAR; i > 0; i--) {
- sym_cum[i] = c;
- c += (sym_freq[i] = (sym_freq[i] + 1) >> 1);
- }
- sym_cum[0] = c;
- }
- for (i = sym; sym_freq[i] == sym_freq[i - 1]; i--) ;
- if (i < sym) {
- ch_i = sym_to_char[i]; ch_sym = sym_to_char[sym];
- sym_to_char[i] = ch_sym; sym_to_char[sym] = ch_i;
- char_to_sym[ch_i] = sym; char_to_sym[ch_sym] = i;
- }
- sym_freq[i]++;
- while (--i > 0) sym_cum[i]++;
- sym_cum[0]++;
-}
-
-static unsigned long BinarySearchSym(unsigned long x)
- /* 1 if x >= sym_cum[1],
- N_CHAR if sym_cum[N_CHAR] > x,
- i such that sym_cum[i - 1] > x >= sym_cum[i] otherwise */
-{
- unsigned long i, j, k;
-
- i = 1; j = N_CHAR;
- while (i < j) {
- k = (i + j) / 2;
- if (sym_cum[k] > x) i = k + 1; else j = k;
- }
- return i;
-}
-
-unsigned long BinarySearchPos(unsigned long x)
- /* 0 if x >= position_cum[1],
- N - 1 if position_cum[N] > x,
- i such that position_cum[i] > x >= position_cum[i + 1] otherwise */
-{
- unsigned long i, j, k;
-
- i = 1; j = N;
- while (i < j) {
- k = (i + j) / 2;
- if (position_cum[k] > x) i = k + 1; else j = k;
- }
- return i - 1;
-}
-
-static int Decode(unsigned char *srcbuf, unsigned char *dstbuf, unsigned long srclen,
- unsigned long dstlen) /* Just the reverse of Encode(). */
-{
- unsigned long i, r, j, k, c, range, sym;
- unsigned char *ip, *op;
- unsigned char *srcend = srcbuf + srclen;
- unsigned char *dstend = dstbuf + dstlen;
- unsigned char buffer = 0;
- unsigned char mask = 0;
- unsigned long low = 0;
- unsigned long high = Q4;
- unsigned long value = 0;
-
- ip = srcbuf;
- op = dstbuf;
- for (i = 0; i < M + 2; i++) {
- value *= 2;
- if ((mask >>= 1) == 0) {
- buffer = (ip >= srcend) ? 0 : *(ip++);
- mask = 128;
- }
- value += ((buffer & mask) != 0);
- }
-
- StartModel();
- for (i = 0; i < N - F; i++) text_buf[i] = ' ';
- r = N - F;
-
- while (op < dstend) {
- range = high - low;
- sym = BinarySearchSym((unsigned long)
- (((value - low + 1) * sym_cum[0] - 1) / range));
- high = low + (range * sym_cum[sym - 1]) / sym_cum[0];
- low += (range * sym_cum[sym ]) / sym_cum[0];
- for ( ; ; ) {
- if (low >= Q2) {
- value -= Q2; low -= Q2; high -= Q2;
- } else if (low >= Q1 && high <= Q3) {
- value -= Q1; low -= Q1; high -= Q1;
- } else if (high > Q2) break;
- low += low; high += high;
- value *= 2;
- if ((mask >>= 1) == 0) {
- buffer = (ip >= srcend) ? 0 : *(ip++);
- mask = 128;
- }
- value += ((buffer & mask) != 0);
- }
- c = sym_to_char[sym];
- UpdateModel(sym);
- if (c < 256) {
- if (op >= dstend) return -1;
- *(op++) = c;
- text_buf[r++] = c;
- r &= (N - 1);
- } else {
- j = c - 255 + THRESHOLD;
- range = high - low;
- i = BinarySearchPos((unsigned long)
- (((value - low + 1) * position_cum[0] - 1) / range));
- high = low + (range * position_cum[i ]) / position_cum[0];
- low += (range * position_cum[i + 1]) / position_cum[0];
- for ( ; ; ) {
- if (low >= Q2) {
- value -= Q2; low -= Q2; high -= Q2;
- } else if (low >= Q1 && high <= Q3) {
- value -= Q1; low -= Q1; high -= Q1;
- } else if (high > Q2) break;
- low += low; high += high;
- value *= 2;
- if ((mask >>= 1) == 0) {
- buffer = (ip >= srcend) ? 0 : *(ip++);
- mask = 128;
- }
- value += ((buffer & mask) != 0);
- }
- i = (r - i - 1) & (N - 1);
- for (k = 0; k < j; k++) {
- c = text_buf[(i + k) & (N - 1)];
- if (op >= dstend) return -1;
- *(op++) = c;
- text_buf[r++] = c;
- r &= (N - 1);
- }
- }
- }
- return 0;
-}
-
-int lzari_decompress(unsigned char *data_in, unsigned char *cpage_out,
- u32 srclen, u32 destlen)
-{
- return Decode(data_in, cpage_out, srclen, destlen);
-}
+++ /dev/null
-/*
- * JFFS2 -- Journalling Flash File System, Version 2.
- *
- * Copyright (C) 2004 Patrik Kluba,
- * University of Szeged, Hungary
- *
- * For licensing information, see the file 'LICENCE' in the
- * jffs2 directory.
- *
- * $Id: compr_lzo.c,v 1.3 2004/06/23 16:34:39 havasi Exp $
- *
- */
-
-/*
- LZO1X-1 (and -999) compression module for jffs2
- based on the original LZO sources
-*/
-
-/* -*- Mode: C; indent-tabs-mode: t; c-basic-offset: 4; tab-width: 4 -*- */
-
-/*
- Original copyright notice follows:
-
- lzo1x_9x.c -- implementation of the LZO1X-999 compression algorithm
- lzo_ptr.h -- low-level pointer constructs
- lzo_swd.ch -- sliding window dictionary
- lzoconf.h -- configuration for the LZO real-time data compression library
- lzo_mchw.ch -- matching functions using a window
- minilzo.c -- mini subset of the LZO real-time data compression library
- config1x.h -- configuration for the LZO1X algorithm
- lzo1x.h -- public interface of the LZO1X compression algorithm
-
- These files are part of the LZO real-time data compression library.
-
- Copyright (C) 1996-2002 Markus Franz Xaver Johannes Oberhumer
- All Rights Reserved.
-
- The LZO library is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
-
- The LZO library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with the LZO library; see the file COPYING.
- If not, write to the Free Software Foundation, Inc.,
- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
- Markus F.X.J. Oberhumer
- <markus@oberhumer.com>
-*/
-
-/*
-
- 2004-02-16 pajko <pajko(AT)halom(DOT)u-szeged(DOT)hu>
- Initial release
- -removed all 16 bit code
- -all sensitive data will be on 4 byte boundary
- -removed check parts for library use
- -removed all but LZO1X-* compression
-
-*/
-
-
-#include <config.h>
-#include <linux/stddef.h>
-#include <jffs2/jffs2.h>
-#include <jffs2/compr_rubin.h>
-
-/* Integral types that have *exactly* the same number of bits as a lzo_voidp */
-typedef unsigned long lzo_ptr_t;
-typedef long lzo_sptr_t;
-
-/* data type definitions */
-#define U32 unsigned long
-#define S32 signed long
-#define I32 long
-#define U16 unsigned short
-#define S16 signed short
-#define I16 short
-#define U8 unsigned char
-#define S8 signed char
-#define I8 char
-
-#define M1_MAX_OFFSET 0x0400
-#define M2_MAX_OFFSET 0x0800
-#define M3_MAX_OFFSET 0x4000
-#define M4_MAX_OFFSET 0xbfff
-
-#define __COPY4(dst,src) * (lzo_uint32p)(dst) = * (const lzo_uint32p)(src)
-#define COPY4(dst,src) __COPY4((lzo_ptr_t)(dst),(lzo_ptr_t)(src))
-
-#define TEST_IP (ip < ip_end)
-#define TEST_OP (op <= op_end)
-
-#define NEED_IP(x) \
- if ((lzo_uint)(ip_end - ip) < (lzo_uint)(x)) goto input_overrun
-#define NEED_OP(x) \
- if ((lzo_uint)(op_end - op) < (lzo_uint)(x)) goto output_overrun
-#define TEST_LOOKBEHIND(m_pos,out) if (m_pos < out) goto lookbehind_overrun
-
-typedef U32 lzo_uint32;
-typedef I32 lzo_int32;
-typedef U32 lzo_uint;
-typedef I32 lzo_int;
-typedef int lzo_bool;
-
-#define lzo_byte U8
-#define lzo_bytep U8 *
-#define lzo_charp char *
-#define lzo_voidp void *
-#define lzo_shortp short *
-#define lzo_ushortp unsigned short *
-#define lzo_uint32p lzo_uint32 *
-#define lzo_int32p lzo_int32 *
-#define lzo_uintp lzo_uint *
-#define lzo_intp lzo_int *
-#define lzo_voidpp lzo_voidp *
-#define lzo_bytepp lzo_bytep *
-#define lzo_sizeof_dict_t sizeof(lzo_bytep)
-
-#define LZO_E_OK 0
-#define LZO_E_ERROR (-1)
-#define LZO_E_OUT_OF_MEMORY (-2) /* not used right now */
-#define LZO_E_NOT_COMPRESSIBLE (-3) /* not used right now */
-#define LZO_E_INPUT_OVERRUN (-4)
-#define LZO_E_OUTPUT_OVERRUN (-5)
-#define LZO_E_LOOKBEHIND_OVERRUN (-6)
-#define LZO_E_EOF_NOT_FOUND (-7)
-#define LZO_E_INPUT_NOT_CONSUMED (-8)
-
-#define PTR(a) ((lzo_ptr_t) (a))
-#define PTR_LINEAR(a) PTR(a)
-#define PTR_ALIGNED_4(a) ((PTR_LINEAR(a) & 3) == 0)
-#define PTR_ALIGNED_8(a) ((PTR_LINEAR(a) & 7) == 0)
-#define PTR_ALIGNED2_4(a,b) (((PTR_LINEAR(a) | PTR_LINEAR(b)) & 3) == 0)
-#define PTR_ALIGNED2_8(a,b) (((PTR_LINEAR(a) | PTR_LINEAR(b)) & 7) == 0)
-#define PTR_LT(a,b) (PTR(a) < PTR(b))
-#define PTR_GE(a,b) (PTR(a) >= PTR(b))
-#define PTR_DIFF(a,b) ((lzo_ptrdiff_t) (PTR(a) - PTR(b)))
-#define pd(a,b) ((lzo_uint) ((a)-(b)))
-
-typedef ptrdiff_t lzo_ptrdiff_t;
-
-static int
-lzo1x_decompress (const lzo_byte * in, lzo_uint in_len,
- lzo_byte * out, lzo_uintp out_len, lzo_voidp wrkmem)
-{
- register lzo_byte *op;
- register const lzo_byte *ip;
- register lzo_uint t;
-
- register const lzo_byte *m_pos;
-
- const lzo_byte *const ip_end = in + in_len;
- lzo_byte *const op_end = out + *out_len;
-
- *out_len = 0;
-
- op = out;
- ip = in;
-
- if (*ip > 17)
- {
- t = *ip++ - 17;
- if (t < 4)
- goto match_next;
- NEED_OP (t);
- NEED_IP (t + 1);
- do
- *op++ = *ip++;
- while (--t > 0);
- goto first_literal_run;
- }
-
- while (TEST_IP && TEST_OP)
- {
- t = *ip++;
- if (t >= 16)
- goto match;
- if (t == 0)
- {
- NEED_IP (1);
- while (*ip == 0)
- {
- t += 255;
- ip++;
- NEED_IP (1);
- }
- t += 15 + *ip++;
- }
- NEED_OP (t + 3);
- NEED_IP (t + 4);
- if (PTR_ALIGNED2_4 (op, ip))
- {
- COPY4 (op, ip);
-
- op += 4;
- ip += 4;
- if (--t > 0)
- {
- if (t >= 4)
- {
- do
- {
- COPY4 (op, ip);
- op += 4;
- ip += 4;
- t -= 4;
- }
- while (t >= 4);
- if (t > 0)
- do
- *op++ = *ip++;
- while (--t > 0);
- }
- else
- do
- *op++ = *ip++;
- while (--t > 0);
- }
- }
- else
- {
- *op++ = *ip++;
- *op++ = *ip++;
- *op++ = *ip++;
- do
- *op++ = *ip++;
- while (--t > 0);
- }
- first_literal_run:
-
- t = *ip++;
- if (t >= 16)
- goto match;
-
- m_pos = op - (1 + M2_MAX_OFFSET);
- m_pos -= t >> 2;
- m_pos -= *ip++ << 2;
- TEST_LOOKBEHIND (m_pos, out);
- NEED_OP (3);
- *op++ = *m_pos++;
- *op++ = *m_pos++;
- *op++ = *m_pos;
-
- goto match_done;
-
- while (TEST_IP && TEST_OP)
- {
- match:
- if (t >= 64)
- {
- m_pos = op - 1;
- m_pos -= (t >> 2) & 7;
- m_pos -= *ip++ << 3;
- t = (t >> 5) - 1;
- TEST_LOOKBEHIND (m_pos, out);
- NEED_OP (t + 3 - 1);
- goto copy_match;
-
- }
- else if (t >= 32)
- {
- t &= 31;
- if (t == 0)
- {
- NEED_IP (1);
- while (*ip == 0)
- {
- t += 255;
- ip++;
- NEED_IP (1);
- }
- t += 31 + *ip++;
- }
-
- m_pos = op - 1;
- m_pos -= (ip[0] >> 2) + (ip[1] << 6);
-
- ip += 2;
- }
- else if (t >= 16)
- {
- m_pos = op;
- m_pos -= (t & 8) << 11;
-
- t &= 7;
- if (t == 0)
- {
- NEED_IP (1);
- while (*ip == 0)
- {
- t += 255;
- ip++;
- NEED_IP (1);
- }
- t += 7 + *ip++;
- }
-
- m_pos -= (ip[0] >> 2) + (ip[1] << 6);
-
- ip += 2;
- if (m_pos == op)
- goto eof_found;
- m_pos -= 0x4000;
- }
- else
- {
-
- m_pos = op - 1;
- m_pos -= t >> 2;
- m_pos -= *ip++ << 2;
- TEST_LOOKBEHIND (m_pos, out);
- NEED_OP (2);
- *op++ = *m_pos++;
- *op++ = *m_pos;
-
- goto match_done;
- }
-
- TEST_LOOKBEHIND (m_pos, out);
- NEED_OP (t + 3 - 1);
- if (t >= 2 * 4 - (3 - 1)
- && PTR_ALIGNED2_4 (op, m_pos))
- {
- COPY4 (op, m_pos);
- op += 4;
- m_pos += 4;
- t -= 4 - (3 - 1);
- do
- {
- COPY4 (op, m_pos);
- op += 4;
- m_pos += 4;
- t -= 4;
- }
- while (t >= 4);
- if (t > 0)
- do
- *op++ = *m_pos++;
- while (--t > 0);
- }
- else
-
- {
- copy_match:
- *op++ = *m_pos++;
- *op++ = *m_pos++;
- do
- *op++ = *m_pos++;
- while (--t > 0);
- }
-
- match_done:
- t = ip[-2] & 3;
-
- if (t == 0)
- break;
-
- match_next:
- NEED_OP (t);
- NEED_IP (t + 1);
- do
- *op++ = *ip++;
- while (--t > 0);
- t = *ip++;
- }
- }
- *out_len = op - out;
- return LZO_E_EOF_NOT_FOUND;
-
- eof_found:
- *out_len = op - out;
- return (ip == ip_end ? LZO_E_OK :
- (ip <
- ip_end ? LZO_E_INPUT_NOT_CONSUMED : LZO_E_INPUT_OVERRUN));
-
- input_overrun:
- *out_len = op - out;
- return LZO_E_INPUT_OVERRUN;
-
- output_overrun:
- *out_len = op - out;
- return LZO_E_OUTPUT_OVERRUN;
-
- lookbehind_overrun:
- *out_len = op - out;
- return LZO_E_LOOKBEHIND_OVERRUN;
-}
-
-int lzo_decompress(unsigned char *data_in, unsigned char *cpage_out,
- u32 srclen, u32 destlen)
-{
- lzo_uint outlen = destlen;
- return lzo1x_decompress (data_in, srclen, cpage_out, &outlen, NULL);
-}
+++ /dev/null
-/*
- * Copyright (c) 1992, 1993
- * The Regents of the University of California. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the University nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-/* XXX U-BOOT XXX */
-#include <common.h>
-
-#include "yportenv.h"
-//#include <linux/string.h>
-
-/*
- * Qsort routine from Bentley & McIlroy's "Engineering a Sort Function".
- */
-#define swapcode(TYPE, parmi, parmj, n) { \
- long i = (n) / sizeof (TYPE); \
- register TYPE *pi = (TYPE *) (parmi); \
- register TYPE *pj = (TYPE *) (parmj); \
- do { \
- register TYPE t = *pi; \
- *pi++ = *pj; \
- *pj++ = t; \
- } while (--i > 0); \
-}
-
-#define SWAPINIT(a, es) swaptype = ((char *)a - (char *)0) % sizeof(long) || \
- es % sizeof(long) ? 2 : es == sizeof(long)? 0 : 1;
-
-static __inline void
-swapfunc(char *a, char *b, int n, int swaptype)
-{
- if (swaptype <= 1)
- swapcode(long, a, b, n)
- else
- swapcode(char, a, b, n)
-}
-
-#define swap(a, b) \
- if (swaptype == 0) { \
- long t = *(long *)(a); \
- *(long *)(a) = *(long *)(b); \
- *(long *)(b) = t; \
- } else \
- swapfunc(a, b, es, swaptype)
-
-#define vecswap(a, b, n) if ((n) > 0) swapfunc(a, b, n, swaptype)
-
-static __inline char *
-med3(char *a, char *b, char *c, int (*cmp)(const void *, const void *))
-{
- return cmp(a, b) < 0 ?
- (cmp(b, c) < 0 ? b : (cmp(a, c) < 0 ? c : a ))
- :(cmp(b, c) > 0 ? b : (cmp(a, c) < 0 ? a : c ));
-}
-
-#ifndef min
-#define min(a,b) (((a) < (b)) ? (a) : (b))
-#endif
-
-void
-yaffs_qsort(void *aa, size_t n, size_t es,
- int (*cmp)(const void *, const void *))
-{
- char *pa, *pb, *pc, *pd, *pl, *pm, *pn;
- int d, r, swaptype, swap_cnt;
- register char *a = aa;
-
-loop: SWAPINIT(a, es);
- swap_cnt = 0;
- if (n < 7) {
- for (pm = (char *)a + es; pm < (char *) a + n * es; pm += es)
- for (pl = pm; pl > (char *) a && cmp(pl - es, pl) > 0;
- pl -= es)
- swap(pl, pl - es);
- return;
- }
- pm = (char *)a + (n / 2) * es;
- if (n > 7) {
- pl = (char *)a;
- pn = (char *)a + (n - 1) * es;
- if (n > 40) {
- d = (n / 8) * es;
- pl = med3(pl, pl + d, pl + 2 * d, cmp);
- pm = med3(pm - d, pm, pm + d, cmp);
- pn = med3(pn - 2 * d, pn - d, pn, cmp);
- }
- pm = med3(pl, pm, pn, cmp);
- }
- swap(a, pm);
- pa = pb = (char *)a + es;
-
- pc = pd = (char *)a + (n - 1) * es;
- for (;;) {
- while (pb <= pc && (r = cmp(pb, a)) <= 0) {
- if (r == 0) {
- swap_cnt = 1;
- swap(pa, pb);
- pa += es;
- }
- pb += es;
- }
- while (pb <= pc && (r = cmp(pc, a)) >= 0) {
- if (r == 0) {
- swap_cnt = 1;
- swap(pc, pd);
- pd -= es;
- }
- pc -= es;
- }
- if (pb > pc)
- break;
- swap(pb, pc);
- swap_cnt = 1;
- pb += es;
- pc -= es;
- }
- if (swap_cnt == 0) { /* Switch to insertion sort */
- for (pm = (char *) a + es; pm < (char *) a + n * es; pm += es)
- for (pl = pm; pl > (char *) a && cmp(pl - es, pl) > 0;
- pl -= es)
- swap(pl, pl - es);
- return;
- }
-
- pn = (char *)a + n * es;
- r = min(pa - (char *)a, pb - pa);
- vecswap(a, pb - r, r);
- r = min((long)(pd - pc), (long)(pn - pd - es));
- vecswap(pb, pn - r, r);
- if ((r = pb - pa) > es)
- yaffs_qsort(a, r / es, es, cmp);
- if ((r = pd - pc) > es) {
- /* Iterate rather than recurse to save stack space */
- a = pn - r;
- n = r / es;
- goto loop;
- }
-/* yaffs_qsort(pn - r, r / es, es, cmp);*/
-}
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-/* DO NOT EDIT!! - this file automatically generated
- * from .s file by awk -f s2h.awk
- */
-/* Size defintions
- * Copyright (C) ARM Limited 1998. All rights reserved.
- */
-
-#ifndef __sizes_h
-#define __sizes_h 1
-
-/* handy sizes */
-#define SZ_1K 0x00000400
-#define SZ_4K 0x00001000
-#define SZ_8K 0x00002000
-#define SZ_16K 0x00004000
-#define SZ_64K 0x00010000
-#define SZ_128K 0x00020000
-#define SZ_256K 0x00040000
-#define SZ_512K 0x00080000
-
-#define SZ_1M 0x00100000
-#define SZ_2M 0x00200000
-#define SZ_4M 0x00400000
-#define SZ_8M 0x00800000
-#define SZ_16M 0x01000000
-#define SZ_32M 0x02000000
-#define SZ_64M 0x04000000
-#define SZ_128M 0x08000000
-#define SZ_256M 0x10000000
-#define SZ_512M 0x20000000
-
-#define SZ_1G 0x40000000
-#define SZ_2G 0x80000000
-
-#endif /* __sizes_h */
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA0 2111-1307
- * USA
- */
-/* DO NOT EDIT!! - this file automatically generated
- * from .s file by awk -f s2h.awk
- */
-/* Size defintions
- * Copyright (C) ARM Limited 1998. All rights reserved.
- */
-
-#ifndef __sizes_h
-#define __sizes_h 1
-
-/* handy sizes */
-#define SZ_1K 0x00000400
-#define SZ_4K 0x00001000
-#define SZ_8K 0x00002000
-#define SZ_16K 0x00004000
-#define SZ_64K 0x00010000
-#define SZ_128K 0x00020000
-#define SZ_256K 0x00040000
-#define SZ_512K 0x00080000
-
-#define SZ_1M 0x00100000
-#define SZ_2M 0x00200000
-#define SZ_4M 0x00400000
-#define SZ_8M 0x00800000
-#define SZ_16M 0x01000000
-#define SZ_32M 0x02000000
-#define SZ_64M 0x04000000
-#define SZ_128M 0x08000000
-#define SZ_256M 0x10000000
-#define SZ_512M 0x20000000
-
-#define SZ_1G 0x40000000
-#define SZ_2G 0x80000000
-
-#endif /* __sizes_h */
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-/* DO NOT EDIT!! - this file automatically generated
- * from .s file by awk -f s2h.awk
- */
-/* Size defintions
- * Copyright (C) ARM Limited 1998. All rights reserved.
- */
-
-#ifndef __sizes_h
-#define __sizes_h 1
-
-/* handy sizes */
-#define SZ_1K 0x00000400
-#define SZ_4K 0x00001000
-#define SZ_8K 0x00002000
-#define SZ_16K 0x00004000
-#define SZ_64K 0x00010000
-#define SZ_128K 0x00020000
-#define SZ_256K 0x00040000
-#define SZ_512K 0x00080000
-
-#define SZ_1M 0x00100000
-#define SZ_2M 0x00200000
-#define SZ_4M 0x00400000
-#define SZ_8M 0x00800000
-#define SZ_16M 0x01000000
-#define SZ_32M 0x02000000
-#define SZ_64M 0x04000000
-#define SZ_128M 0x08000000
-#define SZ_256M 0x10000000
-#define SZ_512M 0x20000000
-
-#define SZ_1G 0x40000000
-#define SZ_2G 0x80000000
-
-#endif
-
-/* END */
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-/* Size defintions
- * Copyright (C) ARM Limited 1998. All rights reserved.
- */
-
-#ifndef __sizes_h
-#define __sizes_h 1
-
-/* handy sizes */
-#define SZ_1K 0x00000400
-#define SZ_4K 0x00001000
-#define SZ_8K 0x00002000
-#define SZ_16K 0x00004000
-#define SZ_32K 0x00008000
-#define SZ_64K 0x00010000
-#define SZ_128K 0x00020000
-#define SZ_256K 0x00040000
-#define SZ_512K 0x00080000
-
-#define SZ_1M 0x00100000
-#define SZ_2M 0x00200000
-#define SZ_4M 0x00400000
-#define SZ_8M 0x00800000
-#define SZ_16M 0x01000000
-#define SZ_31M 0x01F00000
-#define SZ_32M 0x02000000
-#define SZ_64M 0x04000000
-#define SZ_128M 0x08000000
-#define SZ_256M 0x10000000
-#define SZ_512M 0x20000000
-
-#define SZ_1G 0x40000000
-#define SZ_2G 0x80000000
-
-#endif /* __sizes_h */
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-/* DO NOT EDIT!! - this file automatically generated
- * from .s file by awk -f s2h.awk
- */
-/* Size defintions
- * Copyright (C) ARM Limited 1998. All rights reserved.
- */
-
-#ifndef __sizes_h
-#define __sizes_h 1
-
-/* handy sizes */
-#define SZ_1K 0x00000400
-#define SZ_4K 0x00001000
-#define SZ_8K 0x00002000
-#define SZ_16K 0x00004000
-#define SZ_64K 0x00010000
-#define SZ_128K 0x00020000
-#define SZ_256K 0x00040000
-#define SZ_512K 0x00080000
-
-#define SZ_1M 0x00100000
-#define SZ_2M 0x00200000
-#define SZ_4M 0x00400000
-#define SZ_8M 0x00800000
-#define SZ_16M 0x01000000
-#define SZ_32M 0x02000000
-#define SZ_64M 0x04000000
-#define SZ_128M 0x08000000
-#define SZ_256M 0x10000000
-#define SZ_512M 0x20000000
-
-#define SZ_1G 0x40000000
-#define SZ_2G 0x80000000
-
-#endif
-
-/* END */
+++ /dev/null
-
-/******************************************************************************
- Copyright (c) 2002, Infineon Technologies. All rights reserved.
-
- No Warranty
- Because the program is licensed free of charge, there is no warranty for
- the program, to the extent permitted by applicable law. Except when
- otherwise stated in writing the copyright holders and/or other parties
- provide the program "as is" without warranty of any kind, either
- expressed or implied, including, but not limited to, the implied
- warranties of merchantability and fitness for a particular purpose. The
- entire risk as to the quality and performance of the program is with
- you. should the program prove defective, you assume the cost of all
- necessary servicing, repair or correction.
-
- In no event unless required by applicable law or agreed to in writing
- will any copyright holder, or any other party who may modify and/or
- redistribute the program as permitted above, be liable to you for
- damages, including any general, special, incidental or consequential
- damages arising out of the use or inability to use the program
- (including but not limited to loss of data or data being rendered
- inaccurate or losses sustained by you or third parties or a failure of
- the program to operate with any other programs), even if such holder or
- other party has been advised of the possibility of such damages.
-******************************************************************************/
-
-
-/***********************************************************************/
-/* Module : WDT register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_WDT (0xB8000000)
-/***********************************************************************/
-
-
-/***Reset Status Register Power On***/
-#define INCA_IP_WDT_RST_SR ((volatile u32*)(INCA_IP_WDT+ 0x0014))
-
-/***Reset Request Register***/
-#define INCA_IP_WDT_RST_REQ ((volatile u32*)(INCA_IP_WDT+ 0x0010))
-#define INCA_IP_WDT_RST_REQ_SWBOOT (1 << 24)
-#define INCA_IP_WDT_RST_REQ_SWCFG (1 << 16)
-#define INCA_IP_WDT_RST_REQ_RRPHY (1 << 5)
-#define INCA_IP_WDT_RST_REQ_RRHSP (1 << 4)
-#define INCA_IP_WDT_RST_REQ_RRFPI (1 << 3)
-#define INCA_IP_WDT_RST_REQ_RREXT (1 << 2)
-#define INCA_IP_WDT_RST_REQ_RRDSP (1 << 1)
-#define INCA_IP_WDT_RST_REQ_RRCPU (1 << 0)
-
-/***NMI Status Register***/
-#define INCA_IP_WDT_NMISR ((volatile u32*)(INCA_IP_WDT+ 0x002C))
-#define INCA_IP_WDT_NMISR_NMIWDT (1 << 2)
-#define INCA_IP_WDT_NMISR_NMIPLL (1 << 1)
-#define INCA_IP_WDT_NMISR_NMIEXT (1 << 0)
-
-/***Manufacturer Identification Register***/
-#define INCA_IP_WDT_MANID ((volatile u32*)(INCA_IP_WDT+ 0x0070))
-#define INCA_IP_WDT_MANID_MANUF (value) (((( 1 << 11) - 1) & (value)) << 5)
-
-/***Chip Identification Register***/
-#define INCA_IP_WDT_CHIPID ((volatile u32*)(INCA_IP_WDT+ 0x0074))
-#define INCA_IP_WDT_CHIPID_VERSION (value) (((( 1 << 4) - 1) & (value)) << 28)
-#define INCA_IP_WDT_CHIPID_PART_NUMBER (value) (((( 1 << 16) - 1) & (value)) << 12)
-#define INCA_IP_WDT_CHIPID_MANID (value) (((( 1 << 11) - 1) & (value)) << 1)
-
-/***Redesign Tracing Identification Register***/
-#define INCA_IP_WDT_RTID ((volatile u32*)(INCA_IP_WDT+ 0x0078))
-#define INCA_IP_WDT_RTID_LC (1 << 15)
-#define INCA_IP_WDT_RTID_RIX (value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***Watchdog Timer Control Register 0***/
-#define INCA_IP_WDT_WDT_CON0 ((volatile u32*)(INCA_IP_WDT+ 0x0020))
-
-/***Watchdog Timer Control Register 1***/
-#define INCA_IP_WDT_WDT_CON1 ((volatile u32*)(INCA_IP_WDT+ 0x0024))
-#define INCA_IP_WDT_WDT_CON1_WDTDR (1 << 3)
-#define INCA_IP_WDT_WDT_CON1_WDTIR (1 << 2)
-
-/***Watchdog Timer Status Register***/
-#define INCA_IP_WDT_WDT_SR ((volatile u32*)(INCA_IP_WDT+ 0x0028))
-#define INCA_IP_WDT_WDT_SR_WDTTIM (value) (((( 1 << 16) - 1) & (value)) << 16)
-#define INCA_IP_WDT_WDT_SR_WDTPR (1 << 5)
-#define INCA_IP_WDT_WDT_SR_WDTTO (1 << 4)
-#define INCA_IP_WDT_WDT_SR_WDTDS (1 << 3)
-#define INCA_IP_WDT_WDT_SR_WDTIS (1 << 2)
-#define INCA_IP_WDT_WDT_SR_WDTOE (1 << 1)
-#define INCA_IP_WDT_WDT_SR_WDTAE (1 << 0)
-
-/***********************************************************************/
-/* Module : CGU register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_CGU (0xBF107000)
-/***********************************************************************/
-
-
-/***CGU PLL1 Control Register***/
-#define INCA_IP_CGU_CGU_PLL1CR ((volatile u32*)(INCA_IP_CGU+ 0x0008))
-#define INCA_IP_CGU_CGU_PLL1CR_SWRST (1 << 31)
-#define INCA_IP_CGU_CGU_PLL1CR_EN (1 << 30)
-#define INCA_IP_CGU_CGU_PLL1CR_NDIV (value) (((( 1 << 6) - 1) & (value)) << 16)
-#define INCA_IP_CGU_CGU_PLL1CR_MDIV (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***CGU PLL0 Control Register***/
-#define INCA_IP_CGU_CGU_PLL0CR ((volatile u32*)(INCA_IP_CGU+ 0x0000))
-#define INCA_IP_CGU_CGU_PLL0CR_SWRST (1 << 31)
-#define INCA_IP_CGU_CGU_PLL0CR_EN (1 << 30)
-#define INCA_IP_CGU_CGU_PLL0CR_NDIV (value) (((( 1 << 6) - 1) & (value)) << 16)
-#define INCA_IP_CGU_CGU_PLL0CR_MDIV (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***CGU PLL0 Status Register***/
-#define INCA_IP_CGU_CGU_PLL0SR ((volatile u32*)(INCA_IP_CGU+ 0x0004))
-#define INCA_IP_CGU_CGU_PLL0SR_LOCK (1 << 31)
-#define INCA_IP_CGU_CGU_PLL0SR_RCF (1 << 29)
-#define INCA_IP_CGU_CGU_PLL0SR_PLLBYP (1 << 15)
-
-/***CGU PLL1 Status Register***/
-#define INCA_IP_CGU_CGU_PLL1SR ((volatile u32*)(INCA_IP_CGU+ 0x000C))
-#define INCA_IP_CGU_CGU_PLL1SR_LOCK (1 << 31)
-#define INCA_IP_CGU_CGU_PLL1SR_RCF (1 << 29)
-#define INCA_IP_CGU_CGU_PLL1SR_PLLBYP (1 << 15)
-
-/***CGU Divider Control Register***/
-#define INCA_IP_CGU_CGU_DIVCR ((volatile u32*)(INCA_IP_CGU+ 0x0010))
-
-/***CGU Multiplexer Control Register***/
-#define INCA_IP_CGU_CGU_MUXCR ((volatile u32*)(INCA_IP_CGU+ 0x0014))
-#define INCA_IP_CGU_CGU_MUXCR_SWRST (1 << 31)
-#define INCA_IP_CGU_CGU_MUXCR_MUXII (1 << 1)
-#define INCA_IP_CGU_CGU_MUXCR_MUXI (1 << 0)
-
-/***CGU Fractional Divider Control Register***/
-#define INCA_IP_CGU_CGU_FDCR ((volatile u32*)(INCA_IP_CGU+ 0x0018))
-#define INCA_IP_CGU_CGU_FDCR_FDEN (1 << 31)
-#define INCA_IP_CGU_CGU_FDCR_INTEGER (value) (((( 1 << 12) - 1) & (value)) << 16)
-#define INCA_IP_CGU_CGU_FDCR_FRACTION (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***********************************************************************/
-/* Module : PMU register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_PMU (0xBF102000)
-/***********************************************************************/
-
-
-/***PM Global Enable Register***/
-#define INCA_IP_PMU_PM_GEN ((volatile u32*)(INCA_IP_PMU+ 0x0000))
-#define INCA_IP_PMU_PM_GEN_EN16 (1 << 16)
-#define INCA_IP_PMU_PM_GEN_EN15 (1 << 15)
-#define INCA_IP_PMU_PM_GEN_EN14 (1 << 14)
-#define INCA_IP_PMU_PM_GEN_EN13 (1 << 13)
-#define INCA_IP_PMU_PM_GEN_EN12 (1 << 12)
-#define INCA_IP_PMU_PM_GEN_EN11 (1 << 11)
-#define INCA_IP_PMU_PM_GEN_EN10 (1 << 10)
-#define INCA_IP_PMU_PM_GEN_EN9 (1 << 9)
-#define INCA_IP_PMU_PM_GEN_EN8 (1 << 8)
-#define INCA_IP_PMU_PM_GEN_EN7 (1 << 7)
-#define INCA_IP_PMU_PM_GEN_EN6 (1 << 6)
-#define INCA_IP_PMU_PM_GEN_EN5 (1 << 5)
-#define INCA_IP_PMU_PM_GEN_EN4 (1 << 4)
-#define INCA_IP_PMU_PM_GEN_EN3 (1 << 3)
-#define INCA_IP_PMU_PM_GEN_EN2 (1 << 2)
-#define INCA_IP_PMU_PM_GEN_EN0 (1 << 0)
-
-/***PM Power Down Enable Register***/
-#define INCA_IP_PMU_PM_PDEN ((volatile u32*)(INCA_IP_PMU+ 0x0008))
-#define INCA_IP_PMU_PM_PDEN_EN16 (1 << 16)
-#define INCA_IP_PMU_PM_PDEN_EN15 (1 << 15)
-#define INCA_IP_PMU_PM_PDEN_EN14 (1 << 14)
-#define INCA_IP_PMU_PM_PDEN_EN13 (1 << 13)
-#define INCA_IP_PMU_PM_PDEN_EN12 (1 << 12)
-#define INCA_IP_PMU_PM_PDEN_EN11 (1 << 11)
-#define INCA_IP_PMU_PM_PDEN_EN10 (1 << 10)
-#define INCA_IP_PMU_PM_PDEN_EN9 (1 << 9)
-#define INCA_IP_PMU_PM_PDEN_EN8 (1 << 8)
-#define INCA_IP_PMU_PM_PDEN_EN7 (1 << 7)
-#define INCA_IP_PMU_PM_PDEN_EN5 (1 << 5)
-#define INCA_IP_PMU_PM_PDEN_EN4 (1 << 4)
-#define INCA_IP_PMU_PM_PDEN_EN3 (1 << 3)
-#define INCA_IP_PMU_PM_PDEN_EN2 (1 << 2)
-#define INCA_IP_PMU_PM_PDEN_EN0 (1 << 0)
-
-/***PM Wake-Up from Power Down Register***/
-#define INCA_IP_PMU_PM_WUP ((volatile u32*)(INCA_IP_PMU+ 0x0010))
-#define INCA_IP_PMU_PM_WUP_WUP16 (1 << 16)
-#define INCA_IP_PMU_PM_WUP_WUP15 (1 << 15)
-#define INCA_IP_PMU_PM_WUP_WUP14 (1 << 14)
-#define INCA_IP_PMU_PM_WUP_WUP13 (1 << 13)
-#define INCA_IP_PMU_PM_WUP_WUP12 (1 << 12)
-#define INCA_IP_PMU_PM_WUP_WUP11 (1 << 11)
-#define INCA_IP_PMU_PM_WUP_WUP10 (1 << 10)
-#define INCA_IP_PMU_PM_WUP_WUP9 (1 << 9)
-#define INCA_IP_PMU_PM_WUP_WUP8 (1 << 8)
-#define INCA_IP_PMU_PM_WUP_WUP7 (1 << 7)
-#define INCA_IP_PMU_PM_WUP_WUP5 (1 << 5)
-#define INCA_IP_PMU_PM_WUP_WUP4 (1 << 4)
-#define INCA_IP_PMU_PM_WUP_WUP3 (1 << 3)
-#define INCA_IP_PMU_PM_WUP_WUP2 (1 << 2)
-#define INCA_IP_PMU_PM_WUP_WUP0 (1 << 0)
-
-/***PM Control Register***/
-#define INCA_IP_PMU_PM_CR ((volatile u32*)(INCA_IP_PMU+ 0x0014))
-#define INCA_IP_PMU_PM_CR_AWEN (1 << 31)
-#define INCA_IP_PMU_PM_CR_SWRST (1 << 30)
-#define INCA_IP_PMU_PM_CR_SWCR (1 << 2)
-#define INCA_IP_PMU_PM_CR_CRD (value) (((( 1 << 2) - 1) & (value)) << 0)
-
-/***********************************************************************/
-/* Module : BCU register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_BCU (0xB8000100)
-/***********************************************************************/
-
-
-/***BCU Control Register (0010H)***/
-#define INCA_IP_BCU_BCU_CON ((volatile u32*)(INCA_IP_BCU+ 0x0010))
-#define INCA_IP_BCU_BCU_CON_SPC (value) (((( 1 << 8) - 1) & (value)) << 24)
-#define INCA_IP_BCU_BCU_CON_SPE (1 << 19)
-#define INCA_IP_BCU_BCU_CON_PSE (1 << 18)
-#define INCA_IP_BCU_BCU_CON_DBG (1 << 16)
-#define INCA_IP_BCU_BCU_CON_TOUT (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***BCU Error Control Capture Register (0020H)***/
-#define INCA_IP_BCU_BCU_ECON ((volatile u32*)(INCA_IP_BCU+ 0x0020))
-#define INCA_IP_BCU_BCU_ECON_TAG (value) (((( 1 << 4) - 1) & (value)) << 24)
-#define INCA_IP_BCU_BCU_ECON_RDN (1 << 23)
-#define INCA_IP_BCU_BCU_ECON_WRN (1 << 22)
-#define INCA_IP_BCU_BCU_ECON_SVM (1 << 21)
-#define INCA_IP_BCU_BCU_ECON_ACK (value) (((( 1 << 2) - 1) & (value)) << 19)
-#define INCA_IP_BCU_BCU_ECON_ABT (1 << 18)
-#define INCA_IP_BCU_BCU_ECON_RDY (1 << 17)
-#define INCA_IP_BCU_BCU_ECON_TOUT (1 << 16)
-#define INCA_IP_BCU_BCU_ECON_ERRCNT (value) (((( 1 << 16) - 1) & (value)) << 0)
-#define INCA_IP_BCU_BCU_ECON_OPC (value) (((( 1 << 4) - 1) & (value)) << 28)
-
-/***BCU Error Address Capture Register (0024 H)***/
-#define INCA_IP_BCU_BCU_EADD ((volatile u32*)(INCA_IP_BCU+ 0x0024))
-#define INCA_IP_BCU_BCU_EADD_FPIADR
-
-/***BCU Error Data Capture Register (0028H)***/
-#define INCA_IP_BCU_BCU_EDAT ((volatile u32*)(INCA_IP_BCU+ 0x0028))
-#define INCA_IP_BCU_BCU_EDAT_FPIDAT
-
-/***********************************************************************/
-/* Module : MBC register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_MBC (0xBF103000)
-/***********************************************************************/
-
-
-/***Mailbox CPU Configuration Register***/
-#define INCA_IP_MBC_MBC_CFG ((volatile u32*)(INCA_IP_MBC+ 0x0080))
-#define INCA_IP_MBC_MBC_CFG_SWAP (value) (((( 1 << 2) - 1) & (value)) << 6)
-#define INCA_IP_MBC_MBC_CFG_RES (1 << 5)
-#define INCA_IP_MBC_MBC_CFG_FWID (value) (((( 1 << 4) - 1) & (value)) << 1)
-#define INCA_IP_MBC_MBC_CFG_SIZE (1 << 0)
-
-/***Mailbox CPU Interrupt Status Register***/
-#define INCA_IP_MBC_MBC_ISR ((volatile u32*)(INCA_IP_MBC+ 0x0084))
-#define INCA_IP_MBC_MBC_ISR_B3DA (1 << 31)
-#define INCA_IP_MBC_MBC_ISR_B2DA (1 << 30)
-#define INCA_IP_MBC_MBC_ISR_B1E (1 << 29)
-#define INCA_IP_MBC_MBC_ISR_B0E (1 << 28)
-#define INCA_IP_MBC_MBC_ISR_WDT (1 << 27)
-#define INCA_IP_MBC_MBC_ISR_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0)
-
-/***Mailbox CPU Mask Register***/
-#define INCA_IP_MBC_MBC_MSK ((volatile u32*)(INCA_IP_MBC+ 0x0088))
-#define INCA_IP_MBC_MBC_MSK_B3DA (1 << 31)
-#define INCA_IP_MBC_MBC_MSK_B2DA (1 << 30)
-#define INCA_IP_MBC_MBC_MSK_B1E (1 << 29)
-#define INCA_IP_MBC_MBC_MSK_B0E (1 << 28)
-#define INCA_IP_MBC_MBC_MSK_WDT (1 << 27)
-#define INCA_IP_MBC_MBC_MSK_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0)
-
-/***Mailbox CPU Mask 01 Register***/
-#define INCA_IP_MBC_MBC_MSK01 ((volatile u32*)(INCA_IP_MBC+ 0x008C))
-#define INCA_IP_MBC_MBC_MSK01_B3DA (1 << 31)
-#define INCA_IP_MBC_MBC_MSK01_B2DA (1 << 30)
-#define INCA_IP_MBC_MBC_MSK01_B1E (1 << 29)
-#define INCA_IP_MBC_MBC_MSK01_B0E (1 << 28)
-#define INCA_IP_MBC_MBC_MSK01_WDT (1 << 27)
-#define INCA_IP_MBC_MBC_MSK01_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0)
-
-/***Mailbox CPU Mask 10 Register***/
-#define INCA_IP_MBC_MBC_MSK10 ((volatile u32*)(INCA_IP_MBC+ 0x0090))
-#define INCA_IP_MBC_MBC_MSK10_B3DA (1 << 31)
-#define INCA_IP_MBC_MBC_MSK10_B2DA (1 << 30)
-#define INCA_IP_MBC_MBC_MSK10_B1E (1 << 29)
-#define INCA_IP_MBC_MBC_MSK10_B0E (1 << 28)
-#define INCA_IP_MBC_MBC_MSK10_WDT (1 << 27)
-#define INCA_IP_MBC_MBC_MSK10_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0)
-
-/***Mailbox CPU Short Command Register***/
-#define INCA_IP_MBC_MBC_CMD ((volatile u32*)(INCA_IP_MBC+ 0x0094))
-#define INCA_IP_MBC_MBC_CMD_CS270 (value) (((( 1 << 28) - 1) & (value)) << 0)
-
-/***Mailbox CPU Input Data of Buffer 0***/
-#define INCA_IP_MBC_MBC_ID0 ((volatile u32*)(INCA_IP_MBC+ 0x0000))
-#define INCA_IP_MBC_MBC_ID0_INDATA
-
-/***Mailbox CPU Input Data of Buffer 1***/
-#define INCA_IP_MBC_MBC_ID1 ((volatile u32*)(INCA_IP_MBC+ 0x0020))
-#define INCA_IP_MBC_MBC_ID1_INDATA
-
-/***Mailbox CPU Output Data of Buffer 2***/
-#define INCA_IP_MBC_MBC_OD2 ((volatile u32*)(INCA_IP_MBC+ 0x0040))
-#define INCA_IP_MBC_MBC_OD2_OUTDATA
-
-/***Mailbox CPU Output Data of Buffer 3***/
-#define INCA_IP_MBC_MBC_OD3 ((volatile u32*)(INCA_IP_MBC+ 0x0060))
-#define INCA_IP_MBC_MBC_OD3_OUTDATA
-
-/***Mailbox CPU Control Register of Buffer 0***/
-#define INCA_IP_MBC_MBC_CR0 ((volatile u32*)(INCA_IP_MBC+ 0x0004))
-#define INCA_IP_MBC_MBC_CR0_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***Mailbox CPU Control Register of Buffer 1***/
-#define INCA_IP_MBC_MBC_CR1 ((volatile u32*)(INCA_IP_MBC+ 0x0024))
-#define INCA_IP_MBC_MBC_CR1_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***Mailbox CPU Control Register of Buffer 2***/
-#define INCA_IP_MBC_MBC_CR2 ((volatile u32*)(INCA_IP_MBC+ 0x0044))
-#define INCA_IP_MBC_MBC_CR2_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***Mailbox CPU Control Register of Buffer 3***/
-#define INCA_IP_MBC_MBC_CR3 ((volatile u32*)(INCA_IP_MBC+ 0x0064))
-#define INCA_IP_MBC_MBC_CR3_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***Mailbox CPU Free Space of Buffer 0***/
-#define INCA_IP_MBC_MBC_FS0 ((volatile u32*)(INCA_IP_MBC+ 0x0008))
-#define INCA_IP_MBC_MBC_FS0_FS
-
-/***Mailbox CPU Free Space of Buffer 1***/
-#define INCA_IP_MBC_MBC_FS1 ((volatile u32*)(INCA_IP_MBC+ 0x0028))
-#define INCA_IP_MBC_MBC_FS1_FS
-
-/***Mailbox CPU Free Space of Buffer 2***/
-#define INCA_IP_MBC_MBC_FS2 ((volatile u32*)(INCA_IP_MBC+ 0x0048))
-#define INCA_IP_MBC_MBC_FS2_FS
-
-/***Mailbox CPU Free Space of Buffer 3***/
-#define INCA_IP_MBC_MBC_FS3 ((volatile u32*)(INCA_IP_MBC+ 0x0068))
-#define INCA_IP_MBC_MBC_FS3_FS
-
-/***Mailbox CPU Data Available in Buffer 0***/
-#define INCA_IP_MBC_MBC_DA0 ((volatile u32*)(INCA_IP_MBC+ 0x000C))
-#define INCA_IP_MBC_MBC_DA0_DA
-
-/***Mailbox CPU Data Available in Buffer 1***/
-#define INCA_IP_MBC_MBC_DA1 ((volatile u32*)(INCA_IP_MBC+ 0x002C))
-#define INCA_IP_MBC_MBC_DA1_DA
-
-/***Mailbox CPU Data Available in Buffer 2***/
-#define INCA_IP_MBC_MBC_DA2 ((volatile u32*)(INCA_IP_MBC+ 0x004C))
-#define INCA_IP_MBC_MBC_DA2_DA
-
-/***Mailbox CPU Data Available in Buffer 3***/
-#define INCA_IP_MBC_MBC_DA3 ((volatile u32*)(INCA_IP_MBC+ 0x006C))
-#define INCA_IP_MBC_MBC_DA3_DA
-
-/***Mailbox CPU Input Absolute Pointer of Buffer 0***/
-#define INCA_IP_MBC_MBC_IABS0 ((volatile u32*)(INCA_IP_MBC+ 0x0010))
-#define INCA_IP_MBC_MBC_IABS0_IABS
-
-/***Mailbox CPU Input Absolute Pointer of Buffer 1***/
-#define INCA_IP_MBC_MBC_IABS1 ((volatile u32*)(INCA_IP_MBC+ 0x0030))
-#define INCA_IP_MBC_MBC_IABS1_IABS
-
-/***Mailbox CPU Input Absolute Pointer of Buffer 2***/
-#define INCA_IP_MBC_MBC_IABS2 ((volatile u32*)(INCA_IP_MBC+ 0x0050))
-#define INCA_IP_MBC_MBC_IABS2_IABS
-
-/***Mailbox CPU Input Absolute Pointer of Buffer 3***/
-#define INCA_IP_MBC_MBC_IABS3 ((volatile u32*)(INCA_IP_MBC+ 0x0070))
-#define INCA_IP_MBC_MBC_IABS3_IABS
-
-/***Mailbox CPU Input Temporary Pointer of Buffer 0***/
-#define INCA_IP_MBC_MBC_ITMP0 ((volatile u32*)(INCA_IP_MBC+ 0x0014))
-#define INCA_IP_MBC_MBC_ITMP0_ITMP
-
-/***Mailbox CPU Input Temporary Pointer of Buffer 1***/
-#define INCA_IP_MBC_MBC_ITMP1 ((volatile u32*)(INCA_IP_MBC+ 0x0034))
-#define INCA_IP_MBC_MBC_ITMP1_ITMP
-
-/***Mailbox CPU Input Temporary Pointer of Buffer 2***/
-#define INCA_IP_MBC_MBC_ITMP2 ((volatile u32*)(INCA_IP_MBC+ 0x0054))
-#define INCA_IP_MBC_MBC_ITMP2_ITMP
-
-/***Mailbox CPU Input Temporary Pointer of Buffer 3***/
-#define INCA_IP_MBC_MBC_ITMP3 ((volatile u32*)(INCA_IP_MBC+ 0x0074))
-#define INCA_IP_MBC_MBC_ITMP3_ITMP
-
-/***Mailbox CPU Output Absolute Pointer of Buffer 0***/
-#define INCA_IP_MBC_MBC_OABS0 ((volatile u32*)(INCA_IP_MBC+ 0x0018))
-#define INCA_IP_MBC_MBC_OABS0_OABS
-
-/***Mailbox CPU Output Absolute Pointer of Buffer 1***/
-#define INCA_IP_MBC_MBC_OABS1 ((volatile u32*)(INCA_IP_MBC+ 0x0038))
-#define INCA_IP_MBC_MBC_OABS1_OABS
-
-/***Mailbox CPU Output Absolute Pointer of Buffer 2***/
-#define INCA_IP_MBC_MBC_OABS2 ((volatile u32*)(INCA_IP_MBC+ 0x0058))
-#define INCA_IP_MBC_MBC_OABS2_OABS
-
-/***Mailbox CPU Output Absolute Pointer of Buffer 3***/
-#define INCA_IP_MBC_MBC_OABS3 ((volatile u32*)(INCA_IP_MBC+ 0x0078))
-#define INCA_IP_MBC_MBC_OABS3_OABS
-
-/***Mailbox CPU Output Temporary Pointer of Buffer 0***/
-#define INCA_IP_MBC_MBC_OTMP0 ((volatile u32*)(INCA_IP_MBC+ 0x001C))
-#define INCA_IP_MBC_MBC_OTMP0_OTMP
-
-/***Mailbox CPU Output Temporary Pointer of Buffer 1***/
-#define INCA_IP_MBC_MBC_OTMP1 ((volatile u32*)(INCA_IP_MBC+ 0x003C))
-#define INCA_IP_MBC_MBC_OTMP1_OTMP
-
-/***Mailbox CPU Output Temporary Pointer of Buffer 2***/
-#define INCA_IP_MBC_MBC_OTMP2 ((volatile u32*)(INCA_IP_MBC+ 0x005C))
-#define INCA_IP_MBC_MBC_OTMP2_OTMP
-
-/***Mailbox CPU Output Temporary Pointer of Buffer 3***/
-#define INCA_IP_MBC_MBC_OTMP3 ((volatile u32*)(INCA_IP_MBC+ 0x007C))
-#define INCA_IP_MBC_MBC_OTMP3_OTMP
-
-/***DSP Control Register***/
-#define INCA_IP_MBC_DCTRL ((volatile u32*)(INCA_IP_MBC+ 0x00A0))
-#define INCA_IP_MBC_DCTRL_BA (1 << 0)
-#define INCA_IP_MBC_DCTRL_BMOD (value) (((( 1 << 3) - 1) & (value)) << 1)
-#define INCA_IP_MBC_DCTRL_IDL (1 << 4)
-#define INCA_IP_MBC_DCTRL_RES (1 << 15)
-
-/***DSP Status Register***/
-#define INCA_IP_MBC_DSTA ((volatile u32*)(INCA_IP_MBC+ 0x00A4))
-#define INCA_IP_MBC_DSTA_IDLE (1 << 0)
-#define INCA_IP_MBC_DSTA_PD (1 << 1)
-
-/***DSP Test 1 Register***/
-#define INCA_IP_MBC_DTST1 ((volatile u32*)(INCA_IP_MBC+ 0x00A8))
-#define INCA_IP_MBC_DTST1_ABORT (1 << 0)
-#define INCA_IP_MBC_DTST1_HWF32 (1 << 1)
-#define INCA_IP_MBC_DTST1_HWF4M (1 << 2)
-#define INCA_IP_MBC_DTST1_HWFOP (1 << 3)
-
-/***********************************************************************/
-/* Module : Switch register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_Switch (0xBF104000)
-/***********************************************************************/
-
-
-/***Unknown Destination Register***/
-#define INCA_IP_Switch_UN_DEST ((volatile u32*)(INCA_IP_Switch+ 0x0000))
-#define INCA_IP_Switch_UN_DEST_CB (1 << 8)
-#define INCA_IP_Switch_UN_DEST_LB (1 << 7)
-#define INCA_IP_Switch_UN_DEST_PB (1 << 6)
-#define INCA_IP_Switch_UN_DEST_CM (1 << 5)
-#define INCA_IP_Switch_UN_DEST_LM (1 << 4)
-#define INCA_IP_Switch_UN_DEST_PM (1 << 3)
-#define INCA_IP_Switch_UN_DEST_CU (1 << 2)
-#define INCA_IP_Switch_UN_DEST_LU (1 << 1)
-#define INCA_IP_Switch_UN_DEST_PU (1 << 0)
-
-/***VLAN Control Register***/
-#define INCA_IP_Switch_VLAN_CTRL ((volatile u32*)(INCA_IP_Switch+ 0x0004))
-#define INCA_IP_Switch_VLAN_CTRL_SC (1 << 6)
-#define INCA_IP_Switch_VLAN_CTRL_SL (1 << 5)
-#define INCA_IP_Switch_VLAN_CTRL_SP (1 << 4)
-#define INCA_IP_Switch_VLAN_CTRL_TC (1 << 3)
-#define INCA_IP_Switch_VLAN_CTRL_TL (1 << 2)
-#define INCA_IP_Switch_VLAN_CTRL_TP (1 << 1)
-#define INCA_IP_Switch_VLAN_CTRL_VA (1 << 0)
-
-/***PC VLAN Configuration Register***/
-#define INCA_IP_Switch_PC_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x0008))
-#define INCA_IP_Switch_PC_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 12)
-#define INCA_IP_Switch_PC_VLAN_VLAN_ID (value) (((( 1 << 12) - 1) & (value)) << 0)
-
-/***LAN VLAN Configuration Register***/
-#define INCA_IP_Switch_LAN_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x000C))
-#define INCA_IP_Switch_LAN_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 12)
-#define INCA_IP_Switch_LAN_VLAN_VLAN_ID (value) (((( 1 << 12) - 1) & (value)) << 0)
-
-/***CPU VLAN Configuration Register***/
-#define INCA_IP_Switch_CPU_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x0010))
-#define INCA_IP_Switch_CPU_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 12)
-#define INCA_IP_Switch_CPU_VLAN_VLAN_ID (value) (((( 1 << 12) - 1) & (value)) << 0)
-
-/***Priority CoS Mapping Register***/
-#define INCA_IP_Switch_PRI_CoS ((volatile u32*)(INCA_IP_Switch+ 0x0014))
-#define INCA_IP_Switch_PRI_CoS_P7 (1 << 7)
-#define INCA_IP_Switch_PRI_CoS_P6 (1 << 6)
-#define INCA_IP_Switch_PRI_CoS_P5 (1 << 5)
-#define INCA_IP_Switch_PRI_CoS_P4 (1 << 4)
-#define INCA_IP_Switch_PRI_CoS_P3 (1 << 3)
-#define INCA_IP_Switch_PRI_CoS_P2 (1 << 2)
-#define INCA_IP_Switch_PRI_CoS_P1 (1 << 1)
-#define INCA_IP_Switch_PRI_CoS_P0 (1 << 0)
-
-/***Spanning Tree Port Status Register***/
-#define INCA_IP_Switch_ST_PT ((volatile u32*)(INCA_IP_Switch+ 0x0018))
-#define INCA_IP_Switch_ST_PT_CPS (value) (((( 1 << 2) - 1) & (value)) << 4)
-#define INCA_IP_Switch_ST_PT_LPS (value) (((( 1 << 2) - 1) & (value)) << 2)
-#define INCA_IP_Switch_ST_PT_PPS (value) (((( 1 << 2) - 1) & (value)) << 0)
-
-/***ARL Control Register***/
-#define INCA_IP_Switch_ARL_CTL ((volatile u32*)(INCA_IP_Switch+ 0x001C))
-#define INCA_IP_Switch_ARL_CTL_CHCC (1 << 15)
-#define INCA_IP_Switch_ARL_CTL_CHCL (1 << 14)
-#define INCA_IP_Switch_ARL_CTL_CHCP (1 << 13)
-#define INCA_IP_Switch_ARL_CTL_CC (1 << 12)
-#define INCA_IP_Switch_ARL_CTL_CL (1 << 11)
-#define INCA_IP_Switch_ARL_CTL_CP (1 << 10)
-#define INCA_IP_Switch_ARL_CTL_CG (1 << 9)
-#define INCA_IP_Switch_ARL_CTL_PS (1 << 8)
-#define INCA_IP_Switch_ARL_CTL_MRO (1 << 7)
-#define INCA_IP_Switch_ARL_CTL_SRC (1 << 6)
-#define INCA_IP_Switch_ARL_CTL_ATS (1 << 5)
-#define INCA_IP_Switch_ARL_CTL_AGE_TICK_SEL (value) (((( 1 << 3) - 1) & (value)) << 2)
-#define INCA_IP_Switch_ARL_CTL_MAF (1 << 1)
-#define INCA_IP_Switch_ARL_CTL_ENL (1 << 0)
-#define INCA_IP_Switch_ARL_CTL_Res (value) (((( 1 << 19) - 1) & (value)) << 13)
-
-/***CPU Access Control Register***/
-#define INCA_IP_Switch_CPU_ACTL ((volatile u32*)(INCA_IP_Switch+ 0x0020))
-#define INCA_IP_Switch_CPU_ACTL_RA (1 << 31)
-#define INCA_IP_Switch_CPU_ACTL_RW (1 << 30)
-#define INCA_IP_Switch_CPU_ACTL_Res (value) (((( 1 << 21) - 1) & (value)) << 9)
-#define INCA_IP_Switch_CPU_ACTL_AVA (1 << 8)
-#define INCA_IP_Switch_CPU_ACTL_IDX (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***CPU Access Data Register 1***/
-#define INCA_IP_Switch_DATA1 ((volatile u32*)(INCA_IP_Switch+ 0x0024))
-#define INCA_IP_Switch_DATA1_Data (value) (((( 1 << 24) - 1) & (value)) << 0)
-
-/***CPU Access Data Register 2***/
-#define INCA_IP_Switch_DATA2 ((volatile u32*)(INCA_IP_Switch+ 0x0028))
-#define INCA_IP_Switch_DATA2_Data
-
-/***CPU Port Control Register***/
-#define INCA_IP_Switch_CPU_PCTL ((volatile u32*)(INCA_IP_Switch+ 0x002C))
-#define INCA_IP_Switch_CPU_PCTL_DA_PORTS (value) (((( 1 << 3) - 1) & (value)) << 11)
-#define INCA_IP_Switch_CPU_PCTL_DAC (1 << 10)
-#define INCA_IP_Switch_CPU_PCTL_MA_STATE (value) (((( 1 << 3) - 1) & (value)) << 7)
-#define INCA_IP_Switch_CPU_PCTL_MAM (1 << 6)
-#define INCA_IP_Switch_CPU_PCTL_MA_Ports (value) (((( 1 << 3) - 1) & (value)) << 3)
-#define INCA_IP_Switch_CPU_PCTL_MAC (1 << 2)
-#define INCA_IP_Switch_CPU_PCTL_EML (1 << 1)
-#define INCA_IP_Switch_CPU_PCTL_EDL (1 << 0)
-#define INCA_IP_Switch_CPU_PCTL_Res (value) (((( 1 << 18) - 1) & (value)) << 14)
-
-/***DSCP CoS Mapping Register 1***/
-#define INCA_IP_Switch_DSCP_COS1 ((volatile u32*)(INCA_IP_Switch+ 0x0030))
-#define INCA_IP_Switch_DSCP_COS1_DSCP
-
-/***DSCP CoS Mapping Register 1***/
-#define INCA_IP_Switch_DSCP_COS2 ((volatile u32*)(INCA_IP_Switch+ 0x0034))
-#define INCA_IP_Switch_DSCP_COS2_DSCP
-
-/***PC WFQ Control Register***/
-#define INCA_IP_Switch_PC_WFQ_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0080))
-#define INCA_IP_Switch_PC_WFQ_CTL_P1 (1 << 9)
-#define INCA_IP_Switch_PC_WFQ_CTL_P0 (1 << 8)
-#define INCA_IP_Switch_PC_WFQ_CTL_WT1 (value) (((( 1 << 3) - 1) & (value)) << 5)
-#define INCA_IP_Switch_PC_WFQ_CTL_WT0 (value) (((( 1 << 3) - 1) & (value)) << 2)
-#define INCA_IP_Switch_PC_WFQ_CTL_SCH_SEL (value) (((( 1 << 2) - 1) & (value)) << 0)
-
-/***PC TX Control Register***/
-#define INCA_IP_Switch_PC_TX_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0084))
-#define INCA_IP_Switch_PC_TX_CTL_ELR (1 << 1)
-#define INCA_IP_Switch_PC_TX_CTL_EER (1 << 0)
-
-/***LAN WFQ Control Register***/
-#define INCA_IP_Switch_LAN_WFQ_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0100))
-#define INCA_IP_Switch_LAN_WFQ_CTL_P1 (1 << 9)
-#define INCA_IP_Switch_LAN_WFQ_CTL_P0 (1 << 8)
-#define INCA_IP_Switch_LAN_WFQ_CTL_WT1 (value) (((( 1 << 3) - 1) & (value)) << 5)
-#define INCA_IP_Switch_LAN_WFQ_CTL_WT0 (value) (((( 1 << 3) - 1) & (value)) << 2)
-#define INCA_IP_Switch_LAN_WFQ_CTL_SCH_SEL (value) (((( 1 << 2) - 1) & (value)) << 0)
-
-/***LAN TX Control Register***/
-#define INCA_IP_Switch_LAN_TX_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0104))
-#define INCA_IP_Switch_LAN_TX_CTL_ELR (1 << 1)
-#define INCA_IP_Switch_LAN_TX_CTL_EER (1 << 0)
-
-/***CPU WFQ Control Register***/
-#define INCA_IP_Switch_CPU_WFQ_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0180))
-#define INCA_IP_Switch_CPU_WFQ_CTL_P1 (1 << 9)
-#define INCA_IP_Switch_CPU_WFQ_CTL_P0 (1 << 8)
-#define INCA_IP_Switch_CPU_WFQ_CTL_WT1 (value) (((( 1 << 3) - 1) & (value)) << 5)
-#define INCA_IP_Switch_CPU_WFQ_CTL_WT0 (value) (((( 1 << 3) - 1) & (value)) << 2)
-#define INCA_IP_Switch_CPU_WFQ_CTL_SCH_SEL (value) (((( 1 << 2) - 1) & (value)) << 0)
-
-/***PM PC RX Watermark Register***/
-#define INCA_IP_Switch_PC_WM ((volatile u32*)(INCA_IP_Switch+ 0x0200))
-#define INCA_IP_Switch_PC_WM_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24)
-#define INCA_IP_Switch_PC_WM_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16)
-#define INCA_IP_Switch_PC_WM_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_Switch_PC_WM_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***PM LAN RX Watermark Register***/
-#define INCA_IP_Switch_LAN_WM ((volatile u32*)(INCA_IP_Switch+ 0x0204))
-#define INCA_IP_Switch_LAN_WM_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24)
-#define INCA_IP_Switch_LAN_WM_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16)
-#define INCA_IP_Switch_LAN_WM_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_Switch_LAN_WM_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***PM CPU RX Watermark Register***/
-#define INCA_IP_Switch_CPU_WM ((volatile u32*)(INCA_IP_Switch+ 0x0208))
-#define INCA_IP_Switch_CPU_WM_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24)
-#define INCA_IP_Switch_CPU_WM_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16)
-#define INCA_IP_Switch_CPU_WM_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_Switch_CPU_WM_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***PM CPU RX Watermark Register***/
-#define INCA_IP_Switch_GBL_WM ((volatile u32*)(INCA_IP_Switch+ 0x020C))
-#define INCA_IP_Switch_GBL_WM_GBL_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24)
-#define INCA_IP_Switch_GBL_WM_GBL_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16)
-#define INCA_IP_Switch_GBL_WM_GBL_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_Switch_GBL_WM_GBL_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***PM Control Register***/
-#define INCA_IP_Switch_PM_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0210))
-#define INCA_IP_Switch_PM_CTL_GDN (1 << 3)
-#define INCA_IP_Switch_PM_CTL_CDN (1 << 2)
-#define INCA_IP_Switch_PM_CTL_LDN (1 << 1)
-#define INCA_IP_Switch_PM_CTL_PDN (1 << 0)
-
-/***PM Header Control Register***/
-#define INCA_IP_Switch_PMAC_HD_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0280))
-#define INCA_IP_Switch_PMAC_HD_CTL_RL2 (1 << 21)
-#define INCA_IP_Switch_PMAC_HD_CTL_RC (1 << 20)
-#define INCA_IP_Switch_PMAC_HD_CTL_CM (1 << 19)
-#define INCA_IP_Switch_PMAC_HD_CTL_CV (1 << 18)
-#define INCA_IP_Switch_PMAC_HD_CTL_TYPE_LEN (value) (((( 1 << 16) - 1) & (value)) << 2)
-#define INCA_IP_Switch_PMAC_HD_CTL_TAG (1 << 1)
-#define INCA_IP_Switch_PMAC_HD_CTL_ADD (1 << 0)
-
-/***PM Source Address Register 1***/
-#define INCA_IP_Switch_PMAC_SA1 ((volatile u32*)(INCA_IP_Switch+ 0x0284))
-#define INCA_IP_Switch_PMAC_SA1_SA_47_32 (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***PM Source Address Register 2***/
-#define INCA_IP_Switch_PMAC_SA2 ((volatile u32*)(INCA_IP_Switch+ 0x0288))
-#define INCA_IP_Switch_PMAC_SA2_SA_31_0
-
-/***PM Dest Address Register 1***/
-#define INCA_IP_Switch_PMAC_DA1 ((volatile u32*)(INCA_IP_Switch+ 0x028C))
-#define INCA_IP_Switch_PMAC_DA1_DA_47_32 (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***PM Dest Address Register 2***/
-#define INCA_IP_Switch_PMAC_DA2 ((volatile u32*)(INCA_IP_Switch+ 0x0290))
-#define INCA_IP_Switch_PMAC_DA2_DA_31_0
-
-/***PM VLAN Register***/
-#define INCA_IP_Switch_PMAC_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x0294))
-#define INCA_IP_Switch_PMAC_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 13)
-#define INCA_IP_Switch_PMAC_VLAN_CFI (1 << 12)
-#define INCA_IP_Switch_PMAC_VLAN_VLANID (value) (((( 1 << 12) - 1) & (value)) << 0)
-
-/***PM TX IPG Counter Register***/
-#define INCA_IP_Switch_PMAC_TX_IPG ((volatile u32*)(INCA_IP_Switch+ 0x0298))
-#define INCA_IP_Switch_PMAC_TX_IPG_IPGCNT (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***PM RX IPG Counter Register***/
-#define INCA_IP_Switch_PMAC_RX_IPG ((volatile u32*)(INCA_IP_Switch+ 0x029C))
-#define INCA_IP_Switch_PMAC_RX_IPG_IPGCNT (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***Mirror Register***/
-#define INCA_IP_Switch_MRR ((volatile u32*)(INCA_IP_Switch+ 0x0300))
-#define INCA_IP_Switch_MRR_MRR (value) (((( 1 << 2) - 1) & (value)) << 6)
-#define INCA_IP_Switch_MRR_EC (1 << 5)
-#define INCA_IP_Switch_MRR_EL (1 << 4)
-#define INCA_IP_Switch_MRR_EP (1 << 3)
-#define INCA_IP_Switch_MRR_IC (1 << 2)
-#define INCA_IP_Switch_MRR_IL (1 << 1)
-#define INCA_IP_Switch_MRR_IP (1 << 0)
-
-/***Packet Length Register***/
-#define INCA_IP_Switch_PKT_LEN ((volatile u32*)(INCA_IP_Switch+ 0x0304))
-#define INCA_IP_Switch_PKT_LEN_ADD (1 << 11)
-#define INCA_IP_Switch_PKT_LEN_MAX_PKT_LEN (value) (((( 1 << 11) - 1) & (value)) << 0)
-
-/***MDIO Access Register***/
-#define INCA_IP_Switch_MDIO_ACC ((volatile u32*)(INCA_IP_Switch+ 0x0480))
-#define INCA_IP_Switch_MDIO_ACC_RA (1 << 31)
-#define INCA_IP_Switch_MDIO_ACC_RW (1 << 30)
-#define INCA_IP_Switch_MDIO_ACC_PHY_ADDR (value) (((( 1 << 5) - 1) & (value)) << 21)
-#define INCA_IP_Switch_MDIO_ACC_REG_ADDR (value) (((( 1 << 5) - 1) & (value)) << 16)
-#define INCA_IP_Switch_MDIO_ACC_PHY_DATA (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***Ethernet PHY Register***/
-#define INCA_IP_Switch_EPHY ((volatile u32*)(INCA_IP_Switch+ 0x0484))
-#define INCA_IP_Switch_EPHY_SL (1 << 7)
-#define INCA_IP_Switch_EPHY_SP (1 << 6)
-#define INCA_IP_Switch_EPHY_LL (1 << 5)
-#define INCA_IP_Switch_EPHY_LP (1 << 4)
-#define INCA_IP_Switch_EPHY_DL (1 << 3)
-#define INCA_IP_Switch_EPHY_DP (1 << 2)
-#define INCA_IP_Switch_EPHY_PL (1 << 1)
-#define INCA_IP_Switch_EPHY_PP (1 << 0)
-
-/***Pause Write Enable Register***/
-#define INCA_IP_Switch_PWR_EN ((volatile u32*)(INCA_IP_Switch+ 0x0488))
-#define INCA_IP_Switch_PWR_EN_PL (1 << 1)
-#define INCA_IP_Switch_PWR_EN_PP (1 << 0)
-
-/***MDIO Configuration Register***/
-#define INCA_IP_Switch_MDIO_CFG ((volatile u32*)(INCA_IP_Switch+ 0x048C))
-#define INCA_IP_Switch_MDIO_CFG_MDS (value) (((( 1 << 2) - 1) & (value)) << 14)
-#define INCA_IP_Switch_MDIO_CFG_PHY_LAN_ADDR (value) (((( 1 << 5) - 1) & (value)) << 9)
-#define INCA_IP_Switch_MDIO_CFG_PHY_PC_ADDR (value) (((( 1 << 5) - 1) & (value)) << 4)
-#define INCA_IP_Switch_MDIO_CFG_UEP (1 << 3)
-#define INCA_IP_Switch_MDIO_CFG_PS (1 << 2)
-#define INCA_IP_Switch_MDIO_CFG_PT (1 << 1)
-#define INCA_IP_Switch_MDIO_CFG_UMM (1 << 0)
-
-/***Clock Configuration Register***/
-#define INCA_IP_Switch_CLK_CFG ((volatile u32*)(INCA_IP_Switch+ 0x0500))
-#define INCA_IP_Switch_CLK_CFG_ARL_ID (1 << 9)
-#define INCA_IP_Switch_CLK_CFG_CPU_ID (1 << 8)
-#define INCA_IP_Switch_CLK_CFG_LAN_ID (1 << 7)
-#define INCA_IP_Switch_CLK_CFG_PC_ID (1 << 6)
-#define INCA_IP_Switch_CLK_CFG_SE_ID (1 << 5)
-
-/***********************************************************************/
-/* Module : SSC1 register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_SSC1 (0xB8000500)
-/***********************************************************************/
-
-
-/***Control Register (Programming Mode)***/
-#define INCA_IP_SSC1_SCC_CON_PRG ((volatile u32*)(INCA_IP_SSC1+ 0x0010))
-#define INCA_IP_SSC1_SCC_CON_PRG_EN (1 << 15)
-#define INCA_IP_SSC1_SCC_CON_PRG_MS (1 << 14)
-#define INCA_IP_SSC1_SCC_CON_PRG_AREN (1 << 12)
-#define INCA_IP_SSC1_SCC_CON_PRG_BEN (1 << 11)
-#define INCA_IP_SSC1_SCC_CON_PRG_PEN (1 << 10)
-#define INCA_IP_SSC1_SCC_CON_PRG_REN (1 << 9)
-#define INCA_IP_SSC1_SCC_CON_PRG_TEN (1 << 8)
-#define INCA_IP_SSC1_SCC_CON_PRG_LB (1 << 7)
-#define INCA_IP_SSC1_SCC_CON_PRG_PO (1 << 6)
-#define INCA_IP_SSC1_SCC_CON_PRG_PH (1 << 5)
-#define INCA_IP_SSC1_SCC_CON_PRG_HB (1 << 4)
-#define INCA_IP_SSC1_SCC_CON_PRG_BM (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***SCC Control Register (Operating Mode)***/
-#define INCA_IP_SSC1_SCC_CON_OPR ((volatile u32*)(INCA_IP_SSC1+ 0x0010))
-#define INCA_IP_SSC1_SCC_CON_OPR_EN (1 << 15)
-#define INCA_IP_SSC1_SCC_CON_OPR_MS (1 << 14)
-#define INCA_IP_SSC1_SCC_CON_OPR_BSY (1 << 12)
-#define INCA_IP_SSC1_SCC_CON_OPR_BE (1 << 11)
-#define INCA_IP_SSC1_SCC_CON_OPR_PE (1 << 10)
-#define INCA_IP_SSC1_SCC_CON_OPR_RE (1 << 9)
-#define INCA_IP_SSC1_SCC_CON_OPR_TE (1 << 8)
-#define INCA_IP_SSC1_SCC_CON_OPR_BC (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***SSC Write Hardware Modified Control Register***/
-#define INCA_IP_SSC1_SSC_WHBCON ((volatile u32*)(INCA_IP_SSC1+ 0x0040))
-#define INCA_IP_SSC1_SSC_WHBCON_SETBE (1 << 15)
-#define INCA_IP_SSC1_SSC_WHBCON_SETPE (1 << 14)
-#define INCA_IP_SSC1_SSC_WHBCON_SETRE (1 << 13)
-#define INCA_IP_SSC1_SSC_WHBCON_SETTE (1 << 12)
-#define INCA_IP_SSC1_SSC_WHBCON_CLRBE (1 << 11)
-#define INCA_IP_SSC1_SSC_WHBCON_CLRPE (1 << 10)
-#define INCA_IP_SSC1_SSC_WHBCON_CLRRE (1 << 9)
-#define INCA_IP_SSC1_SSC_WHBCON_CLRTE (1 << 8)
-
-/***SSC Baudrate Timer Reload Register***/
-#define INCA_IP_SSC1_SSC_BR ((volatile u32*)(INCA_IP_SSC1+ 0x0014))
-#define INCA_IP_SSC1_SSC_BR_BR_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***SSC Transmitter Buffer Register***/
-#define INCA_IP_SSC1_SSC_TB ((volatile u32*)(INCA_IP_SSC1+ 0x0020))
-#define INCA_IP_SSC1_SSC_TB_TB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***SSC Receiver Buffer Register***/
-#define INCA_IP_SSC1_SSC_RB ((volatile u32*)(INCA_IP_SSC1+ 0x0024))
-#define INCA_IP_SSC1_SSC_RB_RB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***SSC Receive FIFO Control Register***/
-#define INCA_IP_SSC1_SSC_RXFCON ((volatile u32*)(INCA_IP_SSC1+ 0x0030))
-#define INCA_IP_SSC1_SSC_RXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8)
-#define INCA_IP_SSC1_SSC_RXFCON_RXTMEN (1 << 2)
-#define INCA_IP_SSC1_SSC_RXFCON_RXFLU (1 << 1)
-#define INCA_IP_SSC1_SSC_RXFCON_RXFEN (1 << 0)
-
-/***SSC Transmit FIFO Control Register***/
-#define INCA_IP_SSC1_SSC_TXFCON ((volatile u32*)(INCA_IP_SSC1+ 0x0034))
-#define INCA_IP_SSC1_SSC_TXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8)
-#define INCA_IP_SSC1_SSC_TXFCON_TXTMEN (1 << 2)
-#define INCA_IP_SSC1_SSC_TXFCON_TXFLU (1 << 1)
-#define INCA_IP_SSC1_SSC_TXFCON_TXFEN (1 << 0)
-
-/***SSC FIFO Status Register***/
-#define INCA_IP_SSC1_SSC_FSTAT ((volatile u32*)(INCA_IP_SSC1+ 0x0038))
-#define INCA_IP_SSC1_SSC_FSTAT_TXFFL (value) (((( 1 << 6) - 1) & (value)) << 8)
-#define INCA_IP_SSC1_SSC_FSTAT_RXFFL (value) (((( 1 << 6) - 1) & (value)) << 0)
-
-/***SSC Clock Control Register***/
-#define INCA_IP_SSC1_SSC_CLC ((volatile u32*)(INCA_IP_SSC1+ 0x0000))
-#define INCA_IP_SSC1_SSC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_SSC1_SSC_CLC_DISS (1 << 1)
-#define INCA_IP_SSC1_SSC_CLC_DISR (1 << 0)
-
-/***********************************************************************/
-/* Module : SSC2 register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_SSC2 (0xB8000600)
-/***********************************************************************/
-
-
-/***Control Register (Programming Mode)***/
-#define INCA_IP_SSC2_SCC_CON_PRG ((volatile u32*)(INCA_IP_SSC2+ 0x0010))
-#define INCA_IP_SSC2_SCC_CON_PRG_EN (1 << 15)
-#define INCA_IP_SSC2_SCC_CON_PRG_MS (1 << 14)
-#define INCA_IP_SSC2_SCC_CON_PRG_AREN (1 << 12)
-#define INCA_IP_SSC2_SCC_CON_PRG_BEN (1 << 11)
-#define INCA_IP_SSC2_SCC_CON_PRG_PEN (1 << 10)
-#define INCA_IP_SSC2_SCC_CON_PRG_REN (1 << 9)
-#define INCA_IP_SSC2_SCC_CON_PRG_TEN (1 << 8)
-#define INCA_IP_SSC2_SCC_CON_PRG_LB (1 << 7)
-#define INCA_IP_SSC2_SCC_CON_PRG_PO (1 << 6)
-#define INCA_IP_SSC2_SCC_CON_PRG_PH (1 << 5)
-#define INCA_IP_SSC2_SCC_CON_PRG_HB (1 << 4)
-#define INCA_IP_SSC2_SCC_CON_PRG_BM (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***SCC Control Register (Operating Mode)***/
-#define INCA_IP_SSC2_SCC_CON_OPR ((volatile u32*)(INCA_IP_SSC2+ 0x0010))
-#define INCA_IP_SSC2_SCC_CON_OPR_EN (1 << 15)
-#define INCA_IP_SSC2_SCC_CON_OPR_MS (1 << 14)
-#define INCA_IP_SSC2_SCC_CON_OPR_BSY (1 << 12)
-#define INCA_IP_SSC2_SCC_CON_OPR_BE (1 << 11)
-#define INCA_IP_SSC2_SCC_CON_OPR_PE (1 << 10)
-#define INCA_IP_SSC2_SCC_CON_OPR_RE (1 << 9)
-#define INCA_IP_SSC2_SCC_CON_OPR_TE (1 << 8)
-#define INCA_IP_SSC2_SCC_CON_OPR_BC (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***SSC Write Hardware Modified Control Register***/
-#define INCA_IP_SSC2_SSC_WHBCON ((volatile u32*)(INCA_IP_SSC2+ 0x0040))
-#define INCA_IP_SSC2_SSC_WHBCON_SETBE (1 << 15)
-#define INCA_IP_SSC2_SSC_WHBCON_SETPE (1 << 14)
-#define INCA_IP_SSC2_SSC_WHBCON_SETRE (1 << 13)
-#define INCA_IP_SSC2_SSC_WHBCON_SETTE (1 << 12)
-#define INCA_IP_SSC2_SSC_WHBCON_CLRBE (1 << 11)
-#define INCA_IP_SSC2_SSC_WHBCON_CLRPE (1 << 10)
-#define INCA_IP_SSC2_SSC_WHBCON_CLRRE (1 << 9)
-#define INCA_IP_SSC2_SSC_WHBCON_CLRTE (1 << 8)
-
-/***SSC Baudrate Timer Reload Register***/
-#define INCA_IP_SSC2_SSC_BR ((volatile u32*)(INCA_IP_SSC2+ 0x0014))
-#define INCA_IP_SSC2_SSC_BR_BR_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***SSC Transmitter Buffer Register***/
-#define INCA_IP_SSC2_SSC_TB ((volatile u32*)(INCA_IP_SSC2+ 0x0020))
-#define INCA_IP_SSC2_SSC_TB_TB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***SSC Receiver Buffer Register***/
-#define INCA_IP_SSC2_SSC_RB ((volatile u32*)(INCA_IP_SSC2+ 0x0024))
-#define INCA_IP_SSC2_SSC_RB_RB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***SSC Receive FIFO Control Register***/
-#define INCA_IP_SSC2_SSC_RXFCON ((volatile u32*)(INCA_IP_SSC2+ 0x0030))
-#define INCA_IP_SSC2_SSC_RXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8)
-#define INCA_IP_SSC2_SSC_RXFCON_RXTMEN (1 << 2)
-#define INCA_IP_SSC2_SSC_RXFCON_RXFLU (1 << 1)
-#define INCA_IP_SSC2_SSC_RXFCON_RXFEN (1 << 0)
-
-/***SSC Transmit FIFO Control Register***/
-#define INCA_IP_SSC2_SSC_TXFCON ((volatile u32*)(INCA_IP_SSC2+ 0x0034))
-#define INCA_IP_SSC2_SSC_TXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8)
-#define INCA_IP_SSC2_SSC_TXFCON_TXTMEN (1 << 2)
-#define INCA_IP_SSC2_SSC_TXFCON_TXFLU (1 << 1)
-#define INCA_IP_SSC2_SSC_TXFCON_TXFEN (1 << 0)
-
-/***SSC FIFO Status Register***/
-#define INCA_IP_SSC2_SSC_FSTAT ((volatile u32*)(INCA_IP_SSC2+ 0x0038))
-#define INCA_IP_SSC2_SSC_FSTAT_TXFFL (value) (((( 1 << 6) - 1) & (value)) << 8)
-#define INCA_IP_SSC2_SSC_FSTAT_RXFFL (value) (((( 1 << 6) - 1) & (value)) << 0)
-
-/***SSC Clock Control Register***/
-#define INCA_IP_SSC2_SSC_CLC ((volatile u32*)(INCA_IP_SSC2+ 0x0000))
-#define INCA_IP_SSC2_SSC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_SSC2_SSC_CLC_DISS (1 << 1)
-#define INCA_IP_SSC2_SSC_CLC_DISR (1 << 0)
-
-/***********************************************************************/
-/* Module : EBU register address and bits */
-/***********************************************************************/
-
-#if defined(CONFIG_INCA_IP)
-#define INCA_IP_EBU (0xB8000200)
-#elif defined(CONFIG_PURPLE)
-#define INCA_IP_EBU (0xB800D800)
-#endif
-
-/***********************************************************************/
-
-
-/***EBU Clock Control Register***/
-#define INCA_IP_EBU_EBU_CLC ((volatile u32*)(INCA_IP_EBU+ 0x0000))
-#define INCA_IP_EBU_EBU_CLC_DISS (1 << 1)
-#define INCA_IP_EBU_EBU_CLC_DISR (1 << 0)
-
-/***EBU Global Control Register***/
-#define INCA_IP_EBU_EBU_CON ((volatile u32*)(INCA_IP_EBU+ 0x0010))
-#define INCA_IP_EBU_EBU_CON_DTACS (value) (((( 1 << 3) - 1) & (value)) << 20)
-#define INCA_IP_EBU_EBU_CON_DTARW (value) (((( 1 << 3) - 1) & (value)) << 16)
-#define INCA_IP_EBU_EBU_CON_TOUTC (value) (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_EBU_EBU_CON_ARBMODE (value) (((( 1 << 2) - 1) & (value)) << 6)
-#define INCA_IP_EBU_EBU_CON_ARBSYNC (1 << 5)
-#define INCA_IP_EBU_EBU_CON_1 (1 << 3)
-
-/***EBU Address Select Register 0***/
-#define INCA_IP_EBU_EBU_ADDSEL0 ((volatile u32*)(INCA_IP_EBU+ 0x0020))
-#define INCA_IP_EBU_EBU_ADDSEL0_BASE (value) (((( 1 << 20) - 1) & (value)) << 12)
-#define INCA_IP_EBU_EBU_ADDSEL0_MASK (value) (((( 1 << 4) - 1) & (value)) << 4)
-#define INCA_IP_EBU_EBU_ADDSEL0_MIRRORE (1 << 1)
-#define INCA_IP_EBU_EBU_ADDSEL0_REGEN (1 << 0)
-
-/***EBU Address Select Register 1***/
-#define INCA_IP_EBU_EBU_ADDSEL1 ((volatile u32*)(INCA_IP_EBU+ 0x0024))
-#define INCA_IP_EBU_EBU_ADDSEL1_BASE (value) (((( 1 << 20) - 1) & (value)) << 12)
-#define INCA_IP_EBU_EBU_ADDSEL1_MASK (value) (((( 1 << 4) - 1) & (value)) << 4)
-#define INCA_IP_EBU_EBU_ADDSEL1_MIRRORE (1 << 1)
-#define INCA_IP_EBU_EBU_ADDSEL1_REGEN (1 << 0)
-
-/***EBU Address Select Register 2***/
-#define INCA_IP_EBU_EBU_ADDSEL2 ((volatile u32*)(INCA_IP_EBU+ 0x0028))
-#define INCA_IP_EBU_EBU_ADDSEL2_BASE (value) (((( 1 << 20) - 1) & (value)) << 12)
-#define INCA_IP_EBU_EBU_ADDSEL2_MASK (value) (((( 1 << 4) - 1) & (value)) << 4)
-#define INCA_IP_EBU_EBU_ADDSEL2_MIRRORE (1 << 1)
-#define INCA_IP_EBU_EBU_ADDSEL2_REGEN (1 << 0)
-
-/***EBU Bus Configuration Register 0***/
-#define INCA_IP_EBU_EBU_BUSCON0 ((volatile u32*)(INCA_IP_EBU+ 0x0060))
-#define INCA_IP_EBU_EBU_BUSCON0_WRDIS (1 << 31)
-#define INCA_IP_EBU_EBU_BUSCON0_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29)
-#define INCA_IP_EBU_EBU_BUSCON0_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27)
-#define INCA_IP_EBU_EBU_BUSCON0_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24)
-#define INCA_IP_EBU_EBU_BUSCON0_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22)
-#define INCA_IP_EBU_EBU_BUSCON0_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20)
-#define INCA_IP_EBU_EBU_BUSCON0_WAITINV (1 << 19)
-#define INCA_IP_EBU_EBU_BUSCON0_SETUP (1 << 18)
-#define INCA_IP_EBU_EBU_BUSCON0_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16)
-#define INCA_IP_EBU_EBU_BUSCON0_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9)
-#define INCA_IP_EBU_EBU_BUSCON0_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6)
-#define INCA_IP_EBU_EBU_BUSCON0_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4)
-#define INCA_IP_EBU_EBU_BUSCON0_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2)
-#define INCA_IP_EBU_EBU_BUSCON0_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0)
-
-/***EBU Bus Configuration Register 1***/
-#define INCA_IP_EBU_EBU_BUSCON1 ((volatile u32*)(INCA_IP_EBU+ 0x0064))
-#define INCA_IP_EBU_EBU_BUSCON1_WRDIS (1 << 31)
-#define INCA_IP_EBU_EBU_BUSCON1_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29)
-#define INCA_IP_EBU_EBU_BUSCON1_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27)
-#define INCA_IP_EBU_EBU_BUSCON1_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24)
-#define INCA_IP_EBU_EBU_BUSCON1_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22)
-#define INCA_IP_EBU_EBU_BUSCON1_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20)
-#define INCA_IP_EBU_EBU_BUSCON1_WAITINV (1 << 19)
-#define INCA_IP_EBU_EBU_BUSCON1_SETUP (1 << 18)
-#define INCA_IP_EBU_EBU_BUSCON1_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16)
-#define INCA_IP_EBU_EBU_BUSCON1_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9)
-#define INCA_IP_EBU_EBU_BUSCON1_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6)
-#define INCA_IP_EBU_EBU_BUSCON1_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4)
-#define INCA_IP_EBU_EBU_BUSCON1_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2)
-#define INCA_IP_EBU_EBU_BUSCON1_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0)
-
-/***EBU Bus Configuration Register 2***/
-#define INCA_IP_EBU_EBU_BUSCON2 ((volatile u32*)(INCA_IP_EBU+ 0x0068))
-#define INCA_IP_EBU_EBU_BUSCON2_WRDIS (1 << 31)
-#define INCA_IP_EBU_EBU_BUSCON2_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29)
-#define INCA_IP_EBU_EBU_BUSCON2_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27)
-#define INCA_IP_EBU_EBU_BUSCON2_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24)
-#define INCA_IP_EBU_EBU_BUSCON2_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22)
-#define INCA_IP_EBU_EBU_BUSCON2_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20)
-#define INCA_IP_EBU_EBU_BUSCON2_WAITINV (1 << 19)
-#define INCA_IP_EBU_EBU_BUSCON2_SETUP (1 << 18)
-#define INCA_IP_EBU_EBU_BUSCON2_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16)
-#define INCA_IP_EBU_EBU_BUSCON2_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9)
-#define INCA_IP_EBU_EBU_BUSCON2_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6)
-#define INCA_IP_EBU_EBU_BUSCON2_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4)
-#define INCA_IP_EBU_EBU_BUSCON2_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2)
-#define INCA_IP_EBU_EBU_BUSCON2_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0)
-
-/***********************************************************************/
-/* Module : SDRAM register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_SDRAM (0xBF800000)
-/***********************************************************************/
-
-
-/***MC Access Error Cause Register***/
-#define INCA_IP_SDRAM_MC_ERRCAUSE ((volatile u32*)(INCA_IP_SDRAM+ 0x0100))
-#define INCA_IP_SDRAM_MC_ERRCAUSE_ERR (1 << 31)
-#define INCA_IP_SDRAM_MC_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16)
-#define INCA_IP_SDRAM_MC_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0)
-#define INCA_IP_SDRAM_MC_ERRCAUSE_Res (value) (((( 1 << NaN) - 1) & (value)) << NaN)
-
-/***MC Access Error Address Register***/
-#define INCA_IP_SDRAM_MC_ERRADDR ((volatile u32*)(INCA_IP_SDRAM+ 0x0108))
-#define INCA_IP_SDRAM_MC_ERRADDR_ADDR
-
-/***MC I/O General Purpose Register***/
-#define INCA_IP_SDRAM_MC_IOGP ((volatile u32*)(INCA_IP_SDRAM+ 0x0800))
-#define INCA_IP_SDRAM_MC_IOGP_GPR6 (value) (((( 1 << 4) - 1) & (value)) << 28)
-#define INCA_IP_SDRAM_MC_IOGP_GPR5 (value) (((( 1 << 4) - 1) & (value)) << 24)
-#define INCA_IP_SDRAM_MC_IOGP_GPR4 (value) (((( 1 << 4) - 1) & (value)) << 20)
-#define INCA_IP_SDRAM_MC_IOGP_GPR3 (value) (((( 1 << 4) - 1) & (value)) << 16)
-#define INCA_IP_SDRAM_MC_IOGP_GPR2 (value) (((( 1 << 4) - 1) & (value)) << 12)
-#define INCA_IP_SDRAM_MC_IOGP_CPS (1 << 11)
-#define INCA_IP_SDRAM_MC_IOGP_CLKDELAY (value) (((( 1 << 3) - 1) & (value)) << 8)
-#define INCA_IP_SDRAM_MC_IOGP_CLKRAT (value) (((( 1 << 4) - 1) & (value)) << 4)
-#define INCA_IP_SDRAM_MC_IOGP_RDDEL (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***MC Self Refresh Register***/
-#define INCA_IP_SDRAM_MC_SELFRFSH ((volatile u32*)(INCA_IP_SDRAM+ 0x0A00))
-#define INCA_IP_SDRAM_MC_SELFRFSH_PWDS (1 << 1)
-#define INCA_IP_SDRAM_MC_SELFRFSH_PWD (1 << 0)
-#define INCA_IP_SDRAM_MC_SELFRFSH_Res (value) (((( 1 << 30) - 1) & (value)) << 2)
-
-/***MC Enable Register***/
-#define INCA_IP_SDRAM_MC_CTRLENA ((volatile u32*)(INCA_IP_SDRAM+ 0x1000))
-#define INCA_IP_SDRAM_MC_CTRLENA_ENA (1 << 0)
-#define INCA_IP_SDRAM_MC_CTRLENA_Res (value) (((( 1 << 31) - 1) & (value)) << 1)
-
-/***MC Mode Register Setup Code***/
-#define INCA_IP_SDRAM_MC_MRSCODE ((volatile u32*)(INCA_IP_SDRAM+ 0x1008))
-#define INCA_IP_SDRAM_MC_MRSCODE_UMC (value) (((( 1 << 5) - 1) & (value)) << 7)
-#define INCA_IP_SDRAM_MC_MRSCODE_CL (value) (((( 1 << 3) - 1) & (value)) << 4)
-#define INCA_IP_SDRAM_MC_MRSCODE_WT (1 << 3)
-#define INCA_IP_SDRAM_MC_MRSCODE_BL (value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***MC Configuration Data-word Width Register***/
-#define INCA_IP_SDRAM_MC_CFGDW ((volatile u32*)(INCA_IP_SDRAM+ 0x1010))
-#define INCA_IP_SDRAM_MC_CFGDW_DW (value) (((( 1 << 4) - 1) & (value)) << 0)
-#define INCA_IP_SDRAM_MC_CFGDW_Res (value) (((( 1 << 28) - 1) & (value)) << 4)
-
-/***MC Configuration Physical Bank 0 Register***/
-#define INCA_IP_SDRAM_MC_CFGPB0 ((volatile u32*)(INCA_IP_SDRAM+ 0x1018))
-#define INCA_IP_SDRAM_MC_CFGPB0_MCSEN0 (value) (((( 1 << 4) - 1) & (value)) << 12)
-#define INCA_IP_SDRAM_MC_CFGPB0_BANKN0 (value) (((( 1 << 4) - 1) & (value)) << 8)
-#define INCA_IP_SDRAM_MC_CFGPB0_ROWW0 (value) (((( 1 << 4) - 1) & (value)) << 4)
-#define INCA_IP_SDRAM_MC_CFGPB0_COLW0 (value) (((( 1 << 4) - 1) & (value)) << 0)
-#define INCA_IP_SDRAM_MC_CFGPB0_Res (value) (((( 1 << 16) - 1) & (value)) << 16)
-
-/***MC Latency Register***/
-#define INCA_IP_SDRAM_MC_LATENCY ((volatile u32*)(INCA_IP_SDRAM+ 0x1038))
-#define INCA_IP_SDRAM_MC_LATENCY_TRP (value) (((( 1 << 4) - 1) & (value)) << 16)
-#define INCA_IP_SDRAM_MC_LATENCY_TRAS (value) (((( 1 << 4) - 1) & (value)) << 12)
-#define INCA_IP_SDRAM_MC_LATENCY_TRCD (value) (((( 1 << 4) - 1) & (value)) << 8)
-#define INCA_IP_SDRAM_MC_LATENCY_TDPL (value) (((( 1 << 4) - 1) & (value)) << 4)
-#define INCA_IP_SDRAM_MC_LATENCY_TDAL (value) (((( 1 << 4) - 1) & (value)) << 0)
-#define INCA_IP_SDRAM_MC_LATENCY_Res (value) (((( 1 << 12) - 1) & (value)) << 20)
-
-/***MC Refresh Cycle Time Register***/
-#define INCA_IP_SDRAM_MC_TREFRESH ((volatile u32*)(INCA_IP_SDRAM+ 0x1040))
-#define INCA_IP_SDRAM_MC_TREFRESH_TREF (value) (((( 1 << 13) - 1) & (value)) << 0)
-#define INCA_IP_SDRAM_MC_TREFRESH_Res (value) (((( 1 << 19) - 1) & (value)) << 13)
-
-/***********************************************************************/
-/* Module : GPTU register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_GPTU (0xB8000300)
-/***********************************************************************/
-
-
-/***GPT Clock Control Register***/
-#define INCA_IP_GPTU_GPT_CLC ((volatile u32*)(INCA_IP_GPTU+ 0x0000))
-#define INCA_IP_GPTU_GPT_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_GPTU_GPT_CLC_DISS (1 << 1)
-#define INCA_IP_GPTU_GPT_CLC_DISR (1 << 0)
-
-/***GPT Timer 3 Control Register***/
-#define INCA_IP_GPTU_GPT_T3CON ((volatile u32*)(INCA_IP_GPTU+ 0x0014))
-#define INCA_IP_GPTU_GPT_T3CON_T3RDIR (1 << 15)
-#define INCA_IP_GPTU_GPT_T3CON_T3CHDIR (1 << 14)
-#define INCA_IP_GPTU_GPT_T3CON_T3EDGE (1 << 13)
-#define INCA_IP_GPTU_GPT_T3CON_BPS1 (value) (((( 1 << 2) - 1) & (value)) << 11)
-#define INCA_IP_GPTU_GPT_T3CON_T3OTL (1 << 10)
-#define INCA_IP_GPTU_GPT_T3CON_T3UD (1 << 7)
-#define INCA_IP_GPTU_GPT_T3CON_T3R (1 << 6)
-#define INCA_IP_GPTU_GPT_T3CON_T3M (value) (((( 1 << 3) - 1) & (value)) << 3)
-#define INCA_IP_GPTU_GPT_T3CON_T3I (value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***GPT Write Hardware Modified Timer 3 Control Register
-If set and clear bit are written concurrently with 1, the associated bit is not changed.***/
-#define INCA_IP_GPTU_GPT_WHBT3CON ((volatile u32*)(INCA_IP_GPTU+ 0x004C))
-#define INCA_IP_GPTU_GPT_WHBT3CON_SETT3CHDIR (1 << 15)
-#define INCA_IP_GPTU_GPT_WHBT3CON_CLRT3CHDIR (1 << 14)
-#define INCA_IP_GPTU_GPT_WHBT3CON_SETT3EDGE (1 << 13)
-#define INCA_IP_GPTU_GPT_WHBT3CON_CLRT3EDGE (1 << 12)
-#define INCA_IP_GPTU_GPT_WHBT3CON_SETT3OTL (1 << 11)
-#define INCA_IP_GPTU_GPT_WHBT3CON_CLRT3OTL (1 << 10)
-
-/***GPT Timer 2 Control Register***/
-#define INCA_IP_GPTU_GPT_T2CON ((volatile u32*)(INCA_IP_GPTU+ 0x0010))
-#define INCA_IP_GPTU_GPT_T2CON_TxRDIR (1 << 15)
-#define INCA_IP_GPTU_GPT_T2CON_TxCHDIR (1 << 14)
-#define INCA_IP_GPTU_GPT_T2CON_TxEDGE (1 << 13)
-#define INCA_IP_GPTU_GPT_T2CON_TxIRDIS (1 << 12)
-#define INCA_IP_GPTU_GPT_T2CON_TxRC (1 << 9)
-#define INCA_IP_GPTU_GPT_T2CON_TxUD (1 << 7)
-#define INCA_IP_GPTU_GPT_T2CON_TxR (1 << 6)
-#define INCA_IP_GPTU_GPT_T2CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3)
-#define INCA_IP_GPTU_GPT_T2CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***GPT Timer 4 Control Register***/
-#define INCA_IP_GPTU_GPT_T4CON ((volatile u32*)(INCA_IP_GPTU+ 0x0018))
-#define INCA_IP_GPTU_GPT_T4CON_TxRDIR (1 << 15)
-#define INCA_IP_GPTU_GPT_T4CON_TxCHDIR (1 << 14)
-#define INCA_IP_GPTU_GPT_T4CON_TxEDGE (1 << 13)
-#define INCA_IP_GPTU_GPT_T4CON_TxIRDIS (1 << 12)
-#define INCA_IP_GPTU_GPT_T4CON_TxRC (1 << 9)
-#define INCA_IP_GPTU_GPT_T4CON_TxUD (1 << 7)
-#define INCA_IP_GPTU_GPT_T4CON_TxR (1 << 6)
-#define INCA_IP_GPTU_GPT_T4CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3)
-#define INCA_IP_GPTU_GPT_T4CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***GPT Write HW Modified Timer 2 Control Register If set
- and clear bit are written concurrently with 1, the associated bit is not changed.***/
-#define INCA_IP_GPTU_GPT_WHBT2CON ((volatile u32*)(INCA_IP_GPTU+ 0x0048))
-#define INCA_IP_GPTU_GPT_WHBT2CON_SETTxCHDIR (1 << 15)
-#define INCA_IP_GPTU_GPT_WHBT2CON_CLRTxCHDIR (1 << 14)
-#define INCA_IP_GPTU_GPT_WHBT2CON_SETTxEDGE (1 << 13)
-#define INCA_IP_GPTU_GPT_WHBT2CON_CLRTxEDGE (1 << 12)
-
-/***GPT Write HW Modified Timer 4 Control Register If set
- and clear bit are written concurrently with 1, the associated bit is not changed.***/
-#define INCA_IP_GPTU_GPT_WHBT4CON ((volatile u32*)(INCA_IP_GPTU+ 0x0050))
-#define INCA_IP_GPTU_GPT_WHBT4CON_SETTxCHDIR (1 << 15)
-#define INCA_IP_GPTU_GPT_WHBT4CON_CLRTxCHDIR (1 << 14)
-#define INCA_IP_GPTU_GPT_WHBT4CON_SETTxEDGE (1 << 13)
-#define INCA_IP_GPTU_GPT_WHBT4CON_CLRTxEDGE (1 << 12)
-
-/***GPT Capture Reload Register***/
-#define INCA_IP_GPTU_GPT_CAPREL ((volatile u32*)(INCA_IP_GPTU+ 0x0030))
-#define INCA_IP_GPTU_GPT_CAPREL_CAPREL (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***GPT Timer 2 Register***/
-#define INCA_IP_GPTU_GPT_T2 ((volatile u32*)(INCA_IP_GPTU+ 0x0034))
-#define INCA_IP_GPTU_GPT_T2_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***GPT Timer 3 Register***/
-#define INCA_IP_GPTU_GPT_T3 ((volatile u32*)(INCA_IP_GPTU+ 0x0038))
-#define INCA_IP_GPTU_GPT_T3_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***GPT Timer 4 Register***/
-#define INCA_IP_GPTU_GPT_T4 ((volatile u32*)(INCA_IP_GPTU+ 0x003C))
-#define INCA_IP_GPTU_GPT_T4_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***GPT Timer 5 Register***/
-#define INCA_IP_GPTU_GPT_T5 ((volatile u32*)(INCA_IP_GPTU+ 0x0040))
-#define INCA_IP_GPTU_GPT_T5_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***GPT Timer 6 Register***/
-#define INCA_IP_GPTU_GPT_T6 ((volatile u32*)(INCA_IP_GPTU+ 0x0044))
-#define INCA_IP_GPTU_GPT_T6_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***GPT Timer 6 Control Register***/
-#define INCA_IP_GPTU_GPT_T6CON ((volatile u32*)(INCA_IP_GPTU+ 0x0020))
-#define INCA_IP_GPTU_GPT_T6CON_T6SR (1 << 15)
-#define INCA_IP_GPTU_GPT_T6CON_T6CLR (1 << 14)
-#define INCA_IP_GPTU_GPT_T6CON_BPS2 (value) (((( 1 << 2) - 1) & (value)) << 11)
-#define INCA_IP_GPTU_GPT_T6CON_T6OTL (1 << 10)
-#define INCA_IP_GPTU_GPT_T6CON_T6UD (1 << 7)
-#define INCA_IP_GPTU_GPT_T6CON_T6R (1 << 6)
-#define INCA_IP_GPTU_GPT_T6CON_T6M (value) (((( 1 << 3) - 1) & (value)) << 3)
-#define INCA_IP_GPTU_GPT_T6CON_T6I (value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***GPT Write HW Modified Timer 6 Control Register If set
- and clear bit are written concurrently with 1, the associated bit is not changed.***/
-#define INCA_IP_GPTU_GPT_WHBT6CON ((volatile u32*)(INCA_IP_GPTU+ 0x0054))
-#define INCA_IP_GPTU_GPT_WHBT6CON_SETT6OTL (1 << 11)
-#define INCA_IP_GPTU_GPT_WHBT6CON_CLRT6OTL (1 << 10)
-
-/***GPT Timer 5 Control Register***/
-#define INCA_IP_GPTU_GPT_T5CON ((volatile u32*)(INCA_IP_GPTU+ 0x001C))
-#define INCA_IP_GPTU_GPT_T5CON_T5SC (1 << 15)
-#define INCA_IP_GPTU_GPT_T5CON_T5CLR (1 << 14)
-#define INCA_IP_GPTU_GPT_T5CON_CI (value) (((( 1 << 2) - 1) & (value)) << 12)
-#define INCA_IP_GPTU_GPT_T5CON_T5CC (1 << 11)
-#define INCA_IP_GPTU_GPT_T5CON_CT3 (1 << 10)
-#define INCA_IP_GPTU_GPT_T5CON_T5RC (1 << 9)
-#define INCA_IP_GPTU_GPT_T5CON_T5UDE (1 << 8)
-#define INCA_IP_GPTU_GPT_T5CON_T5UD (1 << 7)
-#define INCA_IP_GPTU_GPT_T5CON_T5R (1 << 6)
-#define INCA_IP_GPTU_GPT_T5CON_T5M (value) (((( 1 << 3) - 1) & (value)) << 3)
-#define INCA_IP_GPTU_GPT_T5CON_T5I (value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***********************************************************************/
-/* Module : IOM register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_IOM (0xBF105000)
-/***********************************************************************/
-
-
-/***Receive FIFO***/
-#define INCA_IP_IOM_RFIFO ((volatile u32*)(INCA_IP_IOM+ 0x0000))
-#define INCA_IP_IOM_RFIFO_RXD (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***Transmit FIFO***/
-#define INCA_IP_IOM_XFIFO ((volatile u32*)(INCA_IP_IOM+ 0x0000))
-#define INCA_IP_IOM_XFIFO_TXD (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***Interrupt Status Register HDLC***/
-#define INCA_IP_IOM_ISTAH ((volatile u32*)(INCA_IP_IOM+ 0x0080))
-#define INCA_IP_IOM_ISTAH_RME (1 << 7)
-#define INCA_IP_IOM_ISTAH_RPF (1 << 6)
-#define INCA_IP_IOM_ISTAH_RFO (1 << 5)
-#define INCA_IP_IOM_ISTAH_XPR (1 << 4)
-#define INCA_IP_IOM_ISTAH_XMR (1 << 3)
-#define INCA_IP_IOM_ISTAH_XDU (1 << 2)
-
-/***Interrupt Mask Register HDLC***/
-#define INCA_IP_IOM_MASKH ((volatile u32*)(INCA_IP_IOM+ 0x0080))
-#define INCA_IP_IOM_MASKH_RME (1 << 7)
-#define INCA_IP_IOM_MASKH_RPF (1 << 6)
-#define INCA_IP_IOM_MASKH_RFO (1 << 5)
-#define INCA_IP_IOM_MASKH_XPR (1 << 4)
-#define INCA_IP_IOM_MASKH_XMR (1 << 3)
-#define INCA_IP_IOM_MASKH_XDU (1 << 2)
-
-/***Status Register***/
-#define INCA_IP_IOM_STAR ((volatile u32*)(INCA_IP_IOM+ 0x0084))
-#define INCA_IP_IOM_STAR_XDOV (1 << 7)
-#define INCA_IP_IOM_STAR_XFW (1 << 6)
-#define INCA_IP_IOM_STAR_RACI (1 << 3)
-#define INCA_IP_IOM_STAR_XACI (1 << 1)
-
-/***Command Register***/
-#define INCA_IP_IOM_CMDR ((volatile u32*)(INCA_IP_IOM+ 0x0084))
-#define INCA_IP_IOM_CMDR_RMC (1 << 7)
-#define INCA_IP_IOM_CMDR_RRES (1 << 6)
-#define INCA_IP_IOM_CMDR_XTF (1 << 3)
-#define INCA_IP_IOM_CMDR_XME (1 << 1)
-#define INCA_IP_IOM_CMDR_XRES (1 << 0)
-
-/***Mode Register***/
-#define INCA_IP_IOM_MODEH ((volatile u32*)(INCA_IP_IOM+ 0x0088))
-#define INCA_IP_IOM_MODEH_MDS2 (1 << 7)
-#define INCA_IP_IOM_MODEH_MDS1 (1 << 6)
-#define INCA_IP_IOM_MODEH_MDS0 (1 << 5)
-#define INCA_IP_IOM_MODEH_RAC (1 << 3)
-#define INCA_IP_IOM_MODEH_DIM2 (1 << 2)
-#define INCA_IP_IOM_MODEH_DIM1 (1 << 1)
-#define INCA_IP_IOM_MODEH_DIM0 (1 << 0)
-
-/***Extended Mode Register***/
-#define INCA_IP_IOM_EXMR ((volatile u32*)(INCA_IP_IOM+ 0x008C))
-#define INCA_IP_IOM_EXMR_XFBS (1 << 7)
-#define INCA_IP_IOM_EXMR_RFBS (value) (((( 1 << 2) - 1) & (value)) << 5)
-#define INCA_IP_IOM_EXMR_SRA (1 << 4)
-#define INCA_IP_IOM_EXMR_XCRC (1 << 3)
-#define INCA_IP_IOM_EXMR_RCRC (1 << 2)
-#define INCA_IP_IOM_EXMR_ITF (1 << 0)
-
-/***SAPI1 Register***/
-#define INCA_IP_IOM_SAP1 ((volatile u32*)(INCA_IP_IOM+ 0x0094))
-#define INCA_IP_IOM_SAP1_SAPI1 (value) (((( 1 << 6) - 1) & (value)) << 2)
-#define INCA_IP_IOM_SAP1_MHA (1 << 0)
-
-/***Receive Frame Byte Count Low***/
-#define INCA_IP_IOM_RBCL ((volatile u32*)(INCA_IP_IOM+ 0x0098))
-#define INCA_IP_IOM_RBCL_RBC(value) (1 << value)
-
-
-/***SAPI2 Register***/
-#define INCA_IP_IOM_SAP2 ((volatile u32*)(INCA_IP_IOM+ 0x0098))
-#define INCA_IP_IOM_SAP2_SAPI2 (value) (((( 1 << 6) - 1) & (value)) << 2)
-#define INCA_IP_IOM_SAP2_MLA (1 << 0)
-
-/***Receive Frame Byte Count High***/
-#define INCA_IP_IOM_RBCH ((volatile u32*)(INCA_IP_IOM+ 0x009C))
-#define INCA_IP_IOM_RBCH_OV (1 << 4)
-#define INCA_IP_IOM_RBCH_RBC11 (1 << 3)
-#define INCA_IP_IOM_RBCH_RBC10 (1 << 2)
-#define INCA_IP_IOM_RBCH_RBC9 (1 << 1)
-#define INCA_IP_IOM_RBCH_RBC8 (1 << 0)
-
-/***TEI1 Register 1***/
-#define INCA_IP_IOM_TEI1 ((volatile u32*)(INCA_IP_IOM+ 0x009C))
-#define INCA_IP_IOM_TEI1_TEI1 (value) (((( 1 << 7) - 1) & (value)) << 1)
-#define INCA_IP_IOM_TEI1_EA (1 << 0)
-
-/***Receive Status Register***/
-#define INCA_IP_IOM_RSTA ((volatile u32*)(INCA_IP_IOM+ 0x00A0))
-#define INCA_IP_IOM_RSTA_VFR (1 << 7)
-#define INCA_IP_IOM_RSTA_RDO (1 << 6)
-#define INCA_IP_IOM_RSTA_CRC (1 << 5)
-#define INCA_IP_IOM_RSTA_RAB (1 << 4)
-#define INCA_IP_IOM_RSTA_SA1 (1 << 3)
-#define INCA_IP_IOM_RSTA_SA0 (1 << 2)
-#define INCA_IP_IOM_RSTA_TA (1 << 0)
-#define INCA_IP_IOM_RSTA_CR (1 << 1)
-
-/***TEI2 Register***/
-#define INCA_IP_IOM_TEI2 ((volatile u32*)(INCA_IP_IOM+ 0x00A0))
-#define INCA_IP_IOM_TEI2_TEI2 (value) (((( 1 << 7) - 1) & (value)) << 1)
-#define INCA_IP_IOM_TEI2_EA (1 << 0)
-
-/***Test Mode Register HDLC***/
-#define INCA_IP_IOM_TMH ((volatile u32*)(INCA_IP_IOM+ 0x00A4))
-#define INCA_IP_IOM_TMH_TLP (1 << 0)
-
-/***Command/Indication Receive 0***/
-#define INCA_IP_IOM_CIR0 ((volatile u32*)(INCA_IP_IOM+ 0x00B8))
-#define INCA_IP_IOM_CIR0_CODR0 (value) (((( 1 << 4) - 1) & (value)) << 4)
-#define INCA_IP_IOM_CIR0_CIC0 (1 << 3)
-#define INCA_IP_IOM_CIR0_CIC1 (1 << 2)
-#define INCA_IP_IOM_CIR0_SG (1 << 1)
-#define INCA_IP_IOM_CIR0_BAS (1 << 0)
-
-/***Command/Indication Transmit 0***/
-#define INCA_IP_IOM_CIX0 ((volatile u32*)(INCA_IP_IOM+ 0x00B8))
-#define INCA_IP_IOM_CIX0_CODX0 (value) (((( 1 << 4) - 1) & (value)) << 4)
-#define INCA_IP_IOM_CIX0_TBA2 (1 << 3)
-#define INCA_IP_IOM_CIX0_TBA1 (1 << 2)
-#define INCA_IP_IOM_CIX0_TBA0 (1 << 1)
-#define INCA_IP_IOM_CIX0_BAC (1 << 0)
-
-/***Command/Indication Receive 1***/
-#define INCA_IP_IOM_CIR1 ((volatile u32*)(INCA_IP_IOM+ 0x00BC))
-#define INCA_IP_IOM_CIR1_CODR1 (value) (((( 1 << 6) - 1) & (value)) << 2)
-
-/***Command/Indication Transmit 1***/
-#define INCA_IP_IOM_CIX1 ((volatile u32*)(INCA_IP_IOM+ 0x00BC))
-#define INCA_IP_IOM_CIX1_CODX1 (value) (((( 1 << 6) - 1) & (value)) << 2)
-#define INCA_IP_IOM_CIX1_CICW (1 << 1)
-#define INCA_IP_IOM_CIX1_CI1E (1 << 0)
-
-/***Controller Data Access Reg. (CH10)***/
-#define INCA_IP_IOM_CDA10 ((volatile u32*)(INCA_IP_IOM+ 0x0100))
-#define INCA_IP_IOM_CDA10_CDA (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***Controller Data Access Reg. (CH11)***/
-#define INCA_IP_IOM_CDA11 ((volatile u32*)(INCA_IP_IOM+ 0x0104))
-#define INCA_IP_IOM_CDA11_CDA (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***Controller Data Access Reg. (CH20)***/
-#define INCA_IP_IOM_CDA20 ((volatile u32*)(INCA_IP_IOM+ 0x0108))
-#define INCA_IP_IOM_CDA20_CDA (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***Controller Data Access Reg. (CH21)***/
-#define INCA_IP_IOM_CDA21 ((volatile u32*)(INCA_IP_IOM+ 0x010C))
-#define INCA_IP_IOM_CDA21_CDA (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***Time Slot and Data Port Sel. (CH10)***/
-#define INCA_IP_IOM_CDA_TSDP10 ((volatile u32*)(INCA_IP_IOM+ 0x0110))
-#define INCA_IP_IOM_CDA_TSDP10_DPS (1 << 7)
-#define INCA_IP_IOM_CDA_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Time Slot and Data Port Sel. (CH11)***/
-#define INCA_IP_IOM_CDA_TSDP11 ((volatile u32*)(INCA_IP_IOM+ 0x0114))
-#define INCA_IP_IOM_CDA_TSDP11_DPS (1 << 7)
-#define INCA_IP_IOM_CDA_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Time Slot and Data Port Sel. (CH20)***/
-#define INCA_IP_IOM_CDA_TSDP20 ((volatile u32*)(INCA_IP_IOM+ 0x0118))
-#define INCA_IP_IOM_CDA_TSDP20_DPS (1 << 7)
-#define INCA_IP_IOM_CDA_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Time Slot and Data Port Sel. (CH21)***/
-#define INCA_IP_IOM_CDA_TSDP21 ((volatile u32*)(INCA_IP_IOM+ 0x011C))
-#define INCA_IP_IOM_CDA_TSDP21_DPS (1 << 7)
-#define INCA_IP_IOM_CDA_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Time Slot and Data Port Sel. (CH10)***/
-#define INCA_IP_IOM_CO_TSDP10 ((volatile u32*)(INCA_IP_IOM+ 0x0120))
-#define INCA_IP_IOM_CO_TSDP10_DPS (1 << 7)
-#define INCA_IP_IOM_CO_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Time Slot and Data Port Sel. (CH11)***/
-#define INCA_IP_IOM_CO_TSDP11 ((volatile u32*)(INCA_IP_IOM+ 0x0124))
-#define INCA_IP_IOM_CO_TSDP11_DPS (1 << 7)
-#define INCA_IP_IOM_CO_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Time Slot and Data Port Sel. (CH20)***/
-#define INCA_IP_IOM_CO_TSDP20 ((volatile u32*)(INCA_IP_IOM+ 0x0128))
-#define INCA_IP_IOM_CO_TSDP20_DPS (1 << 7)
-#define INCA_IP_IOM_CO_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Time Slot and Data Port Sel. (CH21)***/
-#define INCA_IP_IOM_CO_TSDP21 ((volatile u32*)(INCA_IP_IOM+ 0x012C))
-#define INCA_IP_IOM_CO_TSDP21_DPS (1 << 7)
-#define INCA_IP_IOM_CO_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Ctrl. Reg. Contr. Data Access CH1x***/
-#define INCA_IP_IOM_CDA1_CR ((volatile u32*)(INCA_IP_IOM+ 0x0138))
-#define INCA_IP_IOM_CDA1_CR_EN_TBM (1 << 5)
-#define INCA_IP_IOM_CDA1_CR_EN_I1 (1 << 4)
-#define INCA_IP_IOM_CDA1_CR_EN_I0 (1 << 3)
-#define INCA_IP_IOM_CDA1_CR_EN_O1 (1 << 2)
-#define INCA_IP_IOM_CDA1_CR_EN_O0 (1 << 1)
-#define INCA_IP_IOM_CDA1_CR_SWAP (1 << 0)
-
-/***Ctrl. Reg. Contr. Data Access CH1x***/
-#define INCA_IP_IOM_CDA2_CR ((volatile u32*)(INCA_IP_IOM+ 0x013C))
-#define INCA_IP_IOM_CDA2_CR_EN_TBM (1 << 5)
-#define INCA_IP_IOM_CDA2_CR_EN_I1 (1 << 4)
-#define INCA_IP_IOM_CDA2_CR_EN_I0 (1 << 3)
-#define INCA_IP_IOM_CDA2_CR_EN_O1 (1 << 2)
-#define INCA_IP_IOM_CDA2_CR_EN_O0 (1 << 1)
-#define INCA_IP_IOM_CDA2_CR_SWAP (1 << 0)
-
-/***Control Register B-Channel Data***/
-#define INCA_IP_IOM_BCHA_CR ((volatile u32*)(INCA_IP_IOM+ 0x0144))
-#define INCA_IP_IOM_BCHA_CR_EN_BC2 (1 << 4)
-#define INCA_IP_IOM_BCHA_CR_EN_BC1 (1 << 3)
-
-/***Control Register B-Channel Data***/
-#define INCA_IP_IOM_BCHB_CR ((volatile u32*)(INCA_IP_IOM+ 0x0148))
-#define INCA_IP_IOM_BCHB_CR_EN_BC2 (1 << 4)
-#define INCA_IP_IOM_BCHB_CR_EN_BC1 (1 << 3)
-
-/***Control Reg. for HDLC and CI1 Data***/
-#define INCA_IP_IOM_DCI_CR ((volatile u32*)(INCA_IP_IOM+ 0x014C))
-#define INCA_IP_IOM_DCI_CR_DPS_CI1 (1 << 7)
-#define INCA_IP_IOM_DCI_CR_EN_CI1 (1 << 6)
-#define INCA_IP_IOM_DCI_CR_EN_D (1 << 5)
-
-/***Control Reg. for HDLC and CI1 Data***/
-#define INCA_IP_IOM_DCIC_CR ((volatile u32*)(INCA_IP_IOM+ 0x014C))
-#define INCA_IP_IOM_DCIC_CR_DPS_CI0 (1 << 7)
-#define INCA_IP_IOM_DCIC_CR_EN_CI0 (1 << 6)
-#define INCA_IP_IOM_DCIC_CR_DPS_D (1 << 5)
-
-/***Control Reg. Serial Data Strobe x***/
-#define INCA_IP_IOM_SDS_CR ((volatile u32*)(INCA_IP_IOM+ 0x0154))
-#define INCA_IP_IOM_SDS_CR_ENS_TSS (1 << 7)
-#define INCA_IP_IOM_SDS_CR_ENS_TSS_1 (1 << 6)
-#define INCA_IP_IOM_SDS_CR_ENS_TSS_3 (1 << 5)
-#define INCA_IP_IOM_SDS_CR_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Control Register IOM Data***/
-#define INCA_IP_IOM_IOM_CR ((volatile u32*)(INCA_IP_IOM+ 0x015C))
-#define INCA_IP_IOM_IOM_CR_SPU (1 << 7)
-#define INCA_IP_IOM_IOM_CR_CI_CS (1 << 5)
-#define INCA_IP_IOM_IOM_CR_TIC_DIS (1 << 4)
-#define INCA_IP_IOM_IOM_CR_EN_BCL (1 << 3)
-#define INCA_IP_IOM_IOM_CR_CLKM (1 << 2)
-#define INCA_IP_IOM_IOM_CR_Res (1 << 1)
-#define INCA_IP_IOM_IOM_CR_DIS_IOM (1 << 0)
-
-/***Synchronous Transfer Interrupt***/
-#define INCA_IP_IOM_STI ((volatile u32*)(INCA_IP_IOM+ 0x0160))
-#define INCA_IP_IOM_STI_STOV21 (1 << 7)
-#define INCA_IP_IOM_STI_STOV20 (1 << 6)
-#define INCA_IP_IOM_STI_STOV11 (1 << 5)
-#define INCA_IP_IOM_STI_STOV10 (1 << 4)
-#define INCA_IP_IOM_STI_STI21 (1 << 3)
-#define INCA_IP_IOM_STI_STI20 (1 << 2)
-#define INCA_IP_IOM_STI_STI11 (1 << 1)
-#define INCA_IP_IOM_STI_STI10 (1 << 0)
-
-/***Acknowledge Synchronous Transfer Interrupt***/
-#define INCA_IP_IOM_ASTI ((volatile u32*)(INCA_IP_IOM+ 0x0160))
-#define INCA_IP_IOM_ASTI_ACK21 (1 << 3)
-#define INCA_IP_IOM_ASTI_ACK20 (1 << 2)
-#define INCA_IP_IOM_ASTI_ACK11 (1 << 1)
-#define INCA_IP_IOM_ASTI_ACK10 (1 << 0)
-
-/***Mask Synchronous Transfer Interrupt***/
-#define INCA_IP_IOM_MSTI ((volatile u32*)(INCA_IP_IOM+ 0x0164))
-#define INCA_IP_IOM_MSTI_STOV21 (1 << 7)
-#define INCA_IP_IOM_MSTI_STOV20 (1 << 6)
-#define INCA_IP_IOM_MSTI_STOV11 (1 << 5)
-#define INCA_IP_IOM_MSTI_STOV10 (1 << 4)
-#define INCA_IP_IOM_MSTI_STI21 (1 << 3)
-#define INCA_IP_IOM_MSTI_STI20 (1 << 2)
-#define INCA_IP_IOM_MSTI_STI11 (1 << 1)
-#define INCA_IP_IOM_MSTI_STI10 (1 << 0)
-
-/***Configuration Register for Serial Data Strobes***/
-#define INCA_IP_IOM_SDS_CONF ((volatile u32*)(INCA_IP_IOM+ 0x0168))
-#define INCA_IP_IOM_SDS_CONF_SDS_BCL (1 << 0)
-
-/***Monitoring CDA Bits***/
-#define INCA_IP_IOM_MCDA ((volatile u32*)(INCA_IP_IOM+ 0x016C))
-#define INCA_IP_IOM_MCDA_MCDA21 (value) (((( 1 << 2) - 1) & (value)) << 6)
-#define INCA_IP_IOM_MCDA_MCDA20 (value) (((( 1 << 2) - 1) & (value)) << 4)
-#define INCA_IP_IOM_MCDA_MCDA11 (value) (((( 1 << 2) - 1) & (value)) << 2)
-#define INCA_IP_IOM_MCDA_MCDA10 (value) (((( 1 << 2) - 1) & (value)) << 0)
-
-/***********************************************************************/
-/* Module : ASC register address and bits */
-/***********************************************************************/
-
-#if defined(CONFIG_INCA_IP)
-#define INCA_IP_ASC (0xB8000400)
-#elif defined(CONFIG_PURPLE)
-#define INCA_IP_ASC (0xBE500000)
-#endif
-
-/***********************************************************************/
-
-
-/***ASC Port Input Select Register***/
-#define INCA_IP_ASC_ASC_PISEL ((volatile u32*)(INCA_IP_ASC+ 0x0004))
-#define INCA_IP_ASC_ASC_PISEL_RIS (1 << 0)
-
-/***ASC Control Register***/
-#define INCA_IP_ASC_ASC_CON ((volatile u32*)(INCA_IP_ASC+ 0x0010))
-#define INCA_IP_ASC_ASC_CON_R (1 << 15)
-#define INCA_IP_ASC_ASC_CON_LB (1 << 14)
-#define INCA_IP_ASC_ASC_CON_BRS (1 << 13)
-#define INCA_IP_ASC_ASC_CON_ODD (1 << 12)
-#define INCA_IP_ASC_ASC_CON_FDE (1 << 11)
-#define INCA_IP_ASC_ASC_CON_OE (1 << 10)
-#define INCA_IP_ASC_ASC_CON_FE (1 << 9)
-#define INCA_IP_ASC_ASC_CON_PE (1 << 8)
-#define INCA_IP_ASC_ASC_CON_OEN (1 << 7)
-#define INCA_IP_ASC_ASC_CON_FEN (1 << 6)
-#define INCA_IP_ASC_ASC_CON_PENRXDI (1 << 5)
-#define INCA_IP_ASC_ASC_CON_REN (1 << 4)
-#define INCA_IP_ASC_ASC_CON_STP (1 << 3)
-#define INCA_IP_ASC_ASC_CON_M (value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***ASC Write Hardware Modified Control Register***/
-#define INCA_IP_ASC_ASC_WHBCON ((volatile u32*)(INCA_IP_ASC+ 0x0050))
-#define INCA_IP_ASC_ASC_WHBCON_SETOE (1 << 13)
-#define INCA_IP_ASC_ASC_WHBCON_SETFE (1 << 12)
-#define INCA_IP_ASC_ASC_WHBCON_SETPE (1 << 11)
-#define INCA_IP_ASC_ASC_WHBCON_CLROE (1 << 10)
-#define INCA_IP_ASC_ASC_WHBCON_CLRFE (1 << 9)
-#define INCA_IP_ASC_ASC_WHBCON_CLRPE (1 << 8)
-#define INCA_IP_ASC_ASC_WHBCON_SETREN (1 << 5)
-#define INCA_IP_ASC_ASC_WHBCON_CLRREN (1 << 4)
-
-/***ASC Baudrate Timer/Reload Register***/
-#define INCA_IP_ASC_ASC_BTR ((volatile u32*)(INCA_IP_ASC+ 0x0014))
-#define INCA_IP_ASC_ASC_BTR_BR_VALUE (value) (((( 1 << 13) - 1) & (value)) << 0)
-
-/***ASC Fractional Divider Register***/
-#define INCA_IP_ASC_ASC_FDV ((volatile u32*)(INCA_IP_ASC+ 0x0018))
-#define INCA_IP_ASC_ASC_FDV_FD_VALUE (value) (((( 1 << 9) - 1) & (value)) << 0)
-
-/***ASC IrDA Pulse Mode/Width Register***/
-#define INCA_IP_ASC_ASC_PMW ((volatile u32*)(INCA_IP_ASC+ 0x001C))
-#define INCA_IP_ASC_ASC_PMW_IRPW (1 << 8)
-#define INCA_IP_ASC_ASC_PMW_PW_VALUE (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***ASC Transmit Buffer Register***/
-#define INCA_IP_ASC_ASC_TBUF ((volatile u32*)(INCA_IP_ASC+ 0x0020))
-#define INCA_IP_ASC_ASC_TBUF_TD_VALUE (value) (((( 1 << 9) - 1) & (value)) << 0)
-
-/***ASC Receive Buffer Register***/
-#define INCA_IP_ASC_ASC_RBUF ((volatile u32*)(INCA_IP_ASC+ 0x0024))
-#define INCA_IP_ASC_ASC_RBUF_RD_VALUE (value) (((( 1 << 9) - 1) & (value)) << 0)
-
-/***ASC Autobaud Control Register***/
-#define INCA_IP_ASC_ASC_ABCON ((volatile u32*)(INCA_IP_ASC+ 0x0030))
-#define INCA_IP_ASC_ASC_ABCON_RXINV (1 << 11)
-#define INCA_IP_ASC_ASC_ABCON_TXINV (1 << 10)
-#define INCA_IP_ASC_ASC_ABCON_ABEM (value) (((( 1 << 2) - 1) & (value)) << 8)
-#define INCA_IP_ASC_ASC_ABCON_FCDETEN (1 << 4)
-#define INCA_IP_ASC_ASC_ABCON_ABDETEN (1 << 3)
-#define INCA_IP_ASC_ASC_ABCON_ABSTEN (1 << 2)
-#define INCA_IP_ASC_ASC_ABCON_AUREN (1 << 1)
-#define INCA_IP_ASC_ASC_ABCON_ABEN (1 << 0)
-
-/***Receive FIFO Control Register***/
-#define INCA_IP_ASC_RXFCON ((volatile u32*)(INCA_IP_ASC+ 0x0040))
-#define INCA_IP_ASC_RXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8)
-#define INCA_IP_ASC_RXFCON_RXTMEN (1 << 2)
-#define INCA_IP_ASC_RXFCON_RXFFLU (1 << 1)
-#define INCA_IP_ASC_RXFCON_RXFEN (1 << 0)
-
-/***Transmit FIFO Control Register***/
-#define INCA_IP_ASC_TXFCON ((volatile u32*)(INCA_IP_ASC+ 0x0044))
-#define INCA_IP_ASC_TXFCON_TXFITL (value) (((( 1 << 6) - 1) & (value)) << 8)
-#define INCA_IP_ASC_TXFCON_TXTMEN (1 << 2)
-#define INCA_IP_ASC_TXFCON_TXFFLU (1 << 1)
-#define INCA_IP_ASC_TXFCON_TXFEN (1 << 0)
-
-/***FIFO Status Register***/
-#define INCA_IP_ASC_FSTAT ((volatile u32*)(INCA_IP_ASC+ 0x0048))
-#define INCA_IP_ASC_FSTAT_TXFFL (value) (((( 1 << 6) - 1) & (value)) << 8)
-#define INCA_IP_ASC_FSTAT_RXFFL (value) (((( 1 << 6) - 1) & (value)) << 0)
-
-/***ASC Write HW Modified Autobaud Control Register***/
-#define INCA_IP_ASC_ASC_WHBABCON ((volatile u32*)(INCA_IP_ASC+ 0x0054))
-#define INCA_IP_ASC_ASC_WHBABCON_SETABEN (1 << 1)
-#define INCA_IP_ASC_ASC_WHBABCON_CLRABEN (1 << 0)
-
-/***ASC Autobaud Status Register***/
-#define INCA_IP_ASC_ASC_ABSTAT ((volatile u32*)(INCA_IP_ASC+ 0x0034))
-#define INCA_IP_ASC_ASC_ABSTAT_DETWAIT (1 << 4)
-#define INCA_IP_ASC_ASC_ABSTAT_SCCDET (1 << 3)
-#define INCA_IP_ASC_ASC_ABSTAT_SCSDET (1 << 2)
-#define INCA_IP_ASC_ASC_ABSTAT_FCCDET (1 << 1)
-#define INCA_IP_ASC_ASC_ABSTAT_FCSDET (1 << 0)
-
-/***ASC Write HW Modified Autobaud Status Register***/
-#define INCA_IP_ASC_ASC_WHBABSTAT ((volatile u32*)(INCA_IP_ASC+ 0x0058))
-#define INCA_IP_ASC_ASC_WHBABSTAT_SETDETWAIT (1 << 9)
-#define INCA_IP_ASC_ASC_WHBABSTAT_CLRDETWAIT (1 << 8)
-#define INCA_IP_ASC_ASC_WHBABSTAT_SETSCCDET (1 << 7)
-#define INCA_IP_ASC_ASC_WHBABSTAT_CLRSCCDET (1 << 6)
-#define INCA_IP_ASC_ASC_WHBABSTAT_SETSCSDET (1 << 5)
-#define INCA_IP_ASC_ASC_WHBABSTAT_CLRSCSDET (1 << 4)
-#define INCA_IP_ASC_ASC_WHBABSTAT_SETFCCDET (1 << 3)
-#define INCA_IP_ASC_ASC_WHBABSTAT_CLRFCCDET (1 << 2)
-#define INCA_IP_ASC_ASC_WHBABSTAT_SETFCSDET (1 << 1)
-#define INCA_IP_ASC_ASC_WHBABSTAT_CLRFCSDET (1 << 0)
-
-/***ASC Clock Control Register***/
-#define INCA_IP_ASC_ASC_CLC ((volatile u32*)(INCA_IP_ASC+ 0x0000))
-#define INCA_IP_ASC_ASC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_ASC_ASC_CLC_DISS (1 << 1)
-#define INCA_IP_ASC_ASC_CLC_DISR (1 << 0)
-
-/***********************************************************************/
-/* Module : DMA register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_DMA (0xBF108000)
-/***********************************************************************/
-
-
-/***DMA RX Channel 0 Command Register***/
-#define INCA_IP_DMA_DMA_RXCCR0 ((volatile u32*)(INCA_IP_DMA+ 0x0800))
-#define INCA_IP_DMA_DMA_RXCCR0_LBE (1 << 31)
-#define INCA_IP_DMA_DMA_RXCCR0_HPEN (1 << 30)
-#define INCA_IP_DMA_DMA_RXCCR0_INIT (1 << 2)
-#define INCA_IP_DMA_DMA_RXCCR0_OFF (1 << 1)
-#define INCA_IP_DMA_DMA_RXCCR0_HR (1 << 0)
-
-/***DMA RX Channel 1 Command Register***/
-#define INCA_IP_DMA_DMA_RXCCR1 ((volatile u32*)(INCA_IP_DMA+ 0x0804))
-#define INCA_IP_DMA_DMA_RXCCR1_LBE (1 << 31)
-#define INCA_IP_DMA_DMA_RXCCR1_HPEN (1 << 30)
-#define INCA_IP_DMA_DMA_RXCCR1_INIT (1 << 2)
-#define INCA_IP_DMA_DMA_RXCCR1_OFF (1 << 1)
-#define INCA_IP_DMA_DMA_RXCCR1_HR (1 << 0)
-
-/***DMA Receive Interrupt Status Register***/
-#define INCA_IP_DMA_DMA_RXISR ((volatile u32*)(INCA_IP_DMA+ 0x0808))
-#define INCA_IP_DMA_DMA_RXISR_RDERRx (value) (((( 1 << 2) - 1) & (value)) << 8)
-#define INCA_IP_DMA_DMA_RXISR_CMDCPTx (value) (((( 1 << 2) - 1) & (value)) << 6)
-#define INCA_IP_DMA_DMA_RXISR_EOPx (value) (((( 1 << 2) - 1) & (value)) << 4)
-#define INCA_IP_DMA_DMA_RXISR_CPTx (value) (((( 1 << 2) - 1) & (value)) << 2)
-#define INCA_IP_DMA_DMA_RXISR_HLDx (value) (((( 1 << 2) - 1) & (value)) << 0)
-
-/***DMA Receive Interrupt Mask Register***/
-#define INCA_IP_DMA_DMA_RXIMR ((volatile u32*)(INCA_IP_DMA+ 0x080C))
-#define INCA_IP_DMA_DMA_RXIMR_RDERRx (value) (((( 1 << 2) - 1) & (value)) << 8)
-#define INCA_IP_DMA_DMA_RXIMR_CMDCPTx (value) (((( 1 << 2) - 1) & (value)) << 6)
-#define INCA_IP_DMA_DMA_RXIMR_EOPx (value) (((( 1 << 2) - 1) & (value)) << 4)
-#define INCA_IP_DMA_DMA_RXIMR_CPTx (value) (((( 1 << 2) - 1) & (value)) << 2)
-#define INCA_IP_DMA_DMA_RXIMR_HLDx (value) (((( 1 << 2) - 1) & (value)) << 0)
-
-/***DMA First Receive Descriptor Addr. for Rx Channel 0
-***/
-#define INCA_IP_DMA_DMA_RXFRDA0 ((volatile u32*)(INCA_IP_DMA+ 0x0810))
-#define INCA_IP_DMA_DMA_RXFRDA0_RXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0)
-
-/***DMA First Receive Descriptor Addr. for Rx Channel 1
-***/
-#define INCA_IP_DMA_DMA_RXFRDA1 ((volatile u32*)(INCA_IP_DMA+ 0x0814))
-#define INCA_IP_DMA_DMA_RXFRDA1_RXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0)
-
-/***DMA Receive Channel Polling Time***/
-#define INCA_IP_DMA_DMA_RXPOLL ((volatile u32*)(INCA_IP_DMA+ 0x0818))
-#define INCA_IP_DMA_DMA_RXPOLL_BSZ1 (value) (((( 1 << 2) - 1) & (value)) << 30)
-#define INCA_IP_DMA_DMA_RXPOLL_BSZ0 (value) (((( 1 << 2) - 1) & (value)) << 28)
-#define INCA_IP_DMA_DMA_RXPOLL_RXPOLLTIME (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***DMA TX Channel 0 Command Register (Voice Port)***/
-#define INCA_IP_DMA_DMA_TXCCR0 ((volatile u32*)(INCA_IP_DMA+ 0x0880))
-#define INCA_IP_DMA_DMA_TXCCR0_LBE (1 << 31)
-#define INCA_IP_DMA_DMA_TXCCR0_HPEN (1 << 30)
-#define INCA_IP_DMA_DMA_TXCCR0_HR (1 << 2)
-#define INCA_IP_DMA_DMA_TXCCR0_OFF (1 << 1)
-#define INCA_IP_DMA_DMA_TXCCR0_INIT (1 << 0)
-
-/***DMA TX Channel 1 Command Register (Mangmt Port)***/
-#define INCA_IP_DMA_DMA_TXCCR1 ((volatile u32*)(INCA_IP_DMA+ 0x0884))
-#define INCA_IP_DMA_DMA_TXCCR1_LBE (1 << 31)
-#define INCA_IP_DMA_DMA_TXCCR1_HPEN (1 << 30)
-#define INCA_IP_DMA_DMA_TXCCR1_HR (1 << 2)
-#define INCA_IP_DMA_DMA_TXCCR1_OFF (1 << 1)
-#define INCA_IP_DMA_DMA_TXCCR1_INIT (1 << 0)
-
-/***DMA TX Channel 2 Command Register (SSC Port)***/
-#define INCA_IP_DMA_DMA_TXCCR2 ((volatile u32*)(INCA_IP_DMA+ 0x0888))
-#define INCA_IP_DMA_DMA_TXCCR2_LBE (1 << 31)
-#define INCA_IP_DMA_DMA_TXCCR2_HPEN (1 << 30)
-#define INCA_IP_DMA_DMA_TXCCR2_HBF (1 << 29)
-#define INCA_IP_DMA_DMA_TXCCR2_HR (1 << 2)
-#define INCA_IP_DMA_DMA_TXCCR2_OFF (1 << 1)
-#define INCA_IP_DMA_DMA_TXCCR2_INIT (1 << 0)
-
-/***DMA First Receive Descriptor Addr. for Tx Channel 0
-***/
-#define INCA_IP_DMA_DMA_TXFRDA0 ((volatile u32*)(INCA_IP_DMA+ 0x08A0))
-#define INCA_IP_DMA_DMA_TXFRDA0_TXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0)
-
-/***DMA First Receive Descriptor Addr. for Tx Channel 1
-***/
-#define INCA_IP_DMA_DMA_TXFRDA1 ((volatile u32*)(INCA_IP_DMA+ 0x08A4))
-#define INCA_IP_DMA_DMA_TXFRDA1_TXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0)
-
-/***DMA First Receive Descriptor Addr. for Tx Channel 2
-***/
-#define INCA_IP_DMA_DMA_TXFRDA2 ((volatile u32*)(INCA_IP_DMA+ 0x08A8))
-#define INCA_IP_DMA_DMA_TXFRDA2_TXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0)
-
-/***DMA Transmit Channel Arbitration Register***/
-#define INCA_IP_DMA_DMA_TXWGT ((volatile u32*)(INCA_IP_DMA+ 0x08C0))
-#define INCA_IP_DMA_DMA_TXWGT_TX2PR (value) (((( 1 << 2) - 1) & (value)) << 4)
-#define INCA_IP_DMA_DMA_TXWGT_TX1PRI (value) (((( 1 << 2) - 1) & (value)) << 2)
-#define INCA_IP_DMA_DMA_TXWGT_TX0PRI (value) (((( 1 << 2) - 1) & (value)) << 0)
-
-/***DMA Transmit Channel Polling Time***/
-#define INCA_IP_DMA_DMA_TXPOLL ((volatile u32*)(INCA_IP_DMA+ 0x08C4))
-#define INCA_IP_DMA_DMA_TXPOLL_BSZ2 (value) (((( 1 << 2) - 1) & (value)) << 30)
-#define INCA_IP_DMA_DMA_TXPOLL_BSZ1 (value) (((( 1 << 2) - 1) & (value)) << 28)
-#define INCA_IP_DMA_DMA_TXPOLL_BSZ0 (value) (((( 1 << 2) - 1) & (value)) << 26)
-#define INCA_IP_DMA_DMA_TXPOLL_TXPOLLTIME (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***DMA Transmit Interrupt Status Register***/
-#define INCA_IP_DMA_DMA_TXISR ((volatile u32*)(INCA_IP_DMA+ 0x08C8))
-#define INCA_IP_DMA_DMA_TXISR_RDERRx (value) (((( 1 << 3) - 1) & (value)) << 12)
-#define INCA_IP_DMA_DMA_TXISR_HLDx (value) (((( 1 << 3) - 1) & (value)) << 9)
-#define INCA_IP_DMA_DMA_TXISR_CPTx (value) (((( 1 << 3) - 1) & (value)) << 6)
-#define INCA_IP_DMA_DMA_TXISR_EOPx (value) (((( 1 << 3) - 1) & (value)) << 3)
-#define INCA_IP_DMA_DMA_TXISR_CMDCPTx (value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***DMA Transmit Interrupt Mask Register***/
-#define INCA_IP_DMA_DMA_TXIMR ((volatile u32*)(INCA_IP_DMA+ 0x08CC))
-#define INCA_IP_DMA_DMA_TXIMR_RDERRx (value) (((( 1 << 3) - 1) & (value)) << 12)
-#define INCA_IP_DMA_DMA_TXIMR_HLDx (value) (((( 1 << 3) - 1) & (value)) << 9)
-#define INCA_IP_DMA_DMA_TXIMR_CPTx (value) (((( 1 << 3) - 1) & (value)) << 6)
-#define INCA_IP_DMA_DMA_TXIMR_EOPx (value) (((( 1 << 3) - 1) & (value)) << 3)
-#define INCA_IP_DMA_DMA_TXIMR_CMDCPTx (value) (((( 1 << 3) - 1) & (value)) << 0)
-
-/***********************************************************************/
-/* Module : Debug register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_Debug (0xBF106000)
-/***********************************************************************/
-
-
-/***MCD Break Bus Switch Register***/
-#define INCA_IP_Debug_MCD_BBS ((volatile u32*)(INCA_IP_Debug+ 0x0000))
-#define INCA_IP_Debug_MCD_BBS_BTP1 (1 << 19)
-#define INCA_IP_Debug_MCD_BBS_BTP0 (1 << 18)
-#define INCA_IP_Debug_MCD_BBS_BSP1 (1 << 17)
-#define INCA_IP_Debug_MCD_BBS_BSP0 (1 << 16)
-#define INCA_IP_Debug_MCD_BBS_BT5EN (1 << 15)
-#define INCA_IP_Debug_MCD_BBS_BT4EN (1 << 14)
-#define INCA_IP_Debug_MCD_BBS_BT5 (1 << 13)
-#define INCA_IP_Debug_MCD_BBS_BT4 (1 << 12)
-#define INCA_IP_Debug_MCD_BBS_BS5EN (1 << 7)
-#define INCA_IP_Debug_MCD_BBS_BS4EN (1 << 6)
-#define INCA_IP_Debug_MCD_BBS_BS5 (1 << 5)
-#define INCA_IP_Debug_MCD_BBS_BS4 (1 << 4)
-
-/***MCD Multiplexer Control Register***/
-#define INCA_IP_Debug_MCD_MCR ((volatile u32*)(INCA_IP_Debug+ 0x0008))
-#define INCA_IP_Debug_MCD_MCR_MUX5 (1 << 4)
-#define INCA_IP_Debug_MCD_MCR_MUX4 (1 << 3)
-#define INCA_IP_Debug_MCD_MCR_MUX1 (1 << 0)
-
-/***********************************************************************/
-/* Module : TSF register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_TSF (0xB8000900)
-/***********************************************************************/
-
-
-/***TSF Configuration Register (0000H)***/
-#define INCA_IP_TSF_TSF_CONF ((volatile u32*)(INCA_IP_TSF+ 0x0000))
-#define INCA_IP_TSF_TSF_CONF_PWMEN (1 << 2)
-#define INCA_IP_TSF_TSF_CONF_LEDEN (1 << 1)
-#define INCA_IP_TSF_TSF_CONF_KEYEN (1 << 0)
-
-/***Key scan Configuration Register (0004H)***/
-#define INCA_IP_TSF_KEY_CONF ((volatile u32*)(INCA_IP_TSF+ 0x0004))
-#define INCA_IP_TSF_KEY_CONF_SL (value) (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Scan Register Line 0 and 1 (0008H)***/
-#define INCA_IP_TSF_SREG01 ((volatile u32*)(INCA_IP_TSF+ 0x0008))
-#define INCA_IP_TSF_SREG01_RES1x (value) (((( 1 << 12) - 1) & (value)) << 16)
-#define INCA_IP_TSF_SREG01_RES0x (value) (((( 1 << 13) - 1) & (value)) << 0)
-
-/***Scan Register Line 2 and 3 (000CH)***/
-#define INCA_IP_TSF_SREG23 ((volatile u32*)(INCA_IP_TSF+ 0x000C))
-#define INCA_IP_TSF_SREG23_RES3x (value) (((( 1 << 10) - 1) & (value)) << 16)
-#define INCA_IP_TSF_SREG23_RES2x (value) (((( 1 << 11) - 1) & (value)) << 0)
-
-/***Scan Register Line 4, 5 and 6 (0010H)***/
-#define INCA_IP_TSF_SREG456 ((volatile u32*)(INCA_IP_TSF+ 0x0010))
-#define INCA_IP_TSF_SREG456_RES6x (value) (((( 1 << 7) - 1) & (value)) << 24)
-#define INCA_IP_TSF_SREG456_RES5x (value) (((( 1 << 8) - 1) & (value)) << 16)
-#define INCA_IP_TSF_SREG456_RES4x (value) (((( 1 << 9) - 1) & (value)) << 0)
-
-/***Scan Register Line 7 to 12 (0014H)***/
-#define INCA_IP_TSF_SREG7to12 ((volatile u32*)(INCA_IP_TSF+ 0x0014))
-#define INCA_IP_TSF_SREG7to12_RES12x (1 << 28)
-#define INCA_IP_TSF_SREG7to12_RES11x (value) (((( 1 << 2) - 1) & (value)) << 24)
-#define INCA_IP_TSF_SREG7to12_RES10x (value) (((( 1 << 3) - 1) & (value)) << 20)
-#define INCA_IP_TSF_SREG7to12_RES9x (value) (((( 1 << 4) - 1) & (value)) << 16)
-#define INCA_IP_TSF_SREG7to12_RES8x (value) (((( 1 << 5) - 1) & (value)) << 8)
-#define INCA_IP_TSF_SREG7to12_RES7x (value) (((( 1 << 6) - 1) & (value)) << 0)
-
-/***LEDMUX Configuration Register (0018H)***/
-#define INCA_IP_TSF_LEDMUX_CONF ((volatile u32*)(INCA_IP_TSF+ 0x0018))
-#define INCA_IP_TSF_LEDMUX_CONF_ETL1 (1 << 25)
-#define INCA_IP_TSF_LEDMUX_CONF_ESTA1 (1 << 24)
-#define INCA_IP_TSF_LEDMUX_CONF_EDPX1 (1 << 23)
-#define INCA_IP_TSF_LEDMUX_CONF_EACT1 (1 << 22)
-#define INCA_IP_TSF_LEDMUX_CONF_ESPD1 (1 << 21)
-#define INCA_IP_TSF_LEDMUX_CONF_ETL0 (1 << 20)
-#define INCA_IP_TSF_LEDMUX_CONF_ESTA0 (1 << 19)
-#define INCA_IP_TSF_LEDMUX_CONF_EDPX0 (1 << 18)
-#define INCA_IP_TSF_LEDMUX_CONF_EACT0 (1 << 17)
-#define INCA_IP_TSF_LEDMUX_CONF_ESPD0 (1 << 16)
-#define INCA_IP_TSF_LEDMUX_CONF_INV (1 << 1)
-#define INCA_IP_TSF_LEDMUX_CONF_NCOL (1 << 0)
-
-/***LED Register (001CH)***/
-#define INCA_IP_TSF_LED_REG ((volatile u32*)(INCA_IP_TSF+ 0x001C))
-#define INCA_IP_TSF_LED_REG_Lxy (value) (((( 1 << 24) - 1) & (value)) << 0)
-
-/***Pulse Width Modulator 1 and 2 Register (0020H)***/
-#define INCA_IP_TSF_PWM12 ((volatile u32*)(INCA_IP_TSF+ 0x0020))
-#define INCA_IP_TSF_PWM12_PW2PW1 (value) (((( 1 << NaN) - 1) & (value)) << NaN)
-
-/***********************************************************************/
-/* Module : Ports register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_Ports (0xB8000A00)
-/***********************************************************************/
-
-
-/***Port 1 Data Output Register (0020H)***/
-#define INCA_IP_Ports_P1_OUT ((volatile u32*)(INCA_IP_Ports+ 0x0020))
-#define INCA_IP_Ports_P1_OUT_P(value) (1 << value)
-
-
-/***Port 2 Data Output Register (0040H)***/
-#define INCA_IP_Ports_P2_OUT ((volatile u32*)(INCA_IP_Ports+ 0x0040))
-#define INCA_IP_Ports_P2_OUT_P(value) (1 << value)
-
-
-/***Port 1 Data Input Register (0024H)***/
-#define INCA_IP_Ports_P1_IN ((volatile u32*)(INCA_IP_Ports+ 0x0024))
-#define INCA_IP_Ports_P1_IN_P(value) (1 << value)
-
-
-/***Port 2 Data Input Register (0044H)***/
-#define INCA_IP_Ports_P2_IN ((volatile u32*)(INCA_IP_Ports+ 0x0044))
-#define INCA_IP_Ports_P2_IN_P(value) (1 << value)
-
-
-/***Port 1 Direction Register (0028H)***/
-#define INCA_IP_Ports_P1_DIR ((volatile u32*)(INCA_IP_Ports+ 0x0028))
-#define INCA_IP_Ports_P1_DIR_Port1P(value) (1 << value)
-
-#define INCA_IP_Ports_P1_DIR_Port2Pn (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***Port 2 Direction Register (0048H)***/
-#define INCA_IP_Ports_P2_DIR ((volatile u32*)(INCA_IP_Ports+ 0x0048))
-#define INCA_IP_Ports_P2_DIR_Port1P(value) (1 << value)
-
-#define INCA_IP_Ports_P2_DIR_Port2Pn (value) (((( 1 << 16) - 1) & (value)) << 0)
-
-/***Port 0 Alternate Function Select Register 0 (000C H)
-***/
-#define INCA_IP_Ports_P0_ALTSEL ((volatile u32*)(INCA_IP_Ports+ 0x000C))
-#define INCA_IP_Ports_P0_ALTSEL_Port0P(value) (1 << value)
-
-
-/***Port 1 Alternate Function Select Register 0 (002C H)
-***/
-#define INCA_IP_Ports_P1_ALTSEL ((volatile u32*)(INCA_IP_Ports+ 0x002C))
-#define INCA_IP_Ports_P1_ALTSEL_Port1P(value) (1 << value)
-
-#define INCA_IP_Ports_P1_ALTSEL_Port2P(value) (1 << value)
-
-
-/***Port 2 Alternate Function Select Register 0 (004C H)
-***/
-#define INCA_IP_Ports_P2_ALTSEL ((volatile u32*)(INCA_IP_Ports+ 0x004C))
-#define INCA_IP_Ports_P2_ALTSEL_Port1P(value) (1 << value)
-
-#define INCA_IP_Ports_P2_ALTSEL_Port2P(value) (1 << value)
-
-
-/***Port 0 Input Schmitt-Trigger Off Register (0010 H)
-***/
-#define INCA_IP_Ports_P0_STOFF ((volatile u32*)(INCA_IP_Ports+ 0x0010))
-#define INCA_IP_Ports_P0_STOFF_Port0P(value) (1 << value)
-
-
-/***Port 1 Input Schmitt-Trigger Off Register (0030 H)
-***/
-#define INCA_IP_Ports_P1_STOFF ((volatile u32*)(INCA_IP_Ports+ 0x0030))
-#define INCA_IP_Ports_P1_STOFF_Port1P(value) (1 << value)
-
-#define INCA_IP_Ports_P1_STOFF_Port2P(value) (1 << value)
-
-
-/***Port 2 Input Schmitt-Trigger Off Register (0050 H)
-***/
-#define INCA_IP_Ports_P2_STOFF ((volatile u32*)(INCA_IP_Ports+ 0x0050))
-#define INCA_IP_Ports_P2_STOFF_Port1P(value) (1 << value)
-
-#define INCA_IP_Ports_P2_STOFF_Port2P(value) (1 << value)
-
-
-/***Port 2 Open Drain Control Register (0054H)***/
-#define INCA_IP_Ports_P2_OD ((volatile u32*)(INCA_IP_Ports+ 0x0054))
-#define INCA_IP_Ports_P2_OD_Port2P(value) (1 << value)
-
-
-/***Port 0 Pull Up Device Enable Register (0018 H)***/
-#define INCA_IP_Ports_P0_PUDEN ((volatile u32*)(INCA_IP_Ports+ 0x0018))
-#define INCA_IP_Ports_P0_PUDEN_Port0P(value) (1 << value)
-
-
-/***Port 2 Pull Up Device Enable Register (0058 H)***/
-#define INCA_IP_Ports_P2_PUDEN ((volatile u32*)(INCA_IP_Ports+ 0x0058))
-#define INCA_IP_Ports_P2_PUDEN_Port2P(value) (1 << value)
-
-#define INCA_IP_Ports_P2_PUDEN_Port2P(value) (1 << value)
-
-
-/***Port 0 Pull Up/Pull Down Select Register (001C H)***/
-#define INCA_IP_Ports_P0_PUDSEL ((volatile u32*)(INCA_IP_Ports+ 0x001C))
-#define INCA_IP_Ports_P0_PUDSEL_Port0P(value) (1 << value)
-
-
-/***Port 2 Pull Up/Pull Down Select Register (005C H)***/
-#define INCA_IP_Ports_P2_PUDSEL ((volatile u32*)(INCA_IP_Ports+ 0x005C))
-#define INCA_IP_Ports_P2_PUDSEL_Port2P(value) (1 << value)
-
-#define INCA_IP_Ports_P2_PUDSEL_Port2P(value) (1 << value)
-
-
-/***********************************************************************/
-/* Module : DES/3DES register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_DES_3DES (0xB8000800)
-/***********************************************************************/
-
-
-/***DES Input Data High Register***/
-#define INCA_IP_DES_3DES_DES_IHR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0000))
-#define INCA_IP_DES_3DES_DES_IHR_IH(value) (1 << value)
-
-
-/***DES Input Data Low Register***/
-#define INCA_IP_DES_3DES_DES_ILR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0004))
-#define INCA_IP_DES_3DES_DES_ILR_IL(value) (1 << value)
-
-
-/***DES Key #1 High Register***/
-#define INCA_IP_DES_3DES_DES_K1HR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0008))
-#define INCA_IP_DES_3DES_DES_K1HR_K1H(value) (1 << value)
-
-
-/***DES Key #1 Low Register***/
-#define INCA_IP_DES_3DES_DES_K1LR ((volatile u32*)(INCA_IP_DES_3DES+ 0x000C))
-#define INCA_IP_DES_3DES_DES_K1LR_K1L(value) (1 << value)
-
-
-/***DES Key #2 High Register***/
-#define INCA_IP_DES_3DES_DES_K2HR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0010))
-#define INCA_IP_DES_3DES_DES_K2HR_K2H(value) (1 << value)
-
-
-/***DES Key #2 Low Register***/
-#define INCA_IP_DES_3DES_DES_K2LR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0014))
-#define INCA_IP_DES_3DES_DES_K2LR_K2L(value) (1 << value)
-
-
-/***DES Key #3 High Register***/
-#define INCA_IP_DES_3DES_DES_K3HR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0018))
-#define INCA_IP_DES_3DES_DES_K3HR_K3H(value) (1 << value)
-
-
-/***DES Key #3 Low Register***/
-#define INCA_IP_DES_3DES_DES_K3LR ((volatile u32*)(INCA_IP_DES_3DES+ 0x001C))
-#define INCA_IP_DES_3DES_DES_K3LR_K3L(value) (1 << value)
-
-
-/***DES Initialization Vector High Register***/
-#define INCA_IP_DES_3DES_DES_IVHR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0020))
-#define INCA_IP_DES_3DES_DES_IVHR_IVH(value) (1 << value)
-
-
-/***DES Initialization Vector Low Register***/
-#define INCA_IP_DES_3DES_DES_IVLR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0024))
-#define INCA_IP_DES_3DES_DES_IVLR_IVL(value) (1 << value)
-
-
-/***DES Control Register***/
-#define INCA_IP_DES_3DES_DES_CONTROLR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0028))
-#define INCA_IP_DES_3DES_DES_CONTROLR_KRE (1 << 31)
-#define INCA_IP_DES_3DES_DES_CONTROLR_DAU (1 << 16)
-#define INCA_IP_DES_3DES_DES_CONTROLR_F(value) (1 << value)
-
-#define INCA_IP_DES_3DES_DES_CONTROLR_O(value) (1 << value)
-
-#define INCA_IP_DES_3DES_DES_CONTROLR_GO (1 << 8)
-#define INCA_IP_DES_3DES_DES_CONTROLR_STP (1 << 7)
-#define INCA_IP_DES_3DES_DES_CONTROLR_IEN (1 << 6)
-#define INCA_IP_DES_3DES_DES_CONTROLR_BUS (1 << 5)
-#define INCA_IP_DES_3DES_DES_CONTROLR_SM (1 << 4)
-#define INCA_IP_DES_3DES_DES_CONTROLR_E_D (1 << 3)
-#define INCA_IP_DES_3DES_DES_CONTROLR_M(value) (1 << value)
-
-
-/***DES Output Data High Register***/
-#define INCA_IP_DES_3DES_DES_OHR ((volatile u32*)(INCA_IP_DES_3DES+ 0x002C))
-#define INCA_IP_DES_3DES_DES_OHR_OH(value) (1 << value)
-
-
-/***DES Output Data Low Register***/
-#define INCA_IP_DES_3DES_DES_OLR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0030))
-#define INCA_IP_DES_3DES_DES_OLR_OL(value) (1 << value)
-
-
-/***********************************************************************/
-/* Module : AES register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_AES (0xB8000880)
-/***********************************************************************/
-
-
-/***AES Input Data 3 Register***/
-#define INCA_IP_AES_AES_ID3R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_ID3R_I(value) (1 << value)
-
-
-/***AES Input Data 2 Register***/
-#define INCA_IP_AES_AES_ID2R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_ID2R_I(value) (1 << value)
-
-
-/***AES Input Data 1 Register***/
-#define INCA_IP_AES_AES_ID1R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_ID1R_I(value) (1 << value)
-
-
-/***AES Input Data 0 Register***/
-#define INCA_IP_AES_AES_ID0R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_ID0R_I(value) (1 << value)
-
-
-/***AES Output Data 3 Register***/
-#define INCA_IP_AES_AES_OD3R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_OD3R_O(value) (1 << value)
-
-
-/***AES Output Data 2 Register***/
-#define INCA_IP_AES_AES_OD2R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_OD2R_O(value) (1 << value)
-
-
-/***AES Output Data 1 Register***/
-#define INCA_IP_AES_AES_OD1R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_OD1R_O(value) (1 << value)
-
-
-/***AES Output Data 0 Register***/
-#define INCA_IP_AES_AES_OD0R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_OD0R_O(value) (1 << value)
-
-
-/***AES Key 7 Register***/
-#define INCA_IP_AES_AES_K7R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_K7R_K(value) (1 << value)
-
-
-/***AES Key 6 Register***/
-#define INCA_IP_AES_AES_K6R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_K6R_K(value) (1 << value)
-
-
-/***AES Key 5 Register***/
-#define INCA_IP_AES_AES_K5R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_K5R_K(value) (1 << value)
-
-
-/***AES Key 4 Register***/
-#define INCA_IP_AES_AES_K4R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_K4R_K(value) (1 << value)
-
-
-/***AES Key 3 Register***/
-#define INCA_IP_AES_AES_K3R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_K3R_K(value) (1 << value)
-
-
-/***AES Key 2 Register***/
-#define INCA_IP_AES_AES_K2R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_K2R_K(value) (1 << value)
-
-
-/***AES Key 1 Register***/
-#define INCA_IP_AES_AES_K1R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_K1R_K(value) (1 << value)
-
-
-/***AES Key 0 Register***/
-#define INCA_IP_AES_AES_K0R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_K0R_K(value) (1 << value)
-
-
-/***AES Initialization Vector 3 Register***/
-#define INCA_IP_AES_AES_IV3R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_IV3R_IV(value) (1 << value)
-
-
-/***AES Initialization Vector 2 Register***/
-#define INCA_IP_AES_AES_IV2R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_IV2R_IV(value) (1 << value)
-
-
-/***AES Initialization Vector 1 Register***/
-#define INCA_IP_AES_AES_IV1R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_IV1R_IV(value) (1 << value)
-
-
-/***AES Initialization Vector 0 Register***/
-#define INCA_IP_AES_AES_IV0R ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_IV0R_IV (value) (((( 1 << 32) - 1) &(value)) << 0)
-
-/***AES Control Register***/
-#define INCA_IP_AES_AES_CONTROLR ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_CONTROLR_KRE (1 << 31)
-#define INCA_IP_AES_AES_CONTROLR_DAU (1 << 16)
-#define INCA_IP_AES_AES_CONTROLR_PNK (1 << 15)
-#define INCA_IP_AES_AES_CONTROLR_F(value) (1 << value)
-
-#define INCA_IP_AES_AES_CONTROLR_O(value) (1 << value)
-
-#define INCA_IP_AES_AES_CONTROLR_GO (1 << 8)
-#define INCA_IP_AES_AES_CONTROLR_STP (1 << 7)
-#define INCA_IP_AES_AES_CONTROLR_IEN (1 << 6)
-#define INCA_IP_AES_AES_CONTROLR_BUS (1 << 5)
-#define INCA_IP_AES_AES_CONTROLR_SM (1 << 4)
-#define INCA_IP_AES_AES_CONTROLR_E_D (1 << 3)
-#define INCA_IP_AES_AES_CONTROLR_KV (1 << 2)
-#define INCA_IP_AES_AES_CONTROLR_K(value) (1 << value)
-
-
-/***********************************************************************/
-/* Module : I²C register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_IIC (0xB8000700)
-/***********************************************************************/
-
-
-/***I²C Port Input Select Register***/
-#define INCA_IP_IIC_IIC_PISEL ((volatile u32*)(INCA_IP_IIC+ 0x0004))
-#define INCA_IP_IIC_IIC_PISEL_SDAIS(value) (1 << value)
-
-#define INCA_IP_IIC_IIC_PISEL_SCLIS(value) (1 << value)
-
-
-/***I²C Clock Control Register***/
-#define INCA_IP_IIC_IIC_CLC ((volatile u32*)(INCA_IP_IIC+ 0x0000))
-#define INCA_IP_IIC_IIC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_IIC_IIC_CLC_DISS (1 << 1)
-#define INCA_IP_IIC_IIC_CLC_DISR (1 << 0)
-
-/***I²C System Control Register***/
-#define INCA_IP_IIC_IIC_SYSCON_0 ((volatile u32*)(INCA_IP_IIC+ 0x0010))
-#define INCA_IP_IIC_IIC_SYSCON_0_WMEN (1 << 31)
-#define INCA_IP_IIC_IIC_SYSCON_0_CI (value) (((( 1 << 2) - 1) & (value)) << 26)
-#define INCA_IP_IIC_IIC_SYSCON_0_STP (1 << 25)
-#define INCA_IP_IIC_IIC_SYSCON_0_IGE (1 << 24)
-#define INCA_IP_IIC_IIC_SYSCON_0_TRX (1 << 23)
-#define INCA_IP_IIC_IIC_SYSCON_0_INT (1 << 22)
-#define INCA_IP_IIC_IIC_SYSCON_0_ACKDIS (1 << 21)
-#define INCA_IP_IIC_IIC_SYSCON_0_BUM (1 << 20)
-#define INCA_IP_IIC_IIC_SYSCON_0_MOD (value) (((( 1 << 2) - 1) & (value)) << 18)
-#define INCA_IP_IIC_IIC_SYSCON_0_RSC (1 << 17)
-#define INCA_IP_IIC_IIC_SYSCON_0_M10 (1 << 16)
-#define INCA_IP_IIC_IIC_SYSCON_0_RMEN (1 << 15)
-#define INCA_IP_IIC_IIC_SYSCON_0_CO (value) (((( 1 << 3) - 1) & (value)) << 8)
-#define INCA_IP_IIC_IIC_SYSCON_0_IRQE (1 << 7)
-#define INCA_IP_IIC_IIC_SYSCON_0_IRQP (1 << 6)
-#define INCA_IP_IIC_IIC_SYSCON_0_IRQD (1 << 5)
-#define INCA_IP_IIC_IIC_SYSCON_0_BB (1 << 4)
-#define INCA_IP_IIC_IIC_SYSCON_0_LRB (1 << 3)
-#define INCA_IP_IIC_IIC_SYSCON_0_SLA (1 << 2)
-#define INCA_IP_IIC_IIC_SYSCON_0_AL (1 << 1)
-#define INCA_IP_IIC_IIC_SYSCON_0_ADR (1 << 0)
-
-/***I²C System Control Register***/
-#define INCA_IP_IIC_IIC_SYSCON_1 ((volatile u32*)(INCA_IP_IIC+ 0x0010))
-#define INCA_IP_IIC_IIC_SYSCON_1_RM (value) (((( 1 << 8) - 1) & (value)) << 24)
-#define INCA_IP_IIC_IIC_SYSCON_1_TRX (1 << 23)
-#define INCA_IP_IIC_IIC_SYSCON_1_INT (1 << 22)
-#define INCA_IP_IIC_IIC_SYSCON_1_ACKDIS (1 << 21)
-#define INCA_IP_IIC_IIC_SYSCON_1_BUM (1 << 20)
-#define INCA_IP_IIC_IIC_SYSCON_1_MOD (value) (((( 1 << 2) - 1) & (value)) << 18)
-#define INCA_IP_IIC_IIC_SYSCON_1_RSC (1 << 17)
-#define INCA_IP_IIC_IIC_SYSCON_1_M10 (1 << 16)
-#define INCA_IP_IIC_IIC_SYSCON_1_RMEN (1 << 15)
-#define INCA_IP_IIC_IIC_SYSCON_1_CO (value) (((( 1 << 3) - 1) & (value)) << 8)
-#define INCA_IP_IIC_IIC_SYSCON_1_IRQE (1 << 7)
-#define INCA_IP_IIC_IIC_SYSCON_1_IRQP (1 << 6)
-#define INCA_IP_IIC_IIC_SYSCON_1_IRQD (1 << 5)
-#define INCA_IP_IIC_IIC_SYSCON_1_BB (1 << 4)
-#define INCA_IP_IIC_IIC_SYSCON_1_LRB (1 << 3)
-#define INCA_IP_IIC_IIC_SYSCON_1_SLA (1 << 2)
-#define INCA_IP_IIC_IIC_SYSCON_1_AL (1 << 1)
-#define INCA_IP_IIC_IIC_SYSCON_1_ADR (1 << 0)
-
-/***I²C System Control Register***/
-#define INCA_IP_IIC_IIC_SYSCON_2 ((volatile u32*)(INCA_IP_IIC+ 0x0010))
-#define INCA_IP_IIC_IIC_SYSCON_2_WMEN (1 << 31)
-#define INCA_IP_IIC_IIC_SYSCON_2_CI (value) (((( 1 << 2) - 1) & (value)) << 26)
-#define INCA_IP_IIC_IIC_SYSCON_2_STP (1 << 25)
-#define INCA_IP_IIC_IIC_SYSCON_2_IGE (1 << 24)
-#define INCA_IP_IIC_IIC_SYSCON_2_TRX (1 << 23)
-#define INCA_IP_IIC_IIC_SYSCON_2_INT (1 << 22)
-#define INCA_IP_IIC_IIC_SYSCON_2_ACKDIS (1 << 21)
-#define INCA_IP_IIC_IIC_SYSCON_2_BUM (1 << 20)
-#define INCA_IP_IIC_IIC_SYSCON_2_MOD (value) (((( 1 << 2) - 1) & (value)) << 18)
-#define INCA_IP_IIC_IIC_SYSCON_2_RSC (1 << 17)
-#define INCA_IP_IIC_IIC_SYSCON_2_M10 (1 << 16)
-#define INCA_IP_IIC_IIC_SYSCON_2_WM (value) (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_IIC_IIC_SYSCON_2_IRQE (1 << 7)
-#define INCA_IP_IIC_IIC_SYSCON_2_IRQP (1 << 6)
-#define INCA_IP_IIC_IIC_SYSCON_2_IRQD (1 << 5)
-#define INCA_IP_IIC_IIC_SYSCON_2_BB (1 << 4)
-#define INCA_IP_IIC_IIC_SYSCON_2_LRB (1 << 3)
-#define INCA_IP_IIC_IIC_SYSCON_2_SLA (1 << 2)
-#define INCA_IP_IIC_IIC_SYSCON_2_AL (1 << 1)
-#define INCA_IP_IIC_IIC_SYSCON_2_ADR (1 << 0)
-
-/***I²C Write Hardware Modified System Control Register
-***/
-#define INCA_IP_IIC_IIC_WHBSYSCON ((volatile u32*)(INCA_IP_IIC+ 0x0020))
-#define INCA_IP_IIC_IIC_WHBSYSCON_CLRWMEN (1 << 31)
-#define INCA_IP_IIC_IIC_WHBSYSCON_SETWMEN (1 << 30)
-#define INCA_IP_IIC_IIC_WHBSYSCON_SETSTP (1 << 26)
-#define INCA_IP_IIC_IIC_WHBSYSCON_CLRSTP (1 << 25)
-#define INCA_IP_IIC_IIC_WHBSYSCON_SETTRX (1 << 24)
-#define INCA_IP_IIC_IIC_WHBSYSCON_CLRTRX (1 << 23)
-#define INCA_IP_IIC_IIC_WHBSYSCON_SETACKDIS (1 << 22)
-#define INCA_IP_IIC_IIC_WHBSYSCON_CLRACKDIS (1 << 21)
-#define INCA_IP_IIC_IIC_WHBSYSCON_SETBUM (1 << 20)
-#define INCA_IP_IIC_IIC_WHBSYSCON_CLRBUM (1 << 19)
-#define INCA_IP_IIC_IIC_WHBSYSCON_SETRSC (1 << 17)
-#define INCA_IP_IIC_IIC_WHBSYSCON_CLRRSC (1 << 16)
-#define INCA_IP_IIC_IIC_WHBSYSCON_SETRMEN (1 << 15)
-#define INCA_IP_IIC_IIC_WHBSYSCON_CLRRMEN (1 << 14)
-#define INCA_IP_IIC_IIC_WHBSYSCON_SETIRQE (1 << 10)
-#define INCA_IP_IIC_IIC_WHBSYSCON_SETIRQP (1 << 9)
-#define INCA_IP_IIC_IIC_WHBSYSCON_SETIRQD (1 << 8)
-#define INCA_IP_IIC_IIC_WHBSYSCON_CLRIRQE (1 << 7)
-#define INCA_IP_IIC_IIC_WHBSYSCON_CLRIRQP (1 << 6)
-#define INCA_IP_IIC_IIC_WHBSYSCON_CLRIRQD (1 << 5)
-#define INCA_IP_IIC_IIC_WHBSYSCON_SETAL (1 << 2)
-#define INCA_IP_IIC_IIC_WHBSYSCON_CLRAL (1 << 1)
-
-/***I²C Bus Control Register***/
-#define INCA_IP_IIC_IIC_BUSCON_0 ((volatile u32*)(INCA_IP_IIC+ 0x0014))
-#define INCA_IP_IIC_IIC_BUSCON_0_BRPMOD (1 << 31)
-#define INCA_IP_IIC_IIC_BUSCON_0_PREDIV (value) (((( 1 << 2) - 1) & (value)) << 29)
-#define INCA_IP_IIC_IIC_BUSCON_0_ICA9_0 (value) (((( 1 << 10) - 1) & (value)) << 16)
-#define INCA_IP_IIC_IIC_BUSCON_0_BRP (value) (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_IIC_IIC_BUSCON_0_SCLEN(value) (1 << value)
-
-#define INCA_IP_IIC_IIC_BUSCON_0_SDAEN(value) (1 << value)
-
-
-/***I²C Bus Control Register***/
-#define INCA_IP_IIC_IIC_BUSCON_1 ((volatile u32*)(INCA_IP_IIC+ 0x0014))
-#define INCA_IP_IIC_IIC_BUSCON_1_BRPMOD (1 << 31)
-#define INCA_IP_IIC_IIC_BUSCON_1_PREDIV (value) (((( 1 << 2) - 1) & (value)) << 29)
-#define INCA_IP_IIC_IIC_BUSCON_1_ICA7_1 (value) (((( 1 << 7) - 1) & (value)) << 17)
-#define INCA_IP_IIC_IIC_BUSCON_1_BRP (value) (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_IIC_IIC_BUSCON_1_SCLEN(value) (1 << value)
-
-#define INCA_IP_IIC_IIC_BUSCON_1_SDAEN(value) (1 << value)
-
-
-/***I²C Receive Transmit Buffer***/
-#define INCA_IP_IIC_IIC_RTB ((volatile u32*)(INCA_IP_IIC+ 0x0018))
-#define INCA_IP_IIC_IIC_RTB_RTB(value) (1 << value)
-
-
-/***********************************************************************/
-/* Module : FB register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_FB (0xBF880000)
-/***********************************************************************/
-
-
-/***FB Access Error Cause Register***/
-#define INCA_IP_FB_FB_ERRCAUSE ((volatile u32*)(INCA_IP_FB+ 0x0100))
-#define INCA_IP_FB_FB_ERRCAUSE_ERR (1 << 31)
-#define INCA_IP_FB_FB_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16)
-#define INCA_IP_FB_FB_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0)
-
-/***FB Access Error Address Register***/
-#define INCA_IP_FB_FB_ERRADDR ((volatile u32*)(INCA_IP_FB+ 0x0108))
-#define INCA_IP_FB_FB_ERRADDR_ADDR
-
-/***FB Configuration Register***/
-#define INCA_IP_FB_FB_CFG ((volatile u32*)(INCA_IP_FB+ 0x0800))
-#define INCA_IP_FB_FB_CFG_SVM (1 << 0)
-
-/***********************************************************************/
-/* Module : SRAM register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_SRAM (0xBF980000)
-/***********************************************************************/
-
-
-/***SRAM Size Register***/
-#define INCA_IP_SRAM_SRAM_SIZE ((volatile u32*)(INCA_IP_SRAM+ 0x0800))
-#define INCA_IP_SRAM_SRAM_SIZE_SIZE (value) (((( 1 << 23) - 1) & (value)) << 0)
-
-/***********************************************************************/
-/* Module : BIU register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_BIU (0xBFA80000)
-/***********************************************************************/
-
-
-/***BIU Identification Register***/
-#define INCA_IP_BIU_BIU_ID ((volatile u32*)(INCA_IP_BIU+ 0x0000))
-#define INCA_IP_BIU_BIU_ID_ARCH (1 << 16)
-#define INCA_IP_BIU_BIU_ID_ID (value) (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_BIU_BIU_ID_REV (value) (((( 1 << 8) - 1) & (value)) << 0)
-
-/***BIU Access Error Cause Register***/
-#define INCA_IP_BIU_BIU_ERRCAUSE ((volatile u32*)(INCA_IP_BIU+ 0x0100))
-#define INCA_IP_BIU_BIU_ERRCAUSE_ERR (1 << 31)
-#define INCA_IP_BIU_BIU_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16)
-#define INCA_IP_BIU_BIU_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0)
-
-/***BIU Access Error Address Register***/
-#define INCA_IP_BIU_BIU_ERRADDR ((volatile u32*)(INCA_IP_BIU+ 0x0108))
-#define INCA_IP_BIU_BIU_ERRADDR_ADDR
-
-/***********************************************************************/
-/* Module : ICU register address and bits */
-/***********************************************************************/
-
-#define INCA_IP_ICU (0xBF101000)
-/***********************************************************************/
-
-
-/***IM0 Interrupt Status Register***/
-#define INCA_IP_ICU_IM0_ISR ((volatile u32*)(INCA_IP_ICU+ 0x0000))
-#define INCA_IP_ICU_IM0_ISR_IR(value) (1 << value)
-
-
-/***IM1 Interrupt Status Register***/
-#define INCA_IP_ICU_IM1_ISR ((volatile u32*)(INCA_IP_ICU+ 0x0200))
-#define INCA_IP_ICU_IM1_ISR_IR(value) (1 << value)
-
-
-/***IM2 Interrupt Status Register***/
-#define INCA_IP_ICU_IM2_ISR ((volatile u32*)(INCA_IP_ICU+ 0x0400))
-#define INCA_IP_ICU_IM2_ISR_IR(value) (1 << value)
-
-
-/***IM0 Interrupt Enable Register***/
-#define INCA_IP_ICU_IM0_IER ((volatile u32*)(INCA_IP_ICU+ 0x0008))
-#define INCA_IP_ICU_IM0_IER_IR(value) (1 << value)
-
-
-/***IM1 Interrupt Enable Register***/
-#define INCA_IP_ICU_IM1_IER ((volatile u32*)(INCA_IP_ICU+ 0x0208))
-#define INCA_IP_ICU_IM1_IER_IR(value) (1 << value)
-
-
-/***IM2 Interrupt Enable Register***/
-#define INCA_IP_ICU_IM2_IER ((volatile u32*)(INCA_IP_ICU+ 0x0408))
-#define INCA_IP_ICU_IM2_IER_IR(value) (1 << value)
-
-
-/***IM0 Interrupt Output Status Register***/
-#define INCA_IP_ICU_IM0_IOSR ((volatile u32*)(INCA_IP_ICU+ 0x0010))
-#define INCA_IP_ICU_IM0_IOSR_IR(value) (1 << value)
-
-
-/***IM1 Interrupt Output Status Register***/
-#define INCA_IP_ICU_IM1_IOSR ((volatile u32*)(INCA_IP_ICU+ 0x0210))
-#define INCA_IP_ICU_IM1_IOSR_IR(value) (1 << value)
-
-
-/***IM2 Interrupt Output Status Register***/
-#define INCA_IP_ICU_IM2_IOSR ((volatile u32*)(INCA_IP_ICU+ 0x0410))
-#define INCA_IP_ICU_IM2_IOSR_IR(value) (1 << value)
-
-
-/***IM0 Interrupt Request Set Register***/
-#define INCA_IP_ICU_IM0_IRSR ((volatile u32*)(INCA_IP_ICU+ 0x0018))
-#define INCA_IP_ICU_IM0_IRSR_IR(value) (1 << value)
-
-
-/***IM1 Interrupt Request Set Register***/
-#define INCA_IP_ICU_IM1_IRSR ((volatile u32*)(INCA_IP_ICU+ 0x0218))
-#define INCA_IP_ICU_IM1_IRSR_IR(value) (1 << value)
-
-
-/***IM2 Interrupt Request Set Register***/
-#define INCA_IP_ICU_IM2_IRSR ((volatile u32*)(INCA_IP_ICU+ 0x0418))
-#define INCA_IP_ICU_IM2_IRSR_IR(value) (1 << value)
-
-
-/***External Interrupt Control Register***/
-#define INCA_IP_ICU_ICU_EICR ((volatile u32*)(INCA_IP_ICU+ 0x0B00))
-#define INCA_IP_ICU_ICU_EICR_EII5 (value) (((( 1 << 3) - 1) & (value)) << 20)
-#define INCA_IP_ICU_ICU_EICR_EII4 (value) (((( 1 << 3) - 1) & (value)) << 16)
-#define INCA_IP_ICU_ICU_EICR_EII3 (value) (((( 1 << 3) - 1) & (value)) << 12)
-#define INCA_IP_ICU_ICU_EICR_EII2 (value) (((( 1 << 3) - 1) & (value)) << 8)
-#define INCA_IP_ICU_ICU_EICR_EII1 (value) (((( 1 << 3) - 1) & (value)) << 4)
-#define INCA_IP_ICU_ICU_EICR_EII0 (value) (((( 1 << 3) - 1) & (value)) << 0)
+++ /dev/null
-/*
- * Copyright (c) 2005 Cisco Systems. All rights reserved.
- * Roland Dreier <rolandd@cisco.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#ifndef __4XX_PCIE_H
-#define __4XX_PCIE_H
-
-#include <ppc4xx.h>
-#include <pci.h>
-
-#define DCRN_SDR0_CFGADDR 0x00e
-#define DCRN_SDR0_CFGDATA 0x00f
-
-#if defined(CONFIG_440SPE)
-#define CONFIG_SYS_PCIE_NR_PORTS 3
-
-#define CONFIG_SYS_PCIE_ADDR_HIGH 0x0000000d
-
-#define DCRN_PCIE0_BASE 0x100
-#define DCRN_PCIE1_BASE 0x120
-#define DCRN_PCIE2_BASE 0x140
-
-#define PCIE0_SDR 0x300
-#define PCIE1_SDR 0x340
-#define PCIE2_SDR 0x370
-#endif
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define CONFIG_SYS_PCIE_NR_PORTS 2
-
-#define CONFIG_SYS_PCIE_ADDR_HIGH 0x0000000d
-
-#define DCRN_PCIE0_BASE 0x100
-#define DCRN_PCIE1_BASE 0x120
-
-#define PCIE0_SDR 0x300
-#define PCIE1_SDR 0x340
-#endif
-
-#if defined(CONFIG_405EX)
-#define CONFIG_SYS_PCIE_NR_PORTS 2
-
-#define CONFIG_SYS_PCIE_ADDR_HIGH 0x00000000
-
-#define DCRN_PCIE0_BASE 0x040
-#define DCRN_PCIE1_BASE 0x060
-
-#define PCIE0_SDR 0x400
-#define PCIE1_SDR 0x440
-#endif
-
-#define PCIE0 DCRN_PCIE0_BASE
-#define PCIE1 DCRN_PCIE1_BASE
-#define PCIE2 DCRN_PCIE2_BASE
-
-#define DCRN_PEGPL_CFGBAH(base) (base + 0x00)
-#define DCRN_PEGPL_CFGBAL(base) (base + 0x01)
-#define DCRN_PEGPL_CFGMSK(base) (base + 0x02)
-#define DCRN_PEGPL_MSGBAH(base) (base + 0x03)
-#define DCRN_PEGPL_MSGBAL(base) (base + 0x04)
-#define DCRN_PEGPL_MSGMSK(base) (base + 0x05)
-#define DCRN_PEGPL_OMR1BAH(base) (base + 0x06)
-#define DCRN_PEGPL_OMR1BAL(base) (base + 0x07)
-#define DCRN_PEGPL_OMR1MSKH(base) (base + 0x08)
-#define DCRN_PEGPL_OMR1MSKL(base) (base + 0x09)
-#define DCRN_PEGPL_REGBAH(base) (base + 0x12)
-#define DCRN_PEGPL_REGBAL(base) (base + 0x13)
-#define DCRN_PEGPL_REGMSK(base) (base + 0x14)
-#define DCRN_PEGPL_SPECIAL(base) (base + 0x15)
-#define DCRN_PEGPL_CFG(base) (base + 0x16)
-
-/*
- * System DCRs (SDRs)
- */
-#define PESDR0_PLLLCT1 0x03a0
-#define PESDR0_PLLLCT2 0x03a1
-#define PESDR0_PLLLCT3 0x03a2
-
-/* common regs, at for all 4xx with PCIe core */
-#define SDRN_PESDR_UTLSET1(n) (sdr_base(n) + 0x00)
-#define SDRN_PESDR_UTLSET2(n) (sdr_base(n) + 0x01)
-#define SDRN_PESDR_DLPSET(n) (sdr_base(n) + 0x02)
-#define SDRN_PESDR_LOOP(n) (sdr_base(n) + 0x03)
-#define SDRN_PESDR_RCSSET(n) (sdr_base(n) + 0x04)
-#define SDRN_PESDR_RCSSTS(n) (sdr_base(n) + 0x05)
-
-#if defined(CONFIG_440SPE)
-#define SDRN_PESDR_HSSL0SET1(n) (sdr_base(n) + 0x06)
-#define SDRN_PESDR_HSSL0SET2(n) (sdr_base(n) + 0x07)
-#define SDRN_PESDR_HSSL0STS(n) (sdr_base(n) + 0x08)
-#define SDRN_PESDR_HSSL1SET1(n) (sdr_base(n) + 0x09)
-#define SDRN_PESDR_HSSL1SET2(n) (sdr_base(n) + 0x0a)
-#define SDRN_PESDR_HSSL1STS(n) (sdr_base(n) + 0x0b)
-#define SDRN_PESDR_HSSL2SET1(n) (sdr_base(n) + 0x0c)
-#define SDRN_PESDR_HSSL2SET2(n) (sdr_base(n) + 0x0d)
-#define SDRN_PESDR_HSSL2STS(n) (sdr_base(n) + 0x0e)
-#define SDRN_PESDR_HSSL3SET1(n) (sdr_base(n) + 0x0f)
-#define SDRN_PESDR_HSSL3SET2(n) (sdr_base(n) + 0x10)
-#define SDRN_PESDR_HSSL3STS(n) (sdr_base(n) + 0x11)
-
-#define PESDR0_UTLSET1 0x0300
-#define PESDR0_UTLSET2 0x0301
-#define PESDR0_DLPSET 0x0302
-#define PESDR0_LOOP 0x0303
-#define PESDR0_RCSSET 0x0304
-#define PESDR0_RCSSTS 0x0305
-#define PESDR0_HSSL0SET1 0x0306
-#define PESDR0_HSSL0SET2 0x0307
-#define PESDR0_HSSL0STS 0x0308
-#define PESDR0_HSSL1SET1 0x0309
-#define PESDR0_HSSL1SET2 0x030a
-#define PESDR0_HSSL1STS 0x030b
-#define PESDR0_HSSL2SET1 0x030c
-#define PESDR0_HSSL2SET2 0x030d
-#define PESDR0_HSSL2STS 0x030e
-#define PESDR0_HSSL3SET1 0x030f
-#define PESDR0_HSSL3SET2 0x0310
-#define PESDR0_HSSL3STS 0x0311
-#define PESDR0_HSSL4SET1 0x0312
-#define PESDR0_HSSL4SET2 0x0313
-#define PESDR0_HSSL4STS 0x0314
-#define PESDR0_HSSL5SET1 0x0315
-#define PESDR0_HSSL5SET2 0x0316
-#define PESDR0_HSSL5STS 0x0317
-#define PESDR0_HSSL6SET1 0x0318
-#define PESDR0_HSSL6SET2 0x0319
-#define PESDR0_HSSL6STS 0x031a
-#define PESDR0_HSSL7SET1 0x031b
-#define PESDR0_HSSL7SET2 0x031c
-#define PESDR0_HSSL7STS 0x031d
-#define PESDR0_HSSCTLSET 0x031e
-#define PESDR0_LANE_ABCD 0x031f
-#define PESDR0_LANE_EFGH 0x0320
-
-#define PESDR1_UTLSET1 0x0340
-#define PESDR1_UTLSET2 0x0341
-#define PESDR1_DLPSET 0x0342
-#define PESDR1_LOOP 0x0343
-#define PESDR1_RCSSET 0x0344
-#define PESDR1_RCSSTS 0x0345
-#define PESDR1_HSSL0SET1 0x0346
-#define PESDR1_HSSL0SET2 0x0347
-#define PESDR1_HSSL0STS 0x0348
-#define PESDR1_HSSL1SET1 0x0349
-#define PESDR1_HSSL1SET2 0x034a
-#define PESDR1_HSSL1STS 0x034b
-#define PESDR1_HSSL2SET1 0x034c
-#define PESDR1_HSSL2SET2 0x034d
-#define PESDR1_HSSL2STS 0x034e
-#define PESDR1_HSSL3SET1 0x034f
-#define PESDR1_HSSL3SET2 0x0350
-#define PESDR1_HSSL3STS 0x0351
-#define PESDR1_HSSCTLSET 0x0352
-#define PESDR1_LANE_ABCD 0x0353
-
-#define PESDR2_UTLSET1 0x0370
-#define PESDR2_UTLSET2 0x0371
-#define PESDR2_DLPSET 0x0372
-#define PESDR2_LOOP 0x0373
-#define PESDR2_RCSSET 0x0374
-#define PESDR2_RCSSTS 0x0375
-#define PESDR2_HSSL0SET1 0x0376
-#define PESDR2_HSSL0SET2 0x0377
-#define PESDR2_HSSL0STS 0x0378
-#define PESDR2_HSSL1SET1 0x0379
-#define PESDR2_HSSL1SET2 0x037a
-#define PESDR2_HSSL1STS 0x037b
-#define PESDR2_HSSL2SET1 0x037c
-#define PESDR2_HSSL2SET2 0x037d
-#define PESDR2_HSSL2STS 0x037e
-#define PESDR2_HSSL3SET1 0x037f
-#define PESDR2_HSSL3SET2 0x0380
-#define PESDR2_HSSL3STS 0x0381
-#define PESDR2_HSSCTLSET 0x0382
-#define PESDR2_LANE_ABCD 0x0383
-
-#elif defined(CONFIG_405EX)
-
-#define SDRN_PESDR_PHYSET1(n) (sdr_base(n) + 0x06)
-#define SDRN_PESDR_PHYSET2(n) (sdr_base(n) + 0x07)
-#define SDRN_PESDR_BIST(n) (sdr_base(n) + 0x08)
-#define SDRN_PESDR_LPB(n) (sdr_base(n) + 0x0b)
-#define SDRN_PESDR_PHYSTA(n) (sdr_base(n) + 0x0c)
-
-#define PESDR0_UTLSET1 0x0400
-#define PESDR0_UTLSET2 0x0401
-#define PESDR0_DLPSET 0x0402
-#define PESDR0_LOOP 0x0403
-#define PESDR0_RCSSET 0x0404
-#define PESDR0_RCSSTS 0x0405
-#define PESDR0_PHYSET1 0x0406
-#define PESDR0_PHYSET2 0x0407
-#define PESDR0_BIST 0x0408
-#define PESDR0_LPB 0x040B
-#define PESDR0_PHYSTA 0x040C
-
-#define PESDR1_UTLSET1 0x0440
-#define PESDR1_UTLSET2 0x0441
-#define PESDR1_DLPSET 0x0442
-#define PESDR1_LOOP 0x0443
-#define PESDR1_RCSSET 0x0444
-#define PESDR1_RCSSTS 0x0445
-#define PESDR1_PHYSET1 0x0446
-#define PESDR1_PHYSET2 0x0447
-#define PESDR1_BIST 0x0448
-#define PESDR1_LPB 0x044B
-#define PESDR1_PHYSTA 0x044C
-
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
-
-#define PESDR0_L0BIST 0x0308 /* PE0 L0 built in self test */
-#define PESDR0_L0BISTSTS 0x0309 /* PE0 L0 built in self test status */
-#define PESDR0_L0CDRCTL 0x030A /* PE0 L0 CDR control */
-#define PESDR0_L0DRV 0x030B /* PE0 L0 drive */
-#define PESDR0_L0REC 0x030C /* PE0 L0 receiver */
-#define PESDR0_L0LPB 0x030D /* PE0 L0 loopback */
-#define PESDR0_L0CLK 0x030E /* PE0 L0 clocking */
-#define PESDR0_PHY_CTL_RST 0x030F /* PE0 PHY control reset */
-#define PESDR0_RSTSTA 0x0310 /* PE0 reset status */
-#define PESDR0_OBS 0x0311 /* PE0 observation register */
-#define PESDR0_L0ERRC 0x0320 /* PE0 L0 error counter */
-
-#define PESDR1_L0BIST 0x0348 /* PE1 L0 built in self test */
-#define PESDR1_L1BIST 0x0349 /* PE1 L1 built in self test */
-#define PESDR1_L2BIST 0x034A /* PE1 L2 built in self test */
-#define PESDR1_L3BIST 0x034B /* PE1 L3 built in self test */
-#define PESDR1_L0BISTSTS 0x034C /* PE1 L0 built in self test status */
-#define PESDR1_L1BISTSTS 0x034D /* PE1 L1 built in self test status */
-#define PESDR1_L2BISTSTS 0x034E /* PE1 L2 built in self test status */
-#define PESDR1_L3BISTSTS 0x034F /* PE1 L3 built in self test status */
-#define PESDR1_L0CDRCTL 0x0350 /* PE1 L0 CDR control */
-#define PESDR1_L1CDRCTL 0x0351 /* PE1 L1 CDR control */
-#define PESDR1_L2CDRCTL 0x0352 /* PE1 L2 CDR control */
-#define PESDR1_L3CDRCTL 0x0353 /* PE1 L3 CDR control */
-#define PESDR1_L0DRV 0x0354 /* PE1 L0 drive */
-#define PESDR1_L1DRV 0x0355 /* PE1 L1 drive */
-#define PESDR1_L2DRV 0x0356 /* PE1 L2 drive */
-#define PESDR1_L3DRV 0x0357 /* PE1 L3 drive */
-#define PESDR1_L0REC 0x0358 /* PE1 L0 receiver */
-#define PESDR1_L1REC 0x0359 /* PE1 L1 receiver */
-#define PESDR1_L2REC 0x035A /* PE1 L2 receiver */
-#define PESDR1_L3REC 0x035B /* PE1 L3 receiver */
-#define PESDR1_L0LPB 0x035C /* PE1 L0 loopback */
-#define PESDR1_L1LPB 0x035D /* PE1 L1 loopback */
-#define PESDR1_L2LPB 0x035E /* PE1 L2 loopback */
-#define PESDR1_L3LPB 0x035F /* PE1 L3 loopback */
-#define PESDR1_L0CLK 0x0360 /* PE1 L0 clocking */
-#define PESDR1_L1CLK 0x0361 /* PE1 L1 clocking */
-#define PESDR1_L2CLK 0x0362 /* PE1 L2 clocking */
-#define PESDR1_L3CLK 0x0363 /* PE1 L3 clocking */
-#define PESDR1_PHY_CTL_RST 0x0364 /* PE1 PHY control reset */
-#define PESDR1_RSTSTA 0x0365 /* PE1 reset status */
-#define PESDR1_OBS 0x0366 /* PE1 observation register */
-#define PESDR1_L0ERRC 0x0368 /* PE1 L0 error counter */
-#define PESDR1_L1ERRC 0x0369 /* PE1 L1 error counter */
-#define PESDR1_L2ERRC 0x036A /* PE1 L2 error counter */
-#define PESDR1_L3ERRC 0x036B /* PE1 L3 error counter */
-#define PESDR0_IHS1 0x036C /* PE interrupt handler interfact setting 1 */
-#define PESDR0_IHS2 0x036D /* PE interrupt handler interfact setting 2 */
-
-#endif
-
-/* SDR Bit Mappings */
-#define PESDRx_RCSSET_HLDPLB 0x10000000
-#define PESDRx_RCSSET_RSTGU 0x01000000
-#define PESDRx_RCSSET_RDY 0x00100000
-#define PESDRx_RCSSET_RSTDL 0x00010000
-#define PESDRx_RCSSET_RSTPYN 0x00001000
-
-#define PESDRx_RCSSTS_PLBIDL 0x10000000
-#define PESDRx_RCSSTS_HRSTRQ 0x01000000
-#define PESDRx_RCSSTS_PGRST 0x00100000
-#define PESDRx_RCSSTS_VC0ACT 0x00010000
-#define PESDRx_RCSSTS_BMEN 0x00000100
-
-/*
- * UTL register offsets
- */
-#define PEUTL_PBCTL 0x00
-#define PEUTL_PBBSZ 0x20
-#define PEUTL_OPDBSZ 0x68
-#define PEUTL_IPHBSZ 0x70
-#define PEUTL_IPDBSZ 0x78
-#define PEUTL_OUTTR 0x90
-#define PEUTL_INTR 0x98
-#define PEUTL_PCTL 0xa0
-#define PEUTL_RCSTA 0xb0
-#define PEUTL_RCIRQEN 0xb8
-
-/*
- * Config space register offsets
- */
-#define PECFG_BAR0LMPA 0x210
-#define PECFG_BAR0HMPA 0x214
-#define PECFG_BAR1MPA 0x218
-#define PECFG_BAR2LMPA 0x220
-#define PECFG_BAR2HMPA 0x224
-
-#define PECFG_PIMEN 0x33c
-#define PECFG_PIM0LAL 0x340
-#define PECFG_PIM0LAH 0x344
-#define PECFG_PIM1LAL 0x348
-#define PECFG_PIM1LAH 0x34c
-#define PECFG_PIM01SAL 0x350
-#define PECFG_PIM01SAH 0x354
-
-#define PECFG_POM0LAL 0x380
-#define PECFG_POM0LAH 0x384
-
-#define SDR_READ(offset) ({\
- mtdcr(DCRN_SDR0_CFGADDR, offset); \
- mfdcr(DCRN_SDR0_CFGDATA);})
-
-#define SDR_WRITE(offset, data) ({\
- mtdcr(DCRN_SDR0_CFGADDR, offset); \
- mtdcr(DCRN_SDR0_CFGDATA,data);})
-
-#define GPL_DMER_MASK_DISA 0x02000000
-
-#define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
-#define U64_TO_U32_HIGH(val) ((u32)((val) >> 32))
-
-/*
- * Prototypes
- */
-int ppc4xx_init_pcie(void);
-int ppc4xx_init_pcie_rootport(int port);
-int ppc4xx_init_pcie_endport(int port);
-void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port);
-int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port);
-int pcie_hose_scan(struct pci_controller *hose, int bus);
-
-/*
- * Function to determine root port or endport from env variable.
- */
-static inline int is_end_point(int port)
-{
- char s[10], *tk;
- char *pcie_mode = getenv("pcie_mode");
-
- if (pcie_mode == NULL)
- return 0;
-
- strcpy(s, pcie_mode);
- tk = strtok(s, ":");
-
- switch (port) {
- case 0:
- if (tk != NULL) {
- if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
- return 1;
- else
- return 0;
- }
- else
- return 0;
-
- case 1:
- tk = strtok(NULL, ":");
- if (tk != NULL) {
- if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
- return 1;
- else
- return 0;
- }
- else
- return 0;
-
- case 2:
- tk = strtok(NULL, ":");
- if (tk != NULL)
- tk = strtok(NULL, ":");
- if (tk != NULL) {
- if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
- return 1;
- else
- return 0;
- }
- else
- return 0;
- }
-
- return 0;
-}
-
-static inline void mdelay(int n)
-{
- u32 ms = n;
-
- while (ms--)
- udelay(1000);
-}
-
-#if defined(PCIE0_SDR)
-static inline u32 sdr_base(int port)
-{
- switch (port) {
- default: /* to satisfy compiler */
- case 0:
- return PCIE0_SDR;
- case 1:
- return PCIE1_SDR;
-#if CONFIG_SYS_PCIE_NR_PORTS > 2
- case 2:
- return PCIE2_SDR;
-#endif
- }
-}
-#endif /* defined(PCIE0_SDR) */
-
-#endif /* __4XX_PCIE_H */
+++ /dev/null
-/* $Id$ */
-
-#ifndef _BEDBUG_H
-#define _BEDBUG_H
-
-#ifndef NULL
-#define NULL 0
-#endif
-
-#define _USE_PROTOTYPES
-
-#ifndef isblank
-#define isblank(c) isspace((int)(c))
-#endif
-
-#ifndef __P
-#if defined(_USE_PROTOTYPES) && (defined(__STDC__) || defined(__cplusplus))
-#define __P(protos) protos /* full-blown ANSI C */
-#else
-#define __P(protos) () /* traditional C preprocessor */
-#endif
-#endif
-
-#define assert( condition ) if( (condition) ) _exit(0)
-
-#endif /* _BEDBUG_H */
-
-
-/*
- * Copyright (c) 2001 William L. Pitts
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are freely
- * permitted provided that the above copyright notice and this
- * paragraph and the following disclaimer are duplicated in all
- * such forms.
- *
- * This software is provided "AS IS" and without any express or
- * implied warranties, including, without limitation, the implied
- * warranties of merchantability and fitness for a particular
- * purpose.
- */
+++ /dev/null
-/* $Id$ */
-
-#ifndef _PPC_H
-#define _PPC_H
-
-/*======================================================================
- *
- * OPERANDS
- *
- *======================================================================*/
-
-enum OP_FIELD {
- O_AA = 1, O_BD, O_BI, O_BO, O_crbD, O_crbA, O_crbB, O_CRM, O_d, O_frC, O_frD,
- O_frS, O_IMM, O_LI, O_LK, O_MB, O_ME, O_NB, O_OE, O_rA, O_rB, O_Rc, O_rD,
- O_rS, O_SH, O_SIMM, O_SR, O_TO, O_UIMM, O_crfD, O_crfS, O_L, O_spr, O_tbr,
- O_cr2 };
-
-struct operand {
- enum OP_FIELD field; /* The operand identifier from the
- enum above */
-
- char * name; /* Symbolic name of this operand */
-
- unsigned int bits; /* The number of bits used by this
- operand */
-
- unsigned int shift; /* How far to the right the operand
- should be shifted so that it is
- aligned at the beginning of the
- word */
-
- unsigned int hint; /* A bitwise-inclusive-OR of the
- values shown below. These are used
- tell the disassembler how to print
- this operand */
-};
-
-/* Values for operand hint */
-#define OH_SILENT 0x01 /* dont print this operand */
-#define OH_ADDR 0x02 /* this operand is an address */
-#define OH_REG 0x04 /* this operand is a register */
-#define OH_SPR 0x08 /* this operand is an SPR */
-#define OH_TBR 0x10 /* this operand is a TBR */
-#define OH_OFFSET 0x20 /* this operand is an offset */
-#define OH_LITERAL 0x40 /* a literal string */
-
-\f
-/*======================================================================
- *
- * OPCODES
- *
- *======================================================================*/
-
-/* From the MPCxxx instruction set documentation, all instructions are
- * 32 bits long and word aligned. Bits 0-5 always specify the primary
- * opcode. Many instructions also have an extended opcode.
- */
-
-#define GET_OPCD(i) (((unsigned long)(i) >> 26) & 0x3f)
-#define MAKE_OPCODE(i) ((((unsigned long)(i)) & 0x3f) << 26)
-
-/* The MPC860 User's Manual, Appendix D.4 contains the definitions of the
- * instruction forms
- */
-
-
-/*-------------------------------------------------
- * I-Form Instructions:
- * bX
- *-------------------------------------------------
- * OPCD | LI |AA|LK
- *-------------------------------------------------*/
-
-#define I_OPCODE(i,aa,lk) (MAKE_OPCODE(i) | (((aa) & 0x1) << 1) | ((lk) & 0x1))
-#define I_MASK I_OPCODE(0x3f,0x1,0x1)
-
-
-/*-------------------------------------------------
- * B-Form Instructions:
- * bcX
- *-------------------------------------------------
- * OPCD | BO | BI | BD |AA|LK
- *-------------------------------------------------*/
-
-#define B_OPCODE(i,aa,lk) (MAKE_OPCODE(i) | (((aa) & 0x1) << 1) | ((lk) & 0x1))
-#define B_MASK B_OPCODE(0x3f,0x1,0x1)
-
-
-/*-------------------------------------------------
- * SC-Form Instructions:
- * sc
- *-------------------------------------------------
- * OPCD | 00000 | 00000 | 00000000000000 |1|0
- *-------------------------------------------------*/
-
-#define SC_OPCODE(i) (MAKE_OPCODE(i) | 0x2)
-#define SC_MASK SC_OPCODE(0x3f)
-
-
-/*-------------------------------------------------
- * D-Form Instructions:
- * addi addic addic. addis andi. andis. cmpi cmpli
- * lbz lbzu lha lhau lhz lhzu lmw lwz lwzu mulli
- * ori oris stb stbu sth sthu stmw stw stwu subfic
- * twi xori xoris
- *-------------------------------------------------
- * OPCD | D | A | d
- * OPCD | D | A | SIMM
- * OPCD | S | A | d
- * OPCD | S | A | UIMM
- * OPCD |crfD|0|L| A | SIMM
- * OPCD |crfD|0|L| A | UIMM
- * OPCD | TO | A | SIMM
- *-------------------------------------------------*/
-
-#define D_OPCODE(i) MAKE_OPCODE(i)
-#define D_MASK MAKE_OPCODE(0x3f)
-
-
-/*-------------------------------------------------
- * DS-Form Instructions:
- * (none supported by MPC860)
- *-------------------------------------------------
- * OPCD | D | A | ds |XO
- * OPCD | S | A | ds |XO
- *-------------------------------------------------*/
-
-#define DS_OPCODE(i,xo) (MAKE_OPCODE(i) | ((xo) & 0x3))
-#define DS_MASK DS_OPCODE(0x3f,0x1)
-
-
-/*---------------------------------------------------
- * X-Form Instructions:
- * andX andcX cmp cmpl cntlzwX dcbf dcbi dcbst dcbt
- * dcbtst dcbz eciwx ecowx eieio eqvX extsbX extshX
- * icbi lbzux lbxz lhaux lhax lhbrx lhzux lhxz lswi
- * lswx lwarx lwbrx lwzux lwxz mcrfs mcrxr mfcr
- * mfmsr mfsr mfsrin mtmsr mtsr mtsrin nandX norX
- * orX orcX slwX srawX srawiX srwX stbux stbx
- * sthbrx sthuxsthx stswi stswx stwbrx stwcx. stwux
- * stwx sync tlbie tlbld tlbli tlbsync tw xorX
- *---------------------------------------------------
- * OPCD | D | A | B | XO |0
- * OPCD | D | A | NB | XO |0
- * OPCD | D | 00000 | B | XO |0
- * OPCD | D | 00000 | 00000 | XO |0
- * OPCD | D |0| SR | 00000 | XO |0
- * OPCD | S | A | B | XO |Rc
- * OPCD | S | A | B | XO |1
- * OPCD | S | A | B | XO |0
- * OPCD | S | A | NB | XO |0
- * OPCD | S | A | 00000 | XO |Rc
- * OPCD | S | 00000 | B | XO |0
- * OPCD | S | 00000 | 00000 | XO |0
- * OPCD | S |0| SR | 00000 | XO |0
- * OPCD | S | A | SH | XO |Rc
- * OPCD |crfD|0|L| A | SH | XO |0
- * OPCD |crfD |00| A | B | XO |0
- * OPCD |crfD |00|crfS |00| 00000 | XO |0
- * OPCD |crfD |00| 00000 | 00000 | XO |0
- * OPCD |crfD |00| 00000 | IMM |0| XO |Rc
- * OPCD | TO | A | B | XO |0
- * OPCD | D | 00000 | B | XO |Rc
- * OPCD | D | 00000 | 00000 | XO |Rc
- * OPCD | crbD | 00000 | 00000 | XO |Rc
- * OPCD | 00000 | A | B | XO |0
- * OPCD | 00000 | 00000 | B | XO |0
- * OPCD | 00000 | 00000 | 00000 | XO |0
- *---------------------------------------------------*/
-
-#define X_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
- ((rc) & 0x1))
-#define X_MASK X_OPCODE(0x3f,0x3ff,0x1)
-
-
-/*---------------------------------------------------
- * XL-Form Instructions:
- * bcctrX bclrX crand crandc creqv crnand crnor cror
- * croc crxorisync mcrf rfi
- *---------------------------------------------------
- * OPCD | BO | BI | 00000 | XO |LK
- * OPCD | crbD | crbA | crbB | XO |0
- * OPCD |crfD |00|crfS |00| 00000 | XO |0
- * OPCD | 00000 | 00000 | 00000 | XO |0
- *---------------------------------------------------*/
-
-#define XL_OPCODE(i,xo,lk) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
- ((lk) & 0x1))
-#define XL_MASK XL_OPCODE(0x3f,0x3ff,0x1)
-
-
-/*---------------------------------------------------
- * XFX-Form Instructions:
- * mfspr mftb mtcrf mtspr
- *---------------------------------------------------
- * OPCD | D | spr | XO |0
- * OPCD | D |0| CRM |0| XO |0
- * OPCD | S | spr | XO |0
- * OPCD | D | tbr | XO |0
- *---------------------------------------------------*/
-
-#define XFX_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
- ((rc) & 0x1))
-#define XFX_MASK XFX_OPCODE(0x3f,0x3ff,0x1)
-
-
-/*---------------------------------------------------
- * XFL-Form Instructions:
- * (none supported by MPC860)
- *---------------------------------------------------
- * OPCD |0| FM |0| B | XO |0
- *---------------------------------------------------*/
-
-#define XFL_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
- ((rc) & 0x1))
-#define XFL_MASK XFL_OPCODE(0x3f,0x3ff,0x1)
-
-
-/*---------------------------------------------------
- * XS-Form Instructions:
- * (none supported by MPC860)
- *---------------------------------------------------
- * OPCD | S | A | sh | XO |sh|LK
- *---------------------------------------------------*/
-
-#define XS_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x1ff) << 2) | \
- ((rc) & 0x1))
-#define XS_MASK XS_OPCODE(0x3f,0x1ff,0x1)
-
-
-/*---------------------------------------------------
- * XO-Form Instructions:
- * addX addcXaddeX addmeX addzeX divwX divwuX mulhwX
- * mulhwuX mullwX negX subfX subfcX subfeX subfmeX
- * subfzeX
- *---------------------------------------------------
- * OPCD | D | A | B |OE| XO |Rc
- * OPCD | D | A | B |0 | XO |Rc
- * OPCD | D | A | 00000 |OE| XO |Rc
- *---------------------------------------------------*/
-
-#define XO_OPCODE(i,xo,oe,rc) (MAKE_OPCODE(i) | (((oe) & 0x1) << 10) | \
- (((xo) & 0x1ff) << 1) | ((rc) & 0x1))
-#define XO_MASK XO_OPCODE(0x3f,0x1ff,0x1,0x1)
-
-
-/*---------------------------------------------------
- * A-Form Instructions:
- * (none supported by MPC860)
- *---------------------------------------------------
- * OPCD | D | A | B |00000| XO |Rc
- * OPCD | D | A | B | C | XO |Rc
- * OPCD | D | A | 00000 | C | XO |Rc
- * OPCD | D | 00000 | B |00000| XO |Rc
- *---------------------------------------------------*/
-
-#define A_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x1f) << 1) | \
- ((rc) & 0x1))
-#define A_MASK A_OPCODE(0x3f,0x1f,0x1)
-
-
-/*---------------------------------------------------
- * M-Form Instructions:
- * rlwimiX rlwinmX rlwnmX
- *---------------------------------------------------
- * OPCD | S | A | SH | MB | ME |Rc
- * OPCD | S | A | B | MB | ME |Rc
- *---------------------------------------------------*/
-
-#define M_OPCODE(i,rc) (MAKE_OPCODE(i) | ((rc) & 0x1))
-#define M_MASK M_OPCODE(0x3f,0x1)
-
-
-/*---------------------------------------------------
- * MD-Form Instructions:
- * (none supported by MPC860)
- *---------------------------------------------------
- * OPCD | S | A | sh | mb | XO |sh|Rc
- * OPCD | S | A | sh | me | XO |sh|Rc
- *---------------------------------------------------*/
-
-#define MD_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x7) << 2) | \
- ((rc) & 0x1))
-#define MD_MASK MD_OPCODE(0x3f,0x7,0x1)
-
-
-/*---------------------------------------------------
- * MDS-Form Instructions:
- * (none supported by MPC860)
- *---------------------------------------------------
- * OPCD | S | A | B | mb | XO |Rc
- * OPCD | S | A | B | me | XO |Rc
- *---------------------------------------------------*/
-
-#define MDS_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0xf) << 1) | \
- ((rc) & 0x1))
-#define MDS_MASK MDS_OPCODE(0x3f,0xf,0x1)
-
-#ifndef FALSE
-#define FALSE 0
-#define TRUE (!FALSE)
-#endif
-
-#define INSTRUCTION( memaddr ) ntohl(*(unsigned long *)(memaddr))
-
-#define MAX_OPERANDS 8
-
-struct ppc_ctx;
-
-struct opcode {
- unsigned long opcode; /* The complete opcode as produced by
- one of the XXX_OPCODE macros above */
-
- unsigned long mask; /* The mask to use on an instruction
- before comparing with the opcode
- field to see if it matches */
-
- enum OP_FIELD fields[MAX_OPERANDS];
- /* An array defining the operands for
- this opcode. The values of the
- array are the operand identifiers */
-
- int (*hfunc)(struct ppc_ctx *);
- /* Address of a function to handle the given
- mnemonic */
-
- char * name; /* The symbolic name of this opcode */
-
- unsigned int hint; /* A bitwise-inclusive-OR of the
- values shown below. These are used
- tell the disassembler how to print
- some operands for this opcode */
-};
-
-/* values for opcode hints */
-#define H_RELATIVE 0x1 /* The address operand is relative */
-#define H_IMM_HIGH 0x2 /* [U|S]IMM field shifted high */
-#define H_RA0_IS_0 0x4 /* If rA = 0 then treat as literal 0 */
-
-struct ppc_ctx {
- struct opcode * op;
- unsigned long instr;
- unsigned int flags;
- int datalen;
- char data[ 256 ];
- char radix_fmt[ 8 ];
- unsigned char * virtual;
-};
-
-
-/*======================================================================
- *
- * FUNCTIONS
- *
- *======================================================================*/
-
-/* Values for flags as passed to various ppc routines */
-#define F_RADOCTAL 0x1 /* output radix = unsigned octal */
-#define F_RADUDECIMAL 0x2 /* output radix = unsigned decimal */
-#define F_RADSDECIMAL 0x4 /* output radix = signed decimal */
-#define F_RADHEX 0x8 /* output radix = unsigned hex */
-#define F_SIMPLE 0x10 /* use simplified mnemonics */
-#define F_SYMBOL 0x20 /* use symbol lookups for addresses */
-#define F_INSTR 0x40 /* output the raw instruction */
-#define F_LOCALMEM 0x80 /* retrieve opcodes from local memory
- rather than from the HMI */
-#define F_LINENO 0x100 /* show line number info if available */
-#define F_VALIDONLY 0x200 /* cache: valid entries only */
-
-/* Values for assembler error codes */
-#define E_ASM_BAD_OPCODE 1
-#define E_ASM_NUM_OPERANDS 2
-#define E_ASM_BAD_REGISTER 3
-#define E_ASM_BAD_SPR 4
-#define E_ASM_BAD_TBR 5
-
-extern int disppc __P((unsigned char *,unsigned char *,int,
- int (*)(const char *), unsigned long));
-extern int print_source_line __P((char *,char *,int,
- int (*pfunc)(const char *)));
-extern int find_next_address __P((unsigned char *,int,struct pt_regs *));
-extern int handle_bc __P((struct ppc_ctx *));
-extern unsigned long asmppc __P((unsigned long,char*,int*));
-extern char *asm_error_str __P((int));
-
-/*======================================================================
- *
- * GLOBAL VARIABLES
- *
- *======================================================================*/
-
-extern struct operand operands[];
-extern const unsigned int n_operands;
-extern struct opcode opcodes[];
-extern const unsigned int n_opcodes;
-
-#endif /* _PPC_H */
-
-
-/*
- * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are freely
- * permitted provided that the above copyright notice and this
- * paragraph and the following disclaimer are duplicated in all
- * such forms.
- *
- * This software is provided "AS IS" and without any express or
- * implied warranties, including, without limitation, the implied
- * warranties of merchantability and fitness for a particular
- * purpose.
- */
+++ /dev/null
-/* $Id$ */
-
-#ifndef _REGS_H
-#define _REGS_H
-
-/* Special Purpose Registers */
-
-#define SPR_CR -1
-#define SPR_MSR -2
-
-#define SPR_XER 1
-#define SPR_LR 8
-#define SPR_CTR 9
-#define SPR_DSISR 18
-#define SPR_DAR 19
-#define SPR_DEC 22
-#define SPR_SRR0 26
-#define SPR_SRR1 27
-#define SPR_EIE 80
-#define SPR_EID 81
-#define SPR_CMPA 144
-#define SPR_CMPB 145
-#define SPR_CMPC 146
-#define SPR_CMPD 147
-#define SPR_ICR 148
-#define SPR_DER 149
-#define SPR_COUNTA 150
-#define SPR_COUNTB 151
-#define SPR_CMPE 152
-#define SPR_CMPF 153
-#define SPR_CMPG 154
-#define SPR_CMPH 155
-#define SPR_LCTRL1 156
-#define SPR_LCTRL2 157
-#define SPR_ICTRL 158
-#define SPR_BAR 159
-#define SPR_USPRG0 256
-#define SPR_SPRG4_RO 260
-#define SPR_SPRG5_RO 261
-#define SPR_SPRG6_RO 262
-#define SPR_SPRG7_RO 263
-#define SPR_SPRG0 272
-#define SPR_SPRG1 273
-#define SPR_SPRG2 274
-#define SPR_SPRG3 275
-#define SPR_SPRG4 276
-#define SPR_SPRG5 277
-#define SPR_SPRG6 278
-#define SPR_SPRG7 279
-#define SPR_EAR 282 /* MPC603e core */
-#define SPR_TBL 284
-#define SPR_TBU 285
-#define SPR_PVR 287
-#define SPR_IC_CST 560
-#define SPR_IC_ADR 561
-#define SPR_IC_DAT 562
-#define SPR_DC_CST 568
-#define SPR_DC_ADR 569
-#define SPR_DC_DAT 570
-#define SPR_DPDR 630
-#define SPR_IMMR 638
-#define SPR_MI_CTR 784
-#define SPR_MI_AP 786
-#define SPR_MI_EPN 787
-#define SPR_MI_TWC 789
-#define SPR_MI_RPN 790
-#define SPR_MD_CTR 792
-#define SPR_M_CASID 793
-#define SPR_MD_AP 794
-#define SPR_MD_EPN 795
-#define SPR_M_TWB 796
-#define SPR_MD_TWC 797
-#define SPR_MD_RPN 798
-#define SPR_M_TW 799
-#define SPR_MI_DBCAM 816
-#define SPR_MI_DBRAM0 817
-#define SPR_MI_DBRAM1 818
-#define SPR_MD_DBCAM 824
-#define SPR_MD_DBRAM0 825
-#define SPR_MD_DBRAM1 826
-#define SPR_ZPR 944
-#define SPR_PID 945
-#define SPR_CCR0 947
-#define SPR_IAC3 948
-#define SPR_IAC4 949
-#define SPR_DVC1 950
-#define SPR_DVC2 951
-#define SPR_SGR 953
-#define SPR_DCWR 954
-#define SPR_SLER 955
-#define SPR_SU0R 956
-#define SPR_DBCR1 957
-#define SPR_ICDBDR 979
-#define SPR_ESR 980
-#define SPR_DEAR 981
-#define SPR_EVPR 982
-#define SPR_TSR 984
-#define SPR_TCR 986
-#define SPR_PIT 987
-#define SPR_SRR2 990
-#define SPR_SRR3 991
-#define SPR_DBSR 1008
-#define SPR_DBCR0 1010
-#define SPR_IABR 1010 /* MPC603e core */
-#define SPR_IAC1 1012
-#define SPR_IAC2 1013
-#define SPR_DAC1 1014
-#define SPR_DAC2 1015
-#define SPR_DCCR 1018
-#define SPR_ICCR 1019
-
-/* Bits for the DBCR0 register */
-#define DBCR0_EDM 0x80000000
-#define DBCR0_IDM 0x40000000
-#define DBCR0_RST 0x30000000
-#define DBCR0_IC 0x08000000
-#define DBCR0_BT 0x04000000
-#define DBCR0_EDE 0x02000000
-#define DBCR0_TDE 0x01000000
-#define DBCR0_IA1 0x00800000
-#define DBCR0_IA2 0x00400000
-#define DBCR0_IA12 0x00200000
-#define DBCR0_IA12X 0x00100000
-#define DBCR0_IA3 0x00080000
-#define DBCR0_IA4 0x00040000
-#define DBCR0_IA34 0x00020000
-#define DBCR0_IA34X 0x00010000
-#define DBCR0_IA12T 0x00008000
-#define DBCR0_IA34T 0x00004000
-#define DBCR0_FT 0x00000001
-
-/* Bits for the DBCR1 register */
-#define DBCR1_D1R 0x80000000
-#define DBCR1_D2R 0x40000000
-#define DBCR1_D1W 0x20000000
-#define DBCR1_D2W 0x10000000
-#define DBCR1_D1S 0x0C000000
-#define DBCR1_D2S 0x03000000
-#define DBCR1_DA12 0x00800000
-#define DBCR1_DA12X 0x00400000
-#define DBCR1_DV1M 0x000C0000
-#define DBCR1_DV2M 0x00030000
-#define DBCR1_DV1BE 0x0000F000
-#define DBCR1_DV2BE 0x00000F00
-
-/* Bits for the DBSR register */
-#define DBSR_IC 0x80000000
-#define DBSR_BT 0x40000000
-#define DBSR_EDE 0x20000000
-#define DBSR_TIE 0x10000000
-#define DBSR_UDE 0x08000000
-#define DBSR_IA1 0x04000000
-#define DBSR_IA2 0x02000000
-#define DBSR_DR1 0x01000000
-#define DBSR_DW1 0x00800000
-#define DBSR_DR2 0x00400000
-#define DBSR_DW2 0x00200000
-#define DBSR_IDE 0x00100000
-#define DBSR_IA3 0x00080000
-#define DBSR_IA4 0x00040000
-#define DBSR_MRR 0x00000300
-
-struct spr_info {
- int spr_val;
- char spr_name[ 10 ];
-};
-
-extern struct spr_info spr_map[];
-extern const unsigned int n_sprs;
-
-
-#define SET_REGISTER( str, val ) \
-({ unsigned long __value = (val); \
- asm volatile( str : : "r" (__value)); \
- __value; })
-
-#define GET_REGISTER( str ) \
-({ unsigned long __value; \
- asm volatile( str : "=r" (__value) : ); \
- __value; })
-
-#define GET_CR() GET_REGISTER( "mfcr %0" )
-#define SET_CR(val) SET_REGISTER( "mtcr %0", val )
-#define GET_MSR() GET_REGISTER( "mfmsr %0" )
-#define SET_MSR(val) SET_REGISTER( "mtmsr %0", val )
-#define GET_XER() GET_REGISTER( "mfspr %0,1" )
-#define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val )
-#define GET_LR() GET_REGISTER( "mfspr %0,8" )
-#define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val )
-#define GET_CTR() GET_REGISTER( "mfspr %0,9" )
-#define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val )
-#define GET_DSISR() GET_REGISTER( "mfspr %0,18" )
-#define SET_DSISR(val) SET_REGISTER( "mtspr 18,%0", val )
-#define GET_DAR() GET_REGISTER( "mfspr %0,19" )
-#define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val )
-#define GET_DEC() GET_REGISTER( "mfspr %0,22" )
-#define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val )
-#define GET_SRR0() GET_REGISTER( "mfspr %0,26" )
-#define SET_SRR0(val) SET_REGISTER( "mtspr 26,%0", val )
-#define GET_SRR1() GET_REGISTER( "mfspr %0,27" )
-#define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val )
-#define GET_EIE() GET_REGISTER( "mfspr %0,80" )
-#define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val )
-#define GET_EID() GET_REGISTER( "mfspr %0,81" )
-#define SET_EID(val) SET_REGISTER( "mtspr 81,%0", val )
-#define GET_CMPA() GET_REGISTER( "mfspr %0,144" )
-#define SET_CMPA(val) SET_REGISTER( "mtspr 144,%0", val )
-#define GET_CMPB() GET_REGISTER( "mfspr %0,145" )
-#define SET_CMPB(val) SET_REGISTER( "mtspr 145,%0", val )
-#define GET_CMPC() GET_REGISTER( "mfspr %0,146" )
-#define SET_CMPC(val) SET_REGISTER( "mtspr 146,%0", val )
-#define GET_CMPD() GET_REGISTER( "mfspr %0,147" )
-#define SET_CMPD(val) SET_REGISTER( "mtspr 147,%0", val )
-#define GET_ICR() GET_REGISTER( "mfspr %0,148" )
-#define SET_ICR(val) SET_REGISTER( "mtspr 148,%0", val )
-#define GET_DER() GET_REGISTER( "mfspr %0,149" )
-#define SET_DER(val) SET_REGISTER( "mtspr 149,%0", val )
-#define GET_COUNTA() GET_REGISTER( "mfspr %0,150" )
-#define SET_COUNTA(val) SET_REGISTER( "mtspr 150,%0", val )
-#define GET_COUNTB() GET_REGISTER( "mfspr %0,151" )
-#define SET_COUNTB(val) SET_REGISTER( "mtspr 151,%0", val )
-#define GET_CMPE() GET_REGISTER( "mfspr %0,152" )
-#define SET_CMPE(val) SET_REGISTER( "mtspr 152,%0", val )
-#define GET_CMPF() GET_REGISTER( "mfspr %0,153" )
-#define SET_CMPF(val) SET_REGISTER( "mtspr 153,%0", val )
-#define GET_CMPG() GET_REGISTER( "mfspr %0,154" )
-#define SET_CMPG(val) SET_REGISTER( "mtspr 154,%0", val )
-#define GET_CMPH() GET_REGISTER( "mfspr %0,155" )
-#define SET_CMPH(val) SET_REGISTER( "mtspr 155,%0", val )
-#define GET_LCTRL1() GET_REGISTER( "mfspr %0,156" )
-#define SET_LCTRL1(val) SET_REGISTER( "mtspr 156,%0", val )
-#define GET_LCTRL2() GET_REGISTER( "mfspr %0,157" )
-#define SET_LCTRL2(val) SET_REGISTER( "mtspr 157,%0", val )
-#define GET_ICTRL() GET_REGISTER( "mfspr %0,158" )
-#define SET_ICTRL(val) SET_REGISTER( "mtspr 158,%0", val )
-#define GET_BAR() GET_REGISTER( "mfspr %0,159" )
-#define SET_BAR(val) SET_REGISTER( "mtspr 159,%0", val )
-#define GET_USPRG0() GET_REGISTER( "mfspr %0,256" )
-#define SET_USPRG0(val) SET_REGISTER( "mtspr 256,%0", val )
-#define GET_SPRG4_RO() GET_REGISTER( "mfspr %0,260" )
-#define SET_SPRG4_RO(val) SET_REGISTER( "mtspr 260,%0", val )
-#define GET_SPRG5_RO() GET_REGISTER( "mfspr %0,261" )
-#define SET_SPRG5_RO(val) SET_REGISTER( "mtspr 261,%0", val )
-#define GET_SPRG6_RO() GET_REGISTER( "mfspr %0,262" )
-#define SET_SPRG6_RO(val) SET_REGISTER( "mtspr 262,%0", val )
-#define GET_SPRG7_RO() GET_REGISTER( "mfspr %0,263" )
-#define SET_SPRG7_RO(val) SET_REGISTER( "mtspr 263,%0", val )
-#define GET_SPRG0() GET_REGISTER( "mfspr %0,272" )
-#define SET_SPRG0(val) SET_REGISTER( "mtspr 272,%0", val )
-#define GET_SPRG1() GET_REGISTER( "mfspr %0,273" )
-#define SET_SPRG1(val) SET_REGISTER( "mtspr 273,%0", val )
-#define GET_SPRG2() GET_REGISTER( "mfspr %0,274" )
-#define SET_SPRG2(val) SET_REGISTER( "mtspr 274,%0", val )
-#define GET_SPRG3() GET_REGISTER( "mfspr %0,275" )
-#define SET_SPRG3(val) SET_REGISTER( "mtspr 275,%0", val )
-#define GET_SPRG4() GET_REGISTER( "mfspr %0,276" )
-#define SET_SPRG4(val) SET_REGISTER( "mtspr 276,%0", val )
-#define GET_SPRG5() GET_REGISTER( "mfspr %0,277" )
-#define SET_SPRG5(val) SET_REGISTER( "mtspr 277,%0", val )
-#define GET_SPRG6() GET_REGISTER( "mfspr %0,278" )
-#define SET_SPRG6(val) SET_REGISTER( "mtspr 278,%0", val )
-#define GET_SPRG7() GET_REGISTER( "mfspr %0,279" )
-#define SET_SPRG7(val) SET_REGISTER( "mtspr 279,%0", val )
-#define GET_EAR() GET_REGISTER( "mfspr %0,282" )
-#define SET_EAR(val) SET_REGISTER( "mtspr 282,%0", val )
-#define GET_TBL() GET_REGISTER( "mfspr %0,284" )
-#define SET_TBL(val) SET_REGISTER( "mtspr 284,%0", val )
-#define GET_TBU() GET_REGISTER( "mfspr %0,285" )
-#define SET_TBU(val) SET_REGISTER( "mtspr 285,%0", val )
-#define GET_PVR() GET_REGISTER( "mfspr %0,287" )
-#define SET_PVR(val) SET_REGISTER( "mtspr 287,%0", val )
-#define GET_IC_CST() GET_REGISTER( "mfspr %0,560" )
-#define SET_IC_CST(val) SET_REGISTER( "mtspr 560,%0", val )
-#define GET_IC_ADR() GET_REGISTER( "mfspr %0,561" )
-#define SET_IC_ADR(val) SET_REGISTER( "mtspr 561,%0", val )
-#define GET_IC_DAT() GET_REGISTER( "mfspr %0,562" )
-#define SET_IC_DAT(val) SET_REGISTER( "mtspr 562,%0", val )
-#define GET_DC_CST() GET_REGISTER( "mfspr %0,568" )
-#define SET_DC_CST(val) SET_REGISTER( "mtspr 568,%0", val )
-#define GET_DC_ADR() GET_REGISTER( "mfspr %0,569" )
-#define SET_DC_ADR(val) SET_REGISTER( "mtspr 569,%0", val )
-#define GET_DC_DAT() GET_REGISTER( "mfspr %0,570" )
-#define SET_DC_DAT(val) SET_REGISTER( "mtspr 570,%0", val )
-#define GET_DPDR() GET_REGISTER( "mfspr %0,630" )
-#define SET_DPDR(val) SET_REGISTER( "mtspr 630,%0", val )
-#define GET_IMMR() GET_REGISTER( "mfspr %0,638" )
-#define SET_IMMR(val) SET_REGISTER( "mtspr 638,%0", val )
-#define GET_MI_CTR() GET_REGISTER( "mfspr %0,784" )
-#define SET_MI_CTR(val) SET_REGISTER( "mtspr 784,%0", val )
-#define GET_MI_AP() GET_REGISTER( "mfspr %0,786" )
-#define SET_MI_AP(val) SET_REGISTER( "mtspr 786,%0", val )
-#define GET_MI_EPN() GET_REGISTER( "mfspr %0,787" )
-#define SET_MI_EPN(val) SET_REGISTER( "mtspr 787,%0", val )
-#define GET_MI_TWC() GET_REGISTER( "mfspr %0,789" )
-#define SET_MI_TWC(val) SET_REGISTER( "mtspr 789,%0", val )
-#define GET_MI_RPN() GET_REGISTER( "mfspr %0,790" )
-#define SET_MI_RPN(val) SET_REGISTER( "mtspr 790,%0", val )
-#define GET_MD_CTR() GET_REGISTER( "mfspr %0,792" )
-#define SET_MD_CTR(val) SET_REGISTER( "mtspr 792,%0", val )
-#define GET_M_CASID() GET_REGISTER( "mfspr %0,793" )
-#define SET_M_CASID(val) SET_REGISTER( "mtspr 793,%0", val )
-#define GET_MD_AP() GET_REGISTER( "mfspr %0,794" )
-#define SET_MD_AP(val) SET_REGISTER( "mtspr ,794%0", val )
-#define GET_MD_EPN() GET_REGISTER( "mfspr %0,795" )
-#define SET_MD_EPN(val) SET_REGISTER( "mtspr 795,%0", val )
-#define GET_M_TWB() GET_REGISTER( "mfspr %0,796" )
-#define SET_M_TWB(val) SET_REGISTER( "mtspr 796,%0", val )
-#define GET_MD_TWC() GET_REGISTER( "mfspr %0,797" )
-#define SET_MD_TWC(val) SET_REGISTER( "mtspr 797,%0", val )
-#define GET_MD_RPN() GET_REGISTER( "mfspr %0,798" )
-#define SET_MD_RPN(val) SET_REGISTER( "mtspr 798,%0", val )
-#define GET_M_TW() GET_REGISTER( "mfspr %0,799" )
-#define SET_M_TW(val) SET_REGISTER( "mtspr 799,%0", val )
-#define GET_MI_DBCAM() GET_REGISTER( "mfspr %0,816" )
-#define SET_MI_DBCAM(val) SET_REGISTER( "mtspr 816,%0", val )
-#define GET_MI_DBRAM0() GET_REGISTER( "mfspr %0,817" )
-#define SET_MI_DBRAM0(val) SET_REGISTER( "mtspr 817,%0", val )
-#define GET_MI_DBRAM1() GET_REGISTER( "mfspr %0,818" )
-#define SET_MI_DBRAM1(val) SET_REGISTER( "mtspr 818,%0", val )
-#define GET_MD_DBCAM() GET_REGISTER( "mfspr %0,824" )
-#define SET_MD_DBCA(val) SET_REGISTER( "mtspr 824,%0", val )
-#define GET_MD_DBRAM0() GET_REGISTER( "mfspr %0,825" )
-#define SET_MD_DBRAM0(val) SET_REGISTER( "mtspr 825,%0", val )
-#define GET_MD_DBRAM1() GET_REGISTER( "mfspr %0,826" )
-#define SET_MD_DBRAM1(val) SET_REGISTER( "mtspr 826,%0", val )
-#define GET_ZPR() GET_REGISTER( "mfspr %0,944" )
-#define SET_ZPR(val) SET_REGISTER( "mtspr 944,%0", val )
-#define GET_PID() GET_REGISTER( "mfspr %0,945" )
-#define SET_PID(val) SET_REGISTER( "mtspr 945,%0", val )
-#define GET_CCR0() GET_REGISTER( "mfspr %0,947" )
-#define SET_CCR0(val) SET_REGISTER( "mtspr 947,%0", val )
-#define GET_IAC3() GET_REGISTER( "mfspr %0,948" )
-#define SET_IAC3(val) SET_REGISTER( "mtspr 948,%0", val )
-#define GET_IAC4() GET_REGISTER( "mfspr %0,949" )
-#define SET_IAC4(val) SET_REGISTER( "mtspr 949,%0", val )
-#define GET_DVC1() GET_REGISTER( "mfspr %0,950" )
-#define SET_DVC1(val) SET_REGISTER( "mtspr 950,%0", val )
-#define GET_DVC2() GET_REGISTER( "mfspr %0,951" )
-#define SET_DVC2(val) SET_REGISTER( "mtspr 951,%0", val )
-#define GET_SGR() GET_REGISTER( "mfspr %0,953" )
-#define SET_SGR(val) SET_REGISTER( "mtspr 953,%0", val )
-#define GET_DCWR() GET_REGISTER( "mfspr %0,954" )
-#define SET_DCWR(val) SET_REGISTER( "mtspr 954,%0", val )
-#define GET_SLER() GET_REGISTER( "mfspr %0,955" )
-#define SET_SLER(val) SET_REGISTER( "mtspr 955,%0", val )
-#define GET_SU0R() GET_REGISTER( "mfspr %0,956" )
-#define SET_SU0R(val) SET_REGISTER( "mtspr 956,%0", val )
-#define GET_DBCR1() GET_REGISTER( "mfspr %0,957" )
-#define SET_DBCR1(val) SET_REGISTER( "mtspr 957,%0", val )
-#define GET_ICDBDR() GET_REGISTER( "mfspr %0,979" )
-#define SET_ICDBDR(val) SET_REGISTER( "mtspr 979,%0", val )
-#define GET_ESR() GET_REGISTER( "mfspr %0,980" )
-#define SET_ESR(val) SET_REGISTER( "mtspr 980,%0", val )
-#define GET_DEAR() GET_REGISTER( "mfspr %0,981" )
-#define SET_DEAR(val) SET_REGISTER( "mtspr 981,%0", val )
-#define GET_EVPR() GET_REGISTER( "mfspr %0,982" )
-#define SET_EVPR(val) SET_REGISTER( "mtspr 982,%0", val )
-#define GET_TSR() GET_REGISTER( "mfspr %0,984" )
-#define SET_TSR(val) SET_REGISTER( "mtspr 984,%0", val )
-#define GET_TCR() GET_REGISTER( "mfspr %0,986" )
-#define SET_TCR(val) SET_REGISTER( "mtspr 986,%0", val )
-#define GET_PIT() GET_REGISTER( "mfspr %0,987" )
-#define SET_PIT(val) SET_REGISTER( "mtspr 987,%0", val )
-#define GET_SRR2() GET_REGISTER( "mfspr %0,990" )
-#define SET_SRR2(val) SET_REGISTER( "mtspr 990,%0", val )
-#define GET_SRR3() GET_REGISTER( "mfspr %0,991" )
-#define SET_SRR3(val) SET_REGISTER( "mtspr 991,%0", val )
-#define GET_DBSR() GET_REGISTER( "mfspr %0,1008" )
-#define SET_DBSR(val) SET_REGISTER( "mtspr 1008,%0", val )
-#define GET_DBCR0() GET_REGISTER( "mfspr %0,1010" )
-#define SET_DBCR0(val) SET_REGISTER( "mtspr 1010,%0", val )
-#define GET_IABR() GET_REGISTER( "mfspr %0,1010" )
-#define SET_IABR(val) SET_REGISTER( "mtspr 1010,%0", val )
-#define GET_IAC1() GET_REGISTER( "mfspr %0,1012" )
-#define SET_IAC1(val) SET_REGISTER( "mtspr 1012,%0", val )
-#define GET_IAC2() GET_REGISTER( "mfspr %0,1013" )
-#define SET_IAC2(val) SET_REGISTER( "mtspr 1013,%0", val )
-#define GET_DAC1() GET_REGISTER( "mfspr %0,1014" )
-#define SET_DAC1(val) SET_REGISTER( "mtspr 1014,%0", val )
-#define GET_DAC2() GET_REGISTER( "mfspr %0,1015" )
-#define SET_DAC2(val) SET_REGISTER( "mtspr 1015,%0", val )
-#define GET_DCCR() GET_REGISTER( "mfspr %0,1018" )
-#define SET_DCCR(val) SET_REGISTER( "mtspr 1018,%0", val )
-#define GET_ICCR() GET_REGISTER( "mfspr %0,1019" )
-#define SET_ICCR(val) SET_REGISTER( "mtspr 1019,%0", val )
-
-#endif /* _REGS_H */
-
-
-/*
- * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are freely
- * permitted provided that the above copyright notice and this
- * paragraph and the following disclaimer are duplicated in all
- * such forms.
- *
- * This software is provided "AS IS" and without any express or
- * implied warranties, including, without limitation, the implied
- * warranties of merchantability and fitness for a particular
- * purpose.
- */
+++ /dev/null
-/* $Id$ */
-
-#ifndef TABLES_H
-#define TABLES_H
-
-/* This is only included by common/bedbug.c, and depends on the following
- * files to already be included
- * common.h
- * bedbug/bedbug.h
- * bedbug/ppc.h
- * bedbug/regs.h
- */
-
-struct operand operands[] = {
- /*Field Name Bits Shift Hint Position */
- /*----- ------ ----- ----- ---- ------------ */
- { O_AA, "O_AA", 1, 1, OH_SILENT }, /* 30 */
- { O_BD, "O_BD", 14, 2, OH_ADDR }, /* 16-29 */
- { O_BI, "O_BI", 5, 16, 0 }, /* 11-15 */
- { O_BO, "O_BO", 5, 21, 0 }, /* 6-10 */
- { O_crbD, "O_crbD", 5, 21, 0 }, /* 6-10 */
- { O_crbA, "O_crbA", 5, 16, 0 }, /* 11-15 */
- { O_crbB, "O_crbB", 5, 11, 0 }, /* 16-20 */
- { O_CRM, "O_CRM", 8, 12, 0 }, /* 12-19 */
- { O_d, "O_d", 15, 0, OH_OFFSET }, /* 16-31 */
- { O_frC, "O_frC", 5, 6, 0 }, /* 21-25 */
- { O_frD, "O_frD", 5, 21, 0 }, /* 6-10 */
- { O_frS, "O_frS", 5, 21, 0 }, /* 6-10 */
- { O_IMM, "O_IMM", 4, 12, 0 }, /* 16-19 */
- { O_LI, "O_LI", 24, 2, OH_ADDR }, /* 6-29 */
- { O_LK, "O_LK", 1, 0, OH_SILENT }, /* 31 */
- { O_MB, "O_MB", 5, 6, 0 }, /* 21-25 */
- { O_ME, "O_ME", 5, 1, 0 }, /* 26-30 */
- { O_NB, "O_NB", 5, 11, 0 }, /* 16-20 */
- { O_OE, "O_OE", 1, 10, OH_SILENT }, /* 21 */
- { O_rA, "O_rA", 5, 16, OH_REG }, /* 11-15 */
- { O_rB, "O_rB", 5, 11, OH_REG }, /* 16-20 */
- { O_Rc, "O_Rc", 1, 0, OH_SILENT }, /* 31 */
- { O_rD, "O_rD", 5, 21, OH_REG }, /* 6-10 */
- { O_rS, "O_rS", 5, 21, OH_REG }, /* 6-10 */
- { O_SH, "O_SH", 5, 11, 0 }, /* 16-20 */
- { O_SIMM, "O_SIMM", 16, 0, 0 }, /* 16-31 */
- { O_SR, "O_SR", 4, 16, 0 }, /* 12-15 */
- { O_TO, "O_TO", 5, 21, 0 }, /* 6-10 */
- { O_UIMM, "O_UIMM", 16, 0, 0 }, /* 16-31 */
- { O_crfD, "O_crfD", 3, 23, 0 }, /* 6- 8 */
- { O_crfS, "O_crfS", 3, 18, 0 }, /* 11-13 */
- { O_L, "O_L", 1, 21, 0 }, /* 10 */
- { O_spr, "O_spr", 10, 11, OH_SPR }, /* 11-20 */
- { O_tbr, "O_tbr", 10, 11, OH_TBR }, /* 11-20 */
- { O_cr2, "O_cr2", 0, 0, OH_LITERAL }, /* "cr2" */
-};
-
-const unsigned int n_operands = sizeof(operands) / sizeof(operands[0]);
-
-/* A note about the fields array in the opcodes structure:
- The operands are listed in the order they appear in the output.
-
- This table is arranged in numeric order of the opcode. Note that some
- opcodes have defined bits in odd places so not all forms of a command
- will be in the same place. This is done so that a binary search can be
- done to find the opcodes. Note that table D.2 in the MPC860 User's
- Manual "Instructions Sorted by Opcode" does not account for these
- bit locations */
-
-struct opcode opcodes[] = {
- { D_OPCODE(3), D_MASK, {O_TO, O_rA, O_SIMM, 0},
- 0, "twi", 0 },
- { D_OPCODE(7), D_MASK, {O_rD, O_rA, O_SIMM, 0},
- 0, "mulli", 0 },
- { D_OPCODE(8), D_MASK, {O_rD, O_rA, O_SIMM, 0},
- 0, "subfic", 0 },
- { D_OPCODE(10), D_MASK, {O_crfD, O_L, O_rA, O_UIMM, 0},
- 0, "cmpli", 0 },
- { D_OPCODE(11), D_MASK, {O_crfD, O_L, O_rA, O_SIMM, 0},
- 0, "cmpi", 0 },
- { D_OPCODE(12), D_MASK, {O_rD, O_rA, O_SIMM, 0},
- 0, "addic", 0 },
- { D_OPCODE(13), D_MASK, {O_rD, O_rA, O_SIMM, 0},
- 0, "addic.", 0 },
- { D_OPCODE(14), D_MASK, {O_rD, O_rA, O_SIMM, 0},
- 0, "addi", H_RA0_IS_0 },
- { D_OPCODE(15), D_MASK, {O_rD, O_rA, O_SIMM, 0},
- 0, "addis", H_RA0_IS_0|H_IMM_HIGH },
- { B_OPCODE(16,0,0), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
- handle_bc, "bc", H_RELATIVE },
- { B_OPCODE(16,0,1), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
- 0, "bcl", H_RELATIVE },
- { B_OPCODE(16,1,0), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
- 0, "bca", 0 },
- { B_OPCODE(16,1,1), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
- 0, "bcla", 0 },
- { SC_OPCODE(17), SC_MASK, {0},
- 0, "sc", 0 },
- { I_OPCODE(18,0,0), I_MASK, {O_LI, O_AA, O_LK, 0},
- 0, "b", H_RELATIVE },
- { I_OPCODE(18,0,1), I_MASK, {O_LI, O_AA, O_LK, 0},
- 0, "bl", H_RELATIVE },
- { I_OPCODE(18,1,0), I_MASK, {O_LI, O_AA, O_LK, 0},
- 0, "ba", 0 },
- { I_OPCODE(18,1,1), I_MASK, {O_LI, O_AA, O_LK, 0},
- 0, "bla", 0 },
- { XL_OPCODE(19,0,0), XL_MASK, {O_crfD, O_crfS},
- 0, "mcrf", 0 },
- { XL_OPCODE(19,16,0), XL_MASK, {O_BO, O_BI, O_LK, 0},
- 0, "bclr", 0 },
- { XL_OPCODE(19,16,1), XL_MASK, {O_BO, O_BI, O_LK, 0},
- 0, "bclrl", 0 },
- { XL_OPCODE(19,33,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
- 0, "crnor", 0 },
- { XL_OPCODE(19,50,0), XL_MASK, {0},
- 0, "rfi", 0 },
- { XL_OPCODE(19,129,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
- 0, "crandc", 0 },
- { XL_OPCODE(19,150,0), XL_MASK, {0},
- 0, "isync", 0 },
- { XL_OPCODE(19,193,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
- 0, "crxor", 0 },
- { XL_OPCODE(19,225,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
- 0, "crnand", 0 },
- { XL_OPCODE(19,257,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
- 0, "crand", 0 },
- { XL_OPCODE(19,289,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
- 0, "creqv", 0 },
- { XL_OPCODE(19,417,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
- 0, "crorc", 0 },
- { XL_OPCODE(19,449,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
- 0, "cror", 0 },
- { XL_OPCODE(19,528,0), XL_MASK, {O_BO, O_BI, O_LK, 0},
- 0, "bcctr", 0 },
- { XL_OPCODE(19,528,1), XL_MASK, {O_BO, O_BI, O_LK, 0},
- 0, "bcctrl", 0 },
- { M_OPCODE(20,0), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
- 0, "rlwimi", 0 },
- { M_OPCODE(20,1), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
- 0, "rlwimi.", 0 },
- { M_OPCODE(21,0), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
- 0, "rlwinm", 0 },
- { M_OPCODE(21,1), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
- 0, "rlwinm.", 0 },
- { M_OPCODE(23,0), M_MASK, {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0},
- 0, "rlwnm", 0 },
- { M_OPCODE(23,1), M_MASK, {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0},
- 0, "rlwnm.", 0 },
- { D_OPCODE(24), D_MASK, {O_rA, O_rS, O_UIMM, 0},
- 0, "ori", 0 },
- { D_OPCODE(25), D_MASK, {O_rA, O_rS, O_UIMM, 0},
- 0, "oris", H_IMM_HIGH },
- { D_OPCODE(26), D_MASK, {O_rA, O_rS, O_UIMM, 0},
- 0, "xori", 0 },
- { D_OPCODE(27), D_MASK, {O_rA, O_rS, O_UIMM, 0},
- 0, "xoris", H_IMM_HIGH },
- { D_OPCODE(28), D_MASK, {O_rA, O_rS, O_UIMM, 0},
- 0, "andi.", 0 },
- { D_OPCODE(29), D_MASK, {O_rA, O_rS, O_UIMM, 0},
- 0, "andis.", H_IMM_HIGH },
- { X_OPCODE(31,0,0), X_MASK, {O_crfD, O_L, O_rA, O_rB, 0},
- 0, "cmp", 0 },
- { X_OPCODE(31,4,0), X_MASK, {O_TO, O_rA, O_rB, 0},
- 0, "tw", 0 },
- { XO_OPCODE(31,8,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subfc", 0 },
- { XO_OPCODE(31,8,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subfc.", 0 },
- { XO_OPCODE(31,10,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "addc", 0 },
- { XO_OPCODE(31,10,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "addc.", 0 },
- { XO_OPCODE(31,11,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0},
- 0, "mulhwu", 0 },
- { XO_OPCODE(31,11,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0},
- 0, "mulhwu.", 0 },
- { X_OPCODE(31,19,0), X_MASK, {O_rD, 0},
- 0, "mfcr", 0 },
- { X_OPCODE(31,20,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lwarx", H_RA0_IS_0 },
- { X_OPCODE(31,23,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lwzx", H_RA0_IS_0 },
- { X_OPCODE(31,24,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "slw", 0 },
- { X_OPCODE(31,24,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "slw.", 0 },
- { X_OPCODE(31,26,0), X_MASK, {O_rA, O_rS, O_Rc, 0 },
- 0, "cntlzw", 0 },
- { X_OPCODE(31,26,1), X_MASK, {O_rA, O_rS, O_Rc, 0},
- 0, "cntlzw.", 0 },
- { X_OPCODE(31,28,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "and", 0 },
- { X_OPCODE(31,28,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "and.", 0 },
- { X_OPCODE(31,32,0), X_MASK, {O_crfD, O_L, O_rA, O_rB, 0},
- 0, "cmpl", 0 },
- { XO_OPCODE(31,40,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subf", 0 },
- { XO_OPCODE(31,40,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subf.", 0 },
- { X_OPCODE(31,54,0), X_MASK, {O_rA, O_rB, 0},
- 0, "dcbst", H_RA0_IS_0 },
- { X_OPCODE(31,55,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lwzux", 0 },
- { X_OPCODE(31,60,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "andc", 0 },
- { X_OPCODE(31,60,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "andc.", 0 },
- { XO_OPCODE(31,75,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0},
- 0, "mulhw", 0 },
- { XO_OPCODE(31,75,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0},
- 0, "mulhw.", 0 },
- { X_OPCODE(31,83,0), X_MASK, {O_rD, 0},
- 0, "mfmsr", 0 },
- { X_OPCODE(31,86,0), X_MASK, {O_rA, O_rB, 0},
- 0, "dcbf", H_RA0_IS_0 },
- { X_OPCODE(31,87,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lbzx", H_RA0_IS_0 },
- { XO_OPCODE(31,104,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "neg", 0 },
- { XO_OPCODE(31,104,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "neg.", 0 },
- { X_OPCODE(31,119,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lbzux", 0 },
- { X_OPCODE(31,124,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "nor", 0 },
- { X_OPCODE(31,124,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "nor.", 0 },
- { XO_OPCODE(31,136,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subfe", 0 },
- { XO_OPCODE(31,136,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subfe.", 0 },
- { XO_OPCODE(31,138,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "adde", 0 },
- { XO_OPCODE(31,138,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "adde.", 0 },
- { XFX_OPCODE(31,144,0), XFX_MASK, {O_CRM, O_rS, 0},
- 0, "mtcrf", 0 },
- { X_OPCODE(31,146,0), X_MASK, {O_rS, 0},
- 0, "mtmsr", 0 },
- { X_OPCODE(31,150,1), X_MASK, {O_rS, O_rA, O_rB, 0},
- 0, "stwcx.", 0 },
- { X_OPCODE(31,151,0), X_MASK, {O_rS, O_rA, O_rB, 0},
- 0, "stwx", 0 },
- { X_OPCODE(31,183,0), X_MASK, {O_rS, O_rA, O_rB, 0},
- 0, "stwux", 0 },
- { XO_OPCODE(31,200,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "subfze", 0 },
- { XO_OPCODE(31,200,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "subfze.", 0 },
- { XO_OPCODE(31,202,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "addze", 0 },
- { XO_OPCODE(31,202,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "addze.", 0 },
- { X_OPCODE(31,210,0), X_MASK, {O_SR, O_rS, 0},
- 0, "mtsr", 0 },
- { X_OPCODE(31,215,0), X_MASK, {O_rS, O_rA, O_rB, 0},
- 0, "stbx", H_RA0_IS_0 },
- { XO_OPCODE(31,232,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "subfme", 0 },
- { XO_OPCODE(31,232,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "subfme.", 0 },
- { XO_OPCODE(31,234,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "addme", 0 },
- { XO_OPCODE(31,234,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "addme.", 0 },
- { XO_OPCODE(31,235,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "mullw", 0 },
- { XO_OPCODE(31,235,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "mullw.", 0 },
- { X_OPCODE(31,242,0), X_MASK, {O_rS, O_rB, 0},
- 0, "mtsrin", 0 },
- { X_OPCODE(31,246,0), X_MASK, {O_rA, O_rB, 0},
- 0, "dcbtst", H_RA0_IS_0 },
- { X_OPCODE(31,247,0), X_MASK, {O_rS, O_rA, O_rB, 0},
- 0, "stbux", 0 },
- { XO_OPCODE(31,266,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "add", 0 },
- { XO_OPCODE(31,266,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "add.", 0 },
- { X_OPCODE(31,278,0), X_MASK, {O_rA, O_rB, 0},
- 0, "dcbt", H_RA0_IS_0 },
- { X_OPCODE(31,279,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lhzx", H_RA0_IS_0 },
- { X_OPCODE(31,284,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "eqv", 0 },
- { X_OPCODE(31,284,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "eqv.", 0 },
- { X_OPCODE(31,306,0), X_MASK, {O_rB, 0},
- 0, "tlbie", 0 },
- { X_OPCODE(31,310,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "eciwx", H_RA0_IS_0 },
- { X_OPCODE(31,311,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lhzux", 0 },
- { X_OPCODE(31,316,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "xor", 0 },
- { X_OPCODE(31,316,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "xor.", 0 },
- { XFX_OPCODE(31,339,0), XFX_MASK, {O_rD, O_spr, 0},
- 0, "mfspr", 0 },
- { X_OPCODE(31,343,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lhax", H_RA0_IS_0 },
- { X_OPCODE(31,370,0), X_MASK, {0},
- 0, "tlbia", 0 },
- { XFX_OPCODE(31,371,0), XFX_MASK, {O_rD, O_tbr, 0},
- 0, "mftb", 0 },
- { X_OPCODE(31,375,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lhaux", 0 },
- { X_OPCODE(31,407,0), X_MASK, {O_rS, O_rA, O_rB, 0},
- 0, "sthx", H_RA0_IS_0 },
- { X_OPCODE(31,412,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "orc", 0 },
- { X_OPCODE(31,412,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "orc.", 0 },
- { X_OPCODE(31,438,0), X_MASK, {O_rS, O_rA, O_rB, 0},
- 0, "ecowx", H_RA0_IS_0 },
- { X_OPCODE(31,439,0), X_MASK, {O_rS, O_rA, O_rB, 0},
- 0, "sthux", 0 },
- { X_OPCODE(31,444,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "or", 0 },
- { X_OPCODE(31,444,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "or.", 0 },
- { XO_OPCODE(31,459,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "divwu", 0 },
- { XO_OPCODE(31,459,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "divwu.", 0 },
- { XFX_OPCODE(31,467,0), XFX_MASK, {O_spr, O_rS, 0},
- 0, "mtspr", 0 },
- { X_OPCODE(31,470,0), X_MASK, {O_rA, O_rB, 0},
- 0, "dcbi", H_RA0_IS_0 },
- { X_OPCODE(31,476,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "nand", 0 },
- { X_OPCODE(31,476,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc,0},
- 0, "nand.", 0 },
- { XO_OPCODE(31,491,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "divw", 0 },
- { XO_OPCODE(31,491,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "divw.", 0 },
- { X_OPCODE(31,512,0), X_MASK, {O_crfD, 0},
- 0, "mcrxr", 0 },
- { XO_OPCODE(31,8,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subfco", 0 },
- { XO_OPCODE(31,8,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subfco.", 0 },
- { XO_OPCODE(31,10,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "addco", 0 },
- { XO_OPCODE(31,10,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "addco.", 0 },
- { X_OPCODE(31,533,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lswx", H_RA0_IS_0 },
- { X_OPCODE(31,534,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lwbrx", H_RA0_IS_0 },
- { X_OPCODE(31,536,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "srw", 0 },
- { X_OPCODE(31,536,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "srw.", 0 },
- { XO_OPCODE(31,40,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subfo", 0 },
- { XO_OPCODE(31,40,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subfo.", 0 },
- { X_OPCODE(31,566,0), X_MASK, {0},
- 0, "tlbsync", 0 },
- { X_OPCODE(31,595,0), X_MASK, {O_rD, O_SR, 0},
- 0, "mfsr", 0 },
- { X_OPCODE(31,597,0), X_MASK, {O_rD, O_rA, O_NB, 0},
- 0, "lswi", H_RA0_IS_0 },
- { X_OPCODE(31,598,0), X_MASK, {0},
- 0, "sync", 0 },
- { XO_OPCODE(31,104,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "nego", 0 },
- { XO_OPCODE(31,104,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "nego.", 0 },
- { XO_OPCODE(31,136,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subfeo", 0 },
- { XO_OPCODE(31,136,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subfeo.", 0 },
- { XO_OPCODE(31,138,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "addeo", 0 },
- { XO_OPCODE(31,138,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "addeo.", 0 },
- { X_OPCODE(31,659,0), X_MASK, {O_rD, O_rB, 0},
- 0, "mfsrin", 0 },
- { X_OPCODE(31,661,0), X_MASK, {O_rS, O_rA, O_rB, 0},
- 0, "stswx", H_RA0_IS_0 },
- { X_OPCODE(31,662,0), X_MASK, {O_rS, O_rA, O_rB, 0},
- 0, "stwbrx", H_RA0_IS_0 },
- { XO_OPCODE(31,200,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "subfzeo", 0 },
- { XO_OPCODE(31,200,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "subfzeo.", 0 },
- { XO_OPCODE(31,202,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "addzeo", 0 },
- { XO_OPCODE(31,202,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "addzeo.", 0 },
- { X_OPCODE(31,725,0), X_MASK, {O_rS, O_rA, O_NB, 0},
- 0, "stswi", H_RA0_IS_0 },
- { XO_OPCODE(31,232,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "subfmeo", 0 },
- { XO_OPCODE(31,232,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "subfmeo.", 0 },
- { XO_OPCODE(31,234,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "addmeo", 0 },
- { XO_OPCODE(31,234,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "addmeo.", 0 },
- { XO_OPCODE(31,235,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "mullwo", 0 },
- { XO_OPCODE(31,235,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "mullwo.", 0 },
- { XO_OPCODE(31,266,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "addo", 0 },
- { XO_OPCODE(31,266,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "addo.", 0 },
- { X_OPCODE(31,790,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lhbrx", H_RA0_IS_0 },
- { X_OPCODE(31,792,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "sraw", 0 },
- { X_OPCODE(31,792,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "sraw.", 0 },
- { X_OPCODE(31,824,0), X_MASK, {O_rA, O_rS, O_SH, O_Rc, 0},
- 0, "srawi", 0 },
- { X_OPCODE(31,824,1), X_MASK, {O_rA, O_rS, O_SH, O_Rc, 0},
- 0, "srawi.", 0 },
- { X_OPCODE(31,854,0), X_MASK, {0},
- 0, "eieio", 0 },
- { X_OPCODE(31,918,0), X_MASK, {O_rS, O_rA, O_rB, 0},
- 0, "sthbrx", H_RA0_IS_0 },
- { X_OPCODE(31,922,0), X_MASK, {O_rA, O_rS, O_Rc, 0},
- 0, "extsh", 0 },
- { X_OPCODE(31,922,1), X_MASK, {O_rA, O_rS, O_Rc, 0},
- 0, "extsh.", 0 },
- { X_OPCODE(31,954,0), X_MASK, {O_rA, O_rS, O_Rc, 0},
- 0, "extsb", 0 },
- { X_OPCODE(31,954,1), X_MASK, {O_rA, O_rS, O_Rc, 0},
- 0, "extsb.", 0 },
- { XO_OPCODE(31,459,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "divwuo", 0 },
- { XO_OPCODE(31,459,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "divwuo.", 0 },
- { X_OPCODE(31,978,0), X_MASK, {O_rB, 0},
- 0, "tlbld", 0 },
- { X_OPCODE(31,982,0), X_MASK, {O_rA, O_rB, 0},
- 0, "icbi", H_RA0_IS_0 },
- { XO_OPCODE(31,491,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "divwo", 0 },
- { XO_OPCODE(31,491,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "divwo.", 0 },
- { X_OPCODE(31,1010,0), X_MASK, {O_rB, 0},
- 0, "tlbli", 0 },
- { X_OPCODE(31,1014,0), X_MASK, {O_rA, O_rB, 0},
- 0, "dcbz", H_RA0_IS_0 },
- { D_OPCODE(32), D_MASK, {O_rD, O_d, O_rA, 0},
- 0, "lwz", H_RA0_IS_0 },
- { D_OPCODE(33), D_MASK, {O_rD, O_d, O_rA, 0},
- 0, "lwzu", 0 },
- { D_OPCODE(34), D_MASK, {O_rD, O_d, O_rA, 0},
- 0, "lbz", H_RA0_IS_0 },
- { D_OPCODE(35), D_MASK, {O_rD, O_d, O_rA, 0},
- 0, "lbzu", 0 },
- { D_OPCODE(36), D_MASK, {O_rS, O_d, O_rA, 0},
- 0, "stw", H_RA0_IS_0 },
- { D_OPCODE(37), D_MASK, {O_rS, O_d, O_rA, 0},
- 0, "stwu", 0 },
- { D_OPCODE(38), D_MASK, {O_rS, O_d, O_rA, 0},
- 0, "stb", H_RA0_IS_0 },
- { D_OPCODE(39), D_MASK, {O_rS, O_d, O_rA, 0},
- 0, "stbu", 0 },
- { D_OPCODE(40), D_MASK, {O_rD, O_d, O_rA, 0},
- 0, "lhz", H_RA0_IS_0 },
- { D_OPCODE(41), D_MASK, {O_rD, O_d, O_rA, 0},
- 0, "lhzu", 0 },
- { D_OPCODE(42), D_MASK, {O_rD, O_d, O_rA, 0},
- 0, "lha", H_RA0_IS_0 },
- { D_OPCODE(43), D_MASK, {O_rD, O_d, O_rA, 0},
- 0, "lhau", 0 },
- { D_OPCODE(44), D_MASK, {O_rS, O_d, O_rA, 0},
- 0, "sth", H_RA0_IS_0 },
- { D_OPCODE(45), D_MASK, {O_rS, O_d, O_rA, 0},
- 0, "sthu", 0 },
- { D_OPCODE(46), D_MASK, {O_rD, O_d, O_rA, 0},
- 0, "lmw", H_RA0_IS_0 },
- { D_OPCODE(47), D_MASK, {O_rS, O_d, O_rA, 0},
- 0, "stmw", H_RA0_IS_0 },
-};
-
-const unsigned int n_opcodes = sizeof(opcodes) / sizeof(opcodes[0]);
-
-struct spr_info spr_map[] = {
- { SPR_XER, "XER" },
- { SPR_LR, "LR" },
- { SPR_CTR, "CTR" },
- { SPR_DSISR, "DSISR" },
- { SPR_DAR, "DAR" },
- { SPR_DEC, "DEC" },
- { SPR_SRR0, "SRR0" },
- { SPR_SRR1, "SRR1" },
- { SPR_EIE, "EIE" },
- { SPR_EID, "EID" },
- { SPR_CMPA, "CMPA" },
- { SPR_CMPB, "CMPB" },
- { SPR_CMPC, "CMPC" },
- { SPR_CMPD, "CMPD" },
- { SPR_ICR, "ICR" },
- { SPR_DER, "DER" },
- { SPR_COUNTA, "COUNTA" },
- { SPR_COUNTB, "COUNTB" },
- { SPR_CMPE, "CMPE" },
- { SPR_CMPF, "CMPF" },
- { SPR_CMPG, "CMPG" },
- { SPR_CMPH, "CMPH" },
- { SPR_LCTRL1, "LCTRL1" },
- { SPR_LCTRL2, "LCTRL2" },
- { SPR_ICTRL, "ICTRL" },
- { SPR_BAR, "BAR" },
- { SPR_USPRG0, "USPRG0" },
- { SPR_SPRG4_RO, "SPRG4_RO" },
- { SPR_SPRG5_RO, "SPRG5_RO" },
- { SPR_SPRG6_RO, "SPRG6_RO" },
- { SPR_SPRG7_RO, "SPRG7_RO" },
- { SPR_SPRG0, "SPRG0" },
- { SPR_SPRG1, "SPRG1" },
- { SPR_SPRG2, "SPRG2" },
- { SPR_SPRG3, "SPRG3" },
- { SPR_SPRG4, "SPRG4" },
- { SPR_SPRG5, "SPRG5" },
- { SPR_SPRG6, "SPRG6" },
- { SPR_SPRG7, "SPRG7" },
- { SPR_EAR, "EAR" },
- { SPR_TBL, "TBL" },
- { SPR_TBU, "TBU" },
- { SPR_IC_CST, "IC_CST" },
- { SPR_IC_ADR, "IC_ADR" },
- { SPR_IC_DAT, "IC_DAT" },
- { SPR_DC_CST, "DC_CST" },
- { SPR_DC_ADR, "DC_ADR" },
- { SPR_DC_DAT, "DC_DAT" },
- { SPR_DPDR, "DPDR" },
- { SPR_IMMR, "IMMR" },
- { SPR_MI_CTR, "MI_CTR" },
- { SPR_MI_AP, "MI_AP" },
- { SPR_MI_EPN, "MI_EPN" },
- { SPR_MI_TWC, "MI_TWC" },
- { SPR_MI_RPN, "MI_RPN" },
- { SPR_MD_CTR, "MD_CTR" },
- { SPR_M_CASID, "M_CASID" },
- { SPR_MD_AP, "MD_AP" },
- { SPR_MD_EPN, "MD_EPN" },
- { SPR_M_TWB, "M_TWB" },
- { SPR_MD_TWC, "MD_TWC" },
- { SPR_MD_RPN, "MD_RPN" },
- { SPR_M_TW, "M_TW" },
- { SPR_MI_DBCAM, "MI_DBCAM" },
- { SPR_MI_DBRAM0, "MI_DBRAM0" },
- { SPR_MI_DBRAM1, "MI_DBRAM1" },
- { SPR_MD_DBCAM, "MD_DBCAM" },
- { SPR_MD_DBRAM0, "MD_DBRAM0" },
- { SPR_MD_DBRAM1, "MD_DBRAM1" },
- { SPR_ZPR, "ZPR" },
- { SPR_PID, "PID" },
- { SPR_CCR0, "CCR0" },
- { SPR_IAC3, "IAC3" },
- { SPR_IAC4, "IAC4" },
- { SPR_DVC1, "DVC1" },
- { SPR_DVC2, "DVC2" },
- { SPR_SGR, "SGR" },
- { SPR_DCWR, "DCWR" },
- { SPR_SLER, "SLER" },
- { SPR_SU0R, "SU0R" },
- { SPR_DBCR1, "DBCR1" },
- { SPR_ICDBDR, "ICDBDR" },
- { SPR_ESR, "ESR" },
- { SPR_DEAR, "DEAR" },
- { SPR_EVPR, "EVPR" },
- { SPR_TSR, "TSR" },
- { SPR_TCR, "TCR" },
- { SPR_PIT, "PIT" },
- { SPR_SRR2, "SRR2" },
- { SPR_SRR3, "SRR3" },
- { SPR_DBSR, "DBSR" },
- { SPR_DBCR0, "DBCR0" },
- { SPR_IAC1, "IAC1" },
- { SPR_IAC2, "IAC2" },
- { SPR_DAC1, "DAC1" },
- { SPR_DAC2, "DAC2" },
- { SPR_DCCR, "DCCR" },
- { SPR_ICCR, "ICCR" },
-};
-
-const unsigned int n_sprs = sizeof(spr_map) / sizeof(spr_map[0]);
-
-#endif
-
-/*
- * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are freely
- * permitted provided that the above copyright notice and this
- * paragraph and the following disclaimer are duplicated in all
- * such forms.
- *
- * This software is provided "AS IS" and without any express or
- * implied warranties, including, without limitation, the implied
- * warranties of merchantability and fitness for a particular
- * purpose.
- */
+++ /dev/null
-/*
- * ML300.h: ML300 specific config options
- *
- * http://www.xilinx.com/ml300
- *
- * Derived from : ML2.h
- *
- * Author: Xilinx, Inc.
- *
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- *
- * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
- * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
- * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
- * XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
- * FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR
- * OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
- * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
- * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
- * WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
- * CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
- * FITNESS FOR A PARTICULAR PURPOSE.
- *
- *
- * Xilinx products are not intended for use in life support appliances,
- * devices, or systems. Use in such applications is expressly prohibited.
- *
- *
- * (c) Copyright 2002 Xilinx Inc.
- * All rights reserved.
- *
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* #define DEBUG */
-/* #define ET_DEBUG 1 */
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
-#define CONFIG_XILINX_405 1
-#define CONFIG_XILINX_ML300 1 /* ...on a Xilinx ML300 board */
-
-#define CONFIG_SYSTEMACE 1
-#define CONFIG_DOS_PARTITION 1
-#define CONFIG_SYS_SYSTEMACE_BASE XPAR_OPB_SYSACE_0_BASEADDR
-#define CONFIG_SYS_SYSTEMACE_WIDTH XPAR_XSYSACE_MEM_WIDTH
-
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* environment is in EEPROM */
-
-/* following are used only if env is in EEPROM */
-#ifdef CONFIG_ENV_IS_IN_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_ADDR XPAR_PERSISTENT_0_IIC_0_EEPROMADDR
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_ENV_OFFSET XPAR_PERSISTENT_0_IIC_0_BASEADDR
-#define CONFIG_MISC_INIT_R 1 /* used to call out convert_env() */
-#define CONFIG_ENV_OVERWRITE 1 /* allow users to update ethaddr and serial# */
-#endif
-
-#include "../board/xilinx/ml300/xparameters.h"
-
-#define CONFIG_SYS_NO_FLASH 1 /* no flash */
-#define CONFIG_ENV_SIZE XPAR_PERSISTENT_0_IIC_0_HIGHADDR - XPAR_PERSISTENT_0_IIC_0_BASEADDR + 1
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
-
-#define CONFIG_BOOTARGS "console=ttyS0,9600 ip=off " \
- "root=/dev/xsysace/disc0/part3 rw"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_NET
-
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_FAT
-#undef CONFIG_CMD_IMLS
-
-
-/* #define CONFIG_SYS_CLK_FREQ XPAR_CORE_CLOCK_FREQ_HZ */
-/* 300000000 */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_DUART_CHAN 0
-#define CONFIG_SYS_NS16550_REG_SIZE -4
-#define CONFIG_SYS_NS16550 1
-#define CONFIG_SYS_INIT_CHAN1 1
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_MONITOR_BASE 0x04000000
-#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-
-#define CONFIG_SYS_INIT_RAM_ADDR 0x800000 /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * Copyright (C) 2004 by FS Forth-Systeme GmbH.
- * All rights reserved.
- * Markus Pietrek <mpietrek@fsforth.de>
- *
- * Configuation settings for the NetSilicon NS9750 DevBoard
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
-#define CONFIG_NS9750 1 /* in an NetSilicon NS9750 SoC */
-#define CONFIG_NS9750DEV 1 /* on an NetSilicon NS9750 DevBoard */
-
-/* input clock of PLL */
-#define CONFIG_SYS_CLK_FREQ 324403200 /* Don't use PLL. SW11-4 off */
-
-#define CPU_CLK_FREQ (CONFIG_SYS_CLK_FREQ/2)
-#define AHB_CLK_FREQ (CONFIG_SYS_CLK_FREQ/4)
-#define BBUS_CLK_FREQ (CONFIG_SYS_CLK_FREQ/8)
-
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
-/*@TODO #define CONFIG_STATUS_LED*/
-#define CONFIG_USE_IRQ
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial
- * data */
-
-/*
- * Hardware drivers
- */
-#define CONFIG_NS9750_UART 1 /* use on-chip UART */
-#define CONFIG_DRIVER_NS9750_ETHERNET 1 /* use on-chip ethernet */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_CONS_INDEX 1 /* Port B */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE 38400
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_CONSOLE
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-
-
-#define CONFIG_BOOTDELAY 3
-/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */
-
-#define CONFIG_ETHADDR 00:04:f3:ff:ff:fb /*@TODO unset */
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_IPADDR 192.168.42.30
-#define CONFIG_SERVERIP 192.168.42.1
-
-/*#define CONFIG_BOOTFILE "elinos-lart" */
-/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
-/* what's this ? it's not used anywhere */
-#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "NS9750DEV # " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00780000 /* 7,5 MB in DRAM */ /* @TODO */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00600000 /* default load address */ /* @TODO */
-
-#define CONFIG_SYS_HZ (CPU_CLK_FREQ/64)
-
-/* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
-#define NS9750_ETH_PHY_ADDRESS (0x0000)
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-/* TODO */
-#define CONFIG_NR_DRAM_BANKS 2 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x00800000 /* 8 MB */
-#define PHYS_SDRAM_2 0x10000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_2_SIZE 0x00800000 /* 8 MB */
-
-#define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */
-
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-/* @TODO*/
-#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */
-#if 0
-#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */
-#endif
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#ifdef CONFIG_AMD_LV800
-#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */
-#define CONFIG_SYS_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */
-#endif
-#ifdef CONFIG_AMD_LV400
-#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */
-#define CONFIG_SYS_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */
-#endif
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-/* @TODO */
-/*#define CONFIG_ENV_IS_IN_FLASH 1*/
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
-
-#ifdef CONFIG_STATUS_LED
-
-extern void __led_init(led_id_t mask, int state);
-extern void __led_toggle(led_id_t mask);
-extern void __led_set(led_id_t mask, int state);
-
-#endif /* CONFIG_STATUS_LED */
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * Copyright (c) 1995, 1996, 2001, 2002
- * Erik Theisen. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- * This is the ELF ABI header file
- * formerly known as "elf_abi.h".
- */
-
-#ifndef _ELF_H
-#define _ELF_H
-
-#include "compiler.h"
-
-/*
- * This version doesn't work for 64-bit ABIs - Erik.
- */
-
-/*
- * These typedefs need to be handled better.
- */
-typedef uint32_t Elf32_Addr; /* Unsigned program address */
-typedef uint32_t Elf32_Off; /* Unsigned file offset */
-typedef int32_t Elf32_Sword; /* Signed large integer */
-typedef uint32_t Elf32_Word; /* Unsigned large integer */
-typedef uint16_t Elf32_Half; /* Unsigned medium integer */
-
-/* e_ident[] identification indexes */
-#define EI_MAG0 0 /* file ID */
-#define EI_MAG1 1 /* file ID */
-#define EI_MAG2 2 /* file ID */
-#define EI_MAG3 3 /* file ID */
-#define EI_CLASS 4 /* file class */
-#define EI_DATA 5 /* data encoding */
-#define EI_VERSION 6 /* ELF header version */
-#define EI_OSABI 7 /* OS/ABI specific ELF extensions */
-#define EI_ABIVERSION 8 /* ABI target version */
-#define EI_PAD 9 /* start of pad bytes */
-#define EI_NIDENT 16 /* Size of e_ident[] */
-
-/* e_ident[] magic number */
-#define ELFMAG0 0x7f /* e_ident[EI_MAG0] */
-#define ELFMAG1 'E' /* e_ident[EI_MAG1] */
-#define ELFMAG2 'L' /* e_ident[EI_MAG2] */
-#define ELFMAG3 'F' /* e_ident[EI_MAG3] */
-#define ELFMAG "\177ELF" /* magic */
-#define SELFMAG 4 /* size of magic */
-
-/* e_ident[] file class */
-#define ELFCLASSNONE 0 /* invalid */
-#define ELFCLASS32 1 /* 32-bit objs */
-#define ELFCLASS64 2 /* 64-bit objs */
-#define ELFCLASSNUM 3 /* number of classes */
-
-/* e_ident[] data encoding */
-#define ELFDATANONE 0 /* invalid */
-#define ELFDATA2LSB 1 /* Little-Endian */
-#define ELFDATA2MSB 2 /* Big-Endian */
-#define ELFDATANUM 3 /* number of data encode defines */
-
-/* e_ident[] OS/ABI specific ELF extensions */
-#define ELFOSABI_NONE 0 /* No extension specified */
-#define ELFOSABI_HPUX 1 /* Hewlett-Packard HP-UX */
-#define ELFOSABI_NETBSD 2 /* NetBSD */
-#define ELFOSABI_LINUX 3 /* Linux */
-#define ELFOSABI_SOLARIS 6 /* Sun Solaris */
-#define ELFOSABI_AIX 7 /* AIX */
-#define ELFOSABI_IRIX 8 /* IRIX */
-#define ELFOSABI_FREEBSD 9 /* FreeBSD */
-#define ELFOSABI_TRU64 10 /* Compaq TRU64 UNIX */
-#define ELFOSABI_MODESTO 11 /* Novell Modesto */
-#define ELFOSABI_OPENBSD 12 /* OpenBSD */
-/* 64-255 Architecture-specific value range */
-
-/* e_ident[] ABI Version */
-#define ELFABIVERSION 0
-
-/* e_ident */
-#define IS_ELF(ehdr) ((ehdr).e_ident[EI_MAG0] == ELFMAG0 && \
- (ehdr).e_ident[EI_MAG1] == ELFMAG1 && \
- (ehdr).e_ident[EI_MAG2] == ELFMAG2 && \
- (ehdr).e_ident[EI_MAG3] == ELFMAG3)
-
-/* ELF Header */
-typedef struct elfhdr{
- unsigned char e_ident[EI_NIDENT]; /* ELF Identification */
- Elf32_Half e_type; /* object file type */
- Elf32_Half e_machine; /* machine */
- Elf32_Word e_version; /* object file version */
- Elf32_Addr e_entry; /* virtual entry point */
- Elf32_Off e_phoff; /* program header table offset */
- Elf32_Off e_shoff; /* section header table offset */
- Elf32_Word e_flags; /* processor-specific flags */
- Elf32_Half e_ehsize; /* ELF header size */
- Elf32_Half e_phentsize; /* program header entry size */
- Elf32_Half e_phnum; /* number of program header entries */
- Elf32_Half e_shentsize; /* section header entry size */
- Elf32_Half e_shnum; /* number of section header entries */
- Elf32_Half e_shstrndx; /* section header table's "section
- header string table" entry offset */
-} Elf32_Ehdr;
-
-/* e_type */
-#define ET_NONE 0 /* No file type */
-#define ET_REL 1 /* relocatable file */
-#define ET_EXEC 2 /* executable file */
-#define ET_DYN 3 /* shared object file */
-#define ET_CORE 4 /* core file */
-#define ET_NUM 5 /* number of types */
-#define ET_LOOS 0xfe00 /* reserved range for operating */
-#define ET_HIOS 0xfeff /* system specific e_type */
-#define ET_LOPROC 0xff00 /* reserved range for processor */
-#define ET_HIPROC 0xffff /* specific e_type */
-
-/* e_machine */
-#define EM_NONE 0 /* No Machine */
-#define EM_M32 1 /* AT&T WE 32100 */
-#define EM_SPARC 2 /* SPARC */
-#define EM_386 3 /* Intel 80386 */
-#define EM_68K 4 /* Motorola 68000 */
-#define EM_88K 5 /* Motorola 88000 */
-#if 0
-#define EM_486 6 /* RESERVED - was Intel 80486 */
-#endif
-#define EM_860 7 /* Intel 80860 */
-#define EM_MIPS 8 /* MIPS R3000 Big-Endian only */
-#define EM_S370 9 /* IBM System/370 Processor */
-#define EM_MIPS_RS4_BE 10 /* MIPS R4000 Big-Endian */
-#if 0
-#define EM_SPARC64 11 /* RESERVED - was SPARC v9
- 64-bit unoffical */
-#endif
-/* RESERVED 11-14 for future use */
-#define EM_PARISC 15 /* HPPA */
-/* RESERVED 16 for future use */
-#define EM_VPP500 17 /* Fujitsu VPP500 */
-#define EM_SPARC32PLUS 18 /* Enhanced instruction set SPARC */
-#define EM_960 19 /* Intel 80960 */
-#define EM_PPC 20 /* PowerPC */
-#define EM_PPC64 21 /* 64-bit PowerPC */
-#define EM_S390 22 /* IBM System/390 Processor */
-/* RESERVED 23-35 for future use */
-#define EM_V800 36 /* NEC V800 */
-#define EM_FR20 37 /* Fujitsu FR20 */
-#define EM_RH32 38 /* TRW RH-32 */
-#define EM_RCE 39 /* Motorola RCE */
-#define EM_ARM 40 /* Advanced Risc Machines ARM */
-#define EM_ALPHA 41 /* Digital Alpha */
-#define EM_SH 42 /* Hitachi SH */
-#define EM_SPARCV9 43 /* SPARC Version 9 */
-#define EM_TRICORE 44 /* Siemens TriCore embedded processor */
-#define EM_ARC 45 /* Argonaut RISC Core */
-#define EM_H8_300 46 /* Hitachi H8/300 */
-#define EM_H8_300H 47 /* Hitachi H8/300H */
-#define EM_H8S 48 /* Hitachi H8S */
-#define EM_H8_500 49 /* Hitachi H8/500 */
-#define EM_IA_64 50 /* Intel Merced */
-#define EM_MIPS_X 51 /* Stanford MIPS-X */
-#define EM_COLDFIRE 52 /* Motorola Coldfire */
-#define EM_68HC12 53 /* Motorola M68HC12 */
-#define EM_MMA 54 /* Fujitsu MMA Multimedia Accelerator*/
-#define EM_PCP 55 /* Siemens PCP */
-#define EM_NCPU 56 /* Sony nCPU embeeded RISC */
-#define EM_NDR1 57 /* Denso NDR1 microprocessor */
-#define EM_STARCORE 58 /* Motorola Start*Core processor */
-#define EM_ME16 59 /* Toyota ME16 processor */
-#define EM_ST100 60 /* STMicroelectronic ST100 processor */
-#define EM_TINYJ 61 /* Advanced Logic Corp. Tinyj emb.fam*/
-#define EM_X86_64 62 /* AMD x86-64 */
-#define EM_PDSP 63 /* Sony DSP Processor */
-/* RESERVED 64,65 for future use */
-#define EM_FX66 66 /* Siemens FX66 microcontroller */
-#define EM_ST9PLUS 67 /* STMicroelectronics ST9+ 8/16 mc */
-#define EM_ST7 68 /* STmicroelectronics ST7 8 bit mc */
-#define EM_68HC16 69 /* Motorola MC68HC16 microcontroller */
-#define EM_68HC11 70 /* Motorola MC68HC11 microcontroller */
-#define EM_68HC08 71 /* Motorola MC68HC08 microcontroller */
-#define EM_68HC05 72 /* Motorola MC68HC05 microcontroller */
-#define EM_SVX 73 /* Silicon Graphics SVx */
-#define EM_ST19 74 /* STMicroelectronics ST19 8 bit mc */
-#define EM_VAX 75 /* Digital VAX */
-#define EM_CHRIS 76 /* Axis Communications embedded proc. */
-#define EM_JAVELIN 77 /* Infineon Technologies emb. proc. */
-#define EM_FIREPATH 78 /* Element 14 64-bit DSP Processor */
-#define EM_ZSP 79 /* LSI Logic 16-bit DSP Processor */
-#define EM_MMIX 80 /* Donald Knuth's edu 64-bit proc. */
-#define EM_HUANY 81 /* Harvard University mach-indep objs */
-#define EM_PRISM 82 /* SiTera Prism */
-#define EM_AVR 83 /* Atmel AVR 8-bit microcontroller */
-#define EM_FR30 84 /* Fujitsu FR30 */
-#define EM_D10V 85 /* Mitsubishi DV10V */
-#define EM_D30V 86 /* Mitsubishi DV30V */
-#define EM_V850 87 /* NEC v850 */
-#define EM_M32R 88 /* Mitsubishi M32R */
-#define EM_MN10300 89 /* Matsushita MN10200 */
-#define EM_MN10200 90 /* Matsushita MN10200 */
-#define EM_PJ 91 /* picoJava */
-#define EM_NUM 92 /* number of machine types */
-
-/* Version */
-#define EV_NONE 0 /* Invalid */
-#define EV_CURRENT 1 /* Current */
-#define EV_NUM 2 /* number of versions */
-
-/* Section Header */
-typedef struct {
- Elf32_Word sh_name; /* name - index into section header
- string table section */
- Elf32_Word sh_type; /* type */
- Elf32_Word sh_flags; /* flags */
- Elf32_Addr sh_addr; /* address */
- Elf32_Off sh_offset; /* file offset */
- Elf32_Word sh_size; /* section size */
- Elf32_Word sh_link; /* section header table index link */
- Elf32_Word sh_info; /* extra information */
- Elf32_Word sh_addralign; /* address alignment */
- Elf32_Word sh_entsize; /* section entry size */
-} Elf32_Shdr;
-
-/* Special Section Indexes */
-#define SHN_UNDEF 0 /* undefined */
-#define SHN_LORESERVE 0xff00 /* lower bounds of reserved indexes */
-#define SHN_LOPROC 0xff00 /* reserved range for processor */
-#define SHN_HIPROC 0xff1f /* specific section indexes */
-#define SHN_LOOS 0xff20 /* reserved range for operating */
-#define SHN_HIOS 0xff3f /* specific semantics */
-#define SHN_ABS 0xfff1 /* absolute value */
-#define SHN_COMMON 0xfff2 /* common symbol */
-#define SHN_XINDEX 0xffff /* Index is an extra table */
-#define SHN_HIRESERVE 0xffff /* upper bounds of reserved indexes */
-
-/* sh_type */
-#define SHT_NULL 0 /* inactive */
-#define SHT_PROGBITS 1 /* program defined information */
-#define SHT_SYMTAB 2 /* symbol table section */
-#define SHT_STRTAB 3 /* string table section */
-#define SHT_RELA 4 /* relocation section with addends*/
-#define SHT_HASH 5 /* symbol hash table section */
-#define SHT_DYNAMIC 6 /* dynamic section */
-#define SHT_NOTE 7 /* note section */
-#define SHT_NOBITS 8 /* no space section */
-#define SHT_REL 9 /* relation section without addends */
-#define SHT_SHLIB 10 /* reserved - purpose unknown */
-#define SHT_DYNSYM 11 /* dynamic symbol table section */
-#define SHT_INIT_ARRAY 14 /* Array of constructors */
-#define SHT_FINI_ARRAY 15 /* Array of destructors */
-#define SHT_PREINIT_ARRAY 16 /* Array of pre-constructors */
-#define SHT_GROUP 17 /* Section group */
-#define SHT_SYMTAB_SHNDX 18 /* Extended section indeces */
-#define SHT_NUM 19 /* number of section types */
-#define SHT_LOOS 0x60000000 /* Start OS-specific */
-#define SHT_HIOS 0x6fffffff /* End OS-specific */
-#define SHT_LOPROC 0x70000000 /* reserved range for processor */
-#define SHT_HIPROC 0x7fffffff /* specific section header types */
-#define SHT_LOUSER 0x80000000 /* reserved range for application */
-#define SHT_HIUSER 0xffffffff /* specific indexes */
-
-/* Section names */
-#define ELF_BSS ".bss" /* uninitialized data */
-#define ELF_COMMENT ".comment" /* version control information */
-#define ELF_DATA ".data" /* initialized data */
-#define ELF_DATA1 ".data1" /* initialized data */
-#define ELF_DEBUG ".debug" /* debug */
-#define ELF_DYNAMIC ".dynamic" /* dynamic linking information */
-#define ELF_DYNSTR ".dynstr" /* dynamic string table */
-#define ELF_DYNSYM ".dynsym" /* dynamic symbol table */
-#define ELF_FINI ".fini" /* termination code */
-#define ELF_FINI_ARRAY ".fini_array" /* Array of destructors */
-#define ELF_GOT ".got" /* global offset table */
-#define ELF_HASH ".hash" /* symbol hash table */
-#define ELF_INIT ".init" /* initialization code */
-#define ELF_INIT_ARRAY ".init_array" /* Array of constuctors */
-#define ELF_INTERP ".interp" /* Pathname of program interpreter */
-#define ELF_LINE ".line" /* Symbolic line numnber information */
-#define ELF_NOTE ".note" /* Contains note section */
-#define ELF_PLT ".plt" /* Procedure linkage table */
-#define ELF_PREINIT_ARRAY ".preinit_array" /* Array of pre-constructors */
-#define ELF_REL_DATA ".rel.data" /* relocation data */
-#define ELF_REL_FINI ".rel.fini" /* relocation termination code */
-#define ELF_REL_INIT ".rel.init" /* relocation initialization code */
-#define ELF_REL_DYN ".rel.dyn" /* relocaltion dynamic link info */
-#define ELF_REL_RODATA ".rel.rodata" /* relocation read-only data */
-#define ELF_REL_TEXT ".rel.text" /* relocation code */
-#define ELF_RODATA ".rodata" /* read-only data */
-#define ELF_RODATA1 ".rodata1" /* read-only data */
-#define ELF_SHSTRTAB ".shstrtab" /* section header string table */
-#define ELF_STRTAB ".strtab" /* string table */
-#define ELF_SYMTAB ".symtab" /* symbol table */
-#define ELF_SYMTAB_SHNDX ".symtab_shndx"/* symbol table section index */
-#define ELF_TBSS ".tbss" /* thread local uninit data */
-#define ELF_TDATA ".tdata" /* thread local init data */
-#define ELF_TDATA1 ".tdata1" /* thread local init data */
-#define ELF_TEXT ".text" /* code */
-
-/* Section Attribute Flags - sh_flags */
-#define SHF_WRITE 0x1 /* Writable */
-#define SHF_ALLOC 0x2 /* occupies memory */
-#define SHF_EXECINSTR 0x4 /* executable */
-#define SHF_MERGE 0x10 /* Might be merged */
-#define SHF_STRINGS 0x20 /* Contains NULL terminated strings */
-#define SHF_INFO_LINK 0x40 /* sh_info contains SHT index */
-#define SHF_LINK_ORDER 0x80 /* Preserve order after combining*/
-#define SHF_OS_NONCONFORMING 0x100 /* Non-standard OS specific handling */
-#define SHF_GROUP 0x200 /* Member of section group */
-#define SHF_TLS 0x400 /* Thread local storage */
-#define SHF_MASKOS 0x0ff00000 /* OS specific */
-#define SHF_MASKPROC 0xf0000000 /* reserved bits for processor */
- /* specific section attributes */
-
-/* Section Group Flags */
-#define GRP_COMDAT 0x1 /* COMDAT group */
-#define GRP_MASKOS 0x0ff00000 /* Mask OS specific flags */
-#define GRP_MASKPROC 0xf0000000 /* Mask processor specific flags */
-
-/* Symbol Table Entry */
-typedef struct elf32_sym {
- Elf32_Word st_name; /* name - index into string table */
- Elf32_Addr st_value; /* symbol value */
- Elf32_Word st_size; /* symbol size */
- unsigned char st_info; /* type and binding */
- unsigned char st_other; /* 0 - no defined meaning */
- Elf32_Half st_shndx; /* section header index */
-} Elf32_Sym;
-
-/* Symbol table index */
-#define STN_UNDEF 0 /* undefined */
-
-/* Extract symbol info - st_info */
-#define ELF32_ST_BIND(x) ((x) >> 4)
-#define ELF32_ST_TYPE(x) (((unsigned int) x) & 0xf)
-#define ELF32_ST_INFO(b,t) (((b) << 4) + ((t) & 0xf))
-#define ELF32_ST_VISIBILITY(x) ((x) & 0x3)
-
-/* Symbol Binding - ELF32_ST_BIND - st_info */
-#define STB_LOCAL 0 /* Local symbol */
-#define STB_GLOBAL 1 /* Global symbol */
-#define STB_WEAK 2 /* like global - lower precedence */
-#define STB_NUM 3 /* number of symbol bindings */
-#define STB_LOOS 10 /* reserved range for operating */
-#define STB_HIOS 12 /* system specific symbol bindings */
-#define STB_LOPROC 13 /* reserved range for processor */
-#define STB_HIPROC 15 /* specific symbol bindings */
-
-/* Symbol type - ELF32_ST_TYPE - st_info */
-#define STT_NOTYPE 0 /* not specified */
-#define STT_OBJECT 1 /* data object */
-#define STT_FUNC 2 /* function */
-#define STT_SECTION 3 /* section */
-#define STT_FILE 4 /* file */
-#define STT_NUM 5 /* number of symbol types */
-#define STT_TLS 6 /* Thread local storage symbol */
-#define STT_LOOS 10 /* reserved range for operating */
-#define STT_HIOS 12 /* system specific symbol types */
-#define STT_LOPROC 13 /* reserved range for processor */
-#define STT_HIPROC 15 /* specific symbol types */
-
-/* Symbol visibility - ELF32_ST_VISIBILITY - st_other */
-#define STV_DEFAULT 0 /* Normal visibility rules */
-#define STV_INTERNAL 1 /* Processor specific hidden class */
-#define STV_HIDDEN 2 /* Symbol unavailable in other mods */
-#define STV_PROTECTED 3 /* Not preemptible, not exported */
-
-
-/* Relocation entry with implicit addend */
-typedef struct
-{
- Elf32_Addr r_offset; /* offset of relocation */
- Elf32_Word r_info; /* symbol table index and type */
-} Elf32_Rel;
-
-/* Relocation entry with explicit addend */
-typedef struct
-{
- Elf32_Addr r_offset; /* offset of relocation */
- Elf32_Word r_info; /* symbol table index and type */
- Elf32_Sword r_addend;
-} Elf32_Rela;
-
-/* Extract relocation info - r_info */
-#define ELF32_R_SYM(i) ((i) >> 8)
-#define ELF32_R_TYPE(i) ((unsigned char) (i))
-#define ELF32_R_INFO(s,t) (((s) << 8) + (unsigned char)(t))
-
-/* Program Header */
-typedef struct {
- Elf32_Word p_type; /* segment type */
- Elf32_Off p_offset; /* segment offset */
- Elf32_Addr p_vaddr; /* virtual address of segment */
- Elf32_Addr p_paddr; /* physical address - ignored? */
- Elf32_Word p_filesz; /* number of bytes in file for seg. */
- Elf32_Word p_memsz; /* number of bytes in mem. for seg. */
- Elf32_Word p_flags; /* flags */
- Elf32_Word p_align; /* memory alignment */
-} Elf32_Phdr;
-
-/* Segment types - p_type */
-#define PT_NULL 0 /* unused */
-#define PT_LOAD 1 /* loadable segment */
-#define PT_DYNAMIC 2 /* dynamic linking section */
-#define PT_INTERP 3 /* the RTLD */
-#define PT_NOTE 4 /* auxiliary information */
-#define PT_SHLIB 5 /* reserved - purpose undefined */
-#define PT_PHDR 6 /* program header */
-#define PT_TLS 7 /* Thread local storage template */
-#define PT_NUM 8 /* Number of segment types */
-#define PT_LOOS 0x60000000 /* reserved range for operating */
-#define PT_HIOS 0x6fffffff /* system specific segment types */
-#define PT_LOPROC 0x70000000 /* reserved range for processor */
-#define PT_HIPROC 0x7fffffff /* specific segment types */
-
-/* Segment flags - p_flags */
-#define PF_X 0x1 /* Executable */
-#define PF_W 0x2 /* Writable */
-#define PF_R 0x4 /* Readable */
-#define PF_MASKOS 0x0ff00000 /* OS specific segment flags */
-#define PF_MASKPROC 0xf0000000 /* reserved bits for processor */
- /* specific segment flags */
-/* Dynamic structure */
-typedef struct
-{
- Elf32_Sword d_tag; /* controls meaning of d_val */
- union
- {
- Elf32_Word d_val; /* Multiple meanings - see d_tag */
- Elf32_Addr d_ptr; /* program virtual address */
- } d_un;
-} Elf32_Dyn;
-
-extern Elf32_Dyn _DYNAMIC[];
-
-/* Dynamic Array Tags - d_tag */
-#define DT_NULL 0 /* marks end of _DYNAMIC array */
-#define DT_NEEDED 1 /* string table offset of needed lib */
-#define DT_PLTRELSZ 2 /* size of relocation entries in PLT */
-#define DT_PLTGOT 3 /* address PLT/GOT */
-#define DT_HASH 4 /* address of symbol hash table */
-#define DT_STRTAB 5 /* address of string table */
-#define DT_SYMTAB 6 /* address of symbol table */
-#define DT_RELA 7 /* address of relocation table */
-#define DT_RELASZ 8 /* size of relocation table */
-#define DT_RELAENT 9 /* size of relocation entry */
-#define DT_STRSZ 10 /* size of string table */
-#define DT_SYMENT 11 /* size of symbol table entry */
-#define DT_INIT 12 /* address of initialization func. */
-#define DT_FINI 13 /* address of termination function */
-#define DT_SONAME 14 /* string table offset of shared obj */
-#define DT_RPATH 15 /* string table offset of library
- search path */
-#define DT_SYMBOLIC 16 /* start sym search in shared obj. */
-#define DT_REL 17 /* address of rel. tbl. w addends */
-#define DT_RELSZ 18 /* size of DT_REL relocation table */
-#define DT_RELENT 19 /* size of DT_REL relocation entry */
-#define DT_PLTREL 20 /* PLT referenced relocation entry */
-#define DT_DEBUG 21 /* bugger */
-#define DT_TEXTREL 22 /* Allow rel. mod. to unwritable seg */
-#define DT_JMPREL 23 /* add. of PLT's relocation entries */
-#define DT_BIND_NOW 24 /* Process relocations of object */
-#define DT_INIT_ARRAY 25 /* Array with addresses of init fct */
-#define DT_FINI_ARRAY 26 /* Array with addresses of fini fct */
-#define DT_INIT_ARRAYSZ 27 /* Size in bytes of DT_INIT_ARRAY */
-#define DT_FINI_ARRAYSZ 28 /* Size in bytes of DT_FINI_ARRAY */
-#define DT_RUNPATH 29 /* Library search path */
-#define DT_FLAGS 30 /* Flags for the object being loaded */
-#define DT_ENCODING 32 /* Start of encoded range */
-#define DT_PREINIT_ARRAY 32 /* Array with addresses of preinit fct*/
-#define DT_PREINIT_ARRAYSZ 33 /* size in bytes of DT_PREINIT_ARRAY */
-#define DT_NUM 34 /* Number used. */
-#define DT_LOOS 0x60000000 /* reserved range for OS */
-#define DT_HIOS 0x6fffffff /* specific dynamic array tags */
-#define DT_LOPROC 0x70000000 /* reserved range for processor */
-#define DT_HIPROC 0x7fffffff /* specific dynamic array tags */
-
-/* Dynamic Tag Flags - d_un.d_val */
-#define DF_ORIGIN 0x01 /* Object may use DF_ORIGIN */
-#define DF_SYMBOLIC 0x02 /* Symbol resolutions starts here */
-#define DF_TEXTREL 0x04 /* Object contains text relocations */
-#define DF_BIND_NOW 0x08 /* No lazy binding for this object */
-#define DF_STATIC_TLS 0x10 /* Static thread local storage */
-
-/* Standard ELF hashing function */
-unsigned long elf_hash(const unsigned char *name);
-
-#define ELF_TARG_VER 1 /* The ver for which this code is intended */
-
-/*
- * XXX - PowerPC defines really don't belong in here,
- * but we'll put them in for simplicity.
- */
-
-/* Values for Elf32/64_Ehdr.e_flags. */
-#define EF_PPC_EMB 0x80000000 /* PowerPC embedded flag */
-
-/* Cygnus local bits below */
-#define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag*/
-#define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib
- flag */
-
-/* PowerPC relocations defined by the ABIs */
-#define R_PPC_NONE 0
-#define R_PPC_ADDR32 1 /* 32bit absolute address */
-#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */
-#define R_PPC_ADDR16 3 /* 16bit absolute address */
-#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */
-#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */
-#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */
-#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */
-#define R_PPC_ADDR14_BRTAKEN 8
-#define R_PPC_ADDR14_BRNTAKEN 9
-#define R_PPC_REL24 10 /* PC relative 26 bit */
-#define R_PPC_REL14 11 /* PC relative 16 bit */
-#define R_PPC_REL14_BRTAKEN 12
-#define R_PPC_REL14_BRNTAKEN 13
-#define R_PPC_GOT16 14
-#define R_PPC_GOT16_LO 15
-#define R_PPC_GOT16_HI 16
-#define R_PPC_GOT16_HA 17
-#define R_PPC_PLTREL24 18
-#define R_PPC_COPY 19
-#define R_PPC_GLOB_DAT 20
-#define R_PPC_JMP_SLOT 21
-#define R_PPC_RELATIVE 22
-#define R_PPC_LOCAL24PC 23
-#define R_PPC_UADDR32 24
-#define R_PPC_UADDR16 25
-#define R_PPC_REL32 26
-#define R_PPC_PLT32 27
-#define R_PPC_PLTREL32 28
-#define R_PPC_PLT16_LO 29
-#define R_PPC_PLT16_HI 30
-#define R_PPC_PLT16_HA 31
-#define R_PPC_SDAREL16 32
-#define R_PPC_SECTOFF 33
-#define R_PPC_SECTOFF_LO 34
-#define R_PPC_SECTOFF_HI 35
-#define R_PPC_SECTOFF_HA 36
-/* Keep this the last entry. */
-#define R_PPC_NUM 37
-
-/* The remaining relocs are from the Embedded ELF ABI, and are not
- in the SVR4 ELF ABI. */
-#define R_PPC_EMB_NADDR32 101
-#define R_PPC_EMB_NADDR16 102
-#define R_PPC_EMB_NADDR16_LO 103
-#define R_PPC_EMB_NADDR16_HI 104
-#define R_PPC_EMB_NADDR16_HA 105
-#define R_PPC_EMB_SDAI16 106
-#define R_PPC_EMB_SDA2I16 107
-#define R_PPC_EMB_SDA2REL 108
-#define R_PPC_EMB_SDA21 109 /* 16 bit offset in SDA */
-#define R_PPC_EMB_MRKREF 110
-#define R_PPC_EMB_RELSEC16 111
-#define R_PPC_EMB_RELST_LO 112
-#define R_PPC_EMB_RELST_HI 113
-#define R_PPC_EMB_RELST_HA 114
-#define R_PPC_EMB_BIT_FLD 115
-#define R_PPC_EMB_RELSDA 116 /* 16 bit relative offset in SDA */
-
-/* Diab tool relocations. */
-#define R_PPC_DIAB_SDA21_LO 180 /* like EMB_SDA21, but lower 16 bit */
-#define R_PPC_DIAB_SDA21_HI 181 /* like EMB_SDA21, but high 16 bit */
-#define R_PPC_DIAB_SDA21_HA 182 /* like EMB_SDA21, adjusted high 16 */
-#define R_PPC_DIAB_RELSDA_LO 183 /* like EMB_RELSDA, but lower 16 bit */
-#define R_PPC_DIAB_RELSDA_HI 184 /* like EMB_RELSDA, but high 16 bit */
-#define R_PPC_DIAB_RELSDA_HA 185 /* like EMB_RELSDA, adjusted high 16 */
-
-/* This is a phony reloc to handle any old fashioned TOC16 references
- that may still be in object files. */
-#define R_PPC_TOC16 255
-
-#endif /* _ELF_H */
+++ /dev/null
-/*
- * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
- * Copyright 2003-2004 Jeff Garzik
- * Copyright (C) 2008 Freescale Semiconductor, Inc.
- * Dave Liu <daveliu@freescale.com>
- * port from libata of linux kernel
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#ifndef __LIBATA_H__
-#define __LIBATA_H__
-
-#include <common.h>
-
-enum {
- /* various global constants */
- ATA_MAX_DEVICES = 2, /* per bus/port */
- ATA_MAX_PRD = 256, /* we could make these 256/256 */
- ATA_SECT_SIZE = 512,
- ATA_MAX_SECTORS_128 = 128,
- ATA_MAX_SECTORS = 256,
- ATA_MAX_SECTORS_LBA48 = 65535,
- ATA_MAX_SECTORS_TAPE = 65535,
-
- ATA_ID_WORDS = 256,
- ATA_ID_SERNO = 10,
- ATA_ID_FW_REV = 23,
- ATA_ID_PROD = 27,
- ATA_ID_OLD_PIO_MODES = 51,
- ATA_ID_FIELD_VALID = 53,
- ATA_ID_LBA_SECTORS = 60,
- ATA_ID_MWDMA_MODES = 63,
- ATA_ID_PIO_MODES = 64,
- ATA_ID_EIDE_DMA_MIN = 65,
- ATA_ID_EIDE_PIO = 67,
- ATA_ID_EIDE_PIO_IORDY = 68,
- ATA_ID_PIO4 = (1 << 1),
- ATA_ID_QUEUE_DEPTH = 75,
- ATA_ID_SATA_CAP = 76,
- ATA_ID_SATA_FEATURES = 78,
- ATA_ID_SATA_FEATURES_EN = 79,
- ATA_ID_MAJOR_VER = 80,
- ATA_ID_MINOR_VER = 81,
- ATA_ID_UDMA_MODES = 88,
- ATA_ID_LBA48_SECTORS = 100,
-
- ATA_ID_SERNO_LEN = 20,
- ATA_ID_FW_REV_LEN = 8,
- ATA_ID_PROD_LEN = 40,
-
- ATA_PCI_CTL_OFS = 2,
-
- ATA_PIO0 = (1 << 0),
- ATA_PIO1 = ATA_PIO0 | (1 << 1),
- ATA_PIO2 = ATA_PIO1 | (1 << 2),
- ATA_PIO3 = ATA_PIO2 | (1 << 3),
- ATA_PIO4 = ATA_PIO3 | (1 << 4),
- ATA_PIO5 = ATA_PIO4 | (1 << 5),
- ATA_PIO6 = ATA_PIO5 | (1 << 6),
-
- ATA_SWDMA0 = (1 << 0),
- ATA_SWDMA1 = ATA_SWDMA0 | (1 << 1),
- ATA_SWDMA2 = ATA_SWDMA1 | (1 << 2),
-
- ATA_SWDMA2_ONLY = (1 << 2),
-
- ATA_MWDMA0 = (1 << 0),
- ATA_MWDMA1 = ATA_MWDMA0 | (1 << 1),
- ATA_MWDMA2 = ATA_MWDMA1 | (1 << 2),
-
- ATA_MWDMA12_ONLY = (1 << 1) | (1 << 2),
- ATA_MWDMA2_ONLY = (1 << 2),
-
- ATA_UDMA0 = (1 << 0),
- ATA_UDMA1 = ATA_UDMA0 | (1 << 1),
- ATA_UDMA2 = ATA_UDMA1 | (1 << 2),
- ATA_UDMA3 = ATA_UDMA2 | (1 << 3),
- ATA_UDMA4 = ATA_UDMA3 | (1 << 4),
- ATA_UDMA5 = ATA_UDMA4 | (1 << 5),
- ATA_UDMA6 = ATA_UDMA5 | (1 << 6),
- ATA_UDMA7 = ATA_UDMA6 | (1 << 7),
- /* ATA_UDMA7 is just for completeness... doesn't exist (yet?). */
-
- ATA_UDMA_MASK_40C = ATA_UDMA2, /* udma0-2 */
-
- /* DMA-related */
- ATA_PRD_SZ = 8,
- ATA_PRD_TBL_SZ = (ATA_MAX_PRD * ATA_PRD_SZ),
- ATA_PRD_EOT = (1 << 31), /* end-of-table flag */
-
- ATA_DMA_TABLE_OFS = 4,
- ATA_DMA_STATUS = 2,
- ATA_DMA_CMD = 0,
- ATA_DMA_WR = (1 << 3),
- ATA_DMA_START = (1 << 0),
- ATA_DMA_INTR = (1 << 2),
- ATA_DMA_ERR = (1 << 1),
- ATA_DMA_ACTIVE = (1 << 0),
-
- /* bits in ATA command block registers */
- ATA_HOB = (1 << 7), /* LBA48 selector */
- ATA_NIEN = (1 << 1), /* disable-irq flag */
- ATA_LBA = (1 << 6), /* LBA28 selector */
- ATA_DEV1 = (1 << 4), /* Select Device 1 (slave) */
- ATA_DEVICE_OBS = (1 << 7) | (1 << 5), /* obs bits in dev reg */
- ATA_DEVCTL_OBS = (1 << 3), /* obsolete bit in devctl reg */
- ATA_BUSY = (1 << 7), /* BSY status bit */
- ATA_DRDY = (1 << 6), /* device ready */
- ATA_DF = (1 << 5), /* device fault */
- ATA_DRQ = (1 << 3), /* data request i/o */
- ATA_ERR = (1 << 0), /* have an error */
- ATA_SRST = (1 << 2), /* software reset */
- ATA_ICRC = (1 << 7), /* interface CRC error */
- ATA_UNC = (1 << 6), /* uncorrectable media error */
- ATA_IDNF = (1 << 4), /* ID not found */
- ATA_ABORTED = (1 << 2), /* command aborted */
-
- /* ATA command block registers */
- ATA_REG_DATA = 0x00,
- ATA_REG_ERR = 0x01,
- ATA_REG_NSECT = 0x02,
- ATA_REG_LBAL = 0x03,
- ATA_REG_LBAM = 0x04,
- ATA_REG_LBAH = 0x05,
- ATA_REG_DEVICE = 0x06,
- ATA_REG_STATUS = 0x07,
-
- ATA_REG_FEATURE = ATA_REG_ERR, /* and their aliases */
- ATA_REG_CMD = ATA_REG_STATUS,
- ATA_REG_BYTEL = ATA_REG_LBAM,
- ATA_REG_BYTEH = ATA_REG_LBAH,
- ATA_REG_DEVSEL = ATA_REG_DEVICE,
- ATA_REG_IRQ = ATA_REG_NSECT,
-
- /* ATA device commands */
- ATA_CMD_DEV_RESET = 0x08, /* ATAPI device reset */
- ATA_CMD_CHK_POWER = 0xE5, /* check power mode */
- ATA_CMD_STANDBY = 0xE2, /* place in standby power mode */
- ATA_CMD_IDLE = 0xE3, /* place in idle power mode */
- ATA_CMD_EDD = 0x90, /* execute device diagnostic */
- ATA_CMD_FLUSH = 0xE7,
- ATA_CMD_FLUSH_EXT = 0xEA,
- ATA_CMD_ID_ATA = 0xEC,
- ATA_CMD_ID_ATAPI = 0xA1,
- ATA_CMD_READ = 0xC8,
- ATA_CMD_READ_EXT = 0x25,
- ATA_CMD_WRITE = 0xCA,
- ATA_CMD_WRITE_EXT = 0x35,
- ATA_CMD_WRITE_FUA_EXT = 0x3D,
- ATA_CMD_FPDMA_READ = 0x60,
- ATA_CMD_FPDMA_WRITE = 0x61,
- ATA_CMD_PIO_READ = 0x20,
- ATA_CMD_PIO_READ_EXT = 0x24,
- ATA_CMD_PIO_WRITE = 0x30,
- ATA_CMD_PIO_WRITE_EXT = 0x34,
- ATA_CMD_READ_MULTI = 0xC4,
- ATA_CMD_READ_MULTI_EXT = 0x29,
- ATA_CMD_WRITE_MULTI = 0xC5,
- ATA_CMD_WRITE_MULTI_EXT = 0x39,
- ATA_CMD_WRITE_MULTI_FUA_EXT = 0xCE,
- ATA_CMD_SET_FEATURES = 0xEF,
- ATA_CMD_SET_MULTI = 0xC6,
- ATA_CMD_PACKET = 0xA0,
- ATA_CMD_VERIFY = 0x40,
- ATA_CMD_VERIFY_EXT = 0x42,
- ATA_CMD_STANDBYNOW1 = 0xE0,
- ATA_CMD_IDLEIMMEDIATE = 0xE1,
- ATA_CMD_SLEEP = 0xE6,
- ATA_CMD_INIT_DEV_PARAMS = 0x91,
- ATA_CMD_READ_NATIVE_MAX = 0xF8,
- ATA_CMD_READ_NATIVE_MAX_EXT = 0x27,
- ATA_CMD_SET_MAX = 0xF9,
- ATA_CMD_SET_MAX_EXT = 0x37,
- ATA_CMD_READ_LOG_EXT = 0x2f,
- ATA_CMD_PMP_READ = 0xE4,
- ATA_CMD_PMP_WRITE = 0xE8,
- ATA_CMD_CONF_OVERLAY = 0xB1,
- ATA_CMD_SEC_FREEZE_LOCK = 0xF5,
-
- /* READ_LOG_EXT pages */
- ATA_LOG_SATA_NCQ = 0x10,
-
- /* READ/WRITE LONG (obsolete) */
- ATA_CMD_READ_LONG = 0x22,
- ATA_CMD_READ_LONG_ONCE = 0x23,
- ATA_CMD_WRITE_LONG = 0x32,
- ATA_CMD_WRITE_LONG_ONCE = 0x33,
-
- /* SETFEATURES stuff */
- SETFEATURES_XFER = 0x03,
- XFER_UDMA_7 = 0x47,
- XFER_UDMA_6 = 0x46,
- XFER_UDMA_5 = 0x45,
- XFER_UDMA_4 = 0x44,
- XFER_UDMA_3 = 0x43,
- XFER_UDMA_2 = 0x42,
- XFER_UDMA_1 = 0x41,
- XFER_UDMA_0 = 0x40,
- XFER_MW_DMA_4 = 0x24, /* CFA only */
- XFER_MW_DMA_3 = 0x23, /* CFA only */
- XFER_MW_DMA_2 = 0x22,
- XFER_MW_DMA_1 = 0x21,
- XFER_MW_DMA_0 = 0x20,
- XFER_SW_DMA_2 = 0x12,
- XFER_SW_DMA_1 = 0x11,
- XFER_SW_DMA_0 = 0x10,
- XFER_PIO_6 = 0x0E, /* CFA only */
- XFER_PIO_5 = 0x0D, /* CFA only */
- XFER_PIO_4 = 0x0C,
- XFER_PIO_3 = 0x0B,
- XFER_PIO_2 = 0x0A,
- XFER_PIO_1 = 0x09,
- XFER_PIO_0 = 0x08,
- XFER_PIO_SLOW = 0x00,
-
- SETFEATURES_WC_ON = 0x02, /* Enable write cache */
- SETFEATURES_WC_OFF = 0x82, /* Disable write cache */
-
- SETFEATURES_SPINUP = 0x07, /* Spin-up drive */
-
- SETFEATURES_SATA_ENABLE = 0x10, /* Enable use of SATA feature */
- SETFEATURES_SATA_DISABLE = 0x90, /* Disable use of SATA feature */
-
- /* SETFEATURE Sector counts for SATA features */
- SATA_AN = 0x05, /* Asynchronous Notification */
- SATA_DIPM = 0x03, /* Device Initiated Power Management */
-
- /* feature values for SET_MAX */
- ATA_SET_MAX_ADDR = 0x00,
- ATA_SET_MAX_PASSWD = 0x01,
- ATA_SET_MAX_LOCK = 0x02,
- ATA_SET_MAX_UNLOCK = 0x03,
- ATA_SET_MAX_FREEZE_LOCK = 0x04,
-
- /* feature values for DEVICE CONFIGURATION OVERLAY */
- ATA_DCO_RESTORE = 0xC0,
- ATA_DCO_FREEZE_LOCK = 0xC1,
- ATA_DCO_IDENTIFY = 0xC2,
- ATA_DCO_SET = 0xC3,
-
- /* ATAPI stuff */
- ATAPI_PKT_DMA = (1 << 0),
- ATAPI_DMADIR = (1 << 2), /* ATAPI data dir:
- 0=to device, 1=to host */
- ATAPI_CDB_LEN = 16,
-
- /* PMP stuff */
- SATA_PMP_MAX_PORTS = 15,
- SATA_PMP_CTRL_PORT = 15,
-
- SATA_PMP_GSCR_DWORDS = 128,
- SATA_PMP_GSCR_PROD_ID = 0,
- SATA_PMP_GSCR_REV = 1,
- SATA_PMP_GSCR_PORT_INFO = 2,
- SATA_PMP_GSCR_ERROR = 32,
- SATA_PMP_GSCR_ERROR_EN = 33,
- SATA_PMP_GSCR_FEAT = 64,
- SATA_PMP_GSCR_FEAT_EN = 96,
-
- SATA_PMP_PSCR_STATUS = 0,
- SATA_PMP_PSCR_ERROR = 1,
- SATA_PMP_PSCR_CONTROL = 2,
-
- SATA_PMP_FEAT_BIST = (1 << 0),
- SATA_PMP_FEAT_PMREQ = (1 << 1),
- SATA_PMP_FEAT_DYNSSC = (1 << 2),
- SATA_PMP_FEAT_NOTIFY = (1 << 3),
-
- /* cable types */
- ATA_CBL_NONE = 0,
- ATA_CBL_PATA40 = 1,
- ATA_CBL_PATA80 = 2,
- ATA_CBL_PATA40_SHORT = 3, /* 40 wire cable to high UDMA spec */
- ATA_CBL_PATA_UNK = 4, /* don't know, maybe 80c? */
- ATA_CBL_PATA_IGN = 5, /* don't know, ignore cable handling */
- ATA_CBL_SATA = 6,
-
- /* SATA Status and Control Registers */
- SCR_STATUS = 0,
- SCR_ERROR = 1,
- SCR_CONTROL = 2,
- SCR_ACTIVE = 3,
- SCR_NOTIFICATION = 4,
-
- /* SError bits */
- SERR_DATA_RECOVERED = (1 << 0), /* recovered data error */
- SERR_COMM_RECOVERED = (1 << 1), /* recovered comm failure */
- SERR_DATA = (1 << 8), /* unrecovered data error */
- SERR_PERSISTENT = (1 << 9), /* persistent data/comm error */
- SERR_PROTOCOL = (1 << 10), /* protocol violation */
- SERR_INTERNAL = (1 << 11), /* host internal error */
- SERR_PHYRDY_CHG = (1 << 16), /* PHY RDY changed */
- SERR_PHY_INT_ERR = (1 << 17), /* PHY internal error */
- SERR_COMM_WAKE = (1 << 18), /* Comm wake */
- SERR_10B_8B_ERR = (1 << 19), /* 10b to 8b decode error */
- SERR_DISPARITY = (1 << 20), /* Disparity */
- SERR_CRC = (1 << 21), /* CRC error */
- SERR_HANDSHAKE = (1 << 22), /* Handshake error */
- SERR_LINK_SEQ_ERR = (1 << 23), /* Link sequence error */
- SERR_TRANS_ST_ERROR = (1 << 24), /* Transport state trans. error */
- SERR_UNRECOG_FIS = (1 << 25), /* Unrecognized FIS */
- SERR_DEV_XCHG = (1 << 26), /* device exchanged */
-
- /* struct ata_taskfile flags */
- ATA_TFLAG_LBA48 = (1 << 0), /* enable 48-bit LBA and "HOB" */
- ATA_TFLAG_ISADDR = (1 << 1), /* enable r/w to nsect/lba regs */
- ATA_TFLAG_DEVICE = (1 << 2), /* enable r/w to device reg */
- ATA_TFLAG_WRITE = (1 << 3), /* data dir: host->dev==1 (write) */
- ATA_TFLAG_LBA = (1 << 4), /* enable LBA */
- ATA_TFLAG_FUA = (1 << 5), /* enable FUA */
- ATA_TFLAG_POLLING = (1 << 6), /* set nIEN to 1 and use polling */
-
- /* protocol flags */
- ATA_PROT_FLAG_PIO = (1 << 0), /* is PIO */
- ATA_PROT_FLAG_DMA = (1 << 1), /* is DMA */
- ATA_PROT_FLAG_DATA = ATA_PROT_FLAG_PIO | ATA_PROT_FLAG_DMA,
- ATA_PROT_FLAG_NCQ = (1 << 2), /* is NCQ */
- ATA_PROT_FLAG_ATAPI = (1 << 3), /* is ATAPI */
-};
-
-enum ata_tf_protocols {
- /* ATA taskfile protocols */
- ATA_PROT_UNKNOWN, /* unknown/invalid */
- ATA_PROT_NODATA, /* no data */
- ATA_PROT_PIO, /* PIO data xfer */
- ATA_PROT_DMA, /* DMA */
- ATA_PROT_NCQ, /* NCQ */
- ATAPI_PROT_NODATA, /* packet command, no data */
- ATAPI_PROT_PIO, /* packet command, PIO data xfer*/
- ATAPI_PROT_DMA, /* packet command with special DMA sauce */
-};
-
-enum ata_ioctls {
- ATA_IOC_GET_IO32 = 0x309,
- ATA_IOC_SET_IO32 = 0x324,
-};
-
-enum ata_dev_typed {
- ATA_DEV_ATA, /* ATA device */
- ATA_DEV_ATAPI, /* ATAPI device */
- ATA_DEV_PMP, /* Port Multiplier Port */
- ATA_DEV_UNKNOWN, /* unknown */
-};
-
-struct ata_taskfile {
- unsigned long flags; /* ATA_TFLAG_xxx */
- u8 protocol; /* ATA_PROT_xxx */
-
- u8 ctl; /* control reg */
-
- u8 hob_feature; /* additional data */
- u8 hob_nsect; /* to support LBA48 */
- u8 hob_lbal;
- u8 hob_lbam;
- u8 hob_lbah;
-
- u8 feature;
- u8 nsect;
- u8 lbal;
- u8 lbam;
- u8 lbah;
-
- u8 device;
-
- u8 command; /* IO operation */
-};
-
-/*
- * protocol tests
- */
-static inline unsigned int ata_prot_flags(u8 prot)
-{
- switch (prot) {
- case ATA_PROT_NODATA:
- return 0;
- case ATA_PROT_PIO:
- return ATA_PROT_FLAG_PIO;
- case ATA_PROT_DMA:
- return ATA_PROT_FLAG_DMA;
- case ATA_PROT_NCQ:
- return ATA_PROT_FLAG_DMA | ATA_PROT_FLAG_NCQ;
- case ATAPI_PROT_NODATA:
- return ATA_PROT_FLAG_ATAPI;
- case ATAPI_PROT_PIO:
- return ATA_PROT_FLAG_ATAPI | ATA_PROT_FLAG_PIO;
- case ATAPI_PROT_DMA:
- return ATA_PROT_FLAG_ATAPI | ATA_PROT_FLAG_DMA;
- }
- return 0;
-}
-
-static inline int ata_is_atapi(u8 prot)
-{
- return ata_prot_flags(prot) & ATA_PROT_FLAG_ATAPI;
-}
-
-static inline int ata_is_nodata(u8 prot)
-{
- return !(ata_prot_flags(prot) & ATA_PROT_FLAG_DATA);
-}
-
-static inline int ata_is_pio(u8 prot)
-{
- return ata_prot_flags(prot) & ATA_PROT_FLAG_PIO;
-}
-
-static inline int ata_is_dma(u8 prot)
-{
- return ata_prot_flags(prot) & ATA_PROT_FLAG_DMA;
-}
-
-static inline int ata_is_ncq(u8 prot)
-{
- return ata_prot_flags(prot) & ATA_PROT_FLAG_NCQ;
-}
-
-static inline int ata_is_data(u8 prot)
-{
- return ata_prot_flags(prot) & ATA_PROT_FLAG_DATA;
-}
-
-/*
- * id tests
- */
-#define ata_id_is_ata(id) (((id)[0] & (1 << 15)) == 0)
-#define ata_id_has_lba(id) ((id)[49] & (1 << 9))
-#define ata_id_has_dma(id) ((id)[49] & (1 << 8))
-#define ata_id_has_ncq(id) ((id)[76] & (1 << 8))
-#define ata_id_queue_depth(id) (((id)[75] & 0x1f) + 1)
-#define ata_id_removeable(id) ((id)[0] & (1 << 7))
-#define ata_id_iordy_disable(id) ((id)[49] & (1 << 10))
-#define ata_id_has_iordy(id) ((id)[49] & (1 << 11))
-
-#define ata_id_u32(id,n) \
- (((u32) (id)[(n) + 1] << 16) | ((u32) (id)[(n)]))
-#define ata_id_u64(id,n) \
- ( ((u64) (id)[(n) + 3] << 48) | \
- ((u64) (id)[(n) + 2] << 32) | \
- ((u64) (id)[(n) + 1] << 16) | \
- ((u64) (id)[(n) + 0]) )
-
-#define ata_id_cdb_intr(id) (((id)[0] & 0x60) == 0x20)
-
-static inline int ata_id_has_fua(const u16 *id)
-{
- if ((id[84] & 0xC000) != 0x4000)
- return 0;
- return id[84] & (1 << 6);
-}
-
-static inline int ata_id_has_flush(const u16 *id)
-{
- if ((id[83] & 0xC000) != 0x4000)
- return 0;
- return id[83] & (1 << 12);
-}
-
-static inline int ata_id_has_flush_ext(const u16 *id)
-{
- if ((id[83] & 0xC000) != 0x4000)
- return 0;
- return id[83] & (1 << 13);
-}
-
-static inline int ata_id_has_lba48(const u16 *id)
-{
- if ((id[83] & 0xC000) != 0x4000)
- return 0;
- if (!ata_id_u64(id, 100))
- return 0;
- return id[83] & (1 << 10);
-}
-
-static inline int ata_id_hpa_enabled(const u16 *id)
-{
- /* Yes children, word 83 valid bits cover word 82 data */
- if ((id[83] & 0xC000) != 0x4000)
- return 0;
- /* And 87 covers 85-87 */
- if ((id[87] & 0xC000) != 0x4000)
- return 0;
- /* Check command sets enabled as well as supported */
- if ((id[85] & ( 1 << 10)) == 0)
- return 0;
- return id[82] & (1 << 10);
-}
-
-static inline int ata_id_has_wcache(const u16 *id)
-{
- /* Yes children, word 83 valid bits cover word 82 data */
- if ((id[83] & 0xC000) != 0x4000)
- return 0;
- return id[82] & (1 << 5);
-}
-
-static inline int ata_id_has_pm(const u16 *id)
-{
- if ((id[83] & 0xC000) != 0x4000)
- return 0;
- return id[82] & (1 << 3);
-}
-
-static inline int ata_id_rahead_enabled(const u16 *id)
-{
- if ((id[87] & 0xC000) != 0x4000)
- return 0;
- return id[85] & (1 << 6);
-}
-
-static inline int ata_id_wcache_enabled(const u16 *id)
-{
- if ((id[87] & 0xC000) != 0x4000)
- return 0;
- return id[85] & (1 << 5);
-}
-
-static inline unsigned int ata_id_major_version(const u16 *id)
-{
- unsigned int mver;
-
- if (id[ATA_ID_MAJOR_VER] == 0xFFFF)
- return 0;
-
- for (mver = 14; mver >= 1; mver--)
- if (id[ATA_ID_MAJOR_VER] & (1 << mver))
- break;
- return mver;
-}
-
-static inline int ata_id_is_sata(const u16 *id)
-{
- return ata_id_major_version(id) >= 5 && id[93] == 0;
-}
-
-static inline int ata_id_has_tpm(const u16 *id)
-{
- /* The TPM bits are only valid on ATA8 */
- if (ata_id_major_version(id) < 8)
- return 0;
- if ((id[48] & 0xC000) != 0x4000)
- return 0;
- return id[48] & (1 << 0);
-}
-
-static inline int ata_id_has_dword_io(const u16 *id)
-{
- /* ATA 8 reuses this flag for "trusted" computing */
- if (ata_id_major_version(id) > 7)
- return 0;
- if (id[48] & (1 << 0))
- return 1;
- return 0;
-}
-
-static inline int ata_id_current_chs_valid(const u16 *id)
-{
- /* For ATA-1 devices, if the INITIALIZE DEVICE PARAMETERS command
- has not been issued to the device then the values of
- id[54] to id[56] are vendor specific. */
- return (id[53] & 0x01) && /* Current translation valid */
- id[54] && /* cylinders in current translation */
- id[55] && /* heads in current translation */
- id[55] <= 16 &&
- id[56]; /* sectors in current translation */
-}
-
-static inline int ata_id_is_cfa(const u16 *id)
-{
- u16 v = id[0];
- if (v == 0x848A) /* Standard CF */
- return 1;
- /* Could be CF hiding as standard ATA */
- if (ata_id_major_version(id) >= 3 && id[82] != 0xFFFF &&
- (id[82] & ( 1 << 2)))
- return 1;
- return 0;
-}
-
-static inline int ata_drive_40wire(const u16 *dev_id)
-{
- if (ata_id_is_sata(dev_id))
- return 0; /* SATA */
- if ((dev_id[93] & 0xE000) == 0x6000)
- return 0; /* 80 wire */
- return 1;
-}
-
-static inline int ata_drive_40wire_relaxed(const u16 *dev_id)
-{
- if ((dev_id[93] & 0x2000) == 0x2000)
- return 0; /* 80 wire */
- return 1;
-}
-
-static inline int atapi_cdb_len(const u16 *dev_id)
-{
- u16 tmp = dev_id[0] & 0x3;
- switch (tmp) {
- case 0: return 12;
- case 1: return 16;
- default: return -1;
- }
-}
-
-static inline int atapi_command_packet_set(const u16 *dev_id)
-{
- return (dev_id[0] >> 8) & 0x1f;
-}
-
-static inline int atapi_id_dmadir(const u16 *dev_id)
-{
- return ata_id_major_version(dev_id) >= 7 && (dev_id[62] & 0x8000);
-}
-
-static inline int is_multi_taskfile(struct ata_taskfile *tf)
-{
- return (tf->command == ATA_CMD_READ_MULTI) ||
- (tf->command == ATA_CMD_WRITE_MULTI) ||
- (tf->command == ATA_CMD_READ_MULTI_EXT) ||
- (tf->command == ATA_CMD_WRITE_MULTI_EXT) ||
- (tf->command == ATA_CMD_WRITE_MULTI_FUA_EXT);
-}
-
-static inline int ata_ok(u8 status)
-{
- return ((status & (ATA_BUSY | ATA_DRDY | ATA_DF | ATA_DRQ | ATA_ERR))
- == ATA_DRDY);
-}
-
-static inline int lba_28_ok(u64 block, u32 n_block)
-{
- /* check the ending block number */
- return ((block + n_block - 1) < ((u64)1 << 28)) && (n_block <= 256);
-}
-
-static inline int lba_48_ok(u64 block, u32 n_block)
-{
- /* check the ending block number */
- return ((block + n_block - 1) < ((u64)1 << 48)) && (n_block <= 65536);
-}
-
-#define sata_pmp_gscr_vendor(gscr) ((gscr)[SATA_PMP_GSCR_PROD_ID] & 0xffff)
-#define sata_pmp_gscr_devid(gscr) ((gscr)[SATA_PMP_GSCR_PROD_ID] >> 16)
-#define sata_pmp_gscr_rev(gscr) (((gscr)[SATA_PMP_GSCR_REV] >> 8) & 0xff)
-#define sata_pmp_gscr_ports(gscr) ((gscr)[SATA_PMP_GSCR_PORT_INFO] & 0xf)
-
-u64 ata_id_n_sectors(u16 *id);
-u32 ata_dev_classify(u32 sig);
-void ata_id_c_string(const u16 *id, unsigned char *s,
- unsigned int ofs, unsigned int len);
-void ata_dump_id(u16 *id);
-void ata_swap_buf_le16(u16 *buf, unsigned int buf_words);
-
-#endif /* __LIBATA_H__ */
+++ /dev/null
-/***********************************************************************
- *
- * Copyright (C) 2004 by FS Forth-Systeme GmbH.
- * All rights reserved.
- *
- * $Id: ns9750_eth.h,v 1.2 2004/02/24 13:25:39 mpietrek Exp $
- * @Author: Markus Pietrek
- * @References: [1] NS9750 Hardware Reference, December 2003
- * [2] Intel LXT971 Datasheet #249414 Rev. 02
- * [3] NS7520 Linux Ethernet Driver
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- ***********************************************************************/
-
-#ifndef __LXT971A_H__
-#define __LXT971A_H__
-
-/* PHY definitions (LXT971A) [2] */
-#define PHY_LXT971_PORT_CFG (0x10)
-#define PHY_LXT971_STAT2 (0x11)
-#define PHY_LXT971_INT_ENABLE (0x12)
-#define PHY_LXT971_INT_STATUS (0x13)
-#define PHY_LXT971_LED_CFG (0x14)
-#define PHY_LXT971_DIG_CFG (0x1A)
-#define PHY_LXT971_TX_CTRL (0x1E)
-
-/* PORT_CFG Port Configuration Register Bit Fields */
-#define PHY_LXT971_PORT_CFG_RES1 (0x8000)
-#define PHY_LXT971_PORT_CFG_FORCE_LNK (0x4000)
-#define PHY_LXT971_PORT_CFG_TX_DISABLE (0x2000)
-#define PHY_LXT971_PORT_CFG_BYPASS_SCR (0x1000)
-#define PHY_LXT971_PORT_CFG_RES2 (0x0800)
-#define PHY_LXT971_PORT_CFG_JABBER (0x0400)
-#define PHY_LXT971_PORT_CFG_SQE (0x0200)
-#define PHY_LXT971_PORT_CFG_TP_LOOPBACK (0x0100)
-#define PHY_LXT971_PORT_CFG_CRS_SEL (0x0080)
-#define PHY_LXT971_PORT_CFG_SLEEP_MODE (0x0040)
-#define PHY_LXT971_PORT_CFG_PRE_EN (0x0020)
-#define PHY_LXT971_PORT_CFG_SLEEP_T_MA (0x0018)
-#define PHY_LXT971_PORT_CFG_SLEEP_T_104 (0x0010)
-#define PHY_LXT971_PORT_CFG_SLEEP_T_200 (0x0001)
-#define PHY_LXT971_PORT_CFG_SLEEP_T_304 (0x0000)
-#define PHY_LXT971_PORT_CFG_FLT_CODE_EN (0x0004)
-#define PHY_LXT971_PORT_CFG_ALT_NP (0x0002)
-#define PHY_LXT971_PORT_CFG_FIBER_SEL (0x0001)
-
-/* STAT2 Status Register #2 Bit Fields */
-#define PHY_LXT971_STAT2_RES1 (0x8000)
-#define PHY_LXT971_STAT2_100BTX (0x4000)
-#define PHY_LXT971_STAT2_TX_STATUS (0x2000)
-#define PHY_LXT971_STAT2_RX_STATUS (0x1000)
-#define PHY_LXT971_STAT2_COL_STATUS (0x0800)
-#define PHY_LXT971_STAT2_LINK (0x0400)
-#define PHY_LXT971_STAT2_DUPLEX_MODE (0x0200)
-#define PHY_LXT971_STAT2_AUTO_NEG (0x0100)
-#define PHY_LXT971_STAT2_AUTO_NEG_COMP (0x0080)
-#define PHY_LXT971_STAT2_RES2 (0x0040)
-#define PHY_LXT971_STAT2_POLARITY (0x0020)
-#define PHY_LXT971_STAT2_PAUSE (0x0010)
-#define PHY_LXT971_STAT2_ERROR (0x0008)
-#define PHY_LXT971_STAT2_RES3 (0x0007)
-
-/* INT_ENABLE Interrupt Enable Register Bit Fields */
-#define PHY_LXT971_INT_ENABLE_RES1 (0xFF00)
-#define PHY_LXT971_INT_ENABLE_ANMSK (0x0080)
-#define PHY_LXT971_INT_ENABLE_SPEEDMSK (0x0040)
-#define PHY_LXT971_INT_ENABLE_DUPLEXMSK (0x0020)
-#define PHY_LXT971_INT_ENABLE_LINKMSK (0x0010)
-#define PHY_LXT971_INT_ENABLE_RES2 (0x000C)
-#define PHY_LXT971_INT_ENABLE_INTEN (0x0002)
-#define PHY_LXT971_INT_ENABLE_TINT (0x0001)
-
-/* INT_STATUS Interrupt Status Register Bit Fields */
-#define PHY_LXT971_INT_STATUS_RES1 (0xFF00)
-#define PHY_LXT971_INT_STATUS_ANDONE (0x0080)
-#define PHY_LXT971_INT_STATUS_SPEEDCHG (0x0040)
-#define PHY_LXT971_INT_STATUS_DUPLEXCHG (0x0020)
-#define PHY_LXT971_INT_STATUS_LINKCHG (0x0010)
-#define PHY_LXT971_INT_STATUS_RES2 (0x0008)
-#define PHY_LXT971_INT_STATUS_MDINT (0x0004)
-#define PHY_LXT971_INT_STATUS_RES3 (0x0003)
-
-/* LED_CFG Interrupt LED Configuration Register Bit Fields */
-#define PHY_LXT971_LED_CFG_SHIFT_LED1 (0x000C)
-#define PHY_LXT971_LED_CFG_SHIFT_LED2 (0x0008)
-#define PHY_LXT971_LED_CFG_SHIFT_LED3 (0x0004)
-#define PHY_LXT971_LED_CFG_LEDFREQ_MA (0x000C)
-#define PHY_LXT971_LED_CFG_LEDFREQ_RES (0x000C)
-#define PHY_LXT971_LED_CFG_LEDFREQ_100 (0x0008)
-#define PHY_LXT971_LED_CFG_LEDFREQ_60 (0x0004)
-#define PHY_LXT971_LED_CFG_LEDFREQ_30 (0x0000)
-#define PHY_LXT971_LED_CFG_PULSE_STR (0x0002)
-#define PHY_LXT971_LED_CFG_RES1 (0x0001)
-
-/* only one of these values must be shifted for each SHIFT_LED? */
-#define PHY_LXT971_LED_CFG_UNUSED1 (0x000F)
-#define PHY_LXT971_LED_CFG_DUPLEX_COL (0x000E)
-#define PHY_LXT971_LED_CFG_LINK_ACT (0x000D)
-#define PHY_LXT971_LED_CFG_LINK_RX (0x000C)
-#define PHY_LXT971_LED_CFG_TEST_BLK_SLW (0x000B)
-#define PHY_LXT971_LED_CFG_TEST_BLK_FST (0x000A)
-#define PHY_LXT971_LED_CFG_TEST_OFF (0x0009)
-#define PHY_LXT971_LED_CFG_TEST_ON (0x0008)
-#define PHY_LXT971_LED_CFG_RX_OR_TX (0x0007)
-#define PHY_LXT971_LED_CFG_UNUSED2 (0x0006)
-#define PHY_LXT971_LED_CFG_DUPLEX (0x0005)
-#define PHY_LXT971_LED_CFG_LINK (0x0004)
-#define PHY_LXT971_LED_CFG_COLLISION (0x0003)
-#define PHY_LXT971_LED_CFG_RECEIVE (0x0002)
-#define PHY_LXT971_LED_CFG_TRANSMIT (0x0001)
-#define PHY_LXT971_LED_CFG_SPEED (0x0000)
-
-/* DIG_CFG Digitial Configuration Register Bit Fields */
-#define PHY_LXT971_DIG_CFG_RES1 (0xF000)
-#define PHY_LXT971_DIG_CFG_MII_DRIVE (0x0800)
-#define PHY_LXT971_DIG_CFG_RES2 (0x0400)
-#define PHY_LXT971_DIG_CFG_SHOW_SYMBOL (0x0200)
-#define PHY_LXT971_DIG_CFG_RES3 (0x01FF)
-
-#define PHY_LXT971_MDIO_MAX_CLK (8000000)
-#define PHY_MDIO_MAX_CLK (2500000)
-
-/* TX_CTRL Transmit Control Register Bit Fields
- documentation is buggy for this register, therefore setting not included */
-
-typedef enum
-{
- PHY_NONE = 0x0000, /* no PHY detected yet */
- PHY_LXT971A = 0x0013
-} PhyType;
-
-#endif /* __LXT971A_H__ */
+++ /dev/null
-/***********************************************************************
- *
- * Copyright 2003 by FS Forth-Systeme GmbH.
- * All rights reserved.
- *
- * $Id$
- * @Author: Markus Pietrek
- * @Descr: Defines the NS7520 ethernet registers.
- * Stick with the old ETH prefix names instead going to the
- * new EFE names in the manual.
- * NS7520_ETH_* refer to NS7520 Hardware
- * Reference/January 2003 [1]
- * PHY_LXT971_* refer to Intel LXT971 Datasheet
- * #249414 Rev. 02 [2]
- * Partly derived from netarm_eth_module.h
- *
- * Modified by Arthur Shipkowski <art@videon-central.com> from the
- * Linux version to be properly formatted for U-Boot (i.e. no C++ comments)
- *
- ***********************************************************************/
-
-#ifndef FS_NS7520_ETH_H
-#define FS_NS7520_ETH_H
-
-#ifdef CONFIG_DRIVER_NS7520_ETHERNET
-
-#include <miiphy.h>
-#include "lxt971a.h"
-
-/* The port addresses */
-
-#define NS7520_ETH_MODULE_BASE (0xFF800000)
-
-#define get_eth_reg_addr(c) \
- ((volatile unsigned int*) ( NS7520_ETH_MODULE_BASE+(unsigned int) (c)))
-#define NS7520_ETH_EGCR (0x0000) /* Ethernet Gen Control */
-#define NS7520_ETH_EGSR (0x0004) /* Ethernet Gen Status */
-#define NS7520_ETH_FIFO (0x0008) /* FIFO Data */
-#define NS7520_ETH_FIFOL (0x000C) /* FIFO Data Last */
-#define NS7520_ETH_ETSR (0x0010) /* Ethernet Transmit Status */
-#define NS7520_ETH_ERSR (0x0014) /* Ethernet Receive Status */
-#define NS7520_ETH_MAC1 (0x0400) /* MAC Config 1 */
-#define NS7520_ETH_MAC2 (0x0404) /* MAC Config 2 */
-#define NS7520_ETH_IPGT (0x0408) /* Back2Back InterPacket Gap */
-#define NS7520_ETH_IPGR (0x040C) /* non back2back InterPacket Gap */
-#define NS7520_ETH_CLRT (0x0410) /* Collision Window/Retry */
-#define NS7520_ETH_MAXF (0x0414) /* Maximum Frame Register */
-#define NS7520_ETH_SUPP (0x0418) /* PHY Support */
-#define NS7520_ETH_TEST (0x041C) /* Test Register */
-#define NS7520_ETH_MCFG (0x0420) /* MII Management Configuration */
-#define NS7520_ETH_MCMD (0x0424) /* MII Management Command */
-#define NS7520_ETH_MADR (0x0428) /* MII Management Address */
-#define NS7520_ETH_MWTD (0x042C) /* MII Management Write Data */
-#define NS7520_ETH_MRDD (0x0430) /* MII Management Read Data */
-#define NS7520_ETH_MIND (0x0434) /* MII Management Indicators */
-#define NS7520_ETH_SMII (0x0438) /* SMII Status Register */
-#define NS7520_ETH_SA1 (0x0440) /* Station Address 1 */
-#define NS7520_ETH_SA2 (0x0444) /* Station Address 2 */
-#define NS7520_ETH_SA3 (0x0448) /* Station Address 3 */
-#define NS7520_ETH_SAFR (0x05C0) /* Station Address Filter */
-#define NS7520_ETH_HT1 (0x05D0) /* Hash Table 1 */
-#define NS7520_ETH_HT2 (0x05D4) /* Hash Table 2 */
-#define NS7520_ETH_HT3 (0x05D8) /* Hash Table 3 */
-#define NS7520_ETH_HT4 (0x05DC) /* Hash Table 4 */
-
-/* EGCR Ethernet General Control Register Bit Fields*/
-
-#define NS7520_ETH_EGCR_ERX (0x80000000) /* Enable Receive FIFO */
-#define NS7520_ETH_EGCR_ERXDMA (0x40000000) /* Enable Receive DMA */
-#define NS7520_ETH_EGCR_ERXLNG (0x20000000) /* Accept Long packets */
-#define NS7520_ETH_EGCR_ERXSHT (0x10000000) /* Accept Short packets */
-#define NS7520_ETH_EGCR_ERXREG (0x08000000) /* Enable Receive Data Interrupt */
-#define NS7520_ETH_EGCR_ERFIFOH (0x04000000) /* Enable Receive Half-Full Int */
-#define NS7520_ETH_EGCR_ERXBR (0x02000000) /* Enable Receive buffer ready */
-#define NS7520_ETH_EGCR_ERXBAD (0x01000000) /* Accept bad receive packets */
-#define NS7520_ETH_EGCR_ETX (0x00800000) /* Enable Transmit FIFO */
-#define NS7520_ETH_EGCR_ETXDMA (0x00400000) /* Enable Transmit DMA */
-#define NS7520_ETH_EGCR_ETXWM_R (0x00300000) /* Enable Transmit FIFO mark Reserv */
-#define NS7520_ETH_EGCR_ETXWM_75 (0x00200000) /* Enable Transmit FIFO mark 75% */
-#define NS7520_ETH_EGCR_ETXWM_50 (0x00100000) /* Enable Transmit FIFO mark 50% */
-#define NS7520_ETH_EGCR_ETXWM_25 (0x00000000) /* Enable Transmit FIFO mark 25% */
-#define NS7520_ETH_EGCR_ETXREG (0x00080000) /* Enable Transmit Data Read Int */
-#define NS7520_ETH_EGCR_ETFIFOH (0x00040000) /* Enable Transmit Fifo Half Int */
-#define NS7520_ETH_EGCR_ETXBC (0x00020000) /* Enable Transmit Buffer Compl Int */
-#define NS7520_ETH_EGCR_EFULLD (0x00010000) /* Enable Full Duplex Operation */
-#define NS7520_ETH_EGCR_MODE_MA (0x0000C000) /* Mask */
-#define NS7520_ETH_EGCR_MODE_SEE (0x0000C000) /* 10 Mbps SEEQ ENDEC PHY */
-#define NS7520_ETH_EGCR_MODE_LEV (0x00008000) /* 10 Mbps Level1 ENDEC PHY */
-#define NS7520_ETH_EGCR_RES1 (0x00002000) /* Reserved */
-#define NS7520_ETH_EGCR_RXCINV (0x00001000) /* Invert the receive clock input */
-#define NS7520_ETH_EGCR_TXCINV (0x00000800) /* Invert the transmit clock input */
-#define NS7520_ETH_EGCR_PNA (0x00000400) /* pSOS pNA buffer */
-#define NS7520_ETH_EGCR_MAC_RES (0x00000200) /* MAC Software reset */
-#define NS7520_ETH_EGCR_ITXA (0x00000100) /* Insert Transmit Source Address */
-#define NS7520_ETH_EGCR_ENDEC_MA (0x000000FC) /* ENDEC media control bits */
-#define NS7520_ETH_EGCR_EXINT_MA (0x00000003) /* Mask */
-#define NS7520_ETH_EGCR_EXINT_RE (0x00000003) /* Reserved */
-#define NS7520_ETH_EGCR_EXINT_TP (0x00000002) /* TP-PMD Mode */
-#define NS7520_ETH_EGCR_EXINT_10 (0x00000001) /* 10-MBit Mode */
-#define NS7520_ETH_EGCR_EXINT_NO (0x00000000) /* MII normal operation */
-
-/* EGSR Ethernet General Status Register Bit Fields*/
-
-#define NS7520_ETH_EGSR_RES1 (0xC0000000) /* Reserved */
-#define NS7520_ETH_EGSR_RXFDB_MA (0x30000000) /* Receive FIFO mask */
-#define NS7520_ETH_EGSR_RXFDB_3 (0x30000000) /* Receive FIFO 3 bytes available */
-#define NS7520_ETH_EGSR_RXFDB_2 (0x20000000) /* Receive FIFO 2 bytes available */
-#define NS7520_ETH_EGCR_RXFDB_1 (0x10000000) /* Receive FIFO 1 Bytes available */
-#define NS7520_ETH_EGCR_RXFDB_4 (0x00000000) /* Receive FIFO 4 Bytes available */
-#define NS7520_ETH_EGSR_RXREGR (0x08000000) /* Receive Register Ready */
-#define NS7520_ETH_EGSR_RXFIFOH (0x04000000) /* Receive FIFO Half Full */
-#define NS7520_ETH_EGSR_RXBR (0x02000000) /* Receive Buffer Ready */
-#define NS7520_ETH_EGSR_RXSKIP (0x01000000) /* Receive Buffer Skip */
-#define NS7520_ETH_EGSR_RES2 (0x00F00000) /* Reserved */
-#define NS7520_ETH_EGSR_TXREGE (0x00080000) /* Transmit Register Empty */
-#define NS7520_ETH_EGSR_TXFIFOH (0x00040000) /* Transmit FIFO half empty */
-#define NS7520_ETH_EGSR_TXBC (0x00020000) /* Transmit buffer complete */
-#define NS7520_ETH_EGSR_TXFIFOE (0x00010000) /* Transmit FIFO empty */
-#define NS7520_ETH_EGSR_RXPINS (0x0000FC00) /* ENDEC Phy Status */
-#define NS7520_ETH_EGSR_RES3 (0x000003FF) /* Reserved */
-
-/* ETSR Ethernet Transmit Status Register Bit Fields*/
-
-#define NS7520_ETH_ETSR_RES1 (0xFFFF0000) /* Reserved */
-#define NS7520_ETH_ETSR_TXOK (0x00008000) /* Packet transmitted OK */
-#define NS7520_ETH_ETSR_TXBR (0x00004000) /* Broadcast packet transmitted */
-#define NS7520_ETH_ETSR_TXMC (0x00002000) /* Multicast packet transmitted */
-#define NS7520_ETH_ETSR_TXAL (0x00001000) /* Transmit abort - late collision */
-#define NS7520_ETH_ETSR_TXAED (0x00000800) /* Transmit abort - deferral */
-#define NS7520_ETH_ETSR_TXAEC (0x00000400) /* Transmit abort - exc collisions */
-#define NS7520_ETH_ETSR_TXAUR (0x00000200) /* Transmit abort - underrun */
-#define NS7520_ETH_ETSR_TXAJ (0x00000100) /* Transmit abort - jumbo */
-#define NS7520_ETH_ETSR_RES2 (0x00000080) /* Reserved */
-#define NS7520_ETH_ETSR_TXDEF (0x00000040) /* Transmit Packet Deferred */
-#define NS7520_ETH_ETSR_TXCRC (0x00000020) /* Transmit CRC error */
-#define NS7520_ETH_ETSR_RES3 (0x00000010) /* Reserved */
-#define NS7520_ETH_ETSR_TXCOLC (0x0000000F) /* Transmit Collision Count */
-
-/* ERSR Ethernet Receive Status Register Bit Fields*/
-
-#define NS7520_ETH_ERSR_RXSIZE (0xFFFF0000) /* Receive Buffer Size */
-#define NS7520_ETH_ERSR_RXCE (0x00008000) /* Receive Carrier Event */
-#define NS7520_ETH_ERSR_RXDV (0x00004000) /* Receive Data Violation Event */
-#define NS7520_ETH_ERSR_RXOK (0x00002000) /* Receive Packet OK */
-#define NS7520_ETH_ERSR_RXBR (0x00001000) /* Receive Broadcast Packet */
-#define NS7520_ETH_ERSR_RXMC (0x00000800) /* Receive Multicast Packet */
-#define NS7520_ETH_ERSR_RXCRC (0x00000400) /* Receive Packet has CRC error */
-#define NS7520_ETH_ERSR_RXDR (0x00000200) /* Receive Packet has dribble error */
-#define NS7520_ETH_ERSR_RXCV (0x00000100) /* Receive Packet code violation */
-#define NS7520_ETH_ERSR_RXLNG (0x00000080) /* Receive Packet too long */
-#define NS7520_ETH_ERSR_RXSHT (0x00000040) /* Receive Packet too short */
-#define NS7520_ETH_ERSR_ROVER (0x00000020) /* Recive overflow */
-#define NS7520_ETH_ERSR_RES (0x0000001F) /* Reserved */
-
-/* MAC1 MAC Configuration Register 1 Bit Fields*/
-
-#define NS7520_ETH_MAC1_RES1 (0xFFFF0000) /* Reserved */
-#define NS7520_ETH_MAC1_SRST (0x00008000) /* Soft Reset */
-#define NS7520_ETH_MAC1_SIMMRST (0x00004000) /* Simulation Reset */
-#define NS7520_ETH_MAC1_RES2 (0x00003000) /* Reserved */
-#define NS7520_ETH_MAC1_RPEMCSR (0x00000800) /* Reset PEMCS/RX */
-#define NS7520_ETH_MAC1_RPERFUN (0x00000400) /* Reset PERFUN */
-#define NS7520_ETH_MAC1_RPEMCST (0x00000200) /* Reset PEMCS/TX */
-#define NS7520_ETH_MAC1_RPETFUN (0x00000100) /* Reset PETFUN */
-#define NS7520_ETH_MAC1_RES3 (0x000000E0) /* Reserved */
-#define NS7520_ETH_MAC1_LOOPBK (0x00000010) /* Internal Loopback */
-#define NS7520_ETH_MAC1_TXFLOW (0x00000008) /* TX flow control */
-#define NS7520_ETH_MAC1_RXFLOW (0x00000004) /* RX flow control */
-#define NS7520_ETH_MAC1_PALLRX (0x00000002) /* Pass ALL receive frames */
-#define NS7520_ETH_MAC1_RXEN (0x00000001) /* Receive enable */
-
-/* MAC Configuration Register 2 Bit Fields*/
-
-#define NS7520_ETH_MAC2_RES1 (0xFFFF8000) /* Reserved */
-#define NS7520_ETH_MAC2_EDEFER (0x00004000) /* Excess Deferral */
-#define NS7520_ETH_MAC2_BACKP (0x00002000) /* Backpressure/NO back off */
-#define NS7520_ETH_MAC2_NOBO (0x00001000) /* No back off */
-#define NS7520_ETH_MAC2_RES2 (0x00000C00) /* Reserved */
-#define NS7520_ETH_MAC2_LONGP (0x00000200) /* Long Preable enforcement */
-#define NS7520_ETH_MAC2_PUREP (0x00000100) /* Pure preamble enforcement */
-#define NS7520_ETH_MAC2_AUTOP (0x00000080) /* Auto detect PAD enable */
-#define NS7520_ETH_MAC2_VLANP (0x00000040) /* VLAN pad enable */
-#define NS7520_ETH_MAC2_PADEN (0x00000020) /* PAD/CRC enable */
-#define NS7520_ETH_MAC2_CRCEN (0x00000010) /* CRC enable */
-#define NS7520_ETH_MAC2_DELCRC (0x00000008) /* Delayed CRC */
-#define NS7520_ETH_MAC2_HUGE (0x00000004) /* Huge frame enable */
-#define NS7520_ETH_MAC2_FLENC (0x00000002) /* Frame length checking */
-#define NS7520_ETH_MAC2_FULLD (0x00000001) /* Full duplex */
-
-/* IPGT Back-to-Back Inter-Packet-Gap Register Bit Fields*/
-
-#define NS7520_ETH_IPGT_RES (0xFFFFFF80) /* Reserved */
-#define NS7520_ETH_IPGT_IPGT (0x0000007F) /* Back-to-Back Interpacket Gap */
-
-/* IPGR Non Back-to-Back Inter-Packet-Gap Register Bit Fields*/
-
-#define NS7520_ETH_IPGR_RES1 (0xFFFF8000) /* Reserved */
-#define NS7520_ETH_IPGR_IPGR1 (0x00007F00) /* Non Back-to-back Interpacket Gap */
-#define NS7520_ETH_IPGR_RES2 (0x00000080) /* Reserved */
-#define NS7520_ETH_IPGR_IPGR2 (0x0000007F) /* Non back-to-back Interpacket Gap */
-
-/* CLRT Collision Windows/Collision Retry Register Bit Fields*/
-
-#define NS7520_ETH_CLRT_RES1 (0xFFFFC000) /* Reserved */
-#define NS7520_ETH_CLRT_CWIN (0x00003F00) /* Collision Windows */
-#define NS7520_ETH_CLRT_RES2 (0x000000F0) /* Reserved */
-#define NS7520_ETH_CLRT_RETX (0x0000000F) /* Retransmission maximum */
-
-/* MAXF Maximum Frame Register Bit Fields*/
-
-#define NS7520_ETH_MAXF_RES1 (0xFFFF0000) /* Reserved */
-#define NS7520_ETH_MAXF_MAXF (0x0000FFFF) /* Maximum frame length */
-
-/* SUPP PHY Support Register Bit Fields*/
-
-#define NS7520_ETH_SUPP_RES1 (0xFFFFFF00) /* Reserved */
-#define NS7520_ETH_SUPP_RPE100X (0x00000080) /* Reset PE100X module */
-#define NS7520_ETH_SUPP_FORCEQ (0x00000040) /* Force Quit */
-#define NS7520_ETH_SUPP_NOCIPH (0x00000020) /* No Cipher */
-#define NS7520_ETH_SUPP_DLINKF (0x00000010) /* Disable link fail */
-#define NS7520_ETH_SUPP_RPE10T (0x00000008) /* Reset PE10T module */
-#define NS7520_ETH_SUPP_RES2 (0x00000004) /* Reserved */
-#define NS7520_ETH_SUPP_JABBER (0x00000002) /* Enable Jabber protection */
-#define NS7520_ETH_SUPP_BITMODE (0x00000001) /* Bit Mode */
-
-/* TEST Register Bit Fields*/
-
-#define NS7520_ETH_TEST_RES1 (0xFFFFFFF8) /* Reserved */
-#define NS7520_ETH_TEST_TBACK (0x00000004) /* Test backpressure */
-#define NS7520_ETH_TEST_TPAUSE (0x00000002) /* Test Pause */
-#define NS7520_ETH_TEST_SPQ (0x00000001) /* Shortcut pause quanta */
-
-/* MCFG MII Management Configuration Register Bit Fields*/
-
-#define NS7520_ETH_MCFG_RES1 (0xFFFF0000) /* Reserved */
-#define NS7520_ETH_MCFG_RMIIM (0x00008000) /* Reset MII management */
-#define NS7520_ETH_MCFG_RES2 (0x00007FE0) /* Reserved */
-#define NS7520_ETH_MCFG_CLKS_MA (0x0000001C) /* Clock Select */
-#define NS7520_ETH_MCFG_CLKS_4 (0x00000004) /* Sysclk / 4 */
-#define NS7520_ETH_MCFG_CLKS_6 (0x00000008) /* Sysclk / 6 */
-#define NS7520_ETH_MCFG_CLKS_8 (0x0000000C) /* Sysclk / 8 */
-#define NS7520_ETH_MCFG_CLKS_10 (0x00000010) /* Sysclk / 10 */
-#define NS7520_ETH_MCFG_CLKS_14 (0x00000014) /* Sysclk / 14 */
-#define NS7520_ETH_MCFG_CLKS_20 (0x00000018) /* Sysclk / 20 */
-#define NS7520_ETH_MCFG_CLKS_28 (0x0000001C) /* Sysclk / 28 */
-#define NS7520_ETH_MCFG_SPRE (0x00000002) /* Suppress preamble */
-#define NS7520_ETH_MCFG_SCANI (0x00000001) /* Scan increment */
-
-/* MCMD MII Management Command Register Bit Fields*/
-
-#define NS7520_ETH_MCMD_RES1 (0xFFFFFFFC) /* Reserved */
-#define NS7520_ETH_MCMD_SCAN (0x00000002) /* Automatically Scan for Read Data */
-#define NS7520_ETH_MCMD_READ (0x00000001) /* Single scan for Read Data */
-
-/* MCMD MII Management Address Register Bit Fields*/
-
-#define NS7520_ETH_MADR_RES1 (0xFFFFE000) /* Reserved */
-#define NS7520_ETH_MADR_DADR (0x00001F00) /* MII PHY device address */
-#define NS7520_ETH_MADR_RES2 (0x000000E0) /* Reserved */
-#define NS7520_ETH_MADR_RADR (0x0000001F) /* MII PHY register address */
-
-/* MWTD MII Management Write Data Register Bit Fields*/
-
-#define NS7520_ETH_MWTD_RES1 (0xFFFF0000) /* Reserved */
-#define NS7520_ETH_MWTD_MWTD (0x0000FFFF) /* MII Write Data */
-
-/* MRRD MII Management Read Data Register Bit Fields*/
-
-#define NS7520_ETH_MRRD_RES1 (0xFFFF0000) /* Reserved */
-#define NS7520_ETH_MRRD_MRDD (0x0000FFFF) /* MII Read Data */
-
-/* MIND MII Management Indicators Register Bit Fields*/
-
-#define NS7520_ETH_MIND_RES1 (0xFFFFFFF8) /* Reserved */
-#define NS7520_ETH_MIND_NVALID (0x00000004) /* Read Data not valid */
-#define NS7520_ETH_MIND_SCAN (0x00000002) /* Automatically scan for read data */
-#define NS7520_ETH_MIND_BUSY (0x00000001) /* MII interface busy */
-
-/* SMII Status Register Bit Fields*/
-
-#define NS7520_ETH_SMII_RES1 (0xFFFFFFE0) /* Reserved */
-#define NS7520_ETH_SMII_CLASH (0x00000010) /* MAC-to-MAC with PHY */
-#define NS7520_ETH_SMII_JABBER (0x00000008) /* Jabber condition present */
-#define NS7520_ETH_SMII_LINK (0x00000004) /* Link OK */
-#define NS7520_ETH_SMII_DUPLEX (0x00000002) /* Full-duplex operation */
-#define NS7520_ETH_SMII_SPEED (0x00000001) /* 100 Mbps */
-
-/* SA1 Station Address 1 Register Bit Fields*/
-
-#define NS7520_ETH_SA1_RES1 (0xFFFF0000) /* Reserved */
-#define NS7520_ETH_SA1_OCTET1 (0x0000FF00) /* Station Address octet 1 */
-#define NS7520_ETH_SA1_OCTET2 (0x000000FF) /* Station Address octet 2 */
-
-/* SA2 Station Address 2 Register Bit Fields*/
-
-#define NS7520_ETH_SA2_RES1 (0xFFFF0000) /* Reserved */
-#define NS7520_ETH_SA2_OCTET3 (0x0000FF00) /* Station Address octet 3 */
-#define NS7520_ETH_SA2_OCTET4 (0x000000FF) /* Station Address octet 4 */
-
-/* SA3 Station Address 3 Register Bit Fields*/
-
-#define NS7520_ETH_SA3_RES1 (0xFFFF0000) /* Reserved */
-#define NS7520_ETH_SA3_OCTET5 (0x0000FF00) /* Station Address octet 5 */
-#define NS7520_ETH_SA3_OCTET6 (0x000000FF) /* Station Address octet 6 */
-
-/* SAFR Station Address Filter Register Bit Fields*/
-
-#define NS7520_ETH_SAFR_RES1 (0xFFFFFFF0) /* Reserved */
-#define NS7520_ETH_SAFR_PRO (0x00000008) /* Enable Promiscuous mode */
-#define NS7520_ETH_SAFR_PRM (0x00000004) /* Accept ALL multicast packets */
-#define NS7520_ETH_SAFR_PRA (0x00000002) /* Accept multicast packets table */
-#define NS7520_ETH_SAFR_BROAD (0x00000001) /* Accept ALL Broadcast packets */
-
-/* HT1 Hash Table 1 Register Bit Fields*/
-
-#define NS7520_ETH_HT1_RES1 (0xFFFF0000) /* Reserved */
-#define NS7520_ETH_HT1_HT1 (0x0000FFFF) /* CRC value 15-0 */
-
-/* HT2 Hash Table 2 Register Bit Fields*/
-
-#define NS7520_ETH_HT2_RES1 (0xFFFF0000) /* Reserved */
-#define NS7520_ETH_HT2_HT2 (0x0000FFFF) /* CRC value 31-16 */
-
-/* HT3 Hash Table 3 Register Bit Fields*/
-
-#define NS7520_ETH_HT3_RES1 (0xFFFF0000) /* Reserved */
-#define NS7520_ETH_HT3_HT3 (0x0000FFFF) /* CRC value 47-32 */
-
-/* HT4 Hash Table 4 Register Bit Fields*/
-
-#define NS7520_ETH_HT4_RES1 (0xFFFF0000) /* Reserved */
-#define NS7520_ETH_HT4_HT4 (0x0000FFFF) /* CRC value 63-48 */
-
-#endif /* CONFIG_DRIVER_NS7520_ETHERNET */
-
-#endif /* FS_NS7520_ETH_H */
+++ /dev/null
-/***********************************************************************
- *
- * Copyright (C) 2004 by FS Forth-Systeme GmbH.
- * All rights reserved.
- *
- * $Id: ns9750_bbus.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
- * @Author: Markus Pietrek
- * @Descr: Definitions for BBus usage
- * @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 10
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- *
- ***********************************************************************/
-
-#ifndef FS_NS9750_BBUS_H
-#define FS_NS9750_BBUS_H
-
-#define NS9750_BBUS_MODULE_BASE (0x90600000)
-
-#define get_bbus_reg_addr(c) \
- ((volatile unsigned int *)(NS9750_BBUS_MODULE_BASE+(unsigned int) (c)))
-
-/* We have support for 50 GPIO pins */
-
-#define get_gpio_cfg_reg_addr(pin) \
- get_bbus_reg_addr( NS9750_BBUS_GPIO_CFG_BASE + (((pin) >> 3) * 4) )
-
-/* To Read/Modify/Write a pin configuration register, use it like
- set_gpio_cfg_reg_val( 12, NS9750_GPIO_CFG_FUNC_GPIO|NS9750_GPIO_CFG_OUTPUT );
- They should be wrapped by cli()/sti() */
-#define set_gpio_cfg_reg_val(pin,cfg) \
- *get_gpio_cfg_reg_addr(pin)=(*get_gpio_cfg_reg_addr((pin)) & \
- ~NS9750_GPIO_CFG_MASK((pin))) |\
- NS9750_GPIO_CFG_VAL((pin),(cfg));
-
-#define NS9750_GPIO_CFG_MASK(pin) (NS9750_GPIO_CFG_VAL(pin, \
- NS9750_GPIO_CFG_MA))
-#define NS9750_GPIO_CFG_VAL(pin,cfg) ((cfg) << (((pin) % 8) * 4))
-
-#define NS9750_GPIO_CFG_MA (0x0F)
-#define NS9750_GPIO_CFG_INPUT (0x00)
-#define NS9750_GPIO_CFG_OUTPUT (0x08)
-#define NS9750_GPIO_CFG_FUNC_GPIO (0x03)
-#define NS9750_GPIO_CFG_FUNC_2 (0x02)
-#define NS9750_GPIO_CFG_FUNC_1 (0x01)
-#define NS9750_GPIO_CFG_FUNC_0 (0x00)
-
-/* the register addresses */
-
-#define NS9750_BBUS_MASTER_RESET (0x00)
-#define NS9750_BBUS_GPIO_CFG_BASE (0x10)
-#define NS9750_BBUS_GPIO_CTRL_BASE (0x30)
-#define NS9750_BBUS_GPIO_STAT_BASE (0x40)
-#define NS9750_BBUS_MONITOR (0x50)
-#define NS9750_BBUS_DMA_INT_STAT (0x60)
-#define NS9750_BBUS_DMA_INT_ENABLE (0x64)
-#define NS9750_BBUS_USB_CFG (0x70)
-#define NS9750_BBUS_ENDIAN_CFG (0x80)
-#define NS9750_BBUS_ARM_WAKE_UP (0x90)
-
-/* register bit fields */
-
-#define NS9750_BBUS_MASTER_RESET_UTIL (0x00000100)
-#define NS9750_BBUS_MASTER_RESET_I2C (0x00000080)
-#define NS9750_BBUS_MASTER_RESET_1284 (0x00000040)
-#define NS9750_BBUS_MASTER_RESET_SER4 (0x00000020)
-#define NS9750_BBUS_MASTER_RESET_SER3 (0x00000010)
-#define NS9750_BBUS_MASTER_RESET_SER2 (0x00000008)
-#define NS9750_BBUS_MASTER_RESET_SER1 (0x00000004)
-#define NS9750_BBUS_MASTER_RESET_USB (0x00000002)
-#define NS9750_BBUS_MASTER_RESET_DMA (0x00000001)
-
-/* BS9750_BBUS_DMA_INT_BINT* are valid for *DMA_INT_STAT and *DMA_INT_ENABLE */
-
-#define NS9750_BBUS_DMA_INT_BINT16 (0x00010000)
-#define NS9750_BBUS_DMA_INT_BINT15 (0x00008000)
-#define NS9750_BBUS_DMA_INT_BINT14 (0x00004000)
-#define NS9750_BBUS_DMA_INT_BINT13 (0x00002000)
-#define NS9750_BBUS_DMA_INT_BINT12 (0x00001000)
-#define NS9750_BBUS_DMA_INT_BINT11 (0x00000800)
-#define NS9750_BBUS_DMA_INT_BINT10 (0x00000400)
-#define NS9750_BBUS_DMA_INT_BINT9 (0x00000200)
-#define NS9750_BBUS_DMA_INT_BINT8 (0x00000100)
-#define NS9750_BBUS_DMA_INT_BINT7 (0x00000080)
-#define NS9750_BBUS_DMA_INT_BINT6 (0x00000040)
-#define NS9750_BBUS_DMA_INT_BINT5 (0x00000020)
-#define NS9750_BBUS_DMA_INT_BINT4 (0x00000010)
-#define NS9750_BBUS_DMA_INT_BINT3 (0x00000008)
-#define NS9750_BBUS_DMA_INT_BINT2 (0x00000004)
-#define NS9750_BBUS_DMA_INT_BINT1 (0x00000002)
-#define NS9750_BBUS_DMA_INT_BINT0 (0x00000001)
-
-#define NS9750_BBUS_USB_CFG_OUTEN (0x00000008)
-#define NS9750_BBUS_USB_CFG_SPEED (0x00000004)
-#define NS9750_BBUS_USB_CFG_CFG_MA (0x00000003)
-#define NS9750_BBUS_USB_CFG_CFG_HOST_SOFT (0x00000003)
-#define NS9750_BBUS_USB_CFG_CFG_DEVICE (0x00000002)
-#define NS9750_BBUS_USB_CFG_CFG_HOST (0x00000001)
-#define NS9750_BBUS_USB_CFG_CFG_DIS (0x00000000)
-
-#define NS9750_BBUS_ENDIAN_CFG_AHBM (0x00001000)
-#define NS9750_BBUS_ENDIAN_CFG_I2C (0x00000080)
-#define NS9750_BBUS_ENDIAN_CFG_IEEE1284 (0x00000040)
-#define NS9750_BBUS_ENDIAN_CFG_SER4 (0x00000020)
-#define NS9750_BBUS_ENDIAN_CFG_SER3 (0x00000010)
-#define NS9750_BBUS_ENDIAN_CFG_SER2 (0x00000008)
-#define NS9750_BBUS_ENDIAN_CFG_SER1 (0x00000004)
-#define NS9750_BBUS_ENDIAN_CFG_USB (0x00000002)
-#define NS9750_BBUS_ENDIAN_CFG_DMA (0x00000001)
-
-#endif /* FS_NS9750_BBUS_H */
+++ /dev/null
-/***********************************************************************
- *
- * Copyright (C) 2004 by FS Forth-Systeme GmbH.
- * All rights reserved.
- *
- * $Id: ns9750_eth.h,v 1.2 2004/02/24 13:25:39 mpietrek Exp $
- * @Author: Markus Pietrek
- * @References: [1] NS9750 Hardware Reference, December 2003
- * [2] Intel LXT971 Datasheet #249414 Rev. 02
- * [3] NS7520 Linux Ethernet Driver
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- ***********************************************************************/
-
-#ifndef FS_NS9750_ETH_H
-#define FS_NS9750_ETH_H
-
-#ifdef CONFIG_DRIVER_NS9750_ETHERNET
-
-#include <miiphy.h>
-#include "lxt971a.h"
-
-#define NS9750_ETH_MODULE_BASE (0xA0600000)
-
-#define get_eth_reg_addr(c) \
- ((volatile unsigned int*) ( NS9750_ETH_MODULE_BASE+(unsigned int) (c)))
-
-#define NS9750_ETH_EGCR1 (0x0000)
-#define NS9750_ETH_EGCR2 (0x0004)
-#define NS9750_ETH_EGSR (0x0008)
-#define NS9750_ETH_FIFORX (0x000C)
-#define NS9750_ETH_FIFOTX (0x0010)
-#define NS9750_ETH_FIFOTXS (0x0014)
-#define NS9750_ETH_ETSR (0x0018)
-#define NS9750_ETH_ERSR (0x001C)
-#define NS9750_ETH_MAC1 (0x0400)
-#define NS9750_ETH_MAC2 (0x0404)
-#define NS9750_ETH_IPGT (0x0408)
-#define NS9750_ETH_IPGR (0x040C)
-#define NS9750_ETH_CLRT (0x0410)
-#define NS9750_ETH_MAXF (0x0414)
-#define NS9750_ETH_SUPP (0x0418)
-#define NS9750_ETH_TEST (0x041C)
-#define NS9750_ETH_MCFG (0x0420)
-#define NS9750_ETH_MCMD (0x0424)
-#define NS9750_ETH_MADR (0x0428)
-#define NS9750_ETH_MWTD (0x042C)
-#define NS9750_ETH_MRDD (0x0430)
-#define NS9750_ETH_MIND (0x0434)
-#define NS9750_ETH_SA1 (0x0440)
-#define NS9750_ETH_SA2 (0x0444)
-#define NS9750_ETH_SA3 (0x0448)
-#define NS9750_ETH_SAFR (0x0500)
-#define NS9750_ETH_HT1 (0x0504)
-#define NS9750_ETH_HT2 (0x0508)
-#define NS9750_ETH_STAT_BASE (0x0680)
-#define NS9750_ETH_RXAPTR (0x0A00)
-#define NS9750_ETH_RXBPTR (0x0A04)
-#define NS9750_ETH_RXCPTR (0x0A08)
-#define NS9750_ETH_RXDPTR (0x0A0C)
-#define NS9750_ETH_EINTR (0x0A10)
-#define NS9750_ETH_EINTREN (0x0A14)
-#define NS9750_ETH_TXPTR (0x0A18)
-#define NS9750_ETH_TXRPTR (0x0A1C)
-#define NS9750_ETH_TXERBD (0x0A20)
-#define NS9750_ETH_TXSPTR (0x0A24)
-#define NS9750_ETH_RXAOFF (0x0A28)
-#define NS9750_ETH_RXBOFF (0x0A2C)
-#define NS9750_ETH_RXCOFF (0x0A30)
-#define NS9750_ETH_RXDOFF (0x0A34)
-#define NS9750_ETH_TXOFF (0x0A38)
-#define NS9750_ETH_RXFREE (0x0A3C)
-#define NS9750_ETH_TXBD (0x1000)
-
-/* register bit fields */
-
-#define NS9750_ETH_EGCR1_ERX (0x80000000)
-#define NS9750_ETH_EGCR1_ERXDMA (0x40000000)
-#define NS9750_ETH_EGCR1_ERXSHT (0x10000000)
-#define NS9750_ETH_EGCR1_ERXSIZ (0x08000000)
-#define NS9750_ETH_EGCR1_ETXSIZ (0x04000000)
-#define NS9750_ETH_EGCR1_ETXDIAG (0x02000000)
-#define NS9750_ETH_EGCR1_ERXBAD (0x01000000)
-#define NS9750_ETH_EGCR1_ETX (0x00800000)
-#define NS9750_ETH_EGCR1_ETXDMA (0x00400000)
-#define NS9750_ETH_EGCR1_ETXWM (0x00200000)
-#define NS9750_ETH_EGCR1_ERXADV (0x00100000)
-#define NS9750_ETH_EGCR1_ERXINIT (0x00080000)
-#define NS9750_ETH_EGCR1_PHY_MODE_MA (0x0000C000)
-#define NS9750_ETH_EGCR1_PHY_MODE_MII (0x00008000)
-#define NS9750_ETH_EGCR1_PHY_MODE_RMII (0x00004000)
-#define NS9750_ETH_EGCR1_RXCINV (0x00001000)
-#define NS9750_ETH_EGCR1_TXCINV (0x00000800)
-#define NS9750_ETH_EGCR1_RXALIGN (0x00000400)
-#define NS9750_ETH_EGCR1_MAC_HRST (0x00000200)
-#define NS9750_ETH_EGCR1_ITXA (0x00000100)
-
-#define NS9750_ETH_EGCR2_TPTV_MA (0xFFFF0000)
-#define NS9750_ETH_EGCR2_TPCF (0x00000040)
-#define NS9750_ETH_EGCR2_THPDF (0x00000020)
-#define NS9750_ETH_EGCR2_TCLER (0x00000008)
-#define NS9750_ETH_EGCR2_AUTOZ (0x00000004)
-#define NS9750_ETH_EGCR2_CLRCNT (0x00000002)
-#define NS9750_ETH_EGCR2_STEN (0x00000001)
-
-#define NS9750_ETH_EGSR_RXINIT (0x00100000)
-#define NS9750_ETH_EGSR_TXFIFONF (0x00080000)
-#define NS9750_ETH_EGSR_TXFIFOH (0x00040000)
-#define NS9750_ETH_EGSR_TXFIFOE (0x00010000)
-
-#define NS9750_ETH_FIFOTXS_ALL (0x00000055)
-#define NS9750_ETH_FIFOTXS_3 (0x000000d5)
-#define NS9750_ETH_FIFOTXS_2 (0x00000035)
-#define NS9750_ETH_FIFOTXS_1 (0x0000000D)
-#define NS9750_ETH_FIFOTXS_0 (0x00000003)
-
-#define NS9750_ETH_ETSR_TXOK (0x00008000)
-#define NS9750_ETH_ETSR_TXBR (0x00004000)
-#define NS9750_ETH_ETSR_TXMC (0x00002000)
-#define NS9750_ETH_ETSR_TXAL (0x00001000)
-#define NS9750_ETH_ETSR_TXAED (0x00000800)
-#define NS9750_ETH_ETSR_TXAEC (0x00000400)
-#define NS9750_ETH_ETSR_TXAUR (0x00000200)
-#define NS9750_ETH_ETSR_TXAJ (0x00000100)
-#define NS9750_ETH_ETSR_TXDEF (0x00000040)
-#define NS9750_ETH_ETSR_TXCRC (0x00000020)
-#define NS9750_ETH_ETSR_TXCOLC (0x0000000F)
-
-#define NS9750_ETH_ERSR_RXSIZE_MA (0x0FFF0000)
-#define NS9750_ETH_ERSR_RXCE (0x00008000)
-#define NS9750_ETH_ERSR_RXDV (0x00004000)
-#define NS9750_ETH_ERSR_RXOK (0x00002000)
-#define NS9750_ETH_ERSR_RXBR (0x00001000)
-#define NS9750_ETH_ERSR_RXMC (0x00000800)
-#define NS9750_ETH_ERSR_RXCRC (0x00000400)
-#define NS9750_ETH_ERSR_RXDR (0x00000200)
-#define NS9750_ETH_ERSR_RXCV (0x00000100)
-#define NS9750_ETH_ERSR_RXSHT (0x00000040)
-
-#define NS9750_ETH_MAC1_SRST (0x00008000)
-#define NS9750_ETH_MAC1_SIMMRST (0x00004000)
-#define NS9750_ETH_MAC1_RPEMCSR (0x00000800)
-#define NS9750_ETH_MAC1_RPERFUN (0x00000400)
-#define NS9750_ETH_MAC1_RPEMCST (0x00000200)
-#define NS9750_ETH_MAC1_RPETFUN (0x00000100)
-#define NS9750_ETH_MAC1_LOOPBK (0x00000010)
-#define NS9750_ETH_MAC1_TXFLOW (0x00000008)
-#define NS9750_ETH_MAC1_RXFLOW (0x00000004)
-#define NS9750_ETH_MAC1_PALLRX (0x00000002)
-#define NS9750_ETH_MAC1_RXEN (0x00000001)
-
-#define NS9750_ETH_MAC2_EDEFER (0x00004000)
-#define NS9750_ETH_MAC2_BACKP (0x00002000)
-#define NS9750_ETH_MAC2_NOBO (0x00001000)
-#define NS9750_ETH_MAC2_LONGP (0x00000200)
-#define NS9750_ETH_MAC2_PUREP (0x00000100)
-#define NS9750_ETH_MAC2_AUTOP (0x00000080)
-#define NS9750_ETH_MAC2_VLANP (0x00000040)
-#define NS9750_ETH_MAC2_PADEN (0x00000020)
-#define NS9750_ETH_MAC2_CRCEN (0x00000010)
-#define NS9750_ETH_MAC2_DELCRC (0x00000008)
-#define NS9750_ETH_MAC2_HUGE (0x00000004)
-#define NS9750_ETH_MAC2_FLENC (0x00000002)
-#define NS9750_ETH_MAC2_FULLD (0x00000001)
-
-#define NS9750_ETH_IPGT_MA (0x0000007F)
-
-#define NS9750_ETH_IPGR_IPGR1 (0x00007F00)
-#define NS9750_ETH_IPGR_IPGR2 (0x0000007F)
-
-#define NS9750_ETH_CLRT_CWIN (0x00003F00)
-#define NS9750_ETH_CLRT_RETX (0x0000000F)
-
-#define NS9750_ETH_MAXF_MAXF (0x0000FFFF)
-
-#define NS9750_ETH_SUPP_RPERMII (0x00008000)
-#define NS9750_ETH_SUPP_SPEED (0x00000080)
-
-#define NS9750_ETH_TEST_TBACK (0x00000004)
-#define NS9750_ETH_TEST_TPAUSE (0x00000002)
-#define NS9750_ETH_TEST_SPQ (0x00000001)
-
-#define NS9750_ETH_MCFG_RMIIM (0x00008000)
-#define NS9750_ETH_MCFG_CLKS_MA (0x0000001C)
-#define NS9750_ETH_MCFG_CLKS_4 (0x00000004)
-#define NS9750_ETH_MCFG_CLKS_6 (0x00000008)
-#define NS9750_ETH_MCFG_CLKS_8 (0x0000000C)
-#define NS9750_ETH_MCFG_CLKS_10 (0x00000010)
-#define NS9750_ETH_MCFG_CLKS_20 (0x00000014)
-#define NS9750_ETH_MCFG_CLKS_30 (0x00000018)
-#define NS9750_ETH_MCFG_CLKS_40 (0x0000001C)
-#define NS9750_ETH_MCFG_SPRE (0x00000002)
-#define NS9750_ETH_MCFG_SCANI (0x00000001)
-
-#define NS9750_ETH_MCMD_SCAN (0x00000002)
-#define NS9750_ETH_MCMD_READ (0x00000001)
-
-#define NS9750_ETH_MADR_DADR_MA (0x00001F00)
-#define NS9750_ETH_MADR_RADR_MA (0x0000001F)
-
-#define NS9750_ETH_MWTD_MA (0x0000FFFF)
-
-#define NS9750_ETH_MRRD_MA (0x0000FFFF)
-
-#define NS9750_ETH_MIND_MIILF (0x00000008)
-#define NS9750_ETH_MIND_NVALID (0x00000004)
-#define NS9750_ETH_MIND_SCAN (0x00000002)
-#define NS9750_ETH_MIND_BUSY (0x00000001)
-
-#define NS9750_ETH_SA1_OCTET1_MA (0x0000FF00)
-#define NS9750_ETH_SA1_OCTET2_MA (0x000000FF)
-
-#define NS9750_ETH_SA2_OCTET3_MA (0x0000FF00)
-#define NS9750_ETH_SA2_OCTET4_MA (0x000000FF)
-
-#define NS9750_ETH_SA3_OCTET5_MA (0x0000FF00)
-#define NS9750_ETH_SA3_OCTET6_MA (0x000000FF)
-
-#define NS9750_ETH_SAFR_PRO (0x00000008)
-#define NS9750_ETH_SAFR_PRM (0x00000004)
-#define NS9750_ETH_SAFR_PRA (0x00000002)
-#define NS9750_ETH_SAFR_BROAD (0x00000001)
-
-#define NS9750_ETH_HT1_MA (0x0000FFFF)
-
-#define NS9750_ETH_HT2_MA (0x0000FFFF)
-
-/* also valid for EINTREN */
-#define NS9750_ETH_EINTR_RXOVL_DATA (0x02000000)
-#define NS9750_ETH_EINTR_RXOVL_STAT (0x01000000)
-#define NS9750_ETH_EINTR_RXBUFC (0x00800000)
-#define NS9750_ETH_EINTR_RXDONEA (0x00400000)
-#define NS9750_ETH_EINTR_RXDONEB (0x00200000)
-#define NS9750_ETH_EINTR_RXDONEC (0x00100000)
-#define NS9750_ETH_EINTR_RXDONED (0x00080000)
-#define NS9750_ETH_EINTR_RXNOBUF (0x00040000)
-#define NS9750_ETH_EINTR_RXBUFFUL (0x00020000)
-#define NS9750_ETH_EINTR_RXBR (0x00010000)
-#define NS9750_ETH_EINTR_STOVFL (0x00000040)
-#define NS9750_ETH_EINTR_TXPAUSE (0x00000020)
-#define NS9750_ETH_EINTR_TXBUFC (0x00000010)
-#define NS9750_ETH_EINTR_TXBUFNR (0x00000008)
-#define NS9750_ETH_EINTR_TXDONE (0x00000004)
-#define NS9750_ETH_EINTR_TXERR (0x00000002)
-#define NS9750_ETH_EINTR_TXIDLE (0x00000001)
-#define NS9750_ETH_EINTR_RX_MA \
- (NS9750_ETH_EINTR_RXOVL_DATA | \
- NS9750_ETH_EINTR_RXOVL_STAT | \
- NS9750_ETH_EINTR_RXBUFC | \
- NS9750_ETH_EINTR_RXDONEA | \
- NS9750_ETH_EINTR_RXDONEB | \
- NS9750_ETH_EINTR_RXDONEC | \
- NS9750_ETH_EINTR_RXDONED | \
- NS9750_ETH_EINTR_RXNOBUF | \
- NS9750_ETH_EINTR_RXBUFFUL | \
- NS9750_ETH_EINTR_RXBR )
-#define NS9750_ETH_EINTR_TX_MA \
- (NS9750_ETH_EINTR_TXPAUSE | \
- NS9750_ETH_EINTR_TXBUFC | \
- NS9750_ETH_EINTR_TXBUFNR | \
- NS9750_ETH_EINTR_TXDONE | \
- NS9750_ETH_EINTR_TXERR | \
- NS9750_ETH_EINTR_TXIDLE)
-
-/* for TXPTR, TXRPTR, TXERBD and TXSPTR */
-#define NS9750_ETH_TXPTR_MA (0x000000FF)
-
-/* for RXAOFF, RXBOFF, RXCOFF and RXDOFF */
-#define NS9750_ETH_RXOFF_MA (0x000007FF)
-
-#define NS9750_ETH_TXOFF_MA (0x000003FF)
-
-#define NS9750_ETH_RXFREE_D (0x00000008)
-#define NS9750_ETH_RXFREE_C (0x00000004)
-#define NS9750_ETH_RXFREE_B (0x00000002)
-#define NS9750_ETH_RXFREE_A (0x00000001)
-
-#ifndef NS9750_ETH_PHY_ADDRESS
-# define NS9750_ETH_PHY_ADDRESS (0x0001) /* suitable for UNC20 */
-#endif /* NETARM_ETH_PHY_ADDRESS */
-
-#endif /* CONFIG_DRIVER_NS9750_ETHERNET */
-
-#endif /* FS_NS9750_ETH_H */
+++ /dev/null
-/***********************************************************************
- *
- * Copyright (C) 2004 by FS Forth-Systeme GmbH.
- * All rights reserved.
- *
- * $Id: ns9750_mem.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
- * @Author: Markus Pietrek
- * @Descr: Definitions for Memory Control Module
- * @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 5
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- ***********************************************************************/
-
-#ifndef FS_NS9750_MEM_H
-#define FS_NS9750_SYS_H
-
-#define NS9750_MEM_MODULE_BASE (0xA0700000)
-
-#define get_mem_reg_addr(c) \
- ((volatile unsigned int *)(NS9750_MEM_MODULE_BASE+(unsigned int) (c)))
-
-/* the register addresses */
-
-#define NS9750_MEM_CTRL (0x0000)
-#define NS9750_MEM_STATUS (0x0004)
-#define NS9750_MEM_CFG (0x0008)
-#define NS9750_MEM_DYN_CTRL (0x0020)
-#define NS9750_MEM_DYN_REFRESH (0x0024)
-#define NS9750_MEM_DYN_READ_CFG (0x0028)
-#define NS9750_MEM_DYN_TRP (0x0030)
-#define NS9750_MEM_DYN_TRAS (0x0034)
-#define NS9750_MEM_DYN_TSREX (0x0038)
-#define NS9750_MEM_DYN_TAPR (0x003C)
-#define NS9750_MEM_DYN_TDAL (0x0040)
-#define NS9750_MEM_DYN_TWR (0x0044)
-#define NS9750_MEM_DYN_TRC (0x0048)
-#define NS9750_MEM_DYN_TRFC (0x004C)
-#define NS9750_MEM_DYN_TXSR (0x0050)
-#define NS9750_MEM_DYN_TRRD (0x0054)
-#define NS9750_MEM_DYN_TMRD (0x0058)
-#define NS9750_MEM_STAT_EXT_WAIT (0x0080)
-#define NS9750_MEM_DYN_CFG_BASE (0x0100)
-#define NS9750_MEM_DYN_RAS_CAS_BASE (0x0104)
-#define NS9750_MEM_STAT_CFG_BASE (0x0200)
-#define NS9750_MEM_STAT_WAIT_WEN_BASE (0x0204)
-#define NS9750_MEM_STAT_WAIT_OEN_BASE (0x0208)
-#define NS9750_MEM_STAT_WAIT_RD_BASE (0x020C)
-#define NS9750_MEM_STAT_WAIT_PAGE_BASE (0x0210)
-#define NS9750_MEM_STAT_WAIR_WR_BASE (0x0214)
-#define NS9750_MEM_STAT_WAIT_TURN_BASE (0x0218)
-
-/* the vectored register addresses */
-
-#define NS9750_MEM_DYN_CFG(c) (NS9750_MEM_DYN_CFG_BASE + (c)*0x20)
-#define NS9750_MEM_DYN_RAS_CAS(c) (NS9750_MEM_DYN_RAS_CAS_BASE + (c)*0x20)
-#define NS9750_MEM_STAT_CFG(c) (NS9750_MEM_STAT_CFG_BASE + (c)*0x20)
-#define NS9750_MEM_STAT_WAIT_WEN(c) (NS9750_MEM_STAT_WAIT_WEN_BASE+(c)*0x20)
-#define NS9750_MEM_STAT_WAIT_OEN(c) (NS9750_MEM_STAT_WAIT_OEN_BASE+(c)*0x20)
-#define NS9750_MEM_STAT_RD(c) (NS9750_MEM_STAT_WAIT_RD_BASE+(c)*0x20)
-#define NS9750_MEM_STAT_PAGE(c) (NS9750_MEM_STAT_WAIT_PAGE_BASE+(c)*0x20)
-#define NS9750_MEM_STAT_WR(c) (NS9750_MEM_STAT_WAIT_WR_BASE+(c)*0x20)
-#define NS9750_MEM_STAT_TURN(c) (NS9750_MEM_STAT_WAIT_TURN_BASE+(c)*0x20)
-
-/* register bit fields */
-
-#define NS9750_MEM_CTRL_L (0x00000004)
-#define NS9750_MEM_CTRL_M (0x00000002)
-#define NS9750_MEM_CTRL_E (0x00000001)
-
-#define NS9750_MEM_STAT_SA (0x00000004)
-#define NS9750_MEM_STAT_S (0x00000002)
-#define NS9750_MEM_STAT_B (0x00000001)
-
-#define NS9750_MEM_CFG_CLK (0x00000010)
-#define NS9750_MEM_CFG_N (0x00000001)
-
-#define NS9750_MEM_DYN_CTRL_NRP (0x00004000)
-#define NS9750_MEM_DYN_CTRL_DP (0x00002000)
-#define NS9750_MEM_DYN_CTRL_I_MA (0x00000180)
-#define NS9750_MEM_DYN_CTRL_I_NORMAL (0x00000000)
-#define NS9750_MEM_DYN_CTRL_I_MODE (0x00000080)
-#define NS9750_MEM_DYN_CTRL_I_PALL (0x00000100)
-#define NS9750_MEM_DYN_CTRL_I_NOP (0x00000180)
-#define NS9750_MEM_DYN_CTRL_SR (0x00000002)
-#define NS9750_MEM_DYN_CTRL_CE (0x00000001)
-
-
-#define NS9750_MEM_DYN_REFRESH_MA (0x000007FF)
-
-#define NS9750_MEM_DYN_READ_CFG_MA (0x00000003)
-#define NS9750_MEM_DYN_READ_CFG_DELAY0 (0x00000001)
-#define NS9750_MEM_DYN_READ_CFG_DELAY1 (0x00000002)
-#define NS9750_MEM_DYN_READ_CFG_DELAY2 (0x00000003)
-
-#define NS9750_MEM_DYN_TRP_MA (0x0000000F)
-
-#define NS9750_MEM_DYN_TRAS_MA (0x0000000F)
-
-#define NS9750_MEM_DYN_TSREX_MA (0x0000000F)
-
-#define NS9750_MEM_DYN_TAPR_MA (0x0000000F)
-
-#define NS9750_MEM_DYN_TDAL_MA (0x0000000F)
-
-#define NS9750_MEM_DYN_TWR_MA (0x0000000F)
-
-#define NS9750_MEM_DYN_TRC_MA (0x0000001F)
-
-#define NS9750_MEM_DYN_TRFC_MA (0x0000001F)
-
-#define NS9750_MEM_DYN_TXSR_MA (0x0000001F)
-
-#define NS9750_MEM_DYN_TRRD_MA (0x0000000F)
-
-#define NS9750_MEM_DYN_TMRD_MA (0x0000000F)
-
-#define NS9750_MEM_STAT_EXTW_WAIT_MA (0x0000003F)
-
-#define NS9750_MEM_DYN_CFG_P (0x00100000)
-#define NS9750_MEM_DYN_CFG_BDMC (0x00080000)
-#define NS9750_MEM_DYN_CFG_AM (0x00004000)
-#define NS9750_MEM_DYN_CFG_AM_MA (0x00001F80)
-#define NS9750_MEM_DYN_CFG_MD (0x00000018)
-
-#define NS9750_MEM_DYN_RAS_CAS_CAS_MA (0x00000300)
-#define NS9750_MEM_DYN_RAS_CAS_CAS_1 (0x00000100)
-#define NS9750_MEM_DYN_RAS_CAS_CAS_2 (0x00000200)
-#define NS9750_MEM_DYN_RAS_CAS_CAS_3 (0x00000300)
-#define NS9750_MEM_DYN_RAS_CAS_RAS_MA (0x00000003)
-#define NS9750_MEM_DYN_RAS_CAS_RAS_1 (0x00000001)
-#define NS9750_MEM_DYN_RAS_CAS_RAS_2 (0x00000002)
-#define NS9750_MEM_DYN_RAS_CAS_RAS_3 (0x00000003)
-
-#define NS9750_MEM_STAT_CFG_PSMC (0x00100000)
-#define NS9750_MEM_STAT_CFG_BSMC (0x00080000)
-#define NS9750_MEM_STAT_CFG_EW (0x00000100)
-#define NS9750_MEM_STAT_CFG_PB (0x00000080)
-#define NS9750_MEM_STAT_CFG_PC (0x00000040)
-#define NS9750_MEM_STAT_CFG_PM (0x00000008)
-#define NS9750_MEM_STAT_CFG_MW_MA (0x00000003)
-#define NS9750_MEM_STAT_CFG_MW_8 (0x00000000)
-#define NS9750_MEM_STAT_CFG_MW_16 (0x00000001)
-#define NS9750_MEM_STAT_CFG_MW_32 (0x00000002)
-
-#define NS9750_MEM_STAT_WAIT_WEN_MA (0x0000000F)
-
-#define NS9750_MEM_STAT_WAIT_OEN_MA (0x0000000F)
-
-#define NS9750_MEM_STAT_WAIT_RD_MA (0x0000001F)
-
-#define NS9750_MEM_STAT_WAIT_PAGE_MA (0x0000001F)
-
-#define NS9750_MEM_STAT_WAIT_WR_MA (0x0000001F)
-
-#define NS9750_MEM_STAT_WAIT_TURN_MA (0x0000000F)
-
-
-#endif /* FS_NS9750_MEM_H */
+++ /dev/null
-/***********************************************************************
- *
- * Copyright (C) 2004 by FS Forth-Systeme GmbH.
- * All rights reserved.
- *
- * $Id: ns9750_ser.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
- * @Author: Markus Pietrek
- * @References: [1] NS9750 Hardware Reference, December 2003
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- ***********************************************************************/
-
-#ifndef FS_NS9750_SER_H
-#define FS_NS9750_SER_H
-
-#define NS9750_SER_MODULE_BASE (0x90200000)
-
-#define get_ser_reg_addr(c) \
- ((volatile unsigned int *)(NS9750_SER_MODULE_BASE+(unsigned int) (c)))
-
-#define get_ser_reg_addr_channel(reg,chan) \
- get_ser_reg_addr((reg)+(((chan)<2)?0:0x00100000)+(((chan)&1)?0x40:0))
-
-/* the register addresses */
-
-#define NS9750_SER_CTRL_A (0x00)
-#define NS9750_SER_CTRL_B (0x04)
-#define NS9750_SER_STAT_A (0x08)
-#define NS9750_SER_BITRATE (0x0C)
-#define NS9750_SER_FIFO (0x10)
-#define NS9750_SER_RX_BUF_TIMER (0x14)
-#define NS9750_SER_RX_CHAR_TIMER (0x18)
-#define NS9750_SER_RX_MATCH (0x1C)
-#define NS9750_SER_RX_MATCH_MASK (0x20)
-#define NS9750_SER_FLOW_CTRL (0x34)
-#define NS9750_SER_FLOW_CTRL_FORCE (0x38)
-
-/* register bit fields */
-
-/* control A register */
-
-#define NS9750_SER_CTRL_A_CE (0x80000000)
-#define NS9750_SER_CTRL_A_BRK (0x40000000)
-#define NS9750_SER_CTRL_A_STICKP (0x20000000)
-#define NS9750_SER_CTRL_A_EPS (0x10000000)
-#define NS9750_SER_CTRL_A_PE (0x08000000)
-#define NS9750_SER_CTRL_A_STOP (0x04000000)
-#define NS9750_SER_CTRL_A_WLS_MA (0x03000000)
-#define NS9750_SER_CTRL_A_WLS_5 (0x00000000)
-#define NS9750_SER_CTRL_A_WLS_6 (0x01000000)
-#define NS9750_SER_CTRL_A_WLS_7 (0x02000000)
-#define NS9750_SER_CTRL_A_WLS_8 (0x03000000)
-#define NS9750_SER_CTRL_A_CTSTX (0x00800000)
-#define NS9750_SER_CTRL_A_RTSRX (0x00400000)
-#define NS9750_SER_CTRL_A_RL (0x00200000)
-#define NS9750_SER_CTRL_A_LL (0x00100000)
-#define NS9750_SER_CTRL_A_RES (0x000CF000)
-#define NS9750_SER_CTRL_A_DTR (0x00020000)
-#define NS9750_SER_CTRL_A_RTS (0x00010000)
-#define NS9750_SER_CTRL_A_RIE_MA (0x00000E00)
-#define NS9750_SER_CTRL_A_ERXDMA (0x00000100)
-#define NS9750_SER_CTRL_A_RIC_MA (0x000000E0)
-#define NS9750_SER_CTRL_A_TIC_MA (0x0000001E)
-#define NS9750_SER_CTRL_A_ETXDMA (0x00000001)
-
-/* control B register */
-
-#define NS9750_SER_CTRL_B_RDM1 (0x80000000)
-#define NS9750_SER_CTRL_B_RDM2 (0x40000000)
-#define NS9750_SER_CTRL_B_RDM3 (0x20000000)
-#define NS9750_SER_CTRL_B_RDM4 (0x10000000)
-#define NS9750_SER_CTRL_B_RBGT (0x08000000)
-#define NS9750_SER_CTRL_B_RCGT (0x04000000)
-#define NS9750_SER_CTRL_B_MODE_MA (0x00300000)
-#define NS9750_SER_CTRL_B_MODE_UART (0x00000000)
-#define NS9750_SER_CTRL_B_MODE_HDLC (0x00100000)
-#define NS9750_SER_CTRL_B_MODE_SPI_M (0x00200000)
-#define NS9750_SER_CTRL_B_MODE_SPI_S (0x00300000)
-#define NS9750_SER_CTRL_B_BITORDR (0x00080000)
-#define NS9750_SER_CTRL_B_RES (0x0007703F)
-#define NS9750_SER_CTRL_B_RTSTX (0x00008000)
-#define NS9750_SER_CTRL_B_ENDEC_MA (0x00000FC0)
-
-/* status A register */
-
-#define NS9750_SER_STAT_A_MATCH1 (0x80000000)
-#define NS9750_SER_STAT_A_MATCH2 (0x40000000)
-#define NS9750_SER_STAT_A_MATCH3 (0x20000000)
-#define NS9750_SER_STAT_A_MATCH4 (0x10000000)
-#define NS9750_SER_STAT_A_BGAP (0x08000000)
-#define NS9750_SER_STAT_A_CGAP (0x04000000)
-#define NS9750_SER_STAT_A_RXFDB_MA (0x00300000)
-#define NS9750_SER_STAT_A_RXFDB_FULL (0x00000000)
-#define NS9750_SER_STAT_A_RXFDB_1 (0x00100000)
-#define NS9750_SER_STAT_A_RXFDB_2 (0x00200000)
-#define NS9750_SER_STAT_A_RXFDB_3 (0x00300000)
-#define NS9750_SER_STAT_A_DCD (0x00080000)
-#define NS9750_SER_STAT_A_RI (0x00040000)
-#define NS9750_SER_STAT_A_DSR (0x00020000)
-#define NS9750_SER_STAT_A_CTS (0x00010000)
-#define NS9750_SER_STAT_A_RBRK (0x00008000)
-#define NS9750_SER_STAT_A_RFE (0x00004000)
-#define NS9750_SER_STAT_A_RPE (0x00002000)
-#define NS9750_SER_STAT_A_ROVER (0x00001000)
-#define NS9750_SER_STAT_A_RRDY (0x00000800)
-#define NS9750_SER_STAT_A_RHALF (0x00000400)
-#define NS9750_SER_STAT_A_RBC (0x00000200)
-#define NS9750_SER_STAT_A_RFULL (0x00000100)
-#define NS9750_SER_STAT_A_DCDI (0x00000080)
-#define NS9750_SER_STAT_A_RII (0x00000040)
-#define NS9750_SER_STAT_A_DSRI (0x00000020)
-#define NS9750_SER_STAT_A_CTSI (0x00000010)
-#define NS9750_SER_STAT_A_TRDY (0x00000008)
-#define NS9750_SER_STAT_A_THALF (0x00000004)
-#define NS9750_SER_STAT_A_TBC (0x00000002)
-#define NS9750_SER_STAT_A_TEMPTY (0x00000001)
-
-#define NS9750_SER_STAT_A_RX_COND_ERR ( NS9750_SER_STAT_A_RFE | \
- NS9750_SER_STAT_A_ROVER | \
- NS9750_SER_STAT_A_RPE )
-#define NS9750_SER_STAT_A_RX_COND_ALL ( NS9750_SER_STAT_A_RX_COND_ERR | \
- NS9750_SER_STAT_A_RBRK | \
- NS9750_SER_STAT_A_RRDY | \
- NS9750_SER_STAT_A_RHALF | \
- NS9750_SER_STAT_A_RBC | \
- NS9750_SER_STAT_A_DCDI | \
- NS9750_SER_STAT_A_RII | \
- NS9750_SER_STAT_A_DSRI | \
- NS9750_SER_STAT_A_CTSI )
-#define NS9750_SER_STAT_A_TX_COND_ALL ( NS9750_SER_STAT_A_TRDY | \
- NS9750_SER_STAT_A_THALF | \
- NS9750_SER_STAT_A_TBC | \
- NS9750_SER_STAT_A_TEMPTY )
-/* bit rate register */
-
-#define NS9750_SER_BITRATE_EBIT (0x80000000)
-#define NS9750_SER_BITRATE_TMODE (0x40000000)
-#define NS9750_SER_BITRATE_RXSRC (0x20000000)
-#define NS9750_SER_BITRATE_TXSRC (0x10000000)
-#define NS9750_SER_BITRATE_RXEXT (0x08000000)
-#define NS9750_SER_BITRATE_TXEXT (0x04000000)
-#define NS9750_SER_BITRATE_CLKMUX_MA (0x03000000)
-#define NS9750_SER_BITRATE_CLKMUX_XTAL (0x00000000)
-#define NS9750_SER_BITRATE_CLKMUX_BCLK (0x01000000)
-#define NS9750_SER_BITRATE_CLKMUX_OUT1 (0x02000000)
-#define NS9750_SER_BITRATE_CLKMUX_OUT2 (0x03000000)
-#define NS9750_SER_BITRATE_TXCINV (0x00800000)
-#define NS9750_SER_BITRATE_RXCINV (0x00400000)
-#define NS9750_SER_BITRATE_TCDR_MA (0x00180000)
-#define NS9750_SER_BITRATE_TCDR_1 (0x00000000)
-#define NS9750_SER_BITRATE_TCDR_8 (0x00080000)
-#define NS9750_SER_BITRATE_TCDR_16 (0x00100000)
-#define NS9750_SER_BITRATE_TCDR_32 (0x00180000)
-#define NS9750_SER_BITRATE_RCDR_MA (0x00070000)
-#define NS9750_SER_BITRATE_RCDR_1 (0x00000000)
-#define NS9750_SER_BITRATE_RCDR_8 (0x00020000)
-#define NS9750_SER_BITRATE_RCDR_16 (0x00040000)
-#define NS9750_SER_BITRATE_RCDR_32 (0x00060000)
-#define NS9750_SER_BITRATE_TICS (0x00010000)
-#define NS9750_SER_BITRATE_RICS (0x00008000)
-#define NS9750_SER_BITRATE_N_MA (0x00007FFF)
-
-/* receive buffer gap timer */
-
-#define NS9750_SER_RX_BUF_TIMER_TRUN (0x80000000) /* UART and SPI */
-#define NS9750_SER_RX_BUF_TIMER_BT_MA (0x0000FFFF) /* UART and SPI */
-#define NS9750_SER_RX_BUF_TIMER_MAXLEN_MA (0x0000FFFF) /* HDLC only */
-
-/* receive character gap timer */
-
-#define NS9750_SER_RX_CHAR_TIMER_TRUN (0x80000000)
-#define NS9750_SER_RX_CHAR_TIMER_CT_MA (0x000FFFFF)
-
-/* receive match */
-
-#define NS9750_SER_RX_MATCH_RDMB1_MA (0xFF000000)
-#define NS9750_SER_RX_MATCH_RDMB2_MA (0x00FF0000)
-#define NS9750_SER_RX_MATCH_RDMB3_MA (0x0000FF00)
-#define NS9750_SER_RX_MATCH_RDMB4_MA (0x000000FF)
-
-/* receive match mask */
-
-#define NS9750_SER_RX_MATCH_MASK_RDMB1_MA (0xFF000000)
-#define NS9750_SER_RX_MATCH_MASK_RDMB2_MA (0x00FF0000)
-#define NS9750_SER_RX_MATCH_MASK_RDMB3_MA (0x0000FF00)
-#define NS9750_SER_RX_MATCH_MASK_RDMB4_MA (0x000000FF)
-
-#endif /* FS_NS9750_SER_H */
+++ /dev/null
-/***********************************************************************
- *
- * Copyright (C) 2004 by FS Forth-Systeme GmbH.
- * All rights reserved.
- *
- * $Id: ns9750_sys.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
- * @Author: Markus Pietrek
- * @Descr: Definitions for SYS Control Module
- * @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 4
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- ***********************************************************************/
-
-#ifndef FS_NS9750_SYS_H
-#define FS_NS9750_SYS_H
-
-#define NS9750_SYS_MODULE_BASE (0xA0900000)
-
-#define get_sys_reg_addr(c) \
- ((volatile unsigned int *)(NS9750_SYS_MODULE_BASE+(unsigned int) (c)))
-
-/* the register addresses */
-
-#define NS9750_SYS_AHB_GEN (0x0000)
-#define NS9750_SYS_BRC_BASE (0x0004)
-#define NS9750_SYS_AHB_TIMEOUT (0x0014)
-#define NS9750_SYS_AHB_ERROR1 (0x0018)
-#define NS9750_SYS_AHB_ERROR2 (0x001C)
-#define NS9750_SYS_AHB_MON (0x0020)
-#define NS9750_SYS_TIMER_COUNT_BASE (0x0044)
-#define NS9750_SYS_TIMER_READ_BASE (0x0084)
-#define NS9750_SYS_INT_VEC_ADR_BASE (0x00C4)
-#define NS9750_SYS_INT_CFG_BASE (0x0144)
-#define NS9750_SYS_ISRADDR (0x0164)
-#define NS9750_SYS_INT_STAT_ACTIVE (0x0168)
-#define NS9750_SYS_INT_STAT_RAW (0x016C)
-#define NS9750_SYS_TIMER_INT_STAT (0x0170)
-#define NS9750_SYS_SW_WDOG_CFG (0x0174)
-#define NS9750_SYS_SW_WDOG_TIMER (0x0178)
-#define NS9750_SYS_CLOCK (0x017C)
-#define NS9750_SYS_RESET (0x0180)
-#define NS9750_SYS_MISC (0x0184)
-#define NS9750_SYS_PLL (0x0188)
-#define NS9750_SYS_ACT_INT_STAT (0x018C)
-#define NS9750_SYS_TIMER_CTRL_BASE (0x0190)
-#define NS9750_SYS_CS_DYN_BASE_BASE (0x01D0)
-#define NS9750_SYS_CS_DYN_MASK_BASE (0x01D4)
-#define NS9750_SYS_CS_STATIC_BASE_BASE (0x01F0)
-#define NS9750_SYS_CS_STATIC_MASK_BASE (0x01F4)
-#define NS9750_SYS_GEN_ID (0x0210)
-#define NS9750_SYS_EXT_INT_CTRL_BASE (0x0214)
-
-/* the vectored register addresses */
-
-#define NS9750_SYS_TIMER_COUNT(c) (NS9750_SYS_TIMER_COUNT_BASE + (c))
-#define NS9750_SYS_TIMER_READ(c) (NS9750_SYS_TIMER_READ_BASE + (c))
-#define NS9750_SYS_INT_VEC_ADR(c) (NS9750_SYS_INT_VEC_ADR_BASE + (c))
-#define NS9750_SYS_TIMER_CTRL(c) (NS9750_SYS_TIMER_CTRL_BASE + (c))
-/* CS_DYN start with 4 */
-#define NS9750_SYS_CS_DYN_BASE(c) (NS9750_SYS_CS_DYN_BASE_BASE + ((c)-4)*2)
-#define NS9750_SYS_CS_DYN_MASK(c) (NS9750_SYS_CS_DYN_MASK_BASE + ((c)-4)*2)
-/* CS_STATIC start with 0 */
-#define NS9750_SYS_CS_STATIC_BASE(c) (NS9750_SYS_CS_STATIC_BASE_BASE + (c)*2)
-#define NS9750_SYS_CS_STATIC_MASK(c) (NS9750_SYS_CS_STATIC_MASK_BASE + (c)*2)
-#define NS9750_SYS_EXT_INT_CTRL(c) (NS9750_SYS_EXT_INT_CTRL + (c))
-
-/* register bit fields */
-
-#define NS9750_SYS_AHB_GEN_EXMAM (0x00000001)
-
-/* need to be n*8bit to BRC channel */
-#define NS9750_SYS_BRC_CEB (0x00000080)
-#define NS9750_SYS_BRC_BRF_MA (0x00000030)
-#define NS9750_SYS_BRC_BRF_100 (0x00000000)
-#define NS9750_SYS_BRC_BRF_75 (0x00000010)
-#define NS9750_SYS_BRC_BRF_50 (0x00000020)
-#define NS9750_SYS_BRC_BRF_25 (0x00000030)
-
-#define NS9750_SYS_AHB_TIMEOUT_BAT_MA (0xFFFF0000)
-#define NS9750_SYS_AHB_TIMEOUT_BMT_MA (0x0000FFFF)
-
-#define NS9750_SYS_AHB_ERROR2_ABL (0x00040000)
-#define NS9750_SYS_AHB_ERROR2_AER (0x00020000)
-#define NS9750_SYS_AHB_ERROR2_ABM (0x00010000)
-#define NS9750_SYS_AHB_ERROR2_ABA (0x00008000)
-#define NS9750_SYS_AHB_ERROR2_HWRT (0x00004000)
-#define NS9750_SYS_AHB_ERROR2_HMID_MA (0x00003C00)
-#define NS9750_SYS_AHB_ERROR2_HTPC_MA (0x000003C0)
-#define NS9750_SYS_AHB_ERROR2_HSZ_MA (0x00000038)
-#define NS9750_SYS_AHB_ERROR2_RR_MA (0x00000007)
-
-#define NS9750_SYS_AHB_MON_EIC (0x00800000)
-#define NS9750_SYS_AHB_MON_MBII (0x00400000)
-#define NS9750_SYS_AHB_MON_MBL_MA (0x003FFFC0)
-#define NS9750_SYS_AHB_MON_MBLDC (0x00000020)
-#define NS9750_SYS_AHB_MON_SERDC (0x00000010)
-#define NS9750_SYS_AHB_MON_BMTC_MA (0x0000000C)
-#define NS9750_SYS_AHB_MON_BMTC_RECORD (0x00000000)
-#define NS9750_SYS_AHB_MON_BMTC_GEN_IRQ (0x00000004)
-#define NS9750_SYS_AHB_MON_BMTC_GEN_RES (0x00000008)
-#define NS9750_SYS_AHB_MON_BATC_MA (0x00000003)
-#define NS9750_SYS_AHB_MON_BATC_RECORD (0x00000000)
-#define NS9750_SYS_AHB_MON_BATC_GEN_IRQ (0x00000001)
-#define NS9750_SYS_AHB_MON_BATC_GEN_RES (0x00000002)
-
-/* need to be n*8bit to Int Level */
-
-#define NS9750_SYS_INT_CFG_IE (0x00000080)
-#define NS9750_SYS_INT_CFG_IT (0x00000020)
-#define NS9750_SYS_INT_CFG_IAD_MA (0x0000001F)
-
-#define NS9750_SYS_TIMER_INT_STAT_MA (0x0000FFFF)
-
-#define NS9750_SYS_SW_WDOG_CFG_SWWE (0x00000080)
-#define NS9750_SYS_SW_WDOG_CFG_SWWI (0x00000020)
-#define NS9750_SYS_SW_WDOG_CFG_SWWIC (0x00000010)
-#define NS9750_SYS_SW_WDOG_CFG_SWTCS_MA (0x00000007)
-#define NS9750_SYS_SW_WDOG_CFG_SWTCS_2 (0x00000000)
-#define NS9750_SYS_SW_WDOG_CFG_SWTCS_4 (0x00000001)
-#define NS9750_SYS_SW_WDOG_CFG_SWTCS_8 (0x00000002)
-#define NS9750_SYS_SW_WDOG_CFG_SWTCS_16 (0x00000003)
-#define NS9750_SYS_SW_WDOG_CFG_SWTCS_32 (0x00000004)
-#define NS9750_SYS_SW_WDOG_CFG_SWTCS_64 (0x00000005)
-
-#define NS9750_SYS_CLOCK_LPCS_MA (0x00000380)
-#define NS9750_SYS_CLOCK_LPCS_1 (0x00000000)
-#define NS9750_SYS_CLOCK_LPCS_2 (0x00000080)
-#define NS9750_SYS_CLOCK_LPCS_4 (0x00000100)
-#define NS9750_SYS_CLOCK_LPCS_8 (0x00000180)
-#define NS9750_SYS_CLOCK_LPCS_EXT (0x00000200)
-#define NS9750_SYS_CLOCK_BBC (0x00000040)
-#define NS9750_SYS_CLOCK_LCC (0x00000020)
-#define NS9750_SYS_CLOCK_MCC (0x00000010)
-#define NS9750_SYS_CLOCK_PARBC (0x00000008)
-#define NS9750_SYS_CLOCK_PC (0x00000004)
-#define NS9750_SYS_CLOCK_MACC (0x00000001)
-
-#define NS9750_SYS_RESET_SR (0x80000000)
-#define NS9750_SYS_RESET_I2CW (0x00100000)
-#define NS9750_SYS_RESET_CSE (0x00080000)
-#define NS9750_SYS_RESET_SMWE (0x00040000)
-#define NS9750_SYS_RESET_EWE (0x00020000)
-#define NS9750_SYS_RESET_PI3WE (0x00010000)
-#define NS9750_SYS_RESET_BBT (0x00000040)
-#define NS9750_SYS_RESET_LCDC (0x00000020)
-#define NS9750_SYS_RESET_MEMC (0x00000010)
-#define NS9750_SYS_RESET_PCIAR (0x00000008)
-#define NS9750_SYS_RESET_PCIM (0x00000004)
-#define NS9750_SYS_RESET_MACM (0x00000001)
-
-#define NS9750_SYS_MISC_REV_MA (0xFF000000)
-#define NS9750_SYS_MISC_PCIA (0x00002000)
-#define NS9750_SYS_MISC_VDIS (0x00001000)
-#define NS9750_SYS_MISC_BMM (0x00000800)
-#define NS9750_SYS_MISC_CS1DB (0x00000400)
-#define NS9750_SYS_MISC_CS1DW_MA (0x00000300)
-#define NS9750_SYS_MISC_MCCM (0x00000080)
-#define NS9750_SYS_MISC_PMSS (0x00000040)
-#define NS9750_SYS_MISC_CS1P (0x00000020)
-#define NS9750_SYS_MISC_ENDM (0x00000008)
-#define NS9750_SYS_MISC_MBAR (0x00000004)
-#define NS9750_SYS_MISC_IRAM0 (0x00000001)
-
-#define NS9750_SYS_PLL_PLLBS (0x02000000)
-#define NS9750_SYS_PLL_PLLFS_MA (0x01800000)
-#define NS9750_SYS_PLL_PLLIS_MA (0x00600000)
-#define NS9750_SYS_PLL_PLLND_MA (0x001F0000)
-#define NS9750_SYS_PLL_PLLSW (0x00008000)
-#define NS9750_SYS_PLL_PLLBSSW (0x00000200)
-#define NS9750_SYS_PLL_FSEL_MA (0x00000180)
-#define NS9750_SYS_PLL_CPCC_MA (0x00000060)
-#define NS9750_SYS_PLL_NDSW_MA (0x0000001F)
-
-#define NS9750_SYS_ACT_INT_STAT_MA (0x0000FFFF)
-
-#define NS9750_SYS_TIMER_CTRL_TEN (0x00008000)
-#define NS9750_SYS_TIMER_CTRL_INTC (0x00000200)
-#define NS9750_SYS_TIMER_CTRL_TLCS_MA (0x000001C0)
-#define NS9750_SYS_TIMER_CTRL_TLCS_1 (0x00000000)
-#define NS9750_SYS_TIMER_CTRL_TLCS_2 (0x00000040)
-#define NS9750_SYS_TIMER_CTRL_TLCS_4 (0x00000080)
-#define NS9750_SYS_TIMER_CTRL_TLCS_8 (0x000000C0)
-#define NS9750_SYS_TIMER_CTRL_TLCS_16 (0x00000100)
-#define NS9750_SYS_TIMER_CTRL_TLCS_32 (0x00000140)
-#define NS9750_SYS_TIMER_CTRL_TLCS_64 (0x00000180)
-#define NS9750_SYS_TIMER_CTRL_TLCS_EXT (0x000001C0)
-#define NS9750_SYS_TIMER_CTRL_TM_MA (0x00000030)
-#define NS9750_SYS_TIMER_CTRL_TM_INT (0x00000000)
-#define NS9750_SYS_TIMER_CTRL_TM_LOW (0x00000010)
-#define NS9750_SYS_TIMER_CTRL_TM_HIGH (0x00000020)
-#define NS9750_SYS_TIMER_CTRL_INTS (0x00000008)
-#define NS9750_SYS_TIMER_CTRL_UDS (0x00000004)
-#define NS9750_SYS_TIMER_CTRL_TSZ (0x00000002)
-#define NS9750_SYS_TIMER_CTRL_REN (0x00000001)
-
-#define NS9750_SYS_EXT_INT_CTRL_STS (0x00000008)
-#define NS9750_SYS_EXT_INT_CTRL_CLR (0x00000004)
-#define NS9750_SYS_EXT_INT_CTRL_PLTY (0x00000002)
-#define NS9750_SYS_EXT_INT_CTRL_LVEDG (0x00000001)
-
-#endif /* FS_NS9750_SYS_H */
+++ /dev/null
-/*
- * cirrus.h 1.4 1999/10/25 20:03:34
- *
- * The contents of this file are subject to the Mozilla Public License
- * Version 1.1 (the "License"); you may not use this file except in
- * compliance with the License. You may obtain a copy of the License
- * at http://www.mozilla.org/MPL/
- *
- * Software distributed under the License is distributed on an "AS IS"
- * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
- * the License for the specific language governing rights and
- * limitations under the License.
- *
- * The initial developer of the original code is David A. Hinds
- * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
- * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
- *
- * Alternatively, the contents of this file may be used under the
- * terms of the GNU General Public License version 2 (the "GPL"), in which
- * case the provisions of the GPL are applicable instead of the
- * above. If you wish to allow the use of your version of this file
- * only under the terms of the GPL and not to allow others to use
- * your version of this file under the MPL, indicate your decision by
- * deleting the provisions above and replace them with the notice and
- * other provisions required by the GPL. If you do not delete the
- * provisions above, a recipient may use your version of this file
- * under either the MPL or the GPL.
- */
-
-#ifndef _LINUX_CIRRUS_H
-#define _LINUX_CIRRUS_H
-
-#ifndef PCI_VENDOR_ID_CIRRUS
-#define PCI_VENDOR_ID_CIRRUS 0x1013
-#endif
-#ifndef PCI_DEVICE_ID_CIRRUS_6729
-#define PCI_DEVICE_ID_CIRRUS_6729 0x1100
-#endif
-#ifndef PCI_DEVICE_ID_CIRRUS_6832
-#define PCI_DEVICE_ID_CIRRUS_6832 0x1110
-#endif
-
-#define PD67_MISC_CTL_1 0x16 /* Misc control 1 */
-#define PD67_FIFO_CTL 0x17 /* FIFO control */
-#define PD67_MISC_CTL_2 0x1E /* Misc control 2 */
-#define PD67_CHIP_INFO 0x1f /* Chip information */
-#define PD67_ATA_CTL 0x026 /* 6730: ATA control */
-#define PD67_EXT_INDEX 0x2e /* Extension index */
-#define PD67_EXT_DATA 0x2f /* Extension data */
-
-/* PD6722 extension registers -- indexed in PD67_EXT_INDEX */
-#define PD67_DATA_MASK0 0x01 /* Data mask 0 */
-#define PD67_DATA_MASK1 0x02 /* Data mask 1 */
-#define PD67_DMA_CTL 0x03 /* DMA control */
-
-/* PD6730 extension registers -- indexed in PD67_EXT_INDEX */
-#define PD67_EXT_CTL_1 0x03 /* Extension control 1 */
-#define PD67_MEM_PAGE(n) ((n)+5) /* PCI window bits 31:24 */
-#define PD67_EXTERN_DATA 0x0a
-#define PD67_MISC_CTL_3 0x25
-#define PD67_SMB_PWR_CTL 0x26
-
-/* I/O window address offset */
-#define PD67_IO_OFF(w) (0x36+((w)<<1))
-
-/* Timing register sets */
-#define PD67_TIME_SETUP(n) (0x3a + 3*(n))
-#define PD67_TIME_CMD(n) (0x3b + 3*(n))
-#define PD67_TIME_RECOV(n) (0x3c + 3*(n))
-
-/* Flags for PD67_MISC_CTL_1 */
-#define PD67_MC1_5V_DET 0x01 /* 5v detect */
-#define PD67_MC1_MEDIA_ENA 0x01 /* 6730: Multimedia enable */
-#define PD67_MC1_VCC_3V 0x02 /* 3.3v Vcc */
-#define PD67_MC1_PULSE_MGMT 0x04
-#define PD67_MC1_PULSE_IRQ 0x08
-#define PD67_MC1_SPKR_ENA 0x10
-#define PD67_MC1_INPACK_ENA 0x80
-
-/* Flags for PD67_FIFO_CTL */
-#define PD67_FIFO_EMPTY 0x80
-
-/* Flags for PD67_MISC_CTL_2 */
-#define PD67_MC2_FREQ_BYPASS 0x01
-#define PD67_MC2_DYNAMIC_MODE 0x02
-#define PD67_MC2_SUSPEND 0x04
-#define PD67_MC2_5V_CORE 0x08
-#define PD67_MC2_LED_ENA 0x10 /* IRQ 12 is LED enable */
-#define PD67_MC2_FAST_PCI 0x10 /* 6729: PCI bus > 25 MHz */
-#define PD67_MC2_3STATE_BIT7 0x20 /* Floppy change bit */
-#define PD67_MC2_DMA_MODE 0x40
-#define PD67_MC2_IRQ15_RI 0x80 /* IRQ 15 is ring enable */
-
-/* Flags for PD67_CHIP_INFO */
-#define PD67_INFO_SLOTS 0x20 /* 0 = 1 slot, 1 = 2 slots */
-#define PD67_INFO_CHIP_ID 0xc0
-#define PD67_INFO_REV 0x1c
-
-/* Fields in PD67_TIME_* registers */
-#define PD67_TIME_SCALE 0xc0
-#define PD67_TIME_SCALE_1 0x00
-#define PD67_TIME_SCALE_16 0x40
-#define PD67_TIME_SCALE_256 0x80
-#define PD67_TIME_SCALE_4096 0xc0
-#define PD67_TIME_MULT 0x3f
-
-/* Fields in PD67_DMA_CTL */
-#define PD67_DMA_MODE 0xc0
-#define PD67_DMA_OFF 0x00
-#define PD67_DMA_DREQ_INPACK 0x40
-#define PD67_DMA_DREQ_WP 0x80
-#define PD67_DMA_DREQ_BVD2 0xc0
-#define PD67_DMA_PULLUP 0x20 /* Disable socket pullups? */
-
-/* Fields in PD67_EXT_CTL_1 */
-#define PD67_EC1_VCC_PWR_LOCK 0x01
-#define PD67_EC1_AUTO_PWR_CLEAR 0x02
-#define PD67_EC1_LED_ENA 0x04
-#define PD67_EC1_INV_CARD_IRQ 0x08
-#define PD67_EC1_INV_MGMT_IRQ 0x10
-#define PD67_EC1_PULLUP_CTL 0x20
-
-/* Fields in PD67_MISC_CTL_3 */
-#define PD67_MC3_IRQ_MASK 0x03
-#define PD67_MC3_IRQ_PCPCI 0x00
-#define PD67_MC3_IRQ_EXTERN 0x01
-#define PD67_MC3_IRQ_PCIWAY 0x02
-#define PD67_MC3_IRQ_PCI 0x03
-#define PD67_MC3_PWR_MASK 0x0c
-#define PD67_MC3_PWR_SERIAL 0x00
-#define PD67_MC3_PWR_TI2202 0x08
-#define PD67_MC3_PWR_SMB 0x0c
-
-/* Register definitions for Cirrus PD6832 PCI-to-CardBus bridge */
-
-/* PD6832 extension registers -- indexed in PD67_EXT_INDEX */
-#define PD68_EXT_CTL_2 0x0b
-#define PD68_PCI_SPACE 0x22
-#define PD68_PCCARD_SPACE 0x23
-#define PD68_WINDOW_TYPE 0x24
-#define PD68_EXT_CSC 0x2e
-#define PD68_MISC_CTL_4 0x2f
-#define PD68_MISC_CTL_5 0x30
-#define PD68_MISC_CTL_6 0x31
-
-/* Extra flags in PD67_MISC_CTL_3 */
-#define PD68_MC3_HW_SUSP 0x10
-#define PD68_MC3_MM_EXPAND 0x40
-#define PD68_MC3_MM_ARM 0x80
-
-/* Bridge Control Register */
-#define PD6832_BCR_MGMT_IRQ_ENA 0x0800
-
-/* Socket Number Register */
-#define PD6832_SOCKET_NUMBER 0x004c /* 8 bit */
-
-
-typedef struct cirrus_state_t {
- u_char misc1, misc2;
- u_char timer[6];
-} cirrus_state_t;
-
-/* Cirrus options */
-static int has_dma = -1;
-static int has_led = -1;
-static int has_ring = -1;
-static int dynamic_mode = 0;
-static int freq_bypass = -1;
-#ifdef CONFIG_CPC45
-static int setup_time = 2;
-static int cmd_time = 6;
-static int recov_time = 1;
-#else
-static int setup_time = -1;
-static int cmd_time = -1;
-static int recov_time = -1;
-#endif
-
-
-#endif /* _LINUX_CIRRUS_H */
+++ /dev/null
-/*
- * i82365.h 1.21 2001/08/24 12:15:33
- *
- * The contents of this file are subject to the Mozilla Public License
- * Version 1.1 (the "License"); you may not use this file except in
- * compliance with the License. You may obtain a copy of the License
- * at http://www.mozilla.org/MPL/
- *
- * Software distributed under the License is distributed on an "AS IS"
- * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
- * the License for the specific language governing rights and
- * limitations under the License.
- *
- * The initial developer of the original code is David A. Hinds
- * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
- * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
- *
- * Alternatively, the contents of this file may be used under the
- * terms of the GNU General Public License version 2 (the "GPL"), in
- * which case the provisions of the GPL are applicable instead of the
- * above. If you wish to allow the use of your version of this file
- * only under the terms of the GPL and not to allow others to use
- * your version of this file under the MPL, indicate your decision by
- * deleting the provisions above and replace them with the notice and
- * other provisions required by the GPL. If you do not delete the
- * provisions above, a recipient may use your version of this file
- * under either the MPL or the GPL.
- */
-
-#ifndef _LINUX_I82365_H
-#define _LINUX_I82365_H
-
-/* register definitions for the Intel 82365SL PCMCIA controller */
-
-/* Offsets for PCIC registers */
-#define I365_IDENT 0x00 /* Identification and revision */
-#define I365_STATUS 0x01 /* Interface status */
-#define I365_POWER 0x02 /* Power and RESETDRV control */
-#define I365_INTCTL 0x03 /* Interrupt and general control */
-#define I365_CSC 0x04 /* Card status change */
-#define I365_CSCINT 0x05 /* Card status change interrupt control */
-#define I365_ADDRWIN 0x06 /* Address window enable */
-#define I365_IOCTL 0x07 /* I/O control */
-#define I365_GENCTL 0x16 /* Card detect and general control */
-#define I365_GBLCTL 0x1E /* Global control register */
-
-/* Offsets for I/O and memory window registers */
-#define I365_IO(map) (0x08+((map)<<2))
-#define I365_MEM(map) (0x10+((map)<<3))
-#define I365_W_START 0
-#define I365_W_STOP 2
-#define I365_W_OFF 4
-
-/* Flags for I365_STATUS */
-#define I365_CS_BVD1 0x01
-#define I365_CS_STSCHG 0x01
-#define I365_CS_BVD2 0x02
-#define I365_CS_SPKR 0x02
-#define I365_CS_DETECT 0x0C
-#define I365_CS_WRPROT 0x10
-#define I365_CS_READY 0x20 /* Inverted */
-#define I365_CS_POWERON 0x40
-#define I365_CS_GPI 0x80
-
-/* Flags for I365_POWER */
-#define I365_PWR_OFF 0x00 /* Turn off the socket */
-#define I365_PWR_OUT 0x80 /* Output enable */
-#define I365_PWR_NORESET 0x40 /* Disable RESETDRV on resume */
-#define I365_PWR_AUTO 0x20 /* Auto pwr switch enable */
-#define I365_VCC_MASK 0x18 /* Mask for turning off Vcc */
-/* There are different layouts for B-step and DF-step chips: the B
- step has independent Vpp1/Vpp2 control, and the DF step has only
- Vpp1 control, plus 3V control */
-#define I365_VCC_5V 0x10 /* Vcc = 5.0v */
-#define I365_VCC_3V 0x18 /* Vcc = 3.3v */
-#define I365_VPP2_MASK 0x0c /* Mask for turning off Vpp2 */
-#define I365_VPP2_5V 0x04 /* Vpp2 = 5.0v */
-#define I365_VPP2_12V 0x08 /* Vpp2 = 12.0v */
-#define I365_VPP1_MASK 0x03 /* Mask for turning off Vpp1 */
-#define I365_VPP1_5V 0x01 /* Vpp2 = 5.0v */
-#define I365_VPP1_12V 0x02 /* Vpp2 = 12.0v */
-
-/* Flags for I365_INTCTL */
-#define I365_RING_ENA 0x80
-#define I365_PC_RESET 0x40
-#define I365_PC_IOCARD 0x20
-#define I365_INTR_ENA 0x10
-#define I365_IRQ_MASK 0x0F
-
-/* Flags for I365_CSC and I365_CSCINT*/
-#define I365_CSC_BVD1 0x01
-#define I365_CSC_STSCHG 0x01
-#define I365_CSC_BVD2 0x02
-#define I365_CSC_READY 0x04
-#define I365_CSC_DETECT 0x08
-#define I365_CSC_ANY 0x0F
-#define I365_CSC_GPI 0x10
-
-/* Flags for I365_ADDRWIN */
-#define I365_ADDR_MEMCS16 0x20
-#define I365_ENA_IO(map) (0x40 << (map))
-#define I365_ENA_MEM(map) (0x01 << (map))
-
-/* Flags for I365_IOCTL */
-#define I365_IOCTL_MASK(map) (0x0F << (map<<2))
-#define I365_IOCTL_WAIT(map) (0x08 << (map<<2))
-#define I365_IOCTL_0WS(map) (0x04 << (map<<2))
-#define I365_IOCTL_IOCS16(map) (0x02 << (map<<2))
-#define I365_IOCTL_16BIT(map) (0x01 << (map<<2))
-
-/* Flags for I365_GENCTL */
-#define I365_CTL_16DELAY 0x01
-#define I365_CTL_RESET 0x02
-#define I365_CTL_GPI_ENA 0x04
-#define I365_CTL_GPI_CTL 0x08
-#define I365_CTL_RESUME 0x10
-#define I365_CTL_SW_IRQ 0x20
-
-/* Flags for I365_GBLCTL */
-#define I365_GBL_PWRDOWN 0x01
-#define I365_GBL_CSC_LEV 0x02
-#define I365_GBL_WRBACK 0x04
-#define I365_GBL_IRQ_0_LEV 0x08
-#define I365_GBL_IRQ_1_LEV 0x10
-
-/* Flags for memory window registers */
-#define I365_MEM_16BIT 0x8000 /* In memory start high byte */
-#define I365_MEM_0WS 0x4000
-#define I365_MEM_WS1 0x8000 /* In memory stop high byte */
-#define I365_MEM_WS0 0x4000
-#define I365_MEM_WRPROT 0x8000 /* In offset high byte */
-#define I365_MEM_REG 0x4000
-
-#define I365_REG(slot, reg) (((slot) << 6) | (reg))
-
-/* Default ISA interrupt mask */
-#define I365_ISA_IRQ_MASK 0xdeb8 /* irq's 3-5,7,9-12,14,15 */
-
-/* Device ID's for PCI-to-PCMCIA bridges */
-
-#ifndef PCI_VENDOR_ID_INTEL
-#define PCI_VENDOR_ID_INTEL 0x8086
-#endif
-#ifndef PCI_DEVICE_ID_INTEL_82092AA_0
-#define PCI_DEVICE_ID_INTEL_82092AA_0 0x1221
-#endif
-#ifndef PCI_VENDOR_ID_OMEGA
-#define PCI_VENDOR_ID_OMEGA 0x119b
-#endif
-#ifndef PCI_DEVICE_ID_OMEGA_82C092G
-#define PCI_DEVICE_ID_OMEGA_82C092G 0x1221
-#endif
-
-#endif /* _LINUX_I82365_H */
+++ /dev/null
-/*
- * ss.h 1.31 2001/08/24 12:16:13
- *
- * The contents of this file are subject to the Mozilla Public License
- * Version 1.1 (the "License"); you may not use this file except in
- * compliance with the License. You may obtain a copy of the License
- * at http://www.mozilla.org/MPL/
- *
- * Software distributed under the License is distributed on an "AS IS"
- * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
- * the License for the specific language governing rights and
- * limitations under the License.
- *
- * The initial developer of the original code is David A. Hinds
- * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
- * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
- *
- * Alternatively, the contents of this file may be used under the
- * terms of the GNU General Public License version 2 (the "GPL"), in
- * which case the provisions of the GPL are applicable instead of the
- * above. If you wish to allow the use of your version of this file
- * only under the terms of the GPL and not to allow others to use
- * your version of this file under the MPL, indicate your decision by
- * deleting the provisions above and replace them with the notice and
- * other provisions required by the GPL. If you do not delete the
- * provisions above, a recipient may use your version of this file
- * under either the MPL or the GPL.
- */
-
-#ifndef _LINUX_SS_H
-#define _LINUX_SS_H
-
-/* For RegisterCallback */
-typedef struct ss_callback_t {
- void (*handler)(void *info, u_int events);
- void *info;
-} ss_callback_t;
-
-/* Definitions for card status flags for GetStatus */
-#define SS_WRPROT 0x0001
-#define SS_CARDLOCK 0x0002
-#define SS_EJECTION 0x0004
-#define SS_INSERTION 0x0008
-#define SS_BATDEAD 0x0010
-#define SS_BATWARN 0x0020
-#define SS_READY 0x0040
-#define SS_DETECT 0x0080
-#define SS_POWERON 0x0100
-#define SS_GPI 0x0200
-#define SS_STSCHG 0x0400
-#define SS_CARDBUS 0x0800
-#define SS_3VCARD 0x1000
-#define SS_XVCARD 0x2000
-#define SS_PENDING 0x4000
-
-/* for InquireSocket */
-typedef struct socket_cap_t {
- u_int features;
- u_int irq_mask;
- u_int map_size;
- u_char pci_irq;
- u_char cardbus;
- struct pci_bus *cb_bus;
- struct bus_operations *bus;
-} socket_cap_t;
-
-/* InquireSocket capabilities */
-#define SS_CAP_PAGE_REGS 0x0001
-#define SS_CAP_VIRTUAL_BUS 0x0002
-#define SS_CAP_MEM_ALIGN 0x0004
-#define SS_CAP_STATIC_MAP 0x0008
-#define SS_CAP_PCCARD 0x4000
-#define SS_CAP_CARDBUS 0x8000
-
-/* for GetSocket, SetSocket */
-typedef struct socket_state_t {
- u_int flags;
- u_int csc_mask;
- u_char Vcc, Vpp;
- u_char io_irq;
-} socket_state_t;
-
-/* Socket configuration flags */
-#define SS_PWR_AUTO 0x0010
-#define SS_IOCARD 0x0020
-#define SS_RESET 0x0040
-#define SS_DMA_MODE 0x0080
-#define SS_SPKR_ENA 0x0100
-#define SS_OUTPUT_ENA 0x0200
-#define SS_ZVCARD 0x0400
-
-/* Flags for I/O port and memory windows */
-#define MAP_ACTIVE 0x01
-#define MAP_16BIT 0x02
-#define MAP_AUTOSZ 0x04
-#define MAP_0WS 0x08
-#define MAP_WRPROT 0x10
-#define MAP_ATTRIB 0x20
-#define MAP_USE_WAIT 0x40
-#define MAP_PREFETCH 0x80
-
-/* Use this just for bridge windows */
-#define MAP_IOSPACE 0x20
-
-typedef struct pccard_io_map {
- u_char map;
- u_char flags;
- u_short speed;
- u_short start, stop;
-} pccard_io_map;
-
-typedef struct pccard_mem_map {
- u_char map;
- u_char flags;
- u_short speed;
- u_long sys_start, sys_stop;
- u_int card_start;
-} pccard_mem_map;
-
-typedef struct cb_bridge_map {
- u_char map;
- u_char flags;
- u_int start, stop;
-} cb_bridge_map;
-
-enum ss_service {
- SS_RegisterCallback, SS_InquireSocket,
- SS_GetStatus, SS_GetSocket, SS_SetSocket,
- SS_GetIOMap, SS_SetIOMap, SS_GetMemMap, SS_SetMemMap,
- SS_GetBridge, SS_SetBridge, SS_ProcSetup
-};
-
-#endif /* _LINUX_SS_H */
+++ /dev/null
-/*
- * ti113x.h 1.31 2002/05/12 18:19:47
- *
- * The contents of this file are subject to the Mozilla Public License
- * Version 1.1 (the "License"); you may not use this file except in
- * compliance with the License. You may obtain a copy of the License
- * at http://www.mozilla.org/MPL/
- *
- * Software distributed under the License is distributed on an "AS IS"
- * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
- * the License for the specific language governing rights and
- * limitations under the License.
- *
- * The initial developer of the original code is David A. Hinds
- * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
- * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
- *
- * Alternatively, the contents of this file may be used under the
- * terms of the GNU General Public License version 2 (the "GPL"), in
- * which case the provisions of the GPL are applicable instead of the
- * above. If you wish to allow the use of your version of this file
- * only under the terms of the GPL and not to allow others to use
- * your version of this file under the MPL, indicate your decision by
- * deleting the provisions above and replace them with the notice and
- * other provisions required by the GPL. If you do not delete the
- * provisions above, a recipient may use your version of this file
- * under either the MPL or the GPL.
- */
-
-#ifndef _LINUX_TI113X_H
-#define _LINUX_TI113X_H
-
-#ifndef PCI_VENDOR_ID_TI
-#define PCI_VENDOR_ID_TI 0x104c
-#endif
-
-#ifndef PCI_DEVICE_ID_TI_1130
-#define PCI_DEVICE_ID_TI_1130 0xac12
-#endif
-#ifndef PCI_DEVICE_ID_TI_1031
-#define PCI_DEVICE_ID_TI_1031 0xac13
-#endif
-#ifndef PCI_DEVICE_ID_TI_1131
-#define PCI_DEVICE_ID_TI_1131 0xac15
-#endif
-#ifndef PCI_DEVICE_ID_TI_1210
-#define PCI_DEVICE_ID_TI_1210 0xac1a
-#endif
-#ifndef PCI_DEVICE_ID_TI_1211
-#define PCI_DEVICE_ID_TI_1211 0xac1e
-#endif
-#ifndef PCI_DEVICE_ID_TI_1220
-#define PCI_DEVICE_ID_TI_1220 0xac17
-#endif
-#ifndef PCI_DEVICE_ID_TI_1221
-#define PCI_DEVICE_ID_TI_1221 0xac19
-#endif
-#ifndef PCI_DEVICE_ID_TI_1250A
-#define PCI_DEVICE_ID_TI_1250A 0xac16
-#endif
-#ifndef PCI_DEVICE_ID_TI_1225
-#define PCI_DEVICE_ID_TI_1225 0xac1c
-#endif
-#ifndef PCI_DEVICE_ID_TI_1251A
-#define PCI_DEVICE_ID_TI_1251A 0xac1d
-#endif
-#ifndef PCI_DEVICE_ID_TI_1251B
-#define PCI_DEVICE_ID_TI_1251B 0xac1f
-#endif
-#ifndef PCI_DEVICE_ID_TI_1410
-#define PCI_DEVICE_ID_TI_1410 0xac50
-#endif
-#ifndef PCI_DEVICE_ID_TI_1420
-#define PCI_DEVICE_ID_TI_1420 0xac51
-#endif
-#ifndef PCI_DEVICE_ID_TI_1450
-#define PCI_DEVICE_ID_TI_1450 0xac1b
-#endif
-#ifndef PCI_DEVICE_ID_TI_1451
-#define PCI_DEVICE_ID_TI_1451 0xac52
-#endif
-#ifndef PCI_DEVICE_ID_TI_1510
-#define PCI_DEVICE_ID_TI_1510 0xac56
-#endif
-#ifndef PCI_DEVICE_ID_TI_4410
-#define PCI_DEVICE_ID_TI_4410 0xac41
-#endif
-#ifndef PCI_DEVICE_ID_TI_4450
-#define PCI_DEVICE_ID_TI_4450 0xac40
-#endif
-#ifndef PCI_DEVICE_ID_TI_4451
-#define PCI_DEVICE_ID_TI_4451 0xac42
-#endif
-
-/* Register definitions for TI 113X PCI-to-CardBus bridges */
-
-/* System Control Register */
-#define TI113X_SYSTEM_CONTROL 0x80 /* 32 bit */
-#define TI113X_SCR_SMIROUTE 0x04000000
-#define TI113X_SCR_SMISTATUS 0x02000000
-#define TI113X_SCR_SMIENB 0x01000000
-#define TI113X_SCR_VCCPROT 0x00200000
-#define TI113X_SCR_REDUCEZV 0x00100000
-#define TI113X_SCR_CDREQEN 0x00080000
-#define TI113X_SCR_CDMACHAN 0x00070000
-#define TI113X_SCR_SOCACTIVE 0x00002000
-#define TI113X_SCR_PWRSTREAM 0x00000800
-#define TI113X_SCR_DELAYUP 0x00000400
-#define TI113X_SCR_DELAYDOWN 0x00000200
-#define TI113X_SCR_INTERROGATE 0x00000100
-#define TI113X_SCR_CLKRUN_SEL 0x00000080
-#define TI113X_SCR_PWRSAVINGS 0x00000040
-#define TI113X_SCR_SUBSYSRW 0x00000020
-#define TI113X_SCR_CB_DPAR 0x00000010
-#define TI113X_SCR_CDMA_EN 0x00000008
-#define TI113X_SCR_ASYNC_IRQ 0x00000004
-#define TI113X_SCR_KEEPCLK 0x00000002
-#define TI113X_SCR_CLKRUN_ENA 0x00000001
-
-#define TI122X_SCR_SER_STEP 0xc0000000
-#define TI122X_SCR_INTRTIE 0x20000000
-#define TI122X_SCR_P2CCLK 0x08000000
-#define TI122X_SCR_CBRSVD 0x00400000
-#define TI122X_SCR_MRBURSTDN 0x00008000
-#define TI122X_SCR_MRBURSTUP 0x00004000
-#define TI122X_SCR_RIMUX 0x00000001
-
-/* Multimedia Control Register */
-#define TI1250_MULTIMEDIA_CTL 0x84 /* 8 bit */
-#define TI1250_MMC_ZVOUTEN 0x80
-#define TI1250_MMC_PORTSEL 0x40
-#define TI1250_MMC_ZVEN1 0x02
-#define TI1250_MMC_ZVEN0 0x01
-
-#define TI1250_GENERAL_STATUS 0x85 /* 8 bit */
-#define TI1250_GPIO0_CONTROL 0x88 /* 8 bit */
-#define TI1250_GPIO1_CONTROL 0x89 /* 8 bit */
-#define TI1250_GPIO2_CONTROL 0x8a /* 8 bit */
-#define TI1250_GPIO3_CONTROL 0x8b /* 8 bit */
-#define TI12XX_IRQMUX 0x8c /* 32 bit */
-
-/* Retry Status Register */
-#define TI113X_RETRY_STATUS 0x90 /* 8 bit */
-#define TI113X_RSR_PCIRETRY 0x80
-#define TI113X_RSR_CBRETRY 0x40
-#define TI113X_RSR_TEXP_CBB 0x20
-#define TI113X_RSR_MEXP_CBB 0x10
-#define TI113X_RSR_TEXP_CBA 0x08
-#define TI113X_RSR_MEXP_CBA 0x04
-#define TI113X_RSR_TEXP_PCI 0x02
-#define TI113X_RSR_MEXP_PCI 0x01
-
-/* Card Control Register */
-#define TI113X_CARD_CONTROL 0x91 /* 8 bit */
-#define TI113X_CCR_RIENB 0x80
-#define TI113X_CCR_ZVENABLE 0x40
-#define TI113X_CCR_PCI_IRQ_ENA 0x20
-#define TI113X_CCR_PCI_IREQ 0x10
-#define TI113X_CCR_PCI_CSC 0x08
-#define TI113X_CCR_SPKROUTEN 0x02
-#define TI113X_CCR_IFG 0x01
-
-#define TI1220_CCR_PORT_SEL 0x20
-#define TI122X_CCR_AUD2MUX 0x04
-
-/* Device Control Register */
-#define TI113X_DEVICE_CONTROL 0x92 /* 8 bit */
-#define TI113X_DCR_5V_FORCE 0x40
-#define TI113X_DCR_3V_FORCE 0x20
-#define TI113X_DCR_IMODE_MASK 0x06
-#define TI113X_DCR_IMODE_ISA 0x02
-#define TI113X_DCR_IMODE_SERIAL 0x04
-
-#define TI12XX_DCR_IMODE_PCI_ONLY 0x00
-#define TI12XX_DCR_IMODE_ALL_SERIAL 0x06
-
-/* Buffer Control Register */
-#define TI113X_BUFFER_CONTROL 0x93 /* 8 bit */
-#define TI113X_BCR_CB_READ_DEPTH 0x08
-#define TI113X_BCR_CB_WRITE_DEPTH 0x04
-#define TI113X_BCR_PCI_READ_DEPTH 0x02
-#define TI113X_BCR_PCI_WRITE_DEPTH 0x01
-
-/* Diagnostic Register */
-#define TI1250_DIAGNOSTIC 0x93 /* 8 bit */
-#define TI1250_DIAG_TRUE_VALUE 0x80
-#define TI1250_DIAG_PCI_IREQ 0x40
-#define TI1250_DIAG_PCI_CSC 0x20
-#define TI1250_DIAG_ASYNC_CSC 0x01
-
-/* DMA Registers */
-#define TI113X_DMA_0 0x94 /* 32 bit */
-#define TI113X_DMA_1 0x98 /* 32 bit */
-
-/* ExCA IO offset registers */
-#define TI113X_IO_OFFSET(map) (0x36+((map)<<1))
-
-/* Data structure for tracking vendor-specific state */
-typedef struct ti113x_state_t {
- u32 sysctl; /* TI113X_SYSTEM_CONTROL */
- u8 cardctl; /* TI113X_CARD_CONTROL */
- u8 devctl; /* TI113X_DEVICE_CONTROL */
- u8 diag; /* TI1250_DIAGNOSTIC */
- u32 irqmux; /* TI12XX_IRQMUX */
-} ti113x_state_t;
-
-#define TI_PCIC_ID \
- IS_TI1130, IS_TI1131, IS_TI1031, IS_TI1210, IS_TI1211, \
- IS_TI1220, IS_TI1221, IS_TI1225, IS_TI1250A, IS_TI1251A, \
- IS_TI1251B, IS_TI1410, IS_TI1420, IS_TI1450, IS_TI1451, \
- IS_TI1510, IS_TI4410, IS_TI4450, IS_TI4451
-
-#define TI_PCIC_INFO \
- { "TI 1130", IS_TI|IS_CARDBUS, ID(TI, 1130) }, \
- { "TI 1131", IS_TI|IS_CARDBUS, ID(TI, 1131) }, \
- { "TI 1031", IS_TI|IS_CARDBUS, ID(TI, 1031) }, \
- { "TI 1210", IS_TI|IS_CARDBUS, ID(TI, 1210) }, \
- { "TI 1211", IS_TI|IS_CARDBUS, ID(TI, 1211) }, \
- { "TI 1220", IS_TI|IS_CARDBUS, ID(TI, 1220) }, \
- { "TI 1221", IS_TI|IS_CARDBUS, ID(TI, 1221) }, \
- { "TI 1225", IS_TI|IS_CARDBUS, ID(TI, 1225) }, \
- { "TI 1250A", IS_TI|IS_CARDBUS, ID(TI, 1250A) }, \
- { "TI 1251A", IS_TI|IS_CARDBUS, ID(TI, 1251A) }, \
- { "TI 1251B", IS_TI|IS_CARDBUS, ID(TI, 1251B) }, \
- { "TI 1410", IS_TI|IS_CARDBUS, ID(TI, 1410) }, \
- { "TI 1420", IS_TI|IS_CARDBUS, ID(TI, 1420) }, \
- { "TI 1450", IS_TI|IS_CARDBUS, ID(TI, 1450) }, \
- { "TI 1451", IS_TI|IS_CARDBUS, ID(TI, 1451) }, \
- { "TI 1510", IS_TI|IS_CARDBUS, ID(TI, 1510) }, \
- { "TI 4410", IS_TI|IS_CARDBUS, ID(TI, 4410) }, \
- { "TI 4450", IS_TI|IS_CARDBUS, ID(TI, 4450) }, \
- { "TI 4451", IS_TI|IS_CARDBUS, ID(TI, 4451) }
-
-#endif /* _LINUX_TI113X_H */
+++ /dev/null
-/*
- * yenta.h 1.20 2001/08/24 12:15:34
- *
- * The contents of this file are subject to the Mozilla Public License
- * Version 1.1 (the "License"); you may not use this file except in
- * compliance with the License. You may obtain a copy of the License
- * at http://www.mozilla.org/MPL/
- *
- * Software distributed under the License is distributed on an "AS IS"
- * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
- * the License for the specific language governing rights and
- * limitations under the License.
- *
- * The initial developer of the original code is David A. Hinds
- * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
- * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
- *
- * Alternatively, the contents of this file may be used under the
- * terms of the GNU General Public License version 2 (the "GPL"), in
- * which case the provisions of the GPL are applicable instead of the
- * above. If you wish to allow the use of your version of this file
- * only under the terms of the GPL and not to allow others to use
- * your version of this file under the MPL, indicate your decision by
- * deleting the provisions above and replace them with the notice and
- * other provisions required by the GPL. If you do not delete the
- * provisions above, a recipient may use your version of this file
- * under either the MPL or the GPL.
- */
-
-#ifndef _LINUX_YENTA_H
-#define _LINUX_YENTA_H
-
-/* PCI Configuration Registers */
-
-#define PCI_STATUS_CAPLIST 0x10
-#define PCI_CB_CAPABILITY_POINTER 0x14 /* 8 bit */
-#define PCI_CAPABILITY_ID 0x00 /* 8 bit */
-#define PCI_CAPABILITY_PM 0x01
-#define PCI_NEXT_CAPABILITY 0x01 /* 8 bit */
-#define PCI_PM_CAPABILITIES 0x02 /* 16 bit */
-#define PCI_PMCAP_PME_D3COLD 0x8000
-#define PCI_PMCAP_PME_D3HOT 0x4000
-#define PCI_PMCAP_PME_D2 0x2000
-#define PCI_PMCAP_PME_D1 0x1000
-#define PCI_PMCAP_PME_D0 0x0800
-#define PCI_PMCAP_D2_CAP 0x0400
-#define PCI_PMCAP_D1_CAP 0x0200
-#define PCI_PMCAP_DYN_DATA 0x0100
-#define PCI_PMCAP_DSI 0x0020
-#define PCI_PMCAP_AUX_PWR 0x0010
-#define PCI_PMCAP_PMECLK 0x0008
-#define PCI_PMCAP_VERSION_MASK 0x0007
-#define PCI_PM_CONTROL_STATUS 0x04 /* 16 bit */
-#define PCI_PMCS_PME_STATUS 0x8000
-#define PCI_PMCS_DATASCALE_MASK 0x6000
-#define PCI_PMCS_DATASCALE_SHIFT 13
-#define PCI_PMCS_DATASEL_MASK 0x1e00
-#define PCI_PMCS_DATASEL_SHIFT 9
-#define PCI_PMCS_PME_ENABLE 0x0100
-#define PCI_PMCS_PWR_STATE_MASK 0x0003
-#define PCI_PMCS_PWR_STATE_D0 0x0000
-#define PCI_PMCS_PWR_STATE_D1 0x0001
-#define PCI_PMCS_PWR_STATE_D2 0x0002
-#define PCI_PMCS_PWR_STATE_D3 0x0003
-#define PCI_PM_BRIDGE_EXT 0x06 /* 8 bit */
-#define PCI_PM_DATA 0x07 /* 8 bit */
-
-#define CB_PRIMARY_BUS 0x18 /* 8 bit */
-#define CB_CARDBUS_BUS 0x19 /* 8 bit */
-#define CB_SUBORD_BUS 0x1a /* 8 bit */
-#define CB_LATENCY_TIMER 0x1b /* 8 bit */
-
-#define CB_MEM_BASE(m) (0x1c + 8*(m))
-#define CB_MEM_LIMIT(m) (0x20 + 8*(m))
-#define CB_IO_BASE(m) (0x2c + 8*(m))
-#define CB_IO_LIMIT(m) (0x30 + 8*(m))
-
-#define CB_BRIDGE_CONTROL 0x3e /* 16 bit */
-#define CB_BCR_PARITY_ENA 0x0001
-#define CB_BCR_SERR_ENA 0x0002
-#define CB_BCR_ISA_ENA 0x0004
-#define CB_BCR_VGA_ENA 0x0008
-#define CB_BCR_MABORT 0x0020
-#define CB_BCR_CB_RESET 0x0040
-#define CB_BCR_ISA_IRQ 0x0080
-#define CB_BCR_PREFETCH(m) (0x0100 << (m))
-#define CB_BCR_WRITE_POST 0x0400
-
-#define CB_LEGACY_MODE_BASE 0x44
-
-/* Memory mapped registers */
-
-#define CB_SOCKET_EVENT 0x0000
-#define CB_SE_CSTSCHG 0x00000001
-#define CB_SE_CCD 0x00000006
-#define CB_SE_CCD1 0x00000002
-#define CB_SE_CCD2 0x00000004
-#define CB_SE_PWRCYCLE 0x00000008
-
-#define CB_SOCKET_MASK 0x0004
-#define CB_SM_CSTSCHG 0x00000001
-#define CB_SM_CCD 0x00000006
-#define CB_SM_PWRCYCLE 0x00000008
-
-#define CB_SOCKET_STATE 0x0008
-#define CB_SS_CSTSCHG 0x00000001
-#define CB_SS_CCD 0x00000006
-#define CB_SS_CCD1 0x00000002
-#define CB_SS_CCD2 0x00000004
-#define CB_SS_PWRCYCLE 0x00000008
-#define CB_SS_16BIT 0x00000010
-#define CB_SS_32BIT 0x00000020
-#define CB_SS_CINT 0x00000040
-#define CB_SS_BADCARD 0x00000080
-#define CB_SS_DATALOST 0x00000100
-#define CB_SS_BADVCC 0x00000200
-#define CB_SS_5VCARD 0x00000400
-#define CB_SS_3VCARD 0x00000800
-#define CB_SS_XVCARD 0x00001000
-#define CB_SS_YVCARD 0x00002000
-#define CB_SS_VSENSE 0x00003c86
-#define CB_SS_5VSOCKET 0x10000000
-#define CB_SS_3VSOCKET 0x20000000
-#define CB_SS_XVSOCKET 0x40000000
-#define CB_SS_YVSOCKET 0x80000000
-
-#define CB_SOCKET_FORCE 0x000c
-#define CB_SF_CVSTEST 0x00004000
-
-#define CB_SOCKET_CONTROL 0x0010
-#define CB_SC_VPP_MASK 0x00000007
-#define CB_SC_VPP_OFF 0x00000000
-#define CB_SC_VPP_12V 0x00000001
-#define CB_SC_VPP_5V 0x00000002
-#define CB_SC_VPP_3V 0x00000003
-#define CB_SC_VPP_XV 0x00000004
-#define CB_SC_VPP_YV 0x00000005
-#define CB_SC_VCC_MASK 0x00000070
-#define CB_SC_VCC_OFF 0x00000000
-#define CB_SC_VCC_5V 0x00000020
-#define CB_SC_VCC_3V 0x00000030
-#define CB_SC_VCC_XV 0x00000040
-#define CB_SC_VCC_YV 0x00000050
-#define CB_SC_CCLK_STOP 0x00000080
-
-#define CB_SOCKET_POWER 0x0020
-#define CB_SP_CLK_CTRL 0x00000001
-#define CB_SP_CLK_CTRL_ENA 0x00010000
-#define CB_SP_CLK_MODE 0x01000000
-#define CB_SP_ACCESS 0x02000000
-
-/* Address bits 31..24 for memory windows for 16-bit cards,
- accessable only by memory mapping the 16-bit register set */
-#define CB_MEM_PAGE(map) (0x40 + (map))
-
-#endif /* _LINUX_YENTA_H */
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