]> git.sur5r.net Git - u-boot/commitdiff
mx6sxsabresd: Add PFUZE100 PMIC support
authorFabio Estevam <fabio.estevam@freescale.com>
Wed, 9 Jul 2014 19:13:30 +0000 (16:13 -0300)
committerStefano Babic <sbabic@denx.de>
Wed, 23 Jul 2014 10:25:40 +0000 (12:25 +0200)
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
board/freescale/mx6sxsabresd/mx6sxsabresd.c
include/configs/mx6sxsabresd.h

index ff4c88ffa47b7a3d73ae1499e0005765d0637eb6..24d6a5196ebd64a7ba14c4be87f4100a382001d5 100644 (file)
 #include <asm/gpio.h>
 #include <asm/imx-common/iomux-v3.h>
 #include <asm/io.h>
+#include <asm/imx-common/mxc_i2c.h>
 #include <linux/sizes.h>
 #include <common.h>
 #include <fsl_esdhc.h>
 #include <mmc.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -29,6 +33,11 @@ DECLARE_GLOBAL_DATA_PTR;
        PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
        PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
+#define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
+       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
+       PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
+       PAD_CTL_ODE)
+
 int dram_init(void)
 {
        gd->ram_size = PHYS_SDRAM_SIZE;
@@ -56,9 +65,77 @@ static void setup_iomux_uart(void)
        imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 }
 
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC */
+struct i2c_pads_info i2c_pad_info1 = {
+       .scl = {
+               .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
+               .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
+               .gp = IMX_GPIO_NR(1, 0),
+       },
+       .sda = {
+               .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
+               .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
+               .gp = IMX_GPIO_NR(1, 1),
+       },
+};
+
+static int pfuze_init(void)
+{
+       struct pmic *p;
+       int ret;
+       unsigned int reg;
+
+       ret = power_pfuze100_init(I2C_PMIC);
+       if (ret)
+               return ret;
+
+       p = pmic_get("PFUZE100_PMIC");
+       ret = pmic_probe(p);
+       if (ret)
+               return ret;
+
+       pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+       printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
+
+       /* Set SW1AB standby voltage to 0.975V */
+       pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
+       reg &= ~0x3f;
+       reg |= 0x1b;
+       pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
+
+       /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+       pmic_reg_read(p, PUZE_100_SW1ABCONF, &reg);
+       reg &= ~0xc0;
+       reg |= 0x40;
+       pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
+
+       /* Set SW1C standby voltage to 0.975V */
+       pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
+       reg &= ~0x3f;
+       reg |= 0x1b;
+       pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
+
+       /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
+       pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
+       reg &= ~0xc0;
+       reg |= 0x40;
+       pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
+
+       /* Enable power of VGEN5 3V3, needed for SD3 */
+       pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
+       reg &= ~0x1F;
+       reg |= 0x1F;
+       pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
+
+       return 0;
+}
+
 int board_early_init_f(void)
 {
        setup_iomux_uart();
+       setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
        return 0;
 }
 
@@ -87,6 +164,13 @@ int board_init(void)
        return 0;
 }
 
+int board_late_init(void)
+{
+       pfuze_init();
+
+       return 0;
+}
+
 int checkboard(void)
 {
        puts("Board: MX6SX SABRE SDB\n");
index 390286b6457631c335c38ea838118c4379ce9c57..7967b5d4c9c4a29919b975dd1b33f304efee87d6 100644 (file)
@@ -28,6 +28,7 @@
 #define CONFIG_SYS_MALLOC_LEN          (3 * SZ_1M)
 
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
 #define CONFIG_MXC_GPIO
 
 #define CONFIG_MXC_UART
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED             100000
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+
 /* FLASH and environment organization */
 #define CONFIG_SYS_NO_FLASH