+++ /dev/null
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
- * Add support the Sharp chips on the mpc8260ads.
- * I started with board/ip860/flash.c and made changes I found in
- * the MTD project by David Schleef.
- *
- * (C) Copyright 2003 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- * Re-written to support multi-bank flash SIMMs.
- * Added support for real protection and JFFS2.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-/* Intel-compatible flash ID */
-#define INTEL_COMPAT 0x89898989
-#define INTEL_ALT 0xB0B0B0B0
-
-/* Intel-compatible flash commands */
-#define INTEL_PROGRAM 0x10101010
-#define INTEL_ERASE 0x20202020
-#define INTEL_CLEAR 0x50505050
-#define INTEL_LOCKBIT 0x60606060
-#define INTEL_PROTECT 0x01010101
-#define INTEL_STATUS 0x70707070
-#define INTEL_READID 0x90909090
-#define INTEL_CONFIRM 0xD0D0D0D0
-#define INTEL_RESET 0xFFFFFFFF
-
-/* Intel-compatible flash status bits */
-#define INTEL_FINISHED 0x80808080
-#define INTEL_OK 0x80808080
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * This board supports 32-bit wide flash SIMMs (4x8-bit configuration.)
- * Up to 32MB of flash supported (up to 4 banks.)
- * BCSR is used for flash presence detect (page 4-65 of the User's Manual)
- *
- * The following code can not run from flash!
- */
-unsigned long flash_init (void)
-{
- ulong size = 0, sect_start, sect_size = 0, bank_size;
- ushort sect_count = 0;
- int i, j, nbanks;
- vu_long *addr = (vu_long *)CONFIG_SYS_FLASH_BASE;
- vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR;
-
- switch (bcsr[2] & 0xF) {
- case 0:
- nbanks = 4;
- break;
- case 1:
- nbanks = 2;
- break;
- case 2:
- nbanks = 1;
- break;
- default: /* Unsupported configurations */
- nbanks = CONFIG_SYS_MAX_FLASH_BANKS;
- }
-
- if (nbanks > CONFIG_SYS_MAX_FLASH_BANKS)
- nbanks = CONFIG_SYS_MAX_FLASH_BANKS;
-
- for (i = 0; i < nbanks; i++) {
- *addr = INTEL_READID; /* Read Intelligent Identifier */
- if ((addr[0] == INTEL_COMPAT) || (addr[0] == INTEL_ALT)) {
- switch (addr[1]) {
- case SHARP_ID_28F016SCL:
- case SHARP_ID_28F016SCZ:
- flash_info[i].flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
- sect_count = 32;
- sect_size = 0x40000;
- break;
- default:
- flash_info[i].flash_id = FLASH_UNKNOWN;
- sect_count = CONFIG_SYS_MAX_FLASH_SECT;
- sect_size =
- CONFIG_SYS_FLASH_SIZE / CONFIG_SYS_MAX_FLASH_BANKS / CONFIG_SYS_MAX_FLASH_SECT;
- }
- }
- else
- flash_info[i].flash_id = FLASH_UNKNOWN;
- if (flash_info[i].flash_id == FLASH_UNKNOWN) {
- printf("### Unknown flash ID %08lX %08lX at address %08lX ###\n",
- addr[0], addr[1], (ulong)addr);
- size = 0;
- *addr = INTEL_RESET; /* Reset bank to Read Array mode */
- break;
- }
- flash_info[i].sector_count = sect_count;
- flash_info[i].size = bank_size = sect_size * sect_count;
- size += bank_size;
- sect_start = (ulong)addr;
- for (j = 0; j < sect_count; j++) {
- addr = (vu_long *)sect_start;
- flash_info[i].start[j] = sect_start;
- flash_info[i].protect[j] = (addr[2] == 0x01010101);
- sect_start += sect_size;
- }
- *addr = INTEL_RESET; /* Reset bank to Read Array mode */
- addr = (vu_long *)sect_start;
- }
-
- if (size == 0) { /* Unknown flash, fill with hard-coded values */
- sect_start = CONFIG_SYS_FLASH_BASE;
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- flash_info[i].size = CONFIG_SYS_FLASH_SIZE / CONFIG_SYS_MAX_FLASH_BANKS;
- flash_info[i].sector_count = sect_count;
- for (j = 0; j < sect_count; j++) {
- flash_info[i].start[j] = sect_start;
- flash_info[i].protect[j] = 0;
- sect_start += sect_size;
- }
- }
- size = CONFIG_SYS_FLASH_SIZE;
- }
- else
- for (i = nbanks; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- flash_info[i].size = 0;
- flash_info[i].sector_count = 0;
- }
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
- &flash_info[0]);
-#endif
- return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL: printf ("Intel "); break;
- case FLASH_MAN_SHARP: printf ("Sharp "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n");
- break;
- case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
- break;
- case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
- break;
- case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
- && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- vu_long *addr = (vu_long *)(info->start[sect]);
-
- last = start = get_timer (0);
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Clear Status Register */
- *addr = INTEL_CLEAR;
- /* Single Block Erase Command */
- *addr = INTEL_ERASE;
- /* Confirm */
- *addr = INTEL_CONFIRM;
-
- if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
- /* Resume Command, as per errata update */
- *addr = INTEL_CONFIRM;
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
- if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- *addr = INTEL_RESET; /* reset bank */
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
- if (*addr != INTEL_OK) {
- printf("Block erase failed at %08X, CSR=%08X\n",
- (uint)addr, (uint)*addr);
- *addr = INTEL_RESET; /* reset bank */
- return 1;
- }
-
- /* reset to read mode */
- *addr = INTEL_RESET;
- }
- }
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- ulong start;
- int rc = 0;
- int flag;
- vu_long *addr = (vu_long *)dest;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) {
- return (2);
- }
-
- *addr = INTEL_CLEAR; /* Clear status register */
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Write Command */
- *addr = INTEL_PROGRAM;
-
- /* Write Data */
- *addr = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- printf("Write timed out\n");
- rc = 1;
- break;
- }
- }
- if (*addr != INTEL_OK) {
- printf ("Write failed at %08X, CSR=%08X\n", (uint)addr, (uint)*addr);
- rc = 1;
- }
-
- *addr = INTEL_RESET; /* Reset to read array mode */
-
- return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- *(vu_long *)wp = INTEL_RESET; /* Reset to read array mode */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- rc = write_word(info, wp, data);
-
- return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Set/Clear sector's lock bit, returns:
- * 0 - OK
- * 1 - Error (timeout, voltage problems, etc.)
- */
-int flash_real_protect(flash_info_t *info, long sector, int prot)
-{
- ulong start;
- int i;
- int rc = 0;
- vu_long *addr = (vu_long *)(info->start[sector]);
- int flag = disable_interrupts();
-
- *addr = INTEL_CLEAR; /* Clear status register */
- if (prot) { /* Set sector lock bit */
- *addr = INTEL_LOCKBIT; /* Sector lock bit */
- *addr = INTEL_PROTECT; /* set */
- }
- else { /* Clear sector lock bit */
- *addr = INTEL_LOCKBIT; /* All sectors lock bits */
- *addr = INTEL_CONFIRM; /* clear */
- }
-
- start = get_timer(0);
- while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
- if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
- printf("Flash lock bit operation timed out\n");
- rc = 1;
- break;
- }
- }
-
- if (*addr != INTEL_OK) {
- printf("Flash lock bit operation failed at %08X, CSR=%08X\n",
- (uint)addr, (uint)*addr);
- rc = 1;
- }
-
- if (!rc)
- info->protect[sector] = prot;
-
- /*
- * Clear lock bit command clears all sectors lock bits, so
- * we have to restore lock bits of protected sectors.
- */
- if (!prot)
- for (i = 0; i < info->sector_count; i++)
- if (info->protect[i]) {
- addr = (vu_long *)(info->start[i]);
- *addr = INTEL_LOCKBIT; /* Sector lock bit */
- *addr = INTEL_PROTECT; /* set */
- udelay(CONFIG_SYS_FLASH_LOCK_TOUT * 1000);
- }
-
- if (flag)
- enable_interrupts();
-
- *addr = INTEL_RESET; /* Reset to read array mode */
-
- return rc;
-}
+++ /dev/null
-/*
- * (C) Copyright 2001-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Modified during 2001 by
- * Advanced Communications Technologies (Australia) Pty. Ltd.
- * Howard Walker, Tuong Vu-Dinh
- *
- * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
- * Added support for the 16M dram simm on the 8260ads boards
- *
- * (C) Copyright 2003-2004 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
- *
- * Copyright (c) 2005 MontaVista Software, Inc.
- * Vitaly Bordug <vbordug@ru.mvista.com>
- * Added support for PCI.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include <asm/m8260_pci.h>
-#include <i2c.h>
-#include <spd.h>
-#include <miiphy.h>
-#ifdef CONFIG_PCI
-#include <pci.h>
-#endif
-#ifdef CONFIG_OF_LIBFDT
-#include <libfdt.h>
-#include <fdt_support.h>
-#endif
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1)
-#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2)
-#define CONFIG_SYS_FCC3 (CONFIG_ETHER_INDEX == 3)
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
- /* PA30 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
- /* PA29 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
- /* PA28 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
- /* PA27 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
- /* PA26 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
- /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
- /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
- /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
- /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
- /* PA21 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
- /* PA20 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
- /* PA19 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
- /* PA18 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
- /* PA17 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
- /* PA16 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
- /* PA15 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
- /* PA14 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
- /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
- /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
- /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
- /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
- /* PA9 */ { 0, 0, 0, 0, 0, 0 }, /* PA9 */
- /* PA8 */ { 0, 0, 0, 0, 0, 0 }, /* PA8 */
- /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
- /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
- /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
- /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
- /* PB16 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
- /* PB15 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
- /* PB14 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
- /* PB13 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */
- /* PB12 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
- /* PB11 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB10 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB9 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB8 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB7 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB6 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB5 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB4 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
- /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
- /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
- /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
- /* PC22 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Tx Clock (CLK10) */
- /* PC21 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Rx Clock (CLK11) */
- /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
-#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
- /* PC19 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
- /* PC18 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
- /* PC17 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK15) */
- /* PC16 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK16) */
-#else
- /* PC19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */
- /* PC18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */
- /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
- /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
- /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
- /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
- /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
-#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
- /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
- /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */
-#else
- /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
- /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
- /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
- /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
- /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
- /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */
- /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */
- /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
- /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
- /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
- /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
- /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
- /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
- /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
- /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
- /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
- /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- }
-};
-
-void reset_phy (void)
-{
- vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR;
-
- /* Reset the PHY */
-#if CONFIG_SYS_PHY_ADDR == 0
- bcsr[1] &= ~(FETHIEN1 | FETH1_RST);
- udelay(2);
- bcsr[1] |= FETH1_RST;
-#else
- bcsr[3] &= ~(FETHIEN2 | FETH2_RST);
- udelay(2);
- bcsr[3] |= FETH2_RST;
-#endif /* CONFIG_SYS_PHY_ADDR == 0 */
- udelay(1000);
-#ifdef CONFIG_MII
-#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
- /*
- * Do not bypass Rx/Tx (de)scrambler (fix configuration error)
- * Enable autonegotiation.
- */
- bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, 16, 0x610);
- bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_BMCR,
- BMCR_ANENABLE | BMCR_ANRESTART);
-#else
- /*
- * Ethernet PHY is configured (by means of configuration pins)
- * to work at 10Mb/s only. We reconfigure it using MII
- * to advertise all capabilities, including 100Mb/s, and
- * restart autonegotiation.
- */
-
- /* Advertise all capabilities */
- bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_ADVERTISE, 0x01E1);
-
- /* Do not bypass Rx/Tx (de)scrambler */
- bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_FCSCOUNTER, 0x0000);
-
- bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_BMCR,
- BMCR_ANENABLE | BMCR_ANRESTART);
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
-#endif /* CONFIG_MII */
-}
-
-#ifdef CONFIG_PCI
-typedef struct pci_ic_s {
- unsigned long pci_int_stat;
- unsigned long pci_int_mask;
-}pci_ic_t;
-#endif
-
-int board_early_init_f (void)
-{
- vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR;
-
-#ifdef CONFIG_PCI
- volatile pci_ic_t* pci_ic = (pci_ic_t *) CONFIG_SYS_PCI_INT;
-
- /* mask alll the PCI interrupts */
- pci_ic->pci_int_mask |= 0xfff00000;
-#endif
-#if (CONFIG_CONS_INDEX == 1) || (CONFIG_KGDB_INDEX == 1)
- bcsr[1] &= ~RS232EN_1;
-#endif
-#if (CONFIG_CONS_INDEX > 1) || (CONFIG_KGDB_INDEX > 1)
- bcsr[1] &= ~RS232EN_2;
-#endif
-
-#if CONFIG_ADSTYPE != CONFIG_SYS_8260ADS /* PCI mode can be selected */
-#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
- if ((bcsr[3] & BCSR_PCI_MODE) == 0) /* PCI mode selected by JP9 */
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
- {
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
- immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
- immap->im_siu_conf.sc_siumcr =
- (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
- | SIUMCR_LBPC01;
- }
-#endif /* CONFIG_ADSTYPE != CONFIG_SYS_8260ADS */
-
- return 0;
-}
-
-#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
-
-phys_size_t initdram (int board_type)
-{
-#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
- long int msize = 32;
-#elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
- long int msize = 64;
-#else
- long int msize = 16;
-#endif
-
-#ifndef CONFIG_SYS_RAMBOOT
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
- volatile uchar *ramaddr, c = 0xff;
- uint or;
- uint psdmr;
- uint psrt;
-
- int i;
-
- immap->im_siu_conf.sc_ppc_acr = 0x00000002;
- immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
- immap->im_siu_conf.sc_tescr1 = 0x00004000;
-
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-#ifdef CONFIG_SYS_LSDRAM_BASE
- /*
- Initialise local bus SDRAM only if the pins
- are configured as local bus pins and not as PCI.
- The configuration is determined by the HRCW.
- */
- if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
- memctl->memc_lsrt = CONFIG_SYS_LSRT;
-#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS /* CS3 */
- memctl->memc_or3 = 0xFF803280;
- memctl->memc_br3 = CONFIG_SYS_LSDRAM_BASE | 0x00001861;
-#else /* CS4 */
- memctl->memc_or4 = 0xFFC01480;
- memctl->memc_br4 = CONFIG_SYS_LSDRAM_BASE | 0x00001861;
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
- memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x28000000;
- ramaddr = (uchar *) CONFIG_SYS_LSDRAM_BASE;
- *ramaddr = c;
- memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x08000000;
- for (i = 0; i < 8; i++)
- *ramaddr = c;
- memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x18000000;
- *ramaddr = c;
- memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x40000000;
- }
-#endif /* CONFIG_SYS_LSDRAM_BASE */
-
- /* Init 60x bus SDRAM */
-#ifdef CONFIG_SPD_EEPROM
- {
- spd_eeprom_t spd;
- uint pbi, bsel, rowst, lsb, tmp;
-
- i2c_read (CONFIG_SPD_ADDR, 0, 1, (uchar *) & spd, sizeof (spd));
-
- /* Bank-based interleaving is not supported for physical bank
- sizes greater than 128MB which is encoded as 0x20 in SPD
- */
- pbi = (spd.row_dens > 32) ? 1 : CONFIG_SDRAM_PBI;
- msize = spd.nrows * (4 * spd.row_dens); /* Mixed size not supported */
- or = ~(msize - 1) << 20; /* SDAM */
- switch (spd.nbanks) { /* BPD */
- case 2:
- bsel = 1;
- break;
- case 4:
- bsel = 2;
- or |= 0x00002000;
- break;
- case 8:
- bsel = 3;
- or |= 0x00004000;
- break;
- }
- lsb = 3; /* For 64-bit port, lsb is 3 bits */
-
- if (pbi) { /* Bus partition depends on interleaving */
- rowst = 32 - (spd.nrow_addr + spd.ncol_addr + bsel + lsb);
- or |= (rowst << 9); /* ROWST */
- } else {
- rowst = 32 - (spd.nrow_addr + spd.ncol_addr + lsb);
- or |= ((rowst * 2 - 12) << 9); /* ROWST */
- }
- or |= ((spd.nrow_addr - 9) << 6); /* NUMR */
-
- psdmr = (pbi << 31); /* PBI */
- /* Bus multiplexing parameters */
- tmp = 32 - (lsb + spd.nrow_addr); /* Tables 10-19 and 10-20 */
- psdmr |= ((tmp - (rowst - 5) - 13) << 24); /* SDAM */
- psdmr |= ((tmp - 3 - 12) << 21); /* BSMA */
-
- tmp = (31 - lsb - 10) - tmp;
- /* Pin connected to SDA10 is (31 - lsb - 10).
- rowst is multiplexed over (32 - (lsb + spd.nrow_addr)),
- so (rowst + tmp) alternates with AP.
- */
- if (pbi) /* Table 10-7 */
- psdmr |= ((10 - (rowst + tmp)) << 18); /* SDA10 */
- else
- psdmr |= ((12 - (rowst + tmp)) << 18); /* SDA10 */
-
- /* SDRAM device-specific parameters */
- tmp = ns2clk (70); /* Refresh recovery is not in SPD, so assume 70ns */
- switch (tmp) { /* RFRC */
- case 1:
- case 2:
- psdmr |= (1 << 15);
- break;
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
- case 8:
- psdmr |= ((tmp - 2) << 15);
- break;
- default:
- psdmr |= (7 << 15);
- }
- psdmr |= (ns2clk (spd.trp) % 8 << 12); /* PRETOACT */
- psdmr |= (ns2clk (spd.trcd) % 8 << 9); /* ACTTORW */
- /* BL=0 because for 64-bit SDRAM burst length must be 4 */
- /* LDOTOPRE ??? */
- for (i = 0, tmp = spd.write_lat; (i < 4) && ((tmp & 1) == 0); i++)
- tmp >>= 1;
- switch (i) { /* WRC */
- case 0:
- case 1:
- psdmr |= (1 << 4);
- break;
- case 2:
- case 3:
- psdmr |= (i << 4);
- break;
- }
- /* EAMUX=0 - no external address multiplexing */
- /* BUFCMD=0 - no external buffers */
- for (i = 1, tmp = spd.cas_lat; (i < 3) && ((tmp & 1) == 0); i++)
- tmp >>= 1;
- psdmr |= i; /* CL */
-
- switch (spd.refresh & 0x7F) {
- case 1:
- tmp = 3900;
- break;
- case 2:
- tmp = 7800;
- break;
- case 3:
- tmp = 31300;
- break;
- case 4:
- tmp = 62500;
- break;
- case 5:
- tmp = 125000;
- break;
- default:
- tmp = 15625;
- }
- psrt = tmp / (1000000000 / CONFIG_8260_CLKIN *
- ((memctl->memc_mptpr >> 8) + 1)) - 1;
-#ifdef SPD_DEBUG
- printf ("\nDIMM type: %-18.18s\n", spd.mpart);
- printf ("SPD size: %d\n", spd.info_size);
- printf ("EEPROM size: %d\n", 1 << spd.chip_size);
- printf ("Memory type: %d\n", spd.mem_type);
- printf ("Row addr: %d\n", spd.nrow_addr);
- printf ("Column addr: %d\n", spd.ncol_addr);
- printf ("# of rows: %d\n", spd.nrows);
- printf ("Row density: %d\n", spd.row_dens);
- printf ("# of banks: %d\n", spd.nbanks);
- printf ("Data width: %d\n",
- 256 * spd.dataw_msb + spd.dataw_lsb);
- printf ("Chip width: %d\n", spd.primw);
- printf ("Refresh rate: %02X\n", spd.refresh);
- printf ("CAS latencies: %02X\n", spd.cas_lat);
- printf ("Write latencies: %02X\n", spd.write_lat);
- printf ("tRP: %d\n", spd.trp);
- printf ("tRCD: %d\n", spd.trcd);
-
- printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt);
-#endif /* SPD_DEBUG */
- }
-#else /* !CONFIG_SPD_EEPROM */
- or = CONFIG_SYS_OR2;
- psdmr = CONFIG_SYS_PSDMR;
- psrt = CONFIG_SYS_PSRT;
-#endif /* CONFIG_SPD_EEPROM */
- memctl->memc_psrt = psrt;
- memctl->memc_or2 = or;
- memctl->memc_br2 = CONFIG_SYS_SDRAM_BASE | 0x00000041;
- ramaddr = (uchar *) CONFIG_SYS_SDRAM_BASE;
- memctl->memc_psdmr = psdmr | 0x28000000; /* Precharge all banks */
- *ramaddr = c;
- memctl->memc_psdmr = psdmr | 0x08000000; /* CBR refresh */
- for (i = 0; i < 8; i++)
- *ramaddr = c;
-
- memctl->memc_psdmr = psdmr | 0x18000000; /* Mode Register write */
- *ramaddr = c;
- memctl->memc_psdmr = psdmr | 0x40000000; /* Refresh enable */
- *ramaddr = c;
-#endif /* CONFIG_SYS_RAMBOOT */
-
- /* return total 60x bus SDRAM size */
- return (msize * 1024 * 1024);
-}
-
-int checkboard (void)
-{
-#if CONFIG_ADSTYPE == CONFIG_SYS_8260ADS
- puts ("Board: Motorola MPC8260ADS\n");
-#elif CONFIG_ADSTYPE == CONFIG_SYS_8266ADS
- puts ("Board: Motorola MPC8266ADS\n");
-#elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
- puts ("Board: Motorola PQ2FADS-ZU\n");
-#elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
- puts ("Board: Motorola MPC8272ADS\n");
-#else
- puts ("Board: unknown\n");
-#endif
- return 0;
-}
-
-#ifdef CONFIG_PCI
-struct pci_controller hose;
-
-extern void pci_mpc8250_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
- pci_mpc8250_init(&hose);
-}
-#endif
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Stuart Hughes <stuarth@lineo.com>
- * This file is based on similar values for other boards found in other
- * U-Boot config files, and some that I found in the mpc8260ads manual.
- *
- * Note: my board is a PILOT rev.
- * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
- *
- * (C) Copyright 2003-2004 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2.
- * Ported to PQ2FADS-ZU and PQ2FADS-VR boards.
- * Ported to MPC8272ADS board.
- *
- * Copyright (c) 2005 MontaVista Software, Inc.
- * Vitaly Bordug <vbordug@ru.mvista.com>
- * Added support for PCI bridge on MPC8272ADS
- *
- * Copyright (C) Freescale Semiconductor, Inc. 2006-2009.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8260ADS 1 /* Motorola PQ2 ADS family board */
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */
-#endif
-
-#define CONFIG_CPM2 1 /* Has a CPM2 */
-
-/*
- * Figure out if we are booting low via flash HRCW or high via the BCSR.
- */
-#if (CONFIG_SYS_TEXT_BASE != 0xFFF00000) /* Boot low (flash HRCW) */
-# define CONFIG_SYS_LOWBOOT 1
-#endif
-
-/* ADS flavours */
-#define CONFIG_SYS_8260ADS 1 /* MPC8260ADS */
-#define CONFIG_SYS_8266ADS 2 /* MPC8266ADS */
-#define CONFIG_SYS_PQ2FADS 3 /* PQ2FADS-ZU or PQ2FADS-VR */
-#define CONFIG_SYS_8272ADS 4 /* MPC8272ADS */
-
-#ifndef CONFIG_ADSTYPE
-#define CONFIG_ADSTYPE CONFIG_SYS_8260ADS
-#endif /* CONFIG_ADSTYPE */
-
-#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
-#define CONFIG_MPC8272 1
-#elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
-/*
- * Actually MPC8275, but the code is littered with ifdefs that
- * apply to both, or which use this ifdef to assume board-specific
- * details. :-(
- */
-#define CONFIG_MPC8272 1
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
-
-/* allow serial and ethaddr to be overwritten */
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
-#define CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on something else */
-#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- */
-#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
-#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
-#undef CONFIG_ETHER_NONE /* define if ether on something else */
-
-#ifdef CONFIG_ETHER_ON_FCC
-
-#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
-
-#if CONFIG_ETHER_INDEX == 1
-
-# define CONFIG_SYS_PHY_ADDR 0
-# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
-# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
-
-#elif CONFIG_ETHER_INDEX == 2
-
-#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS /* RxCLK is CLK15, TxCLK is CLK16 */
-# define CONFIG_SYS_PHY_ADDR 3
-# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16)
-#else /* RxCLK is CLK13, TxCLK is CLK14 */
-# define CONFIG_SYS_PHY_ADDR 0
-# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
-
-# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-
-#endif /* CONFIG_ETHER_INDEX */
-
-#define CONFIG_SYS_CPMFCR_RAMTYPE 0 /* BDs and buffers on 60x bus */
-#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) /* Full duplex */
-
-#define CONFIG_MII /* MII PHY management */
-#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
-/*
- * GPIO pins used for bit-banged MII communications
- */
-#define MDIO_PORT 2 /* Port C */
-#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
-#define MDC_DECLARE MDIO_DECLARE
-
-#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
-#define CONFIG_SYS_MDIO_PIN 0x00002000 /* PC18 */
-#define CONFIG_SYS_MDC_PIN 0x00001000 /* PC19 */
-#else
-#define CONFIG_SYS_MDIO_PIN 0x00400000 /* PC9 */
-#define CONFIG_SYS_MDC_PIN 0x00200000 /* PC10 */
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
-
-#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
-#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
-#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
-
-#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \
- else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
-
-#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \
- else iop->pdat &= ~CONFIG_SYS_MDC_PIN
-
-#define MIIDELAY udelay(1)
-
-#endif /* CONFIG_ETHER_ON_FCC */
-
-#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
-#undef CONFIG_SPD_EEPROM /* On new boards, SDRAM is soldered */
-#else
-#define CONFIG_HARD_I2C 1 /* To enable I2C support */
-#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
-#define CONFIG_SPD_ADDR 0x50
-#endif
-#endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */
-
-/*PCI*/
-#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
-#define CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_PNP
-#define CONFIG_PCI_BOOTDELAY 0
-#define CONFIG_PCI_SCAN_SHOW
-#endif
-
-#ifndef CONFIG_SDRAM_PBI
-#define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */
-#endif
-
-#ifndef CONFIG_8260_CLKIN
-#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
-#define CONFIG_8260_CLKIN 100000000 /* in Hz */
-#else
-#define CONFIG_8260_CLKIN 66000000 /* in Hz */
-#endif
-#endif
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#if defined(CONFIG_OF_LIBFDT)
-#define OF_TBCLK (bd->bi_busfreq / 4)
-#endif
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_CDP
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_PORTIO
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_SDRAM
-
-#undef CONFIG_CMD_XIMG
-
-#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
- #undef CONFIG_CMD_SDRAM
- #undef CONFIG_CMD_I2C
-
-#elif CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
- #undef CONFIG_CMD_SDRAM
- #undef CONFIG_CMD_I2C
-
-#else
- #undef CONFIG_CMD_PCI
-
-#endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */
-
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_BOOTCOMMAND "bootm fff80000" /* autoboot command */
-#define CONFIG_BOOTARGS "root=/dev/mtdblock2"
-
-#if defined(CONFIG_CMD_KGDB)
-#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
-#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
-#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
-#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
-#endif
-
-#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
-#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_SYS_FLASH_BASE 0xff800000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 32 /* max num of sects on one chip */
-#define CONFIG_SYS_FLASH_SIZE 8
-#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
-#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
-#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
-
-/*
- * JFFS2 partitions
- *
- * Note: fake mtd_id used, no linux mtd map file
- */
-#define MTDIDS_DEFAULT "nor0=mpc8260ads-0"
-#define MTDPARTS_DEFAULT "mtdparts=mpc8260ads-0:-@1m(jffs2)"
-#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
-
-/* this is stuff came out of the Motorola docs */
-#ifndef CONFIG_SYS_LOWBOOT
-#define CONFIG_SYS_DEFAULT_IMMR 0x0F010000
-#endif
-
-#define CONFIG_SYS_IMMR 0xF0000000
-#define CONFIG_SYS_BCSR 0xF4500000
-#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
-#define CONFIG_SYS_PCI_INT 0xF8200000
-#endif
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_LSDRAM_BASE 0xFD000000
-
-#define RS232EN_1 0x02000002
-#define RS232EN_2 0x01000001
-#define FETHIEN1 0x08000008
-#define FETH1_RST 0x04000004
-#define FETHIEN2 0x10000000
-#define FETH2_RST 0x08000000
-#define BCSR_PCI_MODE 0x01000000
-
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#ifdef CONFIG_SYS_LOWBOOT
-/* PQ2FADS flash HRCW = 0x0EB4B645 */
-#define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
- ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB100 ) |\
- ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\
- ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \
- )
-#else
-/* PQ2FADS BCSR HRCW = 0x0CB23645 */
-#define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
- ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 ) |\
- ( HRCW_BMS | HRCW_APPC10 ) |\
- ( HRCW_MODCK_H0101 ) \
- )
-#endif
-/* no slaves */
-#define CONFIG_SYS_HRCW_SLAVE1 0
-#define CONFIG_SYS_HRCW_SLAVE2 0
-#define CONFIG_SYS_HRCW_SLAVE3 0
-#define CONFIG_SYS_HRCW_SLAVE4 0
-#define CONFIG_SYS_HRCW_SLAVE5 0
-#define CONFIG_SYS_HRCW_SLAVE6 0
-#define CONFIG_SYS_HRCW_SLAVE7 0
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#ifdef CONFIG_BZIP2
-#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
-#else
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
-#endif /* CONFIG_BZIP2 */
-
-#ifndef CONFIG_SYS_RAMBOOT
-# define CONFIG_ENV_IS_IN_FLASH 1
-# define CONFIG_ENV_SECT_SIZE 0x40000
-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE)
-#else
-# define CONFIG_ENV_IS_IN_NVRAM 1
-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
-# define CONFIG_ENV_SIZE 0x200
-#endif /* CONFIG_SYS_RAMBOOT */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-#define CONFIG_SYS_HID0_INIT 0
-#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
-
-#define CONFIG_SYS_HID2 0
-
-#define CONFIG_SYS_SYPCR 0xFFFFFFC3
-#define CONFIG_SYS_BCR 0x100C0000
-#define CONFIG_SYS_SIUMCR 0x0A200000
-#define CONFIG_SYS_SCCR SCCR_DFBRG01
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001801)
-#define CONFIG_SYS_OR0_PRELIM 0xFF800876
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x00001801)
-#define CONFIG_SYS_OR1_PRELIM 0xFFFF8010
-
-/*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/
-
-#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */
-#define CONFIG_SYS_OR3_PRELIM 0xFFFF8010
-#elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
-#define CONFIG_SYS_BR8_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */
-#define CONFIG_SYS_OR8_PRELIM 0xFFFF8010
-#endif
-
-#define CONFIG_SYS_RMR RMR_CSRE
-#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
-#define CONFIG_SYS_RCCR 0
-
-#if (CONFIG_ADSTYPE == CONFIG_SYS_8266ADS) || (CONFIG_ADSTYPE == CONFIG_SYS_8272ADS)
-#undef CONFIG_SYS_LSDRAM_BASE /* No local bus SDRAM on these boards */
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8266ADS */
-
-#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
-#define CONFIG_SYS_OR2 0xFE002EC0
-#define CONFIG_SYS_PSDMR 0x824B36A3
-#define CONFIG_SYS_PSRT 0x13
-#define CONFIG_SYS_LSDMR 0x828737A3
-#define CONFIG_SYS_LSRT 0x13
-#define CONFIG_SYS_MPTPR 0x2800
-#elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
-#define CONFIG_SYS_OR2 0xFC002CC0
-#define CONFIG_SYS_PSDMR 0x834E24A3
-#define CONFIG_SYS_PSRT 0x13
-#define CONFIG_SYS_MPTPR 0x2800
-#else
-#define CONFIG_SYS_OR2 0xFF000CA0
-#define CONFIG_SYS_PSDMR 0x016EB452
-#define CONFIG_SYS_PSRT 0x21
-#define CONFIG_SYS_LSDMR 0x0086A522
-#define CONFIG_SYS_LSRT 0x21
-#define CONFIG_SYS_MPTPR 0x1900
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
-
-#define CONFIG_SYS_RESET_ADDRESS 0x04400000
-
-#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
-
-/* PCI Memory map (if different from default map */
-#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */
-#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
-#define CONFIG_SYS_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
- PICMR_PREFETCH_EN)
-
-/*
- * These are the windows that allow the CPU to access PCI address space.
- * All three PCI master windows, which allow the CPU to access PCI
- * prefetch, non prefetch, and IO space (see below), must all fit within
- * these windows.
- */
-
-/*
- * Master window that allows the CPU to access PCI Memory (prefetch).
- * This window will be setup with the second set of Outbound ATU registers
- * in the bridge.
- */
-
-#define CONFIG_SYS_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
-#define CONFIG_SYS_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
-#define CONFIG_SYS_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
-#define CONFIG_SYS_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
-#define CONFIG_SYS_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
-
-/*
- * Master window that allows the CPU to access PCI Memory (non-prefetch).
- * This window will be setup with the second set of Outbound ATU registers
- * in the bridge.
- */
-
-#define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
-#define CONFIG_SYS_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
-#define CONFIG_SYS_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
-#define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
-#define CONFIG_SYS_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
-
-/*
- * Master window that allows the CPU to access PCI IO space.
- * This window will be setup with the first set of Outbound ATU registers
- * in the bridge.
- */
-
-#define CONFIG_SYS_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */
-#define CONFIG_SYS_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
-#define CONFIG_SYS_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
-#define CONFIG_SYS_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */
-#define CONFIG_SYS_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
-
-
-/* PCIBR0 - for PCI IO*/
-#define CONFIG_SYS_PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL /* Local base */
-#define CONFIG_SYS_PCIMSK0_MASK ~(CONFIG_SYS_PCI_MSTR_IO_SIZE - 1U) /* Size of window */
-/* PCIBR1 - prefetch and non-prefetch regions joined together */
-#define CONFIG_SYS_PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL
-#define CONFIG_SYS_PCIMSK1_MASK ~(CONFIG_SYS_PCI_MSTR_MEM_SIZE + CONFIG_SYS_PCI_MSTR_MEMIO_SIZE - 1U)
-
-#endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/
-
-#define CONFIG_HAS_ETH0
-
-#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
-#define CONFIG_HAS_ETH1
-#endif
-
-#define CONFIG_NETDEV eth0
-#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=" __stringify(CONFIG_NETDEV) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize\0" \
- "fdtaddr=400000\0" \
- "console=ttyCPM0\0" \
- "setbootargs=setenv bootargs " \
- "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
- "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv rootdev /dev/nfs;" \
- "run setipargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv rootdev /dev/ram;" \
- "run setbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#endif /* __CONFIG_H */
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