]> git.sur5r.net Git - u-boot/commitdiff
x86: ivybridge: Convert report_platform to DM PCI API
authorSimon Glass <sjg@chromium.org>
Sun, 17 Jan 2016 23:11:51 +0000 (16:11 -0700)
committerBin Meng <bmeng.cn@gmail.com>
Sun, 24 Jan 2016 04:09:41 +0000 (12:09 +0800)
Convert these functions to use the driver model PCI API.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
arch/x86/cpu/ivybridge/report_platform.c
arch/x86/cpu/ivybridge/sdram.c
arch/x86/include/asm/arch-ivybridge/sandybridge.h

index 44938709c9bccc086a05ce376ad44d9a6c1d725a..c78322aef99b9a5a5bdf4fa5fd7c7a3fbd99911e 100644 (file)
@@ -10,6 +10,7 @@
 #include <asm/cpu.h>
 #include <asm/pci.h>
 #include <asm/arch/pch.h>
+#include <asm/arch/sandybridge.h>
 
 static void report_cpu_info(void)
 {
@@ -63,27 +64,27 @@ static struct {
        {0x1E5F, "NM70"},
 };
 
-static void report_pch_info(void)
+static void report_pch_info(struct udevice *dev)
 {
        const char *pch_type = "Unknown";
        int i;
        u16 dev_id;
        uint8_t rev_id;
 
-       dev_id = x86_pci_read_config16(PCH_LPC_DEV, 2);
+       dm_pci_read_config16(dev, 2, &dev_id);
        for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
                if (pch_table[i].dev_id == dev_id) {
                        pch_type = pch_table[i].dev_name;
                        break;
                }
        }
-       rev_id = x86_pci_read_config8(PCH_LPC_DEV, 8);
+       dm_pci_read_config8(dev, 8, &rev_id);
        debug("PCH type: %s, device id: %x, rev id %x\n", pch_type, dev_id,
              rev_id);
 }
 
-void report_platform_info(void)
+void report_platform_info(struct udevice *dev)
 {
        report_cpu_info();
-       report_pch_info();
+       report_pch_info(dev);
 }
index 696351b7bf7186d6e9d38fbe7fec65ca62f005a7..3e5be4e0a09888f1931c8147fd0e9b65315486dc 100644 (file)
@@ -294,7 +294,7 @@ int sdram_initialise(struct udevice *dev, struct udevice *me_dev,
        uint16_t done;
        int ret;
 
-       report_platform_info();
+       report_platform_info(dev);
 
        /* Wait for ME to be ready */
        ret = intel_early_me_init(me_dev);
index af8a9f742a454bdc0f5cd0efd556273c0015602b..ce8d030f324ce3abfae175dc262ed32ad5695f41 100644 (file)
 
 int bridge_silicon_revision(void);
 
-void report_platform_info(void);
+void report_platform_info(struct udevice *dev);
 
 void sandybridge_early_init(int chipset_type);