]> git.sur5r.net Git - u-boot/commitdiff
armv8: ls2080a: Reorganise NAND_BOOT code in config flag
authorSantan Kumar <santan.kumar@nxp.com>
Fri, 5 May 2017 10:12:28 +0000 (15:42 +0530)
committerYork Sun <york.sun@nxp.com>
Fri, 2 Jun 2017 02:57:07 +0000 (19:57 -0700)
Add CONFIG_NAND_BOOT config flag to organise
NAND_BOOT specific code in config flag like
-nand-boot specfic errata errata_rcw_src()
-CONFIG_SYS_NAND_U_BOOT_DST,etc

Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
arch/arm/cpu/armv8/fsl-layerscape/soc.c
configs/ls2080aqds_nand_defconfig
configs/ls2080ardb_nand_defconfig
include/configs/ls2080a_common.h
include/configs/ls2080aqds.h

index 9e3cdd78af5b6f70fffc9298801c69331f599462..76e3af0d561d34fc4cefa1a6b327cfddbedd6f52 100644 (file)
@@ -134,7 +134,7 @@ void erratum_a009635(void)
 
 static void erratum_rcw_src(void)
 {
-#if defined(CONFIG_SPL)
+#if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
        u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
        u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
        u32 val;
index 99df6e0818f196b506946fef5aedeb05fda89109..614660008b991626a804aef5332a4e7f1eb859fa 100644 (file)
@@ -10,6 +10,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_NAND_BOOT=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
 CONFIG_BOOTDELAY=10
 CONFIG_SPL=y
index 5ce37fdfb433d6015b34db2b6d64512f7ec563d7..5800213e41e058b19d36bbbd5645c4851710258b 100644 (file)
@@ -10,6 +10,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_NAND_BOOT=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
 CONFIG_BOOTDELAY=10
 CONFIG_SPL=y
index 3706b1a4c46c639af70656ba1820f1b1041cf6f8..43c5fef9b99547ba80b45efa1f588599a06a63e9 100644 (file)
@@ -233,8 +233,10 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
 #define CONFIG_SPL_TEXT_BASE           0x1800a000
 
+#ifdef CONFIG_NAND_BOOT
 #define CONFIG_SYS_NAND_U_BOOT_DST     0x80400000
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_NAND_U_BOOT_DST
+#endif
 #define CONFIG_SYS_SPL_MALLOC_SIZE     0x00100000
 #define CONFIG_SYS_SPL_MALLOC_START    0x80200000
 #define CONFIG_SYS_MONITOR_LEN         (640 * 1024)
index d0b0aa93e463c807a09b319c909570835f767b53..e6ebec50ba846a60df0216d38a009fb1b2bd9c81 100644 (file)
@@ -198,7 +198,8 @@ unsigned long get_board_ddr_clk(void);
                                        FTIM2_GPCM_TWP(0x3E))
 #define CONFIG_SYS_CS3_FTIM3           0x0
 
-#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
+#if defined(CONFIG_SPL)
+#if defined(CONFIG_NAND_BOOT)
 #define CONFIG_SYS_CSPR1_EXT           CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR1               CONFIG_SYS_NOR0_CSPR_EARLY
 #define CONFIG_SYS_CSPR1_FINAL         CONFIG_SYS_NOR0_CSPR
@@ -234,6 +235,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SPL_PAD_TO              0x20000
 #define CONFIG_SYS_NAND_U_BOOT_OFFS    (256 * 1024)
 #define CONFIG_SYS_NAND_U_BOOT_SIZE    (640 * 1024)
+#endif
 #else
 #define CONFIG_SYS_CSPR0_EXT           CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR0               CONFIG_SYS_NOR0_CSPR_EARLY