x86: cougarcanyon2: Remove CONFIG_HAVE_INTEL_ME

As README.x86 already mentions, there are two SPI flashes mounted
on Intel Cougar Canyon 2 board, called SPI-0 and SPI-1 respectively.
SPI-0 stores the flash descriptor and the ME firmware. SPI-1 stores
the actual BIOS image which is U-Boot. Building a single image with
both ME firmware and U-Boot does not make sense.

This also describes the exact flash location where the u-boot.rom
should be programmed in the documentation.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig
index 6c79b77d06c1d9360ccc6907237dfb80ce6a99db..04ad23262b8a7834d2a78e9d3ef85fa0fc6b43df 100644 (file)
--- a/configs/cougarcanyon2_defconfig
+++ b/configs/cougarcanyon2_defconfig
@@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0xFFE00000
 CONFIG_VENDOR_INTEL=y
 CONFIG_DEFAULT_DEVICE_TREE="cougarcanyon2"
 CONFIG_TARGET_COUGARCANYON2=y
+# CONFIG_HAVE_INTEL_ME is not set
 # CONFIG_ENABLE_MRC_CACHE is not set
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"

diff --git a/doc/README.x86 b/doc/README.x86
index 04f02202b47b1b19d31e6529101e3e88528bb537..78664c3d0a54996e931d422fa406cfb6f3a5bfbc 100644 (file)
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -256,7 +256,9 @@ the board manual. The SPI-0 flash should have flash descriptor plus ME firmware
 and SPI-1 flash is used to store U-Boot. For convenience, the complete 8MB SPI-0
 flash image is included in the FSP package (named Rom00_8M_MB_PPT.bin). Program
 this image to the SPI-0 flash according to the board manual just once and we are
-all set. For programming U-Boot we just need to program SPI-1 flash.
+all set. For programming U-Boot we just need to program SPI-1 flash. Since the
+default u-boot.rom image for this board is set to 2MB, it should be programmed
+to the last 2MB of the 8MB chip, address range [600000, 7FFFFF].
 
 ---