u_int16_t data;
if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &data) && (data & 0x04)) {
- davinci_eth_phy_read(EMAC_MDIO_PHY_NUM,
- MII_PHY_CONFIG_REG, &data);
+ davinci_eth_phy_read(phy_addr, MII_PHY_CONFIG_REG, &data);
/* Enable 125MHz clock sourced from PHY */
- davinci_eth_phy_write(EMAC_MDIO_PHY_NUM,
- MII_PHY_CONFIG_REG,
+ davinci_eth_phy_write(phy_addr, MII_PHY_CONFIG_REG,
data | PHY_SYS_CLK_EN);
return (1);
}
#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
#endif
-/* PHY mask - set only those phy number bits where phy is/can be connected */
-#define EMAC_MDIO_PHY_NUM CONFIG_EMAC_MDIO_PHY_NUM
-#define EMAC_MDIO_PHY_MASK (1 << EMAC_MDIO_PHY_NUM)
-
/* Ethernet Min/Max packet size */
#define EMAC_MIN_ETHERNET_PKT_SIZE 60
#define EMAC_MAX_ETHERNET_PKT_SIZE 1518
#define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args)
#ifdef DAVINCI_EMAC_GIG_ENABLE
-#define emac_gigabit_enable() davinci_eth_gigabit_enable()
+#define emac_gigabit_enable(phy_addr) davinci_eth_gigabit_enable(phy_addr)
#else
-#define emac_gigabit_enable() /* no gigabit to enable */
+#define emac_gigabit_enable(phy_addr) /* no gigabit to enable */
#endif
static void davinci_eth_mdio_enable(void);
}
#endif
-static void __attribute__((unused)) davinci_eth_gigabit_enable(void)
+static void __attribute__((unused)) davinci_eth_gigabit_enable(int phy_addr)
{
u_int16_t data;
- if (davinci_eth_phy_read(EMAC_MDIO_PHY_NUM, 0, &data)) {
+ if (davinci_eth_phy_read(phy_addr, 0, &data)) {
if (data & (1 << 6)) { /* speed selection MSB */
/*
* Check if link detected is giga-bit
if (index == -1)
return(0);
- emac_gigabit_enable();
+ emac_gigabit_enable(active_phy_addr[index]);
/* Start receive process */
writel((u_int32_t)emac_rx_desc, &adap_emac->RX0HDP);
return (ret_status);
}
- emac_gigabit_enable();
+ emac_gigabit_enable(active_phy_addr[index]);
/* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */
if (length < EMAC_MIN_ETHERNET_PKT_SIZE) {
return (ret_status);
}
- emac_gigabit_enable();
+ emac_gigabit_enable(active_phy_addr[index]);
if (readl(&adap_emac->TXINTSTATRAW) & 0x01) {
ret_status = length;
* Network & Ethernet Configuration
*/
#ifdef CONFIG_DRIVER_TI_EMAC
-#define CONFIG_EMAC_MDIO_PHY_NUM 1
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
* Network & Ethernet Configuration
*/
#ifdef CONFIG_DRIVER_TI_EMAC
-#define CONFIG_EMAC_MDIO_PHY_NUM 0
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
/* Network Configuration */
#define CONFIG_DRIVER_TI_EMAC
-#define CONFIG_EMAC_MDIO_PHY_NUM 0
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
/* Network & Ethernet Configuration */
#define CONFIG_DRIVER_TI_EMAC
-#define CONFIG_EMAC_MDIO_PHY_NUM 1
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
/* Network & Ethernet Configuration */
/*==================================*/
#define CONFIG_DRIVER_TI_EMAC
-#define CONFIG_EMAC_MDIO_PHY_NUM 1
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
/* Network & Ethernet Configuration */
/*==================================*/
#define CONFIG_DRIVER_TI_EMAC
-#define CONFIG_EMAC_MDIO_PHY_NUM 1
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
/* Network & Ethernet Configuration */
#define CONFIG_DRIVER_TI_EMAC
-#define CONFIG_EMAC_MDIO_PHY_NUM 1
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
/* Network & Ethernet Configuration */
/*==================================*/
#define CONFIG_DRIVER_TI_EMAC
-#define CONFIG_EMAC_MDIO_PHY_NUM 1
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
* Network & Ethernet Configuration
*/
#ifdef CONFIG_DRIVER_TI_EMAC
-#define CONFIG_EMAC_MDIO_PHY_NUM 0
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
/*
* Network & Ethernet Configuration
*/
-#define CONFIG_EMAC_MDIO_PHY_NUM 0x7
#if !defined(CONFIG_NAND_SPL)
#define CONFIG_DRIVER_TI_EMAC
#endif