config ARM
bool "ARM architecture"
- select HAVE_PRIVATE_LIBGCC
+ select HAVE_PRIVATE_LIBGCC if !ARM64
select HAVE_GENERIC_BOARD
select SUPPORT_OF_CONTROL
bool "Support tbs2910"
select CPU_V7
-config TARGET_TQMA6
- bool "TQ Systems TQMa6 board"
- select CPU_V7
-
config TARGET_OT1200
bool "Bachmann OT1200"
select CPU_V7
source "board/timll/devkit3250/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
source "board/toradex/colibri_vf/Kconfig"
-source "board/tqc/tqma6/Kconfig"
source "board/trizepsiv/Kconfig"
source "board/ttcontrol/vision2/Kconfig"
source "board/udoo/Kconfig"
bool "Support secomx6 boards"
select CPU_V7
+config TARGET_TQMA6
+ bool "TQ Systems TQMa6 board"
+ select CPU_V7
+
endchoice
config SYS_SOC
default "mx6"
source "board/seco/Kconfig"
+source "board/tqc/tqma6/Kconfig"
endif
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
u32 reg = readl(&anatop->digprog_sololite);
u32 type = ((reg >> 16) & 0xff);
+ u32 major;
if (type != MXC_CPU_MX6SL) {
reg = readl(&anatop->digprog);
}
}
+ major = ((reg >> 8) & 0xff);
reg &= 0xff; /* mx6 silicon revision */
- return (type << 12) | (reg + 0x10);
+ return (type << 12) | (reg + (0x10 * (major + 1)));
}
/*
*
* Startup Code (reset vector)
*
- * do important init only if we don't start from memory!
- * setup Memory and board specific bits prior to relocation.
- * relocate armboot to ram
- * setup stack
+ * Do important init only if we don't start from memory!
+ * Setup memory and board specific bits prior to relocation.
+ * Relocate armboot to ram. Setup stack.
*
*************************************************************************/
sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
#endif
#if defined(CONFIG_MACH_SUN8I)
- sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0_TX);
- sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0_RX);
+ sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
#else
- sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0_TX);
- sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0_RX);
+ sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
#endif
sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
+ sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
struct sunxi_rsb_reg * const rsb =
(struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
- rsb_cfg_io();
-
/* Enable RSB and PIO clk, and de-assert their resets */
prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
+ /* Setup external pins */
+ rsb_cfg_io();
+
writel(RSB_CTRL_SOFT_RST, &rsb->ctrl);
rsb_set_clk();
dtb-$(CONFIG_MACH_SUN8I_A33) += \
sun8i-a33-et-q8-v1.6.dtb \
sun8i-a33-ga10h-v1.1.dtb \
- sun8i-a33-ippo-q8h-v1.2-lcd1024x600.dtb
+ sun8i-a33-ippo-q8h-v1.2.dtb \
+ sun8i-a33-sinlinx-sina33.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+ mmc2_8bit_pins: mmc2_8bit {
+ allwinner,pins = "PC5", "PC6", "PC8",
+ "PC9", "PC10", "PC11",
+ "PC12", "PC13", "PC14",
+ "PC15";
+ allwinner,function = "mmc2";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
i2c0_pins_a: i2c0@0 {
allwinner,pins = "PH2", "PH3";
allwinner,function = "i2c0";
+++ /dev/null
-/*
- * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
- *
- * Minimal dts file for the Ippo Q8H V1.2 (A33, 1024x600) for u-boot only
- *
- * SPDX-License-Identifier: GPL-2.0+ or X11
- */
-
-/dts-v1/;
-#include "sun8i-a33.dtsi"
-
-/ {
- model = "Ippo Q8H V1.2 (A33, 1024x600)";
- compatible = "ippo,q8h-v1.2-a33-lcd1024x600", "allwinner,sun8i-a23";
-
- aliases {
- serial0 = &r_uart;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&r_uart {
- pinctrl-names = "default";
- pinctrl-0 = <&r_uart_pins_a>;
- status = "okay";
-};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Minimal dts file for the Ippo Q8H V1.2 (A33, 1024x600) for u-boot only
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include "sun8i-a33.dtsi"
+
+/ {
+ model = "Ippo Q8H V1.2 (A33, 1024x600)";
+ compatible = "ippo,q8h-v1.2-a33-lcd1024x600", "allwinner,sun8i-a23";
+
+ aliases {
+ serial0 = &r_uart;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&r_uart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_uart_pins_a>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a33.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Sinlinx SinA33";
+ compatible = "sinlinx,sina33", "allwinner,sun8i-a33";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&lradc {
+ vref-supply = <®_vcc3v0>;
+ status = "okay";
+
+ button@200 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <191011>;
+ };
+
+ button@400 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <391304>;
+ };
+
+ button@600 {
+ label = "Home";
+ linux,code = <KEY_HOME>;
+ channel = <0>;
+ voltage = <600000>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_sina33>;
+ vmmc-supply = <®_vcc3v0>;
+ bus-width = <4>;
+ cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <®_vcc3v0>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&mmc2_8bit_pins {
+ /* eMMC is missing pull-ups */
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
+
+&pio {
+ mmc0_cd_pin_sina33: mmc0_cd_pin@0 {
+ allwinner,pins = "PB4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_b>;
+ status = "okay";
+};
compatible = "allwinner,sun8i-a33-pinctrl";
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+
+ uart0_pins_b: uart0@1 {
+ allwinner,pins = "PB0", "PB1";
+ allwinner,function = "uart0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
};
{
#if defined(CONFIG_MX6)
if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) &&
- (is_soc_rev(CHIP_REV_1_0) > 0)) || is_cpu_type(MXC_CPU_MX6DL) ||
- is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX))
+ (soc_rev() > CHIP_REV_1_0)) || is_cpu_type(MXC_CPU_MX6DL) ||
+ is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX))
return 1;
return 0;
#define ARCH_MXC
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
#if defined(CONFIG_MX51)
#define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
#define IPU_SOC_BASE_ADDR 0x40000000
#define CHIP_REV_1_0 0x10
#define CHIP_REV_1_2 0x12
#define CHIP_REV_1_5 0x15
+#define CHIP_REV_2_0 0x20
#ifndef CONFIG_MX6SX
#define IRAM_SIZE 0x00040000
#else
#include "../arch-imx/cpu.h"
#define soc_rev() (get_cpu_rev() & 0xFF)
-#define is_soc_rev(rev) (soc_rev() - rev)
+#define is_soc_rev(rev) (soc_rev() == rev)
u32 get_nr_cpus(void);
u32 get_cpu_rev(void);
u32 get_cpu_temp_grade(int *minc, int *maxc);
/* returns MXC_CPU_ value */
-#define cpu_type(rev) (((rev) >> 12)&0xff)
+#define cpu_type(rev) (((rev) >> 12) & 0xff)
/* both macros return/take MXC_CPU_ constants */
#define get_cpu_type() (cpu_type(get_cpu_rev()))
unsigned imx_ddr_size(void);
void set_chipselect_size(int const);
+#define is_mx6dqp() ((is_cpu_type(MXC_CPU_MX6Q) || \
+ is_cpu_type(MXC_CPU_MX6D)) && \
+ (soc_rev() >= CHIP_REV_2_0))
+
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
#define SUN4I_GPB_UART0 2
#define SUN5I_GPB_UART0 2
#define SUN8I_GPB_UART2 2
+#define SUN8I_A33_GPB_UART0 3
#define SUNXI_GPC_SDC2 3
#define SUN6I_GPC_SDC3 4
#define IH_ARCH_DEFAULT IH_ARCH_ARM64
#endif
-#if defined(CONFIG_USE_PRIVATE_LIBGCC) && defined(CONFIG_SYS_THUMB_BUILD)
-#error Thumb build does not work with private libgcc.
-#endif
-
#endif /* _U_BOOT_H_ */
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <linux/linkage.h>
+
#ifdef __ARMEB__
#define al r1
#define ah r0
#endif
.globl __ashldi3
-.globl __aeabi_llsl
__ashldi3:
-__aeabi_llsl:
+ENTRY(__aeabi_llsl)
subs r3, r2, #32
rsb ip, r2, #32
orrmi ah, ah, al, lsr ip
mov al, al, lsl r2
mov pc, lr
+ENDPROC(__aeabi_llsl)
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <linux/linkage.h>
+
#ifdef __ARMEB__
#define al r1
#define ah r0
#endif
.globl __ashrdi3
-.globl __aeabi_lasr
__ashrdi3:
-__aeabi_lasr:
+ENTRY(__aeabi_lasr)
subs r3, r2, #32
rsb ip, r2, #32
orrmi al, al, ah, lsl ip
mov ah, ah, asr r2
mov pc, lr
+ENDPROC(__aeabi_lasr)
+#include <linux/linkage.h>
+
.macro ARM_DIV_BODY dividend, divisor, result, curbit
#if __LINUX_ARM_ARCH__ >= 5
.align 5
.globl __divsi3
-.globl __aeabi_idiv
__divsi3:
-__aeabi_idiv:
+ENTRY(__aeabi_idiv)
cmp r1, #0
eor ip, r0, r1 @ save the sign of the result.
beq Ldiv0
bl __div0
mov r0, #0 @ About as wrong as it could be.
ldr pc, [sp], #4
+ENDPROC(__aeabi_idiv)
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <linux/linkage.h>
+
#ifdef __ARMEB__
#define al r1
#define ah r0
#endif
.globl __lshrdi3
-.globl __aeabi_llsr
__lshrdi3:
-__aeabi_llsr:
+ENTRY(__aeabi_llsr)
subs r3, r2, #32
rsb ip, r2, #32
orrmi al, al, ah, lsl ip
mov ah, ah, lsr r2
mov pc, lr
+ENDPROC(__aeabi_llsr)
+#include <linux/linkage.h>
+
.macro ARM_MOD_BODY dividend, divisor, order, spare
#if __LINUX_ARM_ARCH__ >= 5
.endm
.align 5
-.globl __modsi3
-__modsi3:
+ENTRY(__modsi3)
cmp r1, #0
beq Ldiv0
rsbmi r1, r1, #0 @ loops below use unsigned.
10: cmp ip, #0
rsbmi r0, r0, #0
mov pc, lr
-
+ENDPROC(__modsi3)
Ldiv0:
+#include <linux/linkage.h>
+
/* # 1 "libgcc1.S" */
@ libgcc1 routines for ARM cpu.
@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk)
ldmia sp!, {pc}
.size __udivsi3 , . - __udivsi3
-.globl __aeabi_uidivmod
-__aeabi_uidivmod:
+ENTRY(__aeabi_uidivmod)
stmfd sp!, {r0, r1, ip, lr}
bl __aeabi_uidiv
mul r3, r0, r2
sub r1, r1, r3
mov pc, lr
+ENDPROC(__aeabi_uidivmod)
-.globl __aeabi_idivmod
-__aeabi_idivmod:
+ENTRY(__aeabi_idivmod)
stmfd sp!, {r0, r1, ip, lr}
bl __aeabi_idiv
mul r3, r0, r2
sub r1, r1, r3
mov pc, lr
+ENDPROC(__aeabi_idivmod)
+#include <linux/linkage.h>
+
/* # 1 "libgcc1.S" */
@ libgcc1 routines for ARM cpu.
@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk)
/* lr .req r14 */
/* pc .req r15 */
.text
- .globl __umodsi3
.type __umodsi3 ,function
.align 0
- __umodsi3 :
+ ENTRY(__umodsi3)
cmp divisor, #0
beq Ldiv0
mov curbit, #1
/* # 456 "libgcc1.S" */
/* # 500 "libgcc1.S" */
/* # 580 "libgcc1.S" */
+ENDPROC(__umodsi3)
--- /dev/null
+CAIRO BOARD
+M: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
+S: Maintained
+F: board/quipos/cairo/
+F: include/configs/omap3_cairo.h
+F: configs/cairo_defconfig
.p0_mpdgctrl0 = 0x023C0224,
.p0_mpdgctrl1 = 0x02000220,
.p1_mpdgctrl0 = 0x02200220,
- .p1_mpdgctrl1 = 0x02000220,
+ .p1_mpdgctrl1 = 0x02040208,
.p0_mprddlctl = 0x44444846,
.p1_mprddlctl = 0x4042463C,
.p0_mpwrdlctl = 0x32343032,
else if (is_cpu_type(MXC_CPU_MX6Q))
mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
else if (is_cpu_type(MXC_CPU_MX6DL))
- mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g);
+ mx6_dram_cfg(&sysinfo, &mx6dl_1g_mmcd_calib, &mem_ddr_2g);
else if (is_cpu_type(MXC_CPU_MX6SOLO))
mx6_dram_cfg(&sysinfo, &mx6dl_512m_mmcd_calib, &mem_ddr_2g);
}
S: Maintained
F: configs/MSI_Primo81_defconfig
+SINLINX SINA33 BOARD
+M: Chen-Yu Tsai <wens@csie.org>
+S: Maintained
+F: configs/Sinlinx_SinA33_defconfig
+W: http://linux-sunxi.org/Sinlinx_SinA33
+
TZX-Q8-713B7 BOARD
M: Paul Kocialkowski <contact@paulk.fr>
S: Maintained
F: include/configs/am43xx_evm.h
F: configs/am43xx_evm_defconfig
F: configs/am43xx_evm_qspiboot_defconfig
+F: configs/am43xx_evm_ethboot_defconfig
+F: configs/am43xx_evm_usbhost_boot_defconfig
#ifdef CONFIG_IODELAY_RECALIBRATION
const struct iodelay_cfg_entry iodelay_cfg_array[] = {
- {0x6F0, 480, 0}, /* RGMMI0_RXC_IN */
- {0x6FC, 111, 1641}, /* RGMMI0_RXCTL_IN */
- {0x708, 272, 1116}, /* RGMMI0_RXD0_IN */
- {0x714, 243, 1260}, /* RGMMI0_RXD1_IN */
- {0x720, 0, 1614}, /* RGMMI0_RXD2_IN */
- {0x72C, 105, 1673}, /* RGMMI0_RXD3_IN */
- {0x740, 531, 120}, /* RGMMI0_TXC_OUT */
- {0x74C, 11, 60}, /* RGMMI0_TXCTL_OUT */
- {0x758, 7, 120}, /* RGMMI0_TXD0_OUT */
- {0x764, 0, 0}, /* RGMMI0_TXD1_OUT */
- {0x770, 276, 120}, /* RGMMI0_TXD2_OUT */
- {0x77C, 440, 120}, /* RGMMI0_TXD3_OUT */
- {0xAB0, 702, 0}, /* CFG_VIN2A_D18_IN */
- {0xABC, 136, 976}, /* CFG_VIN2A_D19_IN */
- {0xAD4, 210, 1357}, /* CFG_VIN2A_D20_IN */
- {0xAE0, 189, 1462}, /* CFG_VIN2A_D21_IN */
- {0xAEC, 232, 1278}, /* CFG_VIN2A_D22_IN */
- {0xAF8, 0, 1397}, /* CFG_VIN2A_D23_IN */
- {0xA70, 1551, 115}, /* CFG_VIN2A_D12_OUT */
- {0xA7C, 816, 0}, /* CFG_VIN2A_D13_OUT */
- {0xA88, 876, 0}, /* CFG_VIN2A_D14_OUT */
- {0xA94, 312, 0}, /* CFG_VIN2A_D15_OUT */
- {0xAA0, 58, 0}, /* CFG_VIN2A_D16_OUT */
- {0xAAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
+ {0x6F0, 359, 0}, /* RGMMI0_RXC_IN */
+ {0x6FC, 129, 1896}, /* RGMMI0_RXCTL_IN */
+ {0x708, 80, 1391}, /* RGMMI0_RXD0_IN */
+ {0x714, 196, 1522}, /* RGMMI0_RXD1_IN */
+ {0x720, 40, 1860}, /* RGMMI0_RXD2_IN */
+ {0x72C, 0, 1956}, /* RGMMI0_RXD3_IN */
+ {0x740, 0, 220}, /* RGMMI0_TXC_OUT */
+ {0x74C, 1820, 180}, /* RGMMI0_TXCTL_OUT */
+ {0x758, 1740, 440}, /* RGMMI0_TXD0_OUT */
+ {0x764, 1740, 240}, /* RGMMI0_TXD1_OUT */
+ {0x770, 1680, 380}, /* RGMMI0_TXD2_OUT */
+ {0x77C, 1740, 440}, /* RGMMI0_TXD3_OUT */
+ /* These values are for using RGMII1 configuration on VIN2a_x pins. */
+ {0xAB0, 596, 0}, /* CFG_VIN2A_D18_IN */
+ {0xABC, 314, 980}, /* CFG_VIN2A_D19_IN */
+ {0xAD4, 241, 1536}, /* CFG_VIN2A_D20_IN */
+ {0xAE0, 103, 1689}, /* CFG_VIN2A_D21_IN */
+ {0xAEC, 161, 1563}, /* CFG_VIN2A_D22_IN */
+ {0xAF8, 0, 1613}, /* CFG_VIN2A_D23_IN */
+ {0xA70, 0, 200}, /* CFG_VIN2A_D12_OUT */
+ {0xA7C, 1560, 140}, /* CFG_VIN2A_D13_OUT */
+ {0xA88, 1700, 0}, /* CFG_VIN2A_D14_OUT */
+ {0xA94, 1260, 0}, /* CFG_VIN2A_D15_OUT */
+ {0xAA0, 1400, 0}, /* CFG_VIN2A_D16_OUT */
+ {0xAAC, 1290, 0}, /* CFG_VIN2A_D17_OUT */
};
#endif
config SYS_CONFIG_NAME
default "tqma6"
+choice
+ prompt "TQMa6 SoC variant"
+ default TQMA6Q
+ help
+ select the TQMa6 module variant. The variants differing in the used
+ i.MX6 CPU type and DRAM
+
+config TQMA6Q
+ bool "TQMa6Q / TQMa6D"
+ select MX6Q
+ help
+ select TQMa6Q / TQMa6D with i.MX6Q/D and 1GiB DRAM
+
+config TQMA6S
+ bool "TQMa6S"
+ select MX6S
+ help
+ select TQMa6S with i.MX6S and 512 MiB DRAM
+
+endchoice
+
+choice
+ prompt "TQMa6 boot configuration"
+ default TQMA6X_MMC_BOOT
+ help
+ Configure boot device. This is also used to implement environment
+ location.
+
+config TQMA6X_MMC_BOOT
+ bool "MMC / SD Boot"
+ help
+ Boot from eMMC / SD Card
+
+config TQMA6X_SPI_BOOT
+ bool "SPI NOR Boot"
+ help
+ Boot from on board SPI NOR flash
+
+endchoice
+
+choice
+ prompt "TQMa6 base board variant"
+ default MBA6
+ help
+ Select base board for TQMa6
+
+config MBA6
+ bool "TQMa6 on MBa6 Starterkit"
+ help
+ Select the MBa6 starterkit. This features a GigE Phy, USB, SD-Card
+ etc.
+
+endchoice
+
+config IMX_CONFIG
+ default "board/tqc/tqma6/tqma6q.cfg" if TQMA6Q
+ default "board/tqc/tqma6/tqma6s.cfg" if TQMA6S
+
endif
--- /dev/null
+BALTOS BOARD
+M: Yegor Yefremov <yegorslists@googlemail.com>
+S: Maintained
+F: board/vscom/baltos/
+F: include/configs/baltos.h
+F: configs/am335x_baltos_defconfig
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_USB_MUSB_SUNXI=y
-CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-ippo-q8h-v1.2-lcd1024x600"
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-ippo-q8h-v1.2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_A33=y
+CONFIG_DRAM_CLK=552
+CONFIG_DRAM_ZQ=15291
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
+CONFIG_AXP221_ALDO1_VOLT=3000
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_DM=y
+CONFIG_DM_THERMAL=y
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TQMA6=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/tqc/tqma6/tqma6q.cfg,MX6Q,MBA6,TQMA6X_MMC_BOOT"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TQMA6=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/tqc/tqma6/tqma6q.cfg,MX6Q,MBA6,TQMA6X_SPI_BOOT"
+CONFIG_TQMA6X_SPI_BOOT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TQMA6=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/tqc/tqma6/tqma6s.cfg,MX6S,MBA6,TQMA6X_MMC_BOOT"
+CONFIG_TQMA6S=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TQMA6=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/tqc/tqma6/tqma6s.cfg,MX6S,MBA6,TQMA6X_SPI_BOOT"
+CONFIG_TQMA6S=y
+CONFIG_TQMA6X_SPI_BOOT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
#define LPC32XX_GPIOS 128
-struct lpc32xx_gpio_platdata {
+struct lpc32xx_gpio_priv {
struct gpio_regs *regs;
/* GPIO FUNCTION: SEE WARNING #2 */
signed char function[LPC32XX_GPIOS];
static int lpc32xx_gpio_direction_input(struct udevice *dev, unsigned offset)
{
int port, mask;
- struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev);
- struct gpio_regs *regs = gpio_platdata->regs;
+ struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
+ struct gpio_regs *regs = gpio_priv->regs;
port = GPIO_TO_PORT(offset);
mask = GPIO_TO_MASK(offset);
}
/* GPIO FUNCTION: SEE WARNING #2 */
- gpio_platdata->function[offset] = GPIOF_INPUT;
+ gpio_priv->function[offset] = GPIOF_INPUT;
return 0;
}
static int lpc32xx_gpio_get_value(struct udevice *dev, unsigned offset)
{
int port, rank, mask, value;
- struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev);
- struct gpio_regs *regs = gpio_platdata->regs;
+ struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
+ struct gpio_regs *regs = gpio_priv->regs;
port = GPIO_TO_PORT(offset);
static int gpio_set(struct udevice *dev, unsigned gpio)
{
int port, mask;
- struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev);
- struct gpio_regs *regs = gpio_platdata->regs;
+ struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
+ struct gpio_regs *regs = gpio_priv->regs;
port = GPIO_TO_PORT(gpio);
mask = GPIO_TO_MASK(gpio);
static int gpio_clr(struct udevice *dev, unsigned gpio)
{
int port, mask;
- struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev);
- struct gpio_regs *regs = gpio_platdata->regs;
+ struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
+ struct gpio_regs *regs = gpio_priv->regs;
port = GPIO_TO_PORT(gpio);
mask = GPIO_TO_MASK(gpio);
int value)
{
int port, mask;
- struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev);
- struct gpio_regs *regs = gpio_platdata->regs;
+ struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
+ struct gpio_regs *regs = gpio_priv->regs;
port = GPIO_TO_PORT(offset);
mask = GPIO_TO_MASK(offset);
}
/* GPIO FUNCTION: SEE WARNING #2 */
- gpio_platdata->function[offset] = GPIOF_OUTPUT;
+ gpio_priv->function[offset] = GPIOF_OUTPUT;
return lpc32xx_gpio_set_value(dev, offset, value);
}
static int lpc32xx_gpio_get_function(struct udevice *dev, unsigned offset)
{
- struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev);
- return gpio_platdata->function[offset];
+ struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
+ return gpio_priv->function[offset];
}
static const struct dm_gpio_ops gpio_lpc32xx_ops = {
static int lpc32xx_gpio_probe(struct udevice *dev)
{
- struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev);
+ struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
struct gpio_dev_priv *uc_priv = dev->uclass_priv;
if (dev->of_offset == -1) {
}
/* set base address for GPIO registers */
- gpio_platdata->regs = (struct gpio_regs *)GPIO_BASE;
+ gpio_priv->regs = (struct gpio_regs *)GPIO_BASE;
/* all GPIO functions are unknown until requested */
/* GPIO FUNCTION: SEE WARNING #2 */
- memset(gpio_platdata->function, GPIOF_UNKNOWN,
- sizeof(gpio_platdata->function));
+ memset(gpio_priv->function, GPIOF_UNKNOWN, sizeof(gpio_priv->function));
return 0;
}
.id = UCLASS_GPIO,
.ops = &gpio_lpc32xx_ops,
.probe = lpc32xx_gpio_probe,
- .priv_auto_alloc_size = sizeof(struct lpc32xx_gpio_platdata),
+ .priv_auto_alloc_size = sizeof(struct lpc32xx_gpio_priv),
};
mdelay(100);
};
+ /*
+ * Soft reset above clears HW address registers.
+ * So we have to set it here once again.
+ */
+ _dw_write_hwaddr(priv, enetaddr);
+
rx_descs_init(priv);
tx_descs_init(priv);
#define status_dcc(x) \
__asm__ volatile ("mrc p14, 0, %0, c14, c0, 0\n" : "=r" (x))
+#elif defined(CONFIG_CPU_ARMV8)
+/*
+ * ARMV8
+ */
+#define DCC_RBIT (1 << 30)
+#define DCC_WBIT (1 << 29)
+
+#define write_dcc(x) \
+ __asm__ volatile ("msr dbgdtrtx_el0, %0\n" : : "r" (x))
+
+#define read_dcc(x) \
+ __asm__ volatile ("mrs %0, dbgdtrrx_el0\n" : "=r" (x))
+
+#define status_dcc(x) \
+ __asm__ volatile ("mrs %0, mdccsr_el0\n" : "=r" (x))
+
#else
#define DCC_RBIT (1 << 0)
#define DCC_WBIT (1 << 1)
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_PROMPT "Colibri VFxx # "
#undef CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_CMD_FAT
/* Miscellaneous configurable options */
-#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_CMDLINE_EDITING
"fi; " \
"else run netboot; fi"
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_CMDLINE_EDITING
-
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
+#define CONFIG_FAT_WRITE
#define CONFIG_CMD_FUSE
#define CONFIG_CMD_MII
#define CONFIG_CMD_PCI
#define CONFIG_SYS_PROMPT "Matrix U-Boot> "
#define CONFIG_SYS_HZ 1000
+#define CONFIG_IMX6_THERMAL
+
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
#define CONFIG_CONSOLE_MUX
#define CONFIG_CONS_INDEX 1
+#define CONFIG_PRE_CONSOLE_BUFFER
+#define CONFIG_PRE_CON_BUF_SZ 4096
+#define CONFIG_PRE_CON_BUF_ADDR 0x7C000000
+
/* *** Command definition *** */
#define CONFIG_CMD_BMODE
#define CONFIG_CMD_MEMTEST
#ifndef __CONFIG_H
#define __CONFIG_H
+#include <linux/kconfig.h>
/* SPL */
/* #if defined(CONFIG_SPL_BUILD) */
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