On i.MX6SX, 6UL and 7D, there are two enet controllers each has a
MDIO port. But Some boards share one MDIO port for the two enets. So
introduce a configuration CONFIG_FEC_MXC_MDIO_BASE to indicate
the MDIO port for sharing.
In Kconfig, user needs enable CONFIG_FEC_MXC_SHARE_MDIO first to enter
the CONFIG_FEC_MXC_MDIO_BASE.
To i.MX28, adapt to use the new config
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
help
This MAC is present in OpenRISC and Xtensa XTFPGA boards.
+config FEC_MXC_SHARE_MDIO
+ bool "Share the MDIO bus for FEC controller"
+ depends on FEC_MXC
+
+config FEC_MXC_MDIO_BASE
+ hex "MDIO base address for the FEC controller"
+ depends on FEC_MXC_SHARE_MDIO
+ help
+ This specifies the MDIO registers base address. It is used when
+ two FEC controllers share MDIO bus.
+
config FEC_MXC
bool "FEC Ethernet controller"
- depends on MX5 || MX6
+ depends on MX5 || MX6 || MX7
help
This driver supports the 10/100 Fast Ethernet controller for
NXP i.MX processors.
#endif
int ret;
-#ifdef CONFIG_MX28
+#ifdef CONFIG_FEC_MXC_MDIO_BASE
/*
* The i.MX28 has two ethernet interfaces, but they are not equal.
* Only the first one can access the MDIO bus.
*/
- base_mii = MXS_ENET0_BASE;
+ base_mii = CONFIG_FEC_MXC_MDIO_BASE;
#else
base_mii = addr;
#endif
fec_reg_setup(priv);
priv->dev_id = dev->seq;
+#ifdef CONFIG_FEC_MXC_MDIO_BASE
+ bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE, dev->seq);
+#else
bus = fec_get_miibus((ulong)priv->eth, dev->seq);
+#endif
if (!bus) {
ret = -ENOMEM;
goto err_mii;
/* FEC Ethernet on SoC */
#ifdef CONFIG_CMD_NET
#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_MDIO_BASE MXS_ENET0_BASE
#define CONFIG_MX28_FEC_MAC_IN_OCOTP
#endif