switch (spl_boot_device()) {
case BOOT_DEVICE_MMC1:
#ifdef CONFIG_SPL_FAT_SUPPORT
- return MMCSD_MODE_FAT;
+ return MMCSD_MODE_FS;
#else
return MMCSD_MODE_RAW;
#endif
flush_dcache_range((ulong)level0_table,
(ulong)level0_table + gd->arch.tlb_size);
-#ifdef CONFIG_SYS_DPAA_FMAN
- flush_dcache_all();
-#endif
/* point TTBR to the new table */
set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR_FINAL,
MEMORY_ATTRIBUTES);
#ifdef CONFIG_MP
#include <asm/arch/mp.h>
#endif
+#include <fsl_sec.h>
+#include <asm/arch-fsl-layerscape/soc.h>
int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
{
void ft_cpu_setup(void *blob, bd_t *bd)
{
+#ifdef CONFIG_FSL_LSCH2
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ unsigned int svr = in_be32(&gur->svr);
+
+ /* delete crypto node if not on an E-processor */
+ if (!IS_E_PROCESSOR(svr))
+ fdt_fixup_crypto_node(blob, 0);
+#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
+ else {
+ ccsr_sec_t __iomem *sec;
+
+ sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+ fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
+ }
+#endif
+#endif
+
#ifdef CONFIG_MP
ft_fixup_cpu(blob);
#endif
#include <asm/io.h>
#include <asm/global_data.h>
#include <asm/arch-fsl-layerscape/config.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr.h>
#ifdef CONFIG_CHAIN_OF_TRUST
#include <fsl_validate.h>
#endif
#endif
}
+static void erratum_a008850_early(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
+ /* part 1 of 2 */
+ struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
+ struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+
+ /* disables propagation of barrier transactions to DDRC from CCI400 */
+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
+
+ /* disable the re-ordering in DDRC */
+ ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
+#endif
+}
+
+void erratum_a008850_post(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
+ /* part 2 of 2 */
+ struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
+ struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ u32 tmp;
+
+ /* enable propagation of barrier transactions to DDRC from CCI400 */
+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+ /* enable the re-ordering in DDRC */
+ tmp = ddr_in32(&ddr->eor);
+ tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
+ ddr_out32(&ddr->eor, tmp);
+#endif
+}
+
void fsl_lsch2_early_init_f(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
/* Erratum */
+ erratum_a008850_early(); /* part 1 of 2 */
erratum_a009929();
erratum_a009660();
}
switch (spl_boot_device()) {
case BOOT_DEVICE_MMC1:
#ifdef CONFIG_SPL_FAT_SUPPORT
- return MMCSD_MODE_FAT;
+ return MMCSD_MODE_FS;
#else
return MMCSD_MODE_RAW;
#endif
memset((void *)gd, 0, sizeof(gd_t));
#ifdef CONFIG_LS2080A
arch_cpu_init();
-#endif
-#ifdef CONFIG_FSL_IFC
- init_early_memctl_regs();
#endif
board_early_init_f();
timer_init();
compatible = "fsl,vf610-qspi";
#address-cells = <1>;
#size-cells = <0>;
- reg = <0x1550000 0x10000>,
- <0x40000000 0x4000000>;
+ reg = <0x0 0x1550000 0x0 0x10000>,
+ <0x0 0x40000000 0x0 0x4000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
num-cs = <2>;
big-endian;
status = "disabled";
#define CONFIG_SYS_FSL_ERRATUM_A008751
#define CONFIG_SYS_FSL_ERRATUM_A009635
#define CONFIG_SYS_FSL_ERRATUM_A009663
+#define CONFIG_SYS_FSL_ERRATUM_A009801
#define CONFIG_SYS_FSL_ERRATUM_A009803
#define CONFIG_SYS_FSL_ERRATUM_A009942
+#define CONFIG_SYS_FSL_ERRATUM_A010165
/* ARM A57 CORE ERRATA */
#define CONFIG_ARM_ERRATA_826974
#define CONFIG_ARM_ERRATA_829520
#define CONFIG_ARM_ERRATA_833471
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#elif defined(CONFIG_LS1043A)
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_CACHELINE_SIZE 64
#define GICD_BASE 0x01401000
#define GICC_BASE 0x01402000
+#define CONFIG_SYS_FSL_ERRATUM_A008850
#define CONFIG_SYS_FSL_ERRATUM_A009663
#define CONFIG_SYS_FSL_ERRATUM_A009929
#define CONFIG_SYS_FSL_ERRATUM_A009942
#define CONFIG_SYS_FSL_ERRATUM_A009660
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#else
#error SoC not defined
#endif
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
-#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000)
-#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000)
#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000)
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
+#define CONFIG_SYS_FSL_SEC_OFFSET 0x700000ull
+#define CONFIG_SYS_FSL_JR0_OFFSET 0x710000ull
+#define CONFIG_SYS_FSL_SEC_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
+
/* Device Configuration and Pin Control */
struct ccsr_gur {
u32 porsr1; /* POR status 1 */
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
/* SEC */
-#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x07000000)
-#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x07010000)
+#define CONFIG_SYS_FSL_SEC_OFFSET 0x07000000ull
+#define CONFIG_SYS_FSL_JR0_OFFSET 0x07010000ull
+#define CONFIG_SYS_FSL_SEC_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
/* Security Monitor */
#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
(CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
#define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000
+#define CONFIG_SYS_FSL_JR0_OFFSET 0x00710000
#define CONFIG_SYS_LS102XA_USB1_OFFSET 0x07600000
#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
#define CONFIG_SYS_TSEC2_OFFSET 0x01d50000
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_ERRATUM_A008378
#define CONFIG_SYS_FSL_ERRATUM_A009663
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#else
#error SoC not defined
#endif
#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
-#define CONFIG_SYS_FSL_SEC_ADDR CAAM_BASE_ADDR
-#define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + 0x1000)
+#define CONFIG_SYS_FSL_SEC_OFFSET 0
+#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \
+ CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
+#define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \
+ CONFIG_SYS_FSL_JR0_OFFSET)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
#define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
#define FEC_QUIRK_ENET_MAC
#define SNVS_LPGPR 0x68
-
-#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR)
-#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + 0x1000)
-
+#define CONFIG_SYS_FSL_SEC_OFFSET 0
+#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
+ CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
+#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
+ CONFIG_SYS_FSL_JR0_OFFSET)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/imx-common/regs-lcdif.h>
#include <asm/types.h>
#ifdef CONFIG_FSL_CAAM
sec_init();
+
+#if defined(CONFIG_PPC_C29X)
+ if ((SVR_SOC_VER(svr) == SVR_C292) ||
+ (SVR_SOC_VER(svr) == SVR_C293))
+ sec_init_idx(1);
+
+ if (SVR_SOC_VER(svr) == SVR_C293)
+ sec_init_idx(2);
+#endif
#endif
#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
+#define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
#elif defined(CONFIG_QEMU_E500)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_DDRC_GEN3
#endif
+#if !defined(CONFIG_PPC_C29X)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
+#endif
+
#endif /* _ASM_MPC85xx_CONFIG_H_ */
while ((nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,sec-v6.0",
CONFIG_SYS_CCSRBAR_PHYS + CONFIG_SYS_FSL_SEC_OFFSET
- + offset * 0x20000)) >= 0) {
+ + offset * CONFIG_SYS_FSL_SEC_IDX_OFFSET)) >= 0) {
fdt_del_node(blob, nodeoff);
offset++;
}
void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num)
{
- uint32_t *scfg = (uint32_t *)CONFIG_SYS_FSL_SCFG_ADDR;
+ void *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
int i;
for (i = 0; i < num; i++)
- out_be32(scfg + id[i].offset, id[i].stream_id);
+ out_be32((u32 *)(scfg + id[i].offset), id[i].stream_id);
}
void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size)
else
liodn = tbl[i].id[0];
- out_le32((uint32_t *)(tbl[i].reg_offset), liodn);
+ out_le32((u32 *)(tbl[i].reg_offset), liodn);
}
}
dram_size = fsl_ddr_sdram();
#endif
+ erratum_a008850_post();
#ifdef CONFIG_FSL_DEEP_SLEEP
fsl_dp_ddr_restore();
#ifndef __DDR_H__
#define __DDR_H__
+extern void erratum_a008850_post(void);
+
struct board_specific_parameters {
u32 n_ranks;
u32 datarate_mhz_high;
int board_init(void)
{
- struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
- CONFIG_SYS_CCI400_ADDR;
-
- /* Set CCI-400 control override register to enable barrier
- * transaction */
- out_le32(&cci->ctrl_ord,
- CCI400_CTRLORD_EN_BARRIER);
-
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
board_retimer_init();
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
#endif
-
-#ifdef CONFIG_ENV_IS_NOWHERE
- gd->env_addr = (ulong)&default_environment[0];
-#endif
return 0;
}
/* Set the boot bank to the alternate bank */
void cpld_set_altbank(void)
{
+ u16 reg = CPLD_CFG_RCW_SRC_NOR;
u8 reg4 = CPLD_READ(soft_mux_on);
+ u8 reg5 = (u8)(reg >> 1);
+ u8 reg6 = (u8)(reg & 1);
u8 reg7 = CPLD_READ(vbank);
- CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL);
+ cpld_rev_bit(®5);
+
+ CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
+
+ CPLD_WRITE(cfg_rcw_src1, reg5);
+ CPLD_WRITE(cfg_rcw_src2, reg6);
reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK;
CPLD_WRITE(vbank, reg7);
/* Set the boot bank to the default bank */
void cpld_set_defbank(void)
{
- CPLD_WRITE(global_rst, 1);
+ u16 reg = CPLD_CFG_RCW_SRC_NOR;
+ u8 reg4 = CPLD_READ(soft_mux_on);
+ u8 reg5 = (u8)(reg >> 1);
+ u8 reg6 = (u8)(reg & 1);
+
+ cpld_rev_bit(®5);
+
+ CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
+
+ CPLD_WRITE(cfg_rcw_src1, reg5);
+ CPLD_WRITE(cfg_rcw_src2, reg6);
+
+ CPLD_WRITE(vbank, 0);
+
+ CPLD_WRITE(system_rst, 1);
}
void cpld_set_nand(void)
#define CPLD_SW_MUX_BANK_SEL 0x40
#define CPLD_BANK_SEL_MASK 0x07
#define CPLD_BANK_SEL_ALTBANK 0x04
+#define CPLD_CFG_RCW_SRC_NOR 0x025
#define CPLD_CFG_RCW_SRC_NAND 0x106
#define CPLD_CFG_RCW_SRC_SD 0x040
#endif
#else
dram_size = fsl_ddr_sdram_size();
#endif
+ erratum_a008850_post();
+
#ifdef CONFIG_FSL_DEEP_SLEEP
fsl_dp_ddr_restore();
#endif
#ifndef __DDR_H__
#define __DDR_H__
+
+extern void erratum_a008850_post(void);
+
struct board_specific_parameters {
u32 n_ranks;
u32 datarate_mhz_high;
#include <fsl_csu.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
-#include <environment.h>
#include <fsl_sec.h>
#include "cpld.h"
#ifdef CONFIG_U_QE
int checkboard(void)
{
- static const char *freq[3] = {"100.00MHZ", "156.25MHZ"};
+ static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
#ifndef CONFIG_SD_BOOT
u8 cfg_rcw_src1, cfg_rcw_src2;
- u32 cfg_rcw_src;
+ u16 cfg_rcw_src;
#endif
- u32 sd1refclk_sel;
+ u8 sd1refclk_sel;
printf("Board: LS1043ARDB, boot from ");
int board_init(void)
{
- struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
-
- /*
- * Set CCI-400 control override register to enable barrier
- * transaction
- */
- out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_FSL_IFC
init_final_memctl_regs();
#endif
-#ifdef CONFIG_ENV_IS_NOWHERE
- gd->env_addr = (ulong)&default_environment[0];
-#endif
-
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
#endif
#ifdef CONFIG_U_QE
u_qe_init();
#endif
+ /* invert AQR105 IRQ pins polarity */
+ out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
return 0;
}
LS2080A BOARD
-M: Prabhakar Kushwaha <prabhakar@freescale.com>
+M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
S: Maintained
F: board/freescale/ls2080aqds/
F: board/freescale/ls2080a/ls2080aqds.c
LS2080A BOARD
-M: Prabhakar Kushwaha <prabhakar@freescale.com>
+M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
S: Maintained
F: board/freescale/ls2080ardb/
F: board/freescale/ls2080a/ls2080ardb.c
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
{2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
- {2, 1666, 0, 4, 8, 0x08090B0D, 0x0E10100C,},
- {2, 1900, 0, 4, 8, 0x090A0C0E, 0x1012120D,},
- {2, 2300, 0, 4, 9, 0x0A0B0C10, 0x1114140E,},
+ {2, 1666, 0, 5, 9, 0x090A0B0E, 0x0F11110C,},
+ {2, 1900, 0, 6, 0xA, 0x0B0C0E11, 0x1214140F,},
+ {2, 2300, 0, 6, 0xB, 0x0C0D0F12, 0x14161610,},
{}
};
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SYS_NS16550=y
CONFIG_RSA=y
CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="LPUART"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
CONFIG_HUSH_PARSER=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
CONFIG_HUSH_PARSER=y
CONFIG_SYS_NS16550=y
CONFIG_RSA=y
CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-lpuart"
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="LPUART"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SPL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
#define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
#define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size))
-struct jobring jr;
+uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
+ 0,
+#if defined(CONFIG_PPC_C29X)
+ CONFIG_SYS_FSL_SEC_IDX_OFFSET,
+ 2 * CONFIG_SYS_FSL_SEC_IDX_OFFSET
+#endif
+};
+
+#define SEC_ADDR(idx) \
+ ((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
+
+#define SEC_JR0_ADDR(idx) \
+ (SEC_ADDR(idx) + \
+ (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
+
+struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
-static inline void start_jr0(void)
+static inline void start_jr0(uint8_t sec_idx)
{
- ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+ ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
u32 scfgr = sec_in32(&sec->scfgr);
}
}
-static inline void jr_reset_liodn(void)
+static inline void jr_reset_liodn(uint8_t sec_idx)
{
- ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+ ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
sec_out32(&sec->jrliodnr[0].ls, 0);
}
-static inline void jr_disable_irq(void)
+static inline void jr_disable_irq(uint8_t sec_idx)
{
- struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
+ struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
uint32_t jrcfg = sec_in32(®s->jrcfg1);
jrcfg = jrcfg | JR_INTMASK;
sec_out32(®s->jrcfg1, jrcfg);
}
-static void jr_initregs(void)
+static void jr_initregs(uint8_t sec_idx)
{
- struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
- phys_addr_t ip_base = virt_to_phys((void *)jr.input_ring);
- phys_addr_t op_base = virt_to_phys((void *)jr.output_ring);
+ struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
+ struct jobring *jr = &jr0[sec_idx];
+ phys_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
+ phys_addr_t op_base = virt_to_phys((void *)jr->output_ring);
#ifdef CONFIG_PHYS_64BIT
sec_out32(®s->irba_h, ip_base >> 32);
sec_out32(®s->ors, JR_SIZE);
sec_out32(®s->irs, JR_SIZE);
- if (!jr.irq)
- jr_disable_irq();
+ if (!jr->irq)
+ jr_disable_irq(sec_idx);
}
-static int jr_init(void)
+static int jr_init(uint8_t sec_idx)
{
- memset(&jr, 0, sizeof(struct jobring));
+ struct jobring *jr = &jr0[sec_idx];
- jr.jq_id = DEFAULT_JR_ID;
- jr.irq = DEFAULT_IRQ;
+ memset(jr, 0, sizeof(struct jobring));
+
+ jr->jq_id = DEFAULT_JR_ID;
+ jr->irq = DEFAULT_IRQ;
#ifdef CONFIG_FSL_CORENET
- jr.liodn = DEFAULT_JR_LIODN;
+ jr->liodn = DEFAULT_JR_LIODN;
#endif
- jr.size = JR_SIZE;
- jr.input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN,
+ jr->size = JR_SIZE;
+ jr->input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN,
JR_SIZE * sizeof(dma_addr_t));
- if (!jr.input_ring)
+ if (!jr->input_ring)
return -1;
- jr.op_size = roundup(JR_SIZE * sizeof(struct op_ring),
- ARCH_DMA_MINALIGN);
- jr.output_ring =
- (struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr.op_size);
- if (!jr.output_ring)
+ jr->op_size = roundup(JR_SIZE * sizeof(struct op_ring),
+ ARCH_DMA_MINALIGN);
+ jr->output_ring =
+ (struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr->op_size);
+ if (!jr->output_ring)
return -1;
- memset(jr.input_ring, 0, JR_SIZE * sizeof(dma_addr_t));
- memset(jr.output_ring, 0, jr.op_size);
+ memset(jr->input_ring, 0, JR_SIZE * sizeof(dma_addr_t));
+ memset(jr->output_ring, 0, jr->op_size);
- start_jr0();
+ start_jr0(sec_idx);
- jr_initregs();
+ jr_initregs(sec_idx);
return 0;
}
-static int jr_sw_cleanup(void)
+static int jr_sw_cleanup(uint8_t sec_idx)
{
- jr.head = 0;
- jr.tail = 0;
- jr.read_idx = 0;
- jr.write_idx = 0;
- memset(jr.info, 0, sizeof(jr.info));
- memset(jr.input_ring, 0, jr.size * sizeof(dma_addr_t));
- memset(jr.output_ring, 0, jr.size * sizeof(struct op_ring));
+ struct jobring *jr = &jr0[sec_idx];
+
+ jr->head = 0;
+ jr->tail = 0;
+ jr->read_idx = 0;
+ jr->write_idx = 0;
+ memset(jr->info, 0, sizeof(jr->info));
+ memset(jr->input_ring, 0, jr->size * sizeof(dma_addr_t));
+ memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
return 0;
}
-static int jr_hw_reset(void)
+static int jr_hw_reset(uint8_t sec_idx)
{
- struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
+ struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
uint32_t timeout = 100000;
uint32_t jrint, jrcr;
/* -1 --- error, can't enqueue -- no space available */
static int jr_enqueue(uint32_t *desc_addr,
void (*callback)(uint32_t status, void *arg),
- void *arg)
+ void *arg, uint8_t sec_idx)
{
- struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
- int head = jr.head;
+ struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
+ struct jobring *jr = &jr0[sec_idx];
+ int head = jr->head;
uint32_t desc_word;
int length = desc_len(desc_addr);
int i;
phys_addr_t desc_phys_addr = virt_to_phys(desc_addr);
- if (sec_in32(®s->irsa) == 0 ||
- CIRC_SPACE(jr.head, jr.tail, jr.size) <= 0)
- return -1;
-
- jr.info[head].desc_phys_addr = desc_phys_addr;
- jr.info[head].callback = (void *)callback;
- jr.info[head].arg = arg;
- jr.info[head].op_done = 0;
+ jr->info[head].desc_phys_addr = desc_phys_addr;
+ jr->info[head].callback = (void *)callback;
+ jr->info[head].arg = arg;
+ jr->info[head].op_done = 0;
- unsigned long start = (unsigned long)&jr.info[head] &
+ unsigned long start = (unsigned long)&jr->info[head] &
~(ARCH_DMA_MINALIGN - 1);
- unsigned long end = ALIGN((unsigned long)&jr.info[head] +
+ unsigned long end = ALIGN((unsigned long)&jr->info[head] +
sizeof(struct jr_info), ARCH_DMA_MINALIGN);
flush_dcache_range(start, end);
* depend on endianness of SEC block.
*/
#ifdef CONFIG_SYS_FSL_SEC_LE
- addr_lo = (uint32_t *)(&jr.input_ring[head]);
- addr_hi = (uint32_t *)(&jr.input_ring[head]) + 1;
+ addr_lo = (uint32_t *)(&jr->input_ring[head]);
+ addr_hi = (uint32_t *)(&jr->input_ring[head]) + 1;
#elif defined(CONFIG_SYS_FSL_SEC_BE)
- addr_hi = (uint32_t *)(&jr.input_ring[head]);
- addr_lo = (uint32_t *)(&jr.input_ring[head]) + 1;
+ addr_hi = (uint32_t *)(&jr->input_ring[head]);
+ addr_lo = (uint32_t *)(&jr->input_ring[head]) + 1;
#endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
sec_out32(addr_hi, (uint32_t)(desc_phys_addr >> 32));
#else
/* Write the 32 bit Descriptor address on Input Ring. */
- sec_out32(&jr.input_ring[head], desc_phys_addr);
+ sec_out32(&jr->input_ring[head], desc_phys_addr);
#endif /* ifdef CONFIG_PHYS_64BIT */
- start = (unsigned long)&jr.input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
- end = ALIGN((unsigned long)&jr.input_ring[head] +
+ start = (unsigned long)&jr->input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
+ end = ALIGN((unsigned long)&jr->input_ring[head] +
sizeof(dma_addr_t), ARCH_DMA_MINALIGN);
flush_dcache_range(start, end);
- jr.head = (head + 1) & (jr.size - 1);
+ jr->head = (head + 1) & (jr->size - 1);
/* Invalidate output ring */
- start = (unsigned long)jr.output_ring &
+ start = (unsigned long)jr->output_ring &
~(ARCH_DMA_MINALIGN - 1);
- end = ALIGN((unsigned long)jr.output_ring + jr.op_size,
- ARCH_DMA_MINALIGN);
+ end = ALIGN((unsigned long)jr->output_ring + jr->op_size,
+ ARCH_DMA_MINALIGN);
invalidate_dcache_range(start, end);
sec_out32(®s->irja, 1);
return 0;
}
-static int jr_dequeue(void)
+static int jr_dequeue(int sec_idx)
{
- struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
- int head = jr.head;
- int tail = jr.tail;
+ struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
+ struct jobring *jr = &jr0[sec_idx];
+ int head = jr->head;
+ int tail = jr->tail;
int idx, i, found;
void (*callback)(uint32_t status, void *arg);
void *arg = NULL;
uint32_t *addr;
#endif
- while (sec_in32(®s->orsf) && CIRC_CNT(jr.head, jr.tail, jr.size)) {
+ while (sec_in32(®s->orsf) && CIRC_CNT(jr->head, jr->tail,
+ jr->size)) {
found = 0;
* depend on endianness of SEC block.
*/
#ifdef CONFIG_SYS_FSL_SEC_LE
- addr_lo = (uint32_t *)(&jr.output_ring[jr.tail].desc);
- addr_hi = (uint32_t *)(&jr.output_ring[jr.tail].desc) + 1;
+ addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc);
+ addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1;
#elif defined(CONFIG_SYS_FSL_SEC_BE)
- addr_hi = (uint32_t *)(&jr.output_ring[jr.tail].desc);
- addr_lo = (uint32_t *)(&jr.output_ring[jr.tail].desc) + 1;
+ addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc);
+ addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1;
#endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
op_desc = ((u64)sec_in32(addr_hi) << 32) |
#else
/* Read the 32 bit Descriptor address from Output Ring. */
- addr = (uint32_t *)&jr.output_ring[jr.tail].desc;
+ addr = (uint32_t *)&jr->output_ring[jr->tail].desc;
op_desc = sec_in32(addr);
#endif /* ifdef CONFIG_PHYS_64BIT */
- uint32_t status = sec_in32(&jr.output_ring[jr.tail].status);
+ uint32_t status = sec_in32(&jr->output_ring[jr->tail].status);
- for (i = 0; CIRC_CNT(head, tail + i, jr.size) >= 1; i++) {
- idx = (tail + i) & (jr.size - 1);
- if (op_desc == jr.info[idx].desc_phys_addr) {
+ for (i = 0; CIRC_CNT(head, tail + i, jr->size) >= 1; i++) {
+ idx = (tail + i) & (jr->size - 1);
+ if (op_desc == jr->info[idx].desc_phys_addr) {
found = 1;
break;
}
if (!found)
return -1;
- jr.info[idx].op_done = 1;
- callback = (void *)jr.info[idx].callback;
- arg = jr.info[idx].arg;
+ jr->info[idx].op_done = 1;
+ callback = (void *)jr->info[idx].callback;
+ arg = jr->info[idx].arg;
/* When the job on tail idx gets done, increment
* tail till the point where job completed out of oredr has
*/
if (idx == tail)
do {
- tail = (tail + 1) & (jr.size - 1);
- } while (jr.info[tail].op_done);
+ tail = (tail + 1) & (jr->size - 1);
+ } while (jr->info[tail].op_done);
- jr.tail = tail;
- jr.read_idx = (jr.read_idx + 1) & (jr.size - 1);
+ jr->tail = tail;
+ jr->read_idx = (jr->read_idx + 1) & (jr->size - 1);
sec_out32(®s->orjr, 1);
- jr.info[idx].op_done = 0;
+ jr->info[idx].op_done = 0;
callback(status, arg);
}
x->done = 1;
}
-int run_descriptor_jr(uint32_t *desc)
+static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
{
unsigned long long timeval = get_ticks();
unsigned long long timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
memset(&op, 0, sizeof(op));
- ret = jr_enqueue(desc, desc_done, &op);
+ ret = jr_enqueue(desc, desc_done, &op, sec_idx);
if (ret) {
debug("Error in SEC enq\n");
ret = JQ_ENQ_ERR;
timeval = get_ticks();
timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
while (op.done != 1) {
- ret = jr_dequeue();
+ ret = jr_dequeue(sec_idx);
if (ret) {
debug("Error in SEC deq\n");
ret = JQ_DEQ_ERR;
return ret;
}
-int jr_reset(void)
+int run_descriptor_jr(uint32_t *desc)
+{
+ return run_descriptor_jr_idx(desc, 0);
+}
+
+static inline int jr_reset_sec(uint8_t sec_idx)
{
- if (jr_hw_reset() < 0)
+ if (jr_hw_reset(sec_idx) < 0)
return -1;
/* Clean up the jobring structure maintained by software */
- jr_sw_cleanup();
+ jr_sw_cleanup(sec_idx);
return 0;
}
-int sec_reset(void)
+int jr_reset(void)
{
- ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+ return jr_reset_sec(0);
+}
+
+static inline int sec_reset_idx(uint8_t sec_idx)
+{
+ ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
uint32_t mcfgr = sec_in32(&sec->mcfgr);
uint32_t timeout = 100000;
return 0;
}
-static int instantiate_rng(void)
+static int instantiate_rng(uint8_t sec_idx)
{
struct result op;
u32 *desc;
u32 rdsta_val;
int ret = 0;
- ccsr_sec_t __iomem *sec =
- (ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+ ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
struct rng4tst __iomem *rng =
(struct rng4tst __iomem *)&sec->rng;
flush_dcache_range((unsigned long)desc,
(unsigned long)desc + size);
- ret = run_descriptor_jr(desc);
+ ret = run_descriptor_jr_idx(desc, sec_idx);
if (ret)
printf("RNG: Instantiation failed with error %x\n", ret);
return ret;
}
-static u8 get_rng_vid(void)
+int sec_reset(void)
+{
+ return sec_reset_idx(0);
+}
+
+static u8 get_rng_vid(uint8_t sec_idx)
{
- ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+ ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
u32 cha_vid = sec_in32(&sec->chavid_ls);
return (cha_vid & SEC_CHAVID_RNG_LS_MASK) >> SEC_CHAVID_LS_RNG_SHIFT;
* By default, the TRNG runs for 200 clocks per sample;
* 1200 clocks per sample generates better entropy.
*/
-static void kick_trng(int ent_delay)
+static void kick_trng(int ent_delay, uint8_t sec_idx)
{
- ccsr_sec_t __iomem *sec =
- (ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+ ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
struct rng4tst __iomem *rng =
(struct rng4tst __iomem *)&sec->rng;
u32 val;
sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
}
-static int rng_init(void)
+static int rng_init(uint8_t sec_idx)
{
int ret, ent_delay = RTSDCTL_ENT_DLY_MIN;
- ccsr_sec_t __iomem *sec =
- (ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+ ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
struct rng4tst __iomem *rng =
(struct rng4tst __iomem *)&sec->rng;
* Also, if a handle was instantiated, do not change
* the TRNG parameters.
*/
- kick_trng(ent_delay);
+ kick_trng(ent_delay, sec_idx);
ent_delay += 400;
/*
* if instantiate_rng(...) fails, the loop will rerun
* interval, leading to a sucessful initialization of
* the RNG.
*/
- ret = instantiate_rng();
+ ret = instantiate_rng(sec_idx);
} while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
if (ret) {
printf("RNG: Failed to instantiate RNG\n");
return ret;
}
-int sec_init(void)
+int sec_init_idx(uint8_t sec_idx)
{
- ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+ ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
uint32_t mcr = sec_in32(&sec->mcfgr);
int ret = 0;
uint32_t liodn_s;
#endif
+ if (!(sec_idx < CONFIG_SYS_FSL_MAX_NUM_OF_SEC)) {
+ printf("SEC initialization failed\n");
+ return -1;
+ }
+
/*
* Modifying CAAM Read/Write Attributes
* For LS2080A
liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
#endif
- ret = jr_init();
+ ret = jr_init(sec_idx);
if (ret < 0) {
printf("SEC initialization failed\n");
return -1;
pamu_enable();
#endif
- if (get_rng_vid() >= 4) {
- if (rng_init() < 0) {
- printf("RNG instantiation failed\n");
+ if (get_rng_vid(sec_idx) >= 4) {
+ if (rng_init(sec_idx) < 0) {
+ printf("SEC%u: RNG instantiation failed\n", sec_idx);
return -1;
}
- printf("SEC: RNG instantiated\n");
+ printf("SEC%u: RNG instantiated\n", sec_idx);
}
return ret;
}
+
+int sec_init(void)
+{
+ return sec_init_idx(0);
+}
/* This ring can be on the stack */
struct jr_info info[JR_SIZE];
struct op_ring *output_ring;
+ /* Offset in CCSR to the SEC engine to which this JR belongs */
+ uint32_t sec_offset;
+
};
struct result {
u32 vref_seq2[3] = {0xc0, 0xf0, 0x70}; /* for range 2 */
u32 *vref_seq = vref_seq1;
#endif
-#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) | \
+ defined(CONFIG_SYS_FSL_ERRATUM_A010165)
ulong ddr_freq;
u32 tmp;
#endif
/* Disable DRAM VRef training */
ddr_out32(&ddr->ddr_cdr2,
regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
- /* Disable deskew */
- ddr_out32(&ddr->debug[28], 0x400);
+ /* disable transmit bit deskew */
+ temp32 = ddr_in32(&ddr->debug[28]);
+ temp32 |= DDR_TX_BD_DIS;
+ ddr_out32(&ddr->debug[28], temp32);
/* Disable D_INIT */
ddr_out32(&ddr->sdram_cfg_2,
regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
}
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009801
+ temp32 = ddr_in32(&ddr->debug[25]);
+ temp32 &= ~DDR_CAS_TO_PRE_SUB_MASK;
+ temp32 |= 9 << DDR_CAS_TO_PRE_SUB_SHIFT;
+ ddr_out32(&ddr->debug[25], temp32);
+#endif
+
#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
tmp = ddr_in32(&ddr->debug[28]);
ddr_out32(&ddr->debug[28], tmp | 0x0060007b);
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010165
+ ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
+ if ((ddr_freq > 1900) && (ddr_freq < 2300)) {
+ tmp = ddr_in32(&ddr->debug[28]);
+ ddr_out32(&ddr->debug[28], tmp | 0x000a0000);
+ }
+#endif
/*
* For RDIMMs, JEDEC spec requires clocks to be stable before reset is
* deasserted. Clocks start when any chip select is enabled and clock
debug("MR6 = 0x%08x\n", temp32);
}
ddr_out32(&ddr->sdram_md_cntl, 0);
- ddr_out32(&ddr->debug[28], 0); /* Enable deskew */
+ temp32 = ddr_in32(&ddr->debug[28]);
+ temp32 &= ~DDR_TX_BD_DIS; /* Enable deskew */
+ ddr_out32(&ddr->debug[28], temp32);
ddr_out32(&ddr->debug[1], 0x400); /* restart deskew */
/* wait for idle */
timeout = 40;
const void *buf);
#endif
+#ifdef CONFIG_SPI_FLASH_SPANSION
+/* Used for Spansion S25FS-S family flash only. */
+#define CMD_SPANSION_RDAR 0x65 /* Read any device register */
+#define CMD_SPANSION_WRAR 0x71 /* Write any device register */
+#endif
/**
* struct spi_flash_params - SPI/QSPI flash device params structure
*
}
#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
+#ifdef CONFIG_SPI_FLASH_SPANSION
+static int spansion_s25fss_disable_4KB_erase(struct spi_slave *spi)
+{
+ u8 cmd[4];
+ u32 offset = 0x800004; /* CR3V register offset */
+ u8 cr3v;
+ int ret;
+
+ cmd[0] = CMD_SPANSION_RDAR;
+ cmd[1] = offset >> 16;
+ cmd[2] = offset >> 8;
+ cmd[3] = offset >> 0;
+
+ ret = spi_flash_cmd_read(spi, cmd, 4, &cr3v, 1);
+ if (ret)
+ return -EIO;
+ /* CR3V bit3: 4-KB Erase */
+ if (cr3v & 0x8)
+ return 0;
+
+ cmd[0] = CMD_SPANSION_WRAR;
+ cr3v |= 0x8;
+ ret = spi_flash_cmd_write(spi, cmd, 4, &cr3v, 1);
+ if (ret)
+ return -EIO;
+
+ cmd[0] = CMD_SPANSION_RDAR;
+ ret = spi_flash_cmd_read(spi, cmd, 4, &cr3v, 1);
+ if (ret)
+ return -EIO;
+ if (!(cr3v & 0x8))
+ return -EFAULT;
+
+ return 0;
+}
+#endif
+
int spi_flash_scan(struct spi_flash *flash)
{
struct spi_slave *spi = flash->spi;
return -EPROTONOSUPPORT;
}
+#ifdef CONFIG_SPI_FLASH_SPANSION
+ /*
+ * The S25FS-S family physical sectors may be configured as a
+ * hybrid combination of eight 4-kB parameter sectors
+ * at the top or bottom of the address space with all
+ * but one of the remaining sectors being uniform size.
+ * The Parameter Sector Erase commands (20h or 21h) must
+ * be used to erase the 4-kB parameter sectors individually.
+ * The Sector (uniform sector) Erase commands (D8h or DCh)
+ * must be used to erase any of the remaining
+ * sectors, including the portion of highest or lowest address
+ * sector that is not overlaid by the parameter sectors.
+ * The uniform sector erase command has no effect on parameter sectors.
+ */
+ if (jedec == 0x0219 && (ext_jedec & 0xff00) == 0x4d00) {
+ int ret;
+ u8 id[6];
+
+ /* Read the ID codes again, 6 bytes */
+ ret = spi_flash_cmd(flash->spi, CMD_READ_ID, id, sizeof(id));
+ if (ret)
+ return -EIO;
+
+ ret = memcmp(id, idcode, 5);
+ if (ret)
+ return -EIO;
+
+ /* 0x81: S25FS-S family 0x80: S25FL-S family */
+ if (id[5] == 0x81) {
+ ret = spansion_s25fss_disable_4KB_erase(spi);
+ if (ret)
+ return ret;
+ }
+ }
+#endif
/* Flash powers up read-only, so clear BP# bits */
if (idcode[0] == SPI_FLASH_CFI_MFR_ATMEL ||
idcode[0] == SPI_FLASH_CFI_MFR_MACRONIX ||
#define SEQID_RDEAR 11
#define SEQID_WREAR 12
#endif
+#define SEQID_WRAR 13
+#define SEQID_RDAR 14
/* QSPI CMD */
#define QSPI_CMD_PP 0x02 /* Page program (up to 256 bytes) */
#define QSPI_CMD_BRRD 0x16 /* Bank register read */
#define QSPI_CMD_BRWR 0x17 /* Bank register write */
+/* Used for Spansion S25FS-S family flash only. */
+#define QSPI_CMD_RDAR 0x65 /* Read any device register */
+#define QSPI_CMD_WRAR 0x71 /* Write any device register */
+
/* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
#define QSPI_CMD_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */
#define QSPI_CMD_PP_4B 0x12 /* Page program (up to 256 bytes) */
struct fsl_qspi_platdata {
u32 flags;
u32 speed_hz;
- u32 reg_base;
- u32 amba_base;
- u32 amba_total_size;
+ fdt_addr_t reg_base;
+ fdt_addr_t amba_base;
+ fdt_size_t amba_total_size;
u32 flash_num;
u32 num_chipselect;
};
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
#endif
+
+ /*
+ * Read any device register.
+ * Used for Spansion S25FS-S family flash only.
+ */
+ lut_base = SEQID_RDAR * 4;
+ qspi_write32(priv->flags, ®s->lut[lut_base],
+ OPRND0(QSPI_CMD_RDAR) | PAD0(LUT_PAD1) |
+ INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
+ PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
+ qspi_write32(priv->flags, ®s->lut[lut_base + 1],
+ OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
+ OPRND1(1) | PAD1(LUT_PAD1) |
+ INSTR1(LUT_READ));
+
+ /*
+ * Write any device register.
+ * Used for Spansion S25FS-S family flash only.
+ */
+ lut_base = SEQID_WRAR * 4;
+ qspi_write32(priv->flags, ®s->lut[lut_base],
+ OPRND0(QSPI_CMD_WRAR) | PAD0(LUT_PAD1) |
+ INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
+ PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
+ qspi_write32(priv->flags, ®s->lut[lut_base + 1],
+ OPRND0(1) | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
+
/* Lock the LUT */
qspi_write32(priv->flags, ®s->lutkey, LUT_KEY_VALUE);
qspi_write32(priv->flags, ®s->lckcr, QSPI_LCKCR_LOCK);
qspi_write32(priv->flags, ®s->mcr, mcr_reg);
}
-#ifndef CONFIG_SYS_FSL_QSPI_AHB
/* If not use AHB read, read data from ip interface */
static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
{
u32 mcr_reg, data;
int i, size;
u32 to_or_from;
+ u32 seqid;
+
+ if (priv->cur_seqid == QSPI_CMD_RDAR)
+ seqid = SEQID_RDAR;
+ else
+ seqid = SEQID_FAST_READ;
mcr_reg = qspi_read32(priv->flags, ®s->mcr);
qspi_write32(priv->flags, ®s->mcr,
RX_BUFFER_SIZE : len;
qspi_write32(priv->flags, ®s->ipcr,
- (SEQID_FAST_READ << QSPI_IPCR_SEQID_SHIFT) |
+ (seqid << QSPI_IPCR_SEQID_SHIFT) |
size);
while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK)
;
while ((RX_BUFFER_SIZE >= size) && (size > 0)) {
data = qspi_read32(priv->flags, ®s->rbdr[i]);
data = qspi_endian_xchg(data);
- memcpy(rxbuf, &data, 4);
+ if (size < 4)
+ memcpy(rxbuf, &data, size);
+ else
+ memcpy(rxbuf, &data, 4);
rxbuf++;
size -= 4;
i++;
qspi_write32(priv->flags, ®s->mcr, mcr_reg);
}
-#endif
static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len)
{
/* Default is page programming */
seqid = SEQID_PP;
+ if (priv->cur_seqid == QSPI_CMD_WRAR)
+ seqid = SEQID_WRAR;
#ifdef CONFIG_SPI_FLASH_BAR
if (priv->cur_seqid == QSPI_CMD_BRWR)
seqid = SEQID_BRWR;
return 0;
}
- if (priv->cur_seqid == QSPI_CMD_FAST_READ) {
+ if (priv->cur_seqid == QSPI_CMD_FAST_READ ||
+ priv->cur_seqid == QSPI_CMD_RDAR) {
priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
} else if ((priv->cur_seqid == QSPI_CMD_SE) ||
(priv->cur_seqid == QSPI_CMD_BE_4K)) {
priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
qspi_op_erase(priv);
- } else if (priv->cur_seqid == QSPI_CMD_PP) {
+ } else if (priv->cur_seqid == QSPI_CMD_PP ||
+ priv->cur_seqid == QSPI_CMD_WRAR) {
wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
} else if ((priv->cur_seqid == QSPI_CMD_BRWR) ||
(priv->cur_seqid == QSPI_CMD_WREAR)) {
#else
qspi_op_read(priv, din, bytes);
#endif
+ } else if (priv->cur_seqid == QSPI_CMD_RDAR) {
+ qspi_op_read(priv, din, bytes);
} else if (priv->cur_seqid == QSPI_CMD_RDID)
qspi_op_rdid(priv, din, bytes);
else if (priv->cur_seqid == QSPI_CMD_RDSR)
static int fsl_qspi_probe(struct udevice *bus)
{
- u32 total_size;
+ u32 amba_size_per_chip;
struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
struct fsl_qspi_priv *priv = dev_get_priv(bus);
struct dm_spi_bus *dm_spi_bus;
+ int i;
dm_spi_bus = bus->uclass_priv;
priv->flags = plat->flags;
priv->speed_hz = plat->speed_hz;
- priv->amba_base[0] = plat->amba_base;
- priv->amba_total_size = plat->amba_total_size;
+ /*
+ * QSPI SFADR width is 32bits, the max dest addr is 4GB-1.
+ * AMBA memory zone should be located on the 0~4GB space
+ * even on a 64bits cpu.
+ */
+ priv->amba_base[0] = (u32)plat->amba_base;
+ priv->amba_total_size = (u32)plat->amba_total_size;
priv->flash_num = plat->flash_num;
priv->num_chipselect = plat->num_chipselect;
qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
- total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM;
+ /*
+ * Assign AMBA memory zone for every chipselect
+ * QuadSPI has two channels, every channel has two chipselects.
+ * If the property 'num-cs' in dts is 2, the AMBA memory will be divided
+ * into two parts and assign to every channel. This indicate that every
+ * channel only has one valid chipselect.
+ * If the property 'num-cs' in dts is 4, the AMBA memory will be divided
+ * into four parts and assign to every chipselect.
+ * Every channel will has two valid chipselects.
+ */
+ amba_size_per_chip = priv->amba_total_size >>
+ (priv->num_chipselect >> 1);
+ for (i = 1 ; i < priv->num_chipselect ; i++)
+ priv->amba_base[i] =
+ amba_size_per_chip + priv->amba_base[i - 1];
+
/*
* Any read access to non-implemented addresses will provide
* undefined results.
* setting the size of these devices to 0. This would ensure
* that the complete memory map is assigned to only one flash device.
*/
- qspi_write32(priv->flags, &priv->regs->sfa1ad,
- FSL_QSPI_FLASH_SIZE | priv->amba_base[0]);
- qspi_write32(priv->flags, &priv->regs->sfa2ad,
- FSL_QSPI_FLASH_SIZE | priv->amba_base[0]);
- qspi_write32(priv->flags, &priv->regs->sfb1ad,
- total_size | priv->amba_base[0]);
- qspi_write32(priv->flags, &priv->regs->sfb2ad,
- total_size | priv->amba_base[0]);
+ qspi_write32(priv->flags, &priv->regs->sfa1ad, priv->amba_base[1]);
+ switch (priv->num_chipselect) {
+ case 2:
+ qspi_write32(priv->flags, &priv->regs->sfa2ad,
+ priv->amba_base[1]);
+ qspi_write32(priv->flags, &priv->regs->sfb1ad,
+ priv->amba_base[1] + amba_size_per_chip);
+ qspi_write32(priv->flags, &priv->regs->sfb2ad,
+ priv->amba_base[1] + amba_size_per_chip);
+ break;
+ case 4:
+ qspi_write32(priv->flags, &priv->regs->sfa2ad,
+ priv->amba_base[2]);
+ qspi_write32(priv->flags, &priv->regs->sfb1ad,
+ priv->amba_base[3]);
+ qspi_write32(priv->flags, &priv->regs->sfb2ad,
+ priv->amba_base[3] + amba_size_per_chip);
+ break;
+ default:
+ debug("Error: Unsupported chipselect number %u!\n",
+ priv->num_chipselect);
+ qspi_module_disable(priv, 1);
+ return -EINVAL;
+ }
qspi_set_lut(priv);
static int fsl_qspi_ofdata_to_platdata(struct udevice *bus)
{
- struct reg_data {
- u32 addr;
- u32 size;
- } regs_data[2];
+ struct fdt_resource res_regs, res_mem;
struct fsl_qspi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
int node = bus->of_offset;
if (fdtdec_get_bool(blob, node, "big-endian"))
plat->flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
- ret = fdtdec_get_int_array(blob, node, "reg", (u32 *)regs_data,
- sizeof(regs_data)/sizeof(u32));
+ ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
+ "QuadSPI", &res_regs);
+ if (ret) {
+ debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
+ return -ENOMEM;
+ }
+ ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
+ "QuadSPI-memory", &res_mem);
if (ret) {
- debug("Error: can't get base addresses (ret = %d)!\n", ret);
+ debug("Error: can't get AMBA base addresses(ret = %d)!\n", ret);
return -ENOMEM;
}
plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs",
FSL_QSPI_MAX_CHIPSELECT_NUM);
- plat->reg_base = regs_data[0].addr;
- plat->amba_base = regs_data[1].addr;
- plat->amba_total_size = regs_data[1].size;
+ plat->reg_base = res_regs.start;
+ plat->amba_base = res_mem.start;
+ plat->amba_total_size = res_mem.end - res_mem.start + 1;
plat->flash_num = flash_num;
- debug("%s: regs=<0x%x> <0x%x, 0x%x>, max-frequency=%d, endianess=%s\n",
+ debug("%s: regs=<0x%llx> <0x%llx, 0x%llx>, max-frequency=%d, endianess=%s\n",
__func__,
- plat->reg_base,
- plat->amba_base,
- plat->amba_total_size,
+ (u64)plat->reg_base,
+ (u64)plat->amba_base,
+ (u64)plat->amba_total_size,
plat->speed_hz,
plat->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le"
);
bus = dev->parent;
priv = dev_get_priv(bus);
- priv->cur_amba_base =
- priv->amba_base[0] + FSL_QSPI_FLASH_SIZE * slave_plat->cs;
+ priv->cur_amba_base = priv->amba_base[slave_plat->cs];
qspi_module_disable(priv, 0);
#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
"earlycon=uart8250,mmio,0x21c0500"
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \
+ "e0000 f00000 && bootm $kernel_load"
+#else
#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
"$kernel_size && bootm $kernel_load"
+#endif
#define CONFIG_BOOTDELAY 10
/* Monitor Command Prompt */
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_REALTEK
#define CONFIG_PHY_AQUANTIA
+#define AQR105_IRQ_MASK 0x40000000
#define RGMII_PHY1_ADDR 0x1
#define RGMII_PHY2_ADDR 0x2
#define CONFIG_USB_STORAGE
#endif
+/* SATA */
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_CMD_SCSI
+#ifndef CONFIG_CMD_FAT
+#define CONFIG_CMD_FAT
+#endif
+#ifndef CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT2
+#endif
+#define CONFIG_DOS_PARTITION
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
+#define CONFIG_SYS_SCSI_MAX_LUN 2
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+#define SCSI_VEND_ID 0x1b4b
+#define SCSI_DEV_ID 0x9170
+#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
+#define CONFIG_PCI
+
#include <asm/fsl_secure_boot.h>
#endif /* __LS1043ARDB_H__ */
/* We need architecture specific misc initializations */
#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
+
/* Link Definitions */
#ifdef CONFIG_SPL
#define CONFIG_SYS_TEXT_BASE 0x80400000
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
#endif /* __LS2_COMMON_H */
#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
#define CONFIG_MII /* MII PHY management */
-#define CONFIG_ETHPRIME "DPNI1"
+#define CONFIG_ETHPRIME "DPMAC1@xgmii"
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
#endif
#define AQR405_IRQ_MASK 0x36
#define CONFIG_MII
-#define CONFIG_ETHPRIME "DPNI1"
+#define CONFIG_ETHPRIME "DPMAC1@xgmii"
#define CONFIG_PHY_GIGE
#define CONFIG_PHY_AQUANTIA
#endif
#define WR_DATA_DELAY_SHIFT 10
#endif
+/* DDR_EOR register */
+#define DDR_EOR_RD_REOD_DIS 0x07000000
+#define DDR_EOR_WD_REOD_DIS 0x00100000
+
/* DDR_MD_CNTL */
#define MD_CNTL_MD_EN 0x80000000
#define MD_CNTL_CS_SEL_CS0 0x00000000
#define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */
#define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */
+/* DEBUG_26 register */
+#define DDR_CAS_TO_PRE_SUB_MASK 0x0000f000 /* CAS to preamble subtract value */
+#define DDR_CAS_TO_PRE_SUB_SHIFT 12
+
+/* DEBUG_29 register */
+#define DDR_TX_BD_DIS (1 << 10) /* Transmit Bit Deskew Disable */
+
#if (defined(CONFIG_SYS_FSL_DDR_VER) && \
(CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
#endif
-int sec_init(void);
-
/* blob_dek:
* Encapsulates the src in a secure blob and stores it dst
* @src: reference to the plaintext
*/
int blob_dek(const u8 *src, u8 *dst, u8 len);
+#if defined(CONFIG_PPC_C29X)
+int sec_init_idx(uint8_t);
+#endif
+int sec_init(void);
#endif
#endif /* __FSL_SEC_H */
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