]> git.sur5r.net Git - u-boot/commitdiff
board: ti: AM43XX: Add ddr voltage rail configuration
authorKeerthy <j-keerthy@ti.com>
Fri, 2 Jun 2017 09:30:31 +0000 (15:00 +0530)
committerJaehoon Chung <jh80.chung@samsung.com>
Fri, 9 Jun 2017 11:25:16 +0000 (20:25 +0900)
Add ddr voltage rail (dcdc3) configuration. Set the dcdc3
DDR supply to 1.35V.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
board/ti/am43xx/board.c
include/power/tps65218.h

index f44103d4d6fe250083aa833bb6d5e17449fb7022..a25902813eda311e7327e95495a2ca208fc7cad5 100644 (file)
@@ -421,6 +421,13 @@ void scale_vcores_generic(u32 m)
                printf("%s failure\n", __func__);
                return;
        }
+
+       /* Set DCDC3 (DDR) voltage */
+       if (tps65218_voltage_update(TPS65218_DCDC3,
+           TPS65218_DCDC3_VOLT_SEL_1350MV)) {
+               printf("%s failure\n", __func__);
+               return;
+       }
 }
 
 void scale_vcores_idk(u32 m)
index e3538e21f04c361a9f79409e8c88c02c2117b615..43b9c9aa52d8fc05f65b659b20d1448bd120a27d 100644 (file)
@@ -63,6 +63,7 @@ enum {
 #define TPS65218_DCDC_VOLT_SEL_1200MV          0x23
 #define TPS65218_DCDC_VOLT_SEL_1260MV          0x29
 #define TPS65218_DCDC_VOLT_SEL_1330MV          0x30
+#define TPS65218_DCDC3_VOLT_SEL_1350MV         0x12
 
 #define TPS65218_CC_STAT       (BIT(0) | BIT(1))
 #define TPS65218_STATE         (BIT(2) | BIT(3))