#include <netdev.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
+ #include <usb.h>
+ #include <usb/ehci-fsl.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
++#ifdef CONFIG_USB_EHCI_MX6
++#define USB_OTHERREGS_OFFSET 0x800
++#define UCTRL_PWR_POL (1 << 9)
++
++static iomux_v3_cfg_t const usb_otg_pads[] = {
++ /* OGT1 */
++ MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
++ MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
++ /* OTG2 */
++ MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
++};
++
++static void setup_usb(void)
++{
++ imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
++ ARRAY_SIZE(usb_otg_pads));
++}
++
++int board_usb_phy_mode(int port)
++{
++ if (port == 1)
++ return USB_INIT_HOST;
++ else
++ return usb_phy_mode(port);
++}
++
++int board_ehci_hcd_init(int port)
++{
++ u32 *usbnc_usb_ctrl;
++
++ if (port > 1)
++ return -EINVAL;
++
++ usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
++ port * 4);
++
++ /* Set Power polarity */
++ setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
++
++ return 0;
++}
++#endif
++
int board_phy_config(struct phy_device *phydev)
{
/*
return 0;
}
-#endif
-
int board_init(void)
{
/* Address of boot parameters */