]> git.sur5r.net Git - u-boot/commitdiff
mpc83xx: Add support for MPC83xx PCI-E controllers
authorAnton Vorontsov <avorontsov@ru.mvista.com>
Thu, 8 Jan 2009 01:26:12 +0000 (04:26 +0300)
committerKim Phillips <kim.phillips@freescale.com>
Thu, 22 Jan 2009 00:43:49 +0000 (18:43 -0600)
This patch adds support for MPC83xx PCI-E controllers in Root Complex
mode.

The patch is based on Tony Li and Dave Liu work[1].

Though unlike the original patch, by default we don't register PCI-E
buses for use in U-Boot, we only configure the controllers for future
use in other OSes (Linux). This is done because we don't have enough
of spare BATs to map all the PCI-E regions.

To actually use PCI-E in U-Boot, users should explicitly define
CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES symbol in the board file. And
only then U-Boot will able to access PCI-E, but at the cost of disabled
address translation.

[1] http://lists.denx.de/pipermail/u-boot/2008-January/027630.html

Signed-off-by: Tony Li <tony.li@freescale.com>
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Acked-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
cpu/mpc83xx/Makefile
cpu/mpc83xx/pcie.c [new file with mode: 0644]
cpu/mpc83xx/speed.c
include/asm-ppc/global_data.h
include/asm-ppc/immap_83xx.h
include/mpc83xx.h
include/pci.h

index fcb6a524659f94c9031fd5e2e76dccb69a015b7d..dd35e6bf88b1ae9580a0499caff6148db44b17a1 100644 (file)
@@ -39,6 +39,7 @@ COBJS-y += ecc.o
 COBJS-$(CONFIG_QE) += qe_io.o
 COBJS-$(CONFIG_FSL_SERDES) += serdes.o
 COBJS-$(CONFIG_83XX_GENERIC_PCI) += pci.o
+COBJS-$(CONFIG_83XX_GENERIC_PCIE) += pcie.o
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
 
 COBJS  := $(COBJS-y)
diff --git a/cpu/mpc83xx/pcie.c b/cpu/mpc83xx/pcie.c
new file mode 100644 (file)
index 0000000..02150ba
--- /dev/null
@@ -0,0 +1,314 @@
+/*
+ * Copyright (C) 2007-2009  Freescale Semiconductor, Inc.
+ * Copyright (C) 2008-2009  MontaVista Software, Inc.
+ *
+ * Authors: Tony Li <tony.li@freescale.com>
+ *          Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <mpc83xx.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PCIE_MAX_BUSES 2
+
+#ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
+
+static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev)
+{
+       int bus = PCI_BUS(dev) - hose->first_busno;
+       immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+       pex83xx_t *pex = &immr->pciexp[bus];
+       struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0];
+       u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev);
+       u32 dev_base = bus << 24 | devfn << 16;
+
+       if (hose->indirect_type == INDIRECT_TYPE_NO_PCIE_LINK)
+               return -1;
+       /*
+        * Workaround for the HW bug: for Type 0 configure transactions the
+        * PCI-E controller does not check the device number bits and just
+        * assumes that the device number bits are 0.
+        */
+       if (devfn & 0xf8)
+               return -1;
+
+       out_le32(&out_win->tarl, dev_base);
+       return 0;
+}
+
+#define cfg_read(val, addr, type, op) \
+       do { *val = op((type)(addr)); } while (0)
+#define cfg_write(val, addr, type, op) \
+       do { op((type *)(addr), (val)); } while (0)
+
+#define PCIE_OP(rw, size, type, op)                                    \
+static int pcie_##rw##_config_##size(struct pci_controller *hose,      \
+                                    pci_dev_t dev, int offset,         \
+                                    type val)                          \
+{                                                                      \
+       int ret;                                                        \
+                                                                       \
+       ret = mpc83xx_pcie_remap_cfg(hose, dev);                        \
+       if (ret)                                                        \
+               return ret;                                             \
+       cfg_##rw(val, (void *)hose->cfg_addr + offset, type, op);       \
+       return 0;                                                       \
+}
+
+PCIE_OP(read, byte, u8 *, in_8)
+PCIE_OP(read, word, u16 *, in_le16)
+PCIE_OP(read, dword, u32 *, in_le32)
+PCIE_OP(write, byte, u8, out_8)
+PCIE_OP(write, word, u16, out_le16)
+PCIE_OP(write, dword, u32, out_le32)
+
+static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
+                                      u8 link)
+{
+       extern void disable_addr_trans(void); /* start.S */
+       static struct pci_controller pcie_hose[PCIE_MAX_BUSES];
+       static int max_bus;
+       struct pci_controller *hose = &pcie_hose[bus];
+       int i;
+
+       /*
+        * There are no spare BATs to remap all PCI-E windows for U-Boot, so
+        * disable translations. In general, this is not great solution, and
+        * that's why we don't register PCI-E hoses by default.
+        */
+       disable_addr_trans();
+
+       for (i = 0; i < 2; i++, reg++) {
+               if (reg->size == 0)
+                       break;
+
+               hose->regions[i] = *reg;
+               hose->region_count++;
+       }
+
+       i = hose->region_count++;
+       hose->regions[i].bus_start = 0;
+       hose->regions[i].phys_start = 0;
+       hose->regions[i].size = gd->ram_size;
+       hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY;
+
+       i = hose->region_count++;
+       hose->regions[i].bus_start = CONFIG_SYS_IMMR;
+       hose->regions[i].phys_start = CONFIG_SYS_IMMR;
+       hose->regions[i].size = 0x100000;
+       hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY;
+
+       hose->first_busno = max_bus;
+       hose->last_busno = 0xff;
+
+       if (bus == 0)
+               hose->cfg_addr = (unsigned int *)CONFIG_SYS_PCIE1_CFG_BASE;
+       else
+               hose->cfg_addr = (unsigned int *)CONFIG_SYS_PCIE2_CFG_BASE;
+
+       pci_set_ops(hose,
+                       pcie_read_config_byte,
+                       pcie_read_config_word,
+                       pcie_read_config_dword,
+                       pcie_write_config_byte,
+                       pcie_write_config_word,
+                       pcie_write_config_dword);
+
+       if (!link)
+               hose->indirect_type = INDIRECT_TYPE_NO_PCIE_LINK;
+
+       pci_register_hose(hose);
+
+#ifdef CONFIG_PCI_SCAN_SHOW
+       printf("PCI:   Bus Dev VenId DevId Class Int\n");
+#endif
+       /*
+        * Hose scan.
+        */
+       hose->last_busno = pci_hose_scan(hose);
+       max_bus = hose->last_busno + 1;
+}
+
+#else
+
+static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
+                                      u8 link) {}
+
+#endif /* CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES */
+
+static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
+{
+       immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+       pex83xx_t *pex = &immr->pciexp[bus];
+       struct pex_outbound_window *out_win;
+       struct pex_inbound_window *in_win;
+       void *hose_cfg_base;
+       unsigned int ram_sz;
+       unsigned int barl;
+       unsigned int tar;
+       u16 reg16;
+       int i;
+
+       /* Enable pex csb bridge inbound & outbound transactions */
+       out_le32(&pex->bridge.pex_csb_ctrl,
+               in_le32(&pex->bridge.pex_csb_ctrl) | PEX_CSB_CTRL_OBPIOE |
+               PEX_CSB_CTRL_IBPIOE);
+
+       /* Enable bridge outbound */
+       out_le32(&pex->bridge.pex_csb_obctrl, PEX_CSB_OBCTRL_PIOE |
+               PEX_CSB_OBCTRL_MEMWE | PEX_CSB_OBCTRL_IOWE |
+               PEX_CSB_OBCTRL_CFGWE);
+
+       out_win = &pex->bridge.pex_outbound_win[0];
+       if (bus) {
+               out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG |
+                       CONFIG_SYS_PCIE2_CFG_SIZE);
+               out_le32(&out_win->bar, CONFIG_SYS_PCIE2_CFG_BASE);
+       } else {
+               out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG |
+                       CONFIG_SYS_PCIE1_CFG_SIZE);
+               out_le32(&out_win->bar, CONFIG_SYS_PCIE1_CFG_BASE);
+       }
+       out_le32(&out_win->tarl, 0);
+       out_le32(&out_win->tarh, 0);
+
+       for (i = 0; i < 2; i++, reg++) {
+               u32 ar;
+
+               if (reg->size == 0)
+                       break;
+
+               out_win = &pex->bridge.pex_outbound_win[i + 1];
+               out_le32(&out_win->bar, reg->phys_start);
+               out_le32(&out_win->tarl, reg->bus_start);
+               out_le32(&out_win->tarh, 0);
+               ar = PEX_OWAR_EN | (reg->size & PEX_OWAR_SIZE);
+               if (reg->flags & PCI_REGION_IO)
+                       ar |= PEX_OWAR_TYPE_IO;
+               else
+                       ar |= PEX_OWAR_TYPE_MEM;
+               out_le32(&out_win->ar, ar);
+       }
+
+       out_le32(&pex->bridge.pex_csb_ibctrl, PEX_CSB_IBCTRL_PIOE);
+
+       ram_sz = gd->ram_size;
+       barl = 0;
+       tar = 0;
+       i = 0;
+       while (ram_sz > 0) {
+               in_win = &pex->bridge.pex_inbound_win[i];
+               out_le32(&in_win->barl, barl);
+               out_le32(&in_win->barh, 0x0);
+               out_le32(&in_win->tar, tar);
+               if (ram_sz >= 0x10000000) {
+                       /* The maxium windows size is 256M */
+                       out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV |
+                               PEX_IWAR_TYPE_PF | 0x0FFFF000);
+                       barl += 0x10000000;
+                       tar += 0x10000000;
+                       ram_sz -= 0x10000000;
+               } else {
+                       /* The UM  is not clear here.
+                        * So, round up to even Mb boundary */
+
+                       ram_sz = ram_sz >> (20 +
+                                       ((ram_sz & 0xFFFFF) ? 1 : 0));
+                       if (!(ram_sz % 2))
+                               ram_sz -= 1;
+                       out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV |
+                               PEX_IWAR_TYPE_PF | (ram_sz << 20) | 0xFF000);
+                       ram_sz = 0;
+               }
+               i++;
+       }
+
+       in_win = &pex->bridge.pex_inbound_win[i];
+       out_le32(&in_win->barl, CONFIG_SYS_IMMR);
+       out_le32(&in_win->barh, 0);
+       out_le32(&in_win->tar, CONFIG_SYS_IMMR);
+       out_le32(&in_win->ar, PEX_IWAR_EN |
+               PEX_IWAR_TYPE_NO_PF | PEX_IWAR_SIZE_1M);
+
+       /* Enable the host virtual INTX interrupts */
+       out_le32(&pex->bridge.pex_int_axi_misc_enb,
+               in_le32(&pex->bridge.pex_int_axi_misc_enb) | 0x1E0);
+
+       /* Hose configure header is memory-mapped */
+       hose_cfg_base = (void *)pex;
+
+       get_clocks();
+       /* Configure the PCIE controller core clock ratio */
+       out_le32(hose_cfg_base + PEX_GCLK_RATIO,
+               (((bus ? gd->pciexp2_clk : gd->pciexp1_clk) / 1000000) * 16)
+               / 333);
+       udelay(1000000);
+
+       /* Do Type 1 bridge configuration */
+       out_8(hose_cfg_base + PCI_PRIMARY_BUS, 0);
+       out_8(hose_cfg_base + PCI_SECONDARY_BUS, 1);
+       out_8(hose_cfg_base + PCI_SUBORDINATE_BUS, 255);
+
+       /*
+        * Write to Command register
+        */
+       reg16 = in_le16(hose_cfg_base + PCI_COMMAND);
+       reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO |
+                       PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
+       out_le16(hose_cfg_base + PCI_COMMAND, reg16);
+
+       /*
+        * Clear non-reserved bits in status register.
+        */
+       out_le16(hose_cfg_base + PCI_STATUS, 0xffff);
+       out_8(hose_cfg_base + PCI_LATENCY_TIMER, 0x80);
+       out_8(hose_cfg_base + PCI_CACHE_LINE_SIZE, 0x08);
+
+       printf("PCIE%d: ", bus);
+
+       reg16 = in_le16(hose_cfg_base + PCI_LTSSM);
+       if (reg16 >= PCI_LTSSM_L0)
+               printf("link\n");
+       else
+               printf("No link\n");
+
+       mpc83xx_pcie_register_hose(bus, reg, reg16 >= PCI_LTSSM_L0);
+}
+
+/*
+ * The caller must have already set SCCR, SERDES and the PCIE_LAW BARs
+ * must have been set to cover all of the requested regions.
+ */
+void mpc83xx_pcie_init(int num_buses, struct pci_region **reg, int warmboot)
+{
+       int i;
+
+       /*
+        * Release PCI RST Output signal.
+        * Power on to RST high must be at least 100 ms as per PCI spec.
+        * On warm boots only 1 ms is required.
+        */
+       udelay(warmboot ? 1000 : 100000);
+
+       for (i = 0; i < num_buses; i++)
+               mpc83xx_pcie_init_bus(i, reg[i]);
+}
index bf9bf36e5f1766ffc65f3056a13e4b069ee41e3c..4230099c0ce77605592be9fb11b3e7ed3f32e6b1 100644 (file)
@@ -132,7 +132,7 @@ int get_clocks(void)
        u32 qe_clk;
        u32 brg_clk;
 #endif
-#if defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC831X)
        u32 pciexp1_clk;
        u32 pciexp2_clk;
 #endif
@@ -328,7 +328,7 @@ int get_clocks(void)
        i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
 #endif
 
-#if defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC831X)
        switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
        case 0:
                pciexp1_clk = 0;
index 2bb50b47f518cb4eeb9222bc6ce308e45f6fee4b..e5a3b2c170abf2f3d27a23d905835dae75b03ad8 100644 (file)
@@ -75,7 +75,7 @@ typedef       struct  global_data {
        u32 lbiu_clk;
        u32 lclk_clk;
        u32 pci_clk;
-#if defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC831X)
        u32 pciexp1_clk;
        u32 pciexp2_clk;
 #endif
index df24a6e874c217b327e4a312400d1ab792421826..77c09db6b891365eaefa62fc394b062f7785ab8c 100644 (file)
@@ -52,23 +52,28 @@ typedef struct sysconf83xx {
        law83xx_t lblaw[4];     /* LBIU local access window */
        u8 res2[0x20];
        law83xx_t pcilaw[2];    /* PCI local access window */
-       u8 res3[0x30];
+       u8 res3[0x10];
+       law83xx_t pcielaw[2];   /* PCI Express local access window */
+       u8 res4[0x10];
        law83xx_t ddrlaw[2];    /* DDR local access window */
-       u8 res4[0x50];
+       u8 res5[0x50];
        u32 sgprl;              /* System General Purpose Register Low */
        u32 sgprh;              /* System General Purpose Register High */
        u32 spridr;             /* System Part and Revision ID Register */
-       u8 res5[0x04];
+       u8 res6[0x04];
        u32 spcr;               /* System Priority Configuration Register */
        u32 sicrl;              /* System I/O Configuration Register Low */
        u32 sicrh;              /* System I/O Configuration Register High */
-       u8 res6[0x04];
+       u8 res7[0x04];
        u32 sidcr0;             /* System I/O Delay Configuration Register 0 */
        u32 sidcr1;             /* System I/O Delay Configuration Register 1 */
        u32 ddrcdr;             /* DDR Control Driver Register */
        u32 ddrdsr;             /* DDR Debug Status Register */
        u32 obir;               /* Output Buffer Impedance Register */
-       u8 res7[0xCC];
+       u8 res8[0xC];
+       u32 pecr1;              /* PCI Express control register 1 */
+       u32 pecr2;              /* PCI Express control register 2 */
+       u8 res9[0xB8];
 } sysconf83xx_t;
 
 /*
@@ -503,8 +508,110 @@ typedef struct security83xx {
 /*
  *  PCI Express
  */
+struct pex_inbound_window {
+       u32 ar;
+       u32 tar;
+       u32 barl;
+       u32 barh;
+};
+
+struct pex_outbound_window {
+       u32 ar;
+       u32 bar;
+       u32 tarl;
+       u32 tarh;
+};
+
+struct pex_csb_bridge {
+       u32 pex_csb_ver;
+       u32 pex_csb_cab;
+       u32 pex_csb_ctrl;
+       u8 res0[8];
+       u32 pex_dms_dstmr;
+       u8 res1[4];
+       u32 pex_cbs_stat;
+       u8 res2[0x20];
+       u32 pex_csb_obctrl;
+       u32 pex_csb_obstat;
+       u8 res3[0x98];
+       u32 pex_csb_ibctrl;
+       u32 pex_csb_ibstat;
+       u8 res4[0xb8];
+       u32 pex_wdma_ctrl;
+       u32 pex_wdma_addr;
+       u32 pex_wdma_stat;
+       u8 res5[0x94];
+       u32 pex_rdma_ctrl;
+       u32 pex_rdma_addr;
+       u32 pex_rdma_stat;
+       u8 res6[0xd4];
+       u32 pex_ombcr;
+       u32 pex_ombdr;
+       u8 res7[0x38];
+       u32 pex_imbcr;
+       u32 pex_imbdr;
+       u8 res8[0x38];
+       u32 pex_int_enb;
+       u32 pex_int_stat;
+       u32 pex_int_apio_vec1;
+       u32 pex_int_apio_vec2;
+       u8 res9[0x10];
+       u32 pex_int_ppio_vec1;
+       u32 pex_int_ppio_vec2;
+       u32 pex_int_wdma_vec1;
+       u32 pex_int_wdma_vec2;
+       u32 pex_int_rdma_vec1;
+       u32 pex_int_rdma_vec2;
+       u32 pex_int_misc_vec;
+       u8 res10[4];
+       u32 pex_int_axi_pio_enb;
+       u32 pex_int_axi_wdma_enb;
+       u32 pex_int_axi_rdma_enb;
+       u32 pex_int_axi_misc_enb;
+       u32 pex_int_axi_pio_stat;
+       u32 pex_int_axi_wdma_stat;
+       u32 pex_int_axi_rdma_stat;
+       u32 pex_int_axi_misc_stat;
+       u8 res11[0xa0];
+       struct pex_outbound_window pex_outbound_win[4];
+       u8 res12[0x100];
+       u32 pex_epiwtar0;
+       u32 pex_epiwtar1;
+       u32 pex_epiwtar2;
+       u32 pex_epiwtar3;
+       u8 res13[0x70];
+       struct pex_inbound_window pex_inbound_win[4];
+};
+
 typedef struct pex83xx {
-       u8 fixme[0x1000];
+       u8 pex_cfg_header[0x404];
+       u32 pex_ltssm_stat;
+       u8 res0[0x30];
+       u32 pex_ack_replay_timeout;
+       u8 res1[4];
+       u32 pex_gclk_ratio;
+       u8 res2[0xc];
+       u32 pex_pm_timer;
+       u32 pex_pme_timeout;
+       u8 res3[4];
+       u32 pex_aspm_req_timer;
+       u8 res4[0x18];
+       u32 pex_ssvid_update;
+       u8 res5[0x34];
+       u32 pex_cfg_ready;
+       u8 res6[0x24];
+       u32 pex_bar_sizel;
+       u8 res7[4];
+       u32 pex_bar_sel;
+       u8 res8[0x20];
+       u32 pex_bar_pf;
+       u8 res9[0x88];
+       u32 pex_pme_to_ack_tor;
+       u8 res10[0xc];
+       u32 pex_ss_intr_mask;
+       u8 res11[0x25c];
+       struct pex_csb_bridge bridge;
+       u8 res12[0x160];
 } pex83xx_t;
 
 /*
index e5dfe3f21e801c6409e54b679cdd9843a451d9b0..191488aa89938d2454438bdd36878b717435c9e3 100644 (file)
 #define SCCR_USBDRCM_2                 0x00800000
 #define SCCR_USBDRCM_3                 0x00c00000
 
-#define SCCR_PCIEXP1CM                 0x00300000
-#define SCCR_PCIEXP2CM                 0x000c0000
-
 #define SCCR_SATA1CM                   0x00003000
 #define SCCR_SATA1CM_SHIFT             12
 #define SCCR_SATACM                    0x00003c00
 #define SCCR_USBDRCM_2                 0x00800000
 #define SCCR_USBDRCM_3                 0x00c00000
 
+/* All of the four SATA controllers must have the same clock ratio */
+#define SCCR_SATA1CM                   0x000000c0
+#define SCCR_SATA1CM_SHIFT             6
+#define SCCR_SATACM                    0x000000ff
+#define SCCR_SATACM_SHIFT              0
+#define SCCR_SATACM_0                  0x00000000
+#define SCCR_SATACM_1                  0x00000055
+#define SCCR_SATACM_2                  0x000000aa
+#define SCCR_SATACM_3                  0x000000ff
+#endif
+
 #define SCCR_PCIEXP1CM                 0x00300000
 #define SCCR_PCIEXP1CM_SHIFT           20
 #define SCCR_PCIEXP1CM_0               0x00000000
 #define SCCR_PCIEXP2CM_2               0x00080000
 #define SCCR_PCIEXP2CM_3               0x000c0000
 
-/* All of the four SATA controllers must have the same clock ratio */
-#define SCCR_SATA1CM                   0x000000c0
-#define SCCR_SATA1CM_SHIFT             6
-#define SCCR_SATACM                    0x000000ff
-#define SCCR_SATACM_SHIFT              0
-#define SCCR_SATACM_0                  0x00000000
-#define SCCR_SATACM_1                  0x00000055
-#define SCCR_SATACM_2                  0x000000aa
-#define SCCR_SATACM_3                  0x000000ff
-#endif
-
 /* CSn_BDNS - Chip Select memory Bounds Register
  */
 #define CSBNDS_SA                      0x00FF0000
 #define DDRCDR_M_ODR           0x00000002
 #define DDRCDR_Q_DRN           0x00000001
 
+/* PCIE Bridge Register
+*/
+#define PEX_CSB_CTRL_OBPIOE    0x00000001
+#define PEX_CSB_CTRL_IBPIOE    0x00000002
+#define PEX_CSB_CTRL_WDMAE     0x00000004
+#define PEX_CSB_CTRL_RDMAE     0x00000008
+
+#define PEX_CSB_OBCTRL_PIOE    0x00000001
+#define PEX_CSB_OBCTRL_MEMWE   0x00000002
+#define PEX_CSB_OBCTRL_IOWE    0x00000004
+#define PEX_CSB_OBCTRL_CFGWE   0x00000008
+
+#define PEX_CSB_IBCTRL_PIOE    0x00000001
+
+#define PEX_OWAR_EN            0x00000001
+#define PEX_OWAR_TYPE_CFG      0x00000000
+#define PEX_OWAR_TYPE_IO       0x00000002
+#define PEX_OWAR_TYPE_MEM      0x00000004
+#define PEX_OWAR_RLXO          0x00000008
+#define PEX_OWAR_NANP          0x00000010
+#define PEX_OWAR_SIZE          0xFFFFF000
+
+#define PEX_IWAR_EN            0x00000001
+#define PEX_IWAR_TYPE_INT      0x00000000
+#define PEX_IWAR_TYPE_PF       0x00000004
+#define PEX_IWAR_TYPE_NO_PF    0x00000006
+#define PEX_IWAR_NSOV          0x00000008
+#define PEX_IWAR_NSNP          0x00000010
+#define PEX_IWAR_SIZE          0xFFFFF000
+#define PEX_IWAR_SIZE_1M       0x000FF000
+#define PEX_IWAR_SIZE_2M       0x001FF000
+#define PEX_IWAR_SIZE_4M       0x003FF000
+#define PEX_IWAR_SIZE_8M       0x007FF000
+#define PEX_IWAR_SIZE_16M      0x00FFF000
+#define PEX_IWAR_SIZE_32M      0x01FFF000
+#define PEX_IWAR_SIZE_64M      0x03FFF000
+#define PEX_IWAR_SIZE_128M     0x07FFF000
+#define PEX_IWAR_SIZE_256M     0x0FFFF000
+
+#define PEX_GCLK_RATIO         0x440
+
 #ifndef __ASSEMBLY__
 struct pci_region;
 void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot);
 void mpc83xx_pcislave_unlock(int bus);
+void mpc83xx_pcie_init(int num_buses, struct pci_region **reg, int warmboot);
 #endif
 
 #endif /* __MPC83XX_H__ */
index eebe8a8a548c4785c6361f3ebe80afa72d43fdce..072273be572b1e7f14773cb865087736044ba4ce 100644 (file)
@@ -382,6 +382,8 @@ extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev
 
 #define MAX_PCI_REGIONS                7
 
+#define INDIRECT_TYPE_NO_PCIE_LINK     1
+
 /*
  * Structure of a PCI controller (host bridge)
  */
@@ -394,6 +396,8 @@ struct pci_controller {
        volatile unsigned int *cfg_addr;
        volatile unsigned char *cfg_data;
 
+       int indirect_type;
+
        struct pci_region regions[MAX_PCI_REGIONS];
        int region_count;