+++ /dev/null
-/*
- * NVIDIA Tegra SPI controller
- *
- * Copyright 2010-2013 NVIDIA Corporation
- *
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _TEGRA114_SPI_H_
-#define _TEGRA114_SPI_H_
-
-#include <asm/types.h>
-
-int tegra114_spi_init(int *node_list, int count);
-int tegra114_spi_cs_is_valid(unsigned int bus, unsigned int cs);
-struct spi_slave *tegra114_spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode);
-void tegra114_spi_free_slave(struct spi_slave *slave);
-int tegra114_spi_claim_bus(struct spi_slave *slave);
-void tegra114_spi_cs_activate(struct spi_slave *slave);
-void tegra114_spi_cs_deactivate(struct spi_slave *slave);
-int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
- const void *data_out, void *data_in, unsigned long flags);
-
-#endif /* _TEGRA114_SPI_H_ */
+++ /dev/null
-/*
- * NVIDIA Tegra20 SPI-FLASH controller
- *
- * Copyright 2010-2012 NVIDIA Corporation
- *
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _TEGRA20_SPI_H_
-#define _TEGRA20_SPI_H_
-
-#include <asm/types.h>
-
-int tegra20_spi_cs_is_valid(unsigned int bus, unsigned int cs);
-struct spi_slave *tegra20_spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode);
-void tegra20_spi_free_slave(struct spi_slave *slave);
-int tegra20_spi_init(int *node_list, int count);
-int tegra20_spi_claim_bus(struct spi_slave *slave);
-void tegra20_spi_cs_activate(struct spi_slave *slave);
-void tegra20_spi_cs_deactivate(struct spi_slave *slave);
-int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
- const void *data_out, void *data_in, unsigned long flags);
-
-#endif /* _TEGRA20_SPI_H_ */
+++ /dev/null
-/*
- * NVIDIA Tegra SPI-SLINK controller
- *
- * Copyright 2010-2013 NVIDIA Corporation
- *
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _TEGRA30_SPI_H_
-#define _TEGRA30_SPI_H_
-
-#include <asm/types.h>
-
-int tegra30_spi_init(int *node_list, int count);
-int tegra30_spi_cs_is_valid(unsigned int bus, unsigned int cs);
-struct spi_slave *tegra30_spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode);
-void tegra30_spi_free_slave(struct spi_slave *slave);
-int tegra30_spi_claim_bus(struct spi_slave *slave);
-void tegra30_spi_cs_activate(struct spi_slave *slave);
-void tegra30_spi_cs_deactivate(struct spi_slave *slave);
-int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
- const void *data_out, void *data_in, unsigned long flags);
-
-#endif /* _TEGRA30_SPI_H_ */
clock_init();
clock_verify();
-#ifdef CONFIG_FDT_SPI
+#ifdef CONFIG_TEGRA_SPI
pin_mux_spi();
- spi_init();
#endif
#ifdef CONFIG_PWM_TEGRA
obj-$(CONFIG_SH_SPI) += sh_spi.o
obj-$(CONFIG_SH_QSPI) += sh_qspi.o
obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
-obj-$(CONFIG_FDT_SPI) += fdt_spi.o
obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
+++ /dev/null
-/*
- * Common fdt based SPI driver front end
- *
- * Copyright (c) 2013 NVIDIA Corporation
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <asm/io.h>
-#include <asm/gpio.h>
-#include <asm/arch/clock.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra20/tegra20_sflash.h>
-#include <asm/arch-tegra20/tegra20_slink.h>
-#include <asm/arch-tegra114/tegra114_spi.h>
-#include <spi.h>
-#include <fdtdec.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct fdt_spi_driver {
- int compat;
- int max_ctrls;
- int (*init)(int *node_list, int count);
- int (*claim_bus)(struct spi_slave *slave);
- int (*release_bus)(struct spi_slave *slave);
- int (*cs_is_valid)(unsigned int bus, unsigned int cs);
- struct spi_slave *(*setup_slave)(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode);
- void (*free_slave)(struct spi_slave *slave);
- void (*cs_activate)(struct spi_slave *slave);
- void (*cs_deactivate)(struct spi_slave *slave);
- int (*xfer)(struct spi_slave *slave, unsigned int bitlen,
- const void *data_out, void *data_in, unsigned long flags);
-};
-
-static struct fdt_spi_driver fdt_spi_drivers[] = {
-#ifdef CONFIG_TEGRA20_SFLASH
- {
- .compat = COMPAT_NVIDIA_TEGRA20_SFLASH,
- .max_ctrls = 1,
- .init = tegra20_spi_init,
- .claim_bus = tegra20_spi_claim_bus,
- .cs_is_valid = tegra20_spi_cs_is_valid,
- .setup_slave = tegra20_spi_setup_slave,
- .free_slave = tegra20_spi_free_slave,
- .cs_activate = tegra20_spi_cs_activate,
- .cs_deactivate = tegra20_spi_cs_deactivate,
- .xfer = tegra20_spi_xfer,
- },
-#endif
-#ifdef CONFIG_TEGRA20_SLINK
- {
- .compat = COMPAT_NVIDIA_TEGRA20_SLINK,
- .max_ctrls = CONFIG_TEGRA_SLINK_CTRLS,
- .init = tegra30_spi_init,
- .claim_bus = tegra30_spi_claim_bus,
- .cs_is_valid = tegra30_spi_cs_is_valid,
- .setup_slave = tegra30_spi_setup_slave,
- .free_slave = tegra30_spi_free_slave,
- .cs_activate = tegra30_spi_cs_activate,
- .cs_deactivate = tegra30_spi_cs_deactivate,
- .xfer = tegra30_spi_xfer,
- },
-#endif
-#ifdef CONFIG_TEGRA114_SPI
- {
- .compat = COMPAT_NVIDIA_TEGRA114_SPI,
- .max_ctrls = CONFIG_TEGRA114_SPI_CTRLS,
- .init = tegra114_spi_init,
- .claim_bus = tegra114_spi_claim_bus,
- .cs_is_valid = tegra114_spi_cs_is_valid,
- .setup_slave = tegra114_spi_setup_slave,
- .free_slave = tegra114_spi_free_slave,
- .cs_activate = tegra114_spi_cs_activate,
- .cs_deactivate = tegra114_spi_cs_deactivate,
- .xfer = tegra114_spi_xfer,
- },
-#endif
-};
-
-static struct fdt_spi_driver *driver;
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- if (!driver)
- return 0;
- else if (!driver->cs_is_valid)
- return 1;
- else
- return driver->cs_is_valid(bus, cs);
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- if (!driver || !driver->setup_slave)
- return NULL;
-
- return driver->setup_slave(bus, cs, max_hz, mode);
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- if (driver && driver->free_slave)
- return driver->free_slave(slave);
-}
-
-static int spi_init_driver(struct fdt_spi_driver *driver)
-{
- int count;
- int node_list[driver->max_ctrls];
-
- count = fdtdec_find_aliases_for_id(gd->fdt_blob, "spi",
- driver->compat,
- node_list,
- driver->max_ctrls);
- return driver->init(node_list, count);
-}
-
-void spi_init(void)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(fdt_spi_drivers); i++) {
- driver = &fdt_spi_drivers[i];
- if (!spi_init_driver(driver))
- break;
- }
- if (i == ARRAY_SIZE(fdt_spi_drivers))
- driver = NULL;
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- if (!driver)
- return 1;
- if (!driver->claim_bus)
- return 0;
-
- return driver->claim_bus(slave);
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
- if (driver && driver->release_bus)
- driver->release_bus(slave);
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- if (driver && driver->cs_activate)
- driver->cs_activate(slave);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- if (driver && driver->cs_deactivate)
- driver->cs_deactivate(slave);
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
- const void *data_out, void *data_in, unsigned long flags)
-{
- if (!driver || !driver->xfer)
- return -1;
-
- return driver->xfer(slave, bitlen, data_out, data_in, flags);
-}
*/
#include <common.h>
-#include <malloc.h>
+#include <dm.h>
#include <asm/io.h>
-#include <asm/gpio.h>
#include <asm/arch/clock.h>
#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra114/tegra114_spi.h>
#include <spi.h>
#include <fdtdec.h>
+#include "tegra_spi.h"
DECLARE_GLOBAL_DATA_PTR;
u32 spare_ctl; /* 18c:SPI_SPARE_CTRL register */
};
-struct tegra_spi_ctrl {
+struct tegra114_spi_priv {
struct spi_regs *regs;
unsigned int freq;
unsigned int mode;
int periph_id;
int valid;
+ int last_transaction_us;
};
-struct tegra_spi_slave {
- struct spi_slave slave;
- struct tegra_spi_ctrl *ctrl;
-};
-
-static struct tegra_spi_ctrl spi_ctrls[CONFIG_TEGRA114_SPI_CTRLS];
-
-static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
+static int tegra114_spi_ofdata_to_platdata(struct udevice *bus)
{
- return container_of(slave, struct tegra_spi_slave, slave);
-}
+ struct tegra_spi_platdata *plat = bus->platdata;
+ const void *blob = gd->fdt_blob;
+ int node = bus->of_offset;
-int tegra114_spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- if (bus >= CONFIG_TEGRA114_SPI_CTRLS || cs > 3 || !spi_ctrls[bus].valid)
- return 0;
- else
- return 1;
-}
+ plat->base = fdtdec_get_addr(blob, node, "reg");
+ plat->periph_id = clock_decode_periph_id(blob, node);
-struct spi_slave *tegra114_spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct tegra_spi_slave *spi;
-
- debug("%s: bus: %u, cs: %u, max_hz: %u, mode: %u\n", __func__,
- bus, cs, max_hz, mode);
-
- if (!spi_cs_is_valid(bus, cs)) {
- printf("SPI error: unsupported bus %d / chip select %d\n",
- bus, cs);
- return NULL;
- }
-
- if (max_hz > TEGRA_SPI_MAX_FREQ) {
- printf("SPI error: unsupported frequency %d Hz. Max frequency"
- " is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
- return NULL;
+ if (plat->periph_id == PERIPH_ID_NONE) {
+ debug("%s: could not decode periph id %d\n", __func__,
+ plat->periph_id);
+ return -FDT_ERR_NOTFOUND;
}
- spi = spi_alloc_slave(struct tegra_spi_slave, bus, cs);
- if (!spi) {
- printf("SPI error: malloc of SPI structure failed\n");
- return NULL;
- }
- spi->ctrl = &spi_ctrls[bus];
- if (!spi->ctrl) {
- printf("SPI error: could not find controller for bus %d\n",
- bus);
- return NULL;
- }
+ /* Use 500KHz as a suitable default */
+ plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
+ 500000);
+ plat->deactivate_delay_us = fdtdec_get_int(blob, node,
+ "spi-deactivate-delay", 0);
+ debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
+ __func__, plat->base, plat->periph_id, plat->frequency,
+ plat->deactivate_delay_us);
- if (max_hz < spi->ctrl->freq) {
- debug("%s: limiting frequency from %u to %u\n", __func__,
- spi->ctrl->freq, max_hz);
- spi->ctrl->freq = max_hz;
- }
- spi->ctrl->mode = mode;
-
- return &spi->slave;
-}
-
-void tegra114_spi_free_slave(struct spi_slave *slave)
-{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
-
- free(spi);
+ return 0;
}
-int tegra114_spi_init(int *node_list, int count)
+static int tegra114_spi_probe(struct udevice *bus)
{
- struct tegra_spi_ctrl *ctrl;
- int i;
- int node = 0;
- int found = 0;
-
- for (i = 0; i < count; i++) {
- ctrl = &spi_ctrls[i];
- node = node_list[i];
-
- ctrl->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob,
- node, "reg");
- if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) {
- debug("%s: no spi register found\n", __func__);
- continue;
- }
- ctrl->freq = fdtdec_get_int(gd->fdt_blob, node,
- "spi-max-frequency", 0);
- if (!ctrl->freq) {
- debug("%s: no spi max frequency found\n", __func__);
- continue;
- }
+ struct tegra_spi_platdata *plat = dev_get_platdata(bus);
+ struct tegra114_spi_priv *priv = dev_get_priv(bus);
- ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
- if (ctrl->periph_id == PERIPH_ID_NONE) {
- debug("%s: could not decode periph id\n", __func__);
- continue;
- }
- ctrl->valid = 1;
- found = 1;
+ priv->regs = (struct spi_regs *)plat->base;
- debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
- __func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
- }
+ priv->last_transaction_us = timer_get_us();
+ priv->freq = plat->frequency;
+ priv->periph_id = plat->periph_id;
- return !found;
+ return 0;
}
-int tegra114_spi_claim_bus(struct spi_slave *slave)
+static int tegra114_spi_claim_bus(struct udevice *bus)
{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
- struct spi_regs *regs = spi->ctrl->regs;
+ struct tegra114_spi_priv *priv = dev_get_priv(bus);
+ struct spi_regs *regs = priv->regs;
/* Change SPI clock to correct frequency, PLLP_OUT0 source */
- clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH,
- spi->ctrl->freq);
+ clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
/* Clear stale status here */
setbits_le32(®s->fifo_status,
/* Set master mode and sw controlled CS */
setbits_le32(®s->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW |
- (spi->ctrl->mode << SPI_CMD1_MODE_SHIFT));
+ (priv->mode << SPI_CMD1_MODE_SHIFT));
debug("%s: COMMAND1 = %08x\n", __func__, readl(®s->command1));
return 0;
}
-void tegra114_spi_cs_activate(struct spi_slave *slave)
+/**
+ * Activate the CS by driving it LOW
+ *
+ * @param slave Pointer to spi_slave to which controller has to
+ * communicate with
+ */
+static void spi_cs_activate(struct udevice *dev)
{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
- struct spi_regs *regs = spi->ctrl->regs;
+ struct udevice *bus = dev->parent;
+ struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
+ struct tegra114_spi_priv *priv = dev_get_priv(bus);
+
+ /* If it's too soon to do another transaction, wait */
+ if (pdata->deactivate_delay_us &&
+ priv->last_transaction_us) {
+ ulong delay_us; /* The delay completed so far */
+ delay_us = timer_get_us() - priv->last_transaction_us;
+ if (delay_us < pdata->deactivate_delay_us)
+ udelay(pdata->deactivate_delay_us - delay_us);
+ }
- clrbits_le32(®s->command1, SPI_CMD1_CS_SW_VAL);
+ clrbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL);
}
-void tegra114_spi_cs_deactivate(struct spi_slave *slave)
+/**
+ * Deactivate the CS by driving it HIGH
+ *
+ * @param slave Pointer to spi_slave to which controller has to
+ * communicate with
+ */
+static void spi_cs_deactivate(struct udevice *dev)
{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
- struct spi_regs *regs = spi->ctrl->regs;
+ struct udevice *bus = dev->parent;
+ struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
+ struct tegra114_spi_priv *priv = dev_get_priv(bus);
+
+ setbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL);
- setbits_le32(®s->command1, SPI_CMD1_CS_SW_VAL);
+ /* Remember time of this transaction so we can honour the bus delay */
+ if (pdata->deactivate_delay_us)
+ priv->last_transaction_us = timer_get_us();
+
+ debug("Deactivate CS, bus '%s'\n", bus->name);
}
-int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
- const void *data_out, void *data_in, unsigned long flags)
+static int tegra114_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *data_out, void *data_in,
+ unsigned long flags)
{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
- struct spi_regs *regs = spi->ctrl->regs;
+ struct udevice *bus = dev->parent;
+ struct tegra114_spi_priv *priv = dev_get_priv(bus);
+ struct spi_regs *regs = priv->regs;
u32 reg, tmpdout, tmpdin = 0;
const u8 *dout = data_out;
u8 *din = data_in;
int ret;
debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
- __func__, slave->bus, slave->cs, dout, din, bitlen);
+ __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
if (bitlen % 8)
return -1;
num_bytes = bitlen / 8;
clrsetbits_le32(®s->command1, SPI_CMD1_CS_SW_VAL,
SPI_CMD1_RX_EN | SPI_CMD1_TX_EN | SPI_CMD1_LSBY_FE |
- (slave->cs << SPI_CMD1_CS_SEL_SHIFT));
+ (spi_chip_select(dev) << SPI_CMD1_CS_SEL_SHIFT));
/* set xfer size to 1 block (32 bits) */
writel(0, ®s->dma_blk);
if (flags & SPI_XFER_BEGIN)
- spi_cs_activate(slave);
+ spi_cs_activate(dev);
/* handle data in 32-bit chunks */
while (num_bytes > 0) {
}
if (flags & SPI_XFER_END)
- spi_cs_deactivate(slave);
+ spi_cs_deactivate(dev);
debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n",
__func__, tmpdin, readl(®s->fifo_status));
return -1;
}
+ return ret;
+}
+
+static int tegra114_spi_set_speed(struct udevice *bus, uint speed)
+{
+ struct tegra_spi_platdata *plat = bus->platdata;
+ struct tegra114_spi_priv *priv = dev_get_priv(bus);
+
+ if (speed > plat->frequency)
+ speed = plat->frequency;
+ priv->freq = speed;
+ debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
+
return 0;
}
+
+static int tegra114_spi_set_mode(struct udevice *bus, uint mode)
+{
+ struct tegra114_spi_priv *priv = dev_get_priv(bus);
+
+ priv->mode = mode;
+ debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
+
+ return 0;
+}
+
+static const struct dm_spi_ops tegra114_spi_ops = {
+ .claim_bus = tegra114_spi_claim_bus,
+ .xfer = tegra114_spi_xfer,
+ .set_speed = tegra114_spi_set_speed,
+ .set_mode = tegra114_spi_set_mode,
+ /*
+ * cs_info is not needed, since we require all chip selects to be
+ * in the device tree explicitly
+ */
+};
+
+static const struct udevice_id tegra114_spi_ids[] = {
+ { .compatible = "nvidia,tegra114-spi" },
+ { }
+};
+
+U_BOOT_DRIVER(tegra114_spi) = {
+ .name = "tegra114_spi",
+ .id = UCLASS_SPI,
+ .of_match = tegra114_spi_ids,
+ .ops = &tegra114_spi_ops,
+ .ofdata_to_platdata = tegra114_spi_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
+ .priv_auto_alloc_size = sizeof(struct tegra114_spi_priv),
+ .per_child_auto_alloc_size = sizeof(struct spi_slave),
+ .probe = tegra114_spi_probe,
+};
*/
#include <common.h>
-#include <malloc.h>
+#include <dm.h>
+#include <errno.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/clock.h>
#include <asm/arch/pinmux.h>
#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra20/tegra20_sflash.h>
#include <spi.h>
#include <fdtdec.h>
+#include "tegra_spi.h"
DECLARE_GLOBAL_DATA_PTR;
u32 rx_fifo; /* SPI_RX_FIFO_0 register */
};
-struct tegra_spi_ctrl {
+struct tegra20_sflash_priv {
struct spi_regs *regs;
unsigned int freq;
unsigned int mode;
int periph_id;
int valid;
+ int last_transaction_us;
};
-struct tegra_spi_slave {
- struct spi_slave slave;
- struct tegra_spi_ctrl *ctrl;
-};
-
-/* tegra20 only supports one SFLASH controller */
-static struct tegra_spi_ctrl spi_ctrls[1];
-
-static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
-{
- return container_of(slave, struct tegra_spi_slave, slave);
-}
-
-int tegra20_spi_cs_is_valid(unsigned int bus, unsigned int cs)
+int tegra20_sflash_cs_info(struct udevice *bus, unsigned int cs,
+ struct spi_cs_info *info)
{
/* Tegra20 SPI-Flash - only 1 device ('bus/cs') */
- if (bus != 0 || cs != 0)
- return 0;
+ if (cs != 0)
+ return -ENODEV;
else
- return 1;
+ return 0;
}
-struct spi_slave *tegra20_spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
+static int tegra20_sflash_ofdata_to_platdata(struct udevice *bus)
{
- struct tegra_spi_slave *spi;
+ struct tegra_spi_platdata *plat = bus->platdata;
+ const void *blob = gd->fdt_blob;
+ int node = bus->of_offset;
- if (!spi_cs_is_valid(bus, cs)) {
- printf("SPI error: unsupported bus %d / chip select %d\n",
- bus, cs);
- return NULL;
- }
+ plat->base = fdtdec_get_addr(blob, node, "reg");
+ plat->periph_id = clock_decode_periph_id(blob, node);
- if (max_hz > TEGRA_SPI_MAX_FREQ) {
- printf("SPI error: unsupported frequency %d Hz. Max frequency"
- " is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
- return NULL;
+ if (plat->periph_id == PERIPH_ID_NONE) {
+ debug("%s: could not decode periph id %d\n", __func__,
+ plat->periph_id);
+ return -FDT_ERR_NOTFOUND;
}
- spi = spi_alloc_slave(struct tegra_spi_slave, bus, cs);
- if (!spi) {
- printf("SPI error: malloc of SPI structure failed\n");
- return NULL;
- }
- spi->ctrl = &spi_ctrls[bus];
- if (!spi->ctrl) {
- printf("SPI error: could not find controller for bus %d\n",
- bus);
- return NULL;
- }
+ /* Use 500KHz as a suitable default */
+ plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
+ 500000);
+ plat->deactivate_delay_us = fdtdec_get_int(blob, node,
+ "spi-deactivate-delay", 0);
+ debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
+ __func__, plat->base, plat->periph_id, plat->frequency,
+ plat->deactivate_delay_us);
- if (max_hz < spi->ctrl->freq) {
- debug("%s: limiting frequency from %u to %u\n", __func__,
- spi->ctrl->freq, max_hz);
- spi->ctrl->freq = max_hz;
- }
- spi->ctrl->mode = mode;
-
- return &spi->slave;
+ return 0;
}
-void tegra20_spi_free_slave(struct spi_slave *slave)
+static int tegra20_sflash_probe(struct udevice *bus)
{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
-
- free(spi);
-}
+ struct tegra_spi_platdata *plat = dev_get_platdata(bus);
+ struct tegra20_sflash_priv *priv = dev_get_priv(bus);
-int tegra20_spi_init(int *node_list, int count)
-{
- struct tegra_spi_ctrl *ctrl;
- int i;
- int node = 0;
- int found = 0;
-
- for (i = 0; i < count; i++) {
- ctrl = &spi_ctrls[i];
- node = node_list[i];
-
- ctrl->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob,
- node, "reg");
- if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) {
- debug("%s: no slink register found\n", __func__);
- continue;
- }
- ctrl->freq = fdtdec_get_int(gd->fdt_blob, node,
- "spi-max-frequency", 0);
- if (!ctrl->freq) {
- debug("%s: no slink max frequency found\n", __func__);
- continue;
- }
+ priv->regs = (struct spi_regs *)plat->base;
- ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
- if (ctrl->periph_id == PERIPH_ID_NONE) {
- debug("%s: could not decode periph id\n", __func__);
- continue;
- }
- ctrl->valid = 1;
- found = 1;
+ priv->last_transaction_us = timer_get_us();
+ priv->freq = plat->frequency;
+ priv->periph_id = plat->periph_id;
- debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
- __func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
- }
- return !found;
+ return 0;
}
-int tegra20_spi_claim_bus(struct spi_slave *slave)
+static int tegra20_sflash_claim_bus(struct udevice *bus)
{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
- struct spi_regs *regs = spi->ctrl->regs;
+ struct tegra20_sflash_priv *priv = dev_get_priv(bus);
+ struct spi_regs *regs = priv->regs;
u32 reg;
/* Change SPI clock to correct frequency, PLLP_OUT0 source */
- clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH,
- spi->ctrl->freq);
+ clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
+ priv->freq);
/* Clear stale status here */
reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
/*
* Use sw-controlled CS, so we can clock in data after ReadID, etc.
*/
- reg = (spi->ctrl->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT;
- if (spi->ctrl->mode & 2)
+ reg = (priv->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT;
+ if (priv->mode & 2)
reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT;
clrsetbits_le32(®s->command, SPI_CMD_ACTIVE_SCLK_MASK |
SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg);
return 0;
}
-void tegra20_spi_cs_activate(struct spi_slave *slave)
+static void spi_cs_activate(struct udevice *dev)
{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
- struct spi_regs *regs = spi->ctrl->regs;
+ struct udevice *bus = dev->parent;
+ struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
+ struct tegra20_sflash_priv *priv = dev_get_priv(bus);
+
+ /* If it's too soon to do another transaction, wait */
+ if (pdata->deactivate_delay_us &&
+ priv->last_transaction_us) {
+ ulong delay_us; /* The delay completed so far */
+ delay_us = timer_get_us() - priv->last_transaction_us;
+ if (delay_us < pdata->deactivate_delay_us)
+ udelay(pdata->deactivate_delay_us - delay_us);
+ }
/* CS is negated on Tegra, so drive a 1 to get a 0 */
- setbits_le32(®s->command, SPI_CMD_CS_VAL);
+ setbits_le32(&priv->regs->command, SPI_CMD_CS_VAL);
}
-void tegra20_spi_cs_deactivate(struct spi_slave *slave)
+static void spi_cs_deactivate(struct udevice *dev)
{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
- struct spi_regs *regs = spi->ctrl->regs;
+ struct udevice *bus = dev->parent;
+ struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
+ struct tegra20_sflash_priv *priv = dev_get_priv(bus);
/* CS is negated on Tegra, so drive a 0 to get a 1 */
- clrbits_le32(®s->command, SPI_CMD_CS_VAL);
+ clrbits_le32(&priv->regs->command, SPI_CMD_CS_VAL);
+
+ /* Remember time of this transaction so we can honour the bus delay */
+ if (pdata->deactivate_delay_us)
+ priv->last_transaction_us = timer_get_us();
}
-int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
- const void *data_out, void *data_in, unsigned long flags)
+static int tegra20_sflash_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *data_out, void *data_in,
+ unsigned long flags)
{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
- struct spi_regs *regs = spi->ctrl->regs;
+ struct udevice *bus = dev->parent;
+ struct tegra20_sflash_priv *priv = dev_get_priv(bus);
+ struct spi_regs *regs = priv->regs;
u32 reg, tmpdout, tmpdin = 0;
const u8 *dout = data_out;
u8 *din = data_in;
int num_bytes;
int ret;
- debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
- slave->bus, slave->cs, *(u8 *)dout, *(u8 *)din, bitlen);
+ debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
+ __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
if (bitlen % 8)
return -1;
num_bytes = bitlen / 8;
debug("spi_xfer: COMMAND = %08x\n", readl(®s->command));
if (flags & SPI_XFER_BEGIN)
- spi_cs_activate(slave);
+ spi_cs_activate(dev);
/* handle data in 32-bit chunks */
while (num_bytes > 0) {
}
if (flags & SPI_XFER_END)
- spi_cs_deactivate(slave);
+ spi_cs_deactivate(dev);
debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n",
tmpdin, readl(®s->status));
return 0;
}
+
+static int tegra20_sflash_set_speed(struct udevice *bus, uint speed)
+{
+ struct tegra_spi_platdata *plat = bus->platdata;
+ struct tegra20_sflash_priv *priv = dev_get_priv(bus);
+
+ if (speed > plat->frequency)
+ speed = plat->frequency;
+ priv->freq = speed;
+ debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
+
+ return 0;
+}
+
+static int tegra20_sflash_set_mode(struct udevice *bus, uint mode)
+{
+ struct tegra20_sflash_priv *priv = dev_get_priv(bus);
+
+ priv->mode = mode;
+ debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
+
+ return 0;
+}
+
+static const struct dm_spi_ops tegra20_sflash_ops = {
+ .claim_bus = tegra20_sflash_claim_bus,
+ .xfer = tegra20_sflash_xfer,
+ .set_speed = tegra20_sflash_set_speed,
+ .set_mode = tegra20_sflash_set_mode,
+ .cs_info = tegra20_sflash_cs_info,
+};
+
+static const struct udevice_id tegra20_sflash_ids[] = {
+ { .compatible = "nvidia,tegra20-sflash" },
+ { }
+};
+
+U_BOOT_DRIVER(tegra20_sflash) = {
+ .name = "tegra20_sflash",
+ .id = UCLASS_SPI,
+ .of_match = tegra20_sflash_ids,
+ .ops = &tegra20_sflash_ops,
+ .ofdata_to_platdata = tegra20_sflash_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
+ .priv_auto_alloc_size = sizeof(struct tegra20_sflash_priv),
+ .per_child_auto_alloc_size = sizeof(struct spi_slave),
+ .probe = tegra20_sflash_probe,
+};
*/
#include <common.h>
-#include <malloc.h>
+#include <dm.h>
#include <asm/io.h>
-#include <asm/gpio.h>
#include <asm/arch/clock.h>
#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra20/tegra20_slink.h>
#include <spi.h>
#include <fdtdec.h>
+#include "tegra_spi.h"
DECLARE_GLOBAL_DATA_PTR;
u32 rx_fifo; /* SLINK_RX_FIFO_0 reg off 180h */
};
-struct tegra_spi_ctrl {
+struct tegra30_spi_priv {
struct spi_regs *regs;
unsigned int freq;
unsigned int mode;
int periph_id;
int valid;
+ int last_transaction_us;
};
struct tegra_spi_slave {
struct spi_slave slave;
- struct tegra_spi_ctrl *ctrl;
+ struct tegra30_spi_priv *ctrl;
};
-static struct tegra_spi_ctrl spi_ctrls[CONFIG_TEGRA_SLINK_CTRLS];
-
-static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
-{
- return container_of(slave, struct tegra_spi_slave, slave);
-}
-
-int tegra30_spi_cs_is_valid(unsigned int bus, unsigned int cs)
+static int tegra30_spi_ofdata_to_platdata(struct udevice *bus)
{
- if (bus >= CONFIG_TEGRA_SLINK_CTRLS || cs > 3 || !spi_ctrls[bus].valid)
- return 0;
- else
- return 1;
-}
+ struct tegra_spi_platdata *plat = bus->platdata;
+ const void *blob = gd->fdt_blob;
+ int node = bus->of_offset;
-struct spi_slave *tegra30_spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct tegra_spi_slave *spi;
+ plat->base = fdtdec_get_addr(blob, node, "reg");
+ plat->periph_id = clock_decode_periph_id(blob, node);
- debug("%s: bus: %u, cs: %u, max_hz: %u, mode: %u\n", __func__,
- bus, cs, max_hz, mode);
-
- if (!spi_cs_is_valid(bus, cs)) {
- printf("SPI error: unsupported bus %d / chip select %d\n",
- bus, cs);
- return NULL;
- }
-
- if (max_hz > TEGRA_SPI_MAX_FREQ) {
- printf("SPI error: unsupported frequency %d Hz. Max frequency"
- " is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
- return NULL;
+ if (plat->periph_id == PERIPH_ID_NONE) {
+ debug("%s: could not decode periph id %d\n", __func__,
+ plat->periph_id);
+ return -FDT_ERR_NOTFOUND;
}
- spi = spi_alloc_slave(struct tegra_spi_slave, bus, cs);
- if (!spi) {
- printf("SPI error: malloc of SPI structure failed\n");
- return NULL;
- }
- spi->ctrl = &spi_ctrls[bus];
- if (!spi->ctrl) {
- printf("SPI error: could not find controller for bus %d\n",
- bus);
- return NULL;
- }
+ /* Use 500KHz as a suitable default */
+ plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
+ 500000);
+ plat->deactivate_delay_us = fdtdec_get_int(blob, node,
+ "spi-deactivate-delay", 0);
+ debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
+ __func__, plat->base, plat->periph_id, plat->frequency,
+ plat->deactivate_delay_us);
- if (max_hz < spi->ctrl->freq) {
- debug("%s: limiting frequency from %u to %u\n", __func__,
- spi->ctrl->freq, max_hz);
- spi->ctrl->freq = max_hz;
- }
- spi->ctrl->mode = mode;
-
- return &spi->slave;
+ return 0;
}
-void tegra30_spi_free_slave(struct spi_slave *slave)
+static int tegra30_spi_probe(struct udevice *bus)
{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
-
- free(spi);
-}
+ struct tegra_spi_platdata *plat = dev_get_platdata(bus);
+ struct tegra30_spi_priv *priv = dev_get_priv(bus);
-int tegra30_spi_init(int *node_list, int count)
-{
- struct tegra_spi_ctrl *ctrl;
- int i;
- int node = 0;
- int found = 0;
-
- for (i = 0; i < count; i++) {
- ctrl = &spi_ctrls[i];
- node = node_list[i];
-
- ctrl->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob,
- node, "reg");
- if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) {
- debug("%s: no slink register found\n", __func__);
- continue;
- }
- ctrl->freq = fdtdec_get_int(gd->fdt_blob, node,
- "spi-max-frequency", 0);
- if (!ctrl->freq) {
- debug("%s: no slink max frequency found\n", __func__);
- continue;
- }
+ priv->regs = (struct spi_regs *)plat->base;
- ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
- if (ctrl->periph_id == PERIPH_ID_NONE) {
- debug("%s: could not decode periph id\n", __func__);
- continue;
- }
- ctrl->valid = 1;
- found = 1;
+ priv->last_transaction_us = timer_get_us();
+ priv->freq = plat->frequency;
+ priv->periph_id = plat->periph_id;
- debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
- __func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
- }
- return !found;
+ return 0;
}
-int tegra30_spi_claim_bus(struct spi_slave *slave)
+static int tegra30_spi_claim_bus(struct udevice *bus)
{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
- struct spi_regs *regs = spi->ctrl->regs;
+ struct tegra30_spi_priv *priv = dev_get_priv(bus);
+ struct spi_regs *regs = priv->regs;
u32 reg;
/* Change SPI clock to correct frequency, PLLP_OUT0 source */
- clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH,
- spi->ctrl->freq);
+ clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
+ priv->freq);
/* Clear stale status here */
reg = SLINK_STAT_RDY | SLINK_STAT_RXF_FLUSH | SLINK_STAT_TXF_FLUSH | \
return 0;
}
-void tegra30_spi_cs_activate(struct spi_slave *slave)
+static void spi_cs_activate(struct udevice *dev)
{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
- struct spi_regs *regs = spi->ctrl->regs;
+ struct udevice *bus = dev->parent;
+ struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
+ struct tegra30_spi_priv *priv = dev_get_priv(bus);
+
+ /* If it's too soon to do another transaction, wait */
+ if (pdata->deactivate_delay_us &&
+ priv->last_transaction_us) {
+ ulong delay_us; /* The delay completed so far */
+ delay_us = timer_get_us() - priv->last_transaction_us;
+ if (delay_us < pdata->deactivate_delay_us)
+ udelay(pdata->deactivate_delay_us - delay_us);
+ }
/* CS is negated on Tegra, so drive a 1 to get a 0 */
- setbits_le32(®s->command, SLINK_CMD_CS_VAL);
+ setbits_le32(&priv->regs->command, SLINK_CMD_CS_VAL);
}
-void tegra30_spi_cs_deactivate(struct spi_slave *slave)
+static void spi_cs_deactivate(struct udevice *dev)
{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
- struct spi_regs *regs = spi->ctrl->regs;
+ struct udevice *bus = dev->parent;
+ struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
+ struct tegra30_spi_priv *priv = dev_get_priv(bus);
/* CS is negated on Tegra, so drive a 0 to get a 1 */
- clrbits_le32(®s->command, SLINK_CMD_CS_VAL);
+ clrbits_le32(&priv->regs->command, SLINK_CMD_CS_VAL);
+
+ /* Remember time of this transaction so we can honour the bus delay */
+ if (pdata->deactivate_delay_us)
+ priv->last_transaction_us = timer_get_us();
}
-int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
- const void *data_out, void *data_in, unsigned long flags)
+static int tegra30_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *data_out, void *data_in,
+ unsigned long flags)
{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
- struct spi_regs *regs = spi->ctrl->regs;
+ struct udevice *bus = dev->parent;
+ struct tegra30_spi_priv *priv = dev_get_priv(bus);
+ struct spi_regs *regs = priv->regs;
u32 reg, tmpdout, tmpdin = 0;
const u8 *dout = data_out;
u8 *din = data_in;
int ret;
debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
- __func__, slave->bus, slave->cs, dout, din, bitlen);
+ __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
if (bitlen % 8)
return -1;
num_bytes = bitlen / 8;
clrsetbits_le32(®s->command2, SLINK_CMD2_SS_EN_MASK,
SLINK_CMD2_TXEN | SLINK_CMD2_RXEN |
- (slave->cs << SLINK_CMD2_SS_EN_SHIFT));
+ (spi_chip_select(dev) << SLINK_CMD2_SS_EN_SHIFT));
debug("%s entry: COMMAND2 = %08x\n", __func__, readl(®s->command2));
if (flags & SPI_XFER_BEGIN)
- spi_cs_activate(slave);
+ spi_cs_activate(dev);
/* handle data in 32-bit chunks */
while (num_bytes > 0) {
}
if (flags & SPI_XFER_END)
- spi_cs_deactivate(slave);
+ spi_cs_deactivate(dev);
debug("%s: transfer ended. Value=%08x, status = %08x\n",
__func__, tmpdin, readl(®s->status));
return 0;
}
+
+static int tegra30_spi_set_speed(struct udevice *bus, uint speed)
+{
+ struct tegra_spi_platdata *plat = bus->platdata;
+ struct tegra30_spi_priv *priv = dev_get_priv(bus);
+
+ if (speed > plat->frequency)
+ speed = plat->frequency;
+ priv->freq = speed;
+ debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
+
+ return 0;
+}
+
+static int tegra30_spi_set_mode(struct udevice *bus, uint mode)
+{
+ struct tegra30_spi_priv *priv = dev_get_priv(bus);
+
+ priv->mode = mode;
+ debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
+
+ return 0;
+}
+
+static const struct dm_spi_ops tegra30_spi_ops = {
+ .claim_bus = tegra30_spi_claim_bus,
+ .xfer = tegra30_spi_xfer,
+ .set_speed = tegra30_spi_set_speed,
+ .set_mode = tegra30_spi_set_mode,
+ /*
+ * cs_info is not needed, since we require all chip selects to be
+ * in the device tree explicitly
+ */
+};
+
+static const struct udevice_id tegra30_spi_ids[] = {
+ { .compatible = "nvidia,tegra20-slink" },
+ { }
+};
+
+U_BOOT_DRIVER(tegra30_spi) = {
+ .name = "tegra20_slink",
+ .id = UCLASS_SPI,
+ .of_match = tegra30_spi_ids,
+ .ops = &tegra30_spi_ops,
+ .ofdata_to_platdata = tegra30_spi_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
+ .priv_auto_alloc_size = sizeof(struct tegra30_spi_priv),
+ .per_child_auto_alloc_size = sizeof(struct spi_slave),
+ .probe = tegra30_spi_probe,
+};
--- /dev/null
+/*
+ * (C) Copyright 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+struct tegra_spi_platdata {
+ enum periph_id periph_id;
+ int frequency; /* Default clock frequency, -1 for none */
+ ulong base;
+ uint deactivate_delay_us; /* Delay to wait after deactivate */
+};
BOARD_EXTRA_ENV_SETTINGS
#if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) || defined(CONFIG_TEGRA114_SPI)
-#define CONFIG_FDT_SPI
+#define CONFIG_TEGRA_SPI
#endif
/* overrides for SPL build here */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_DM_SERIAL
#endif
+#define CONFIG_DM_SPI
+#define CONFIG_DM_SPI_FLASH
#define CONFIG_SYS_TIMER_RATE 1000000
#define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE
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