}
debug("PCI regions:\n");
- debug(" I/O: %#x-%#x\n", pcie->io.start, pcie->io.end);
- debug(" non-prefetchable memory: %#x-%#x\n", pcie->mem.start,
- pcie->mem.end);
- debug(" prefetchable memory: %#x-%#x\n", pcie->prefetch.start,
- pcie->prefetch.end);
+ debug(" I/O: %pa-%pa\n", &pcie->io.start, &pcie->io.end);
+ debug(" non-prefetchable memory: %pa-%pa\n", &pcie->mem.start,
+ &pcie->mem.end);
+ debug(" prefetchable memory: %pa-%pa\n", &pcie->prefetch.start,
+ &pcie->prefetch.end);
return 0;
}
plat->speed_hz = fdtdec_get_int(blob,
node, "spi-max-frequency", FSL_DSPI_DEFAULT_SCK_FREQ);
- debug("DSPI: regs=0x%llx, max-frequency=%d, endianess=%s, num-cs=%d\n",
- (u64)plat->regs_addr, plat->speed_hz,
+ debug("DSPI: regs=%pa, max-frequency=%d, endianess=%s, num-cs=%d\n",
+ &plat->regs_addr, plat->speed_hz,
plat->flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le",
plat->num_chipselect);
/* Enable flushing after LCD writes if requested */
lcd_set_flush_dcache(config.cache_type & FDT_LCD_CACHE_FLUSH);
- debug("LCD frame buffer at %08X\n", disp_config->frame_buffer);
+ debug("LCD frame buffer at %pa\n", &disp_config->frame_buffer);
}
ulong calc_fbsize(void)