fix: phy: marvell: cp110: update comphy selector option

Align PHY selectors register with Armada-CP-110 functional SPEC
update all relevant device trees with this change.

Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>

diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts
index c1a0f468d7a3969fed494515aac35fdfc3df7d09..b140b3476e751c94bbe7019549b2d100ef9605fc 100644 (file)
--- a/arch/arm/dts/armada-7040-db.dts
+++ b/arch/arm/dts/armada-7040-db.dts
@@ -159,7 +159,7 @@
 
 &cpm_comphy {
        phy0 {
-               phy-type = <PHY_TYPE_SGMII2>;
+               phy-type = <PHY_TYPE_SGMII1>;
                phy-speed = <PHY_SPEED_1_25G>;
        };
 

diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts
index dde495ae4ffa5cd2643d0e53119d31462eb58207..991ddc0c43b83ba3f8e8ca386ff0fc3b4d32ede5 100644 (file)
--- a/arch/arm/dts/armada-8040-mcbin.dts
+++ b/arch/arm/dts/armada-8040-mcbin.dts
@@ -264,7 +264,7 @@
 &cps_comphy {
        /*
         * CP1 Serdes Configuration:
-        * Lane 0: SGMII2
+        * Lane 0: SGMII1
         * Lane 1: SATA 0
         * Lane 2: USB HOST 0
         * Lane 3: SATA1
@@ -272,7 +272,7 @@
         * Lane 5: SGMII3
         */
        phy0 {
-               phy-type = <PHY_TYPE_SGMII2>;
+               phy-type = <PHY_TYPE_SGMII1>;
                phy-speed = <PHY_SPEED_1_25G>;
        };
        phy1 {

diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c
index a4dddb8bce852278168fe871c8ac3f9e6a17b8bb..6a6083b322be6ce328b3df57e70b1ab7254dc9ed 100644 (file)
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -37,23 +37,20 @@ struct utmi_phy_data {
  * Eth_port_0 that include (SGMII0, XAUI0, RXAUI0, SFI)
  */
 struct comphy_mux_data cp110_comphy_phy_mux_data[] = {
-       {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 0 */
-            {PHY_TYPE_XAUI2, 0x1}, {PHY_TYPE_SATA1, 0x4} } },
-       {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII3, 0x1}, /* Lane 1 */
-            {PHY_TYPE_XAUI3, 0x1}, {PHY_TYPE_SATA0, 0x4} } },
+       {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, /* Lane 0 */
+            {PHY_TYPE_SATA1, 0x4} } },
+       {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 1 */
+            {PHY_TYPE_SATA0, 0x4} } },
        {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */
-            {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1},
-            {PHY_TYPE_SFI, 0x1}, {PHY_TYPE_SATA0, 0x4} } },
-       {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 3 */
-            {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1},
-            {PHY_TYPE_SFI, 0x1}, {PHY_TYPE_XAUI1, 0x1},
-            {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SATA1, 0x4} } },
-       {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */
-            {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x2},
-            {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_XAUI2, 0x1} } },
-       {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_XAUI1, 0x1}, /* Lane 5 */
-            {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SGMII3, 0x1},
-            {PHY_TYPE_XAUI3, 0x1}, {PHY_TYPE_SATA1, 0x4} } },
+            {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x1},
+            {PHY_TYPE_SATA0, 0x4} } },
+       {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, /* Lane 3 */
+            {PHY_TYPE_SGMII1, 0x2}, {PHY_TYPE_SATA1, 0x4} } },
+       {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 4 */
+            {PHY_TYPE_RXAUI0, 0x2}, {PHY_TYPE_SFI, 0x2},
+            {PHY_TYPE_SGMII1, 0x2} } },
+       {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 5 */
+            {PHY_TYPE_RXAUI1, 0x2}, {PHY_TYPE_SATA1, 0x4} } },
 };
 
 struct comphy_mux_data cp110_comphy_pipe_mux_data[] = {