]> git.sur5r.net Git - u-boot/commitdiff
sunxi: clock: Fix OHCI clock gating for H3/H5
authorChen-Yu Tsai <wens@csie.org>
Mon, 7 May 2018 07:33:24 +0000 (13:03 +0530)
committerJagan Teki <jagan@amarulasolutions.com>
Mon, 28 May 2018 11:10:43 +0000 (16:40 +0530)
Clock gating bits on H43/H5 were wrong, fix them.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Jun Nie <jun.nie@linaro.org>
arch/arm/include/asm/arch-sunxi/clock_sun6i.h

index 87d82f205cc02e33db97565a99c31b391a0fba36..8acf79fbba320c3a7bd711f78e275d9e68aae8ca 100644 (file)
@@ -350,13 +350,10 @@ struct sunxi_ccm_reg {
 #define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)
 #define CCM_USB_CTRL_PHY3_CLK (0x1 << 11)
 #ifdef CONFIG_MACH_SUNXI_H3_H5
-/*
- * These are OHCI1 - OHCI3 in the datasheet (OHCI0 is for the OTG) we call
- * them 0 - 2 like they were called on older SoCs.
- */
-#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 17)
-#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 18)
-#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 19)
+#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16)
+#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17)
+#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 18)
+#define CCM_USB_CTRL_OHCI3_CLK (0x1 << 19)
 #else
 #define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16)
 #define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17)