]> git.sur5r.net Git - u-boot/commitdiff
tegra: spi: rename tegra SPI drivers
authorAllen Martin <amartin@nvidia.com>
Sat, 16 Mar 2013 18:58:03 +0000 (18:58 +0000)
committerTom Warren <twarren@nvidia.com>
Mon, 25 Mar 2013 16:56:05 +0000 (09:56 -0700)
Rename tegra SPI drivers to tegra20_flash and tegra20_slink in
preparation for commonization and addition of tegra114_spi.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
12 files changed:
arch/arm/include/asm/arch-tegra/tegra_slink.h [deleted file]
arch/arm/include/asm/arch-tegra/tegra_spi.h [deleted file]
arch/arm/include/asm/arch-tegra20/tegra20_sflash.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra20/tegra20_slink.h [new file with mode: 0644]
board/nvidia/common/board.c
drivers/spi/Makefile
drivers/spi/tegra20_sflash.c [new file with mode: 0644]
drivers/spi/tegra20_slink.c [new file with mode: 0644]
drivers/spi/tegra_slink.c [deleted file]
drivers/spi/tegra_spi.c [deleted file]
include/configs/cardhu.h
include/configs/trimslice.h

diff --git a/arch/arm/include/asm/arch-tegra/tegra_slink.h b/arch/arm/include/asm/arch-tegra/tegra_slink.h
deleted file mode 100644 (file)
index 74804b5..0000000
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * NVIDIA Tegra SPI-SLINK controller
- *
- * Copyright 2010-2013 NVIDIA Corporation
- *
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _TEGRA_SLINK_H_
-#define _TEGRA_SLINK_H_
-
-#include <asm/types.h>
-
-struct slink_tegra {
-       u32 command;    /* SLINK_COMMAND_0 register  */
-       u32 command2;   /* SLINK_COMMAND2_0 reg */
-       u32 status;     /* SLINK_STATUS_0 register */
-       u32 reserved;   /* Reserved offset 0C */
-       u32 mas_data;   /* SLINK_MAS_DATA_0 reg */
-       u32 slav_data;  /* SLINK_SLAVE_DATA_0 reg */
-       u32 dma_ctl;    /* SLINK_DMA_CTL_0 register */
-       u32 status2;    /* SLINK_STATUS2_0 reg */
-       u32 rsvd[56];   /* 0x20 to 0xFF reserved */
-       u32 tx_fifo;    /* SLINK_TX_FIFO_0 reg off 100h */
-       u32 rsvd2[31];  /* 0x104 to 0x17F reserved */
-       u32 rx_fifo;    /* SLINK_RX_FIFO_0 reg off 180h */
-};
-
-/* COMMAND */
-#define SLINK_CMD_ENB                  (1 << 31)
-#define SLINK_CMD_GO                   (1 << 30)
-#define SLINK_CMD_M_S                  (1 << 28)
-#define SLINK_CMD_CK_SDA               (1 << 21)
-#define SLINK_CMD_CS_POL               (1 << 13)
-#define SLINK_CMD_CS_VAL               (1 << 12)
-#define SLINK_CMD_CS_SOFT              (1 << 11)
-#define SLINK_CMD_BIT_LENGTH           (1 << 4)
-#define SLINK_CMD_BIT_LENGTH_MASK      0x0000001F
-/* COMMAND2 */
-#define SLINK_CMD2_TXEN                        (1 << 30)
-#define SLINK_CMD2_RXEN                        (1 << 31)
-#define SLINK_CMD2_SS_EN               (1 << 18)
-#define SLINK_CMD2_SS_EN_SHIFT         18
-#define SLINK_CMD2_SS_EN_MASK          0x000C0000
-#define SLINK_CMD2_CS_ACTIVE_BETWEEN   (1 << 17)
-/* STATUS */
-#define SLINK_STAT_BSY                 (1 << 31)
-#define SLINK_STAT_RDY                 (1 << 30)
-#define SLINK_STAT_ERR                 (1 << 29)
-#define SLINK_STAT_RXF_FLUSH           (1 << 27)
-#define SLINK_STAT_TXF_FLUSH           (1 << 26)
-#define SLINK_STAT_RXF_OVF             (1 << 25)
-#define SLINK_STAT_TXF_UNR             (1 << 24)
-#define SLINK_STAT_RXF_EMPTY           (1 << 23)
-#define SLINK_STAT_RXF_FULL            (1 << 22)
-#define SLINK_STAT_TXF_EMPTY           (1 << 21)
-#define SLINK_STAT_TXF_FULL            (1 << 20)
-#define SLINK_STAT_TXF_OVF             (1 << 19)
-#define SLINK_STAT_RXF_UNR             (1 << 18)
-#define SLINK_STAT_CUR_BLKCNT          (1 << 15)
-/* STATUS2 */
-#define SLINK_STAT2_RXF_FULL_CNT       (1 << 16)
-#define SLINK_STAT2_TXF_FULL_CNT       (1 << 0)
-
-#define SPI_TIMEOUT            1000
-#define TEGRA_SPI_MAX_FREQ     52000000
-
-#endif /* _TEGRA_SLINK_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/tegra_spi.h b/arch/arm/include/asm/arch-tegra/tegra_spi.h
deleted file mode 100644 (file)
index d53a93f..0000000
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * NVIDIA Tegra20 SPI-FLASH controller
- *
- * Copyright 2010-2012 NVIDIA Corporation
- *
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _TEGRA_SPI_H_
-#define _TEGRA_SPI_H_
-
-#include <asm/types.h>
-
-struct spi_tegra {
-       u32 command;    /* SPI_COMMAND_0 register  */
-       u32 status;     /* SPI_STATUS_0 register */
-       u32 rx_cmp;     /* SPI_RX_CMP_0 register  */
-       u32 dma_ctl;    /* SPI_DMA_CTL_0 register */
-       u32 tx_fifo;    /* SPI_TX_FIFO_0 register */
-       u32 rsvd[3];    /* offsets 0x14 to 0x1F reserved */
-       u32 rx_fifo;    /* SPI_RX_FIFO_0 register */
-};
-
-#define SPI_CMD_GO                     (1 << 30)
-#define SPI_CMD_ACTIVE_SCLK_SHIFT      26
-#define SPI_CMD_ACTIVE_SCLK_MASK       (3 << SPI_CMD_ACTIVE_SCLK_SHIFT)
-#define SPI_CMD_CK_SDA                 (1 << 21)
-#define SPI_CMD_ACTIVE_SDA_SHIFT       18
-#define SPI_CMD_ACTIVE_SDA_MASK                (3 << SPI_CMD_ACTIVE_SDA_SHIFT)
-#define SPI_CMD_CS_POL                 (1 << 16)
-#define SPI_CMD_TXEN                   (1 << 15)
-#define SPI_CMD_RXEN                   (1 << 14)
-#define SPI_CMD_CS_VAL                 (1 << 13)
-#define SPI_CMD_CS_SOFT                        (1 << 12)
-#define SPI_CMD_CS_DELAY               (1 << 9)
-#define SPI_CMD_CS3_EN                 (1 << 8)
-#define SPI_CMD_CS2_EN                 (1 << 7)
-#define SPI_CMD_CS1_EN                 (1 << 6)
-#define SPI_CMD_CS0_EN                 (1 << 5)
-#define SPI_CMD_BIT_LENGTH             (1 << 4)
-#define SPI_CMD_BIT_LENGTH_MASK                0x0000001F
-
-#define SPI_STAT_BSY                   (1 << 31)
-#define SPI_STAT_RDY                   (1 << 30)
-#define SPI_STAT_RXF_FLUSH             (1 << 29)
-#define SPI_STAT_TXF_FLUSH             (1 << 28)
-#define SPI_STAT_RXF_UNR               (1 << 27)
-#define SPI_STAT_TXF_OVF               (1 << 26)
-#define SPI_STAT_RXF_EMPTY             (1 << 25)
-#define SPI_STAT_RXF_FULL              (1 << 24)
-#define SPI_STAT_TXF_EMPTY             (1 << 23)
-#define SPI_STAT_TXF_FULL              (1 << 22)
-#define SPI_STAT_SEL_TXRX_N            (1 << 16)
-#define SPI_STAT_CUR_BLKCNT            (1 << 15)
-
-#define SPI_TIMEOUT            1000
-#define TEGRA_SPI_MAX_FREQ     52000000
-
-#endif /* _TEGRA_SPI_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h b/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h
new file mode 100644 (file)
index 0000000..26a8402
--- /dev/null
@@ -0,0 +1,75 @@
+/*
+ * NVIDIA Tegra20 SPI-FLASH controller
+ *
+ * Copyright 2010-2012 NVIDIA Corporation
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA20_SPI_H_
+#define _TEGRA20_SPI_H_
+
+#include <asm/types.h>
+
+struct spi_tegra {
+       u32 command;    /* SPI_COMMAND_0 register  */
+       u32 status;     /* SPI_STATUS_0 register */
+       u32 rx_cmp;     /* SPI_RX_CMP_0 register  */
+       u32 dma_ctl;    /* SPI_DMA_CTL_0 register */
+       u32 tx_fifo;    /* SPI_TX_FIFO_0 register */
+       u32 rsvd[3];    /* offsets 0x14 to 0x1F reserved */
+       u32 rx_fifo;    /* SPI_RX_FIFO_0 register */
+};
+
+#define SPI_CMD_GO                     (1 << 30)
+#define SPI_CMD_ACTIVE_SCLK_SHIFT      26
+#define SPI_CMD_ACTIVE_SCLK_MASK       (3 << SPI_CMD_ACTIVE_SCLK_SHIFT)
+#define SPI_CMD_CK_SDA                 (1 << 21)
+#define SPI_CMD_ACTIVE_SDA_SHIFT       18
+#define SPI_CMD_ACTIVE_SDA_MASK                (3 << SPI_CMD_ACTIVE_SDA_SHIFT)
+#define SPI_CMD_CS_POL                 (1 << 16)
+#define SPI_CMD_TXEN                   (1 << 15)
+#define SPI_CMD_RXEN                   (1 << 14)
+#define SPI_CMD_CS_VAL                 (1 << 13)
+#define SPI_CMD_CS_SOFT                        (1 << 12)
+#define SPI_CMD_CS_DELAY               (1 << 9)
+#define SPI_CMD_CS3_EN                 (1 << 8)
+#define SPI_CMD_CS2_EN                 (1 << 7)
+#define SPI_CMD_CS1_EN                 (1 << 6)
+#define SPI_CMD_CS0_EN                 (1 << 5)
+#define SPI_CMD_BIT_LENGTH             (1 << 4)
+#define SPI_CMD_BIT_LENGTH_MASK                0x0000001F
+
+#define SPI_STAT_BSY                   (1 << 31)
+#define SPI_STAT_RDY                   (1 << 30)
+#define SPI_STAT_RXF_FLUSH             (1 << 29)
+#define SPI_STAT_TXF_FLUSH             (1 << 28)
+#define SPI_STAT_RXF_UNR               (1 << 27)
+#define SPI_STAT_TXF_OVF               (1 << 26)
+#define SPI_STAT_RXF_EMPTY             (1 << 25)
+#define SPI_STAT_RXF_FULL              (1 << 24)
+#define SPI_STAT_TXF_EMPTY             (1 << 23)
+#define SPI_STAT_TXF_FULL              (1 << 22)
+#define SPI_STAT_SEL_TXRX_N            (1 << 16)
+#define SPI_STAT_CUR_BLKCNT            (1 << 15)
+
+#define SPI_TIMEOUT            1000
+#define TEGRA_SPI_MAX_FREQ     52000000
+
+#endif /* _TEGRA20_SPI_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/tegra20_slink.h b/arch/arm/include/asm/arch-tegra20/tegra20_slink.h
new file mode 100644 (file)
index 0000000..afa9b36
--- /dev/null
@@ -0,0 +1,84 @@
+/*
+ * NVIDIA Tegra SPI-SLINK controller
+ *
+ * Copyright 2010-2013 NVIDIA Corporation
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA30_SPI_H_
+#define _TEGRA30_SPI_H_
+
+#include <asm/types.h>
+
+struct slink_tegra {
+       u32 command;    /* SLINK_COMMAND_0 register  */
+       u32 command2;   /* SLINK_COMMAND2_0 reg */
+       u32 status;     /* SLINK_STATUS_0 register */
+       u32 reserved;   /* Reserved offset 0C */
+       u32 mas_data;   /* SLINK_MAS_DATA_0 reg */
+       u32 slav_data;  /* SLINK_SLAVE_DATA_0 reg */
+       u32 dma_ctl;    /* SLINK_DMA_CTL_0 register */
+       u32 status2;    /* SLINK_STATUS2_0 reg */
+       u32 rsvd[56];   /* 0x20 to 0xFF reserved */
+       u32 tx_fifo;    /* SLINK_TX_FIFO_0 reg off 100h */
+       u32 rsvd2[31];  /* 0x104 to 0x17F reserved */
+       u32 rx_fifo;    /* SLINK_RX_FIFO_0 reg off 180h */
+};
+
+/* COMMAND */
+#define SLINK_CMD_ENB                  (1 << 31)
+#define SLINK_CMD_GO                   (1 << 30)
+#define SLINK_CMD_M_S                  (1 << 28)
+#define SLINK_CMD_CK_SDA               (1 << 21)
+#define SLINK_CMD_CS_POL               (1 << 13)
+#define SLINK_CMD_CS_VAL               (1 << 12)
+#define SLINK_CMD_CS_SOFT              (1 << 11)
+#define SLINK_CMD_BIT_LENGTH           (1 << 4)
+#define SLINK_CMD_BIT_LENGTH_MASK      0x0000001F
+/* COMMAND2 */
+#define SLINK_CMD2_TXEN                        (1 << 30)
+#define SLINK_CMD2_RXEN                        (1 << 31)
+#define SLINK_CMD2_SS_EN               (1 << 18)
+#define SLINK_CMD2_SS_EN_SHIFT         18
+#define SLINK_CMD2_SS_EN_MASK          0x000C0000
+#define SLINK_CMD2_CS_ACTIVE_BETWEEN   (1 << 17)
+/* STATUS */
+#define SLINK_STAT_BSY                 (1 << 31)
+#define SLINK_STAT_RDY                 (1 << 30)
+#define SLINK_STAT_ERR                 (1 << 29)
+#define SLINK_STAT_RXF_FLUSH           (1 << 27)
+#define SLINK_STAT_TXF_FLUSH           (1 << 26)
+#define SLINK_STAT_RXF_OVF             (1 << 25)
+#define SLINK_STAT_TXF_UNR             (1 << 24)
+#define SLINK_STAT_RXF_EMPTY           (1 << 23)
+#define SLINK_STAT_RXF_FULL            (1 << 22)
+#define SLINK_STAT_TXF_EMPTY           (1 << 21)
+#define SLINK_STAT_TXF_FULL            (1 << 20)
+#define SLINK_STAT_TXF_OVF             (1 << 19)
+#define SLINK_STAT_RXF_UNR             (1 << 18)
+#define SLINK_STAT_CUR_BLKCNT          (1 << 15)
+/* STATUS2 */
+#define SLINK_STAT2_RXF_FULL_CNT       (1 << 16)
+#define SLINK_STAT2_TXF_FULL_CNT       (1 << 0)
+
+#define SPI_TIMEOUT            1000
+#define TEGRA_SPI_MAX_FREQ     52000000
+
+#endif /* _TEGRA30_SPI_H_ */
index b6e6566685d4d687e4ffff6f9e8431160d4bc515..87a418bc6a34b49c3435e5b1baac007aecf4ebad 100644 (file)
@@ -132,7 +132,7 @@ int board_init(void)
        clock_init();
        clock_verify();
 
-#if defined(CONFIG_TEGRA_SPI) || defined(CONFIG_TEGRA_SLINK)
+#if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK)
        pin_mux_spi();
        spi_init();
 #endif
index b8264df3a9b34cac227461d6563c4dadcfc0cdb8..78e3d3d5683220481816469738ca25edb9d81916 100644 (file)
@@ -46,8 +46,8 @@ COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
 COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
 COBJS-$(CONFIG_SH_SPI) += sh_spi.o
 COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
-COBJS-$(CONFIG_TEGRA_SPI) += tegra_spi.o
-COBJS-$(CONFIG_TEGRA_SLINK) += tegra_slink.o
+COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
+COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
 COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
 
 COBJS  := $(COBJS-y)
diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c
new file mode 100644 (file)
index 0000000..c6af30f
--- /dev/null
@@ -0,0 +1,307 @@
+/*
+ * Copyright (c) 2010-2012 NVIDIA Corporation
+ * With help from the mpc8xxx SPI driver
+ * With more help from omap3_spi SPI driver
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra20/tegra20_sflash.h>
+#include <spi.h>
+#include <fdtdec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct tegra_spi_slave {
+       struct spi_slave slave;
+       struct spi_tegra *regs;
+       unsigned int freq;
+       unsigned int mode;
+       int periph_id;
+};
+
+static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
+{
+       return container_of(slave, struct tegra_spi_slave, slave);
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+       /* Tegra20 SPI-Flash - only 1 device ('bus/cs') */
+       if (bus != 0 || cs != 0)
+               return 0;
+       else
+               return 1;
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+               unsigned int max_hz, unsigned int mode)
+{
+       struct tegra_spi_slave *spi;
+
+       if (!spi_cs_is_valid(bus, cs)) {
+               printf("SPI error: unsupported bus %d / chip select %d\n",
+                      bus, cs);
+               return NULL;
+       }
+
+       if (max_hz > TEGRA_SPI_MAX_FREQ) {
+               printf("SPI error: unsupported frequency %d Hz. Max frequency"
+                       " is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
+               return NULL;
+       }
+
+       spi = malloc(sizeof(struct tegra_spi_slave));
+       if (!spi) {
+               printf("SPI error: malloc of SPI structure failed\n");
+               return NULL;
+       }
+       spi->slave.bus = bus;
+       spi->slave.cs = cs;
+#ifdef CONFIG_OF_CONTROL
+       int node = fdtdec_next_compatible(gd->fdt_blob, 0,
+                                         COMPAT_NVIDIA_TEGRA20_SFLASH);
+       if (node < 0) {
+               debug("%s: cannot locate sflash node\n", __func__);
+               return NULL;
+       }
+       if (!fdtdec_get_is_enabled(gd->fdt_blob, node)) {
+               debug("%s: sflash is disabled\n", __func__);
+               return NULL;
+       }
+       spi->regs = (struct spi_tegra *)fdtdec_get_addr(gd->fdt_blob,
+                                                       node, "reg");
+       if ((fdt_addr_t)spi->regs == FDT_ADDR_T_NONE) {
+               debug("%s: no sflash register found\n", __func__);
+               return NULL;
+       }
+       spi->freq = fdtdec_get_int(gd->fdt_blob, node, "spi-max-frequency", 0);
+       if (!spi->freq) {
+               debug("%s: no sflash max frequency found\n", __func__);
+               return NULL;
+       }
+       spi->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
+       if (spi->periph_id == PERIPH_ID_NONE) {
+               debug("%s: could not decode periph id\n", __func__);
+               return NULL;
+       }
+#else
+       spi->regs = (struct spi_tegra *)NV_PA_SPI_BASE;
+       spi->freq = TEGRA_SPI_MAX_FREQ;
+       spi->periph_id = PERIPH_ID_SPI1;
+#endif
+       if (max_hz < spi->freq) {
+               debug("%s: limiting frequency from %u to %u\n", __func__,
+                     spi->freq, max_hz);
+               spi->freq = max_hz;
+       }
+       debug("%s: controller initialized at %p, freq = %u, periph_id = %d\n",
+             __func__, spi->regs, spi->freq, spi->periph_id);
+       spi->mode = mode;
+
+       return &spi->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+       struct tegra_spi_slave *spi = to_tegra_spi(slave);
+
+       free(spi);
+}
+
+void spi_init(void)
+{
+       /* do nothing */
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+       struct tegra_spi_slave *spi = to_tegra_spi(slave);
+       struct spi_tegra *regs = spi->regs;
+       u32 reg;
+
+       /* Change SPI clock to correct frequency, PLLP_OUT0 source */
+       clock_start_periph_pll(spi->periph_id, CLOCK_ID_PERIPH, spi->freq);
+
+       /* Clear stale status here */
+       reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
+               SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF;
+       writel(reg, &regs->status);
+       debug("spi_init: STATUS = %08x\n", readl(&regs->status));
+
+       /*
+        * Use sw-controlled CS, so we can clock in data after ReadID, etc.
+        */
+       reg = (spi->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT;
+       if (spi->mode & 2)
+               reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT;
+       clrsetbits_le32(&regs->command, SPI_CMD_ACTIVE_SCLK_MASK |
+               SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg);
+       debug("spi_init: COMMAND = %08x\n", readl(&regs->command));
+
+       /*
+        * SPI pins on Tegra20 are muxed - change pinmux later due to UART
+        * issue.
+        */
+       pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH);
+       pinmux_tristate_disable(PINGRP_LSPI);
+       pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH);
+
+       return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+       /*
+        * We can't release UART_DISABLE and set pinmux to UART4 here since
+        * some code (e,g, spi_flash_probe) uses printf() while the SPI
+        * bus is held. That is arguably bad, but it has the advantage of
+        * already being in the source tree.
+        */
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+       struct tegra_spi_slave *spi = to_tegra_spi(slave);
+
+       /* CS is negated on Tegra, so drive a 1 to get a 0 */
+       setbits_le32(&spi->regs->command, SPI_CMD_CS_VAL);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+       struct tegra_spi_slave *spi = to_tegra_spi(slave);
+
+       /* CS is negated on Tegra, so drive a 0 to get a 1 */
+       clrbits_le32(&spi->regs->command, SPI_CMD_CS_VAL);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+               const void *data_out, void *data_in, unsigned long flags)
+{
+       struct tegra_spi_slave *spi = to_tegra_spi(slave);
+       struct spi_tegra *regs = spi->regs;
+       u32 reg, tmpdout, tmpdin = 0;
+       const u8 *dout = data_out;
+       u8 *din = data_in;
+       int num_bytes;
+       int ret;
+
+       debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
+             slave->bus, slave->cs, *(u8 *)dout, *(u8 *)din, bitlen);
+       if (bitlen % 8)
+               return -1;
+       num_bytes = bitlen / 8;
+
+       ret = 0;
+
+       reg = readl(&regs->status);
+       writel(reg, &regs->status);     /* Clear all SPI events via R/W */
+       debug("spi_xfer entry: STATUS = %08x\n", reg);
+
+       reg = readl(&regs->command);
+       reg |= SPI_CMD_TXEN | SPI_CMD_RXEN;
+       writel(reg, &regs->command);
+       debug("spi_xfer: COMMAND = %08x\n", readl(&regs->command));
+
+       if (flags & SPI_XFER_BEGIN)
+               spi_cs_activate(slave);
+
+       /* handle data in 32-bit chunks */
+       while (num_bytes > 0) {
+               int bytes;
+               int is_read = 0;
+               int tm, i;
+
+               tmpdout = 0;
+               bytes = (num_bytes > 4) ?  4 : num_bytes;
+
+               if (dout != NULL) {
+                       for (i = 0; i < bytes; ++i)
+                               tmpdout = (tmpdout << 8) | dout[i];
+               }
+
+               num_bytes -= bytes;
+               if (dout)
+                       dout += bytes;
+
+               clrsetbits_le32(&regs->command, SPI_CMD_BIT_LENGTH_MASK,
+                               bytes * 8 - 1);
+               writel(tmpdout, &regs->tx_fifo);
+               setbits_le32(&regs->command, SPI_CMD_GO);
+
+               /*
+                * Wait for SPI transmit FIFO to empty, or to time out.
+                * The RX FIFO status will be read and cleared last
+                */
+               for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
+                       u32 status;
+
+                       status = readl(&regs->status);
+
+                       /* We can exit when we've had both RX and TX activity */
+                       if (is_read && (status & SPI_STAT_TXF_EMPTY))
+                               break;
+
+                       if ((status & (SPI_STAT_BSY | SPI_STAT_RDY)) !=
+                                       SPI_STAT_RDY)
+                               tm++;
+
+                       else if (!(status & SPI_STAT_RXF_EMPTY)) {
+                               tmpdin = readl(&regs->rx_fifo);
+                               is_read = 1;
+
+                               /* swap bytes read in */
+                               if (din != NULL) {
+                                       for (i = bytes - 1; i >= 0; --i) {
+                                               din[i] = tmpdin & 0xff;
+                                               tmpdin >>= 8;
+                                       }
+                                       din += bytes;
+                               }
+                       }
+               }
+
+               if (tm >= SPI_TIMEOUT)
+                       ret = tm;
+
+               /* clear ACK RDY, etc. bits */
+               writel(readl(&regs->status), &regs->status);
+       }
+
+       if (flags & SPI_XFER_END)
+               spi_cs_deactivate(slave);
+
+       debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n",
+               tmpdin, readl(&regs->status));
+
+       if (ret) {
+               printf("spi_xfer: timeout during SPI transfer, tm %d\n", ret);
+               return -1;
+       }
+
+       return 0;
+}
diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c
new file mode 100644 (file)
index 0000000..a6de4ce
--- /dev/null
@@ -0,0 +1,343 @@
+/*
+ * NVIDIA Tegra SPI-SLINK controller
+ *
+ * Copyright (c) 2010-2013 NVIDIA Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra20/tegra20_slink.h>
+#include <spi.h>
+#include <fdtdec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct tegra_spi_ctrl {
+       struct slink_tegra *regs;
+       unsigned int freq;
+       unsigned int mode;
+       int periph_id;
+       int valid;
+};
+
+struct tegra_spi_slave {
+       struct spi_slave slave;
+       struct tegra_spi_ctrl *ctrl;
+};
+
+static struct tegra_spi_ctrl spi_ctrls[CONFIG_TEGRA_SLINK_CTRLS];
+
+static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
+{
+       return container_of(slave, struct tegra_spi_slave, slave);
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+       if (bus >= CONFIG_TEGRA_SLINK_CTRLS || cs > 3 || !spi_ctrls[bus].valid)
+               return 0;
+       else
+               return 1;
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+               unsigned int max_hz, unsigned int mode)
+{
+       struct tegra_spi_slave *spi;
+
+       debug("%s: bus: %u, cs: %u, max_hz: %u, mode: %u\n", __func__,
+               bus, cs, max_hz, mode);
+
+       if (!spi_cs_is_valid(bus, cs)) {
+               printf("SPI error: unsupported bus %d / chip select %d\n",
+                      bus, cs);
+               return NULL;
+       }
+
+       if (max_hz > TEGRA_SPI_MAX_FREQ) {
+               printf("SPI error: unsupported frequency %d Hz. Max frequency"
+                       " is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
+               return NULL;
+       }
+
+       spi = malloc(sizeof(struct tegra_spi_slave));
+       if (!spi) {
+               printf("SPI error: malloc of SPI structure failed\n");
+               return NULL;
+       }
+       spi->slave.bus = bus;
+       spi->slave.cs = cs;
+       spi->ctrl = &spi_ctrls[bus];
+       if (!spi->ctrl) {
+               printf("SPI error: could not find controller for bus %d\n",
+                      bus);
+               return NULL;
+       }
+
+       if (max_hz < spi->ctrl->freq) {
+               debug("%s: limiting frequency from %u to %u\n", __func__,
+                     spi->ctrl->freq, max_hz);
+               spi->ctrl->freq = max_hz;
+       }
+       spi->ctrl->mode = mode;
+
+       return &spi->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+       struct tegra_spi_slave *spi = to_tegra_spi(slave);
+
+       free(spi);
+}
+
+void spi_init(void)
+{
+       struct tegra_spi_ctrl *ctrl;
+       int i;
+#ifdef CONFIG_OF_CONTROL
+       int node = 0;
+       int count;
+       int node_list[CONFIG_TEGRA_SLINK_CTRLS];
+
+       count = fdtdec_find_aliases_for_id(gd->fdt_blob, "spi",
+                                          COMPAT_NVIDIA_TEGRA20_SLINK,
+                                          node_list,
+                                          CONFIG_TEGRA_SLINK_CTRLS);
+       for (i = 0; i < count; i++) {
+               ctrl = &spi_ctrls[i];
+               node = node_list[i];
+
+               ctrl->regs = (struct slink_tegra *)fdtdec_get_addr(gd->fdt_blob,
+                                                                  node, "reg");
+               if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) {
+                       debug("%s: no slink register found\n", __func__);
+                       continue;
+               }
+               ctrl->freq = fdtdec_get_int(gd->fdt_blob, node,
+                                           "spi-max-frequency", 0);
+               if (!ctrl->freq) {
+                       debug("%s: no slink max frequency found\n", __func__);
+                       continue;
+               }
+
+               ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
+               if (ctrl->periph_id == PERIPH_ID_NONE) {
+                       debug("%s: could not decode periph id\n", __func__);
+                       continue;
+               }
+               ctrl->valid = 1;
+
+               debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
+                     __func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
+       }
+#else
+       for (i = 0; i < CONFIG_TEGRA_SLINK_CTRLS; i++) {
+               ctrl = &spi_ctrls[i];
+               u32 base_regs[] = {
+                       NV_PA_SLINK1_BASE,
+                       NV_PA_SLINK2_BASE,
+                       NV_PA_SLINK3_BASE,
+                       NV_PA_SLINK4_BASE,
+                       NV_PA_SLINK5_BASE,
+                       NV_PA_SLINK6_BASE,
+               };
+               int periph_ids[] = {
+                       PERIPH_ID_SBC1,
+                       PERIPH_ID_SBC2,
+                       PERIPH_ID_SBC3,
+                       PERIPH_ID_SBC4,
+                       PERIPH_ID_SBC5,
+                       PERIPH_ID_SBC6,
+               };
+               ctrl->regs = (struct slink_tegra *)base_regs[i];
+               ctrl->freq = TEGRA_SPI_MAX_FREQ;
+               ctrl->periph_id = periph_ids[i];
+               ctrl->valid = 1;
+
+               debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
+                     __func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
+       }
+#endif
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+       struct tegra_spi_slave *spi = to_tegra_spi(slave);
+       struct slink_tegra *regs = spi->ctrl->regs;
+       u32 reg;
+
+       /* Change SPI clock to correct frequency, PLLP_OUT0 source */
+       clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH,
+                              spi->ctrl->freq);
+
+       /* Clear stale status here */
+       reg = SLINK_STAT_RDY | SLINK_STAT_RXF_FLUSH | SLINK_STAT_TXF_FLUSH | \
+               SLINK_STAT_RXF_UNR | SLINK_STAT_TXF_OVF;
+       writel(reg, &regs->status);
+       debug("%s: STATUS = %08x\n", __func__, readl(&regs->status));
+
+       /* Set master mode and sw controlled CS */
+       reg = readl(&regs->command);
+       reg |= SLINK_CMD_M_S | SLINK_CMD_CS_SOFT;
+       writel(reg, &regs->command);
+       debug("%s: COMMAND = %08x\n", __func__, readl(&regs->command));
+
+       return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+       struct tegra_spi_slave *spi = to_tegra_spi(slave);
+       struct slink_tegra *regs = spi->ctrl->regs;
+
+       /* CS is negated on Tegra, so drive a 1 to get a 0 */
+       setbits_le32(&regs->command, SLINK_CMD_CS_VAL);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+       struct tegra_spi_slave *spi = to_tegra_spi(slave);
+       struct slink_tegra *regs = spi->ctrl->regs;
+
+       /* CS is negated on Tegra, so drive a 0 to get a 1 */
+       clrbits_le32(&regs->command, SLINK_CMD_CS_VAL);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+               const void *data_out, void *data_in, unsigned long flags)
+{
+       struct tegra_spi_slave *spi = to_tegra_spi(slave);
+       struct slink_tegra *regs = spi->ctrl->regs;
+       u32 reg, tmpdout, tmpdin = 0;
+       const u8 *dout = data_out;
+       u8 *din = data_in;
+       int num_bytes;
+       int ret;
+
+       debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
+             __func__, slave->bus, slave->cs, dout, din, bitlen);
+       if (bitlen % 8)
+               return -1;
+       num_bytes = bitlen / 8;
+
+       ret = 0;
+
+       reg = readl(&regs->status);
+       writel(reg, &regs->status);     /* Clear all SPI events via R/W */
+       debug("%s entry: STATUS = %08x\n", __func__, reg);
+
+       reg = readl(&regs->status2);
+       writel(reg, &regs->status2);    /* Clear all STATUS2 events via R/W */
+       debug("%s entry: STATUS2 = %08x\n", __func__, reg);
+
+       debug("%s entry: COMMAND = %08x\n", __func__, readl(&regs->command));
+
+       clrsetbits_le32(&regs->command2, SLINK_CMD2_SS_EN_MASK,
+                       SLINK_CMD2_TXEN | SLINK_CMD2_RXEN |
+                       (slave->cs << SLINK_CMD2_SS_EN_SHIFT));
+       debug("%s entry: COMMAND2 = %08x\n", __func__, readl(&regs->command2));
+
+       if (flags & SPI_XFER_BEGIN)
+               spi_cs_activate(slave);
+
+       /* handle data in 32-bit chunks */
+       while (num_bytes > 0) {
+               int bytes;
+               int is_read = 0;
+               int tm, i;
+
+               tmpdout = 0;
+               bytes = (num_bytes > 4) ?  4 : num_bytes;
+
+               if (dout != NULL) {
+                       for (i = 0; i < bytes; ++i)
+                               tmpdout = (tmpdout << 8) | dout[i];
+                       dout += bytes;
+               }
+
+               num_bytes -= bytes;
+
+               clrsetbits_le32(&regs->command, SLINK_CMD_BIT_LENGTH_MASK,
+                               bytes * 8 - 1);
+               writel(tmpdout, &regs->tx_fifo);
+               setbits_le32(&regs->command, SLINK_CMD_GO);
+
+               /*
+                * Wait for SPI transmit FIFO to empty, or to time out.
+                * The RX FIFO status will be read and cleared last
+                */
+               for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
+                       u32 status;
+
+                       status = readl(&regs->status);
+
+                       /* We can exit when we've had both RX and TX activity */
+                       if (is_read && (status & SLINK_STAT_TXF_EMPTY))
+                               break;
+
+                       if ((status & (SLINK_STAT_BSY | SLINK_STAT_RDY)) !=
+                                       SLINK_STAT_RDY)
+                               tm++;
+
+                       else if (!(status & SLINK_STAT_RXF_EMPTY)) {
+                               tmpdin = readl(&regs->rx_fifo);
+                               is_read = 1;
+
+                               /* swap bytes read in */
+                               if (din != NULL) {
+                                       for (i = bytes - 1; i >= 0; --i) {
+                                               din[i] = tmpdin & 0xff;
+                                               tmpdin >>= 8;
+                                       }
+                                       din += bytes;
+                               }
+                       }
+               }
+
+               if (tm >= SPI_TIMEOUT)
+                       ret = tm;
+
+               /* clear ACK RDY, etc. bits */
+               writel(readl(&regs->status), &regs->status);
+       }
+
+       if (flags & SPI_XFER_END)
+               spi_cs_deactivate(slave);
+
+       debug("%s: transfer ended. Value=%08x, status = %08x\n",
+             __func__, tmpdin, readl(&regs->status));
+
+       if (ret) {
+               printf("%s: timeout during SPI transfer, tm %d\n",
+                      __func__, ret);
+               return -1;
+       }
+
+       return 0;
+}
diff --git a/drivers/spi/tegra_slink.c b/drivers/spi/tegra_slink.c
deleted file mode 100644 (file)
index 2c41fab..0000000
+++ /dev/null
@@ -1,343 +0,0 @@
-/*
- * NVIDIA Tegra SPI-SLINK controller
- *
- * Copyright (c) 2010-2013 NVIDIA Corporation
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <asm/io.h>
-#include <asm/gpio.h>
-#include <asm/arch/clock.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/tegra_slink.h>
-#include <spi.h>
-#include <fdtdec.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct tegra_spi_ctrl {
-       struct slink_tegra *regs;
-       unsigned int freq;
-       unsigned int mode;
-       int periph_id;
-       int valid;
-};
-
-struct tegra_spi_slave {
-       struct spi_slave slave;
-       struct tegra_spi_ctrl *ctrl;
-};
-
-static struct tegra_spi_ctrl spi_ctrls[CONFIG_TEGRA_SLINK_CTRLS];
-
-static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
-{
-       return container_of(slave, struct tegra_spi_slave, slave);
-}
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-       if (bus >= CONFIG_TEGRA_SLINK_CTRLS || cs > 3 || !spi_ctrls[bus].valid)
-               return 0;
-       else
-               return 1;
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
-               unsigned int max_hz, unsigned int mode)
-{
-       struct tegra_spi_slave *spi;
-
-       debug("%s: bus: %u, cs: %u, max_hz: %u, mode: %u\n", __func__,
-               bus, cs, max_hz, mode);
-
-       if (!spi_cs_is_valid(bus, cs)) {
-               printf("SPI error: unsupported bus %d / chip select %d\n",
-                      bus, cs);
-               return NULL;
-       }
-
-       if (max_hz > TEGRA_SPI_MAX_FREQ) {
-               printf("SPI error: unsupported frequency %d Hz. Max frequency"
-                       " is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
-               return NULL;
-       }
-
-       spi = malloc(sizeof(struct tegra_spi_slave));
-       if (!spi) {
-               printf("SPI error: malloc of SPI structure failed\n");
-               return NULL;
-       }
-       spi->slave.bus = bus;
-       spi->slave.cs = cs;
-       spi->ctrl = &spi_ctrls[bus];
-       if (!spi->ctrl) {
-               printf("SPI error: could not find controller for bus %d\n",
-                      bus);
-               return NULL;
-       }
-
-       if (max_hz < spi->ctrl->freq) {
-               debug("%s: limiting frequency from %u to %u\n", __func__,
-                     spi->ctrl->freq, max_hz);
-               spi->ctrl->freq = max_hz;
-       }
-       spi->ctrl->mode = mode;
-
-       return &spi->slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
-       struct tegra_spi_slave *spi = to_tegra_spi(slave);
-
-       free(spi);
-}
-
-void spi_init(void)
-{
-       struct tegra_spi_ctrl *ctrl;
-       int i;
-#ifdef CONFIG_OF_CONTROL
-       int node = 0;
-       int count;
-       int node_list[CONFIG_TEGRA_SLINK_CTRLS];
-
-       count = fdtdec_find_aliases_for_id(gd->fdt_blob, "spi",
-                                          COMPAT_NVIDIA_TEGRA20_SLINK,
-                                          node_list,
-                                          CONFIG_TEGRA_SLINK_CTRLS);
-       for (i = 0; i < count; i++) {
-               ctrl = &spi_ctrls[i];
-               node = node_list[i];
-
-               ctrl->regs = (struct slink_tegra *)fdtdec_get_addr(gd->fdt_blob,
-                                                                  node, "reg");
-               if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) {
-                       debug("%s: no slink register found\n", __func__);
-                       continue;
-               }
-               ctrl->freq = fdtdec_get_int(gd->fdt_blob, node,
-                                           "spi-max-frequency", 0);
-               if (!ctrl->freq) {
-                       debug("%s: no slink max frequency found\n", __func__);
-                       continue;
-               }
-
-               ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
-               if (ctrl->periph_id == PERIPH_ID_NONE) {
-                       debug("%s: could not decode periph id\n", __func__);
-                       continue;
-               }
-               ctrl->valid = 1;
-
-               debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
-                     __func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
-       }
-#else
-       for (i = 0; i < CONFIG_TEGRA_SLINK_CTRLS; i++) {
-               ctrl = &spi_ctrls[i];
-               u32 base_regs[] = {
-                       NV_PA_SLINK1_BASE,
-                       NV_PA_SLINK2_BASE,
-                       NV_PA_SLINK3_BASE,
-                       NV_PA_SLINK4_BASE,
-                       NV_PA_SLINK5_BASE,
-                       NV_PA_SLINK6_BASE,
-               };
-               int periph_ids[] = {
-                       PERIPH_ID_SBC1,
-                       PERIPH_ID_SBC2,
-                       PERIPH_ID_SBC3,
-                       PERIPH_ID_SBC4,
-                       PERIPH_ID_SBC5,
-                       PERIPH_ID_SBC6,
-               };
-               ctrl->regs = (struct slink_tegra *)base_regs[i];
-               ctrl->freq = TEGRA_SPI_MAX_FREQ;
-               ctrl->periph_id = periph_ids[i];
-               ctrl->valid = 1;
-
-               debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
-                     __func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
-       }
-#endif
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
-       struct tegra_spi_slave *spi = to_tegra_spi(slave);
-       struct slink_tegra *regs = spi->ctrl->regs;
-       u32 reg;
-
-       /* Change SPI clock to correct frequency, PLLP_OUT0 source */
-       clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH,
-                              spi->ctrl->freq);
-
-       /* Clear stale status here */
-       reg = SLINK_STAT_RDY | SLINK_STAT_RXF_FLUSH | SLINK_STAT_TXF_FLUSH | \
-               SLINK_STAT_RXF_UNR | SLINK_STAT_TXF_OVF;
-       writel(reg, &regs->status);
-       debug("%s: STATUS = %08x\n", __func__, readl(&regs->status));
-
-       /* Set master mode and sw controlled CS */
-       reg = readl(&regs->command);
-       reg |= SLINK_CMD_M_S | SLINK_CMD_CS_SOFT;
-       writel(reg, &regs->command);
-       debug("%s: COMMAND = %08x\n", __func__, readl(&regs->command));
-
-       return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-       struct tegra_spi_slave *spi = to_tegra_spi(slave);
-       struct slink_tegra *regs = spi->ctrl->regs;
-
-       /* CS is negated on Tegra, so drive a 1 to get a 0 */
-       setbits_le32(&regs->command, SLINK_CMD_CS_VAL);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-       struct tegra_spi_slave *spi = to_tegra_spi(slave);
-       struct slink_tegra *regs = spi->ctrl->regs;
-
-       /* CS is negated on Tegra, so drive a 0 to get a 1 */
-       clrbits_le32(&regs->command, SLINK_CMD_CS_VAL);
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
-               const void *data_out, void *data_in, unsigned long flags)
-{
-       struct tegra_spi_slave *spi = to_tegra_spi(slave);
-       struct slink_tegra *regs = spi->ctrl->regs;
-       u32 reg, tmpdout, tmpdin = 0;
-       const u8 *dout = data_out;
-       u8 *din = data_in;
-       int num_bytes;
-       int ret;
-
-       debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
-             __func__, slave->bus, slave->cs, dout, din, bitlen);
-       if (bitlen % 8)
-               return -1;
-       num_bytes = bitlen / 8;
-
-       ret = 0;
-
-       reg = readl(&regs->status);
-       writel(reg, &regs->status);     /* Clear all SPI events via R/W */
-       debug("%s entry: STATUS = %08x\n", __func__, reg);
-
-       reg = readl(&regs->status2);
-       writel(reg, &regs->status2);    /* Clear all STATUS2 events via R/W */
-       debug("%s entry: STATUS2 = %08x\n", __func__, reg);
-
-       debug("%s entry: COMMAND = %08x\n", __func__, readl(&regs->command));
-
-       clrsetbits_le32(&regs->command2, SLINK_CMD2_SS_EN_MASK,
-                       SLINK_CMD2_TXEN | SLINK_CMD2_RXEN |
-                       (slave->cs << SLINK_CMD2_SS_EN_SHIFT));
-       debug("%s entry: COMMAND2 = %08x\n", __func__, readl(&regs->command2));
-
-       if (flags & SPI_XFER_BEGIN)
-               spi_cs_activate(slave);
-
-       /* handle data in 32-bit chunks */
-       while (num_bytes > 0) {
-               int bytes;
-               int is_read = 0;
-               int tm, i;
-
-               tmpdout = 0;
-               bytes = (num_bytes > 4) ?  4 : num_bytes;
-
-               if (dout != NULL) {
-                       for (i = 0; i < bytes; ++i)
-                               tmpdout = (tmpdout << 8) | dout[i];
-                       dout += bytes;
-               }
-
-               num_bytes -= bytes;
-
-               clrsetbits_le32(&regs->command, SLINK_CMD_BIT_LENGTH_MASK,
-                               bytes * 8 - 1);
-               writel(tmpdout, &regs->tx_fifo);
-               setbits_le32(&regs->command, SLINK_CMD_GO);
-
-               /*
-                * Wait for SPI transmit FIFO to empty, or to time out.
-                * The RX FIFO status will be read and cleared last
-                */
-               for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
-                       u32 status;
-
-                       status = readl(&regs->status);
-
-                       /* We can exit when we've had both RX and TX activity */
-                       if (is_read && (status & SLINK_STAT_TXF_EMPTY))
-                               break;
-
-                       if ((status & (SLINK_STAT_BSY | SLINK_STAT_RDY)) !=
-                                       SLINK_STAT_RDY)
-                               tm++;
-
-                       else if (!(status & SLINK_STAT_RXF_EMPTY)) {
-                               tmpdin = readl(&regs->rx_fifo);
-                               is_read = 1;
-
-                               /* swap bytes read in */
-                               if (din != NULL) {
-                                       for (i = bytes - 1; i >= 0; --i) {
-                                               din[i] = tmpdin & 0xff;
-                                               tmpdin >>= 8;
-                                       }
-                                       din += bytes;
-                               }
-                       }
-               }
-
-               if (tm >= SPI_TIMEOUT)
-                       ret = tm;
-
-               /* clear ACK RDY, etc. bits */
-               writel(readl(&regs->status), &regs->status);
-       }
-
-       if (flags & SPI_XFER_END)
-               spi_cs_deactivate(slave);
-
-       debug("%s: transfer ended. Value=%08x, status = %08x\n",
-             __func__, tmpdin, readl(&regs->status));
-
-       if (ret) {
-               printf("%s: timeout during SPI transfer, tm %d\n",
-                      __func__, ret);
-               return -1;
-       }
-
-       return 0;
-}
diff --git a/drivers/spi/tegra_spi.c b/drivers/spi/tegra_spi.c
deleted file mode 100644 (file)
index 2662923..0000000
+++ /dev/null
@@ -1,307 +0,0 @@
-/*
- * Copyright (c) 2010-2012 NVIDIA Corporation
- * With help from the mpc8xxx SPI driver
- * With more help from omap3_spi SPI driver
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <asm/io.h>
-#include <asm/gpio.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/tegra_spi.h>
-#include <spi.h>
-#include <fdtdec.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct tegra_spi_slave {
-       struct spi_slave slave;
-       struct spi_tegra *regs;
-       unsigned int freq;
-       unsigned int mode;
-       int periph_id;
-};
-
-static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
-{
-       return container_of(slave, struct tegra_spi_slave, slave);
-}
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-       /* Tegra20 SPI-Flash - only 1 device ('bus/cs') */
-       if (bus != 0 || cs != 0)
-               return 0;
-       else
-               return 1;
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
-               unsigned int max_hz, unsigned int mode)
-{
-       struct tegra_spi_slave *spi;
-
-       if (!spi_cs_is_valid(bus, cs)) {
-               printf("SPI error: unsupported bus %d / chip select %d\n",
-                      bus, cs);
-               return NULL;
-       }
-
-       if (max_hz > TEGRA_SPI_MAX_FREQ) {
-               printf("SPI error: unsupported frequency %d Hz. Max frequency"
-                       " is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
-               return NULL;
-       }
-
-       spi = malloc(sizeof(struct tegra_spi_slave));
-       if (!spi) {
-               printf("SPI error: malloc of SPI structure failed\n");
-               return NULL;
-       }
-       spi->slave.bus = bus;
-       spi->slave.cs = cs;
-#ifdef CONFIG_OF_CONTROL
-       int node = fdtdec_next_compatible(gd->fdt_blob, 0,
-                                         COMPAT_NVIDIA_TEGRA20_SFLASH);
-       if (node < 0) {
-               debug("%s: cannot locate sflash node\n", __func__);
-               return NULL;
-       }
-       if (!fdtdec_get_is_enabled(gd->fdt_blob, node)) {
-               debug("%s: sflash is disabled\n", __func__);
-               return NULL;
-       }
-       spi->regs = (struct spi_tegra *)fdtdec_get_addr(gd->fdt_blob,
-                                                       node, "reg");
-       if ((fdt_addr_t)spi->regs == FDT_ADDR_T_NONE) {
-               debug("%s: no sflash register found\n", __func__);
-               return NULL;
-       }
-       spi->freq = fdtdec_get_int(gd->fdt_blob, node, "spi-max-frequency", 0);
-       if (!spi->freq) {
-               debug("%s: no sflash max frequency found\n", __func__);
-               return NULL;
-       }
-       spi->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
-       if (spi->periph_id == PERIPH_ID_NONE) {
-               debug("%s: could not decode periph id\n", __func__);
-               return NULL;
-       }
-#else
-       spi->regs = (struct spi_tegra *)NV_PA_SPI_BASE;
-       spi->freq = TEGRA_SPI_MAX_FREQ;
-       spi->periph_id = PERIPH_ID_SPI1;
-#endif
-       if (max_hz < spi->freq) {
-               debug("%s: limiting frequency from %u to %u\n", __func__,
-                     spi->freq, max_hz);
-               spi->freq = max_hz;
-       }
-       debug("%s: controller initialized at %p, freq = %u, periph_id = %d\n",
-             __func__, spi->regs, spi->freq, spi->periph_id);
-       spi->mode = mode;
-
-       return &spi->slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
-       struct tegra_spi_slave *spi = to_tegra_spi(slave);
-
-       free(spi);
-}
-
-void spi_init(void)
-{
-       /* do nothing */
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
-       struct tegra_spi_slave *spi = to_tegra_spi(slave);
-       struct spi_tegra *regs = spi->regs;
-       u32 reg;
-
-       /* Change SPI clock to correct frequency, PLLP_OUT0 source */
-       clock_start_periph_pll(spi->periph_id, CLOCK_ID_PERIPH, spi->freq);
-
-       /* Clear stale status here */
-       reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
-               SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF;
-       writel(reg, &regs->status);
-       debug("spi_init: STATUS = %08x\n", readl(&regs->status));
-
-       /*
-        * Use sw-controlled CS, so we can clock in data after ReadID, etc.
-        */
-       reg = (spi->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT;
-       if (spi->mode & 2)
-               reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT;
-       clrsetbits_le32(&regs->command, SPI_CMD_ACTIVE_SCLK_MASK |
-               SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg);
-       debug("spi_init: COMMAND = %08x\n", readl(&regs->command));
-
-       /*
-        * SPI pins on Tegra20 are muxed - change pinmux later due to UART
-        * issue.
-        */
-       pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH);
-       pinmux_tristate_disable(PINGRP_LSPI);
-       pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH);
-
-       return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
-       /*
-        * We can't release UART_DISABLE and set pinmux to UART4 here since
-        * some code (e,g, spi_flash_probe) uses printf() while the SPI
-        * bus is held. That is arguably bad, but it has the advantage of
-        * already being in the source tree.
-        */
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-       struct tegra_spi_slave *spi = to_tegra_spi(slave);
-
-       /* CS is negated on Tegra, so drive a 1 to get a 0 */
-       setbits_le32(&spi->regs->command, SPI_CMD_CS_VAL);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-       struct tegra_spi_slave *spi = to_tegra_spi(slave);
-
-       /* CS is negated on Tegra, so drive a 0 to get a 1 */
-       clrbits_le32(&spi->regs->command, SPI_CMD_CS_VAL);
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
-               const void *data_out, void *data_in, unsigned long flags)
-{
-       struct tegra_spi_slave *spi = to_tegra_spi(slave);
-       struct spi_tegra *regs = spi->regs;
-       u32 reg, tmpdout, tmpdin = 0;
-       const u8 *dout = data_out;
-       u8 *din = data_in;
-       int num_bytes;
-       int ret;
-
-       debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
-             slave->bus, slave->cs, *(u8 *)dout, *(u8 *)din, bitlen);
-       if (bitlen % 8)
-               return -1;
-       num_bytes = bitlen / 8;
-
-       ret = 0;
-
-       reg = readl(&regs->status);
-       writel(reg, &regs->status);     /* Clear all SPI events via R/W */
-       debug("spi_xfer entry: STATUS = %08x\n", reg);
-
-       reg = readl(&regs->command);
-       reg |= SPI_CMD_TXEN | SPI_CMD_RXEN;
-       writel(reg, &regs->command);
-       debug("spi_xfer: COMMAND = %08x\n", readl(&regs->command));
-
-       if (flags & SPI_XFER_BEGIN)
-               spi_cs_activate(slave);
-
-       /* handle data in 32-bit chunks */
-       while (num_bytes > 0) {
-               int bytes;
-               int is_read = 0;
-               int tm, i;
-
-               tmpdout = 0;
-               bytes = (num_bytes > 4) ?  4 : num_bytes;
-
-               if (dout != NULL) {
-                       for (i = 0; i < bytes; ++i)
-                               tmpdout = (tmpdout << 8) | dout[i];
-               }
-
-               num_bytes -= bytes;
-               if (dout)
-                       dout += bytes;
-
-               clrsetbits_le32(&regs->command, SPI_CMD_BIT_LENGTH_MASK,
-                               bytes * 8 - 1);
-               writel(tmpdout, &regs->tx_fifo);
-               setbits_le32(&regs->command, SPI_CMD_GO);
-
-               /*
-                * Wait for SPI transmit FIFO to empty, or to time out.
-                * The RX FIFO status will be read and cleared last
-                */
-               for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
-                       u32 status;
-
-                       status = readl(&regs->status);
-
-                       /* We can exit when we've had both RX and TX activity */
-                       if (is_read && (status & SPI_STAT_TXF_EMPTY))
-                               break;
-
-                       if ((status & (SPI_STAT_BSY | SPI_STAT_RDY)) !=
-                                       SPI_STAT_RDY)
-                               tm++;
-
-                       else if (!(status & SPI_STAT_RXF_EMPTY)) {
-                               tmpdin = readl(&regs->rx_fifo);
-                               is_read = 1;
-
-                               /* swap bytes read in */
-                               if (din != NULL) {
-                                       for (i = bytes - 1; i >= 0; --i) {
-                                               din[i] = tmpdin & 0xff;
-                                               tmpdin >>= 8;
-                                       }
-                                       din += bytes;
-                               }
-                       }
-               }
-
-               if (tm >= SPI_TIMEOUT)
-                       ret = tm;
-
-               /* clear ACK RDY, etc. bits */
-               writel(readl(&regs->status), &regs->status);
-       }
-
-       if (flags & SPI_XFER_END)
-               spi_cs_deactivate(slave);
-
-       debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n",
-               tmpdin, readl(&regs->status));
-
-       if (ret) {
-               printf("spi_xfer: timeout during SPI transfer, tm %d\n", ret);
-               return -1;
-       }
-
-       return 0;
-}
index 55dc83da6a187bfc00f94d84182c17ba5737a979..6a991752114ae70ecba7c5829dec2eebf35ae533 100644 (file)
@@ -60,7 +60,7 @@
 #define CONFIG_SYS_MMC_ENV_PART                2
 
 /* SPI */
-#define CONFIG_TEGRA_SLINK
+#define CONFIG_TEGRA20_SLINK
 #define CONFIG_TEGRA_SLINK_CTRLS       6
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_WINBOND
index 0644f7a5b8f668351358989f762d80b555a29c62..b92531477e78580edf1e0a0e2b4e60c3eb54ae48 100644 (file)
@@ -46,7 +46,7 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 
 /* SPI */
-#define CONFIG_TEGRA_SPI
+#define CONFIG_TEGRA20_SFLASH
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_WINBOND
 #define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0