ppc4xx: Update PLB/PCI divider for PMC440 board

This patch updates the PLB/PCI divider when running at
400MHz CPU frequency from 4 to 3 which results in 44MHz PCI sync clock.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>

diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c
index d588d8ca9bac92e08736d5e299a5d4dde4be14be..350af48638490ac4365ade03be062491c545de62 100644 (file)
--- a/board/esd/pmc440/cmd_pmc440.c
+++ b/board/esd/pmc440/cmd_pmc440.c
@@ -280,10 +280,10 @@ int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]
 
        if (argc > 1) {
                if (!strcmp(argv[1], "400")) {
-                       /* PLB=133MHz, PLB/PCI=4 */
+                       /* PLB=133MHz, PLB/PCI=3 */
                        printf("Bootstrapping for 400MHz\n");
                        sdsdp[0]=0x8678624e;
-                       sdsdp[1]=0x0947a030;
+                       sdsdp[1]=0x095fa030;
                        sdsdp[2]=0x40082350;
                        sdsdp[3]=0x0d050000;
                } else if (!strcmp(argv[1], "533")) {