mpc83xx: Fix the align bug of SDMA buffer

According to the latest user manual, the SDMA temporary
buffer base address must be 4KB aligned.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 5f209629f40e4c0d82aa9f1b71e7dd7e7f114c62..0f5232a72afe4d394e1526276873adcb2a9891a5 100644 (file)
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -98,7 +98,7 @@ static void qe_sdma_init(void)
        out_be32(&p->sdaqmr, 0);
 
        /* Allocate 2KB temporary buffer for sdma */
-       sdma_buffer_base = qe_muram_alloc(2048, 64);
+       sdma_buffer_base = qe_muram_alloc(2048, 4096);
        out_be32(&p->sdwbcr, sdma_buffer_base & QE_SDEBCR_BA_MASK);
 
        /* Clear sdma status */

diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h
index 0bcd0a9573e8941515c3deeee68d97dd8b448229..400b1a6f603839444483f7f13c0022939277da08 100644 (file)
--- a/drivers/qe/qe.h
+++ b/drivers/qe/qe.h
@@ -29,7 +29,7 @@
 #define QE_NUM_OF_BRGS 16
 #define UCC_MAX_NUM    8
 
-#define QE_DATAONLY_BASE       (uint)(128)
+#define QE_DATAONLY_BASE       0
 #define QE_DATAONLY_SIZE       (QE_MURAM_SIZE - QE_DATAONLY_BASE)
 
 /* QE threads SNUM