--- /dev/null
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2009 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).a
+
+COBJS = soc.o clock.o iomux.o timer.o speed.o
+SOBJS = lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+
+enum pll_clocks {
+ PLL1_CLOCK = 0,
+ PLL2_CLOCK,
+ PLL3_CLOCK,
+ PLL_CLOCKS,
+};
+
+struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
+ [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
+ [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
+ [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
+};
+
+struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+
+/*
+ * Calculate the frequency of this pll.
+ */
+static u32 decode_pll(struct mxc_pll_reg *pll, u32 infreq)
+{
+ u32 mfi, mfn, mfd, pd;
+
+ mfn = __raw_readl(&pll->mfn);
+ mfd = __raw_readl(&pll->mfd) + 1;
+ mfi = __raw_readl(&pll->op);
+ pd = (mfi & 0xF) + 1;
+ mfi = (mfi >> 4) & 0xF;
+ mfi = (mfi >= 5) ? mfi : 5;
+
+ return ((4 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000;
+}
+
+/*
+ * Get mcu main rate
+ */
+u32 get_mcu_main_clk(void)
+{
+ u32 reg, freq;
+
+ reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
+ MXC_CCM_CACRR_ARM_PODF_OFFSET;
+ freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
+ return freq / (reg + 1);
+}
+
+/*
+ * Get the rate of peripheral's root clock.
+ */
+static u32 get_periph_clk(void)
+{
+ u32 reg;
+
+ reg = __raw_readl(&mxc_ccm->cbcdr);
+ if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
+ return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
+ reg = __raw_readl(&mxc_ccm->cbcmr);
+ switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
+ MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
+ case 0:
+ return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
+ case 1:
+ return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
+ default:
+ return 0;
+ }
+ /* NOTREACHED */
+}
+
+/*
+ * Get the rate of ipg clock.
+ */
+static u32 get_ipg_clk(void)
+{
+ u32 ahb_podf, ipg_podf;
+
+ ahb_podf = __raw_readl(&mxc_ccm->cbcdr);
+ ipg_podf = (ahb_podf & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
+ MXC_CCM_CBCDR_IPG_PODF_OFFSET;
+ ahb_podf = (ahb_podf & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
+ MXC_CCM_CBCDR_AHB_PODF_OFFSET;
+ return get_periph_clk() / ((ahb_podf + 1) * (ipg_podf + 1));
+}
+
+/*
+ * Get the rate of ipg_per clock.
+ */
+static u32 get_ipg_per_clk(void)
+{
+ u32 pred1, pred2, podf;
+
+ if (__raw_readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
+ return get_ipg_clk();
+ /* Fixme: not handle what about lpm*/
+ podf = __raw_readl(&mxc_ccm->cbcdr);
+ pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
+ MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET;
+ pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
+ MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET;
+ podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
+ MXC_CCM_CBCDR_PERCLK_PODF_OFFSET;
+
+ return get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
+}
+
+/*
+ * Get the rate of uart clk.
+ */
+static u32 get_uart_clk(void)
+{
+ unsigned int freq, reg, pred, podf;
+
+ reg = __raw_readl(&mxc_ccm->cscmr1);
+ switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
+ MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
+ case 0x0:
+ freq = decode_pll(mxc_plls[PLL1_CLOCK],
+ CONFIG_SYS_MX5_HCLK);
+ break;
+ case 0x1:
+ freq = decode_pll(mxc_plls[PLL2_CLOCK],
+ CONFIG_SYS_MX5_HCLK);
+ break;
+ case 0x2:
+ freq = decode_pll(mxc_plls[PLL3_CLOCK],
+ CONFIG_SYS_MX5_HCLK);
+ break;
+ default:
+ return 66500000;
+ }
+
+ reg = __raw_readl(&mxc_ccm->cscdr1);
+
+ pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
+ MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET;
+
+ podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
+ MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
+ freq /= (pred + 1) * (podf + 1);
+
+ return freq;
+}
+
+/*
+ * This function returns the low power audio clock.
+ */
+u32 get_lp_apm(void)
+{
+ u32 ret_val = 0;
+ u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
+
+ if (((ccsr >> 9) & 1) == 0)
+ ret_val = CONFIG_SYS_MX5_HCLK;
+ else
+ ret_val = ((32768 * 1024));
+
+ return ret_val;
+}
+
+/*
+ * get cspi clock rate.
+ */
+u32 imx_get_cspiclk(void)
+{
+ u32 ret_val = 0, pdf, pre_pdf, clk_sel;
+ u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1);
+ u32 cscdr2 = __raw_readl(&mxc_ccm->cscdr2);
+
+ pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \
+ >> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET;
+ pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \
+ >> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
+ clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \
+ >> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
+
+ switch (clk_sel) {
+ case 0:
+ ret_val = decode_pll(mxc_plls[PLL1_CLOCK],
+ CONFIG_SYS_MX5_HCLK) /
+ ((pre_pdf + 1) * (pdf + 1));
+ break;
+ case 1:
+ ret_val = decode_pll(mxc_plls[PLL2_CLOCK],
+ CONFIG_SYS_MX5_HCLK) /
+ ((pre_pdf + 1) * (pdf + 1));
+ break;
+ case 2:
+ ret_val = decode_pll(mxc_plls[PLL3_CLOCK],
+ CONFIG_SYS_MX5_HCLK) /
+ ((pre_pdf + 1) * (pdf + 1));
+ break;
+ default:
+ ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
+ break;
+ }
+
+ return ret_val;
+}
+
+/*
+ * The API of get mxc clockes.
+ */
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+ switch (clk) {
+ case MXC_ARM_CLK:
+ return get_mcu_main_clk();
+ case MXC_AHB_CLK:
+ break;
+ case MXC_IPG_CLK:
+ return get_ipg_clk();
+ case MXC_IPG_PERCLK:
+ return get_ipg_per_clk();
+ case MXC_UART_CLK:
+ return get_uart_clk();
+ case MXC_CSPI_CLK:
+ return imx_get_cspiclk();
+ case MXC_FEC_CLK:
+ return decode_pll(mxc_plls[PLL1_CLOCK],
+ CONFIG_SYS_MX5_HCLK);
+ default:
+ break;
+ }
+ return -1;
+}
+
+u32 imx_get_uartclk(void)
+{
+ return get_uart_clk();
+}
+
+
+u32 imx_get_fecclk(void)
+{
+ return mxc_get_clock(MXC_IPG_CLK);
+}
+
+/*
+ * Dump some core clockes.
+ */
+int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ u32 freq;
+
+ freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
+ printf("pll1: %dMHz\n", freq / 1000000);
+ freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
+ printf("pll2: %dMHz\n", freq / 1000000);
+ freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
+ printf("pll3: %dMHz\n", freq / 1000000);
+ printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK));
+ printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK));
+
+ return 0;
+}
+
+/***************************************************/
+
+U_BOOT_CMD(
+ clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,
+ "display clocks\n",
+ ""
+);
--- /dev/null
+/*
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx5x_pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+
+/* IOMUX register (base) addresses */
+enum iomux_reg_addr {
+ IOMUXGPR0 = IOMUXC_BASE_ADDR,
+ IOMUXGPR1 = IOMUXC_BASE_ADDR + 0x004,
+ IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR,
+ IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + MUX_I_END,
+ IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + PAD_I_START,
+ IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR,
+};
+
+#define MUX_PIN_NUM_MAX (((MUX_I_END - MUX_I_START) >> 2) + 1)
+
+/* Get the iomux register address of this pin */
+static inline u32 get_mux_reg(iomux_pin_name_t pin)
+{
+ u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
+
+ if (is_soc_rev(CHIP_REV_2_0) < 0) {
+ /*
+ * Fixup register address:
+ * i.MX51 TO1 has offset with the register
+ * which is define as TO2.
+ */
+ if ((pin == MX51_PIN_NANDF_RB5) ||
+ (pin == MX51_PIN_NANDF_RB6) ||
+ (pin == MX51_PIN_NANDF_RB7))
+ ; /* Do nothing */
+ else if (mux_reg >= 0x2FC)
+ mux_reg += 8;
+ else if (mux_reg >= 0x130)
+ mux_reg += 0xC;
+ }
+ mux_reg += IOMUXSW_MUX_CTL;
+ return mux_reg;
+}
+
+/* Get the pad register address of this pin */
+static inline u32 get_pad_reg(iomux_pin_name_t pin)
+{
+ u32 pad_reg = PIN_TO_IOMUX_PAD(pin);
+
+ if (is_soc_rev(CHIP_REV_2_0) < 0) {
+ /*
+ * Fixup register address:
+ * i.MX51 TO1 has offset with the register
+ * which is define as TO2.
+ */
+ if ((pin == MX51_PIN_NANDF_RB5) ||
+ (pin == MX51_PIN_NANDF_RB6) ||
+ (pin == MX51_PIN_NANDF_RB7))
+ ; /* Do nothing */
+ else if (pad_reg == 0x4D0 - PAD_I_START)
+ pad_reg += 0x4C;
+ else if (pad_reg == 0x860 - PAD_I_START)
+ pad_reg += 0x9C;
+ else if (pad_reg >= 0x804 - PAD_I_START)
+ pad_reg += 0xB0;
+ else if (pad_reg >= 0x7FC - PAD_I_START)
+ pad_reg += 0xB4;
+ else if (pad_reg >= 0x4E4 - PAD_I_START)
+ pad_reg += 0xCC;
+ else
+ pad_reg += 8;
+ }
+ pad_reg += IOMUXSW_PAD_CTL;
+ return pad_reg;
+}
+
+/* Get the last iomux register address */
+static inline u32 get_mux_end(void)
+{
+ if (is_soc_rev(CHIP_REV_2_0) < 0)
+ return IOMUXC_BASE_ADDR + (0x3F8 - 4);
+ else
+ return IOMUXC_BASE_ADDR + (0x3F0 - 4);
+}
+
+/*
+ * This function is used to configure a pin through the IOMUX module.
+ * @param pin a pin number as defined in iomux_pin_name_t
+ * @param cfg an output function as defined in iomux_pin_cfg_t
+ *
+ * @return 0 if successful; Non-zero otherwise
+ */
+static void iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
+{
+ u32 mux_reg = get_mux_reg(pin);
+
+ if ((mux_reg > get_mux_end()) || (mux_reg < IOMUXSW_MUX_CTL))
+ return ;
+ if (cfg == IOMUX_CONFIG_GPIO)
+ writel(PIN_TO_ALT_GPIO(pin), mux_reg);
+ else
+ writel(cfg, mux_reg);
+}
+
+/*
+ * Request ownership for an IO pin. This function has to be the first one
+ * being called before that pin is used. The caller has to check the
+ * return value to make sure it returns 0.
+ *
+ * @param pin a name defined by iomux_pin_name_t
+ * @param cfg an input function as defined in iomux_pin_cfg_t
+ *
+ */
+void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
+{
+ iomux_config_mux(pin, cfg);
+}
+
+/*
+ * Release ownership for an IO pin
+ *
+ * @param pin a name defined by iomux_pin_name_t
+ * @param cfg an input function as defined in iomux_pin_cfg_t
+ */
+void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
+{
+}
+
+/*
+ * This function configures the pad value for a IOMUX pin.
+ *
+ * @param pin a pin number as defined in iomux_pin_name_t
+ * @param config the ORed value of elements defined in iomux_pad_config_t
+ */
+void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
+{
+ u32 pad_reg = get_pad_reg(pin);
+ writel(config, pad_reg);
+}
+
+unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin)
+{
+ u32 pad_reg = get_pad_reg(pin);
+ return readl(pad_reg);
+}
--- /dev/null
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/asm-offsets.h>
+
+/*
+ * L2CC Cache setup/invalidation/disable
+ */
+.macro init_l2cc
+ /* explicitly disable L2 cache */
+ mrc 15, 0, r0, c1, c0, 1
+ bic r0, r0, #0x2
+ mcr 15, 0, r0, c1, c0, 1
+
+ /* reconfigure L2 cache aux control reg */
+ mov r0, #0xC0 /* tag RAM */
+ add r0, r0, #0x4 /* data RAM */
+ orr r0, r0, #(1 << 24) /* disable write allocate delay */
+ orr r0, r0, #(1 << 23) /* disable write allocate combine */
+ orr r0, r0, #(1 << 22) /* disable write allocate */
+
+ cmp r3, #0x10 /* r3 contains the silicon rev */
+
+ /* disable write combine for TO 2 and lower revs */
+ orrls r0, r0, #(1 << 25)
+
+ mcr 15, 1, r0, c9, c0, 2
+.endm /* init_l2cc */
+
+/* AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.*/
+.macro init_aips
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ ldr r0, =AIPS1_BASE_ADDR
+ ldr r1, =0x77777777
+ str r1, [r0, #0x0]
+ str r1, [r0, #0x4]
+ ldr r0, =AIPS2_BASE_ADDR
+ str r1, [r0, #0x0]
+ str r1, [r0, #0x4]
+ /*
+ * Clear the on and off peripheral modules Supervisor Protect bit
+ * for SDMA to access them. Did not change the AIPS control registers
+ * (offset 0x20) access type
+ */
+.endm /* init_aips */
+
+/* M4IF setup */
+.macro init_m4if
+ /* VPU and IPU given higher priority (0x4)
+ * IPU accesses with ID=0x1 given highest priority (=0xA)
+ */
+ ldr r0, =M4IF_BASE_ADDR
+
+ ldr r1, =0x00000203
+ str r1, [r0, #0x40]
+
+ ldr r1, =0x0
+ str r1, [r0, #0x44]
+
+ ldr r1, =0x00120125
+ str r1, [r0, #0x9C]
+
+ ldr r1, =0x001901A3
+ str r1, [r0, #0x48]
+
+.endm /* init_m4if */
+
+.macro setup_pll pll, freq
+ ldr r2, =\pll
+ ldr r1, =0x00001232
+ str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
+ mov r1, #0x2
+ str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
+
+ str r3, [r2, #PLL_DP_OP]
+ str r3, [r2, #PLL_DP_HFS_OP]
+
+ str r4, [r2, #PLL_DP_MFD]
+ str r4, [r2, #PLL_DP_HFS_MFD]
+
+ str r5, [r2, #PLL_DP_MFN]
+ str r5, [r2, #PLL_DP_HFS_MFN]
+
+ ldr r1, =0x00001232
+ str r1, [r2, #PLL_DP_CTL]
+1: ldr r1, [r2, #PLL_DP_CTL]
+ ands r1, r1, #0x1
+ beq 1b
+.endm
+
+.macro init_clock
+ ldr r0, =CCM_BASE_ADDR
+
+ /* Gate of clocks to the peripherals first */
+ ldr r1, =0x3FFFFFFF
+ str r1, [r0, #CLKCTL_CCGR0]
+ ldr r1, =0x0
+ str r1, [r0, #CLKCTL_CCGR1]
+ str r1, [r0, #CLKCTL_CCGR2]
+ str r1, [r0, #CLKCTL_CCGR3]
+
+ ldr r1, =0x00030000
+ str r1, [r0, #CLKCTL_CCGR4]
+ ldr r1, =0x00FFF030
+ str r1, [r0, #CLKCTL_CCGR5]
+ ldr r1, =0x00000300
+ str r1, [r0, #CLKCTL_CCGR6]
+
+ /* Disable IPU and HSC dividers */
+ mov r1, #0x60000
+ str r1, [r0, #CLKCTL_CCDR]
+
+ /* Make sure to switch the DDR away from PLL 1 */
+ ldr r1, =0x19239145
+ str r1, [r0, #CLKCTL_CBCDR]
+ /* make sure divider effective */
+1: ldr r1, [r0, #CLKCTL_CDHIPR]
+ cmp r1, #0x0
+ bne 1b
+
+ /* Switch ARM to step clock */
+ mov r1, #0x4
+ str r1, [r0, #CLKCTL_CCSR]
+ mov r3, #DP_OP_800
+ mov r4, #DP_MFD_800
+ mov r5, #DP_MFN_800
+ setup_pll PLL1_BASE_ADDR
+
+ mov r3, #DP_OP_665
+ mov r4, #DP_MFD_665
+ mov r5, #DP_MFN_665
+ setup_pll PLL3_BASE_ADDR
+
+ /* Switch peripheral to PLL 3 */
+ ldr r0, =CCM_BASE_ADDR
+ ldr r1, =0x000010C0
+ orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
+ str r1, [r0, #CLKCTL_CBCMR]
+ ldr r1, =0x13239145
+ str r1, [r0, #CLKCTL_CBCDR]
+ mov r3, #DP_OP_665
+ mov r4, #DP_MFD_665
+ mov r5, #DP_MFN_665
+ setup_pll PLL2_BASE_ADDR
+
+ /* Switch peripheral to PLL2 */
+ ldr r0, =CCM_BASE_ADDR
+ ldr r1, =0x19239145
+ str r1, [r0, #CLKCTL_CBCDR]
+ ldr r1, =0x000020C0
+ orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
+ str r1, [r0, #CLKCTL_CBCMR]
+
+ mov r3, #DP_OP_216
+ mov r4, #DP_MFD_216
+ mov r5, #DP_MFN_216
+ setup_pll PLL3_BASE_ADDR
+
+
+ /* Set the platform clock dividers */
+ ldr r0, =ARM_BASE_ADDR
+ ldr r1, =0x00000725
+ str r1, [r0, #0x14]
+
+ ldr r0, =CCM_BASE_ADDR
+
+ /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
+ ldr r1, =0x0
+ ldr r3, [r1, #ROM_SI_REV]
+ cmp r3, #0x10
+ movls r1, #0x1
+ movhi r1, #0
+ str r1, [r0, #CLKCTL_CACRR]
+
+ /* Switch ARM back to PLL 1 */
+ mov r1, #0
+ str r1, [r0, #CLKCTL_CCSR]
+
+ /* setup the rest */
+ /* Use lp_apm (24MHz) source for perclk */
+ ldr r1, =0x000020C2
+ orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
+ str r1, [r0, #CLKCTL_CBCMR]
+ /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
+ ldr r1, =CONFIG_SYS_CLKTL_CBCDR
+ str r1, [r0, #CLKCTL_CBCDR]
+
+ /* Restore the default values in the Gate registers */
+ ldr r1, =0xFFFFFFFF
+ str r1, [r0, #CLKCTL_CCGR0]
+ str r1, [r0, #CLKCTL_CCGR1]
+ str r1, [r0, #CLKCTL_CCGR2]
+ str r1, [r0, #CLKCTL_CCGR3]
+ str r1, [r0, #CLKCTL_CCGR4]
+ str r1, [r0, #CLKCTL_CCGR5]
+ str r1, [r0, #CLKCTL_CCGR6]
+
+ /* Use PLL 2 for UART's, get 66.5MHz from it */
+ ldr r1, =0xA5A2A020
+ str r1, [r0, #CLKCTL_CSCMR1]
+ ldr r1, =0x00C30321
+ str r1, [r0, #CLKCTL_CSCDR1]
+
+ /* make sure divider effective */
+1: ldr r1, [r0, #CLKCTL_CDHIPR]
+ cmp r1, #0x0
+ bne 1b
+
+ mov r1, #0x0
+ str r1, [r0, #CLKCTL_CCDR]
+
+ /* for cko - for ARM div by 8 */
+ mov r1, #0x000A0000
+ add r1, r1, #0x00000F0
+ str r1, [r0, #CLKCTL_CCOSR]
+.endm
+
+.macro setup_wdog
+ ldr r0, =WDOG1_BASE_ADDR
+ mov r1, #0x30
+ strh r1, [r0]
+.endm
+
+.section ".text.init", "x"
+
+.globl lowlevel_init
+lowlevel_init:
+ ldr r0, =GPIO1_BASE_ADDR
+ ldr r1, [r0, #0x0]
+ orr r1, r1, #(1 << 23)
+ str r1, [r0, #0x0]
+ ldr r1, [r0, #0x4]
+ orr r1, r1, #(1 << 23)
+ str r1, [r0, #0x4]
+
+#ifdef ENABLE_IMPRECISE_ABORT
+ mrs r1, spsr /* save old spsr */
+ mrs r0, cpsr /* read out the cpsr */
+ bic r0, r0, #0x100 /* clear the A bit */
+ msr spsr, r0 /* update spsr */
+ add lr, pc, #0x8 /* update lr */
+ movs pc, lr /* update cpsr */
+ nop
+ nop
+ nop
+ nop
+ msr spsr, r1 /* restore old spsr */
+#endif
+
+ init_l2cc
+
+ init_aips
+
+ init_m4if
+
+ init_clock
+
+ /* r12 saved upper lr*/
+ mov pc,lr
+
+/* Board level setting value */
+DDR_PERCHARGE_CMD: .word 0x04008008
+DDR_REFRESH_CMD: .word 0x00008010
+DDR_LMR1_W: .word 0x00338018
+DDR_LMR_CMD: .word 0xB2220000
+DDR_TIMING_W: .word 0xB02567A9
+DDR_MISC_W: .word 0x000A0104
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_FSL_ESDHC
+#include <fsl_esdhc.h>
+#endif
+
+#if defined(CONFIG_MX51)
+#define CPU_TYPE 0x51000
+#else
+#error "CPU_TYPE not defined"
+#endif
+
+u32 get_cpu_rev(void)
+{
+ int system_rev = CPU_TYPE;
+ int reg = __raw_readl(ROM_SI_REV);
+
+ switch (reg) {
+ case 0x02:
+ system_rev |= CHIP_REV_1_1;
+ break;
+ case 0x10:
+ if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
+ system_rev |= CHIP_REV_2_5;
+ else
+ system_rev |= CHIP_REV_2_0;
+ break;
+ case 0x20:
+ system_rev |= CHIP_REV_3_0;
+ break;
+ return system_rev;
+ default:
+ system_rev |= CHIP_REV_1_0;
+ break;
+ }
+ return system_rev;
+}
+
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+ u32 cpurev;
+
+ cpurev = get_cpu_rev();
+ printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n",
+ (cpurev & 0xFF000) >> 12,
+ (cpurev & 0x000F0) >> 4,
+ (cpurev & 0x0000F) >> 0,
+ mxc_get_clock(MXC_ARM_CLK) / 1000000);
+ return 0;
+}
+#endif
+
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+#if defined(CONFIG_FEC_MXC)
+extern int fecmxc_initialize(bd_t *bis);
+#endif
+
+int cpu_eth_init(bd_t *bis)
+{
+ int rc = -ENODEV;
+
+#if defined(CONFIG_FEC_MXC)
+ rc = fecmxc_initialize(bis);
+#endif
+
+ return rc;
+}
+
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_FSL_ESDHC
+ return fsl_esdhc_mmc_init(bis);
+#else
+ return 0;
+#endif
+}
+
+
+void reset_cpu(ulong addr)
+{
+ __raw_writew(4, WDOG1_BASE_ADDR);
+}
--- /dev/null
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+
+int get_clocks(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_FSL_ESDHC
+ gd->sdhc_clk = mxc_get_clock(MXC_IPG_PERCLK);
+#endif
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+/* General purpose timers registers */
+struct mxc_gpt {
+ unsigned int control;
+ unsigned int prescaler;
+ unsigned int status;
+ unsigned int nouse[6];
+ unsigned int counter;
+};
+
+static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
+
+/* General purpose timers bitfields */
+#define GPTCR_SWR (1<<15) /* Software reset */
+#define GPTCR_FRR (1<<9) /* Freerun / restart */
+#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
+#define GPTCR_TEN (1) /* Timer enable */
+
+static ulong timestamp;
+static ulong lastinc;
+
+int timer_init(void)
+{
+ int i;
+
+ /* setup GP Timer 1 */
+ __raw_writel(GPTCR_SWR, &cur_gpt->control);
+
+ /* We have no udelay by now */
+ for (i = 0; i < 100; i++)
+ __raw_writel(0, &cur_gpt->control);
+
+ __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
+
+ /* Freerun Mode, PERCLK1 input */
+ i = __raw_readl(&cur_gpt->control);
+ __raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control);
+ reset_timer_masked();
+ return 0;
+}
+
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+void reset_timer_masked(void)
+{
+ ulong val = __raw_readl(&cur_gpt->counter);
+ lastinc = val / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ);
+ timestamp = 0;
+}
+
+ulong get_timer_masked(void)
+{
+ ulong val = __raw_readl(&cur_gpt->counter);
+ val /= (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ);
+ if (val >= lastinc)
+ timestamp += (val - lastinc);
+ else
+ timestamp += ((0xFFFFFFFF / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ))
+ - lastinc) + val;
+ lastinc = val;
+ return timestamp;
+}
+
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+ timestamp = t;
+}
+
+/* delay x useconds AND preserve advance timestamp value */
+void __udelay(unsigned long usec)
+{
+ unsigned long now, start, tmo;
+ tmo = usec * (CONFIG_SYS_MX5_CLK32 / 1000) / 1000;
+
+ if (!tmo)
+ tmo = 1;
+
+ now = start = readl(&cur_gpt->counter);
+
+ while ((now - start) < tmo)
+ now = readl(&cur_gpt->counter);
+
+}
--- /dev/null
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ arch/arm/cpu/armv7/start.o
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data)
+ __datarel_start = .;
+ *(.data.rel)
+ __datarelrolocal_start = .;
+ *(.data.rel.ro.local)
+ __datarellocal_start = .;
+ *(.data.rel.local)
+ __datarelro_start = .;
+ *(.data.rel.ro)
+ }
+
+ __got_start = .;
+ . = ALIGN(4);
+ .got : { *(.got) }
+ __got_end = .;
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2009 Freescale Semiconductor, Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(SOC).a
-
-COBJS = soc.o clock.o iomux.o timer.o speed.o
-SOBJS = lowlevel_init.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all: $(obj).depend $(LIB)
-
-$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
-
-enum pll_clocks {
- PLL1_CLOCK = 0,
- PLL2_CLOCK,
- PLL3_CLOCK,
- PLL_CLOCKS,
-};
-
-struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
- [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
- [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
- [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
-};
-
-struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
-
-/*
- * Calculate the frequency of this pll.
- */
-static u32 decode_pll(struct mxc_pll_reg *pll, u32 infreq)
-{
- u32 mfi, mfn, mfd, pd;
-
- mfn = __raw_readl(&pll->mfn);
- mfd = __raw_readl(&pll->mfd) + 1;
- mfi = __raw_readl(&pll->op);
- pd = (mfi & 0xF) + 1;
- mfi = (mfi >> 4) & 0xF;
- mfi = (mfi >= 5) ? mfi : 5;
-
- return ((4 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000;
-}
-
-/*
- * Get mcu main rate
- */
-u32 get_mcu_main_clk(void)
-{
- u32 reg, freq;
-
- reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
- MXC_CCM_CACRR_ARM_PODF_OFFSET;
- freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
- return freq / (reg + 1);
-}
-
-/*
- * Get the rate of peripheral's root clock.
- */
-static u32 get_periph_clk(void)
-{
- u32 reg;
-
- reg = __raw_readl(&mxc_ccm->cbcdr);
- if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
- return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ);
- reg = __raw_readl(&mxc_ccm->cbcmr);
- switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
- MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
- case 0:
- return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
- case 1:
- return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX51_HCLK_FREQ);
- default:
- return 0;
- }
- /* NOTREACHED */
-}
-
-/*
- * Get the rate of ipg clock.
- */
-static u32 get_ipg_clk(void)
-{
- u32 ahb_podf, ipg_podf;
-
- ahb_podf = __raw_readl(&mxc_ccm->cbcdr);
- ipg_podf = (ahb_podf & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
- MXC_CCM_CBCDR_IPG_PODF_OFFSET;
- ahb_podf = (ahb_podf & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
- MXC_CCM_CBCDR_AHB_PODF_OFFSET;
- return get_periph_clk() / ((ahb_podf + 1) * (ipg_podf + 1));
-}
-
-/*
- * Get the rate of ipg_per clock.
- */
-static u32 get_ipg_per_clk(void)
-{
- u32 pred1, pred2, podf;
-
- if (__raw_readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
- return get_ipg_clk();
- /* Fixme: not handle what about lpm*/
- podf = __raw_readl(&mxc_ccm->cbcdr);
- pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
- MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET;
- pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
- MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET;
- podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
- MXC_CCM_CBCDR_PERCLK_PODF_OFFSET;
-
- return get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
-}
-
-/*
- * Get the rate of uart clk.
- */
-static u32 get_uart_clk(void)
-{
- unsigned int freq, reg, pred, podf;
-
- reg = __raw_readl(&mxc_ccm->cscmr1);
- switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
- MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
- case 0x0:
- freq = decode_pll(mxc_plls[PLL1_CLOCK],
- CONFIG_MX51_HCLK_FREQ);
- break;
- case 0x1:
- freq = decode_pll(mxc_plls[PLL2_CLOCK],
- CONFIG_MX51_HCLK_FREQ);
- break;
- case 0x2:
- freq = decode_pll(mxc_plls[PLL3_CLOCK],
- CONFIG_MX51_HCLK_FREQ);
- break;
- default:
- return 66500000;
- }
-
- reg = __raw_readl(&mxc_ccm->cscdr1);
-
- pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
- MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET;
-
- podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
- MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
- freq /= (pred + 1) * (podf + 1);
-
- return freq;
-}
-
-/*
- * This function returns the low power audio clock.
- */
-u32 get_lp_apm(void)
-{
- u32 ret_val = 0;
- u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
-
- if (((ccsr >> 9) & 1) == 0)
- ret_val = CONFIG_MX51_HCLK_FREQ;
- else
- ret_val = ((32768 * 1024));
-
- return ret_val;
-}
-
-/*
- * get cspi clock rate.
- */
-u32 imx_get_cspiclk(void)
-{
- u32 ret_val = 0, pdf, pre_pdf, clk_sel;
- u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1);
- u32 cscdr2 = __raw_readl(&mxc_ccm->cscdr2);
-
- pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \
- >> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET;
- pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \
- >> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
- clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \
- >> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
-
- switch (clk_sel) {
- case 0:
- ret_val = decode_pll(mxc_plls[PLL1_CLOCK],
- CONFIG_MX51_HCLK_FREQ) /
- ((pre_pdf + 1) * (pdf + 1));
- break;
- case 1:
- ret_val = decode_pll(mxc_plls[PLL2_CLOCK],
- CONFIG_MX51_HCLK_FREQ) /
- ((pre_pdf + 1) * (pdf + 1));
- break;
- case 2:
- ret_val = decode_pll(mxc_plls[PLL3_CLOCK],
- CONFIG_MX51_HCLK_FREQ) /
- ((pre_pdf + 1) * (pdf + 1));
- break;
- default:
- ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
- break;
- }
-
- return ret_val;
-}
-
-/*
- * The API of get mxc clockes.
- */
-unsigned int mxc_get_clock(enum mxc_clock clk)
-{
- switch (clk) {
- case MXC_ARM_CLK:
- return get_mcu_main_clk();
- case MXC_AHB_CLK:
- break;
- case MXC_IPG_CLK:
- return get_ipg_clk();
- case MXC_IPG_PERCLK:
- return get_ipg_per_clk();
- case MXC_UART_CLK:
- return get_uart_clk();
- case MXC_CSPI_CLK:
- return imx_get_cspiclk();
- case MXC_FEC_CLK:
- return decode_pll(mxc_plls[PLL1_CLOCK],
- CONFIG_MX51_HCLK_FREQ);
- default:
- break;
- }
- return -1;
-}
-
-u32 imx_get_uartclk(void)
-{
- return get_uart_clk();
-}
-
-
-u32 imx_get_fecclk(void)
-{
- return mxc_get_clock(MXC_IPG_CLK);
-}
-
-/*
- * Dump some core clockes.
- */
-int do_mx51_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- u32 freq;
-
- freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
- printf("mx51 pll1: %dMHz\n", freq / 1000000);
- freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ);
- printf("mx51 pll2: %dMHz\n", freq / 1000000);
- freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX51_HCLK_FREQ);
- printf("mx51 pll3: %dMHz\n", freq / 1000000);
- printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK));
- printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK));
-
- return 0;
-}
-
-/***************************************************/
-
-U_BOOT_CMD(
- clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx51_showclocks,
- "display mx51 clocks\n",
- ""
-);
+++ /dev/null
-/*
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx51_pins.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/sys_proto.h>
-
-/* IOMUX register (base) addresses */
-enum iomux_reg_addr {
- IOMUXGPR0 = IOMUXC_BASE_ADDR,
- IOMUXGPR1 = IOMUXC_BASE_ADDR + 0x004,
- IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR,
- IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + MUX_I_END,
- IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + PAD_I_START,
- IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR,
-};
-
-#define MUX_PIN_NUM_MAX (((MUX_I_END - MUX_I_START) >> 2) + 1)
-
-/* Get the iomux register address of this pin */
-static inline u32 get_mux_reg(iomux_pin_name_t pin)
-{
- u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
-
- if (is_soc_rev(CHIP_REV_2_0) < 0) {
- /*
- * Fixup register address:
- * i.MX51 TO1 has offset with the register
- * which is define as TO2.
- */
- if ((pin == MX51_PIN_NANDF_RB5) ||
- (pin == MX51_PIN_NANDF_RB6) ||
- (pin == MX51_PIN_NANDF_RB7))
- ; /* Do nothing */
- else if (mux_reg >= 0x2FC)
- mux_reg += 8;
- else if (mux_reg >= 0x130)
- mux_reg += 0xC;
- }
- mux_reg += IOMUXSW_MUX_CTL;
- return mux_reg;
-}
-
-/* Get the pad register address of this pin */
-static inline u32 get_pad_reg(iomux_pin_name_t pin)
-{
- u32 pad_reg = PIN_TO_IOMUX_PAD(pin);
-
- if (is_soc_rev(CHIP_REV_2_0) < 0) {
- /*
- * Fixup register address:
- * i.MX51 TO1 has offset with the register
- * which is define as TO2.
- */
- if ((pin == MX51_PIN_NANDF_RB5) ||
- (pin == MX51_PIN_NANDF_RB6) ||
- (pin == MX51_PIN_NANDF_RB7))
- ; /* Do nothing */
- else if (pad_reg == 0x4D0 - PAD_I_START)
- pad_reg += 0x4C;
- else if (pad_reg == 0x860 - PAD_I_START)
- pad_reg += 0x9C;
- else if (pad_reg >= 0x804 - PAD_I_START)
- pad_reg += 0xB0;
- else if (pad_reg >= 0x7FC - PAD_I_START)
- pad_reg += 0xB4;
- else if (pad_reg >= 0x4E4 - PAD_I_START)
- pad_reg += 0xCC;
- else
- pad_reg += 8;
- }
- pad_reg += IOMUXSW_PAD_CTL;
- return pad_reg;
-}
-
-/* Get the last iomux register address */
-static inline u32 get_mux_end(void)
-{
- if (is_soc_rev(CHIP_REV_2_0) < 0)
- return IOMUXC_BASE_ADDR + (0x3F8 - 4);
- else
- return IOMUXC_BASE_ADDR + (0x3F0 - 4);
-}
-
-/*
- * This function is used to configure a pin through the IOMUX module.
- * @param pin a pin number as defined in iomux_pin_name_t
- * @param cfg an output function as defined in iomux_pin_cfg_t
- *
- * @return 0 if successful; Non-zero otherwise
- */
-static void iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
- u32 mux_reg = get_mux_reg(pin);
-
- if ((mux_reg > get_mux_end()) || (mux_reg < IOMUXSW_MUX_CTL))
- return ;
- if (cfg == IOMUX_CONFIG_GPIO)
- writel(PIN_TO_ALT_GPIO(pin), mux_reg);
- else
- writel(cfg, mux_reg);
-}
-
-/*
- * Request ownership for an IO pin. This function has to be the first one
- * being called before that pin is used. The caller has to check the
- * return value to make sure it returns 0.
- *
- * @param pin a name defined by iomux_pin_name_t
- * @param cfg an input function as defined in iomux_pin_cfg_t
- *
- */
-void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
- iomux_config_mux(pin, cfg);
-}
-
-/*
- * Release ownership for an IO pin
- *
- * @param pin a name defined by iomux_pin_name_t
- * @param cfg an input function as defined in iomux_pin_cfg_t
- */
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
-}
-
-/*
- * This function configures the pad value for a IOMUX pin.
- *
- * @param pin a pin number as defined in iomux_pin_name_t
- * @param config the ORed value of elements defined in iomux_pad_config_t
- */
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
-{
- u32 pad_reg = get_pad_reg(pin);
- writel(config, pad_reg);
-}
-
-unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin)
-{
- u32 pad_reg = get_pad_reg(pin);
- return readl(pad_reg);
-}
+++ /dev/null
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/asm-offsets.h>
-
-/*
- * L2CC Cache setup/invalidation/disable
- */
-.macro init_l2cc
- /* explicitly disable L2 cache */
- mrc 15, 0, r0, c1, c0, 1
- bic r0, r0, #0x2
- mcr 15, 0, r0, c1, c0, 1
-
- /* reconfigure L2 cache aux control reg */
- mov r0, #0xC0 /* tag RAM */
- add r0, r0, #0x4 /* data RAM */
- orr r0, r0, #(1 << 24) /* disable write allocate delay */
- orr r0, r0, #(1 << 23) /* disable write allocate combine */
- orr r0, r0, #(1 << 22) /* disable write allocate */
-
- cmp r3, #0x10 /* r3 contains the silicon rev */
-
- /* disable write combine for TO 2 and lower revs */
- orrls r0, r0, #(1 << 25)
-
- mcr 15, 1, r0, c9, c0, 2
-.endm /* init_l2cc */
-
-/* AIPS setup - Only setup MPROTx registers.
- * The PACR default values are good.*/
-.macro init_aips
- /*
- * Set all MPROTx to be non-bufferable, trusted for R/W,
- * not forced to user-mode.
- */
- ldr r0, =AIPS1_BASE_ADDR
- ldr r1, =0x77777777
- str r1, [r0, #0x0]
- str r1, [r0, #0x4]
- ldr r0, =AIPS2_BASE_ADDR
- str r1, [r0, #0x0]
- str r1, [r0, #0x4]
- /*
- * Clear the on and off peripheral modules Supervisor Protect bit
- * for SDMA to access them. Did not change the AIPS control registers
- * (offset 0x20) access type
- */
-.endm /* init_aips */
-
-/* M4IF setup */
-.macro init_m4if
- /* VPU and IPU given higher priority (0x4)
- * IPU accesses with ID=0x1 given highest priority (=0xA)
- */
- ldr r0, =M4IF_BASE_ADDR
-
- ldr r1, =0x00000203
- str r1, [r0, #0x40]
-
- ldr r1, =0x0
- str r1, [r0, #0x44]
-
- ldr r1, =0x00120125
- str r1, [r0, #0x9C]
-
- ldr r1, =0x001901A3
- str r1, [r0, #0x48]
-
-.endm /* init_m4if */
-
-.macro setup_pll pll, freq
- ldr r2, =\pll
- ldr r1, =0x00001232
- str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
- mov r1, #0x2
- str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
-
- str r3, [r2, #PLL_DP_OP]
- str r3, [r2, #PLL_DP_HFS_OP]
-
- str r4, [r2, #PLL_DP_MFD]
- str r4, [r2, #PLL_DP_HFS_MFD]
-
- str r5, [r2, #PLL_DP_MFN]
- str r5, [r2, #PLL_DP_HFS_MFN]
-
- ldr r1, =0x00001232
- str r1, [r2, #PLL_DP_CTL]
-1: ldr r1, [r2, #PLL_DP_CTL]
- ands r1, r1, #0x1
- beq 1b
-.endm
-
-.macro init_clock
- ldr r0, =CCM_BASE_ADDR
-
- /* Gate of clocks to the peripherals first */
- ldr r1, =0x3FFFFFFF
- str r1, [r0, #CLKCTL_CCGR0]
- ldr r1, =0x0
- str r1, [r0, #CLKCTL_CCGR1]
- str r1, [r0, #CLKCTL_CCGR2]
- str r1, [r0, #CLKCTL_CCGR3]
-
- ldr r1, =0x00030000
- str r1, [r0, #CLKCTL_CCGR4]
- ldr r1, =0x00FFF030
- str r1, [r0, #CLKCTL_CCGR5]
- ldr r1, =0x00000300
- str r1, [r0, #CLKCTL_CCGR6]
-
- /* Disable IPU and HSC dividers */
- mov r1, #0x60000
- str r1, [r0, #CLKCTL_CCDR]
-
- /* Make sure to switch the DDR away from PLL 1 */
- ldr r1, =0x19239145
- str r1, [r0, #CLKCTL_CBCDR]
- /* make sure divider effective */
-1: ldr r1, [r0, #CLKCTL_CDHIPR]
- cmp r1, #0x0
- bne 1b
-
- /* Switch ARM to step clock */
- mov r1, #0x4
- str r1, [r0, #CLKCTL_CCSR]
- mov r3, #DP_OP_800
- mov r4, #DP_MFD_800
- mov r5, #DP_MFN_800
- setup_pll PLL1_BASE_ADDR
-
- mov r3, #DP_OP_665
- mov r4, #DP_MFD_665
- mov r5, #DP_MFN_665
- setup_pll PLL3_BASE_ADDR
-
- /* Switch peripheral to PLL 3 */
- ldr r0, =CCM_BASE_ADDR
- ldr r1, =0x000010C0
- orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
- str r1, [r0, #CLKCTL_CBCMR]
- ldr r1, =0x13239145
- str r1, [r0, #CLKCTL_CBCDR]
- mov r3, #DP_OP_665
- mov r4, #DP_MFD_665
- mov r5, #DP_MFN_665
- setup_pll PLL2_BASE_ADDR
-
- /* Switch peripheral to PLL2 */
- ldr r0, =CCM_BASE_ADDR
- ldr r1, =0x19239145
- str r1, [r0, #CLKCTL_CBCDR]
- ldr r1, =0x000020C0
- orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
- str r1, [r0, #CLKCTL_CBCMR]
-
- mov r3, #DP_OP_216
- mov r4, #DP_MFD_216
- mov r5, #DP_MFN_216
- setup_pll PLL3_BASE_ADDR
-
-
- /* Set the platform clock dividers */
- ldr r0, =ARM_BASE_ADDR
- ldr r1, =0x00000725
- str r1, [r0, #0x14]
-
- ldr r0, =CCM_BASE_ADDR
-
- /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
- ldr r1, =0x0
- ldr r3, [r1, #ROM_SI_REV]
- cmp r3, #0x10
- movls r1, #0x1
- movhi r1, #0
- str r1, [r0, #CLKCTL_CACRR]
-
- /* Switch ARM back to PLL 1 */
- mov r1, #0
- str r1, [r0, #CLKCTL_CCSR]
-
- /* setup the rest */
- /* Use lp_apm (24MHz) source for perclk */
- ldr r1, =0x000020C2
- orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
- str r1, [r0, #CLKCTL_CBCMR]
- /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
- ldr r1, =CONFIG_SYS_CLKTL_CBCDR
- str r1, [r0, #CLKCTL_CBCDR]
-
- /* Restore the default values in the Gate registers */
- ldr r1, =0xFFFFFFFF
- str r1, [r0, #CLKCTL_CCGR0]
- str r1, [r0, #CLKCTL_CCGR1]
- str r1, [r0, #CLKCTL_CCGR2]
- str r1, [r0, #CLKCTL_CCGR3]
- str r1, [r0, #CLKCTL_CCGR4]
- str r1, [r0, #CLKCTL_CCGR5]
- str r1, [r0, #CLKCTL_CCGR6]
-
- /* Use PLL 2 for UART's, get 66.5MHz from it */
- ldr r1, =0xA5A2A020
- str r1, [r0, #CLKCTL_CSCMR1]
- ldr r1, =0x00C30321
- str r1, [r0, #CLKCTL_CSCDR1]
-
- /* make sure divider effective */
-1: ldr r1, [r0, #CLKCTL_CDHIPR]
- cmp r1, #0x0
- bne 1b
-
- mov r1, #0x0
- str r1, [r0, #CLKCTL_CCDR]
-
- /* for cko - for ARM div by 8 */
- mov r1, #0x000A0000
- add r1, r1, #0x00000F0
- str r1, [r0, #CLKCTL_CCOSR]
-.endm
-
-.macro setup_wdog
- ldr r0, =WDOG1_BASE_ADDR
- mov r1, #0x30
- strh r1, [r0]
-.endm
-
-.section ".text.init", "x"
-
-.globl lowlevel_init
-lowlevel_init:
- ldr r0, =GPIO1_BASE_ADDR
- ldr r1, [r0, #0x0]
- orr r1, r1, #(1 << 23)
- str r1, [r0, #0x0]
- ldr r1, [r0, #0x4]
- orr r1, r1, #(1 << 23)
- str r1, [r0, #0x4]
-
-#ifdef ENABLE_IMPRECISE_ABORT
- mrs r1, spsr /* save old spsr */
- mrs r0, cpsr /* read out the cpsr */
- bic r0, r0, #0x100 /* clear the A bit */
- msr spsr, r0 /* update spsr */
- add lr, pc, #0x8 /* update lr */
- movs pc, lr /* update cpsr */
- nop
- nop
- nop
- nop
- msr spsr, r1 /* restore old spsr */
-#endif
-
- init_l2cc
-
- init_aips
-
- init_m4if
-
- init_clock
-
- /* r12 saved upper lr*/
- mov pc,lr
-
-/* Board level setting value */
-DDR_PERCHARGE_CMD: .word 0x04008008
-DDR_REFRESH_CMD: .word 0x00008010
-DDR_LMR1_W: .word 0x00338018
-DDR_LMR_CMD: .word 0xB2220000
-DDR_TIMING_W: .word 0xB02567A9
-DDR_MISC_W: .word 0x000A0104
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-#include <asm/errno.h>
-#include <asm/io.h>
-
-#ifdef CONFIG_FSL_ESDHC
-#include <fsl_esdhc.h>
-#endif
-
-u32 get_cpu_rev(void)
-{
- int reg;
- int system_rev;
-
- reg = __raw_readl(ROM_SI_REV);
- switch (reg) {
- case 0x02:
- system_rev = 0x51000 | CHIP_REV_1_1;
- break;
- case 0x10:
- if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
- system_rev = 0x51000 | CHIP_REV_2_5;
- else
- system_rev = 0x51000 | CHIP_REV_2_0;
- break;
- case 0x20:
- system_rev = 0x51000 | CHIP_REV_3_0;
- break;
- return system_rev;
- default:
- system_rev = 0x51000 | CHIP_REV_1_0;
- break;
- }
- return system_rev;
-}
-
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
- u32 cpurev;
-
- cpurev = get_cpu_rev();
- printf("CPU: Freescale i.MX51 family rev%d.%d at %d MHz\n",
- (cpurev & 0xF0) >> 4,
- (cpurev & 0x0F) >> 4,
- mxc_get_clock(MXC_ARM_CLK) / 1000000);
- return 0;
-}
-#endif
-
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-#if defined(CONFIG_FEC_MXC)
-extern int fecmxc_initialize(bd_t *bis);
-#endif
-
-int cpu_eth_init(bd_t *bis)
-{
- int rc = -ENODEV;
-
-#if defined(CONFIG_FEC_MXC)
- rc = fecmxc_initialize(bis);
-#endif
-
- return rc;
-}
-
-/*
- * Initializes on-chip MMC controllers.
- * to override, implement board_mmc_init()
- */
-int cpu_mmc_init(bd_t *bis)
-{
-#ifdef CONFIG_FSL_ESDHC
- return fsl_esdhc_mmc_init(bis);
-#else
- return 0;
-#endif
-}
-
-
-void reset_cpu(ulong addr)
-{
- __raw_writew(4, WDOG1_BASE_ADDR);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-
-int get_clocks(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_FSL_ESDHC
- gd->sdhc_clk = mxc_get_clock(MXC_IPG_PERCLK);
-#endif
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-
-/* General purpose timers registers */
-struct mxc_gpt {
- unsigned int control;
- unsigned int prescaler;
- unsigned int status;
- unsigned int nouse[6];
- unsigned int counter;
-};
-
-static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
-
-/* General purpose timers bitfields */
-#define GPTCR_SWR (1<<15) /* Software reset */
-#define GPTCR_FRR (1<<9) /* Freerun / restart */
-#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
-#define GPTCR_TEN (1) /* Timer enable */
-
-static ulong timestamp;
-static ulong lastinc;
-
-int timer_init(void)
-{
- int i;
-
- /* setup GP Timer 1 */
- __raw_writel(GPTCR_SWR, &cur_gpt->control);
-
- /* We have no udelay by now */
- for (i = 0; i < 100; i++)
- __raw_writel(0, &cur_gpt->control);
-
- __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
-
- /* Freerun Mode, PERCLK1 input */
- i = __raw_readl(&cur_gpt->control);
- __raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control);
- reset_timer_masked();
- return 0;
-}
-
-void reset_timer(void)
-{
- reset_timer_masked();
-}
-
-void reset_timer_masked(void)
-{
- ulong val = __raw_readl(&cur_gpt->counter);
- lastinc = val / (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ);
- timestamp = 0;
-}
-
-ulong get_timer_masked(void)
-{
- ulong val = __raw_readl(&cur_gpt->counter);
- val /= (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ);
- if (val >= lastinc)
- timestamp += (val - lastinc);
- else
- timestamp += ((0xFFFFFFFF / (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ))
- - lastinc) + val;
- lastinc = val;
- return timestamp;
-}
-
-ulong get_timer(ulong base)
-{
- return get_timer_masked() - base;
-}
-
-void set_timer(ulong t)
-{
- timestamp = t;
-}
-
-/* delay x useconds AND preserve advance timestamp value */
-void __udelay(unsigned long usec)
-{
- unsigned long now, start, tmo;
- tmo = usec * (CONFIG_MX51_CLK32 / 1000) / 1000;
-
- if (!tmo)
- tmo = 1;
-
- now = start = readl(&cur_gpt->counter);
-
- while ((now - start) < tmo)
- now = readl(&cur_gpt->counter);
-
-}
+++ /dev/null
-/*
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- arch/arm/cpu/armv7/start.o
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(.rodata) }
-
- . = ALIGN(4);
- .data : {
- *(.data)
- __datarel_start = .;
- *(.data.rel)
- __datarelrolocal_start = .;
- *(.data.rel.ro.local)
- __datarellocal_start = .;
- *(.data.rel.local)
- __datarelro_start = .;
- *(.data.rel.ro)
- }
-
- __got_start = .;
- . = ALIGN(4);
- .got : { *(.got) }
- __got_end = .;
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = ALIGN(4);
- __bss_start = .;
- .bss : { *(.bss) }
- _end = .;
-}
--- /dev/null
+/*
+ * needed for arch/arm/cpu/armv7/mx51/lowlevel_init.S
+ *
+ * These should be auto-generated
+ */
+/* CCM */
+#define CLKCTL_CCR 0x00
+#define CLKCTL_CCDR 0x04
+#define CLKCTL_CSR 0x08
+#define CLKCTL_CCSR 0x0C
+#define CLKCTL_CACRR 0x10
+#define CLKCTL_CBCDR 0x14
+#define CLKCTL_CBCMR 0x18
+#define CLKCTL_CSCMR1 0x1C
+#define CLKCTL_CSCMR2 0x20
+#define CLKCTL_CSCDR1 0x24
+#define CLKCTL_CS1CDR 0x28
+#define CLKCTL_CS2CDR 0x2C
+#define CLKCTL_CDCDR 0x30
+#define CLKCTL_CHSCCDR 0x34
+#define CLKCTL_CSCDR2 0x38
+#define CLKCTL_CSCDR3 0x3C
+#define CLKCTL_CSCDR4 0x40
+#define CLKCTL_CWDR 0x44
+#define CLKCTL_CDHIPR 0x48
+#define CLKCTL_CDCR 0x4C
+#define CLKCTL_CTOR 0x50
+#define CLKCTL_CLPCR 0x54
+#define CLKCTL_CISR 0x58
+#define CLKCTL_CIMR 0x5C
+#define CLKCTL_CCOSR 0x60
+#define CLKCTL_CGPR 0x64
+#define CLKCTL_CCGR0 0x68
+#define CLKCTL_CCGR1 0x6C
+#define CLKCTL_CCGR2 0x70
+#define CLKCTL_CCGR3 0x74
+#define CLKCTL_CCGR4 0x78
+#define CLKCTL_CCGR5 0x7C
+#define CLKCTL_CCGR6 0x80
+#define CLKCTL_CMEOR 0x84
+
+/* DPLL */
+#define PLL_DP_CTL 0x00
+#define PLL_DP_CONFIG 0x04
+#define PLL_DP_OP 0x08
+#define PLL_DP_MFD 0x0C
+#define PLL_DP_MFN 0x10
+#define PLL_DP_HFS_OP 0x1C
+#define PLL_DP_HFS_MFD 0x20
+#define PLL_DP_HFS_MFN 0x24
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+enum mxc_clock {
+ MXC_ARM_CLK = 0,
+ MXC_AHB_CLK,
+ MXC_IPG_CLK,
+ MXC_IPG_PERCLK,
+ MXC_UART_CLK,
+ MXC_CSPI_CLK,
+ MXC_FEC_CLK,
+};
+
+unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref);
+
+u32 imx_get_uartclk(void);
+u32 imx_get_fecclk(void);
+unsigned int mxc_get_clock(enum mxc_clock clk);
+
+#endif /* __ASM_ARCH_CLOCK_H */
--- /dev/null
+/*
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
+#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
+
+#define MXC_CCM_BASE CCM_BASE_ADDR
+
+/* DPLL register mapping structure */
+struct mxc_pll_reg {
+ u32 ctrl;
+ u32 config;
+ u32 op;
+ u32 mfd;
+ u32 mfn;
+ u32 mfn_minus;
+ u32 mfn_plus;
+ u32 hfs_op;
+ u32 hfs_mfd;
+ u32 hfs_mfn;
+ u32 mfn_togc;
+ u32 destat;
+};
+
+/* Register maping of CCM*/
+struct mxc_ccm_reg {
+ u32 ccr; /* 0x0000 */
+ u32 ccdr;
+ u32 csr;
+ u32 ccsr;
+ u32 cacrr; /* 0x0010*/
+ u32 cbcdr;
+ u32 cbcmr;
+ u32 cscmr1;
+ u32 cscmr2; /* 0x0020 */
+ u32 cscdr1;
+ u32 cs1cdr;
+ u32 cs2cdr;
+ u32 cdcdr; /* 0x0030 */
+ u32 chscdr;
+ u32 cscdr2;
+ u32 cscdr3;
+ u32 cscdr4; /* 0x0040 */
+ u32 cwdr;
+ u32 cdhipr;
+ u32 cdcr;
+ u32 ctor; /* 0x0050 */
+ u32 clpcr;
+ u32 cisr;
+ u32 cimr;
+ u32 ccosr; /* 0x0060 */
+ u32 cgpr;
+ u32 CCGR0;
+ u32 CCGR1;
+ u32 CCGR2; /* 0x0070 */
+ u32 CCGR3;
+ u32 CCGR4;
+ u32 CCGR5;
+ u32 CCGR6; /* 0x0080 */
+ u32 cmeor;
+};
+
+/* Define the bits in register CACRR */
+#define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
+#define MXC_CCM_CACRR_ARM_PODF_MASK 0x7
+
+/* Define the bits in register CBCDR */
+#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
+#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
+#define MXC_CCM_CBCDR_EMI_PODF_OFFSET 22
+#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
+#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET 19
+#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
+#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET 16
+#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
+#define MXC_CCM_CBCDR_NFC_PODF_OFFSET 13
+#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
+#define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10
+#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
+#define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8
+#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
+#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET 6
+#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
+#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET 3
+#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
+#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET 0
+#define MXC_CCM_CBCDR_PERCLK_PODF_MASK 0x7
+
+/* Define the bits in register CSCMR1 */
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET 30
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET 28
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
+#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET 26
+#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
+#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET 24
+#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET 22
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET 20
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
+#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
+#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET 16
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 14
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
+#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
+#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET 8
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
+#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7)
+#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET 4
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET 2
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
+#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
+#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL 0x1
+
+/* Define the bits in register CSCDR2 */
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET 25
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET 19
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET 16
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16)
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET 9
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET 6
+#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6)
+#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET 0
+#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK 0x3F
+
+/* Define the bits in register CBCMR */
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET 12
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
+#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET 10
+#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET 8
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET 6
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
+#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET 4
+#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
+#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
+#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
+
+/* Define the bits in register CSCDR1 */
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET 22
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET 19
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET 16
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET 14
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET 11
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
+#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET 3
+#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x7
+
+#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
--- /dev/null
+/*
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_MXC_MX51_H__
+#define __ASM_ARCH_MXC_MX51_H__
+
+/*
+ * IRAM
+ */
+#define IRAM_BASE_ADDR 0x1FFE8000 /* internal ram */
+/*
+ * Graphics Memory of GPU
+ */
+#define GPU_BASE_ADDR 0x20000000
+#define GPU_CTRL_BASE_ADDR 0x30000000
+#define IPU_CTRL_BASE_ADDR 0x40000000
+/*
+ * Debug
+ */
+#define DEBUG_BASE_ADDR 0x60000000
+#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000)
+#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000)
+#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000)
+#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000)
+#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000)
+#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000)
+#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000)
+#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000)
+
+/*
+ * SPBA global module enabled #0
+ */
+#define SPBA0_BASE_ADDR 0x70000000
+
+#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
+#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
+#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
+#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
+#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
+#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
+#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
+#define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000)
+#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000)
+#define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000)
+#define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000)
+#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
+
+/*
+ * AIPS 1
+ */
+#define AIPS1_BASE_ADDR 0x73F00000
+
+#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
+#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
+#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
+#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
+#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
+#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
+#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
+#define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
+#define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
+#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
+#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
+#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
+#define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
+#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
+#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
+#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
+#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000)
+#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000)
+#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000)
+#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000)
+
+/*
+ * AIPS 2
+ */
+#define AIPS2_BASE_ADDR 0x83F00000
+
+#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
+#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
+#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
+#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
+#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
+#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
+#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000)
+#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
+#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000)
+#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
+#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
+#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000)
+#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000)
+#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000)
+#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
+#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
+#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
+#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
+#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
+#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
+#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000)
+#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000)
+#define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000)
+#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00)
+#define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
+#define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
+#define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000)
+#define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000)
+#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
+#define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000)
+#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000)
+#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000)
+
+#define TZIC_BASE_ADDR 0x8FFFC000
+
+/*
+ * Memory regions and CS
+ */
+#define CSD0_BASE_ADDR 0x90000000
+#define CSD1_BASE_ADDR 0xA0000000
+#define CS0_BASE_ADDR 0xB0000000
+#define CS1_BASE_ADDR 0xB8000000
+#define CS2_BASE_ADDR 0xC0000000
+#define CS3_BASE_ADDR 0xC8000000
+#define CS4_BASE_ADDR 0xCC000000
+#define CS5_BASE_ADDR 0xCE000000
+
+/*
+ * NFC
+ */
+#define NFC_BASE_ADDR_AXI 0xCFFF0000 /* NAND flash AXI */
+
+/*!
+ * Number of GPIO port as defined in the IC Spec
+ */
+#define GPIO_PORT_NUM 4
+/*!
+ * Number of GPIO pins per port
+ */
+#define GPIO_NUM_PIN 32
+
+#define IIM_SREV 0x24
+#define ROM_SI_REV 0x48
+
+#define NFC_BUF_SIZE 0x1000
+
+/* M4IF */
+#define M4IF_FBPM0 0x40
+#define M4IF_FIDBP 0x48
+
+/* Assuming 24MHz input clock with doubler ON */
+/* MFI PDF */
+#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
+#define DP_MFD_850 (48 - 1)
+#define DP_MFN_850 41
+
+#define DP_OP_800 ((8 << 4) + ((1 - 1) << 0))
+#define DP_MFD_800 (3 - 1)
+#define DP_MFN_800 1
+
+#define DP_OP_700 ((7 << 4) + ((1 - 1) << 0))
+#define DP_MFD_700 (24 - 1)
+#define DP_MFN_700 7
+
+#define DP_OP_665 ((6 << 4) + ((1 - 1) << 0))
+#define DP_MFD_665 (96 - 1)
+#define DP_MFN_665 89
+
+#define DP_OP_532 ((5 << 4) + ((1 - 1) << 0))
+#define DP_MFD_532 (24 - 1)
+#define DP_MFN_532 13
+
+#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0))
+#define DP_MFD_400 (3 - 1)
+#define DP_MFN_400 1
+
+#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
+#define DP_MFD_216 (4 - 1)
+#define DP_MFN_216 3
+
+#define CHIP_REV_1_0 0x10
+#define CHIP_REV_1_1 0x11
+#define CHIP_REV_2_0 0x20
+#define CHIP_REV_2_5 0x25
+#define CHIP_REV_3_0 0x30
+
+#define BOARD_REV_1_0 0x0
+#define BOARD_REV_2_0 0x1
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+
+#define __REG(x) (*((volatile u32 *)(x)))
+#define __REG16(x) (*((volatile u16 *)(x)))
+#define __REG8(x) (*((volatile u8 *)(x)))
+
+struct clkctl {
+ u32 ccr;
+ u32 ccdr;
+ u32 csr;
+ u32 ccsr;
+ u32 cacrr;
+ u32 cbcdr;
+ u32 cbcmr;
+ u32 cscmr1;
+ u32 cscmr2;
+ u32 cscdr1;
+ u32 cs1cdr;
+ u32 cs2cdr;
+ u32 cdcdr;
+ u32 chsccdr;
+ u32 cscdr2;
+ u32 cscdr3;
+ u32 cscdr4;
+ u32 cwdr;
+ u32 cdhipr;
+ u32 cdcr;
+ u32 ctor;
+ u32 clpcr;
+ u32 cisr;
+ u32 cimr;
+ u32 ccosr;
+ u32 cgpr;
+ u32 ccgr0;
+ u32 ccgr1;
+ u32 ccgr2;
+ u32 ccgr3;
+ u32 ccgr4;
+ u32 ccgr5;
+ u32 ccgr6;
+ u32 cmeor;
+};
+
+/* WEIM registers */
+struct weim {
+ u32 csgcr1;
+ u32 csgcr2;
+ u32 csrcr1;
+ u32 csrcr2;
+ u32 cswcr1;
+ u32 cswcr2;
+};
+
+/* GPIO Registers */
+struct gpio_regs {
+ u32 gpio_dr;
+ u32 gpio_dir;
+ u32 gpio_psr;
+};
+
+/* System Reset Controller (SRC) */
+struct src {
+ u32 scr;
+ u32 sbmr;
+ u32 srsr;
+ u32 reserved1[2];
+ u32 sisr;
+ u32 simr;
+};
+#endif /* __ASSEMBLER__*/
+
+#endif /* __ASM_ARCH_MXC_MX51_H__ */
--- /dev/null
+/*
+ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MACH_MX5_IOMUX_H__
+#define __MACH_MX5_IOMUX_H__
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx5x_pins.h>
+
+typedef unsigned int iomux_pin_name_t;
+
+/* various IOMUX output functions */
+typedef enum iomux_config {
+ IOMUX_CONFIG_ALT0, /*!< used as alternate function 0 */
+ IOMUX_CONFIG_ALT1, /*!< used as alternate function 1 */
+ IOMUX_CONFIG_ALT2, /*!< used as alternate function 2 */
+ IOMUX_CONFIG_ALT3, /*!< used as alternate function 3 */
+ IOMUX_CONFIG_ALT4, /*!< used as alternate function 4 */
+ IOMUX_CONFIG_ALT5, /*!< used as alternate function 5 */
+ IOMUX_CONFIG_ALT6, /*!< used as alternate function 6 */
+ IOMUX_CONFIG_ALT7, /*!< used as alternate function 7 */
+ IOMUX_CONFIG_GPIO, /*!< added to help user use GPIO mode */
+ IOMUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */
+} iomux_pin_cfg_t;
+
+/* various IOMUX pad functions */
+typedef enum iomux_pad_config {
+ PAD_CTL_SRE_SLOW = 0x0 << 0, /* Slow slew rate */
+ PAD_CTL_SRE_FAST = 0x1 << 0, /* Fast slew rate */
+ PAD_CTL_DRV_LOW = 0x0 << 1, /* Low drive strength */
+ PAD_CTL_DRV_MEDIUM = 0x1 << 1, /* Medium drive strength */
+ PAD_CTL_DRV_HIGH = 0x2 << 1, /* High drive strength */
+ PAD_CTL_DRV_MAX = 0x3 << 1, /* Max drive strength */
+ PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3, /* Opendrain disable */
+ PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3,/* Opendrain enable */
+ PAD_CTL_100K_PD = 0x0 << 4, /* 100Kohm pulldown */
+ PAD_CTL_47K_PU = 0x1 << 4, /* 47Kohm pullup */
+ PAD_CTL_100K_PU = 0x2 << 4, /* 100Kohm pullup */
+ PAD_CTL_22K_PU = 0x3 << 4, /* 22Kohm pullup */
+ PAD_CTL_PUE_KEEPER = 0x0 << 6, /* enable pulldown */
+ PAD_CTL_PUE_PULL = 0x1 << 6, /* enable pullup */
+ PAD_CTL_PKE_NONE = 0x0 << 7, /* Disable pullup/pulldown */
+ PAD_CTL_PKE_ENABLE = 0x1 << 7, /* Enable pullup/pulldown */
+ PAD_CTL_HYS_NONE = 0x0 << 8, /* Hysteresis disabled */
+ PAD_CTL_HYS_ENABLE = 0x1 << 8, /* Hysteresis enabled */
+ PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9,/* DDR input CMOS */
+ PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,/* DDR input DDR */
+ PAD_CTL_DRV_VOT_LOW = 0x0 << 13, /* Low voltage mode */
+ PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,/* High voltage mode */
+} iomux_pad_config_t;
+
+/* various IOMUX input select register index */
+typedef enum iomux_input_select {
+ MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
+ MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
+ MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT,
+ MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT,
+ MUX_IN_CCM_IPP_DI_CLK_SELECT_INPUT,
+ /* TO2 */
+ MUX_IN_CCM_IPP_DI1_CLK_SELECT_INPUT,
+ MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
+ MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
+ MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
+ MUX_IN_CSPI_IPP_IND_MISO_SELECT_INPUT,
+ MUX_IN_CSPI_IPP_IND_MOSI_SELECT_INPUT,
+ MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
+ MUX_IN_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
+ MUX_IN_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
+ MUX_IN_DPLLIP1_L1T_TOG_EN_SELECT_INPUT,
+ /* TO2 */
+ MUX_IN_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
+ MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT,
+ MUX_IN_EMI_IPP_IND_RDY_INT_SELECT_INPUT,
+ MUX_IN_ESDHC3_IPP_DAT0_IN_SELECT_INPUT,
+ MUX_IN_ESDHC3_IPP_DAT1_IN_SELECT_INPUT,
+ MUX_IN_ESDHC3_IPP_DAT2_IN_SELECT_INPUT,
+ MUX_IN_ESDHC3_IPP_DAT3_IN_SELECT_INPUT,
+ MUX_IN_FEC_FEC_COL_SELECT_INPUT,
+ MUX_IN_FEC_FEC_CRS_SELECT_INPUT,
+ MUX_IN_FEC_FEC_MDI_SELECT_INPUT,
+ MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT,
+ MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT,
+ MUX_IN_FEC_FEC_RDATA_2_SELECT_INPUT,
+ MUX_IN_FEC_FEC_RDATA_3_SELECT_INPUT,
+ MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT,
+ MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT,
+ MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT,
+ MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT,
+ MUX_IN_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT,
+ MUX_IN_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT,
+ MUX_IN_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT,
+ MUX_IN_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
+ MUX_IN_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT,
+ MUX_IN_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT,
+ MUX_IN_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT,
+ MUX_IN_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT,
+ /* TO2 */
+ MUX_IN_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT,
+ MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
+ MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT,
+ /* TO2 */
+ MUX_IN_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT,
+ /* TO2 */
+ MUX_IN_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT,
+ MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT,
+ MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT,
+ MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT,
+ MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT,
+ MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
+
+ MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
+
+ MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
+
+ MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT,
+ MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT,
+ MUX_IN_KPP_IPP_IND_ROW_4_SELECT_INPUT,
+ MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT,
+ MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT,
+ MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT,
+ MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT,
+ MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
+ MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT,
+ MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
+ MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT,
+ MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT,
+ MUX_INPUT_NUM_MUX,
+} iomux_input_select_t;
+
+/* various IOMUX input functions */
+typedef enum iomux_input_config {
+ INPUT_CTL_PATH0 = 0x0,
+ INPUT_CTL_PATH1,
+ INPUT_CTL_PATH2,
+ INPUT_CTL_PATH3,
+ INPUT_CTL_PATH4,
+ INPUT_CTL_PATH5,
+ INPUT_CTL_PATH6,
+ INPUT_CTL_PATH7,
+} iomux_input_config_t;
+
+void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
+void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
+void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
+unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin);
+void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
+
+#endif /* __MACH_MX5_IOMUX_H__ */
--- /dev/null
+/*
+ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_MX5_MX5X_PINS_H__
+#define __ASM_ARCH_MX5_MX5X_PINS_H__
+
+#ifndef __ASSEMBLY__
+
+/*
+ * In order to identify pins more effectively, each mux-controlled pin's
+ * enumerated value is constructed in the following way:
+ *
+ * -------------------------------------------------------------------
+ * 31-29 | 28 - 24 | 23 - 21 | 20 - 10| 9 - 0
+ * -------------------------------------------------------------------
+ * IO_P | IO_I | GPIO_I | PAD_I | MUX_I
+ * -------------------------------------------------------------------
+ *
+ * Bit 0 to 9 contains MUX_I used to identify the register
+ * offset (0-based. base is IOMUX_module_base) defined in the Section
+ * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The
+ * similar field definitions are used for the pad control register.
+ * The IOMUX controller can be split in two parts. At the begeinning,
+ * there is the register definitions for the multiplexing each pin.
+ * Then there is a set of registers (PAD_I) to configure each pin
+ * (pullup, pulldown, etc).
+ * PAD_I defines the offset of the pad register for each pin.
+ * GPIO_I defines, if available, the number of gpio that can be
+ * connected to that pad
+ * IO_I defines the multiplexer mode required to set the pad in gpio mode
+ * IO_P defines the gpio structure (gpio1..gpio4) the pad belongs
+ *
+ * For example, the MX51_PIN_ETM_D0 is defined in the enumeration:
+ * ( (0x28 - MUX_I_START) << MUX_I)|( (0x250 - PAD_I_START) << PAD_I)
+ * It means the mux control register is at register offset 0x28. The pad control
+ * register offset is: 0x250 and also occupy the least significant bits
+ * within the register.
+ */
+
+/*!
+ * Starting bit position within each entry of \b iomux_pins to represent the
+ * MUX control register offset
+ */
+#define MUX_I 0
+/*!
+ * Starting bit position within each entry of \b iomux_pins to represent the
+ * PAD control register offset
+ */
+#define PAD_I 10
+/*!
+ * Starting bit position within each entry of \b iomux_pins to represent which
+ * mux mode is for GPIO (0-based)
+ */
+#define GPIO_I 21
+
+#define MUX_IO_P 29
+#define MUX_IO_I 24
+#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \
+ GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
+ ((1 << (MUX_IO_P - MUX_IO_I)) - 1)))
+#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin))
+#define GPIO_TO_PORT(n) (n / GPIO_NUM_PIN)
+#define GPIO_TO_INDEX(n) (n % GPIO_NUM_PIN)
+
+#define NON_GPIO_PORT 0x7
+#define PIN_TO_MUX_MASK ((1 << (PAD_I - MUX_I)) - 1)
+#define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1)
+#define PIN_TO_ALT_GPIO_MASK ((1 << (MUX_IO_I - GPIO_I)) - 1)
+
+#define NON_MUX_I PIN_TO_MUX_MASK
+#define MUX_I_START 0x001C
+#define PAD_I_START 0x3F0
+#define INPUT_CTL_START 0x8C4
+#define INPUT_CTL_START_TO1 0x928
+#define MUX_I_END (PAD_I_START - 4)
+
+#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \
+ (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
+ ((mi) << MUX_I) | \
+ ((pi - PAD_I_START) << PAD_I) | \
+ ((ga) << GPIO_I))
+
+#define _MXC_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \
+ _MXC_BUILD_PIN(gp, gi, ga, mi, pi)
+
+#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \
+ _MXC_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi)
+
+#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK)
+#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK)
+#define PIN_TO_ALT_GPIO(pin) ((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK)
+#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2)
+
+/*
+ * This enumeration is constructed based on the Section
+ * "sw_pad_ctl & sw_mux_ctl details" of the MX51 IC Spec. Each enumerated
+ * value is constructed based on the rules described above.
+ */
+enum iomux_pins {
+ MX51_PIN_EIM_DA0 = _MXC_BUILD_NON_GPIO_PIN(0x1C, 0x7A8),
+ MX51_PIN_EIM_DA1 = _MXC_BUILD_NON_GPIO_PIN(0x20, 0x7A8),
+ MX51_PIN_EIM_DA2 = _MXC_BUILD_NON_GPIO_PIN(0x24, 0x7A8),
+ MX51_PIN_EIM_DA3 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x7A8),
+ MX51_PIN_EIM_DA4 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x7AC),
+ MX51_PIN_EIM_DA5 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x7AC),
+ MX51_PIN_EIM_DA6 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x7AC),
+ MX51_PIN_EIM_DA7 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x7AC),
+ MX51_PIN_EIM_DA8 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x7B0),
+ MX51_PIN_EIM_DA9 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x7B0),
+ MX51_PIN_EIM_DA10 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x7B0),
+ MX51_PIN_EIM_DA11 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x7B0),
+ MX51_PIN_EIM_DA12 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x7BC),
+ MX51_PIN_EIM_DA13 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x7BC),
+ MX51_PIN_EIM_DA14 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x7BC),
+ MX51_PIN_EIM_DA15 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x7BC),
+ MX51_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x5C, 0x3F0),
+ MX51_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x60, 0x3F4),
+ MX51_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x64, 0x3F8),
+ MX51_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x68, 0x3FC),
+ MX51_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x6C, 0x400),
+ MX51_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x70, 0x404),
+ MX51_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x74, 0x408),
+ MX51_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x78, 0x40C),
+ MX51_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x7C, 0x410),
+ MX51_PIN_EIM_D25 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x414),
+ MX51_PIN_EIM_D26 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x418),
+ MX51_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x88, 0x41C),
+ MX51_PIN_EIM_D28 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x420),
+ MX51_PIN_EIM_D29 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x424),
+ MX51_PIN_EIM_D30 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x428),
+ MX51_PIN_EIM_D31 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x42C),
+ MX51_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x9C, 0x430),
+ MX51_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0xA0, 0x434),
+ MX51_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0xA4, 0x438),
+ MX51_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0xA8, 0x43C),
+ MX51_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0xAC, 0x440),
+ MX51_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0xB0, 0x444),
+ MX51_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0xB4, 0x448),
+ MX51_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0xB8, 0x44C),
+ MX51_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0xBC, 0x450),
+ MX51_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0xC0, 0x454),
+ MX51_PIN_EIM_A26 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0xC4, 0x458),
+ MX51_PIN_EIM_A27 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0xC8, 0x45C),
+ MX51_PIN_EIM_EB0 = _MXC_BUILD_NON_GPIO_PIN(0xCC, 0x460),
+ MX51_PIN_EIM_EB1 = _MXC_BUILD_NON_GPIO_PIN(0xD0, 0x464),
+ MX51_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0xD4, 0x468),
+ MX51_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0xD8, 0x46C),
+ MX51_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0xDC, 0x470),
+ MX51_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0xE0, 0x474),
+ MX51_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0xE4, 0x478),
+ MX51_PIN_EIM_CS2 = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0xE8, 0x47C),
+ MX51_PIN_EIM_CS3 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0xEC, 0x480),
+ MX51_PIN_EIM_CS4 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0xF0, 0x484),
+ MX51_PIN_EIM_CS5 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0xF4, 0x488),
+ MX51_PIN_EIM_DTACK = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0xF8, 0x48C),
+ MX51_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0xFC, 0x494),
+ MX51_PIN_EIM_CRE = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x100, 0x4A0),
+ MX51_PIN_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0x104, 0x4D0),
+ MX51_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(2, 3, 3, 0x108, 0x4E4),
+ MX51_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(2, 4, 3, 0x10C, 0x4E8),
+ MX51_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(2, 5, 3, 0x110, 0x4EC),
+ MX51_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(2, 6, 3, 0x114, 0x4F0),
+ MX51_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(2, 7, 3, 0x118, 0x4F4),
+ MX51_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(2, 8, 3, 0x11C, 0x4F8),
+ MX51_PIN_NANDF_RB1 = _MXC_BUILD_GPIO_PIN(2, 9, 3, 0x120, 0x4FC),
+ MX51_PIN_NANDF_RB2 = _MXC_BUILD_GPIO_PIN(2, 10, 3, 0x124, 0x500),
+ MX51_PIN_NANDF_RB3 = _MXC_BUILD_GPIO_PIN(2, 11, 3, 0x128, 0x504),
+ MX51_PIN_GPIO_NAND = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x12C, 0x514),
+ MX51_PIN_NANDF_RB4 = MX51_PIN_GPIO_NAND,
+ MX51_PIN_NANDF_RB5 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x130, 0x5D8),
+ MX51_PIN_NANDF_RB6 = _MXC_BUILD_GPIO_PIN(2, 14, 3, 0x134, 0x5DC),
+ MX51_PIN_NANDF_RB7 = _MXC_BUILD_GPIO_PIN(2, 15, 3, 0x138, 0x5E0),
+ MX51_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(2, 16, 3, 0x130, 0x518),
+ MX51_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(2, 17, 3, 0x134, 0x51C),
+ MX51_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(2, 18, 3, 0x138, 0x520),
+ MX51_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(2, 19, 3, 0x13C, 0x524),
+ MX51_PIN_NANDF_CS4 = _MXC_BUILD_GPIO_PIN(2, 20, 3, 0x140, 0x528),
+ MX51_PIN_NANDF_CS5 = _MXC_BUILD_GPIO_PIN(2, 21, 3, 0x144, 0x52C),
+ MX51_PIN_NANDF_CS6 = _MXC_BUILD_GPIO_PIN(2, 22, 3, 0x148, 0x530),
+ MX51_PIN_NANDF_CS7 = _MXC_BUILD_GPIO_PIN(2, 23, 3, 0x14C, 0x534),
+ MX51_PIN_NANDF_RDY_INT = _MXC_BUILD_GPIO_PIN(2, 24, 3, 0x150, 0x538),
+ MX51_PIN_NANDF_D15 = _MXC_BUILD_GPIO_PIN(2, 25, 3, 0x154, 0x53C),
+ MX51_PIN_NANDF_D14 = _MXC_BUILD_GPIO_PIN(2, 26, 3, 0x158, 0x540),
+ MX51_PIN_NANDF_D13 = _MXC_BUILD_GPIO_PIN(2, 27, 3, 0x15C, 0x544),
+ MX51_PIN_NANDF_D12 = _MXC_BUILD_GPIO_PIN(2, 28, 3, 0x160, 0x548),
+ MX51_PIN_NANDF_D11 = _MXC_BUILD_GPIO_PIN(2, 29, 3, 0x164, 0x54C),
+ MX51_PIN_NANDF_D10 = _MXC_BUILD_GPIO_PIN(2, 30, 3, 0x168, 0x550),
+ MX51_PIN_NANDF_D9 = _MXC_BUILD_GPIO_PIN(2, 31, 3, 0x16C, 0x554),
+ MX51_PIN_NANDF_D8 = _MXC_BUILD_GPIO_PIN(3, 0, 3, 0x170, 0x558),
+ MX51_PIN_NANDF_D7 = _MXC_BUILD_GPIO_PIN(3, 1, 3, 0x174, 0x55C),
+ MX51_PIN_NANDF_D6 = _MXC_BUILD_GPIO_PIN(3, 2, 3, 0x178, 0x560),
+ MX51_PIN_NANDF_D5 = _MXC_BUILD_GPIO_PIN(3, 3, 3, 0x17C, 0x564),
+ MX51_PIN_NANDF_D4 = _MXC_BUILD_GPIO_PIN(3, 4, 3, 0x180, 0x568),
+ MX51_PIN_NANDF_D3 = _MXC_BUILD_GPIO_PIN(3, 5, 3, 0x184, 0x56C),
+ MX51_PIN_NANDF_D2 = _MXC_BUILD_GPIO_PIN(3, 6, 3, 0x188, 0x570),
+ MX51_PIN_NANDF_D1 = _MXC_BUILD_GPIO_PIN(3, 7, 3, 0x18C, 0x574),
+ MX51_PIN_NANDF_D0 = _MXC_BUILD_GPIO_PIN(3, 8, 3, 0x190, 0x578),
+ MX51_PIN_CSI1_D8 = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x194, 0x57C),
+ MX51_PIN_CSI1_D9 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x198, 0x580),
+ MX51_PIN_CSI1_D10 = _MXC_BUILD_NON_GPIO_PIN(0x19C, 0x584),
+ MX51_PIN_CSI1_D11 = _MXC_BUILD_NON_GPIO_PIN(0x1A0, 0x588),
+ MX51_PIN_CSI1_D12 = _MXC_BUILD_NON_GPIO_PIN(0x1A4, 0x58C),
+ MX51_PIN_CSI1_D13 = _MXC_BUILD_NON_GPIO_PIN(0x1A8, 0x590),
+ MX51_PIN_CSI1_D14 = _MXC_BUILD_NON_GPIO_PIN(0x1AC, 0x594),
+ MX51_PIN_CSI1_D15 = _MXC_BUILD_NON_GPIO_PIN(0x1B0, 0x598),
+ MX51_PIN_CSI1_D16 = _MXC_BUILD_NON_GPIO_PIN(0x1B4, 0x59C),
+ MX51_PIN_CSI1_D17 = _MXC_BUILD_NON_GPIO_PIN(0x1B8, 0x5A0),
+ MX51_PIN_CSI1_D18 = _MXC_BUILD_NON_GPIO_PIN(0x1BC, 0x5A4),
+ MX51_PIN_CSI1_D19 = _MXC_BUILD_NON_GPIO_PIN(0x1C0, 0x5A8),
+ MX51_PIN_CSI1_VSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C4, 0x5AC),
+ MX51_PIN_CSI1_HSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C8, 0x5B0),
+ MX51_PIN_CSI1_PIXCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B4),
+ MX51_PIN_CSI1_MCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B8),
+ MX51_PIN_CSI1_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x860),
+ MX51_PIN_CSI2_D12 = _MXC_BUILD_GPIO_PIN(3, 9, 3, 0x1CC, 0x5BC),
+ MX51_PIN_CSI2_D13 = _MXC_BUILD_GPIO_PIN(3, 10, 3, 0x1D0, 0x5C0),
+ MX51_PIN_CSI2_D14 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1D4, 0x5C4),
+ MX51_PIN_CSI2_D15 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1D8, 0x5C8),
+ MX51_PIN_CSI2_D16 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1DC, 0x5CC),
+ MX51_PIN_CSI2_D17 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E0, 0x5D0),
+ MX51_PIN_CSI2_D18 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1E4, 0x5D4),
+ MX51_PIN_CSI2_D19 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E8, 0x5D8),
+ MX51_PIN_CSI2_VSYNC = _MXC_BUILD_GPIO_PIN(3, 13, 3, 0x1EC, 0x5DC),
+ MX51_PIN_CSI2_HSYNC = _MXC_BUILD_GPIO_PIN(3, 14, 3, 0x1F0, 0x5E0),
+ MX51_PIN_CSI2_PIXCLK = _MXC_BUILD_GPIO_PIN(3, 15, 3, 0x1F4, 0x5E4),
+ MX51_PIN_CSI2_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x81C),
+ MX51_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 3, 0x1F8, 0x5E8),
+ MX51_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(3, 17, 3, 0x1FC, 0x5EC),
+ MX51_PIN_AUD3_BB_TXD = _MXC_BUILD_GPIO_PIN(3, 18, 3, 0x200, 0x5F0),
+ MX51_PIN_AUD3_BB_RXD = _MXC_BUILD_GPIO_PIN(3, 19, 3, 0x204, 0x5F4),
+ MX51_PIN_AUD3_BB_CK = _MXC_BUILD_GPIO_PIN(3, 20, 3, 0x208, 0x5F8),
+ MX51_PIN_AUD3_BB_FS = _MXC_BUILD_GPIO_PIN(3, 21, 3, 0x20C, 0x5FC),
+ MX51_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(3, 22, 3, 0x210, 0x600),
+ MX51_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(3, 23, 3, 0x214, 0x604),
+ MX51_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(3, 24, 3, 0x218, 0x608),
+ MX51_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(3, 25, 3, 0x21C, 0x60C),
+ MX51_PIN_CSPI1_RDY = _MXC_BUILD_GPIO_PIN(3, 26, 3, 0x220, 0x610),
+ MX51_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(3, 27, 3, 0x224, 0x614),
+ MX51_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN(3, 28, 3, 0x228, 0x618),
+ MX51_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN(3, 29, 3, 0x22C, 0x61C),
+ MX51_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN(3, 30, 3, 0x230, 0x620),
+ MX51_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN(3, 31, 3, 0x234, 0x624),
+ MX51_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN(0, 20, 3, 0x238, 0x628),
+ MX51_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN(0, 21, 3, 0x23C, 0x62C),
+ MX51_PIN_UART3_RXD = _MXC_BUILD_GPIO_PIN(0, 22, 3, 0x240, 0x630),
+ MX51_PIN_UART3_TXD = _MXC_BUILD_GPIO_PIN(0, 23, 3, 0x244, 0x634),
+ MX51_PIN_OWIRE_LINE = _MXC_BUILD_GPIO_PIN(0, 24, 3, 0x248, 0x638),
+ MX51_PIN_KEY_ROW0 = _MXC_BUILD_NON_GPIO_PIN(0x24C, 0x63C),
+ MX51_PIN_KEY_ROW1 = _MXC_BUILD_NON_GPIO_PIN(0x250, 0x640),
+ MX51_PIN_KEY_ROW2 = _MXC_BUILD_NON_GPIO_PIN(0x254, 0x644),
+ MX51_PIN_KEY_ROW3 = _MXC_BUILD_NON_GPIO_PIN(0x258, 0x648),
+ MX51_PIN_KEY_COL0 = _MXC_BUILD_NON_GPIO_PIN(0x25C, 0x64C),
+ MX51_PIN_KEY_COL1 = _MXC_BUILD_NON_GPIO_PIN(0x260, 0x650),
+ MX51_PIN_KEY_COL2 = _MXC_BUILD_NON_GPIO_PIN(0x264, 0x654),
+ MX51_PIN_KEY_COL3 = _MXC_BUILD_NON_GPIO_PIN(0x268, 0x658),
+ MX51_PIN_KEY_COL4 = _MXC_BUILD_NON_GPIO_PIN(0x26C, 0x65C),
+ MX51_PIN_KEY_COL5 = _MXC_BUILD_NON_GPIO_PIN(0x270, 0x660),
+ MX51_PIN_USBH1_CLK = _MXC_BUILD_GPIO_PIN(0, 25, 2, 0x278, 0x678),
+ MX51_PIN_USBH1_DIR = _MXC_BUILD_GPIO_PIN(0, 26, 2, 0x27C, 0x67C),
+ MX51_PIN_USBH1_STP = _MXC_BUILD_GPIO_PIN(0, 27, 2, 0x280, 0x680),
+ MX51_PIN_USBH1_NXT = _MXC_BUILD_GPIO_PIN(0, 28, 2, 0x284, 0x684),
+ MX51_PIN_USBH1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 11, 2, 0x288, 0x688),
+ MX51_PIN_USBH1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 12, 2, 0x28C, 0x68C),
+ MX51_PIN_USBH1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 2, 0x290, 0x690),
+ MX51_PIN_USBH1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 14, 2, 0x294, 0x694),
+ MX51_PIN_USBH1_DATA4 = _MXC_BUILD_GPIO_PIN(0, 15, 2, 0x298, 0x698),
+ MX51_PIN_USBH1_DATA5 = _MXC_BUILD_GPIO_PIN(0, 16, 2, 0x29C, 0x69C),
+ MX51_PIN_USBH1_DATA6 = _MXC_BUILD_GPIO_PIN(0, 17, 2, 0x2A0, 0x6A0),
+ MX51_PIN_USBH1_DATA7 = _MXC_BUILD_GPIO_PIN(0, 18, 2, 0x2A4, 0x6A4),
+ MX51_PIN_DI1_PIN11 = _MXC_BUILD_GPIO_PIN(2, 0, 4, 0x2A8, 0x6A8),
+ MX51_PIN_DI1_PIN12 = _MXC_BUILD_GPIO_PIN(2, 1, 4, 0x2AC, 0x6AC),
+ MX51_PIN_DI1_PIN13 = _MXC_BUILD_GPIO_PIN(2, 2, 4, 0x2B0, 0x6B0),
+ MX51_PIN_DI1_D0_CS = _MXC_BUILD_GPIO_PIN(2, 3, 4, 0x2B4, 0x6B4),
+ MX51_PIN_DI1_D1_CS = _MXC_BUILD_GPIO_PIN(2, 4, 4, 0x2B8, 0x6B8),
+ MX51_PIN_DISPB2_SER_DIN = _MXC_BUILD_GPIO_PIN(2, 5, 4, 0x2BC, 0x6BC),
+ MX51_PIN_DISPB2_SER_DIO = _MXC_BUILD_GPIO_PIN(2, 6, 4, 0x2C0, 0x6C0),
+ MX51_PIN_DISPB2_SER_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 4, 0x2C4, 0x6C4),
+ MX51_PIN_DISPB2_SER_RS = _MXC_BUILD_GPIO_PIN(2, 8, 4, 0x2C8, 0x6C8),
+ MX51_PIN_DISP1_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x2CC, 0x6CC),
+ MX51_PIN_DISP1_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x2D0, 0x6D0),
+ MX51_PIN_DISP1_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x2D4, 0x6D4),
+ MX51_PIN_DISP1_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x2D8, 0x6D8),
+ MX51_PIN_DISP1_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x2DC, 0x6DC),
+ MX51_PIN_DISP1_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x2E0, 0x6E0),
+ MX51_PIN_DISP1_DAT6 = _MXC_BUILD_NON_GPIO_PIN(0x2E4, 0x6E4),
+ MX51_PIN_DISP1_DAT7 = _MXC_BUILD_NON_GPIO_PIN(0x2E8, 0x6E8),
+ MX51_PIN_DISP1_DAT8 = _MXC_BUILD_NON_GPIO_PIN(0x2EC, 0x6EC),
+ MX51_PIN_DISP1_DAT9 = _MXC_BUILD_NON_GPIO_PIN(0x2F0, 0x6F0),
+ MX51_PIN_DISP1_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x2F4, 0x6F4),
+ MX51_PIN_DISP1_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x2F8, 0x6F8),
+ MX51_PIN_DISP1_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x2FC, 0x6FC),
+ MX51_PIN_DISP1_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x300, 0x700),
+ MX51_PIN_DISP1_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x304, 0x704),
+ MX51_PIN_DISP1_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x308, 0x708),
+ MX51_PIN_DISP1_DAT16 = _MXC_BUILD_NON_GPIO_PIN(0x30C, 0x70C),
+ MX51_PIN_DISP1_DAT17 = _MXC_BUILD_NON_GPIO_PIN(0x310, 0x710),
+ MX51_PIN_DISP1_DAT18 = _MXC_BUILD_NON_GPIO_PIN(0x314, 0x714),
+ MX51_PIN_DISP1_DAT19 = _MXC_BUILD_NON_GPIO_PIN(0x318, 0x718),
+ MX51_PIN_DISP1_DAT20 = _MXC_BUILD_NON_GPIO_PIN(0x31C, 0x71C),
+ MX51_PIN_DISP1_DAT21 = _MXC_BUILD_NON_GPIO_PIN(0x320, 0x720),
+ MX51_PIN_DISP1_DAT22 = _MXC_BUILD_NON_GPIO_PIN(0x324, 0x724),
+ MX51_PIN_DISP1_DAT23 = _MXC_BUILD_NON_GPIO_PIN(0x328, 0x728),
+ MX51_PIN_DI1_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x32C, 0x72C),
+ MX51_PIN_DI1_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x330, 0x734),
+ MX51_PIN_DI_GP1 = _MXC_BUILD_NON_GPIO_PIN(0x334, 0x73C),
+ MX51_PIN_DI_GP2 = _MXC_BUILD_NON_GPIO_PIN(0x338, 0x740),
+ MX51_PIN_DI_GP3 = _MXC_BUILD_NON_GPIO_PIN(0x33C, 0x744),
+ MX51_PIN_DI2_PIN4 = _MXC_BUILD_NON_GPIO_PIN(0x340, 0x748),
+ MX51_PIN_DI2_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x344, 0x74C),
+ MX51_PIN_DI2_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x348, 0x750),
+ MX51_PIN_DI2_DISP_CLK = _MXC_BUILD_NON_GPIO_PIN(0x34C, 0x754),
+ MX51_PIN_DI_GP4 = _MXC_BUILD_NON_GPIO_PIN(0x350, 0x758),
+ MX51_PIN_DISP2_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x354, 0x75C),
+ MX51_PIN_DISP2_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x358, 0x760),
+ MX51_PIN_DISP2_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x35C, 0x764),
+ MX51_PIN_DISP2_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x360, 0x768),
+ MX51_PIN_DISP2_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x364, 0x76C),
+ MX51_PIN_DISP2_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x368, 0x770),
+ MX51_PIN_DISP2_DAT6 = _MXC_BUILD_GPIO_PIN(0, 19, 5, 0x36C, 0x774),
+ MX51_PIN_DISP2_DAT7 = _MXC_BUILD_GPIO_PIN(0, 29, 5, 0x370, 0x778),
+ MX51_PIN_DISP2_DAT8 = _MXC_BUILD_GPIO_PIN(0, 30, 5, 0x374, 0x77C),
+ MX51_PIN_DISP2_DAT9 = _MXC_BUILD_GPIO_PIN(0, 31, 5, 0x378, 0x780),
+ MX51_PIN_DISP2_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x37C, 0x784),
+ MX51_PIN_DISP2_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x380, 0x788),
+ MX51_PIN_DISP2_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x384, 0x78C),
+ MX51_PIN_DISP2_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x388, 0x790),
+ MX51_PIN_DISP2_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x38C, 0x794),
+ MX51_PIN_DISP2_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x390, 0x798),
+ MX51_PIN_SD1_CMD = _MXC_BUILD_NON_GPIO_PIN(0x394, 0x79C),
+ MX51_PIN_SD1_CLK = _MXC_BUILD_NON_GPIO_PIN(0x398, 0x7A0),
+ MX51_PIN_SD1_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x39C, 0x7A4),
+ MX51_PIN_SD1_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3A0, 0x7A8),
+ MX51_PIN_SD1_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3A4, 0x7AC),
+ MX51_PIN_SD1_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3A8, 0x7B0),
+ MX51_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x3AC, 0x7B4),
+ MX51_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x3B0, 0x7B8),
+ MX51_PIN_SD2_CMD = _MXC_BUILD_NON_GPIO_PIN(0x3B4, 0x7BC),
+ MX51_PIN_SD2_CLK = _MXC_BUILD_NON_GPIO_PIN(0x3B8, 0x7C0),
+ MX51_PIN_SD2_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x3BC, 0x7C4),
+ MX51_PIN_SD2_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3C0, 0x7C8),
+ MX51_PIN_SD2_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3C4, 0x7CC),
+ MX51_PIN_SD2_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3C8, 0x7D0),
+ MX51_PIN_GPIO1_2 = _MXC_BUILD_GPIO_PIN(0, 2, 0, 0x3CC, 0x7D4),
+ MX51_PIN_GPIO1_3 = _MXC_BUILD_GPIO_PIN(0, 3, 0, 0x3D0, 0x7D8),
+ MX51_PIN_PMIC_INT_REQ = _MXC_BUILD_NON_GPIO_PIN(0x3D4, 0x7FC),
+ MX51_PIN_GPIO1_4 = _MXC_BUILD_GPIO_PIN(0, 4, 0, 0x3D8, 0x804),
+ MX51_PIN_GPIO1_5 = _MXC_BUILD_GPIO_PIN(0, 5, 0, 0x3DC, 0x808),
+ MX51_PIN_GPIO1_6 = _MXC_BUILD_GPIO_PIN(0, 6, 0, 0x3E0, 0x80C),
+ MX51_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN(0, 7, 0, 0x3E4, 0x810),
+ MX51_PIN_GPIO1_8 = _MXC_BUILD_GPIO_PIN(0, 8, 0, 0x3E8, 0x814),
+ MX51_PIN_GPIO1_9 = _MXC_BUILD_GPIO_PIN(0, 9, 0, 0x3EC, 0x818),
+
+ /* The following are PADS used for drive strength */
+
+ MX51_PIN_CTL_GRP_DDRPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x820),
+ MX51_PIN_CTL_GRP_PKEDDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x838),
+ MX51_PIN_CTL_GRP_PKEADDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x890),
+ MX51_PIN_CTL_GRP_DDRAPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x87C),
+ MX51_PIN_CTL_GRP_DDRAPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x84C),
+ MX51_PIN_CTL_GRP_DDRPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x884),
+ MX51_PIN_CTL_GRP_HYSDDR0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x85C),
+ MX51_PIN_CTL_GRP_HYSDDR1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x864),
+ MX51_PIN_CTL_GRP_HYSDDR2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x86C),
+ MX51_PIN_CTL_GRP_HYSDDR3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x874),
+ MX51_PIN_CTL_GRP_DDR_SR_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x878),
+ MX51_PIN_CTL_GRP_DDR_SR_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x880),
+ MX51_PIN_CTL_GRP_DDR_SR_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x88C),
+ MX51_PIN_CTL_GRP_DDR_SR_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x89C),
+ MX51_PIN_CTL_GRP_DRAM_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A4),
+ MX51_PIN_CTL_GRP_DRAM_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8AC),
+ MX51_PIN_CTL_GRP_DRAM_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B8),
+ MX51_PIN_CTL_GRP_DRAM_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x82C),
+ MX51_PIN_CTL_GRP_INMODE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A0),
+ MX51_PIN_CTL_GRP_DDR_SR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B0),
+ MX51_PIN_CTL_GRP_EMI_DS5 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B4),
+ MX51_PIN_CTL_GRP_DDR_SR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8BC),
+ MX51_PIN_CTL_GRP_DDR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x83C),
+ MX51_PIN_CTL_GRP_DDR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x848),
+ MX51_PIN_CTL_GRP_DISP_PKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x868),
+ MX51_PIN_CTL_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A4),
+ MX51_PIN_CTL_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A8),
+ MX51_PIN_CTL_DRAM_SDWE = _MXC_BUILD_NON_GPIO_PIN(0, 0x4Ac),
+ MX51_PIN_CTL_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B0),
+ MX51_PIN_CTL_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B4),
+ MX51_PIN_CTL_DRAM_SDCLK = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B8),
+ MX51_PIN_CTL_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4BC),
+ MX51_PIN_CTL_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C0),
+ MX51_PIN_CTL_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C4),
+ MX51_PIN_CTL_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C8),
+ MX51_PIN_CTL_DRAM_CS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4CC),
+ MX51_PIN_CTL_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D0),
+ MX51_PIN_CTL_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D4),
+ MX51_PIN_CTL_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D8),
+ MX51_PIN_CTL_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4DC),
+ MX51_PIN_CTL_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4E0),
+};
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARCH_MX5_MX5X_PINS_H__ */
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+u32 get_cpu_rev(void);
+#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
+void sdelay(unsigned long);
+
+#endif
+++ /dev/null
-/*
- * needed for arch/arm/cpu/armv7/mx51/lowlevel_init.S
- *
- * These should be auto-generated
- */
-/* CCM */
-#define CLKCTL_CCR 0x00
-#define CLKCTL_CCDR 0x04
-#define CLKCTL_CSR 0x08
-#define CLKCTL_CCSR 0x0C
-#define CLKCTL_CACRR 0x10
-#define CLKCTL_CBCDR 0x14
-#define CLKCTL_CBCMR 0x18
-#define CLKCTL_CSCMR1 0x1C
-#define CLKCTL_CSCMR2 0x20
-#define CLKCTL_CSCDR1 0x24
-#define CLKCTL_CS1CDR 0x28
-#define CLKCTL_CS2CDR 0x2C
-#define CLKCTL_CDCDR 0x30
-#define CLKCTL_CHSCCDR 0x34
-#define CLKCTL_CSCDR2 0x38
-#define CLKCTL_CSCDR3 0x3C
-#define CLKCTL_CSCDR4 0x40
-#define CLKCTL_CWDR 0x44
-#define CLKCTL_CDHIPR 0x48
-#define CLKCTL_CDCR 0x4C
-#define CLKCTL_CTOR 0x50
-#define CLKCTL_CLPCR 0x54
-#define CLKCTL_CISR 0x58
-#define CLKCTL_CIMR 0x5C
-#define CLKCTL_CCOSR 0x60
-#define CLKCTL_CGPR 0x64
-#define CLKCTL_CCGR0 0x68
-#define CLKCTL_CCGR1 0x6C
-#define CLKCTL_CCGR2 0x70
-#define CLKCTL_CCGR3 0x74
-#define CLKCTL_CCGR4 0x78
-#define CLKCTL_CCGR5 0x7C
-#define CLKCTL_CCGR6 0x80
-#define CLKCTL_CMEOR 0x84
-
-/* DPLL */
-#define PLL_DP_CTL 0x00
-#define PLL_DP_CONFIG 0x04
-#define PLL_DP_OP 0x08
-#define PLL_DP_MFD 0x0C
-#define PLL_DP_MFN 0x10
-#define PLL_DP_HFS_OP 0x1C
-#define PLL_DP_HFS_MFD 0x20
-#define PLL_DP_HFS_MFN 0x24
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H
-
-enum mxc_clock {
- MXC_ARM_CLK = 0,
- MXC_AHB_CLK,
- MXC_IPG_CLK,
- MXC_IPG_PERCLK,
- MXC_UART_CLK,
- MXC_CSPI_CLK,
- MXC_FEC_CLK,
-};
-
-unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref);
-
-u32 imx_get_uartclk(void);
-u32 imx_get_fecclk(void);
-unsigned int mxc_get_clock(enum mxc_clock clk);
-
-#endif /* __ASM_ARCH_CLOCK_H */
+++ /dev/null
-/*
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
-#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
-
-#define MXC_CCM_BASE CCM_BASE_ADDR
-
-/* DPLL register mapping structure */
-struct mxc_pll_reg {
- u32 ctrl;
- u32 config;
- u32 op;
- u32 mfd;
- u32 mfn;
- u32 mfn_minus;
- u32 mfn_plus;
- u32 hfs_op;
- u32 hfs_mfd;
- u32 hfs_mfn;
- u32 mfn_togc;
- u32 destat;
-};
-
-/* Register maping of CCM*/
-struct mxc_ccm_reg {
- u32 ccr; /* 0x0000 */
- u32 ccdr;
- u32 csr;
- u32 ccsr;
- u32 cacrr; /* 0x0010*/
- u32 cbcdr;
- u32 cbcmr;
- u32 cscmr1;
- u32 cscmr2; /* 0x0020 */
- u32 cscdr1;
- u32 cs1cdr;
- u32 cs2cdr;
- u32 cdcdr; /* 0x0030 */
- u32 chscdr;
- u32 cscdr2;
- u32 cscdr3;
- u32 cscdr4; /* 0x0040 */
- u32 cwdr;
- u32 cdhipr;
- u32 cdcr;
- u32 ctor; /* 0x0050 */
- u32 clpcr;
- u32 cisr;
- u32 cimr;
- u32 ccosr; /* 0x0060 */
- u32 cgpr;
- u32 CCGR0;
- u32 CCGR1;
- u32 CCGR2; /* 0x0070 */
- u32 CCGR3;
- u32 CCGR4;
- u32 CCGR5;
- u32 CCGR6; /* 0x0080 */
- u32 cmeor;
-};
-
-/* Define the bits in register CACRR */
-#define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
-#define MXC_CCM_CACRR_ARM_PODF_MASK 0x7
-
-/* Define the bits in register CBCDR */
-#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
-#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
-#define MXC_CCM_CBCDR_EMI_PODF_OFFSET 22
-#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
-#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET 19
-#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
-#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET 16
-#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
-#define MXC_CCM_CBCDR_NFC_PODF_OFFSET 13
-#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
-#define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10
-#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
-#define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8
-#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
-#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET 6
-#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
-#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET 3
-#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
-#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET 0
-#define MXC_CCM_CBCDR_PERCLK_PODF_MASK 0x7
-
-/* Define the bits in register CSCMR1 */
-#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET 30
-#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
-#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET 28
-#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
-#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET 26
-#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
-#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET 24
-#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
-#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET 22
-#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
-#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET 20
-#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
-#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
-#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
-#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET 16
-#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 14
-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
-#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
-#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
-#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET 8
-#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
-#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7)
-#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
-#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET 4
-#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
-#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET 2
-#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
-#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
-#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL 0x1
-
-/* Define the bits in register CSCDR2 */
-#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET 25
-#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
-#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET 19
-#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
-#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET 16
-#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16)
-#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET 9
-#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9)
-#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET 6
-#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6)
-#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET 0
-#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK 0x3F
-
-/* Define the bits in register CBCMR */
-#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
-#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
-#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET 12
-#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
-#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET 10
-#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
-#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET 8
-#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
-#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET 6
-#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
-#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET 4
-#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
-#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
-#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
-
-/* Define the bits in register CSCDR1 */
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET 22
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET 19
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET 16
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
-#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET 14
-#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET 11
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
-#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET 3
-#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x7
-
-#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
+++ /dev/null
-/*
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_MXC_MX51_H__
-#define __ASM_ARCH_MXC_MX51_H__
-
-/*
- * IRAM
- */
-#define IRAM_BASE_ADDR 0x1FFE8000 /* internal ram */
-/*
- * Graphics Memory of GPU
- */
-#define GPU_BASE_ADDR 0x20000000
-#define GPU_CTRL_BASE_ADDR 0x30000000
-#define IPU_CTRL_BASE_ADDR 0x40000000
-/*
- * Debug
- */
-#define DEBUG_BASE_ADDR 0x60000000
-#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000)
-#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000)
-#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000)
-#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000)
-#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000)
-#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000)
-#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000)
-#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000)
-
-/*
- * SPBA global module enabled #0
- */
-#define SPBA0_BASE_ADDR 0x70000000
-
-#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
-#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
-#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
-#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
-#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
-#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
-#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
-#define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000)
-#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000)
-#define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000)
-#define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000)
-#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
-
-/*
- * AIPS 1
- */
-#define AIPS1_BASE_ADDR 0x73F00000
-
-#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
-#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
-#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
-#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
-#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
-#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
-#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
-#define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
-#define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
-#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
-#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
-#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
-#define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
-#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
-#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
-#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
-#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000)
-#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000)
-#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000)
-#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000)
-
-/*
- * AIPS 2
- */
-#define AIPS2_BASE_ADDR 0x83F00000
-
-#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
-#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
-#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
-#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
-#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
-#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
-#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000)
-#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
-#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000)
-#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
-#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
-#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000)
-#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000)
-#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000)
-#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
-#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
-#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
-#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
-#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
-#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
-#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000)
-#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000)
-#define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000)
-#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00)
-#define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
-#define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
-#define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000)
-#define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000)
-#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
-#define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000)
-#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000)
-#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000)
-
-#define TZIC_BASE_ADDR 0x8FFFC000
-
-/*
- * Memory regions and CS
- */
-#define CSD0_BASE_ADDR 0x90000000
-#define CSD1_BASE_ADDR 0xA0000000
-#define CS0_BASE_ADDR 0xB0000000
-#define CS1_BASE_ADDR 0xB8000000
-#define CS2_BASE_ADDR 0xC0000000
-#define CS3_BASE_ADDR 0xC8000000
-#define CS4_BASE_ADDR 0xCC000000
-#define CS5_BASE_ADDR 0xCE000000
-
-/*
- * NFC
- */
-#define NFC_BASE_ADDR_AXI 0xCFFF0000 /* NAND flash AXI */
-
-/*!
- * Number of GPIO port as defined in the IC Spec
- */
-#define GPIO_PORT_NUM 4
-/*!
- * Number of GPIO pins per port
- */
-#define GPIO_NUM_PIN 32
-
-#define IIM_SREV 0x24
-#define ROM_SI_REV 0x48
-
-#define NFC_BUF_SIZE 0x1000
-
-/* M4IF */
-#define M4IF_FBPM0 0x40
-#define M4IF_FIDBP 0x48
-
-/* Assuming 24MHz input clock with doubler ON */
-/* MFI PDF */
-#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
-#define DP_MFD_850 (48 - 1)
-#define DP_MFN_850 41
-
-#define DP_OP_800 ((8 << 4) + ((1 - 1) << 0))
-#define DP_MFD_800 (3 - 1)
-#define DP_MFN_800 1
-
-#define DP_OP_700 ((7 << 4) + ((1 - 1) << 0))
-#define DP_MFD_700 (24 - 1)
-#define DP_MFN_700 7
-
-#define DP_OP_665 ((6 << 4) + ((1 - 1) << 0))
-#define DP_MFD_665 (96 - 1)
-#define DP_MFN_665 89
-
-#define DP_OP_532 ((5 << 4) + ((1 - 1) << 0))
-#define DP_MFD_532 (24 - 1)
-#define DP_MFN_532 13
-
-#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0))
-#define DP_MFD_400 (3 - 1)
-#define DP_MFN_400 1
-
-#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
-#define DP_MFD_216 (4 - 1)
-#define DP_MFN_216 3
-
-#define CHIP_REV_1_0 0x10
-#define CHIP_REV_1_1 0x11
-#define CHIP_REV_2_0 0x20
-#define CHIP_REV_2_5 0x25
-#define CHIP_REV_3_0 0x30
-
-#define BOARD_REV_1_0 0x0
-#define BOARD_REV_2_0 0x1
-
-#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
-#include <asm/types.h>
-
-#define __REG(x) (*((volatile u32 *)(x)))
-#define __REG16(x) (*((volatile u16 *)(x)))
-#define __REG8(x) (*((volatile u8 *)(x)))
-
-struct clkctl {
- u32 ccr;
- u32 ccdr;
- u32 csr;
- u32 ccsr;
- u32 cacrr;
- u32 cbcdr;
- u32 cbcmr;
- u32 cscmr1;
- u32 cscmr2;
- u32 cscdr1;
- u32 cs1cdr;
- u32 cs2cdr;
- u32 cdcdr;
- u32 chsccdr;
- u32 cscdr2;
- u32 cscdr3;
- u32 cscdr4;
- u32 cwdr;
- u32 cdhipr;
- u32 cdcr;
- u32 ctor;
- u32 clpcr;
- u32 cisr;
- u32 cimr;
- u32 ccosr;
- u32 cgpr;
- u32 ccgr0;
- u32 ccgr1;
- u32 ccgr2;
- u32 ccgr3;
- u32 ccgr4;
- u32 ccgr5;
- u32 ccgr6;
- u32 cmeor;
-};
-
-/* WEIM registers */
-struct weim {
- u32 csgcr1;
- u32 csgcr2;
- u32 csrcr1;
- u32 csrcr2;
- u32 cswcr1;
- u32 cswcr2;
-};
-
-/* GPIO Registers */
-struct gpio_regs {
- u32 gpio_dr;
- u32 gpio_dir;
- u32 gpio_psr;
-};
-
-/* System Reset Controller (SRC) */
-struct src {
- u32 scr;
- u32 sbmr;
- u32 srsr;
- u32 reserved1[2];
- u32 sisr;
- u32 simr;
-};
-#endif /* __ASSEMBLER__*/
-
-#endif /* __ASM_ARCH_MXC_MX51_H__ */
+++ /dev/null
-/*
- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __MACH_MX51_IOMUX_H__
-#define __MACH_MX51_IOMUX_H__
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx51_pins.h>
-
-typedef unsigned int iomux_pin_name_t;
-
-/* various IOMUX output functions */
-typedef enum iomux_config {
- IOMUX_CONFIG_ALT0, /*!< used as alternate function 0 */
- IOMUX_CONFIG_ALT1, /*!< used as alternate function 1 */
- IOMUX_CONFIG_ALT2, /*!< used as alternate function 2 */
- IOMUX_CONFIG_ALT3, /*!< used as alternate function 3 */
- IOMUX_CONFIG_ALT4, /*!< used as alternate function 4 */
- IOMUX_CONFIG_ALT5, /*!< used as alternate function 5 */
- IOMUX_CONFIG_ALT6, /*!< used as alternate function 6 */
- IOMUX_CONFIG_ALT7, /*!< used as alternate function 7 */
- IOMUX_CONFIG_GPIO, /*!< added to help user use GPIO mode */
- IOMUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */
-} iomux_pin_cfg_t;
-
-/* various IOMUX pad functions */
-typedef enum iomux_pad_config {
- PAD_CTL_SRE_SLOW = 0x0 << 0, /* Slow slew rate */
- PAD_CTL_SRE_FAST = 0x1 << 0, /* Fast slew rate */
- PAD_CTL_DRV_LOW = 0x0 << 1, /* Low drive strength */
- PAD_CTL_DRV_MEDIUM = 0x1 << 1, /* Medium drive strength */
- PAD_CTL_DRV_HIGH = 0x2 << 1, /* High drive strength */
- PAD_CTL_DRV_MAX = 0x3 << 1, /* Max drive strength */
- PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3, /* Opendrain disable */
- PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3,/* Opendrain enable */
- PAD_CTL_100K_PD = 0x0 << 4, /* 100Kohm pulldown */
- PAD_CTL_47K_PU = 0x1 << 4, /* 47Kohm pullup */
- PAD_CTL_100K_PU = 0x2 << 4, /* 100Kohm pullup */
- PAD_CTL_22K_PU = 0x3 << 4, /* 22Kohm pullup */
- PAD_CTL_PUE_KEEPER = 0x0 << 6, /* enable pulldown */
- PAD_CTL_PUE_PULL = 0x1 << 6, /* enable pullup */
- PAD_CTL_PKE_NONE = 0x0 << 7, /* Disable pullup/pulldown */
- PAD_CTL_PKE_ENABLE = 0x1 << 7, /* Enable pullup/pulldown */
- PAD_CTL_HYS_NONE = 0x0 << 8, /* Hysteresis disabled */
- PAD_CTL_HYS_ENABLE = 0x1 << 8, /* Hysteresis enabled */
- PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9,/* DDR input CMOS */
- PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,/* DDR input DDR */
- PAD_CTL_DRV_VOT_LOW = 0x0 << 13, /* Low voltage mode */
- PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,/* High voltage mode */
-} iomux_pad_config_t;
-
-/* various IOMUX input select register index */
-typedef enum iomux_input_select {
- MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
- MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
- MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT,
- MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT,
- MUX_IN_CCM_IPP_DI_CLK_SELECT_INPUT,
- /* TO2 */
- MUX_IN_CCM_IPP_DI1_CLK_SELECT_INPUT,
- MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
- MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
- MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
- MUX_IN_CSPI_IPP_IND_MISO_SELECT_INPUT,
- MUX_IN_CSPI_IPP_IND_MOSI_SELECT_INPUT,
- MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
- MUX_IN_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
- MUX_IN_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
- MUX_IN_DPLLIP1_L1T_TOG_EN_SELECT_INPUT,
- /* TO2 */
- MUX_IN_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
- MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT,
- MUX_IN_EMI_IPP_IND_RDY_INT_SELECT_INPUT,
- MUX_IN_ESDHC3_IPP_DAT0_IN_SELECT_INPUT,
- MUX_IN_ESDHC3_IPP_DAT1_IN_SELECT_INPUT,
- MUX_IN_ESDHC3_IPP_DAT2_IN_SELECT_INPUT,
- MUX_IN_ESDHC3_IPP_DAT3_IN_SELECT_INPUT,
- MUX_IN_FEC_FEC_COL_SELECT_INPUT,
- MUX_IN_FEC_FEC_CRS_SELECT_INPUT,
- MUX_IN_FEC_FEC_MDI_SELECT_INPUT,
- MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT,
- MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT,
- MUX_IN_FEC_FEC_RDATA_2_SELECT_INPUT,
- MUX_IN_FEC_FEC_RDATA_3_SELECT_INPUT,
- MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT,
- MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT,
- MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT,
- MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT,
- MUX_IN_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT,
- MUX_IN_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT,
- MUX_IN_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT,
- MUX_IN_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
- MUX_IN_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT,
- MUX_IN_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT,
- MUX_IN_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT,
- MUX_IN_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT,
- /* TO2 */
- MUX_IN_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT,
- MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
- MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT,
- /* TO2 */
- MUX_IN_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT,
- /* TO2 */
- MUX_IN_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT,
- MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT,
- MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT,
- MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT,
- MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT,
- MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
-
- MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
-
- MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
-
- MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT,
- MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT,
- MUX_IN_KPP_IPP_IND_ROW_4_SELECT_INPUT,
- MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT,
- MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT,
- MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT,
- MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT,
- MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
- MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT,
- MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
- MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT,
- MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT,
- MUX_INPUT_NUM_MUX,
-} iomux_input_select_t;
-
-/* various IOMUX input functions */
-typedef enum iomux_input_config {
- INPUT_CTL_PATH0 = 0x0,
- INPUT_CTL_PATH1,
- INPUT_CTL_PATH2,
- INPUT_CTL_PATH3,
- INPUT_CTL_PATH4,
- INPUT_CTL_PATH5,
- INPUT_CTL_PATH6,
- INPUT_CTL_PATH7,
-} iomux_input_config_t;
-
-void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
-unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin);
-void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
-
-#endif /* __MACH_MX51_IOMUX_H__ */
+++ /dev/null
-/*
- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_MXC_MX51_PINS_H__
-#define __ASM_ARCH_MXC_MX51_PINS_H__
-
-#ifndef __ASSEMBLY__
-
-/*
- * In order to identify pins more effectively, each mux-controlled pin's
- * enumerated value is constructed in the following way:
- *
- * -------------------------------------------------------------------
- * 31-29 | 28 - 24 | 23 - 21 | 20 - 10| 9 - 0
- * -------------------------------------------------------------------
- * IO_P | IO_I | GPIO_I | PAD_I | MUX_I
- * -------------------------------------------------------------------
- *
- * Bit 0 to 9 contains MUX_I used to identify the register
- * offset (0-based. base is IOMUX_module_base) defined in the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The
- * similar field definitions are used for the pad control register.
- * The IOMUX controller can be split in two parts. At the begeinning,
- * there is the register definitions for the multiplexing each pin.
- * Then there is a set of registers (PAD_I) to configure each pin
- * (pullup, pulldown, etc).
- * PAD_I defines the offset of the pad register for each pin.
- * GPIO_I defines, if available, the number of gpio that can be
- * connected to that pad
- * IO_I defines the multiplexer mode required to set the pad in gpio mode
- * IO_P defines the gpio structure (gpio1..gpio4) the pad belongs
- *
- * For example, the MX51_PIN_ETM_D0 is defined in the enumeration:
- * ( (0x28 - MUX_I_START) << MUX_I)|( (0x250 - PAD_I_START) << PAD_I)
- * It means the mux control register is at register offset 0x28. The pad control
- * register offset is: 0x250 and also occupy the least significant bits
- * within the register.
- */
-
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * MUX control register offset
- */
-#define MUX_I 0
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * PAD control register offset
- */
-#define PAD_I 10
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent which
- * mux mode is for GPIO (0-based)
- */
-#define GPIO_I 21
-
-#define MUX_IO_P 29
-#define MUX_IO_I 24
-#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \
- GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
- ((1 << (MUX_IO_P - MUX_IO_I)) - 1)))
-#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin))
-#define GPIO_TO_PORT(n) (n / GPIO_NUM_PIN)
-#define GPIO_TO_INDEX(n) (n % GPIO_NUM_PIN)
-
-#define NON_GPIO_PORT 0x7
-#define PIN_TO_MUX_MASK ((1 << (PAD_I - MUX_I)) - 1)
-#define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1)
-#define PIN_TO_ALT_GPIO_MASK ((1 << (MUX_IO_I - GPIO_I)) - 1)
-
-#define NON_MUX_I PIN_TO_MUX_MASK
-#define MUX_I_START 0x001C
-#define PAD_I_START 0x3F0
-#define INPUT_CTL_START 0x8C4
-#define INPUT_CTL_START_TO1 0x928
-#define MUX_I_END (PAD_I_START - 4)
-
-#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \
- (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
- ((mi) << MUX_I) | \
- ((pi - PAD_I_START) << PAD_I) | \
- ((ga) << GPIO_I))
-
-#define _MXC_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \
- _MXC_BUILD_PIN(gp, gi, ga, mi, pi)
-
-#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \
- _MXC_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi)
-
-#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK)
-#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK)
-#define PIN_TO_ALT_GPIO(pin) ((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK)
-#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2)
-
-/*
- * This enumeration is constructed based on the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the MX51 IC Spec. Each enumerated
- * value is constructed based on the rules described above.
- */
-enum iomux_pins {
- MX51_PIN_EIM_DA0 = _MXC_BUILD_NON_GPIO_PIN(0x1C, 0x7A8),
- MX51_PIN_EIM_DA1 = _MXC_BUILD_NON_GPIO_PIN(0x20, 0x7A8),
- MX51_PIN_EIM_DA2 = _MXC_BUILD_NON_GPIO_PIN(0x24, 0x7A8),
- MX51_PIN_EIM_DA3 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x7A8),
- MX51_PIN_EIM_DA4 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x7AC),
- MX51_PIN_EIM_DA5 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x7AC),
- MX51_PIN_EIM_DA6 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x7AC),
- MX51_PIN_EIM_DA7 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x7AC),
- MX51_PIN_EIM_DA8 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x7B0),
- MX51_PIN_EIM_DA9 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x7B0),
- MX51_PIN_EIM_DA10 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x7B0),
- MX51_PIN_EIM_DA11 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x7B0),
- MX51_PIN_EIM_DA12 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x7BC),
- MX51_PIN_EIM_DA13 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x7BC),
- MX51_PIN_EIM_DA14 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x7BC),
- MX51_PIN_EIM_DA15 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x7BC),
- MX51_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x5C, 0x3F0),
- MX51_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x60, 0x3F4),
- MX51_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x64, 0x3F8),
- MX51_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x68, 0x3FC),
- MX51_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x6C, 0x400),
- MX51_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x70, 0x404),
- MX51_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x74, 0x408),
- MX51_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x78, 0x40C),
- MX51_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x7C, 0x410),
- MX51_PIN_EIM_D25 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x414),
- MX51_PIN_EIM_D26 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x418),
- MX51_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x88, 0x41C),
- MX51_PIN_EIM_D28 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x420),
- MX51_PIN_EIM_D29 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x424),
- MX51_PIN_EIM_D30 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x428),
- MX51_PIN_EIM_D31 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x42C),
- MX51_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x9C, 0x430),
- MX51_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0xA0, 0x434),
- MX51_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0xA4, 0x438),
- MX51_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0xA8, 0x43C),
- MX51_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0xAC, 0x440),
- MX51_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0xB0, 0x444),
- MX51_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0xB4, 0x448),
- MX51_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0xB8, 0x44C),
- MX51_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0xBC, 0x450),
- MX51_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0xC0, 0x454),
- MX51_PIN_EIM_A26 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0xC4, 0x458),
- MX51_PIN_EIM_A27 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0xC8, 0x45C),
- MX51_PIN_EIM_EB0 = _MXC_BUILD_NON_GPIO_PIN(0xCC, 0x460),
- MX51_PIN_EIM_EB1 = _MXC_BUILD_NON_GPIO_PIN(0xD0, 0x464),
- MX51_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0xD4, 0x468),
- MX51_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0xD8, 0x46C),
- MX51_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0xDC, 0x470),
- MX51_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0xE0, 0x474),
- MX51_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0xE4, 0x478),
- MX51_PIN_EIM_CS2 = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0xE8, 0x47C),
- MX51_PIN_EIM_CS3 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0xEC, 0x480),
- MX51_PIN_EIM_CS4 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0xF0, 0x484),
- MX51_PIN_EIM_CS5 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0xF4, 0x488),
- MX51_PIN_EIM_DTACK = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0xF8, 0x48C),
- MX51_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0xFC, 0x494),
- MX51_PIN_EIM_CRE = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x100, 0x4A0),
- MX51_PIN_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0x104, 0x4D0),
- MX51_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(2, 3, 3, 0x108, 0x4E4),
- MX51_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(2, 4, 3, 0x10C, 0x4E8),
- MX51_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(2, 5, 3, 0x110, 0x4EC),
- MX51_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(2, 6, 3, 0x114, 0x4F0),
- MX51_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(2, 7, 3, 0x118, 0x4F4),
- MX51_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(2, 8, 3, 0x11C, 0x4F8),
- MX51_PIN_NANDF_RB1 = _MXC_BUILD_GPIO_PIN(2, 9, 3, 0x120, 0x4FC),
- MX51_PIN_NANDF_RB2 = _MXC_BUILD_GPIO_PIN(2, 10, 3, 0x124, 0x500),
- MX51_PIN_NANDF_RB3 = _MXC_BUILD_GPIO_PIN(2, 11, 3, 0x128, 0x504),
- MX51_PIN_GPIO_NAND = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x12C, 0x514),
- MX51_PIN_NANDF_RB4 = MX51_PIN_GPIO_NAND,
- MX51_PIN_NANDF_RB5 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x130, 0x5D8),
- MX51_PIN_NANDF_RB6 = _MXC_BUILD_GPIO_PIN(2, 14, 3, 0x134, 0x5DC),
- MX51_PIN_NANDF_RB7 = _MXC_BUILD_GPIO_PIN(2, 15, 3, 0x138, 0x5E0),
- MX51_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(2, 16, 3, 0x130, 0x518),
- MX51_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(2, 17, 3, 0x134, 0x51C),
- MX51_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(2, 18, 3, 0x138, 0x520),
- MX51_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(2, 19, 3, 0x13C, 0x524),
- MX51_PIN_NANDF_CS4 = _MXC_BUILD_GPIO_PIN(2, 20, 3, 0x140, 0x528),
- MX51_PIN_NANDF_CS5 = _MXC_BUILD_GPIO_PIN(2, 21, 3, 0x144, 0x52C),
- MX51_PIN_NANDF_CS6 = _MXC_BUILD_GPIO_PIN(2, 22, 3, 0x148, 0x530),
- MX51_PIN_NANDF_CS7 = _MXC_BUILD_GPIO_PIN(2, 23, 3, 0x14C, 0x534),
- MX51_PIN_NANDF_RDY_INT = _MXC_BUILD_GPIO_PIN(2, 24, 3, 0x150, 0x538),
- MX51_PIN_NANDF_D15 = _MXC_BUILD_GPIO_PIN(2, 25, 3, 0x154, 0x53C),
- MX51_PIN_NANDF_D14 = _MXC_BUILD_GPIO_PIN(2, 26, 3, 0x158, 0x540),
- MX51_PIN_NANDF_D13 = _MXC_BUILD_GPIO_PIN(2, 27, 3, 0x15C, 0x544),
- MX51_PIN_NANDF_D12 = _MXC_BUILD_GPIO_PIN(2, 28, 3, 0x160, 0x548),
- MX51_PIN_NANDF_D11 = _MXC_BUILD_GPIO_PIN(2, 29, 3, 0x164, 0x54C),
- MX51_PIN_NANDF_D10 = _MXC_BUILD_GPIO_PIN(2, 30, 3, 0x168, 0x550),
- MX51_PIN_NANDF_D9 = _MXC_BUILD_GPIO_PIN(2, 31, 3, 0x16C, 0x554),
- MX51_PIN_NANDF_D8 = _MXC_BUILD_GPIO_PIN(3, 0, 3, 0x170, 0x558),
- MX51_PIN_NANDF_D7 = _MXC_BUILD_GPIO_PIN(3, 1, 3, 0x174, 0x55C),
- MX51_PIN_NANDF_D6 = _MXC_BUILD_GPIO_PIN(3, 2, 3, 0x178, 0x560),
- MX51_PIN_NANDF_D5 = _MXC_BUILD_GPIO_PIN(3, 3, 3, 0x17C, 0x564),
- MX51_PIN_NANDF_D4 = _MXC_BUILD_GPIO_PIN(3, 4, 3, 0x180, 0x568),
- MX51_PIN_NANDF_D3 = _MXC_BUILD_GPIO_PIN(3, 5, 3, 0x184, 0x56C),
- MX51_PIN_NANDF_D2 = _MXC_BUILD_GPIO_PIN(3, 6, 3, 0x188, 0x570),
- MX51_PIN_NANDF_D1 = _MXC_BUILD_GPIO_PIN(3, 7, 3, 0x18C, 0x574),
- MX51_PIN_NANDF_D0 = _MXC_BUILD_GPIO_PIN(3, 8, 3, 0x190, 0x578),
- MX51_PIN_CSI1_D8 = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x194, 0x57C),
- MX51_PIN_CSI1_D9 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x198, 0x580),
- MX51_PIN_CSI1_D10 = _MXC_BUILD_NON_GPIO_PIN(0x19C, 0x584),
- MX51_PIN_CSI1_D11 = _MXC_BUILD_NON_GPIO_PIN(0x1A0, 0x588),
- MX51_PIN_CSI1_D12 = _MXC_BUILD_NON_GPIO_PIN(0x1A4, 0x58C),
- MX51_PIN_CSI1_D13 = _MXC_BUILD_NON_GPIO_PIN(0x1A8, 0x590),
- MX51_PIN_CSI1_D14 = _MXC_BUILD_NON_GPIO_PIN(0x1AC, 0x594),
- MX51_PIN_CSI1_D15 = _MXC_BUILD_NON_GPIO_PIN(0x1B0, 0x598),
- MX51_PIN_CSI1_D16 = _MXC_BUILD_NON_GPIO_PIN(0x1B4, 0x59C),
- MX51_PIN_CSI1_D17 = _MXC_BUILD_NON_GPIO_PIN(0x1B8, 0x5A0),
- MX51_PIN_CSI1_D18 = _MXC_BUILD_NON_GPIO_PIN(0x1BC, 0x5A4),
- MX51_PIN_CSI1_D19 = _MXC_BUILD_NON_GPIO_PIN(0x1C0, 0x5A8),
- MX51_PIN_CSI1_VSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C4, 0x5AC),
- MX51_PIN_CSI1_HSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C8, 0x5B0),
- MX51_PIN_CSI1_PIXCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B4),
- MX51_PIN_CSI1_MCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B8),
- MX51_PIN_CSI1_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x860),
- MX51_PIN_CSI2_D12 = _MXC_BUILD_GPIO_PIN(3, 9, 3, 0x1CC, 0x5BC),
- MX51_PIN_CSI2_D13 = _MXC_BUILD_GPIO_PIN(3, 10, 3, 0x1D0, 0x5C0),
- MX51_PIN_CSI2_D14 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1D4, 0x5C4),
- MX51_PIN_CSI2_D15 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1D8, 0x5C8),
- MX51_PIN_CSI2_D16 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1DC, 0x5CC),
- MX51_PIN_CSI2_D17 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E0, 0x5D0),
- MX51_PIN_CSI2_D18 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1E4, 0x5D4),
- MX51_PIN_CSI2_D19 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E8, 0x5D8),
- MX51_PIN_CSI2_VSYNC = _MXC_BUILD_GPIO_PIN(3, 13, 3, 0x1EC, 0x5DC),
- MX51_PIN_CSI2_HSYNC = _MXC_BUILD_GPIO_PIN(3, 14, 3, 0x1F0, 0x5E0),
- MX51_PIN_CSI2_PIXCLK = _MXC_BUILD_GPIO_PIN(3, 15, 3, 0x1F4, 0x5E4),
- MX51_PIN_CSI2_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x81C),
- MX51_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 3, 0x1F8, 0x5E8),
- MX51_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(3, 17, 3, 0x1FC, 0x5EC),
- MX51_PIN_AUD3_BB_TXD = _MXC_BUILD_GPIO_PIN(3, 18, 3, 0x200, 0x5F0),
- MX51_PIN_AUD3_BB_RXD = _MXC_BUILD_GPIO_PIN(3, 19, 3, 0x204, 0x5F4),
- MX51_PIN_AUD3_BB_CK = _MXC_BUILD_GPIO_PIN(3, 20, 3, 0x208, 0x5F8),
- MX51_PIN_AUD3_BB_FS = _MXC_BUILD_GPIO_PIN(3, 21, 3, 0x20C, 0x5FC),
- MX51_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(3, 22, 3, 0x210, 0x600),
- MX51_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(3, 23, 3, 0x214, 0x604),
- MX51_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(3, 24, 3, 0x218, 0x608),
- MX51_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(3, 25, 3, 0x21C, 0x60C),
- MX51_PIN_CSPI1_RDY = _MXC_BUILD_GPIO_PIN(3, 26, 3, 0x220, 0x610),
- MX51_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(3, 27, 3, 0x224, 0x614),
- MX51_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN(3, 28, 3, 0x228, 0x618),
- MX51_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN(3, 29, 3, 0x22C, 0x61C),
- MX51_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN(3, 30, 3, 0x230, 0x620),
- MX51_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN(3, 31, 3, 0x234, 0x624),
- MX51_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN(0, 20, 3, 0x238, 0x628),
- MX51_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN(0, 21, 3, 0x23C, 0x62C),
- MX51_PIN_UART3_RXD = _MXC_BUILD_GPIO_PIN(0, 22, 3, 0x240, 0x630),
- MX51_PIN_UART3_TXD = _MXC_BUILD_GPIO_PIN(0, 23, 3, 0x244, 0x634),
- MX51_PIN_OWIRE_LINE = _MXC_BUILD_GPIO_PIN(0, 24, 3, 0x248, 0x638),
- MX51_PIN_KEY_ROW0 = _MXC_BUILD_NON_GPIO_PIN(0x24C, 0x63C),
- MX51_PIN_KEY_ROW1 = _MXC_BUILD_NON_GPIO_PIN(0x250, 0x640),
- MX51_PIN_KEY_ROW2 = _MXC_BUILD_NON_GPIO_PIN(0x254, 0x644),
- MX51_PIN_KEY_ROW3 = _MXC_BUILD_NON_GPIO_PIN(0x258, 0x648),
- MX51_PIN_KEY_COL0 = _MXC_BUILD_NON_GPIO_PIN(0x25C, 0x64C),
- MX51_PIN_KEY_COL1 = _MXC_BUILD_NON_GPIO_PIN(0x260, 0x650),
- MX51_PIN_KEY_COL2 = _MXC_BUILD_NON_GPIO_PIN(0x264, 0x654),
- MX51_PIN_KEY_COL3 = _MXC_BUILD_NON_GPIO_PIN(0x268, 0x658),
- MX51_PIN_KEY_COL4 = _MXC_BUILD_NON_GPIO_PIN(0x26C, 0x65C),
- MX51_PIN_KEY_COL5 = _MXC_BUILD_NON_GPIO_PIN(0x270, 0x660),
- MX51_PIN_USBH1_CLK = _MXC_BUILD_GPIO_PIN(0, 25, 2, 0x278, 0x678),
- MX51_PIN_USBH1_DIR = _MXC_BUILD_GPIO_PIN(0, 26, 2, 0x27C, 0x67C),
- MX51_PIN_USBH1_STP = _MXC_BUILD_GPIO_PIN(0, 27, 2, 0x280, 0x680),
- MX51_PIN_USBH1_NXT = _MXC_BUILD_GPIO_PIN(0, 28, 2, 0x284, 0x684),
- MX51_PIN_USBH1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 11, 2, 0x288, 0x688),
- MX51_PIN_USBH1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 12, 2, 0x28C, 0x68C),
- MX51_PIN_USBH1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 2, 0x290, 0x690),
- MX51_PIN_USBH1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 14, 2, 0x294, 0x694),
- MX51_PIN_USBH1_DATA4 = _MXC_BUILD_GPIO_PIN(0, 15, 2, 0x298, 0x698),
- MX51_PIN_USBH1_DATA5 = _MXC_BUILD_GPIO_PIN(0, 16, 2, 0x29C, 0x69C),
- MX51_PIN_USBH1_DATA6 = _MXC_BUILD_GPIO_PIN(0, 17, 2, 0x2A0, 0x6A0),
- MX51_PIN_USBH1_DATA7 = _MXC_BUILD_GPIO_PIN(0, 18, 2, 0x2A4, 0x6A4),
- MX51_PIN_DI1_PIN11 = _MXC_BUILD_GPIO_PIN(2, 0, 4, 0x2A8, 0x6A8),
- MX51_PIN_DI1_PIN12 = _MXC_BUILD_GPIO_PIN(2, 1, 4, 0x2AC, 0x6AC),
- MX51_PIN_DI1_PIN13 = _MXC_BUILD_GPIO_PIN(2, 2, 4, 0x2B0, 0x6B0),
- MX51_PIN_DI1_D0_CS = _MXC_BUILD_GPIO_PIN(2, 3, 4, 0x2B4, 0x6B4),
- MX51_PIN_DI1_D1_CS = _MXC_BUILD_GPIO_PIN(2, 4, 4, 0x2B8, 0x6B8),
- MX51_PIN_DISPB2_SER_DIN = _MXC_BUILD_GPIO_PIN(2, 5, 4, 0x2BC, 0x6BC),
- MX51_PIN_DISPB2_SER_DIO = _MXC_BUILD_GPIO_PIN(2, 6, 4, 0x2C0, 0x6C0),
- MX51_PIN_DISPB2_SER_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 4, 0x2C4, 0x6C4),
- MX51_PIN_DISPB2_SER_RS = _MXC_BUILD_GPIO_PIN(2, 8, 4, 0x2C8, 0x6C8),
- MX51_PIN_DISP1_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x2CC, 0x6CC),
- MX51_PIN_DISP1_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x2D0, 0x6D0),
- MX51_PIN_DISP1_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x2D4, 0x6D4),
- MX51_PIN_DISP1_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x2D8, 0x6D8),
- MX51_PIN_DISP1_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x2DC, 0x6DC),
- MX51_PIN_DISP1_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x2E0, 0x6E0),
- MX51_PIN_DISP1_DAT6 = _MXC_BUILD_NON_GPIO_PIN(0x2E4, 0x6E4),
- MX51_PIN_DISP1_DAT7 = _MXC_BUILD_NON_GPIO_PIN(0x2E8, 0x6E8),
- MX51_PIN_DISP1_DAT8 = _MXC_BUILD_NON_GPIO_PIN(0x2EC, 0x6EC),
- MX51_PIN_DISP1_DAT9 = _MXC_BUILD_NON_GPIO_PIN(0x2F0, 0x6F0),
- MX51_PIN_DISP1_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x2F4, 0x6F4),
- MX51_PIN_DISP1_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x2F8, 0x6F8),
- MX51_PIN_DISP1_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x2FC, 0x6FC),
- MX51_PIN_DISP1_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x300, 0x700),
- MX51_PIN_DISP1_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x304, 0x704),
- MX51_PIN_DISP1_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x308, 0x708),
- MX51_PIN_DISP1_DAT16 = _MXC_BUILD_NON_GPIO_PIN(0x30C, 0x70C),
- MX51_PIN_DISP1_DAT17 = _MXC_BUILD_NON_GPIO_PIN(0x310, 0x710),
- MX51_PIN_DISP1_DAT18 = _MXC_BUILD_NON_GPIO_PIN(0x314, 0x714),
- MX51_PIN_DISP1_DAT19 = _MXC_BUILD_NON_GPIO_PIN(0x318, 0x718),
- MX51_PIN_DISP1_DAT20 = _MXC_BUILD_NON_GPIO_PIN(0x31C, 0x71C),
- MX51_PIN_DISP1_DAT21 = _MXC_BUILD_NON_GPIO_PIN(0x320, 0x720),
- MX51_PIN_DISP1_DAT22 = _MXC_BUILD_NON_GPIO_PIN(0x324, 0x724),
- MX51_PIN_DISP1_DAT23 = _MXC_BUILD_NON_GPIO_PIN(0x328, 0x728),
- MX51_PIN_DI1_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x32C, 0x72C),
- MX51_PIN_DI1_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x330, 0x734),
- MX51_PIN_DI_GP1 = _MXC_BUILD_NON_GPIO_PIN(0x334, 0x73C),
- MX51_PIN_DI_GP2 = _MXC_BUILD_NON_GPIO_PIN(0x338, 0x740),
- MX51_PIN_DI_GP3 = _MXC_BUILD_NON_GPIO_PIN(0x33C, 0x744),
- MX51_PIN_DI2_PIN4 = _MXC_BUILD_NON_GPIO_PIN(0x340, 0x748),
- MX51_PIN_DI2_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x344, 0x74C),
- MX51_PIN_DI2_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x348, 0x750),
- MX51_PIN_DI2_DISP_CLK = _MXC_BUILD_NON_GPIO_PIN(0x34C, 0x754),
- MX51_PIN_DI_GP4 = _MXC_BUILD_NON_GPIO_PIN(0x350, 0x758),
- MX51_PIN_DISP2_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x354, 0x75C),
- MX51_PIN_DISP2_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x358, 0x760),
- MX51_PIN_DISP2_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x35C, 0x764),
- MX51_PIN_DISP2_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x360, 0x768),
- MX51_PIN_DISP2_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x364, 0x76C),
- MX51_PIN_DISP2_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x368, 0x770),
- MX51_PIN_DISP2_DAT6 = _MXC_BUILD_GPIO_PIN(0, 19, 5, 0x36C, 0x774),
- MX51_PIN_DISP2_DAT7 = _MXC_BUILD_GPIO_PIN(0, 29, 5, 0x370, 0x778),
- MX51_PIN_DISP2_DAT8 = _MXC_BUILD_GPIO_PIN(0, 30, 5, 0x374, 0x77C),
- MX51_PIN_DISP2_DAT9 = _MXC_BUILD_GPIO_PIN(0, 31, 5, 0x378, 0x780),
- MX51_PIN_DISP2_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x37C, 0x784),
- MX51_PIN_DISP2_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x380, 0x788),
- MX51_PIN_DISP2_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x384, 0x78C),
- MX51_PIN_DISP2_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x388, 0x790),
- MX51_PIN_DISP2_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x38C, 0x794),
- MX51_PIN_DISP2_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x390, 0x798),
- MX51_PIN_SD1_CMD = _MXC_BUILD_NON_GPIO_PIN(0x394, 0x79C),
- MX51_PIN_SD1_CLK = _MXC_BUILD_NON_GPIO_PIN(0x398, 0x7A0),
- MX51_PIN_SD1_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x39C, 0x7A4),
- MX51_PIN_SD1_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3A0, 0x7A8),
- MX51_PIN_SD1_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3A4, 0x7AC),
- MX51_PIN_SD1_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3A8, 0x7B0),
- MX51_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x3AC, 0x7B4),
- MX51_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x3B0, 0x7B8),
- MX51_PIN_SD2_CMD = _MXC_BUILD_NON_GPIO_PIN(0x3B4, 0x7BC),
- MX51_PIN_SD2_CLK = _MXC_BUILD_NON_GPIO_PIN(0x3B8, 0x7C0),
- MX51_PIN_SD2_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x3BC, 0x7C4),
- MX51_PIN_SD2_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3C0, 0x7C8),
- MX51_PIN_SD2_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3C4, 0x7CC),
- MX51_PIN_SD2_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3C8, 0x7D0),
- MX51_PIN_GPIO1_2 = _MXC_BUILD_GPIO_PIN(0, 2, 0, 0x3CC, 0x7D4),
- MX51_PIN_GPIO1_3 = _MXC_BUILD_GPIO_PIN(0, 3, 0, 0x3D0, 0x7D8),
- MX51_PIN_PMIC_INT_REQ = _MXC_BUILD_NON_GPIO_PIN(0x3D4, 0x7FC),
- MX51_PIN_GPIO1_4 = _MXC_BUILD_GPIO_PIN(0, 4, 0, 0x3D8, 0x804),
- MX51_PIN_GPIO1_5 = _MXC_BUILD_GPIO_PIN(0, 5, 0, 0x3DC, 0x808),
- MX51_PIN_GPIO1_6 = _MXC_BUILD_GPIO_PIN(0, 6, 0, 0x3E0, 0x80C),
- MX51_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN(0, 7, 0, 0x3E4, 0x810),
- MX51_PIN_GPIO1_8 = _MXC_BUILD_GPIO_PIN(0, 8, 0, 0x3E8, 0x814),
- MX51_PIN_GPIO1_9 = _MXC_BUILD_GPIO_PIN(0, 9, 0, 0x3EC, 0x818),
-
- /* The following are PADS used for drive strength */
-
- MX51_PIN_CTL_GRP_DDRPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x820),
- MX51_PIN_CTL_GRP_PKEDDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x838),
- MX51_PIN_CTL_GRP_PKEADDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x890),
- MX51_PIN_CTL_GRP_DDRAPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x87C),
- MX51_PIN_CTL_GRP_DDRAPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x84C),
- MX51_PIN_CTL_GRP_DDRPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x884),
- MX51_PIN_CTL_GRP_HYSDDR0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x85C),
- MX51_PIN_CTL_GRP_HYSDDR1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x864),
- MX51_PIN_CTL_GRP_HYSDDR2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x86C),
- MX51_PIN_CTL_GRP_HYSDDR3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x874),
- MX51_PIN_CTL_GRP_DDR_SR_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x878),
- MX51_PIN_CTL_GRP_DDR_SR_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x880),
- MX51_PIN_CTL_GRP_DDR_SR_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x88C),
- MX51_PIN_CTL_GRP_DDR_SR_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x89C),
- MX51_PIN_CTL_GRP_DRAM_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A4),
- MX51_PIN_CTL_GRP_DRAM_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8AC),
- MX51_PIN_CTL_GRP_DRAM_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B8),
- MX51_PIN_CTL_GRP_DRAM_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x82C),
- MX51_PIN_CTL_GRP_INMODE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A0),
- MX51_PIN_CTL_GRP_DDR_SR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B0),
- MX51_PIN_CTL_GRP_EMI_DS5 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B4),
- MX51_PIN_CTL_GRP_DDR_SR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8BC),
- MX51_PIN_CTL_GRP_DDR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x83C),
- MX51_PIN_CTL_GRP_DDR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x848),
- MX51_PIN_CTL_GRP_DISP_PKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x868),
- MX51_PIN_CTL_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A4),
- MX51_PIN_CTL_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A8),
- MX51_PIN_CTL_DRAM_SDWE = _MXC_BUILD_NON_GPIO_PIN(0, 0x4Ac),
- MX51_PIN_CTL_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B0),
- MX51_PIN_CTL_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B4),
- MX51_PIN_CTL_DRAM_SDCLK = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B8),
- MX51_PIN_CTL_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4BC),
- MX51_PIN_CTL_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C0),
- MX51_PIN_CTL_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C4),
- MX51_PIN_CTL_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C8),
- MX51_PIN_CTL_DRAM_CS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4CC),
- MX51_PIN_CTL_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D0),
- MX51_PIN_CTL_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D4),
- MX51_PIN_CTL_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D8),
- MX51_PIN_CTL_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4DC),
- MX51_PIN_CTL_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4E0),
-};
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ASM_ARCH_MXC_MX51_PINS_H__ */
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _SYS_PROTO_H_
-#define _SYS_PROTO_H_
-
-u32 get_cpu_rev(void);
-#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
-void sdelay(unsigned long);
-
-#endif
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx51_pins.h>
+#include <asm/arch/mx5x_pins.h>
#include <asm/arch/iomux.h>
#include <asm/errno.h>
#include <asm/arch/sys_proto.h>
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx51_pins.h>
+#include <asm/arch/mx5x_pins.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux.h>
#include <mxc_gpio.h>
jadecpu arm arm926ejs jadecpu syteco mb86r0x
suen3 arm arm926ejs km_arm keymile kirkwood
rd6281a arm arm926ejs - Marvell kirkwood
-mx51evk arm armv7 mx51evk freescale mx51
-vision2 arm armv7 vision2 ttcontrol mx51
+mx51evk arm armv7 mx51evk freescale mx5
+vision2 arm armv7 vision2 ttcontrol mx5
actux1 arm ixp
actux2 arm ixp
actux3 arm ixp
#define CONFIG_MX51 /* in a mx51 */
#define CONFIG_SKIP_RELOCATE_UBOOT
-#define CONFIG_MX51_HCLK_FREQ 24000000 /* RedBoot says 26MHz */
-#define CONFIG_MX51_CLK32 32768
+#define CONFIG_SYS_MX5_HCLK 24000000
+#define CONFIG_SYS_MX5_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MX51 /* in a mx51 */
#define CONFIG_L2_OFF
-#define CONFIG_MX51_HCLK_FREQ 24000000
-#define CONFIG_MX51_CLK32 32768
+#define CONFIG_SYS_MX5_HCLK 24000000
+#define CONFIG_SYS_MX5_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
projects / u-boot / commitdiff