AT91: Makes AT91SAM9263 SoC build correctly against u-boot-atmel/master

Rework for AT91SAM9263 SoC, makes it build again.
Based on the work for AT91SAM9260-EK.

Signed-off-by: Hong Xu <hong.xu@atmel.com>
Signed-off-by: Reinhard Meyer <uboot@emk-elektronik.de>

diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
index 15e880accdd55eb55c8869e79be17ee3218de9dd..6eb0f305b7238d534657ce39fa125f4d5b397437 100644 (file)
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
@@ -28,17 +28,31 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pio.h>
+#include <asm/arch/gpio.h>
+
+/*
+ * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
+ * peripheral pins. Good to have if hardware is soldered optionally
+ * or in case of SPI no slave is selected. Avoid lines to float
+ * needlessly. Use a short local PUP define.
+ *
+ * Due to errata "TXD floats when CTS is inactive" pullups are always
+ * on for TXD pins.
+ */
+#ifdef CONFIG_AT91_GPIO_PULLUP
+# define PUP CONFIG_AT91_GPIO_PULLUP
+#else
+# define PUP 0
+#endif
 
 void at91_serial0_hw_init(void)
 {
        at91_pmc_t      *pmc    = (at91_pmc_t *) ATMEL_BASE_PMC;
 
        at91_set_a_periph(AT91_PIO_PORTA, 26, 1);               /* TXD0 */
-       at91_set_a_periph(AT91_PIO_PORTA, 27, 0);               /* RXD0 */
+       at91_set_a_periph(AT91_PIO_PORTA, 27, PUP);             /* RXD0 */
        writel(1 << ATMEL_ID_USART0, &pmc->pcer);
 }
 
@@ -47,7 +61,7 @@ void at91_serial1_hw_init(void)
        at91_pmc_t      *pmc    = (at91_pmc_t *) ATMEL_BASE_PMC;
 
        at91_set_a_periph(AT91_PIO_PORTD, 0, 1);                /* TXD1 */
-       at91_set_a_periph(AT91_PIO_PORTD, 1, 0);                /* RXD1 */
+       at91_set_a_periph(AT91_PIO_PORTD, 1, PUP);              /* RXD1 */
        writel(1 << ATMEL_ID_USART1, &pmc->pcer);
 }
 
@@ -56,7 +70,7 @@ void at91_serial2_hw_init(void)
        at91_pmc_t      *pmc    = (at91_pmc_t *) ATMEL_BASE_PMC;
 
        at91_set_a_periph(AT91_PIO_PORTD, 2, 1);                /* TXD2 */
-       at91_set_a_periph(AT91_PIO_PORTD, 3, 0);                /* RXD2 */
+       at91_set_a_periph(AT91_PIO_PORTD, 3, PUP);              /* RXD2 */
        writel(1 << ATMEL_ID_USART2, &pmc->pcer);
 }
 
@@ -64,7 +78,7 @@ void at91_seriald_hw_init(void)
 {
        at91_pmc_t      *pmc    = (at91_pmc_t *) ATMEL_BASE_PMC;
 
-       at91_set_a_periph(AT91_PIO_PORTC, 30, 0);               /* DRXD */
+       at91_set_a_periph(AT91_PIO_PORTC, 30, PUP);             /* DRXD */
        at91_set_a_periph(AT91_PIO_PORTC, 31, 1);               /* DTXD */
        writel(1 << ATMEL_ID_SYS, &pmc->pcer);
 }
@@ -74,9 +88,9 @@ void at91_spi0_hw_init(unsigned long cs_mask)
 {
        at91_pmc_t      *pmc    = (at91_pmc_t *) ATMEL_BASE_PMC;
 
-       at91_set_b_periph(AT91_PIO_PORTA, 0, 0);        /* SPI0_MISO */
-       at91_set_b_periph(AT91_PIO_PORTA, 1, 0);        /* SPI0_MOSI */
-       at91_set_b_periph(AT91_PIO_PORTA, 2, 0);        /* SPI0_SPCK */
+       at91_set_b_periph(AT91_PIO_PORTA, 0, PUP);      /* SPI0_MISO */
+       at91_set_b_periph(AT91_PIO_PORTA, 1, PUP);      /* SPI0_MOSI */
+       at91_set_b_periph(AT91_PIO_PORTA, 2, PUP);      /* SPI0_SPCK */
 
        /* Enable clock */
        writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
@@ -111,9 +125,9 @@ void at91_spi1_hw_init(unsigned long cs_mask)
 {
        at91_pmc_t      *pmc    = (at91_pmc_t *) ATMEL_BASE_PMC;
 
-       at91_set_a_periph(AT91_PIO_PORTB, 12, 0);       /* SPI1_MISO */
-       at91_set_a_periph(AT91_PIO_PORTB, 13, 0);       /* SPI1_MOSI */
-       at91_set_a_periph(AT91_PIO_PORTB, 14, 0);       /* SPI1_SPCK */
+       at91_set_a_periph(AT91_PIO_PORTB, 12, PUP);     /* SPI1_MISO */
+       at91_set_a_periph(AT91_PIO_PORTB, 13, PUP);     /* SPI1_MOSI */
+       at91_set_a_periph(AT91_PIO_PORTB, 14, PUP);     /* SPI1_SPCK */
 
        /* Enable clock */
        writel(1 << ATMEL_ID_SPI1, &pmc->pcer);

diff --git a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S b/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S
index 17ff0ddc25be74477dacb72b0f3a8e0cbd72e461..d102195273a8716520f51aad5d4c8ca6f66c385c 100644 (file)
--- a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S
+++ b/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S
@@ -35,7 +35,7 @@
 #include <asm/arch/at91sam9_sdramc.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_rstc.h>
-#ifdef CONFIG_AT91_LEGACY
+#ifdef CONFIG_ATMEL_LEGACY
 #include <asm/arch/at91sam9_matrix.h>
 #endif
 #ifndef CONFIG_SYS_MATRIX_EBICSA_VAL

diff --git a/arch/arm/include/asm/arch-at91/at91_spi.h b/arch/arm/include/asm/arch-at91/at91_spi.h
index c520e89d2b0c053216ee6fcd0d35f3a621d90097..afe724d02fa9175ed1934cd8c7bff558d1d33fd1 100644 (file)
--- a/arch/arm/include/asm/arch-at91/at91_spi.h
+++ b/arch/arm/include/asm/arch-at91/at91_spi.h
@@ -33,7 +33,7 @@ typedef struct at91_spi {
        at91_pdc_t      pdc;
 } at91_spi_t;
 
-#ifdef CONFIG_AT91_LEGACY
+#ifdef CONFIG_ATMEL_LEGACY
 
 #define AT91_SPI_CR                    0x00            /* Control Register */
 #define                AT91_SPI_SPIEN          (1 <<  0)               /* SPI Enable */

diff --git a/arch/arm/include/asm/arch-at91/at91sam9263.h b/arch/arm/include/asm/arch-at91/at91sam9263.h
index 2a1d6ee04c7e1fa1620a0b48278fbb886a1546ba..bf9ff7689d0313f15974faa4dca781fea48e410b 100644 (file)
--- a/arch/arm/include/asm/arch-at91/at91sam9263.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9263.h
@@ -124,11 +124,24 @@
 #define ATMEL_BASE_DMAC                0x00800000      /* DMA Controller */
 #define ATMEL_BASE_UHP         0x00a00000      /* USB Host controller */
 
+/*
+ * External memory
+ */
+#define ATMEL_BASE_CS0         0x10000000      /* typically NOR */
+#define ATMEL_BASE_CS1         0x20000000      /* SDRAM */
+#define ATMEL_BASE_CS2         0x30000000
+#define ATMEL_BASE_CS3         0x40000000      /* typically NAND */
+#define ATMEL_BASE_CS4         0x50000000
+#define ATMEL_BASE_CS5         0x60000000
+#define ATMEL_BASE_CS6         0x70000000
+#define ATMEL_BASE_CS7         0x80000000
+
 /*
  * Other misc defines
  */
 #define ATMEL_PIO_PORTS                5               /* this SoCs has 5 PIO */
 #define ATMEL_BASE_PIO         ATMEL_BASE_PIOA
+#define ATMEL_PMC_UHP          AT91SAM926x_PMC_UHP
 
 /*
  * Cpu Name

diff --git a/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h
index 83aaaab77319726e0a8f8e859021c32a08a4efa1..3f6709363c8adca161230d909f929733000a428c 100644 (file)
--- a/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h
@@ -15,115 +15,53 @@
 #ifndef AT91SAM9263_MATRIX_H
 #define AT91SAM9263_MATRIX_H
 
-#define AT91_MATRIX_MCFG0      (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1      (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2      (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3      (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4      (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5      (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
-#define AT91_MATRIX_MCFG6      (AT91_MATRIX + 0x18)    /* Master Configuration Register 6 */
-#define AT91_MATRIX_MCFG7      (AT91_MATRIX + 0x1C)    /* Master Configuration Register 7 */
-#define AT91_MATRIX_MCFG8      (AT91_MATRIX + 0x20)    /* Master Configuration Register 8 */
-#define                AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
-#define                        AT91_MATRIX_ULBT_INFINITE       (0 << 0)
-#define                        AT91_MATRIX_ULBT_SINGLE         (1 << 0)
-#define                        AT91_MATRIX_ULBT_FOUR           (2 << 0)
-#define                        AT91_MATRIX_ULBT_EIGHT          (3 << 0)
-#define                        AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
+#ifndef __ASSEMBLY__
 
-#define AT91_MATRIX_SCFG0      (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1      (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2      (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3      (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4      (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5      (AT91_MATRIX + 0x54)    /* Slave Configuration Register 5 */
-#define AT91_MATRIX_SCFG6      (AT91_MATRIX + 0x58)    /* Slave Configuration Register 6 */
-#define AT91_MATRIX_SCFG7      (AT91_MATRIX + 0x5C)    /* Slave Configuration Register 7 */
-#define                AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
-#define                AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
-#define                        AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
-#define                        AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
-#define                        AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
-#define                AT91_MATRIX_FIXED_DEFMSTR       (0xf  << 18)    /* Fixed Index of Default Master */
-#define                AT91_MATRIX_ARBT                (3    << 24)    /* Arbitration Type */
-#define                        AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
-#define                        AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
+/*
+ * This struct defines access to the matrix' maximum of
+ * 16 masters and 16 slaves.
+ * Note: not all masters/slaves are available
+ */
+struct at91_matrix {
+       u32     mcfg[16];       /* Master Configuration Registers */
+       u32     scfg[16];       /* Slave Configuration Registers */
+       u32     pras[16][2];    /* Priority Assignment Slave Registers */
+       u32     mrcr;           /* Master Remap Control Register */
+       u32     filler[0x06];
+       u32     ebicsa;         /* EBI Chip Select Assignment Register */
+};
+
+#endif /* __ASSEMBLY__ */
 
-#define AT91_MATRIX_PRAS0      (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRBS0      (AT91_MATRIX + 0x84)    /* Priority Register B for Slave 0 */
-#define AT91_MATRIX_PRAS1      (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRBS1      (AT91_MATRIX + 0x8C)    /* Priority Register B for Slave 1 */
-#define AT91_MATRIX_PRAS2      (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRBS2      (AT91_MATRIX + 0x94)    /* Priority Register B for Slave 2 */
-#define AT91_MATRIX_PRAS3      (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRBS3      (AT91_MATRIX + 0x9C)    /* Priority Register B for Slave 3 */
-#define AT91_MATRIX_PRAS4      (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRBS4      (AT91_MATRIX + 0xA4)    /* Priority Register B for Slave 4 */
-#define AT91_MATRIX_PRAS5      (AT91_MATRIX + 0xA8)    /* Priority Register A for Slave 5 */
-#define AT91_MATRIX_PRBS5      (AT91_MATRIX + 0xAC)    /* Priority Register B for Slave 5 */
-#define AT91_MATRIX_PRAS6      (AT91_MATRIX + 0xB0)    /* Priority Register A for Slave 6 */
-#define AT91_MATRIX_PRBS6      (AT91_MATRIX + 0xB4)    /* Priority Register B for Slave 6 */
-#define AT91_MATRIX_PRAS7      (AT91_MATRIX + 0xB8)    /* Priority Register A for Slave 7 */
-#define AT91_MATRIX_PRBS7      (AT91_MATRIX + 0xBC)    /* Priority Register B for Slave 7 */
-#define                AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
-#define                AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
-#define                AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
-#define                AT91_MATRIX_M3PR                (3 << 12)       /* Master 3 Priority */
-#define                AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
-#define                AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
-#define                AT91_MATRIX_M6PR                (3 << 24)       /* Master 6 Priority */
-#define                AT91_MATRIX_M7PR                (3 << 28)       /* Master 7 Priority */
-#define                AT91_MATRIX_M8PR                (3 << 0)        /* Master 8 Priority (in Register B) */
+#define AT91_MATRIX_ULBT_INFINITE      (0 << 0)
+#define AT91_MATRIX_ULBT_SINGLE                (1 << 0)
+#define AT91_MATRIX_ULBT_FOUR          (2 << 0)
+#define AT91_MATRIX_ULBT_EIGHT         (3 << 0)
+#define AT91_MATRIX_ULBT_SIXTEEN       (4 << 0)
 
-#define AT91_MATRIX_MRCR       (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
-#define                AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define                AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define                AT91_MATRIX_RCB2                (1 << 2)
-#define                AT91_MATRIX_RCB3                (1 << 3)
-#define                AT91_MATRIX_RCB4                (1 << 4)
-#define                AT91_MATRIX_RCB5                (1 << 5)
-#define                AT91_MATRIX_RCB6                (1 << 6)
-#define                AT91_MATRIX_RCB7                (1 << 7)
-#define                AT91_MATRIX_RCB8                (1 << 8)
+#define AT91_MATRIX_DEFMSTR_TYPE_NONE  (0 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_LAST  (1 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
+#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT        18
+#define AT91_MATRIX_ARBT_ROUND_ROBIN   (0 << 24)
+#define AT91_MATRIX_ARBT_FIXED_PRIORITY        (1 << 24)
 
-#define AT91_MATRIX_TCMR       (AT91_MATRIX + 0x114)   /* TCM Configuration Register */
-#define                AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
-#define                        AT91_MATRIX_ITCM_0              (0 << 0)
-#define                        AT91_MATRIX_ITCM_16             (5 << 0)
-#define                        AT91_MATRIX_ITCM_32             (6 << 0)
-#define                AT91_MATRIX_DTCM_SIZE           (0xf << 4)      /* Size of DTCM enabled memory block */
-#define                        AT91_MATRIX_DTCM_0              (0 << 4)
-#define                        AT91_MATRIX_DTCM_16             (5 << 4)
-#define                        AT91_MATRIX_DTCM_32             (6 << 4)
+#define AT91_MATRIX_M0PR_SHIFT         0
+#define AT91_MATRIX_M1PR_SHIFT         4
+#define AT91_MATRIX_M2PR_SHIFT         8
+#define AT91_MATRIX_M3PR_SHIFT         12
+#define AT91_MATRIX_M4PR_SHIFT         16
+#define AT91_MATRIX_M5PR_SHIFT         20
 
-#define AT91_MATRIX_EBI0CSA    (AT91_MATRIX + 0x120)   /* EBI0 Chip Select Assignment Register */
-#define                AT91_MATRIX_EBI0_CS1A           (1 << 1)        /* Chip Select 1 Assignment */
-#define                        AT91_MATRIX_EBI0_CS1A_SMC               (0 << 1)
-#define                        AT91_MATRIX_EBI0_CS1A_SDRAMC            (1 << 1)
-#define                AT91_MATRIX_EBI0_CS3A           (1 << 3)        /* Chip Select 3 Assignment */
-#define                        AT91_MATRIX_EBI0_CS3A_SMC               (0 << 3)
-#define                        AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA    (1 << 3)
-#define                AT91_MATRIX_EBI0_CS4A           (1 << 4)        /* Chip Select 4 Assignment */
-#define                        AT91_MATRIX_EBI0_CS4A_SMC               (0 << 4)
-#define                        AT91_MATRIX_EBI0_CS4A_SMC_CF1           (1 << 4)
-#define                AT91_MATRIX_EBI0_CS5A           (1 << 5)        /* Chip Select 5 Assignment */
-#define                        AT91_MATRIX_EBI0_CS5A_SMC               (0 << 5)
-#define                        AT91_MATRIX_EBI0_CS5A_SMC_CF2           (1 << 5)
-#define                AT91_MATRIX_EBI0_DBPUC          (1 << 8)        /* Data Bus Pull-up Configuration */
-#define                AT91_MATRIX_EBI0_VDDIOMSEL      (1 << 16)       /* Memory voltage selection */
-#define                        AT91_MATRIX_EBI0_VDDIOMSEL_1_8V         (0 << 16)
-#define                        AT91_MATRIX_EBI0_VDDIOMSEL_3_3V         (1 << 16)
+#define AT91_MATRIX_RCB0               (1 << 0)
+#define AT91_MATRIX_RCB1               (1 << 1)
 
-#define AT91_MATRIX_EBI1CSA    (AT91_MATRIX + 0x124)   /* EBI1 Chip Select Assignment Register */
-#define                AT91_MATRIX_EBI1_CS1A           (1 << 1)        /* Chip Select 1 Assignment */
-#define                        AT91_MATRIX_EBI1_CS1A_SMC               (0 << 1)
-#define                        AT91_MATRIX_EBI1_CS1A_SDRAMC            (1 << 1)
-#define                AT91_MATRIX_EBI1_CS2A           (1 << 3)        /* Chip Select 3 Assignment */
-#define                        AT91_MATRIX_EBI1_CS2A_SMC               (0 << 3)
-#define                        AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA    (1 << 3)
-#define                AT91_MATRIX_EBI1_DBPUC          (1 << 8)        /* Data Bus Pull-up Configuration */
-#define                AT91_MATRIX_EBI1_VDDIOMSEL      (1 << 16)       /* Memory voltage selection */
-#define                        AT91_MATRIX_EBI1_VDDIOMSEL_1_8V         (0 << 16)
-#define                        AT91_MATRIX_EBI1_VDDIOMSEL_3_3V         (1 << 16)
+#define AT91_MATRIX_CS1A_SDRAMC                (1 << 1)
+#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA        (1 << 3)
+#define AT91_MATRIX_CS4A_SMC_CF1       (1 << 4)
+#define AT91_MATRIX_CS5A_SMC_CF2       (1 << 5)
+#define AT91_MATRIX_DBPUC              (1 << 8)
+#define AT91_MATRIX_VDDIOMSEL_1_8V     (0 << 16)
+#define AT91_MATRIX_VDDIOMSEL_3_3V     (1 << 16)
 
 #endif